[people/ms/u-boot.git] / include / configs / vexpress_aemv8a.h

/*
 * Configuration for Versatile Express. Parts were derived from other ARM
 *   configurations.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
#define CONFIG_ARMV8_SWITCH_TO_EL1
#endif

#define CONFIG_REMAKE_ELF

#define CONFIG_SUPPORT_RAW_INITRD

/* Link Definitions */
#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
	defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#endif

#define CONFIG_SYS_BOOTM_LEN (64 << 20)      /* Increase max gunzip size */

/* CS register bases for the original memory map. */
#define V2M_PA_CS0			0x00000000
#define V2M_PA_CS1			0x14000000
#define V2M_PA_CS2			0x18000000
#define V2M_PA_CS3			0x1c000000
#define V2M_PA_CS4			0x0c000000
#define V2M_PA_CS5			0x10000000

#define V2M_PERIPH_OFFSET(x)		(x << 16)
#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))

#define V2M_BASE			0x80000000

/* Common peripherals relative to CS7. */
#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))

#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define V2M_UART0			0x7ff80000
#define V2M_UART1			0x7ff70000
#else /* Not Juno */
#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
#endif

#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))

#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))

#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))

#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))

#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))

/* System register offsets. */
#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */

/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
#define GICD_BASE			(0x2f000000)
#define GICR_BASE			(0x2f100000)
#else

#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
	defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
#define GICD_BASE			(0x2f000000)
#define GICC_BASE			(0x2c000000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE			(0x2C010000)
#define GICC_BASE			(0x2C02f000)
#endif
#endif /* !CONFIG_GICV3 */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))

#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111			1
#define CONFIG_SMC91111_BASE		(0x01A000000)
#endif

/* PL011 Serial Configuration */
#define CONFIG_CONS_INDEX		0
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK		7273800
#else
#define CONFIG_PL011_CLOCK		24000000
#endif

/*#define CONFIG_MENU_SHOW*/

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)

/* Physical Memory Map */
#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
/* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE		0x01000000
#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1

#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_NR_DRAM_BANKS		2
#define PHYS_SDRAM_2			(0x880000000)
#define PHYS_SDRAM_2_SIZE		0x180000000
#else
#define CONFIG_NR_DRAM_BANKS		1
#endif

/* Enable memtest */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)

/* Initial environment variables */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
/*
 * Defines where the kernel and FDT exist in NOR flash and where it will
 * be copied into DRAM
 */
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=norkern\0"	\
				"kernel_alt_name=Image\0"	\
				"kernel_addr=0x80080000\0" \
				"initrd_name=ramdisk.img\0"	\
				"initrd_addr=0x84000000\0"	\
				"fdtfile=board.dtb\0" \
				"fdt_alt_name=juno\0" \
				"fdt_addr=0x83000000\0" \
				"fdt_high=0xffffffffffffffff\0" \
				"initrd_high=0xffffffffffffffff\0" \

/* Copy the kernel and FDT to DRAM memory and boot */
#define CONFIG_BOOTCOMMAND	"afs load ${kernel_name} ${kernel_addr} ; " \
				"if test $? -eq 1; then "\
				"  echo Loading ${kernel_alt_name} instead of "\
				"${kernel_name}; "\
				"  afs load ${kernel_alt_name} ${kernel_addr};"\
				"fi ; "\
				"afs load  ${fdtfile} ${fdt_addr} ; " \
				"if test $? -eq 1; then "\
				"  echo Loading ${fdt_alt_name} instead of "\
				"${fdtfile}; "\
				"  afs load ${fdt_alt_name} ${fdt_addr}; "\
				"fi ; "\
				"fdt addr ${fdt_addr}; fdt resize; " \
				"if afs load  ${initrd_name} ${initrd_addr} ; "\
				"then "\
				"  setenv initrd_param ${initrd_addr}; "\
				"  else setenv initrd_param -; "\
				"fi ; " \
				"booti ${kernel_addr} ${initrd_param} ${fdt_addr}"


#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=Image\0"		\
				"kernel_addr=0x80080000\0"	\
				"initrd_name=ramdisk.img\0"	\
				"initrd_addr=0x88000000\0"	\
				"fdtfile=devtree.dtb\0"		\
				"fdt_addr=0x83000000\0"		\
				"fdt_high=0xffffffffffffffff\0"	\
				"initrd_high=0xffffffffffffffff\0"

#define CONFIG_BOOTCOMMAND	"smhload ${kernel_name} ${kernel_addr}; " \
				"smhload ${fdtfile} ${fdt_addr}; " \
				"smhload ${initrd_name} ${initrd_addr} "\
				"initrd_end; " \
				"fdt addr ${fdt_addr}; fdt resize; " \
				"fdt chosen ${initrd_addr} ${initrd_end}; " \
				"booti $kernel_addr - $fdt_addr"


#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_addr=0x80080000\0"	\
				"initrd_addr=0x84000000\0"	\
				"fdt_addr=0x83000000\0"		\
				"fdt_high=0xffffffffffffffff\0"	\
				"initrd_high=0xffffffffffffffff\0"

#define CONFIG_BOOTCOMMAND	"booti $kernel_addr $initrd_addr $fdt_addr"


#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_FLASH_BASE		0x08000000
/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
#define CONFIG_SYS_MAX_FLASH_SECT	259
/* Store environment at top of flash in the same location as blank.img */
/* in the Juno firmware. */
#define CONFIG_ENV_ADDR			0x0BFC0000
#define CONFIG_ENV_SECT_SIZE		0x00010000
#else
#define CONFIG_SYS_FLASH_BASE		0x0C000000
/* 256 x 256KiB sectors */
#define CONFIG_SYS_MAX_FLASH_SECT	256
/* Store environment at top of flash */
#define CONFIG_ENV_ADDR			0x0FFC0000
#define CONFIG_ENV_SECT_SIZE		0x00040000
#endif

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
#define FLASH_MAX_SECTOR_SIZE		0x00040000
#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE

#endif /* __VEXPRESS_AEMV8A_H */
Commit	Line	Data
12916829 DF	1	/*
	2	* Configuration for Versatile Express. Parts were derived from other ARM
	3	* configurations.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __VEXPRESS_AEMV8A_H
	9	#define __VEXPRESS_AEMV8A_H
	10
f91afc4d	11	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	12	#ifndef CONFIG_SEMIHOSTING
f91afc4d	13	#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
261d2760	14	#endif
261d2760 DR	15	#define CONFIG_ARMV8_SWITCH_TO_EL1
	16	#endif
	17
12916829 DF	18	#define CONFIG_REMAKE_ELF
12916829 DF	19
12916829 DF	20	#define CONFIG_SUPPORT_RAW_INITRD
12916829 DF	21
12916829	22	/* Link Definitions */
fc04b923 RH	23	#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) \|\| \
fc04b923 RH	24	defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
261d2760	25	/* ATF loads u-boot here for BASE_FVP model */
261d2760	26	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
ffc10373	27	#elif CONFIG_TARGET_VEXPRESS64_JUNO
ffc10373	28	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
261d2760	29	#endif
12916829	30
0d3012af RH	31	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
0d3012af RH	32
12916829 DF	33	/* CS register bases for the original memory map. */
	34	#define V2M_PA_CS0 0x00000000
	35	#define V2M_PA_CS1 0x14000000
	36	#define V2M_PA_CS2 0x18000000
	37	#define V2M_PA_CS3 0x1c000000
	38	#define V2M_PA_CS4 0x0c000000
	39	#define V2M_PA_CS5 0x10000000
	40
	41	#define V2M_PERIPH_OFFSET(x) (x << 16)
	42	#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
	43	#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
	44	#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
	45
	46	#define V2M_BASE 0x80000000
	47
12916829 DF	48	/* Common peripherals relative to CS7. */
	49	#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
	50	#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
	51	#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
	52	#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
	53
ffc10373 LW	54	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	55	#define V2M_UART0 0x7ff80000
	56	#define V2M_UART1 0x7ff70000
	57	#else /* Not Juno */
12916829 DF	58	#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
	59	#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
	60	#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
	61	#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
ffc10373	62	#endif
12916829 DF	63
	64	#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
	65
	66	#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
	67	#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
	68
	69	#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
	70	#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
	71
	72	#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
	73
	74	#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
	75
	76	/* System register offsets. */
	77	#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
	78	#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
	79	#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
	80
	81	/* Generic Timer Definitions */
	82	#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
	83
	84	/* Generic Interrupt Controller Definitions */
c71645ad DF	85	#ifdef CONFIG_GICV3
	86	#define GICD_BASE (0x2f000000)
	87	#define GICR_BASE (0x2f100000)
	88	#else
261d2760	89
fc04b923 RH	90	#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) \|\| \
fc04b923 RH	91	defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
261d2760 DR	92	#define GICD_BASE (0x2f000000)
261d2760 DR	93	#define GICC_BASE (0x2c000000)
ffc10373 LW	94	#elif CONFIG_TARGET_VEXPRESS64_JUNO
	95	#define GICD_BASE (0x2C010000)
	96	#define GICC_BASE (0x2C02f000)
261d2760	97	#endif
03314f0e	98	#endif /* !CONFIG_GICV3 */
12916829	99
12916829	100	/* Size of malloc() pool */
5bcae13e	101	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
12916829	102
8daec2d9	103	#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
b31f9d7a	104	/* The Vexpress64 simulators use SMSC91C111 */
3865ceb7 BS	105	#define CONFIG_SMC91111 1
3865ceb7 BS	106	#define CONFIG_SMC91111_BASE (0x01A000000)
b31f9d7a	107	#endif
12916829 DF	108
12916829 DF	109	/* PL011 Serial Configuration */
d8bafe13	110	#define CONFIG_CONS_INDEX 0
ffc10373 LW	111	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	112	#define CONFIG_PL011_CLOCK 7273800
	113	#else
12916829	114	#define CONFIG_PL011_CLOCK 24000000
ffc10373	115	#endif
12916829	116
12916829	117	/#define CONFIG_MENU_SHOW/
12916829 DF	118
	119	/* BOOTP options */
	120	#define CONFIG_BOOTP_BOOTFILESIZE
	121	#define CONFIG_BOOTP_BOOTPATH
	122	#define CONFIG_BOOTP_GATEWAY
	123	#define CONFIG_BOOTP_HOSTNAME
	124	#define CONFIG_BOOTP_PXE
12916829 DF	125
	126	/* Miscellaneous configurable options */
	127	#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
	128
	129	/* Physical Memory Map */
12916829	130	#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
30355708 LW	131	/* Top 16MB reserved for secure world use */
	132	#define DRAM_SEC_SIZE 0x01000000
	133	#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
	134	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	135
2c2b2183 RH	136	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	137	#define CONFIG_NR_DRAM_BANKS 2
	138	#define PHYS_SDRAM_2 (0x880000000)
	139	#define PHYS_SDRAM_2_SIZE 0x180000000
	140	#else
	141	#define CONFIG_NR_DRAM_BANKS 1
	142	#endif
	143
30355708	144	/* Enable memtest */
30355708 LW	145	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
30355708 LW	146	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
12916829 DF	147
12916829 DF	148	/* Initial environment variables */
10d1491b LW	149	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	150	/*
	151	* Defines where the kernel and FDT exist in NOR flash and where it will
	152	* be copied into DRAM
	153	*/
	154	#define CONFIG_EXTRA_ENV_SETTINGS \
ecbed5d6 RH	155	"kernel_name=norkern\0" \
ecbed5d6 RH	156	"kernel_alt_name=Image\0" \
7babe482	157	"kernel_addr=0x80080000\0" \
4a6bdb59 RH	158	"initrd_name=ramdisk.img\0" \
4a6bdb59 RH	159	"initrd_addr=0x84000000\0" \
da3e620d	160	"fdtfile=board.dtb\0" \
ecbed5d6	161	"fdt_alt_name=juno\0" \
10d1491b LW	162	"fdt_addr=0x83000000\0" \
	163	"fdt_high=0xffffffffffffffff\0" \
	164	"initrd_high=0xffffffffffffffff\0" \
	165
10d1491b LW	166	/* Copy the kernel and FDT to DRAM memory and boot */
10d1491b LW	167	#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
ecbed5d6 RH	168	"if test $? -eq 1; then "\
	169	" echo Loading ${kernel_alt_name} instead of "\
	170	"${kernel_name}; "\
	171	" afs load ${kernel_alt_name} ${kernel_addr};"\
	172	"fi ; "\
da3e620d	173	"afs load ${fdtfile} ${fdt_addr} ; " \
ecbed5d6 RH	174	"if test $? -eq 1; then "\
ecbed5d6 RH	175	" echo Loading ${fdt_alt_name} instead of "\
da3e620d	176	"${fdtfile}; "\
ecbed5d6 RH	177	" afs load ${fdt_alt_name} ${fdt_addr}; "\
ecbed5d6 RH	178	"fi ; "\
10d1491b	179	"fdt addr ${fdt_addr}; fdt resize; " \
4a6bdb59 RH	180	"if afs load ${initrd_name} ${initrd_addr} ; "\
	181	"then "\
	182	" setenv initrd_param ${initrd_addr}; "\
	183	" else setenv initrd_param -; "\
	184	"fi ; " \
	185	"booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
10d1491b	186
10d1491b LW	187
10d1491b LW	188	#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	189	#define CONFIG_EXTRA_ENV_SETTINGS \
1fd0f92e	190	"kernel_name=Image\0" \
7babe482	191	"kernel_addr=0x80080000\0" \
261d2760	192	"initrd_name=ramdisk.img\0" \
49995ffe	193	"initrd_addr=0x88000000\0" \
da3e620d	194	"fdtfile=devtree.dtb\0" \
49995ffe	195	"fdt_addr=0x83000000\0" \
261d2760 DR	196	"fdt_high=0xffffffffffffffff\0" \
	197	"initrd_high=0xffffffffffffffff\0"
	198
49995ffe	199	#define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \
da3e620d	200	"smhload ${fdtfile} ${fdt_addr}; " \
c0ae9703 RH	201	"smhload ${initrd_name} ${initrd_addr} "\
c0ae9703 RH	202	"initrd_end; " \
1fd0f92e LW	203	"fdt addr ${fdt_addr}; fdt resize; " \
	204	"fdt chosen ${initrd_addr} ${initrd_end}; " \
	205	"booti $kernel_addr - $fdt_addr"
261d2760	206
261d2760	207
fc04b923 RH	208	#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
	209	#define CONFIG_EXTRA_ENV_SETTINGS \
	210	"kernel_addr=0x80080000\0" \
	211	"initrd_addr=0x84000000\0" \
	212	"fdt_addr=0x83000000\0" \
	213	"fdt_high=0xffffffffffffffff\0" \
	214	"initrd_high=0xffffffffffffffff\0"
	215
fc04b923 RH	216	#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr"
fc04b923 RH	217
fc04b923	218
261d2760	219	#endif
12916829	220
12916829 DF	221	/* Monitor Command Prompt */
12916829 DF	222	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
12916829	223	#define CONFIG_SYS_LONGHELP
5bcae13e	224	#define CONFIG_CMDLINE_EDITING
12916829 DF	225	#define CONFIG_SYS_MAXARGS 64 /* max command args */
12916829 DF	226
f3c71c93 RH	227	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	228	#define CONFIG_SYS_FLASH_BASE 0x08000000
	229	/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
	230	#define CONFIG_SYS_MAX_FLASH_SECT 259
	231	/* Store environment at top of flash in the same location as blank.img */
	232	/* in the Juno firmware. */
	233	#define CONFIG_ENV_ADDR 0x0BFC0000
	234	#define CONFIG_ENV_SECT_SIZE 0x00010000
14f264e6	235	#else
f3c71c93 RH	236	#define CONFIG_SYS_FLASH_BASE 0x0C000000
	237	/* 256 x 256KiB sectors */
	238	#define CONFIG_SYS_MAX_FLASH_SECT 256
	239	/* Store environment at top of flash */
	240	#define CONFIG_ENV_ADDR 0x0FFC0000
	241	#define CONFIG_ENV_SECT_SIZE 0x00040000
	242	#endif
	243
14f264e6 LW	244	#define CONFIG_SYS_FLASH_CFI 1
14f264e6 LW	245	#define CONFIG_FLASH_CFI_DRIVER 1
f19f389f	246	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
f3c71c93	247	#define CONFIG_SYS_MAX_FLASH_BANKS 1
14f264e6	248
14f264e6 LW	249	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
	250	#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
	251	#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
f3c71c93 RH	252	#define FLASH_MAX_SECTOR_SIZE 0x00040000
f3c71c93 RH	253	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
14f264e6	254
12916829	255	#endif /* __VEXPRESS_AEMV8A_H */