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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
1d506c26 | 3 | Copyright (C) 2003-2024 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
5af923b0 | 20 | #include "arch-utils.h" |
386c036b | 21 | #include "dis-asm.h" |
b41c5a85 | 22 | #include "dwarf2.h" |
82ca8957 | 23 | #include "dwarf2/frame.h" |
ec452525 | 24 | #include "extract-store-integer.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c | 35 | #include "target.h" |
3f7b46f2 | 36 | #include "target-descriptions.h" |
c906108c | 37 | #include "value.h" |
c906108c | 38 | |
386c036b | 39 | #include "sparc-tdep.h" |
e6f9c00b | 40 | #include "sparc-ravenscar-thread.h" |
325fac50 | 41 | #include <algorithm> |
c906108c | 42 | |
a54124c5 MK |
43 | struct regset; |
44 | ||
9eb42ed1 MK |
45 | /* This file implements the SPARC 32-bit ABI as defined by the section |
46 | "Low-Level System Information" of the SPARC Compliance Definition | |
47 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 48 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 49 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
50 | |
51 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
52 | BSD-based, which is sometimes (retroactively?) referred to as | |
53 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
54 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
55 | suffering from severe version number inflation). Solaris 2.x is | |
56 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
57 | 2.x is SVR4-based. */ | |
58 | ||
59 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
60 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
61 | code that can handle both. The 64-bit specific code lives in | |
62 | sparc64-tdep.c; don't add any here. */ | |
63 | ||
386c036b MK |
64 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 |
65 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
66 | hosts, so undefine it first. */ | |
67 | #undef BIAS | |
68 | #define BIAS 2047 | |
69 | ||
70 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
71 | #define X_OP(i) (((i) >> 30) & 0x3) |
72 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
73 | #define X_A(i) (((i) >> 29) & 1) | |
74 | #define X_COND(i) (((i) >> 25) & 0xf) | |
75 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
76 | #define X_IMM22(i) ((i) & 0x3fffff) | |
77 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 78 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 79 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 80 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 81 | /* Sign extension macros. */ |
c906108c | 82 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 83 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 84 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 85 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
86 | /* Macros to identify some instructions. */ |
87 | /* RETURN (RETT in V8) */ | |
88 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 89 | |
386c036b MK |
90 | /* Fetch the instruction at PC. Instructions are always big-endian |
91 | even if the processor operates in little-endian mode. */ | |
92 | ||
93 | unsigned long | |
94 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 95 | { |
e1613aba | 96 | gdb_byte buf[4]; |
386c036b MK |
97 | unsigned long insn; |
98 | int i; | |
99 | ||
690668cc | 100 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 101 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 102 | return 0; |
c906108c | 103 | |
386c036b MK |
104 | insn = 0; |
105 | for (i = 0; i < sizeof (buf); i++) | |
106 | insn = (insn << 8) | buf[i]; | |
107 | return insn; | |
108 | } | |
42cdca6c MK |
109 | \f |
110 | ||
5465445a JB |
111 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
112 | instruction. */ | |
113 | ||
114 | static int | |
115 | sparc_is_unimp_insn (CORE_ADDR pc) | |
116 | { | |
117 | const unsigned long insn = sparc_fetch_instruction (pc); | |
118 | ||
119 | return ((insn & 0xc1c00000) == 0); | |
120 | } | |
121 | ||
d0b5971a JM |
122 | /* Return non-zero if the instruction corresponding to PC is an |
123 | "annulled" branch, i.e. the annul bit is set. */ | |
124 | ||
125 | int | |
126 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
127 | { | |
128 | /* The branch instructions featuring an annul bit can be identified | |
129 | by the following bit patterns: | |
130 | ||
131 | OP=0 | |
132 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
133 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
134 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
135 | OP2=6: Branch on FP Condition Codes (FBcc). | |
136 | OP2=3 && Bit28=0: | |
dda83cd7 | 137 | Branch on Integer Register with Prediction (BPr). |
d0b5971a JM |
138 | |
139 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
140 | coprocessor branch instructions (Op2=7). */ | |
141 | ||
142 | const unsigned long insn = sparc_fetch_instruction (pc); | |
143 | const unsigned op2 = X_OP2 (insn); | |
144 | ||
145 | if ((X_OP (insn) == 0) | |
146 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
147 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
148 | return X_A (insn); | |
149 | else | |
150 | return 0; | |
151 | } | |
152 | ||
42cdca6c MK |
153 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
154 | website http://stackghost.cerias.purdue.edu "... transparently and | |
155 | automatically protects applications' stack frames; more | |
156 | specifically, it guards the return pointers. The protection | |
157 | mechanisms require no application source or binary modification and | |
158 | imposes only a negligible performance penalty." | |
159 | ||
160 | The same website provides the following description of how | |
161 | StackGhost works: | |
162 | ||
163 | "StackGhost interfaces with the kernel trap handler that would | |
164 | normally write out registers to the stack and the handler that | |
165 | would read them back in. By XORing a cookie into the | |
166 | return-address saved in the user stack when it is actually written | |
167 | to the stack, and then XOR it out when the return-address is pulled | |
168 | from the stack, StackGhost can cause attacker corrupted return | |
169 | pointers to behave in a manner the attacker cannot predict. | |
170 | StackGhost can also use several unused bits in the return pointer | |
171 | to detect a smashed return pointer and abort the process." | |
172 | ||
173 | For GDB this means that whenever we're reading %i7 from a stack | |
174 | frame's window save area, we'll have to XOR the cookie. | |
175 | ||
176 | More information on StackGuard can be found on in: | |
177 | ||
c378eb4e | 178 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
179 | Stack Protection." 2001. Published in USENIX Security Symposium |
180 | '01. */ | |
181 | ||
182 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
183 | ||
184 | ULONGEST | |
e17a4113 | 185 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 186 | { |
e17a4113 | 187 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
328d42d8 | 188 | struct target_ops *ops = current_inferior ()->top_target (); |
e1613aba | 189 | gdb_byte buf[8]; |
baf92889 MK |
190 | int len; |
191 | ||
13547ab6 | 192 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
193 | if (len == -1) |
194 | return 0; | |
42cdca6c | 195 | |
baf92889 MK |
196 | /* We should have either an 32-bit or an 64-bit cookie. */ |
197 | gdb_assert (len == 4 || len == 8); | |
198 | ||
e17a4113 | 199 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 200 | } |
386c036b | 201 | \f |
baf92889 | 202 | |
386c036b MK |
203 | /* The functions on this page are intended to be used to classify |
204 | function arguments. */ | |
c906108c | 205 | |
386c036b | 206 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 207 | |
386c036b MK |
208 | static int |
209 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 210 | { |
df86565b | 211 | int len = type->length (); |
80ad1639 | 212 | |
78134374 | 213 | switch (type->code ()) |
c906108c | 214 | { |
386c036b MK |
215 | case TYPE_CODE_INT: |
216 | case TYPE_CODE_BOOL: | |
217 | case TYPE_CODE_CHAR: | |
218 | case TYPE_CODE_ENUM: | |
219 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
220 | /* We have byte, half-word, word and extended-word/doubleword |
221 | integral types. The doubleword is an extension to the | |
222 | original 32-bit ABI by the SCD 2.4.x. */ | |
223 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
224 | case TYPE_CODE_PTR: |
225 | case TYPE_CODE_REF: | |
aa006118 | 226 | case TYPE_CODE_RVALUE_REF: |
80ad1639 MK |
227 | /* Allow either 32-bit or 64-bit pointers. */ |
228 | return (len == 4 || len == 8); | |
386c036b MK |
229 | default: |
230 | break; | |
231 | } | |
c906108c | 232 | |
386c036b MK |
233 | return 0; |
234 | } | |
c906108c | 235 | |
386c036b | 236 | /* Check whether TYPE is "Floating". */ |
c906108c | 237 | |
386c036b MK |
238 | static int |
239 | sparc_floating_p (const struct type *type) | |
240 | { | |
78134374 | 241 | switch (type->code ()) |
c906108c | 242 | { |
386c036b MK |
243 | case TYPE_CODE_FLT: |
244 | { | |
df86565b | 245 | int len = type->length (); |
386c036b MK |
246 | return (len == 4 || len == 8 || len == 16); |
247 | } | |
248 | default: | |
249 | break; | |
250 | } | |
251 | ||
252 | return 0; | |
253 | } | |
c906108c | 254 | |
fe10a582 DM |
255 | /* Check whether TYPE is "Complex Floating". */ |
256 | ||
257 | static int | |
258 | sparc_complex_floating_p (const struct type *type) | |
259 | { | |
78134374 | 260 | switch (type->code ()) |
fe10a582 DM |
261 | { |
262 | case TYPE_CODE_COMPLEX: | |
263 | { | |
df86565b | 264 | int len = type->length (); |
fe10a582 DM |
265 | return (len == 8 || len == 16 || len == 32); |
266 | } | |
267 | default: | |
268 | break; | |
269 | } | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
0497f5b0 JB |
274 | /* Check whether TYPE is "Structure or Union". |
275 | ||
276 | In terms of Ada subprogram calls, arrays are treated the same as | |
277 | struct and union types. So this function also returns non-zero | |
278 | for array types. */ | |
c906108c | 279 | |
386c036b MK |
280 | static int |
281 | sparc_structure_or_union_p (const struct type *type) | |
282 | { | |
78134374 | 283 | switch (type->code ()) |
386c036b MK |
284 | { |
285 | case TYPE_CODE_STRUCT: | |
286 | case TYPE_CODE_UNION: | |
0497f5b0 | 287 | case TYPE_CODE_ARRAY: |
386c036b MK |
288 | return 1; |
289 | default: | |
290 | break; | |
c906108c | 291 | } |
386c036b MK |
292 | |
293 | return 0; | |
c906108c | 294 | } |
386c036b | 295 | |
05bc7456 JB |
296 | /* Return true if TYPE is returned by memory, false if returned by |
297 | register. */ | |
1933fd8e VM |
298 | |
299 | static bool | |
300 | sparc_structure_return_p (const struct type *type) | |
301 | { | |
bd63c870 | 302 | if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) |
1933fd8e | 303 | { |
05bc7456 | 304 | /* Float vectors are always returned by memory. */ |
27710edb | 305 | if (sparc_floating_p (check_typedef (type->target_type ()))) |
05bc7456 JB |
306 | return true; |
307 | /* Integer vectors are returned by memory if the vector size | |
308 | is greater than 8 bytes long. */ | |
df86565b | 309 | return (type->length () > 8); |
05bc7456 | 310 | } |
1933fd8e | 311 | |
05bc7456 JB |
312 | if (sparc_floating_p (type)) |
313 | { | |
314 | /* Floating point types are passed by register for size 4 and | |
315 | 8 bytes, and by memory for size 16 bytes. */ | |
df86565b | 316 | return (type->length () == 16); |
1933fd8e | 317 | } |
05bc7456 JB |
318 | |
319 | /* Other than that, only aggregates of all sizes get returned by | |
320 | memory. */ | |
1933fd8e VM |
321 | return sparc_structure_or_union_p (type); |
322 | } | |
323 | ||
05bc7456 JB |
324 | /* Return true if arguments of the given TYPE are passed by |
325 | memory; false if returned by register. */ | |
1933fd8e VM |
326 | |
327 | static bool | |
05bc7456 | 328 | sparc_arg_by_memory_p (const struct type *type) |
1933fd8e | 329 | { |
bd63c870 | 330 | if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) |
1933fd8e | 331 | { |
05bc7456 | 332 | /* Float vectors are always passed by memory. */ |
27710edb | 333 | if (sparc_floating_p (check_typedef (type->target_type ()))) |
05bc7456 JB |
334 | return true; |
335 | /* Integer vectors are passed by memory if the vector size | |
336 | is greater than 8 bytes long. */ | |
df86565b | 337 | return (type->length () > 8); |
1933fd8e | 338 | } |
05bc7456 JB |
339 | |
340 | /* Floats are passed by register for size 4 and 8 bytes, and by memory | |
341 | for size 16 bytes. */ | |
342 | if (sparc_floating_p (type)) | |
df86565b | 343 | return (type->length () == 16); |
05bc7456 JB |
344 | |
345 | /* Complex floats and aggregates of all sizes are passed by memory. */ | |
346 | if (sparc_complex_floating_p (type) || sparc_structure_or_union_p (type)) | |
347 | return true; | |
348 | ||
349 | /* Everything else gets passed by register. */ | |
350 | return false; | |
1933fd8e VM |
351 | } |
352 | ||
386c036b | 353 | /* Register information. */ |
7a36499a IR |
354 | #define SPARC32_FPU_REGISTERS \ |
355 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
356 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
357 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
358 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
359 | #define SPARC32_CP0_REGISTERS \ | |
360 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
386c036b | 361 | |
27087b7f TT |
362 | static const char * const sparc_core_register_names[] = { |
363 | SPARC_CORE_REGISTERS | |
364 | }; | |
365 | static const char * const sparc32_fpu_register_names[] = { | |
366 | SPARC32_FPU_REGISTERS | |
367 | }; | |
368 | static const char * const sparc32_cp0_register_names[] = { | |
369 | SPARC32_CP0_REGISTERS | |
370 | }; | |
3f7b46f2 | 371 | |
27087b7f | 372 | static const char * const sparc32_register_names[] = |
5af923b0 | 373 | { |
7a36499a IR |
374 | SPARC_CORE_REGISTERS, |
375 | SPARC32_FPU_REGISTERS, | |
376 | SPARC32_CP0_REGISTERS | |
5af923b0 MS |
377 | }; |
378 | ||
386c036b MK |
379 | /* Total number of registers. */ |
380 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 381 | |
386c036b MK |
382 | /* We provide the aliases %d0..%d30 for the floating registers as |
383 | "psuedo" registers. */ | |
384 | ||
27087b7f | 385 | static const char * const sparc32_pseudo_register_names[] = |
386c036b MK |
386 | { |
387 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
388 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
389 | }; | |
390 | ||
391 | /* Total number of pseudo registers. */ | |
392 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
393 | ||
7a36499a IR |
394 | /* Return the name of pseudo register REGNUM. */ |
395 | ||
396 | static const char * | |
397 | sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
398 | { | |
399 | regnum -= gdbarch_num_regs (gdbarch); | |
400 | ||
9b9e61c7 AB |
401 | gdb_assert (regnum < SPARC32_NUM_PSEUDO_REGS); |
402 | return sparc32_pseudo_register_names[regnum]; | |
7a36499a IR |
403 | } |
404 | ||
386c036b MK |
405 | /* Return the name of register REGNUM. */ |
406 | ||
407 | static const char * | |
d93859e2 | 408 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b | 409 | { |
3f7b46f2 IR |
410 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
411 | return tdesc_register_name (gdbarch, regnum); | |
412 | ||
7a36499a | 413 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
386c036b MK |
414 | return sparc32_register_names[regnum]; |
415 | ||
7a36499a | 416 | return sparc32_pseudo_register_name (gdbarch, regnum); |
386c036b | 417 | } |
2d457077 | 418 | \f |
209bd28e | 419 | /* Construct types for ISA-specific registers. */ |
2d457077 | 420 | |
209bd28e UW |
421 | static struct type * |
422 | sparc_psr_type (struct gdbarch *gdbarch) | |
423 | { | |
08106042 | 424 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); |
2d457077 | 425 | |
209bd28e UW |
426 | if (!tdep->sparc_psr_type) |
427 | { | |
428 | struct type *type; | |
2d457077 | 429 | |
77b7c781 | 430 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32); |
209bd28e UW |
431 | append_flags_type_flag (type, 5, "ET"); |
432 | append_flags_type_flag (type, 6, "PS"); | |
433 | append_flags_type_flag (type, 7, "S"); | |
434 | append_flags_type_flag (type, 12, "EF"); | |
435 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 436 | |
209bd28e UW |
437 | tdep->sparc_psr_type = type; |
438 | } | |
439 | ||
440 | return tdep->sparc_psr_type; | |
441 | } | |
442 | ||
443 | static struct type * | |
444 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 445 | { |
08106042 | 446 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); |
209bd28e UW |
447 | |
448 | if (!tdep->sparc_fsr_type) | |
449 | { | |
450 | struct type *type; | |
451 | ||
77b7c781 | 452 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32); |
209bd28e UW |
453 | append_flags_type_flag (type, 0, "NXA"); |
454 | append_flags_type_flag (type, 1, "DZA"); | |
455 | append_flags_type_flag (type, 2, "UFA"); | |
456 | append_flags_type_flag (type, 3, "OFA"); | |
457 | append_flags_type_flag (type, 4, "NVA"); | |
458 | append_flags_type_flag (type, 5, "NXC"); | |
459 | append_flags_type_flag (type, 6, "DZC"); | |
460 | append_flags_type_flag (type, 7, "UFC"); | |
461 | append_flags_type_flag (type, 8, "OFC"); | |
462 | append_flags_type_flag (type, 9, "NVC"); | |
463 | append_flags_type_flag (type, 22, "NS"); | |
464 | append_flags_type_flag (type, 23, "NXM"); | |
465 | append_flags_type_flag (type, 24, "DZM"); | |
466 | append_flags_type_flag (type, 25, "UFM"); | |
467 | append_flags_type_flag (type, 26, "OFM"); | |
468 | append_flags_type_flag (type, 27, "NVM"); | |
469 | ||
470 | tdep->sparc_fsr_type = type; | |
471 | } | |
472 | ||
473 | return tdep->sparc_fsr_type; | |
2d457077 | 474 | } |
386c036b | 475 | |
7a36499a IR |
476 | /* Return the GDB type object for the "standard" data type of data in |
477 | pseudo register REGNUM. */ | |
478 | ||
479 | static struct type * | |
480 | sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
481 | { | |
482 | regnum -= gdbarch_num_regs (gdbarch); | |
483 | ||
484 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
485 | return builtin_type (gdbarch)->builtin_double; | |
486 | ||
f34652de | 487 | internal_error (_("sparc32_pseudo_register_type: bad register number %d"), |
dda83cd7 | 488 | regnum); |
7a36499a IR |
489 | } |
490 | ||
386c036b | 491 | /* Return the GDB type object for the "standard" data type of data in |
c378eb4e | 492 | register REGNUM. */ |
386c036b MK |
493 | |
494 | static struct type * | |
495 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
496 | { | |
3f7b46f2 IR |
497 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
498 | return tdesc_register_type (gdbarch, regnum); | |
499 | ||
386c036b | 500 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) |
0dfff4cb | 501 | return builtin_type (gdbarch)->builtin_float; |
386c036b | 502 | |
386c036b | 503 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) |
0dfff4cb | 504 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
505 | |
506 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 507 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 508 | |
2d457077 | 509 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 510 | return sparc_psr_type (gdbarch); |
2d457077 MK |
511 | |
512 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 513 | return sparc_fsr_type (gdbarch); |
2d457077 | 514 | |
7a36499a IR |
515 | if (regnum >= gdbarch_num_regs (gdbarch)) |
516 | return sparc32_pseudo_register_type (gdbarch, regnum); | |
517 | ||
df4df182 | 518 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
519 | } |
520 | ||
05d1431c | 521 | static enum register_status |
386c036b | 522 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 523 | readable_regcache *regcache, |
e1613aba | 524 | int regnum, gdb_byte *buf) |
386c036b | 525 | { |
05d1431c PA |
526 | enum register_status status; |
527 | ||
7a36499a | 528 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
529 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
530 | ||
531 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
03f50fc8 | 532 | status = regcache->raw_read (regnum, buf); |
05d1431c | 533 | if (status == REG_VALID) |
03f50fc8 | 534 | status = regcache->raw_read (regnum + 1, buf + 4); |
05d1431c | 535 | return status; |
386c036b MK |
536 | } |
537 | ||
538 | static void | |
539 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
540 | struct regcache *regcache, | |
e1613aba | 541 | int regnum, const gdb_byte *buf) |
386c036b | 542 | { |
7a36499a | 543 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
544 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
545 | ||
546 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
10eaee5f SM |
547 | regcache->raw_write (regnum, buf); |
548 | regcache->raw_write (regnum + 1, buf + 4); | |
386c036b MK |
549 | } |
550 | \f | |
c9cf6e20 | 551 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
961842b2 JM |
552 | |
553 | int | |
c9cf6e20 | 554 | sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
961842b2 JM |
555 | { |
556 | /* This function must return true if we are one instruction after an | |
557 | instruction that destroyed the stack frame of the current | |
558 | function. The SPARC instructions used to restore the callers | |
559 | stack frame are RESTORE and RETURN/RETT. | |
560 | ||
561 | Of these RETURN/RETT is a branch instruction and thus we return | |
562 | true if we are in its delay slot. | |
563 | ||
564 | RESTORE is almost always found in the delay slot of a branch | |
565 | instruction that transfers control to the caller, such as JMPL. | |
566 | Thus the next instruction is in the caller frame and we don't | |
567 | need to do anything about it. */ | |
568 | ||
569 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
570 | ||
571 | return X_RETTURN (insn); | |
572 | } | |
573 | \f | |
386c036b | 574 | |
49a45ecf JB |
575 | static CORE_ADDR |
576 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
577 | { | |
578 | /* The ABI requires double-word alignment. */ | |
579 | return address & ~0x7; | |
580 | } | |
581 | ||
386c036b MK |
582 | static CORE_ADDR |
583 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 584 | CORE_ADDR funcaddr, |
386c036b MK |
585 | struct value **args, int nargs, |
586 | struct type *value_type, | |
e4fd649a UW |
587 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
588 | struct regcache *regcache) | |
c906108c | 589 | { |
e17a4113 UW |
590 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
591 | ||
386c036b MK |
592 | *bp_addr = sp - 4; |
593 | *real_pc = funcaddr; | |
594 | ||
d80b854b | 595 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 596 | { |
e1613aba | 597 | gdb_byte buf[4]; |
386c036b MK |
598 | |
599 | /* This is an UNIMP instruction. */ | |
e17a4113 | 600 | store_unsigned_integer (buf, 4, byte_order, |
df86565b | 601 | value_type->length () & 0x1fff); |
386c036b MK |
602 | write_memory (sp - 8, buf, 4); |
603 | return sp - 8; | |
c906108c SS |
604 | } |
605 | ||
386c036b MK |
606 | return sp - 4; |
607 | } | |
608 | ||
609 | static CORE_ADDR | |
610 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
611 | struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
612 | function_call_return_method return_method, |
613 | CORE_ADDR struct_addr) | |
386c036b | 614 | { |
ac7936df | 615 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 616 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
617 | /* Number of words in the "parameter array". */ |
618 | int num_elements = 0; | |
619 | int element = 0; | |
620 | int i; | |
621 | ||
622 | for (i = 0; i < nargs; i++) | |
c906108c | 623 | { |
d0c97917 | 624 | struct type *type = args[i]->type (); |
df86565b | 625 | int len = type->length (); |
386c036b | 626 | |
05bc7456 | 627 | if (sparc_arg_by_memory_p (type)) |
c906108c | 628 | { |
386c036b MK |
629 | /* Structure, Union and Quad-Precision Arguments. */ |
630 | sp -= len; | |
631 | ||
632 | /* Use doubleword alignment for these values. That's always | |
dda83cd7 | 633 | correct, and wasting a few bytes shouldn't be a problem. */ |
386c036b MK |
634 | sp &= ~0x7; |
635 | ||
efaf1ae0 | 636 | write_memory (sp, args[i]->contents ().data (), len); |
386c036b MK |
637 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
638 | num_elements++; | |
639 | } | |
640 | else if (sparc_floating_p (type)) | |
641 | { | |
642 | /* Floating arguments. */ | |
643 | gdb_assert (len == 4 || len == 8); | |
644 | num_elements += (len / 4); | |
c906108c | 645 | } |
c5aa993b JM |
646 | else |
647 | { | |
05bc7456 | 648 | /* Arguments passed via the General Purpose Registers. */ |
386c036b | 649 | num_elements += ((len + 3) / 4); |
c5aa993b | 650 | } |
c906108c | 651 | } |
c906108c | 652 | |
386c036b | 653 | /* Always allocate at least six words. */ |
325fac50 | 654 | sp -= std::max (6, num_elements) * 4; |
c906108c | 655 | |
386c036b MK |
656 | /* The psABI says that "Software convention requires space for the |
657 | struct/union return value pointer, even if the word is unused." */ | |
658 | sp -= 4; | |
c906108c | 659 | |
386c036b MK |
660 | /* The psABI says that "Although software convention and the |
661 | operating system require every stack frame to be doubleword | |
662 | aligned." */ | |
663 | sp &= ~0x7; | |
c906108c | 664 | |
386c036b | 665 | for (i = 0; i < nargs; i++) |
c906108c | 666 | { |
efaf1ae0 | 667 | const bfd_byte *valbuf = args[i]->contents ().data (); |
d0c97917 | 668 | struct type *type = args[i]->type (); |
df86565b | 669 | int len = type->length (); |
1933fd8e VM |
670 | gdb_byte buf[4]; |
671 | ||
672 | if (len < 4) | |
dda83cd7 SM |
673 | { |
674 | memset (buf, 0, 4 - len); | |
675 | memcpy (buf + 4 - len, valbuf, len); | |
676 | valbuf = buf; | |
677 | len = 4; | |
678 | } | |
c906108c | 679 | |
386c036b | 680 | gdb_assert (len == 4 || len == 8); |
c906108c | 681 | |
386c036b MK |
682 | if (element < 6) |
683 | { | |
684 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 685 | |
b66f5587 | 686 | regcache->cooked_write (regnum, valbuf); |
386c036b | 687 | if (len > 4 && element < 5) |
b66f5587 | 688 | regcache->cooked_write (regnum + 1, valbuf + 4); |
386c036b | 689 | } |
5af923b0 | 690 | |
386c036b MK |
691 | /* Always store the argument in memory. */ |
692 | write_memory (sp + 4 + element * 4, valbuf, len); | |
693 | element += len / 4; | |
694 | } | |
c906108c | 695 | |
386c036b | 696 | gdb_assert (element == num_elements); |
c906108c | 697 | |
cf84fa6b | 698 | if (return_method == return_method_struct) |
c906108c | 699 | { |
e1613aba | 700 | gdb_byte buf[4]; |
c906108c | 701 | |
e17a4113 | 702 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
703 | write_memory (sp, buf, 4); |
704 | } | |
c906108c | 705 | |
386c036b | 706 | return sp; |
c906108c SS |
707 | } |
708 | ||
386c036b | 709 | static CORE_ADDR |
7d9b040b | 710 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
711 | struct regcache *regcache, CORE_ADDR bp_addr, |
712 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
713 | function_call_return_method return_method, |
714 | CORE_ADDR struct_addr) | |
c906108c | 715 | { |
cf84fa6b AH |
716 | CORE_ADDR call_pc = (return_method == return_method_struct |
717 | ? (bp_addr - 12) : (bp_addr - 8)); | |
386c036b MK |
718 | |
719 | /* Set return address. */ | |
720 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
721 | ||
722 | /* Set up function arguments. */ | |
cf84fa6b AH |
723 | sp = sparc32_store_arguments (regcache, nargs, args, sp, return_method, |
724 | struct_addr); | |
386c036b MK |
725 | |
726 | /* Allocate the 16-word window save area. */ | |
727 | sp -= 16 * 4; | |
c906108c | 728 | |
386c036b MK |
729 | /* Stack should be doubleword aligned at this point. */ |
730 | gdb_assert (sp % 8 == 0); | |
c906108c | 731 | |
386c036b MK |
732 | /* Finally, update the stack pointer. */ |
733 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
734 | ||
735 | return sp; | |
736 | } | |
737 | \f | |
c906108c | 738 | |
386c036b MK |
739 | /* Use the program counter to determine the contents and size of a |
740 | breakpoint instruction. Return a pointer to a string of bytes that | |
741 | encode a breakpoint instruction, store the length of the string in | |
742 | *LEN and optionally adjust *PC to point to the correct memory | |
743 | location for inserting the breakpoint. */ | |
04180708 | 744 | constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 745 | |
04180708 | 746 | typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; |
386c036b | 747 | \f |
c906108c | 748 | |
386c036b | 749 | /* Allocate and initialize a frame cache. */ |
c906108c | 750 | |
386c036b MK |
751 | static struct sparc_frame_cache * |
752 | sparc_alloc_frame_cache (void) | |
753 | { | |
754 | struct sparc_frame_cache *cache; | |
c906108c | 755 | |
386c036b | 756 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 757 | |
386c036b MK |
758 | /* Base address. */ |
759 | cache->base = 0; | |
760 | cache->pc = 0; | |
c906108c | 761 | |
386c036b MK |
762 | /* Frameless until proven otherwise. */ |
763 | cache->frameless_p = 1; | |
369c397b JB |
764 | cache->frame_offset = 0; |
765 | cache->saved_regs_mask = 0; | |
766 | cache->copied_regs_mask = 0; | |
386c036b MK |
767 | cache->struct_return_p = 0; |
768 | ||
769 | return cache; | |
770 | } | |
771 | ||
b0b92586 JB |
772 | /* GCC generates several well-known sequences of instructions at the begining |
773 | of each function prologue when compiling with -fstack-check. If one of | |
774 | such sequences starts at START_PC, then return the address of the | |
775 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
776 | ||
777 | static CORE_ADDR | |
778 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
779 | { | |
780 | CORE_ADDR pc = start_pc; | |
781 | unsigned long insn; | |
2067c8d4 | 782 | int probing_loop = 0; |
b0b92586 JB |
783 | |
784 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 785 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 786 | |
dda83cd7 SM |
787 | sethi <some immediate>, %g1 |
788 | sub %sp, %g1, %g1 | |
2067c8d4 JG |
789 | |
790 | or: | |
791 | ||
dda83cd7 SM |
792 | sethi <some immediate>, %g1 |
793 | sethi <some immediate>, %g4 | |
794 | sub %sp, %g1, %g1 | |
2067c8d4 JG |
795 | |
796 | or: | |
797 | ||
dda83cd7 SM |
798 | sethi <some immediate>, %g1 |
799 | sub %sp, %g1, %g1 | |
800 | sethi <some immediate>, %g4 | |
2067c8d4 JG |
801 | |
802 | If the optional instruction is found (setting g4), assume that a | |
803 | probing loop will follow. */ | |
804 | ||
805 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
806 | insn = sparc_fetch_instruction (pc); |
807 | pc = pc + 4; | |
808 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
809 | return start_pc; | |
810 | ||
2067c8d4 | 811 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
812 | insn = sparc_fetch_instruction (pc); |
813 | pc = pc + 4; | |
2067c8d4 JG |
814 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
815 | { | |
816 | probing_loop = 1; | |
817 | insn = sparc_fetch_instruction (pc); | |
818 | pc = pc + 4; | |
819 | } | |
820 | ||
821 | /* sub %sp, %g1, %g1 */ | |
b0b92586 | 822 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
dda83cd7 | 823 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) |
b0b92586 JB |
824 | return start_pc; |
825 | ||
826 | insn = sparc_fetch_instruction (pc); | |
827 | pc = pc + 4; | |
828 | ||
2067c8d4 JG |
829 | /* optional: sethi <some immediate>, %g4 */ |
830 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
831 | { | |
832 | probing_loop = 1; | |
833 | insn = sparc_fetch_instruction (pc); | |
834 | pc = pc + 4; | |
835 | } | |
836 | ||
b0b92586 | 837 | /* First possible sequence: |
dda83cd7 SM |
838 | [first two instructions above] |
839 | clr [%g1 - some immediate] */ | |
b0b92586 JB |
840 | |
841 | /* clr [%g1 - some immediate] */ | |
842 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
843 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
844 | { | |
845 | /* Valid stack-check sequence, return the new PC. */ | |
846 | return pc; | |
847 | } | |
848 | ||
849 | /* Second possible sequence: A small number of probes. | |
dda83cd7 SM |
850 | [first two instructions above] |
851 | clr [%g1] | |
852 | add %g1, -<some immediate>, %g1 | |
853 | clr [%g1] | |
854 | [repeat the two instructions above any (small) number of times] | |
855 | clr [%g1 - some immediate] */ | |
b0b92586 JB |
856 | |
857 | /* clr [%g1] */ | |
858 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
859 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
860 | { | |
861 | while (1) | |
dda83cd7 SM |
862 | { |
863 | /* add %g1, -<some immediate>, %g1 */ | |
864 | insn = sparc_fetch_instruction (pc); | |
865 | pc = pc + 4; | |
866 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
867 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
868 | break; | |
869 | ||
870 | /* clr [%g1] */ | |
871 | insn = sparc_fetch_instruction (pc); | |
872 | pc = pc + 4; | |
873 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
874 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
875 | return start_pc; | |
876 | } | |
b0b92586 JB |
877 | |
878 | /* clr [%g1 - some immediate] */ | |
879 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
dda83cd7 SM |
880 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) |
881 | return start_pc; | |
b0b92586 JB |
882 | |
883 | /* We found a valid stack-check sequence, return the new PC. */ | |
884 | return pc; | |
885 | } | |
886 | ||
887 | /* Third sequence: A probing loop. | |
dda83cd7 SM |
888 | [first three instructions above] |
889 | sub %g1, %g4, %g4 | |
890 | cmp %g1, %g4 | |
891 | be <disp> | |
892 | add %g1, -<some immediate>, %g1 | |
893 | ba <disp> | |
894 | clr [%g1] | |
2067c8d4 JG |
895 | |
896 | And an optional last probe for the remainder: | |
897 | ||
dda83cd7 | 898 | clr [%g4 - some immediate] */ |
b0b92586 | 899 | |
2067c8d4 | 900 | if (probing_loop) |
b0b92586 JB |
901 | { |
902 | /* sub %g1, %g4, %g4 */ | |
b0b92586 | 903 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
dda83cd7 SM |
904 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) |
905 | return start_pc; | |
b0b92586 JB |
906 | |
907 | /* cmp %g1, %g4 */ | |
908 | insn = sparc_fetch_instruction (pc); | |
909 | pc = pc + 4; | |
910 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
dda83cd7 SM |
911 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) |
912 | return start_pc; | |
b0b92586 JB |
913 | |
914 | /* be <disp> */ | |
915 | insn = sparc_fetch_instruction (pc); | |
916 | pc = pc + 4; | |
917 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
dda83cd7 | 918 | return start_pc; |
b0b92586 JB |
919 | |
920 | /* add %g1, -<some immediate>, %g1 */ | |
921 | insn = sparc_fetch_instruction (pc); | |
922 | pc = pc + 4; | |
923 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
dda83cd7 SM |
924 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) |
925 | return start_pc; | |
b0b92586 JB |
926 | |
927 | /* ba <disp> */ | |
928 | insn = sparc_fetch_instruction (pc); | |
929 | pc = pc + 4; | |
930 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
dda83cd7 | 931 | return start_pc; |
b0b92586 | 932 | |
2067c8d4 | 933 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
934 | insn = sparc_fetch_instruction (pc); |
935 | pc = pc + 4; | |
2067c8d4 | 936 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
dda83cd7 | 937 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 |
2067c8d4 | 938 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) |
dda83cd7 | 939 | return start_pc; |
b0b92586 | 940 | |
2067c8d4 JG |
941 | /* We found a valid stack-check sequence, return the new PC. */ |
942 | ||
943 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
944 | insn = sparc_fetch_instruction (pc); |
945 | pc = pc + 4; | |
946 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
dda83cd7 SM |
947 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) |
948 | return pc - 4; | |
2067c8d4 JG |
949 | else |
950 | return pc; | |
b0b92586 JB |
951 | } |
952 | ||
953 | /* No stack check code in our prologue, return the start_pc. */ | |
954 | return start_pc; | |
955 | } | |
956 | ||
369c397b JB |
957 | /* Record the effect of a SAVE instruction on CACHE. */ |
958 | ||
959 | void | |
960 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
961 | { | |
962 | /* The frame is set up. */ | |
963 | cache->frameless_p = 0; | |
964 | ||
965 | /* The frame pointer contains the CFA. */ | |
966 | cache->frame_offset = 0; | |
967 | ||
968 | /* The `local' and `in' registers are all saved. */ | |
969 | cache->saved_regs_mask = 0xffff; | |
970 | ||
971 | /* The `out' registers are all renamed. */ | |
972 | cache->copied_regs_mask = 0xff; | |
973 | } | |
974 | ||
975 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
976 | Bail out early if CURRENT_PC is reached. Return the address where | |
977 | the analysis stopped. | |
978 | ||
979 | We handle both the traditional register window model and the single | |
980 | register window (aka flat) model. */ | |
981 | ||
386c036b | 982 | CORE_ADDR |
be8626e0 MD |
983 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
984 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 985 | { |
08106042 | 986 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); |
386c036b MK |
987 | unsigned long insn; |
988 | int offset = 0; | |
c906108c | 989 | int dest = -1; |
c906108c | 990 | |
b0b92586 JB |
991 | pc = sparc_skip_stack_check (pc); |
992 | ||
386c036b MK |
993 | if (current_pc <= pc) |
994 | return current_pc; | |
995 | ||
996 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
997 | SPARC the linker usually defines a symbol (typically | |
998 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
999 | This symbol makes us end up here with PC pointing at the start of | |
1000 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
1001 | would do our normal prologue analysis, we would probably conclude | |
1002 | that we've got a frame when in reality we don't, since the | |
1003 | dynamic linker patches up the first PLT with some code that | |
1004 | starts with a SAVE instruction. Patch up PC such that it points | |
1005 | at the start of our PLT entry. */ | |
3e5d3a5a | 1006 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 1007 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 1008 | |
386c036b MK |
1009 | insn = sparc_fetch_instruction (pc); |
1010 | ||
369c397b JB |
1011 | /* Recognize store insns and record their sources. */ |
1012 | while (X_OP (insn) == 3 | |
1013 | && (X_OP3 (insn) == 0x4 /* stw */ | |
1014 | || X_OP3 (insn) == 0x7 /* std */ | |
1015 | || X_OP3 (insn) == 0xe) /* stx */ | |
1016 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
1017 | { | |
1018 | int regnum = X_RD (insn); | |
1019 | ||
1020 | /* Recognize stores into the corresponding stack slots. */ | |
1021 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
1022 | && ((X_I (insn) | |
1023 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
1024 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
1025 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
1026 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
1027 | { | |
1028 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
1029 | if (X_OP3 (insn) == 0x7) | |
1030 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
1031 | } | |
1032 | ||
1033 | offset += 4; | |
1034 | ||
1035 | insn = sparc_fetch_instruction (pc + offset); | |
1036 | } | |
1037 | ||
386c036b MK |
1038 | /* Recognize a SETHI insn and record its destination. */ |
1039 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
1040 | { |
1041 | dest = X_RD (insn); | |
386c036b MK |
1042 | offset += 4; |
1043 | ||
369c397b | 1044 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
1045 | } |
1046 | ||
386c036b MK |
1047 | /* Allow for an arithmetic operation on DEST or %g1. */ |
1048 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
1049 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
1050 | { | |
386c036b | 1051 | offset += 4; |
c906108c | 1052 | |
369c397b | 1053 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 1054 | } |
c906108c | 1055 | |
386c036b MK |
1056 | /* Check for the SAVE instruction that sets up the frame. */ |
1057 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 1058 | { |
369c397b JB |
1059 | sparc_record_save_insn (cache); |
1060 | offset += 4; | |
1061 | return pc + offset; | |
1062 | } | |
1063 | ||
1064 | /* Check for an arithmetic operation on %sp. */ | |
1065 | if (X_OP (insn) == 2 | |
1066 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1067 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1068 | && X_RD (insn) == SPARC_SP_REGNUM) | |
1069 | { | |
1070 | if (X_I (insn)) | |
1071 | { | |
1072 | cache->frame_offset = X_SIMM13 (insn); | |
1073 | if (X_OP3 (insn) == 0) | |
1074 | cache->frame_offset = -cache->frame_offset; | |
1075 | } | |
1076 | offset += 4; | |
1077 | ||
1078 | insn = sparc_fetch_instruction (pc + offset); | |
1079 | ||
1080 | /* Check for an arithmetic operation that sets up the frame. */ | |
1081 | if (X_OP (insn) == 2 | |
1082 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1083 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1084 | && X_RD (insn) == SPARC_FP_REGNUM) | |
1085 | { | |
1086 | cache->frameless_p = 0; | |
1087 | cache->frame_offset = 0; | |
1088 | /* We could check that the amount subtracted to %sp above is the | |
1089 | same as the one added here, but this seems superfluous. */ | |
1090 | cache->copied_regs_mask |= 0x40; | |
1091 | offset += 4; | |
1092 | ||
1093 | insn = sparc_fetch_instruction (pc + offset); | |
1094 | } | |
1095 | ||
1096 | /* Check for a move (or) operation that copies the return register. */ | |
1097 | if (X_OP (insn) == 2 | |
1098 | && X_OP3 (insn) == 0x2 | |
1099 | && !X_I (insn) | |
1100 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1101 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1102 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1103 | { | |
1104 | cache->copied_regs_mask |= 0x80; | |
1105 | offset += 4; | |
1106 | } | |
1107 | ||
1108 | return pc + offset; | |
c906108c SS |
1109 | } |
1110 | ||
1111 | return pc; | |
1112 | } | |
1113 | ||
386c036b MK |
1114 | /* Return PC of first real instruction of the function starting at |
1115 | START_PC. */ | |
f510d44e | 1116 | |
386c036b | 1117 | static CORE_ADDR |
6093d2eb | 1118 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1119 | { |
5dd918d9 | 1120 | CORE_ADDR func_addr; |
386c036b | 1121 | struct sparc_frame_cache cache; |
f510d44e DM |
1122 | |
1123 | /* This is the preferred method, find the end of the prologue by | |
1124 | using the debugging information. */ | |
5dd918d9 TT |
1125 | |
1126 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
f510d44e | 1127 | { |
5dd918d9 TT |
1128 | CORE_ADDR post_prologue_pc |
1129 | = skip_prologue_using_sal (gdbarch, func_addr); | |
f510d44e | 1130 | |
5dd918d9 TT |
1131 | if (post_prologue_pc != 0) |
1132 | return std::max (start_pc, post_prologue_pc); | |
f510d44e DM |
1133 | } |
1134 | ||
be8626e0 | 1135 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1136 | |
1137 | /* The psABI says that "Although the first 6 words of arguments | |
1138 | reside in registers, the standard stack frame reserves space for | |
1139 | them.". It also suggests that a function may use that space to | |
1140 | "write incoming arguments 0 to 5" into that space, and that's | |
1141 | indeed what GCC seems to be doing. In that case GCC will | |
1142 | generate debug information that points to the stack slots instead | |
1143 | of the registers, so we should consider the instructions that | |
369c397b | 1144 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1145 | |
369c397b | 1146 | while (1) |
075ccec8 MK |
1147 | { |
1148 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1149 | ||
369c397b JB |
1150 | /* Recognize instructions that store incoming arguments into the |
1151 | corresponding stack slots. */ | |
1152 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1153 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1154 | { |
369c397b JB |
1155 | int regnum = X_RD (insn); |
1156 | ||
1157 | /* Case of arguments still in %o[0..5]. */ | |
1158 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1159 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1160 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1161 | { | |
1162 | start_pc += 4; | |
1163 | continue; | |
1164 | } | |
1165 | ||
1166 | /* Case of arguments copied into %i[0..5]. */ | |
1167 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1168 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1169 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1170 | { | |
1171 | start_pc += 4; | |
1172 | continue; | |
1173 | } | |
075ccec8 MK |
1174 | } |
1175 | ||
1176 | break; | |
1177 | } | |
1178 | ||
1179 | return start_pc; | |
c906108c SS |
1180 | } |
1181 | ||
386c036b | 1182 | /* Normal frames. */ |
9319a2fe | 1183 | |
386c036b | 1184 | struct sparc_frame_cache * |
8480a37e | 1185 | sparc_frame_cache (const frame_info_ptr &this_frame, void **this_cache) |
9319a2fe | 1186 | { |
386c036b | 1187 | struct sparc_frame_cache *cache; |
9319a2fe | 1188 | |
386c036b | 1189 | if (*this_cache) |
19ba03f4 | 1190 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1191 | |
386c036b MK |
1192 | cache = sparc_alloc_frame_cache (); |
1193 | *this_cache = cache; | |
c906108c | 1194 | |
236369e7 | 1195 | cache->pc = get_frame_func (this_frame); |
386c036b | 1196 | if (cache->pc != 0) |
236369e7 JB |
1197 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1198 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1199 | |
1200 | if (cache->frameless_p) | |
c906108c | 1201 | { |
cbeae229 | 1202 | /* This function is frameless, so %fp (%i6) holds the frame |
dda83cd7 SM |
1203 | pointer for our calling frame. Use %sp (%o6) as this frame's |
1204 | base address. */ | |
cbeae229 | 1205 | cache->base = |
dda83cd7 | 1206 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1207 | } |
1208 | else | |
1209 | { | |
1210 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
dda83cd7 | 1211 | base address for the current stack frame. */ |
cbeae229 | 1212 | cache->base = |
236369e7 | 1213 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1214 | } |
c906108c | 1215 | |
369c397b JB |
1216 | cache->base += cache->frame_offset; |
1217 | ||
5b2d44a0 MK |
1218 | if (cache->base & 1) |
1219 | cache->base += BIAS; | |
1220 | ||
386c036b | 1221 | return cache; |
c906108c | 1222 | } |
c906108c | 1223 | |
aff37fc1 DM |
1224 | static int |
1225 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1226 | { | |
5f9c5a63 | 1227 | struct type *type = check_typedef (sym->type ()); |
78134374 | 1228 | enum type_code code = type->code (); |
aff37fc1 DM |
1229 | |
1230 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1231 | { | |
27710edb | 1232 | type = check_typedef (type->target_type ()); |
aff37fc1 | 1233 | if (sparc_structure_or_union_p (type) |
df86565b | 1234 | || (sparc_floating_p (type) && type->length () == 16)) |
aff37fc1 DM |
1235 | return 1; |
1236 | } | |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | ||
386c036b | 1241 | struct sparc_frame_cache * |
8480a37e | 1242 | sparc32_frame_cache (const frame_info_ptr &this_frame, void **this_cache) |
c906108c | 1243 | { |
386c036b MK |
1244 | struct sparc_frame_cache *cache; |
1245 | struct symbol *sym; | |
c906108c | 1246 | |
386c036b | 1247 | if (*this_cache) |
19ba03f4 | 1248 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1249 | |
236369e7 | 1250 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1251 | |
386c036b MK |
1252 | sym = find_pc_function (cache->pc); |
1253 | if (sym) | |
c906108c | 1254 | { |
aff37fc1 | 1255 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1256 | } |
5465445a JB |
1257 | else |
1258 | { | |
1259 | /* There is no debugging information for this function to | |
dda83cd7 SM |
1260 | help us determine whether this function returns a struct |
1261 | or not. So we rely on another heuristic which is to check | |
1262 | the instruction at the return address and see if this is | |
1263 | an "unimp" instruction. If it is, then it is a struct-return | |
1264 | function. */ | |
5465445a | 1265 | CORE_ADDR pc; |
369c397b JB |
1266 | int regnum = |
1267 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1268 | |
236369e7 | 1269 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a | 1270 | if (sparc_is_unimp_insn (pc)) |
dda83cd7 | 1271 | cache->struct_return_p = 1; |
5465445a | 1272 | } |
c906108c | 1273 | |
386c036b MK |
1274 | return cache; |
1275 | } | |
1276 | ||
1277 | static void | |
8480a37e | 1278 | sparc32_frame_this_id (const frame_info_ptr &this_frame, void **this_cache, |
386c036b MK |
1279 | struct frame_id *this_id) |
1280 | { | |
1281 | struct sparc_frame_cache *cache = | |
236369e7 | 1282 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1283 | |
1284 | /* This marks the outermost frame. */ | |
1285 | if (cache->base == 0) | |
1286 | return; | |
1287 | ||
1288 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1289 | } | |
c906108c | 1290 | |
236369e7 | 1291 | static struct value * |
8480a37e | 1292 | sparc32_frame_prev_register (const frame_info_ptr &this_frame, |
236369e7 | 1293 | void **this_cache, int regnum) |
386c036b | 1294 | { |
e17a4113 | 1295 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1296 | struct sparc_frame_cache *cache = |
236369e7 | 1297 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1298 | |
386c036b | 1299 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1300 | { |
236369e7 | 1301 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1302 | |
236369e7 JB |
1303 | /* If this functions has a Structure, Union or Quad-Precision |
1304 | return value, we have to skip the UNIMP instruction that encodes | |
1305 | the size of the structure. */ | |
1306 | if (cache->struct_return_p) | |
1307 | pc += 4; | |
386c036b | 1308 | |
369c397b JB |
1309 | regnum = |
1310 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1311 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1312 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1313 | } |
1314 | ||
42cdca6c MK |
1315 | /* Handle StackGhost. */ |
1316 | { | |
e17a4113 | 1317 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1318 | |
1319 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1320 | { | |
dda83cd7 SM |
1321 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1322 | ULONGEST i7; | |
236369e7 | 1323 | |
dda83cd7 SM |
1324 | /* Read the value in from memory. */ |
1325 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1326 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1327 | } |
1328 | } | |
1329 | ||
369c397b | 1330 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1331 | in the register save area. */ |
369c397b JB |
1332 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1333 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1334 | { |
236369e7 | 1335 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1336 | |
236369e7 | 1337 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1338 | } |
c906108c | 1339 | |
369c397b JB |
1340 | /* The previous frame's `out' registers may be accessible as the current |
1341 | frame's `in' registers. */ | |
1342 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1343 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1344 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1345 | |
236369e7 | 1346 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1347 | } |
c906108c | 1348 | |
386c036b MK |
1349 | static const struct frame_unwind sparc32_frame_unwind = |
1350 | { | |
a154d838 | 1351 | "sparc32 prologue", |
386c036b | 1352 | NORMAL_FRAME, |
8fbca658 | 1353 | default_frame_unwind_stop_reason, |
386c036b | 1354 | sparc32_frame_this_id, |
236369e7 JB |
1355 | sparc32_frame_prev_register, |
1356 | NULL, | |
1357 | default_frame_sniffer | |
386c036b | 1358 | }; |
386c036b | 1359 | \f |
c906108c | 1360 | |
386c036b | 1361 | static CORE_ADDR |
8480a37e | 1362 | sparc32_frame_base_address (const frame_info_ptr &this_frame, void **this_cache) |
386c036b MK |
1363 | { |
1364 | struct sparc_frame_cache *cache = | |
236369e7 | 1365 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1366 | |
386c036b MK |
1367 | return cache->base; |
1368 | } | |
c906108c | 1369 | |
386c036b MK |
1370 | static const struct frame_base sparc32_frame_base = |
1371 | { | |
1372 | &sparc32_frame_unwind, | |
1373 | sparc32_frame_base_address, | |
1374 | sparc32_frame_base_address, | |
1375 | sparc32_frame_base_address | |
1376 | }; | |
c906108c | 1377 | |
386c036b | 1378 | static struct frame_id |
8480a37e | 1379 | sparc_dummy_id (struct gdbarch *gdbarch, const frame_info_ptr &this_frame) |
386c036b MK |
1380 | { |
1381 | CORE_ADDR sp; | |
5af923b0 | 1382 | |
236369e7 | 1383 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1384 | if (sp & 1) |
1385 | sp += BIAS; | |
236369e7 | 1386 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1387 | } |
1388 | \f | |
c906108c | 1389 | |
3923a2b2 MK |
1390 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1391 | that into VALBUF. */ | |
5af923b0 | 1392 | |
386c036b MK |
1393 | static void |
1394 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1395 | gdb_byte *valbuf) |
386c036b | 1396 | { |
df86565b | 1397 | int len = type->length (); |
fe10a582 | 1398 | gdb_byte buf[32]; |
c906108c | 1399 | |
1933fd8e | 1400 | gdb_assert (!sparc_structure_return_p (type)); |
c906108c | 1401 | |
1933fd8e | 1402 | if (sparc_floating_p (type) || sparc_complex_floating_p (type) |
78134374 | 1403 | || type->code () == TYPE_CODE_ARRAY) |
5af923b0 | 1404 | { |
386c036b | 1405 | /* Floating return values. */ |
dca08e1f | 1406 | regcache->cooked_read (SPARC_F0_REGNUM, buf); |
386c036b | 1407 | if (len > 4) |
dca08e1f | 1408 | regcache->cooked_read (SPARC_F1_REGNUM, buf + 4); |
fe10a582 DM |
1409 | if (len > 8) |
1410 | { | |
dca08e1f SM |
1411 | regcache->cooked_read (SPARC_F2_REGNUM, buf + 8); |
1412 | regcache->cooked_read (SPARC_F3_REGNUM, buf + 12); | |
fe10a582 DM |
1413 | } |
1414 | if (len > 16) | |
1415 | { | |
dca08e1f SM |
1416 | regcache->cooked_read (SPARC_F4_REGNUM, buf + 16); |
1417 | regcache->cooked_read (SPARC_F5_REGNUM, buf + 20); | |
1418 | regcache->cooked_read (SPARC_F6_REGNUM, buf + 24); | |
1419 | regcache->cooked_read (SPARC_F7_REGNUM, buf + 28); | |
fe10a582 | 1420 | } |
386c036b | 1421 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1422 | } |
1423 | else | |
1424 | { | |
386c036b MK |
1425 | /* Integral and pointer return values. */ |
1426 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1427 | |
dca08e1f | 1428 | regcache->cooked_read (SPARC_O0_REGNUM, buf); |
386c036b MK |
1429 | if (len > 4) |
1430 | { | |
dca08e1f | 1431 | regcache->cooked_read (SPARC_O1_REGNUM, buf + 4); |
386c036b MK |
1432 | gdb_assert (len == 8); |
1433 | memcpy (valbuf, buf, 8); | |
1434 | } | |
1435 | else | |
1436 | { | |
1437 | /* Just stripping off any unused bytes should preserve the | |
1438 | signed-ness just fine. */ | |
1439 | memcpy (valbuf, buf + 4 - len, len); | |
1440 | } | |
1441 | } | |
1442 | } | |
c906108c | 1443 | |
3923a2b2 MK |
1444 | /* Store the function return value of type TYPE from VALBUF into |
1445 | REGCACHE. */ | |
c906108c | 1446 | |
386c036b MK |
1447 | static void |
1448 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1449 | const gdb_byte *valbuf) |
386c036b | 1450 | { |
df86565b | 1451 | int len = type->length (); |
1933fd8e | 1452 | gdb_byte buf[32]; |
c906108c | 1453 | |
1933fd8e | 1454 | gdb_assert (!sparc_structure_return_p (type)); |
c906108c | 1455 | |
fe10a582 | 1456 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1457 | { |
1458 | /* Floating return values. */ | |
1459 | memcpy (buf, valbuf, len); | |
b66f5587 | 1460 | regcache->cooked_write (SPARC_F0_REGNUM, buf); |
386c036b | 1461 | if (len > 4) |
b66f5587 | 1462 | regcache->cooked_write (SPARC_F1_REGNUM, buf + 4); |
fe10a582 DM |
1463 | if (len > 8) |
1464 | { | |
b66f5587 SM |
1465 | regcache->cooked_write (SPARC_F2_REGNUM, buf + 8); |
1466 | regcache->cooked_write (SPARC_F3_REGNUM, buf + 12); | |
fe10a582 DM |
1467 | } |
1468 | if (len > 16) | |
1469 | { | |
b66f5587 SM |
1470 | regcache->cooked_write (SPARC_F4_REGNUM, buf + 16); |
1471 | regcache->cooked_write (SPARC_F5_REGNUM, buf + 20); | |
1472 | regcache->cooked_write (SPARC_F6_REGNUM, buf + 24); | |
1473 | regcache->cooked_write (SPARC_F7_REGNUM, buf + 28); | |
fe10a582 | 1474 | } |
386c036b MK |
1475 | } |
1476 | else | |
c906108c | 1477 | { |
386c036b MK |
1478 | /* Integral and pointer return values. */ |
1479 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1480 | ||
1481 | if (len > 4) | |
2757dd86 | 1482 | { |
386c036b MK |
1483 | gdb_assert (len == 8); |
1484 | memcpy (buf, valbuf, 8); | |
b66f5587 | 1485 | regcache->cooked_write (SPARC_O1_REGNUM, buf + 4); |
2757dd86 AC |
1486 | } |
1487 | else | |
1488 | { | |
386c036b MK |
1489 | /* ??? Do we need to do any sign-extension here? */ |
1490 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1491 | } |
b66f5587 | 1492 | regcache->cooked_write (SPARC_O0_REGNUM, buf); |
c906108c SS |
1493 | } |
1494 | } | |
1495 | ||
b9d4c5ed | 1496 | static enum return_value_convention |
6a3a010b | 1497 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1498 | struct type *type, struct regcache *regcache, |
5cb0f2d5 | 1499 | struct value **read_value, const gdb_byte *writebuf) |
b9d4c5ed | 1500 | { |
e17a4113 UW |
1501 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1502 | ||
0a8f48b9 MK |
1503 | /* The psABI says that "...every stack frame reserves the word at |
1504 | %fp+64. If a function returns a structure, union, or | |
1505 | quad-precision value, this word should hold the address of the | |
1506 | object into which the return value should be copied." This | |
1507 | guarantees that we can always find the return value, not just | |
1508 | before the function returns. */ | |
1509 | ||
1933fd8e | 1510 | if (sparc_structure_return_p (type)) |
0a8f48b9 | 1511 | { |
bbfdfe1c DM |
1512 | ULONGEST sp; |
1513 | CORE_ADDR addr; | |
1514 | ||
911627e7 | 1515 | if (read_value != nullptr) |
0a8f48b9 | 1516 | { |
0a8f48b9 | 1517 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1518 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
911627e7 | 1519 | *read_value = value_at_non_lval (type, addr); |
0a8f48b9 | 1520 | } |
bbfdfe1c DM |
1521 | if (writebuf) |
1522 | { | |
1523 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1524 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
df86565b | 1525 | write_memory (addr, writebuf, type->length ()); |
bbfdfe1c | 1526 | } |
0a8f48b9 MK |
1527 | |
1528 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1529 | } | |
b9d4c5ed | 1530 | |
911627e7 TT |
1531 | if (read_value != nullptr) |
1532 | { | |
317c3ed9 | 1533 | *read_value = value::allocate (type); |
bbe912ba | 1534 | gdb_byte *readbuf = (*read_value)->contents_raw ().data (); |
911627e7 TT |
1535 | sparc32_extract_return_value (type, regcache, readbuf); |
1536 | } | |
b9d4c5ed MK |
1537 | if (writebuf) |
1538 | sparc32_store_return_value (type, regcache, writebuf); | |
1539 | ||
1540 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1541 | } | |
1542 | ||
386c036b MK |
1543 | static int |
1544 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1545 | { |
386c036b | 1546 | return (sparc_structure_or_union_p (type) |
df86565b | 1547 | || (sparc_floating_p (type) && type->length () == 16) |
fe10a582 | 1548 | || sparc_complex_floating_p (type)); |
386c036b | 1549 | } |
c906108c | 1550 | |
aff37fc1 | 1551 | static int |
8480a37e | 1552 | sparc32_dwarf2_struct_return_p (const frame_info_ptr &this_frame) |
aff37fc1 | 1553 | { |
236369e7 | 1554 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1555 | struct symbol *sym = find_pc_function (pc); |
1556 | ||
1557 | if (sym) | |
1558 | return sparc32_struct_return_from_sym (sym); | |
1559 | return 0; | |
1560 | } | |
1561 | ||
f5a9b87d DM |
1562 | static void |
1563 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1564 | struct dwarf2_frame_state_reg *reg, |
8480a37e | 1565 | const frame_info_ptr &this_frame) |
f5a9b87d | 1566 | { |
aff37fc1 DM |
1567 | int off; |
1568 | ||
f5a9b87d DM |
1569 | switch (regnum) |
1570 | { | |
1571 | case SPARC_G0_REGNUM: | |
1572 | /* Since %g0 is always zero, there is no point in saving it, and | |
1573 | people will be inclined omit it from the CFI. Make sure we | |
1574 | don't warn about that. */ | |
1575 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1576 | break; | |
1577 | case SPARC_SP_REGNUM: | |
1578 | reg->how = DWARF2_FRAME_REG_CFA; | |
1579 | break; | |
1580 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1581 | case SPARC32_NPC_REGNUM: |
1582 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1583 | off = 8; |
4a4e5149 | 1584 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1585 | off += 4; |
1586 | if (regnum == SPARC32_NPC_REGNUM) | |
1587 | off += 4; | |
1588 | reg->loc.offset = off; | |
f5a9b87d DM |
1589 | break; |
1590 | } | |
1591 | } | |
1592 | ||
b41c5a85 JW |
1593 | /* Implement the execute_dwarf_cfa_vendor_op method. */ |
1594 | ||
1595 | static bool | |
1596 | sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, | |
1597 | struct dwarf2_frame_state *fs) | |
1598 | { | |
1599 | /* Only DW_CFA_GNU_window_save is expected on SPARC. */ | |
1600 | if (op != DW_CFA_GNU_window_save) | |
1601 | return false; | |
1602 | ||
1603 | uint64_t reg; | |
1604 | int size = register_size (gdbarch, 0); | |
1605 | ||
1c90d9f0 | 1606 | fs->regs.alloc_regs (32); |
b41c5a85 JW |
1607 | for (reg = 8; reg < 16; reg++) |
1608 | { | |
1609 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG; | |
1610 | fs->regs.reg[reg].loc.reg = reg + 16; | |
1611 | } | |
1612 | for (reg = 16; reg < 32; reg++) | |
1613 | { | |
1614 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET; | |
1615 | fs->regs.reg[reg].loc.offset = (reg - 16) * size; | |
1616 | } | |
1617 | ||
1618 | return true; | |
1619 | } | |
1620 | ||
386c036b MK |
1621 | \f |
1622 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1623 | and most operating systems don't implement it either, so we provide | |
1624 | software single-step mechanism. */ | |
c906108c | 1625 | |
386c036b | 1626 | static CORE_ADDR |
cd76b525 | 1627 | sparc_analyze_control_transfer (struct regcache *regcache, |
c893be75 | 1628 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1629 | { |
1630 | unsigned long insn = sparc_fetch_instruction (pc); | |
1631 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1632 | int branch_p = 0, fused_p = 0; |
386c036b | 1633 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1634 | |
8d1b3521 | 1635 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1636 | { |
8d1b3521 DM |
1637 | if ((insn & 0x10000000) == 0) |
1638 | { | |
1639 | /* Branch on Integer Register with Prediction (BPr). */ | |
1640 | branch_p = 1; | |
1641 | conditional_p = 1; | |
1642 | } | |
1643 | else | |
1644 | { | |
1645 | /* Compare and Branch */ | |
1646 | branch_p = 1; | |
1647 | fused_p = 1; | |
1648 | offset = 4 * X_DISP10 (insn); | |
1649 | } | |
c906108c | 1650 | } |
386c036b | 1651 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1652 | { |
386c036b MK |
1653 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1654 | branch_p = 1; | |
1655 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1656 | } |
386c036b MK |
1657 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1658 | { | |
1659 | /* Branch on Floating-Point Condition Codes with Prediction | |
dda83cd7 | 1660 | (FBPfcc). */ |
386c036b MK |
1661 | branch_p = 1; |
1662 | offset = 4 * X_DISP19 (insn); | |
1663 | } | |
1664 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1665 | { | |
1666 | /* Branch on Integer Condition Codes (Bicc). */ | |
1667 | branch_p = 1; | |
1668 | offset = 4 * X_DISP22 (insn); | |
1669 | } | |
1670 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1671 | { |
386c036b MK |
1672 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1673 | branch_p = 1; | |
1674 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1675 | } |
c893be75 MK |
1676 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1677 | { | |
bd2b40ac | 1678 | frame_info_ptr frame = get_current_frame (); |
cd76b525 | 1679 | |
c893be75 | 1680 | /* Trap instruction (TRAP). */ |
345bd07c | 1681 | gdbarch *arch = regcache->arch (); |
08106042 | 1682 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (arch); |
345bd07c | 1683 | return tdep->step_trap (frame, insn); |
c893be75 | 1684 | } |
386c036b MK |
1685 | |
1686 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1687 | ||
386c036b | 1688 | if (branch_p) |
c906108c | 1689 | { |
8d1b3521 DM |
1690 | if (fused_p) |
1691 | { | |
1692 | /* Fused compare-and-branch instructions are non-delayed, | |
85102364 | 1693 | and do not have an annulling capability. So we need to |
8d1b3521 DM |
1694 | always set a breakpoint on both the NPC and the branch |
1695 | target address. */ | |
1696 | gdb_assert (offset != 0); | |
1697 | return pc + offset; | |
1698 | } | |
1699 | else if (conditional_p) | |
c906108c | 1700 | { |
386c036b MK |
1701 | /* For conditional branches, return nPC + 4 iff the annul |
1702 | bit is 1. */ | |
1703 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1704 | } |
1705 | else | |
1706 | { | |
386c036b MK |
1707 | /* For unconditional branches, return the target if its |
1708 | specified condition is "always" and return nPC + 4 if the | |
1709 | condition is "never". If the annul bit is 1, set *NPC to | |
1710 | zero. */ | |
1711 | if (X_COND (insn) == 0x0) | |
1712 | pc = *npc, offset = 4; | |
1713 | if (X_A (insn)) | |
1714 | *npc = 0; | |
1715 | ||
386c036b | 1716 | return pc + offset; |
c906108c SS |
1717 | } |
1718 | } | |
386c036b MK |
1719 | |
1720 | return 0; | |
c906108c SS |
1721 | } |
1722 | ||
c893be75 | 1723 | static CORE_ADDR |
8480a37e | 1724 | sparc_step_trap (const frame_info_ptr &frame, unsigned long insn) |
c893be75 MK |
1725 | { |
1726 | return 0; | |
1727 | } | |
1728 | ||
a0ff9e1a | 1729 | static std::vector<CORE_ADDR> |
f5ea389a | 1730 | sparc_software_single_step (struct regcache *regcache) |
386c036b | 1731 | { |
ac7936df | 1732 | struct gdbarch *arch = regcache->arch (); |
08106042 | 1733 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (arch); |
8181d85f | 1734 | CORE_ADDR npc, nnpc; |
c906108c | 1735 | |
e0cd558a | 1736 | CORE_ADDR pc, orig_npc; |
a0ff9e1a | 1737 | std::vector<CORE_ADDR> next_pcs; |
c906108c | 1738 | |
cd76b525 YQ |
1739 | pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); |
1740 | orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); | |
c906108c | 1741 | |
e0cd558a | 1742 | /* Analyze the instruction at PC. */ |
cd76b525 | 1743 | nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); |
e0cd558a | 1744 | if (npc != 0) |
a0ff9e1a | 1745 | next_pcs.push_back (npc); |
8181d85f | 1746 | |
e0cd558a | 1747 | if (nnpc != 0) |
a0ff9e1a | 1748 | next_pcs.push_back (nnpc); |
c906108c | 1749 | |
e0cd558a UW |
1750 | /* Assert that we have set at least one breakpoint, and that |
1751 | they're not set at the same spot - unless we're going | |
1752 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1753 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1754 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b | 1755 | |
93f9a11f | 1756 | return next_pcs; |
386c036b MK |
1757 | } |
1758 | ||
1759 | static void | |
61a1198a | 1760 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1761 | { |
345bd07c | 1762 | gdbarch *arch = regcache->arch (); |
08106042 | 1763 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (arch); |
386c036b | 1764 | |
61a1198a UW |
1765 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1766 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1767 | } |
1768 | \f | |
5af923b0 | 1769 | |
e5139de8 | 1770 | /* Iterate over core file register note sections. */ |
a54124c5 | 1771 | |
e5139de8 AA |
1772 | static void |
1773 | sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
1774 | iterate_over_regset_sections_cb *cb, | |
1775 | void *cb_data, | |
1776 | const struct regcache *regcache) | |
a54124c5 | 1777 | { |
08106042 | 1778 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); |
a54124c5 | 1779 | |
a616bb94 AH |
1780 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, |
1781 | cb_data); | |
1782 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, | |
1783 | NULL, cb_data); | |
a54124c5 MK |
1784 | } |
1785 | \f | |
1786 | ||
3f7b46f2 IR |
1787 | static int |
1788 | validate_tdesc_registers (const struct target_desc *tdesc, | |
dda83cd7 SM |
1789 | struct tdesc_arch_data *tdesc_data, |
1790 | const char *feature_name, | |
1791 | const char * const register_names[], | |
1792 | unsigned int registers_num, | |
1793 | unsigned int reg_start) | |
3f7b46f2 IR |
1794 | { |
1795 | int valid_p = 1; | |
1796 | const struct tdesc_feature *feature; | |
1797 | ||
1798 | feature = tdesc_find_feature (tdesc, feature_name); | |
1799 | if (feature == NULL) | |
1800 | return 0; | |
1801 | ||
1802 | for (unsigned int i = 0; i < registers_num; i++) | |
1803 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
dda83cd7 SM |
1804 | reg_start + i, |
1805 | register_names[i]); | |
3f7b46f2 IR |
1806 | |
1807 | return valid_p; | |
1808 | } | |
1809 | ||
386c036b MK |
1810 | static struct gdbarch * |
1811 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1812 | { | |
3f7b46f2 | 1813 | const struct target_desc *tdesc = info.target_desc; |
3f7b46f2 | 1814 | int valid_p = 1; |
c906108c | 1815 | |
386c036b MK |
1816 | /* If there is already a candidate, use it. */ |
1817 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1818 | if (arches != NULL) | |
1819 | return arches->gdbarch; | |
c906108c | 1820 | |
386c036b | 1821 | /* Allocate space for the new architecture. */ |
2b16913c SM |
1822 | gdbarch *gdbarch |
1823 | = gdbarch_alloc (&info, gdbarch_tdep_up (new sparc_gdbarch_tdep)); | |
1824 | sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); | |
5af923b0 | 1825 | |
386c036b MK |
1826 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1827 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1828 | tdep->step_trap = sparc_step_trap; |
3f7b46f2 IR |
1829 | tdep->fpu_register_names = sparc32_fpu_register_names; |
1830 | tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); | |
1831 | tdep->cp0_register_names = sparc32_cp0_register_names; | |
1832 | tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); | |
386c036b MK |
1833 | |
1834 | set_gdbarch_long_double_bit (gdbarch, 128); | |
552f1157 | 1835 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad); |
386c036b | 1836 | |
53375380 PA |
1837 | set_gdbarch_wchar_bit (gdbarch, 16); |
1838 | set_gdbarch_wchar_signed (gdbarch, 1); | |
1839 | ||
386c036b MK |
1840 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); |
1841 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1842 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1843 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
3f7b46f2 IR |
1844 | set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); |
1845 | set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); | |
386c036b | 1846 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); |
7f0f3b0f SM |
1847 | set_gdbarch_deprecated_pseudo_register_write (gdbarch, |
1848 | sparc32_pseudo_register_write); | |
386c036b MK |
1849 | |
1850 | /* Register numbers of various important registers. */ | |
1851 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1852 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1853 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1854 | ||
1855 | /* Call dummy code. */ | |
49a45ecf | 1856 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1857 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1858 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1859 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1860 | ||
5cb0f2d5 | 1861 | set_gdbarch_return_value_as_value (gdbarch, sparc32_return_value); |
386c036b MK |
1862 | set_gdbarch_stabs_argument_has_addr |
1863 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1864 | ||
1865 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1866 | ||
1867 | /* Stack grows downward. */ | |
1868 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1869 | |
04180708 YQ |
1870 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1871 | sparc_breakpoint::kind_from_pc); | |
1872 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1873 | sparc_breakpoint::bp_from_kind); | |
c906108c | 1874 | |
386c036b | 1875 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1876 | |
386c036b MK |
1877 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1878 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1879 | |
236369e7 | 1880 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1881 | |
386c036b MK |
1882 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1883 | ||
f5a9b87d DM |
1884 | /* Hook in the DWARF CFI frame unwinder. */ |
1885 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
b41c5a85 JW |
1886 | /* Register DWARF vendor CFI handler. */ |
1887 | set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, | |
1888 | sparc_execute_dwarf_cfa_vendor_op); | |
f5a9b87d DM |
1889 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the |
1890 | StackGhost issues have been resolved. */ | |
1891 | ||
b2a0b9b2 DM |
1892 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1893 | gdbarch_init_osabi (info, gdbarch); | |
1894 | ||
236369e7 | 1895 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1896 | |
3f7b46f2 IR |
1897 | if (tdesc_has_registers (tdesc)) |
1898 | { | |
c1e1314d | 1899 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
3f7b46f2 IR |
1900 | |
1901 | /* Validate that the descriptor provides the mandatory registers | |
dda83cd7 | 1902 | and allocate their numbers. */ |
c1e1314d | 1903 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), |
dda83cd7 SM |
1904 | "org.gnu.gdb.sparc.cpu", |
1905 | sparc_core_register_names, | |
1906 | ARRAY_SIZE (sparc_core_register_names), | |
1907 | SPARC_G0_REGNUM); | |
c1e1314d | 1908 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), |
dda83cd7 SM |
1909 | "org.gnu.gdb.sparc.fpu", |
1910 | tdep->fpu_register_names, | |
1911 | tdep->fpu_registers_num, | |
1912 | SPARC_F0_REGNUM); | |
c1e1314d | 1913 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), |
dda83cd7 SM |
1914 | "org.gnu.gdb.sparc.cp0", |
1915 | tdep->cp0_register_names, | |
1916 | tdep->cp0_registers_num, | |
1917 | SPARC_F0_REGNUM | |
1918 | + tdep->fpu_registers_num); | |
3f7b46f2 | 1919 | if (!valid_p) |
c1e1314d | 1920 | return NULL; |
3f7b46f2 IR |
1921 | |
1922 | /* Target description may have changed. */ | |
c1e1314d TT |
1923 | info.tdesc_data = tdesc_data.get (); |
1924 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
3f7b46f2 IR |
1925 | } |
1926 | ||
a54124c5 | 1927 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1928 | if (tdep->gregset) |
e5139de8 AA |
1929 | set_gdbarch_iterate_over_regset_sections |
1930 | (gdbarch, sparc_iterate_over_regset_sections); | |
a54124c5 | 1931 | |
7e35103a JB |
1932 | register_sparc_ravenscar_ops (gdbarch); |
1933 | ||
386c036b MK |
1934 | return gdbarch; |
1935 | } | |
1936 | \f | |
1937 | /* Helper functions for dealing with register windows. */ | |
1938 | ||
1939 | void | |
1940 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1941 | { |
ac7936df | 1942 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1943 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b | 1944 | int offset = 0; |
e1613aba | 1945 | gdb_byte buf[8]; |
386c036b MK |
1946 | int i; |
1947 | ||
d1e93af6 SM |
1948 | /* This function calls functions that depend on the global current thread. */ |
1949 | gdb_assert (regcache->ptid () == inferior_ptid); | |
1950 | ||
386c036b MK |
1951 | if (sp & 1) |
1952 | { | |
1953 | /* Registers are 64-bit. */ | |
1954 | sp += BIAS; | |
c906108c | 1955 | |
386c036b MK |
1956 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1957 | { | |
1958 | if (regnum == i || regnum == -1) | |
1959 | { | |
1960 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1961 | |
1962 | /* Handle StackGhost. */ | |
1963 | if (i == SPARC_I7_REGNUM) | |
1964 | { | |
e17a4113 UW |
1965 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1966 | ULONGEST i7; | |
f700a364 | 1967 | |
e17a4113 UW |
1968 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1969 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1970 | i7 ^ wcookie); | |
f700a364 MK |
1971 | } |
1972 | ||
73e1c03f | 1973 | regcache->raw_supply (i, buf); |
386c036b MK |
1974 | } |
1975 | } | |
1976 | } | |
1977 | else | |
c906108c | 1978 | { |
386c036b MK |
1979 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1980 | pointer. */ | |
1981 | sp &= 0xffffffffUL; | |
c906108c | 1982 | |
386c036b MK |
1983 | /* Clear out the top half of the temporary buffer, and put the |
1984 | register value in the bottom half if we're in 64-bit mode. */ | |
ac7936df | 1985 | if (gdbarch_ptr_bit (regcache->arch ()) == 64) |
c906108c | 1986 | { |
386c036b MK |
1987 | memset (buf, 0, 4); |
1988 | offset = 4; | |
1989 | } | |
c906108c | 1990 | |
386c036b MK |
1991 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1992 | { | |
1993 | if (regnum == i || regnum == -1) | |
1994 | { | |
1995 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1996 | buf + offset, 4); | |
42cdca6c MK |
1997 | |
1998 | /* Handle StackGhost. */ | |
1999 | if (i == SPARC_I7_REGNUM) | |
2000 | { | |
e17a4113 UW |
2001 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2002 | ULONGEST i7; | |
42cdca6c | 2003 | |
e17a4113 UW |
2004 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
2005 | store_unsigned_integer (buf + offset, 4, byte_order, | |
2006 | i7 ^ wcookie); | |
42cdca6c MK |
2007 | } |
2008 | ||
73e1c03f | 2009 | regcache->raw_supply (i, buf); |
386c036b | 2010 | } |
c906108c SS |
2011 | } |
2012 | } | |
c906108c | 2013 | } |
c906108c SS |
2014 | |
2015 | void | |
386c036b MK |
2016 | sparc_collect_rwindow (const struct regcache *regcache, |
2017 | CORE_ADDR sp, int regnum) | |
c906108c | 2018 | { |
ac7936df | 2019 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2020 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b | 2021 | int offset = 0; |
e1613aba | 2022 | gdb_byte buf[8]; |
386c036b | 2023 | int i; |
5af923b0 | 2024 | |
d1e93af6 SM |
2025 | /* This function calls functions that depend on the global current thread. */ |
2026 | gdb_assert (regcache->ptid () == inferior_ptid); | |
2027 | ||
386c036b | 2028 | if (sp & 1) |
5af923b0 | 2029 | { |
386c036b MK |
2030 | /* Registers are 64-bit. */ |
2031 | sp += BIAS; | |
c906108c | 2032 | |
386c036b MK |
2033 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
2034 | { | |
2035 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
2036 | { | |
34a79281 | 2037 | regcache->raw_collect (i, buf); |
f700a364 MK |
2038 | |
2039 | /* Handle StackGhost. */ | |
2040 | if (i == SPARC_I7_REGNUM) | |
2041 | { | |
e17a4113 UW |
2042 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2043 | ULONGEST i7; | |
f700a364 | 2044 | |
e17a4113 UW |
2045 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
2046 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
2047 | } |
2048 | ||
386c036b MK |
2049 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
2050 | } | |
2051 | } | |
5af923b0 MS |
2052 | } |
2053 | else | |
2054 | { | |
386c036b MK |
2055 | /* Registers are 32-bit. Toss any sign-extension of the stack |
2056 | pointer. */ | |
2057 | sp &= 0xffffffffUL; | |
2058 | ||
2059 | /* Only use the bottom half if we're in 64-bit mode. */ | |
ac7936df | 2060 | if (gdbarch_ptr_bit (regcache->arch ()) == 64) |
386c036b MK |
2061 | offset = 4; |
2062 | ||
2063 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2064 | { | |
2065 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
2066 | { | |
34a79281 | 2067 | regcache->raw_collect (i, buf); |
42cdca6c MK |
2068 | |
2069 | /* Handle StackGhost. */ | |
2070 | if (i == SPARC_I7_REGNUM) | |
2071 | { | |
e17a4113 UW |
2072 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2073 | ULONGEST i7; | |
42cdca6c | 2074 | |
e17a4113 UW |
2075 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
2076 | store_unsigned_integer (buf + offset, 4, byte_order, | |
2077 | i7 ^ wcookie); | |
42cdca6c MK |
2078 | } |
2079 | ||
386c036b MK |
2080 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
2081 | buf + offset, 4); | |
2082 | } | |
2083 | } | |
5af923b0 | 2084 | } |
c906108c SS |
2085 | } |
2086 | ||
386c036b MK |
2087 | /* Helper functions for dealing with register sets. */ |
2088 | ||
c906108c | 2089 | void |
b4fd25c9 | 2090 | sparc32_supply_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2091 | struct regcache *regcache, |
2092 | int regnum, const void *gregs) | |
c906108c | 2093 | { |
19ba03f4 | 2094 | const gdb_byte *regs = (const gdb_byte *) gregs; |
22e74ef9 | 2095 | gdb_byte zero[4] = { 0 }; |
386c036b | 2096 | int i; |
5af923b0 | 2097 | |
386c036b | 2098 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
73e1c03f | 2099 | regcache->raw_supply (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); |
c906108c | 2100 | |
386c036b | 2101 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
73e1c03f | 2102 | regcache->raw_supply (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); |
5af923b0 | 2103 | |
386c036b | 2104 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
73e1c03f | 2105 | regcache->raw_supply (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); |
5af923b0 | 2106 | |
386c036b | 2107 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
73e1c03f | 2108 | regcache->raw_supply (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); |
5af923b0 | 2109 | |
386c036b | 2110 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
73e1c03f | 2111 | regcache->raw_supply (SPARC_G0_REGNUM, &zero); |
5af923b0 | 2112 | |
386c036b | 2113 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 2114 | { |
b4fd25c9 | 2115 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2116 | |
2117 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2118 | { | |
2119 | if (regnum == i || regnum == -1) | |
73e1c03f | 2120 | regcache->raw_supply (i, regs + offset); |
386c036b MK |
2121 | offset += 4; |
2122 | } | |
c906108c | 2123 | } |
386c036b MK |
2124 | |
2125 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 2126 | { |
386c036b | 2127 | /* Not all of the register set variants include Locals and |
dda83cd7 | 2128 | Inputs. For those that don't, we read them off the stack. */ |
b4fd25c9 | 2129 | if (gregmap->r_l0_offset == -1) |
386c036b MK |
2130 | { |
2131 | ULONGEST sp; | |
2132 | ||
2133 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
2134 | sparc_supply_rwindow (regcache, sp, regnum); | |
2135 | } | |
2136 | else | |
2137 | { | |
b4fd25c9 | 2138 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2139 | |
2140 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2141 | { | |
2142 | if (regnum == i || regnum == -1) | |
73e1c03f | 2143 | regcache->raw_supply (i, regs + offset); |
386c036b MK |
2144 | offset += 4; |
2145 | } | |
2146 | } | |
c906108c SS |
2147 | } |
2148 | } | |
2149 | ||
c5aa993b | 2150 | void |
b4fd25c9 | 2151 | sparc32_collect_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2152 | const struct regcache *regcache, |
2153 | int regnum, void *gregs) | |
c906108c | 2154 | { |
19ba03f4 | 2155 | gdb_byte *regs = (gdb_byte *) gregs; |
386c036b | 2156 | int i; |
c5aa993b | 2157 | |
386c036b | 2158 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
34a79281 | 2159 | regcache->raw_collect (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); |
60054393 | 2160 | |
386c036b | 2161 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
34a79281 | 2162 | regcache->raw_collect (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); |
386c036b MK |
2163 | |
2164 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
34a79281 | 2165 | regcache->raw_collect (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); |
5af923b0 | 2166 | |
386c036b | 2167 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
34a79281 | 2168 | regcache->raw_collect (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); |
386c036b MK |
2169 | |
2170 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 2171 | { |
b4fd25c9 | 2172 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2173 | |
2174 | /* %g0 is always zero. */ | |
2175 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2176 | { | |
2177 | if (regnum == i || regnum == -1) | |
34a79281 | 2178 | regcache->raw_collect (i, regs + offset); |
386c036b MK |
2179 | offset += 4; |
2180 | } | |
5af923b0 | 2181 | } |
386c036b MK |
2182 | |
2183 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2184 | { |
386c036b | 2185 | /* Not all of the register set variants include Locals and |
dda83cd7 | 2186 | Inputs. For those that don't, we read them off the stack. */ |
b4fd25c9 | 2187 | if (gregmap->r_l0_offset != -1) |
386c036b | 2188 | { |
b4fd25c9 | 2189 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2190 | |
2191 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2192 | { | |
2193 | if (regnum == i || regnum == -1) | |
34a79281 | 2194 | regcache->raw_collect (i, regs + offset); |
386c036b MK |
2195 | offset += 4; |
2196 | } | |
2197 | } | |
5af923b0 | 2198 | } |
c906108c SS |
2199 | } |
2200 | ||
c906108c | 2201 | void |
b4fd25c9 | 2202 | sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2203 | struct regcache *regcache, |
386c036b | 2204 | int regnum, const void *fpregs) |
c906108c | 2205 | { |
19ba03f4 | 2206 | const gdb_byte *regs = (const gdb_byte *) fpregs; |
386c036b | 2207 | int i; |
60054393 | 2208 | |
386c036b | 2209 | for (i = 0; i < 32; i++) |
c906108c | 2210 | { |
386c036b | 2211 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
73e1c03f SM |
2212 | regcache->raw_supply (SPARC_F0_REGNUM + i, |
2213 | regs + fpregmap->r_f0_offset + (i * 4)); | |
c906108c | 2214 | } |
5af923b0 | 2215 | |
386c036b | 2216 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
73e1c03f | 2217 | regcache->raw_supply (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset); |
c906108c SS |
2218 | } |
2219 | ||
386c036b | 2220 | void |
b4fd25c9 | 2221 | sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2222 | const struct regcache *regcache, |
386c036b | 2223 | int regnum, void *fpregs) |
c906108c | 2224 | { |
19ba03f4 | 2225 | gdb_byte *regs = (gdb_byte *) fpregs; |
386c036b | 2226 | int i; |
c906108c | 2227 | |
386c036b MK |
2228 | for (i = 0; i < 32; i++) |
2229 | { | |
2230 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
34a79281 SM |
2231 | regcache->raw_collect (SPARC_F0_REGNUM + i, |
2232 | regs + fpregmap->r_f0_offset + (i * 4)); | |
386c036b | 2233 | } |
c906108c | 2234 | |
386c036b | 2235 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
34a79281 SM |
2236 | regcache->raw_collect (SPARC32_FSR_REGNUM, |
2237 | regs + fpregmap->r_fsr_offset); | |
c906108c | 2238 | } |
c906108c | 2239 | \f |
c906108c | 2240 | |
386c036b | 2241 | /* SunOS 4. */ |
c906108c | 2242 | |
386c036b | 2243 | /* From <machine/reg.h>. */ |
b4fd25c9 | 2244 | const struct sparc_gregmap sparc32_sunos4_gregmap = |
c906108c | 2245 | { |
386c036b MK |
2246 | 0 * 4, /* %psr */ |
2247 | 1 * 4, /* %pc */ | |
2248 | 2 * 4, /* %npc */ | |
2249 | 3 * 4, /* %y */ | |
2250 | -1, /* %wim */ | |
2251 | -1, /* %tbr */ | |
2252 | 4 * 4, /* %g1 */ | |
2253 | -1 /* %l0 */ | |
2254 | }; | |
db75c717 | 2255 | |
b4fd25c9 | 2256 | const struct sparc_fpregmap sparc32_sunos4_fpregmap = |
db75c717 DM |
2257 | { |
2258 | 0 * 4, /* %f0 */ | |
2259 | 33 * 4, /* %fsr */ | |
2260 | }; | |
2261 | ||
b4fd25c9 | 2262 | const struct sparc_fpregmap sparc32_bsd_fpregmap = |
db75c717 DM |
2263 | { |
2264 | 0 * 4, /* %f0 */ | |
2265 | 32 * 4, /* %fsr */ | |
2266 | }; | |
c906108c | 2267 | |
6c265988 | 2268 | void _initialize_sparc_tdep (); |
c906108c | 2269 | void |
6c265988 | 2270 | _initialize_sparc_tdep () |
c906108c | 2271 | { |
ec29a63c | 2272 | gdbarch_register (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2273 | } |