]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/arm-dis.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[binutils, ARM, 15/16] Add support for VSCCLRM
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
2d5d5a8f 35#include "bfd.h"
252b5132
RH		 36#include "elf-bfd.h"
37#include "elf/internal.h"
38#include "elf/arm.h"
e49d43ff 39#include "mach-o.h"
252b5132 40
6b5d3a4d 41/* FIXME: Belongs in global header. */
01c7f630 42#ifndef strneq
58efb6c0
NC		 43#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44#endif
45
1fbaefec
PB		 46/* Cached mapping symbol state. */
47enum map_type
48{
49 MAP_ARM,
50 MAP_THUMB,
51 MAP_DATA
52};
53
b0e28b39
DJ		 54struct arm_private_data
55{
56 /* The features to use when disassembling optional instructions. */
57 arm_feature_set features;
58
1fbaefec
PB		 59 /* Track the last type (although this doesn't seem to be useful) */
60 enum map_type last_type;
61
62 /* Tracking symbol table information */
63 int last_mapping_sym;
796d6298
TC		 64
65 /* The end range of the current range being disassembled. */
66 bfd_vma last_stop_offset;
1fbaefec 67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
6b0dd094
AV		 78enum isa {
79 ANY,
80 T32,
81 ARM
82};
83
84
85/* Shared (between Arm and Thumb mode) opcode. */
86struct sopcode32
87{
88 enum isa isa; /* Execution mode instruction availability. */
89 arm_feature_set arch; /* Architecture defining this insn. */
90 unsigned long value; /* If arch is 0 then value is a sentinel. */
91 unsigned long mask; /* Recognise insn if (op & mask) == value. */
92 const char * assembler; /* How to disassemble this insn. */
93};
94
6b5d3a4d
ZW		 95struct opcode16
96{
823d2571 97 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 98 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 99 const char *assembler; /* How to disassemble this insn. */
100};
b7693d02 101
8f06b2d8 102/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 103
2fbad815 104 %% %
4a5329c6 105
c22aaad1 106 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 107 %q print shifter argument
e2efe87d
MGD		 108 %u print condition code (unconditional in ARM mode,
109 UNPREDICTABLE if not AL in Thumb)
4a5329c6 110 %A print address for ldc/stc/ldf/stf instruction
16980d0b 111 %B print vstm/vldm register list
efd6b359 112 %C print vscclrm register list
4a5329c6 113 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 114 %F print the COUNT field of a LFM/SFM instruction.
115 %P print floating point precision in arithmetic insn
116 %Q print floating point precision in ldf/stf insn
117 %R print floating point rounding mode
118
33399f07 119 %<bitfield>c print as a condition code (for vsel)
4a5329c6 120 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 121 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
122 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 123 %<bitfield>d print the bitfield in decimal
16980d0b 124 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 125 %<bitfield>x print the bitfield in hex
126 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 127 %<bitfield>f print a floating point constant if >7 else a
128 floating point register
4a5329c6
ZW		 129 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
130 %<bitfield>g print as an iWMMXt 64-bit register
131 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 132 %<bitfield>D print as a NEON D register
133 %<bitfield>Q print as a NEON Q register
c28eeff2 134 %<bitfield>V print as a NEON D or Q register
6f1c2142 135 %<bitfield>E print a quarter-float immediate value
4a5329c6 136
16980d0b 137 %y<code> print a single precision VFP reg.
2fbad815 138 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 139 %z<code> print a double precision VFP reg
2fbad815 140 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 141
16980d0b
JB		 142 %<bitfield>'c print specified char iff bitfield is all ones
143 %<bitfield>`c print specified char iff bitfield is all zeroes
144 %<bitfield>?ab... select from array of values in big endian order
43e65147 145
2fbad815 146 %L print as an iWMMXt N/M width field.
4a5329c6 147 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 148 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 149 versions.
150 %i print 5-bit immediate in bits 8,3..0
151 (print "32" when 0)
fe56b6ce 152 %r print register offset address for wldt/wstr instruction. */
2fbad815 153
21d799b5 154enum opcode_sentinel_enum
05413229
NC		 155{
156 SENTINEL_IWMMXT_START = 1,
157 SENTINEL_IWMMXT_END,
158 SENTINEL_GENERIC_START
159} opcode_sentinels;
160
aefd8a40 161#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 162#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
163#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 164#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 165
8f06b2d8 166/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 167
6b0dd094 168static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 169{
2fbad815 170 /* XScale instructions. */
6b0dd094 171 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 172 0x0e200010, 0x0fff0ff0,
173 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 174 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 175 0x0e280010, 0x0fff0ff0,
176 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 177 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 178 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 179 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 180 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 181 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 182 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 183
2fbad815 184 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 185 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
186 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 187 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 188 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 189 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 190 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 191 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 192 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 193 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 194 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 195 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 196 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 197 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 198 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 199 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 200 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 201 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 202 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 203 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 204 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 205 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 206 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 207 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 209 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 210 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 211 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 212 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 213 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 214 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 215 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 216 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 217 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 218 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 219 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 220 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 221 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 222 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 223 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 224 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 225 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 226 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 227 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 228 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 229 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 230 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 231 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 232 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 233 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 234 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 235 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 236 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 237 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 238 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 239 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 240 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 241 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 242 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 243 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 244 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 245 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 246 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 247 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 248 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 249 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 250 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 251 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 252 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 253 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 254 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 255 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 256 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 257 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 258 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 259 0x0e800120, 0x0f800ff0,
260 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 261 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 262 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 263 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 264 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 265 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 266 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 267 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 268 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 269 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 270 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 271 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 272 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 273 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 274 0x0e8000a0, 0x0f800ff0,
275 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 276 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 277 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 278 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 279 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 280 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 281 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 282 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 283 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 284 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 285 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 286 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 287 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 288 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 289 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 290 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 291 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 292 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 293 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 294 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 295 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 296 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 297 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 298 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 299 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 300 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 301 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 302 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 303 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 304 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 305 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 306 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 307 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 308 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 309 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 310 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 311 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 312 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 313 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 314 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 315 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 316 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 317 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 318 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 319 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 320 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 321 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 322 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 323 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 324 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 325 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 326 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 327 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 328 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 329 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 330 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 331 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 332 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 333 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 334 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 335 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 336 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 337 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 338 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 339 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 340
fe56b6ce 341 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 342 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 343 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 344 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 345 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 346 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 347 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 348 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 349 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 350 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 351 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 352 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 353 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 354 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 355 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 356 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 357 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 358 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 359 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 360 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 361 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 362 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 363 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 364 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 365 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 366 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 367 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 368 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 369 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 370 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 371 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 372 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 373 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 374 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 375 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 376 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 377 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 378 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 379 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 380 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 381 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 382 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 383 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 384 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 385 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 386 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 387 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 388 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 389 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 390 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 391 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 392 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 393 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 394 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 395 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 396 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 397 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 398 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 399 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 400 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 401 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 402 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 403 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 404 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 405 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 406 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 407 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 408 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 409 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 410 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 411 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 412 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 413 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 414 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 415 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 416 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 417 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 418 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 419 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 420 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 421 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 422 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 423 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 424 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 425 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 426 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 427 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 428
efd6b359
AV		 429 /* Armv8.1-M Mainline instructions. */
430 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
431 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
432 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
433 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
434
16a1fa25 435 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 436 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 437 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 438 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 439 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
440
fe56b6ce 441 /* Register load/store. */
6b0dd094 442 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 443 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 444 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 445 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 446 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 447 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 448 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 449 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 450 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 451 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 452 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 453 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 454 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 455 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 456 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 457 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 458 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 459 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 460 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 461 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 462 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 463 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 464 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 465 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 466 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 467 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 469 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 470 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 471 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571
TG		 473 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
474
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 476 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 477 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 478 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 479 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 480 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 481 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 482 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 483
fe56b6ce 484 /* Data transfer between ARM and NEON registers. */
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 486 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 488 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 490 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
6b0dd094 491 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 492 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
6b0dd094 493 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 494 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 496 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 498 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 500 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 502 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 504 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 505 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 506 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 508 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 510 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 512 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 513 /* Half-precision conversion instructions. */
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 515 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 516 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 517 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 518 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 519 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 520 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 521 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 522
fe56b6ce 523 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 524 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 525 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 526 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 527 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 528 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 529 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 531 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 533 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 535 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 537 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 538 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 539 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 541 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 542 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 543 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 545 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 547 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 549 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 551 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 553 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 554 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 555 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 556 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 557 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 558 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 559 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 560 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 561 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 563 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 565 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 567 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 569 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 571 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 573 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 575 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 577 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 579 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 581 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 583 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 585 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 587 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 589 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 591 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 593 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 595 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 597 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 599 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 601 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 603 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 605 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 607 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 609 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 611 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 613 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 615 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 617 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 619 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 621 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 623 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 625 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 627 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 629 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 631 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 633 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 635 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 637 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 639 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 641 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 643 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 645 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 647 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 649 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 651 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 653 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 655 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 657 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 659 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 661 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 662
663 /* Cirrus coprocessor instructions. */
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 665 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 667 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 669 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 671 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 673 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 675 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 677 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 679 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 681 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 683 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 685 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 687 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 689 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 691 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 693 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 695 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 697 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 699 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 701 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 703 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 705 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 707 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 709 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 711 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 713 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 715 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 717 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 719 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 721 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 723 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 725 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 727 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 729 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 731 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 733 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 735 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 737 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 739 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 741 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 743 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 745 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 747 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 749 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 751 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 753 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 755 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 757 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 759 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 761 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 763 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 765 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 767 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 768 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 769 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 770 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 771 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 772 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 773 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 775 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 777 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 779 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 781 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 782 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 783 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 785 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 787 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 789 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 791 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 793 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 795 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 797 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 799 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 801 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 803 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 805 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 807 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 808 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 809 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 810 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 811 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 812 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 813 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 814 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 815 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 817 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 819 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 821 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 823 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 825 0x0e000600, 0x0ff00f10,
826 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 828 0x0e100600, 0x0ff00f10,
829 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 830 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 831 0x0e200600, 0x0ff00f10,
832 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 834 0x0e300600, 0x0ff00f10,
835 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 836
62f3b8c8 837 /* VFP Fused multiply add instructions. */
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 839 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 841 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 843 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 845 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 847 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 849 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 851 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 853 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 854
33399f07 855 /* FP v5. */
6b0dd094 856 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 857 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 859 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 861 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 863 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 865 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 867 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 869 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 871 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 873 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 875 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 877 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 879 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 880
05413229 881 /* Generic coprocessor instructions. */
6b0dd094
AV		 882 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
883 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 884 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 885 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 886 0x0c500000, 0x0ff00000,
887 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 888 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 889 0x0e000000, 0x0f000010,
890 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 891 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 892 0x0e10f010, 0x0f10f010,
893 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 894 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 895 0x0e100010, 0x0f100010,
896 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 897 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 898 0x0e000010, 0x0f100010,
899 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 900 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 901 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 902 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 903 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 904
05413229 905 /* V6 coprocessor instructions. */
6b0dd094 906 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 907 0xfc500000, 0xfff00000,
908 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 909 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 910 0xfc400000, 0xfff00000,
911 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 912
c28eeff2 913 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 914 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 915 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 916 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 917 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 918 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 919 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 920 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 921 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 922 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 923 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 924 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 925 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 926 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 927 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 928 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 929 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 930 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 931 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 932 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 933 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 934
c604a79a 935 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 937 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 939 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
940
dec41383 941 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 942 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 943 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 944 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 945 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 946 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 947 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 948 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 949 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 950 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 951 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 952 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 953 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 954 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 955 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 956 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 957 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
958
05413229 959 /* V5 coprocessor instructions. */
6b0dd094 960 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 961 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 962 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 963 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 964 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 965 0xfe000000, 0xff000010,
966 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 967 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 968 0xfe000010, 0xff100010,
969 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 970 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 971 0xfe100010, 0xff100010,
972 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
973
b0c11777
RL		 974 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
975 cp_num: bit <11:8> == 0b1001.
976 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 977 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 978 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 979 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 980 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 981 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 982 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 983 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 984 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 985 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 986 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 987 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 988 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 989 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 990 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 991 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 992 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 993 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 994 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 995 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 996 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 997 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 998 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 999 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1000 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1001 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1002 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1003 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1004 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1005 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1006 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1007 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1008 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1010 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1011 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1012 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1013 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1014 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1015 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1016 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1018 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1020 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1021 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1022 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1023 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1024 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1025 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1026 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1027 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1028 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1029 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1030 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1031 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1032 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1033 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1034 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1036 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1037 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1038 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1039 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1040 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1041 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1042 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1043 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1044 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1045 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1046 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1047
49e8a725 1048 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1049 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1050 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1051
6b0dd094 1052 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1053};
1054
16980d0b
JB		 1055/* Neon opcode table: This does not encode the top byte -- that is
1056 checked by the print_insn_neon routine, as it depends on whether we are
1057 doing thumb32 or arm32 disassembly. */
1058
1059/* print_insn_neon recognizes the following format control codes:
1060
1061 %% %
1062
c22aaad1 1063 %c print condition code
e2efe87d
MGD		 1064 %u print condition code (unconditional in ARM mode,
1065 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1066 %A print v{st,ld}[1234] operands
1067 %B print v{st,ld}[1234] any one operands
1068 %C print v{st,ld}[1234] single->all operands
1069 %D print scalar
1070 %E print vmov, vmvn, vorr, vbic encoded constant
1071 %F print vtbl,vtbx register list
1072
1073 %<bitfield>r print as an ARM register
1074 %<bitfield>d print the bitfield in decimal
1075 %<bitfield>e print the 2^N - bitfield in decimal
1076 %<bitfield>D print as a NEON D register
1077 %<bitfield>Q print as a NEON Q register
1078 %<bitfield>R print as a NEON D or Q register
1079 %<bitfield>Sn print byte scaled width limited by n
1080 %<bitfield>Tn print short scaled width limited by n
1081 %<bitfield>Un print long scaled width limited by n
43e65147 1082
16980d0b
JB		 1083 %<bitfield>'c print specified char iff bitfield is all ones
1084 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1085 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1086
1087static const struct opcode32 neon_opcodes[] =
1088{
fe56b6ce 1089 /* Extract. */
823d2571
TG		 1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2b00840, 0xffb00850,
1092 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1094 0xf2b00000, 0xffb00810,
1095 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1096
fe56b6ce 1097 /* Move data element to all lanes. */
823d2571
TG		 1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1104
fe56b6ce 1105 /* Table lookup. */
823d2571
TG		 1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1110
8e79c3df 1111 /* Half-precision conversions. */
823d2571
TG		 1112 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1113 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1114 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1115 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1116
1117 /* NEON fused multiply add instructions. */
823d2571 1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1119 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1121 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1123 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1125 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1126
fe56b6ce 1127 /* Two registers, miscellaneous. */
823d2571
TG		 1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1129 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1130 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1131 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1133 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1134 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1135 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1136 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1137 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1138 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1139 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1140 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1141 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1142 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1143 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1144 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1145 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1146 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1147 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1148 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1149 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1151 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1153 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1157 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1163 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1169 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171 0xf3b20300, 0xffb30fd0,
1172 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1176 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1179 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1180 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1198 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1200 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1204 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1220 0xf3bb0600, 0xffbf0e10,
823d2571 1221 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1223 0xf3b70600, 0xffbf0e10,
1224 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1225
fe56b6ce 1226 /* Three registers of the same length. */
823d2571
TG		 1227 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1228 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1229 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1230 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1231 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1232 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1233 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1234 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1235 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1236 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1237 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1238 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1239 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1240 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1242 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1246 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1252 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1266 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1270 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1274 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1278 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1282 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1286 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1290 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1294 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1298 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1302 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1306 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1310 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1314 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1316 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1318 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1320 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1322 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1324 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1326 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1328 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1330 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1332 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1334 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1336 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf2000b00, 0xff800f10,
1345 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2000b10, 0xff800f10,
1348 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf3000b00, 0xff800f10,
1357 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2000000, 0xfe800f10,
1360 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2000010, 0xfe800f10,
1363 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2000100, 0xfe800f10,
1366 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2000200, 0xfe800f10,
1369 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2000210, 0xfe800f10,
1372 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2000300, 0xfe800f10,
1375 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2000310, 0xfe800f10,
1378 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2000400, 0xfe800f10,
1381 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2000410, 0xfe800f10,
1384 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2000500, 0xfe800f10,
1387 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2000510, 0xfe800f10,
1390 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2000600, 0xfe800f10,
1393 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2000610, 0xfe800f10,
1396 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2000700, 0xfe800f10,
1399 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2000710, 0xfe800f10,
1402 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2000910, 0xfe800f10,
1405 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2000a00, 0xfe800f10,
1408 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf2000a10, 0xfe800f10,
1411 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1413 0xf3000b10, 0xff800f10,
1414 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1416 0xf3000c10, 0xff800f10,
1417 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1418
fe56b6ce 1419 /* One register and an immediate value. */
823d2571
TG		 1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1446
fe56b6ce 1447 /* Two registers and a shift amount. */
823d2571
TG		 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf2880950, 0xfeb80fd0,
1460 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf2900950, 0xfeb00fd0,
1483 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2a00950, 0xfea00fd0,
1528 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2a00e10, 0xfea00e90,
1567 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1569 0xf2a00c10, 0xfea00e90,
1570 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1571
fe56b6ce 1572 /* Three registers of different lengths. */
823d2571
TG		 1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2800400, 0xff800f50,
1579 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2800600, 0xff800f50,
1582 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2800900, 0xff800f50,
1585 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2800b00, 0xff800f50,
1588 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2800d00, 0xff800f50,
1591 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf3800400, 0xff800f50,
1594 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf3800600, 0xff800f50,
1597 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2800000, 0xfe800f50,
1600 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2800100, 0xfe800f50,
1603 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf2800200, 0xfe800f50,
1606 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2800300, 0xfe800f50,
1609 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf2800500, 0xfe800f50,
1612 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2800700, 0xfe800f50,
1615 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf2800800, 0xfe800f50,
1618 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2800a00, 0xfe800f50,
1621 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf2800c00, 0xfe800f50,
1624 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1625
fe56b6ce 1626 /* Two registers and a scalar. */
823d2571
TG		 1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1630 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1631 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1632 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1638 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1639 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1640 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1646 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1647 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1648 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1658 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1659 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1660 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1664 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1665 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1666 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1670 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1671 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1672 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf2800240, 0xfe800f50,
1679 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2800640, 0xfe800f50,
1682 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf2800a40, 0xfe800f50,
1685 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1687 0xf2800e40, 0xff800f50,
1688 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1690 0xf2800f40, 0xff800f50,
1691 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1693 0xf3800e40, 0xff800f50,
1694 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1696 0xf3800f40, 0xff800f50,
1697 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1698 },
16980d0b 1699
fe56b6ce 1700 /* Element and structure load/store. */
823d2571
TG		 1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1739
1740 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1741};
1742
8f06b2d8
PB		 1743/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1744 ordered: they must be searched linearly from the top to obtain a correct
1745 match. */
1746
1747/* print_insn_arm recognizes the following format control codes:
1748
1749 %% %
1750
1751 %a print address for ldr/str instruction
1752 %s print address for ldr/str halfword/signextend instruction
c1e26897 1753 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1754 %b print branch destination
1755 %c print condition code (always bits 28-31)
1756 %m print register mask for ldm/stm instruction
1757 %o print operand2 (immediate or register + shift)
1758 %p print 'p' iff bits 12-15 are 15
1759 %t print 't' iff bit 21 set and bit 24 clear
1760 %B print arm BLX(1) destination
1761 %C print the PSR sub type.
62b3e311
PB		 1762 %U print barrier type.
1763 %P print address for pli instruction.
8f06b2d8
PB		 1764
1765 %<bitfield>r print as an ARM register
9eb6c0f1 1766 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1767 %<bitfield>R as %r but r15 is UNPREDICTABLE
1768 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1769 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1770 %<bitfield>d print the bitfield in decimal
43e65147 1771 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1772 %<bitfield>x print the bitfield in hex
1773 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1774
16980d0b
JB		 1775 %<bitfield>'c print specified char iff bitfield is all ones
1776 %<bitfield>`c print specified char iff bitfield is all zeroes
1777 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1778
8f06b2d8
PB		 1779 %e print arm SMI operand (bits 0..7,8..19).
1780 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1781 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1782 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1783
8f06b2d8
PB		 1784static const struct opcode32 arm_opcodes[] =
1785{
1786 /* ARM instructions. */
823d2571
TG		 1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1788 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1790 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1791
1792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1793 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1795 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1797 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1799 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1801 0x00800090, 0x0fa000f0,
1802 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1804 0x00a00090, 0x0fa000f0,
1805 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1806
105bde57 1807 /* V8.2 RAS extension instructions. */
4d1464f2 1808 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1809 0xe320f010, 0xffffffff, "esb"},
1810
53c4b28b 1811 /* V8 instructions. */
823d2571
TG		 1812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1813 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 1814 /* Defined in V8 but is in NOP space so available to all arch. */
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 1816 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1818 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1819 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1820 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1822 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1824 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1825 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1826 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1827 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1828 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1829 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1830 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1831 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1832 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1833 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1834 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1835 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1836 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1837 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1838 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1839 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1840 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1841 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1842 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1843 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1844 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1845 /* CRC32 instructions. */
823d2571
TG		 1846 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1847 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1848 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1849 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1850 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1851 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1852 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1853 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1854 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1855 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1856 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1857 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1858
ddfded2f
MW		 1859 /* Privileged Access Never extension instructions. */
1860 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1861 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1862
90ec0d68 1863 /* Virtualization Extension instructions. */
823d2571
TG		 1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1866
eea54501 1867 /* Integer Divide Extension instructions. */
823d2571
TG		 1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1869 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1871 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1872
60e5ef9f 1873 /* MP Extension instructions. */
823d2571 1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1875
c597cc3d
SD		 1876 /* Speculation Barriers. */
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1880
62b3e311 1881 /* V7 instructions. */
823d2571
TG		 1882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1890 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1891
c19d1205 1892 /* ARM V6T2 instructions. */
823d2571
TG		 1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1894 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1896 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1898 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1900 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1901
1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1903 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1905 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1906
ff8646ee 1907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1908 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1910 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1912 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1914 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1915
f4c65163 1916 /* ARM Security extension instructions. */
823d2571
TG		 1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1918 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1919
8f06b2d8 1920 /* ARM V6K instructions. */
823d2571
TG		 1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1922 0xf57ff01f, 0xffffffff, "clrex"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1924 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1926 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1928 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1930 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1932 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1934 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1935
7fadb25d
SD		 1936 /* ARMv8.5-A instructions. */
1937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1938
8f06b2d8 1939 /* ARM V6K NOP hints. */
823d2571
TG		 1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1941 0x0320f001, 0x0fffffff, "yield%c"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1943 0x0320f002, 0x0fffffff, "wfe%c"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1945 0x0320f003, 0x0fffffff, "wfi%c"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1947 0x0320f004, 0x0fffffff, "sev%c"},
1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1949 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1950
fe56b6ce 1951 /* ARM V6 instructions. */
823d2571
TG		 1952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1955 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1957 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2137 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2139 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2141 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2143 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2145 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2147 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2149 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2151 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2153 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2155 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2157 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2159 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2161 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2163 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2165 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2167 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2169 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2171 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2173 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2175 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2177 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2179 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2181 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2183 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2185 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2187 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2189 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2191 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2193 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2195 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2196
8f06b2d8 2197 /* V5J instruction. */
823d2571
TG		 2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2199 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2200
8f06b2d8 2201 /* V5 Instructions. */
823d2571
TG		 2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2203 0xe1200070, 0xfff000f0,
2204 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2206 0xfa000000, 0xfe000000, "blx\t%B"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2208 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2210 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2211
2212 /* V5E "El Segundo" Instructions. */
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2214 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2216 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2218 0xf450f000, 0xfc70f000, "pld\t%a"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2220 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2222 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2224 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2226 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2227
2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2229 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2231 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2232
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2234 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2236 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2238 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2240 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2241
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2243 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2245 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2247 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2249 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2250
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2252 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2254 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2255
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2257 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2259 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2261 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2263 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2264
8f06b2d8 2265 /* ARM Instructions. */
823d2571
TG		 2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2268
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2281
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2289 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2290
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2296 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2299
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2303 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2306
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2310 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2313
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2317 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2320
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2324 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2327
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2333 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2334
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2338 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2341
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2348
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2355
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2357 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2359 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2361 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2362
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2369
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2371 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2373 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2375 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2376
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2383
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2390
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2397
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2405 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2407 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2412
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2419
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2426
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2428 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2430 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2431
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2434
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2438 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2439
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2465 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2467 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2469 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2471 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2473 0x092d0000, 0x0fff0000, "push%c\t%m"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2475 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2477 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2478
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2480 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2482 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2484 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2486 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2488 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2490 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2494 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2496 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2498 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2500 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2502 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2504 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2506 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2508 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2510 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2512 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2514 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2516 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2517
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2519 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2521 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2522
2523 /* The rest. */
4ab90a7a
AV		 2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2525 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2527 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2528 {ARM_FEATURE_CORE_LOW (0),
2529 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2530};
2531
2532/* print_insn_thumb16 recognizes the following format control codes:
2533
2534 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2535 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2536 %<bitfield>I print bitfield as a signed decimal
2537 (top bit of range being the sign bit)
2538 %N print Thumb register mask (with LR)
2539 %O print Thumb register mask (with PC)
2540 %M print Thumb register mask
2541 %b print CZB's 6-bit unsigned branch destination
2542 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2543 %c print the condition code
2544 %C print the condition code, or "s" if not conditional
2545 %x print warning if conditional an not at end of IT block"
2546 %X print "\t; unpredictable <IT:code>" if conditional
2547 %I print IT instruction suffix and operands
4547cb56 2548 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2549 %<bitfield>r print bitfield as an ARM register
2550 %<bitfield>d print bitfield as a decimal
2551 %<bitfield>H print (bitfield * 2) as a decimal
2552 %<bitfield>W print (bitfield * 4) as a decimal
2553 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2554 %<bitfield>B print Thumb branch destination (signed displacement)
2555 %<bitfield>c print bitfield as a condition code
2556 %<bitnum>'c print specified char iff bit is one
2557 %<bitnum>?ab print a if bit is one else print b. */
2558
2559static const struct opcode16 thumb_opcodes[] =
2560{
2561 /* Thumb instructions. */
2562
16a1fa25
TP		 2563 /* ARMv8-M Security Extensions instructions. */
2564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 2566
53c4b28b 2567 /* ARM V8 instructions. */
823d2571
TG		 2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2571
8f06b2d8 2572 /* ARM V6K no-argument instructions. */
823d2571
TG		 2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2579
2580 /* ARM V6T2 instructions. */
ff8646ee
TP		 2581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2582 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2584 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2586
2587 /* ARM V6. */
823d2571
TG		 2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2599
2600 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2602 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2603 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2605 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2606 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2608 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2609 /* Format 4. */
823d2571
TG		 2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2626 /* format 13 */
823d2571
TG		 2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2629 /* format 5 */
823d2571
TG		 2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2634 /* format 14 */
823d2571
TG		 2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2637 /* format 2 */
823d2571
TG		 2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2639 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2641 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2643 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2645 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2646 /* format 8 */
823d2571
TG		 2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2648 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2650 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2652 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2653 /* format 7 */
823d2571
TG		 2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2655 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2657 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2658 /* format 1 */
823d2571
TG		 2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2661 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2664 /* format 3 */
823d2571
TG		 2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2669 /* format 6 */
823d2571
TG		 2670 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2672 0x4800, 0xF800,
2673 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2674 /* format 9 */
823d2571
TG		 2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2676 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2678 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2680 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2682 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2683 /* format 10 */
823d2571
TG		 2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2685 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2687 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2688 /* format 11 */
823d2571
TG		 2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2690 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2692 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2693 /* format 12 */
823d2571
TG		 2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2695 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2697 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2698 /* format 15 */
823d2571
TG		 2699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2701 /* format 17 */
823d2571 2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2703 /* format 16 */
823d2571
TG		 2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2707 /* format 18 */
823d2571 2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2709
2710 /* The E800 .. FFFF range is unconditionally redirected to the
2711 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2712 are processed via that table. Thus, we can never encounter a
2713 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2715 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2716};
2717
2718/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2719 We adopt the convention that hw1 is the high 16 bits of .value and
2720 .mask, hw2 the low 16 bits.
2721
2722 print_insn_thumb32 recognizes the following format control codes:
2723
2724 %% %
2725
2726 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2727 %M print a modified 12-bit immediate (same location)
2728 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2729 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2730 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2731 %S print a possibly-shifted Rm
2732
32a94698 2733 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2734 %a print the address of a plain load/store
2735 %w print the width and signedness of a core load/store
2736 %m print register mask for ldm/stm
4b5a202f 2737 %n print register mask for clrm
8f06b2d8
PB		 2738
2739 %E print the lsb and width fields of a bfc/bfi instruction
2740 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 2741 %G print a fallback offset for Branch Future instructions
e5d6e09e 2742 %W print an offset for BF instruction
1caf72a5 2743 %Y print an offset for BFL instruction
1889da70 2744 %Z print an offset for BFCSEL instruction
60f993ce
AV		 2745 %Q print an offset for Low Overhead Loop instructions
2746 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 2747 %b print a conditional branch offset
2748 %B print an unconditional branch offset
2749 %s print the shift field of an SSAT instruction
2750 %R print the rotation field of an SXT instruction
62b3e311
PB		 2751 %U print barrier type.
2752 %P print address for pli instruction.
c22aaad1
PB		 2753 %c print the condition code
2754 %x print warning if conditional an not at end of IT block"
2755 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2756
2757 %<bitfield>d print bitfield in decimal
f0fba320 2758 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2759 %<bitfield>W print bitfield*4 in decimal
2760 %<bitfield>r print bitfield as an ARM register
dd5181d5 2761 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 2762 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 2763 %<bitfield>c print bitfield as a condition code
2764
16980d0b
JB		 2765 %<bitfield>'c print specified char iff bitfield is all ones
2766 %<bitfield>`c print specified char iff bitfield is all zeroes
2767 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2768
2769 With one exception at the bottom (done because BL and BLX(1) need
2770 to come dead last), this table was machine-sorted first in
2771 decreasing order of number of bits set in the mask, then in
2772 increasing numeric order of mask, then in increasing numeric order
2773 of opcode. This order is not the clearest for a human reader, but
2774 is guaranteed never to catch a special-case bit pattern with a more
2775 general mask, which is important, because this instruction encoding
2776 makes heavy use of special-case bit patterns. */
2777static const struct opcode32 thumb32_opcodes[] =
2778{
4b5a202f
AV		 2779 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
2780 instructions. */
60f993ce
AV		 2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2782 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
2783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2784 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
2785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2786 0xf02fc001, 0xfffff001, "le\t%P"},
2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2788 0xf00fc001, 0xfffff001, "le\tlr, %P"},
2789
4389b29a
AV		 2790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2791 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 2792 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2793 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 2794 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2795 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 2796 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2797 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 2798 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2799 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 2800
4b5a202f
AV		 2801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2802 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 2803
16a1fa25
TP		 2804 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2806 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2807 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2808 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2809 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2811 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2813 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2814
105bde57 2815 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2816 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2817 0xf3af8010, 0xffffffff, "esb"},
2818
53c4b28b 2819 /* V8 instructions. */
823d2571
TG		 2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2821 0xf3af8005, 0xffffffff, "sevl%c.w"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2823 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2825 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2827 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2829 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2831 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2833 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2835 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2837 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2839 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2841 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2843 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2845 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2847 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2849 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2851 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2852
dd5181d5 2853 /* CRC32 instructions. */
823d2571 2854 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2855 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 2856 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2857 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 2858 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2859 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 2860 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2861 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 2862 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2863 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 2864 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2865 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 2866
c597cc3d
SD		 2867 /* Speculation Barriers. */
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2871
62b3e311 2872 /* V7 instructions. */
823d2571
TG		 2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2881 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2883 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2884
90ec0d68 2885 /* Virtualization Extension instructions. */
823d2571 2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2887 /* We skip ERET as that is SUBS pc, lr, #0. */
2888
60e5ef9f 2889 /* MP Extension instructions. */
823d2571 2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2891
f4c65163 2892 /* Security extension instructions. */
823d2571 2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2894
7fadb25d
SD		 2895 /* ARMv8.5-A instructions. */
2896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2897
8f06b2d8 2898 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2907
ff8646ee 2908 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2909 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2937 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2938 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2939 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2957 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3064 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3065 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3067 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3109 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3133 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139 0xf810f000, 0xff70f000, "pld%c\t%a"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165 0xfb100000, 0xfff000c0,
3166 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168 0xfbc00080, 0xfff000c0,
3169 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3173 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3175 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3181 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3184 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3185 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3191 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3197 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3199 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3201 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3206 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3207 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3209 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3211 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3213 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3215 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3217 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3219 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3221 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3223 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3225 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3227 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3229 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3231 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3233 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3235 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3237 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3239 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3241 0xe9400000, 0xff500000,
3242 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3244 0xe9500000, 0xff500000,
3245 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3247 0xe8600000, 0xff700000,
3248 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3250 0xe8700000, 0xff700000,
3251 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3253 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3255 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3256
3257 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3259 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3261 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3263 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3265 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3266
8f06b2d8 3267 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3269 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3271 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3272
3273 /* Fallback. */
823d2571
TG		 3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3275 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3276 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3277};
ff4a8d2b 3278
8f06b2d8
PB		 3279static const char *const arm_conditional[] =
3280{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3281 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3282
3283static const char *const arm_fp_const[] =
3284{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3285
3286static const char *const arm_shift[] =
3287{"lsl", "lsr", "asr", "ror"};
3288
3289typedef struct
3290{
3291 const char *name;
3292 const char *description;
3293 const char *reg_names[16];
3294}
3295arm_regname;
3296
3297static const arm_regname regnames[] =
3298{
65b48a81 3299 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3300 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3301 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3302 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3303 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3304 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3305 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3306 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3307 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3308 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3309 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3310 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3311 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3312 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3313};
3314
3315static const char *const iwmmxt_wwnames[] =
3316{"b", "h", "w", "d"};
3317
3318static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3319{"b", "bus", "bc", "bss",
3320 "h", "hus", "hc", "hss",
3321 "w", "wus", "wc", "wss",
3322 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3323};
3324
3325static const char *const iwmmxt_regnames[] =
3326{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3327 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3328};
3329
3330static const char *const iwmmxt_cregnames[] =
3331{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3332 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3333};
3334
3335/* Default to GCC register name set. */
3336static unsigned int regname_selected = 1;
3337
65b48a81 3338#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3339#define arm_regnames regnames[regname_selected].reg_names
3340
3341static bfd_boolean force_thumb = FALSE;
3342
c22aaad1
PB		 3343/* Current IT instruction state. This contains the same state as the IT
3344 bits in the CPSR. */
3345static unsigned int ifthen_state;
3346/* IT state for the next instruction. */
3347static unsigned int ifthen_next_state;
3348/* The address of the insn for which the IT state is valid. */
3349static bfd_vma ifthen_address;
3350#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3351/* Indicates that the current Conditional state is unconditional or outside
3352 an IT block. */
3353#define COND_UNCOND 16
c22aaad1 3354
8f06b2d8
PB		 3355\f
3356/* Functions. */
8f06b2d8 3357
16980d0b
JB		 3358/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3359 Returns pointer to following character of the format string and
3360 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3361 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3362
3363static const char *
fe56b6ce
NC		 3364arm_decode_bitfield (const char *ptr,
3365 unsigned long insn,
3366 unsigned long *valuep,
3367 int *widthp)
16980d0b
JB		 3368{
3369 unsigned long value = 0;
3370 int width = 0;
43e65147
L		 3371
3372 do
16980d0b
JB		 3373 {
3374 int start, end;
3375 int bits;
3376
3377 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3378 start = start * 10 + *ptr - '0';
3379 if (*ptr == '-')
3380 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3381 end = end * 10 + *ptr - '0';
3382 else
3383 end = start;
3384 bits = end - start;
3385 if (bits < 0)
3386 abort ();
3387 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3388 width += bits + 1;
3389 }
3390 while (*ptr++ == ',');
3391 *valuep = value;
3392 if (widthp)
3393 *widthp = width;
3394 return ptr - 1;
3395}
3396
8f06b2d8 3397static void
37b37b2d 3398arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3399 bfd_boolean print_shift)
8f06b2d8
PB		 3400{
3401 func (stream, "%s", arm_regnames[given & 0xf]);
3402
3403 if ((given & 0xff0) != 0)
3404 {
3405 if ((given & 0x10) == 0)
3406 {
3407 int amount = (given & 0xf80) >> 7;
3408 int shift = (given & 0x60) >> 5;
3409
3410 if (amount == 0)
3411 {
3412 if (shift == 3)
3413 {
3414 func (stream, ", rrx");
3415 return;
3416 }
3417
3418 amount = 32;
3419 }
3420
37b37b2d
RE		 3421 if (print_shift)
3422 func (stream, ", %s #%d", arm_shift[shift], amount);
3423 else
3424 func (stream, ", #%d", amount);
8f06b2d8 3425 }
74bdfecf 3426 else if ((given & 0x80) == 0x80)
aefd8a40 3427 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3428 else if (print_shift)
8f06b2d8
PB		 3429 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3430 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3431 else
3432 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3433 }
3434}
3435
c1e26897
NC		 3436#define W_BIT 21
3437#define I_BIT 22
3438#define U_BIT 23
3439#define P_BIT 24
3440
3441#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3442#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3443#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3444#define PRE_BIT_SET (given & (1 << P_BIT))
3445
8f06b2d8
PB		 3446/* Print one coprocessor instruction on INFO->STREAM.
3447 Return TRUE if the instuction matched, FALSE if this is not a
3448 recognised coprocessor instruction. */
3449
3450static bfd_boolean
fe56b6ce
NC		 3451print_insn_coprocessor (bfd_vma pc,
3452 struct disassemble_info *info,
3453 long given,
8f06b2d8
PB		 3454 bfd_boolean thumb)
3455{
6b0dd094 3456 const struct sopcode32 *insn;
8f06b2d8
PB		 3457 void *stream = info->stream;
3458 fprintf_ftype func = info->fprintf_func;
3459 unsigned long mask;
2edcd244 3460 unsigned long value = 0;
c22aaad1 3461 int cond;
8afc7bea 3462 int cp_num;
823d2571
TG		 3463 struct arm_private_data *private_data = info->private_data;
3464 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3465
5b616bef 3466 allowed_arches = private_data->features;
8f06b2d8
PB		 3467
3468 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3469 {
ff4a8d2b
NC		 3470 unsigned long u_reg = 16;
3471 bfd_boolean is_unpredictable = FALSE;
05413229 3472 signed long value_in_comment = 0;
0313a2b8
NC		 3473 const char *c;
3474
823d2571 3475 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3476 switch (insn->value)
3477 {
3478 case SENTINEL_IWMMXT_START:
3479 if (info->mach != bfd_mach_arm_XScale
3480 && info->mach != bfd_mach_arm_iWMMXt
3481 && info->mach != bfd_mach_arm_iWMMXt2)
3482 do
3483 insn++;
823d2571
TG		 3484 while ((! ARM_FEATURE_ZERO (insn->arch))
3485 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3486 continue;
3487
3488 case SENTINEL_IWMMXT_END:
3489 continue;
3490
3491 case SENTINEL_GENERIC_START:
5b616bef 3492 allowed_arches = private_data->features;
05413229
NC		 3493 continue;
3494
3495 default:
3496 abort ();
3497 }
8f06b2d8
PB		 3498
3499 mask = insn->mask;
3500 value = insn->value;
8afc7bea
RL		 3501 cp_num = (given >> 8) & 0xf;
3502
8f06b2d8
PB		 3503 if (thumb)
3504 {
3505 /* The high 4 bits are 0xe for Arm conditional instructions, and
3506 0xe for arm unconditional instructions. The rest of the
3507 encoding is the same. */
3508 mask |= 0xf0000000;
3509 value |= 0xe0000000;
c22aaad1
PB		 3510 if (ifthen_state)
3511 cond = IFTHEN_COND;
3512 else
e2efe87d 3513 cond = COND_UNCOND;
8f06b2d8
PB		 3514 }
3515 else
3516 {
3517 /* Only match unconditional instuctions against unconditional
3518 patterns. */
3519 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3520 {
3521 mask |= 0xf0000000;
e2efe87d 3522 cond = COND_UNCOND;
c22aaad1
PB		 3523 }
3524 else
3525 {
3526 cond = (given >> 28) & 0xf;
3527 if (cond == 0xe)
e2efe87d 3528 cond = COND_UNCOND;
c22aaad1 3529 }
8f06b2d8 3530 }
823d2571 3531
6b0dd094
AV		 3532 if ((insn->isa == T32 && !thumb)
3533 || (insn->isa == ARM && thumb))
3534 continue;
3535
0313a2b8
NC		 3536 if ((given & mask) != value)
3537 continue;
8f06b2d8 3538
823d2571 3539 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3540 continue;
3541
8afc7bea
RL		 3542 if (insn->value == 0xfe000010 /* mcr2 */
3543 || insn->value == 0xfe100010 /* mrc2 */
3544 || insn->value == 0xfc100000 /* ldc2 */
3545 || insn->value == 0xfc000000) /* stc2 */
3546 {
b0c11777 3547 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3548 is_unpredictable = TRUE;
3549 }
3550 else if (insn->value == 0x0e000000 /* cdp */
3551 || insn->value == 0xfe000000 /* cdp2 */
3552 || insn->value == 0x0e000010 /* mcr */
3553 || insn->value == 0x0e100010 /* mrc */
3554 || insn->value == 0x0c100000 /* ldc */
3555 || insn->value == 0x0c000000) /* stc */
3556 {
3557 /* Floating-point instructions. */
b0c11777 3558 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3559 continue;
3560 }
3561
0313a2b8
NC		 3562 for (c = insn->assembler; *c; c++)
3563 {
3564 if (*c == '%')
8f06b2d8 3565 {
0313a2b8 3566 switch (*++c)
8f06b2d8 3567 {
0313a2b8
NC		 3568 case '%':
3569 func (stream, "%%");
3570 break;
3571
3572 case 'A':
05413229 3573 {
79862e45 3574 int rn = (given >> 16) & 0xf;
b0c11777 3575 bfd_vma offset = given & 0xff;
0313a2b8 3576
05413229 3577 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3578
79862e45
DJ		 3579 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3580 {
3581 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3582 if (cp_num == 9)
3583 /* vldr.16/vstr.16 will shift the address
3584 left by 1 bit only. */
3585 offset = offset * 2;
3586 else
3587 offset = offset * 4;
3588
79862e45
DJ		 3589 if (NEGATIVE_BIT_SET)
3590 offset = - offset;
3591 if (rn != 15)
3592 value_in_comment = offset;
3593 }
3594
c1e26897 3595 if (PRE_BIT_SET)
05413229
NC		 3596 {
3597 if (offset)
fe56b6ce 3598 func (stream, ", #%d]%s",
d908c8af 3599 (int) offset,
c1e26897 3600 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3601 else if (NEGATIVE_BIT_SET)
3602 func (stream, ", #-0]");
05413229
NC		 3603 else
3604 func (stream, "]");
3605 }
3606 else
3607 {
0313a2b8 3608 func (stream, "]");
8f06b2d8 3609
c1e26897 3610 if (WRITEBACK_BIT_SET)
05413229
NC		 3611 {
3612 if (offset)
d908c8af 3613 func (stream, ", #%d", (int) offset);
26d97720
NS		 3614 else if (NEGATIVE_BIT_SET)
3615 func (stream, ", #-0");
05413229
NC		 3616 }
3617 else
fe56b6ce 3618 {
26d97720
NS		 3619 func (stream, ", {%s%d}",
3620 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3621 (int) offset);
fe56b6ce
NC		 3622 value_in_comment = offset;
3623 }
05413229 3624 }
79862e45
DJ		 3625 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3626 {
3627 func (stream, "\t; ");
6844b2c2
MGD		 3628 /* For unaligned PCs, apply off-by-alignment
3629 correction. */
43e65147 3630 info->print_address_func (offset + pc
6844b2c2
MGD		 3631 + info->bytes_per_chunk * 2
3632 - (pc & 3),
dffaa15c 3633 info);
79862e45 3634 }
05413229 3635 }
0313a2b8 3636 break;
8f06b2d8 3637
0313a2b8
NC		 3638 case 'B':
3639 {
3640 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3641 int offset = (given >> 1) & 0x3f;
3642
3643 if (offset == 1)
3644 func (stream, "{d%d}", regno);
3645 else if (regno + offset > 32)
3646 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3647 else
3648 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3649 }
3650 break;
8f06b2d8 3651
efd6b359
AV		 3652 case 'C':
3653 {
3654 bfd_boolean single = ((given >> 8) & 1) == 0;
3655 char reg_prefix = single ? 's' : 'd';
3656 int Dreg = (given >> 22) & 0x1;
3657 int Vdreg = (given >> 12) & 0xf;
3658 int reg = single ? ((Vdreg << 1) | Dreg)
3659 : ((Dreg << 4) | Vdreg);
3660 int num = (given >> (single ? 0 : 1)) & 0x7f;
3661 int maxreg = single ? 31 : 15;
3662 int topreg = reg + num - 1;
3663
3664 if (!num)
3665 func (stream, "{VPR}");
3666 else if (num == 1)
3667 func (stream, "{%c%d, VPR}", reg_prefix, reg);
3668 else if (topreg > maxreg)
3669 func (stream, "{%c%d-<overflow reg d%d, VPR}",
3670 reg_prefix, reg, single ? topreg >> 1 : topreg);
3671 else
3672 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
3673 reg_prefix, topreg);
3674 }
3675 break;
3676
e2efe87d
MGD		 3677 case 'u':
3678 if (cond != COND_UNCOND)
3679 is_unpredictable = TRUE;
3680
3681 /* Fall through. */
0313a2b8 3682 case 'c':
b0c11777
RL		 3683 if (cond != COND_UNCOND && cp_num == 9)
3684 is_unpredictable = TRUE;
3685
0313a2b8
NC		 3686 func (stream, "%s", arm_conditional[cond]);
3687 break;
8f06b2d8 3688
0313a2b8
NC		 3689 case 'I':
3690 /* Print a Cirrus/DSP shift immediate. */
3691 /* Immediates are 7bit signed ints with bits 0..3 in
3692 bits 0..3 of opcode and bits 4..6 in bits 5..7
3693 of opcode. */
3694 {
3695 int imm;
8f06b2d8 3696
0313a2b8 3697 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3698
0313a2b8
NC		 3699 /* Is ``imm'' a negative number? */
3700 if (imm & 0x40)
24b4cf66 3701 imm -= 0x80;
8f06b2d8 3702
0313a2b8
NC		 3703 func (stream, "%d", imm);
3704 }
3705
3706 break;
8f06b2d8 3707
0313a2b8
NC		 3708 case 'F':
3709 switch (given & 0x00408000)
3710 {
3711 case 0:
3712 func (stream, "4");
3713 break;
3714 case 0x8000:
3715 func (stream, "1");
3716 break;
3717 case 0x00400000:
3718 func (stream, "2");
8f06b2d8 3719 break;
0313a2b8
NC		 3720 default:
3721 func (stream, "3");
3722 }
3723 break;
8f06b2d8 3724
0313a2b8
NC		 3725 case 'P':
3726 switch (given & 0x00080080)
3727 {
3728 case 0:
3729 func (stream, "s");
3730 break;
3731 case 0x80:
3732 func (stream, "d");
3733 break;
3734 case 0x00080000:
3735 func (stream, "e");
3736 break;
3737 default:
3738 func (stream, _("<illegal precision>"));
8f06b2d8 3739 break;
0313a2b8
NC		 3740 }
3741 break;
8f06b2d8 3742
0313a2b8
NC		 3743 case 'Q':
3744 switch (given & 0x00408000)
3745 {
3746 case 0:
3747 func (stream, "s");
8f06b2d8 3748 break;
0313a2b8
NC		 3749 case 0x8000:
3750 func (stream, "d");
8f06b2d8 3751 break;
0313a2b8
NC		 3752 case 0x00400000:
3753 func (stream, "e");
3754 break;
3755 default:
3756 func (stream, "p");
8f06b2d8 3757 break;
0313a2b8
NC		 3758 }
3759 break;
8f06b2d8 3760
0313a2b8
NC		 3761 case 'R':
3762 switch (given & 0x60)
3763 {
3764 case 0:
3765 break;
3766 case 0x20:
3767 func (stream, "p");
3768 break;
3769 case 0x40:
3770 func (stream, "m");
3771 break;
3772 default:
3773 func (stream, "z");
3774 break;
3775 }
3776 break;
16980d0b 3777
0313a2b8
NC		 3778 case '0': case '1': case '2': case '3': case '4':
3779 case '5': case '6': case '7': case '8': case '9':
3780 {
3781 int width;
8f06b2d8 3782
0313a2b8 3783 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3784
0313a2b8
NC		 3785 switch (*c)
3786 {
ff4a8d2b
NC		 3787 case 'R':
3788 if (value == 15)
3789 is_unpredictable = TRUE;
3790 /* Fall through. */
0313a2b8 3791 case 'r':
ff4a8d2b
NC		 3792 if (c[1] == 'u')
3793 {
3794 /* Eat the 'u' character. */
3795 ++ c;
3796
3797 if (u_reg == value)
3798 is_unpredictable = TRUE;
3799 u_reg = value;
3800 }
0313a2b8
NC		 3801 func (stream, "%s", arm_regnames[value]);
3802 break;
c28eeff2
SN		 3803 case 'V':
3804 if (given & (1 << 6))
3805 goto Q;
3806 /* FALLTHROUGH */
0313a2b8
NC		 3807 case 'D':
3808 func (stream, "d%ld", value);
3809 break;
3810 case 'Q':
c28eeff2 3811 Q:
0313a2b8
NC		 3812 if (value & 1)
3813 func (stream, "<illegal reg q%ld.5>", value >> 1);
3814 else
3815 func (stream, "q%ld", value >> 1);
3816 break;
3817 case 'd':
3818 func (stream, "%ld", value);
05413229 3819 value_in_comment = value;
0313a2b8 3820 break;
6f1c2142
AM		 3821 case 'E':
3822 {
3823 /* Converts immediate 8 bit back to float value. */
3824 unsigned floatVal = (value & 0x80) << 24
3825 | (value & 0x3F) << 19
3826 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3827
3828 /* Quarter float have a maximum value of 31.0.
3829 Get floating point value multiplied by 1e7.
3830 The maximum value stays in limit of a 32-bit int. */
3831 unsigned decVal =
3832 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3833 (16 + (value & 0xF));
3834
3835 if (!(decVal % 1000000))
3836 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3837 floatVal, value & 0x80 ? '-' : ' ',
3838 decVal / 10000000,
3839 decVal % 10000000 / 1000000);
3840 else if (!(decVal % 10000))
3841 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3842 floatVal, value & 0x80 ? '-' : ' ',
3843 decVal / 10000000,
3844 decVal % 10000000 / 10000);
3845 else
3846 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3847 floatVal, value & 0x80 ? '-' : ' ',
3848 decVal / 10000000, decVal % 10000000);
3849 break;
3850 }
0313a2b8
NC		 3851 case 'k':
3852 {
3853 int from = (given & (1 << 7)) ? 32 : 16;
3854 func (stream, "%ld", from - value);
3855 }
3856 break;
8f06b2d8 3857
0313a2b8
NC		 3858 case 'f':
3859 if (value > 7)
3860 func (stream, "#%s", arm_fp_const[value & 7]);
3861 else
3862 func (stream, "f%ld", value);
3863 break;
4146fd53 3864
0313a2b8
NC		 3865 case 'w':
3866 if (width == 2)
3867 func (stream, "%s", iwmmxt_wwnames[value]);
3868 else
3869 func (stream, "%s", iwmmxt_wwssnames[value]);
3870 break;
4146fd53 3871
0313a2b8
NC		 3872 case 'g':
3873 func (stream, "%s", iwmmxt_regnames[value]);
3874 break;
3875 case 'G':
3876 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3877 break;
8f06b2d8 3878
0313a2b8 3879 case 'x':
d1aaab3c 3880 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3881 break;
8f06b2d8 3882
33399f07
MGD		 3883 case 'c':
3884 switch (value)
3885 {
3886 case 0:
3887 func (stream, "eq");
3888 break;
3889
3890 case 1:
3891 func (stream, "vs");
3892 break;
3893
3894 case 2:
3895 func (stream, "ge");
3896 break;
3897
3898 case 3:
3899 func (stream, "gt");
3900 break;
3901
3902 default:
3903 func (stream, "??");
3904 break;
3905 }
3906 break;
3907
0313a2b8
NC		 3908 case '`':
3909 c++;
3910 if (value == 0)
3911 func (stream, "%c", *c);
3912 break;
3913 case '\'':
3914 c++;
3915 if (value == ((1ul << width) - 1))
3916 func (stream, "%c", *c);
3917 break;
3918 case '?':
fe56b6ce 3919 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3920 c += 1 << width;
3921 break;
3922 default:
3923 abort ();
3924 }
dffaa15c
AM		 3925 }
3926 break;
0313a2b8 3927
dffaa15c
AM		 3928 case 'y':
3929 case 'z':
3930 {
3931 int single = *c++ == 'y';
3932 int regno;
8f06b2d8 3933
dffaa15c
AM		 3934 switch (*c)
3935 {
3936 case '4': /* Sm pair */
3937 case '0': /* Sm, Dm */
3938 regno = given & 0x0000000f;
3939 if (single)
3940 {
3941 regno <<= 1;
3942 regno += (given >> 5) & 1;
3943 }
3944 else
3945 regno += ((given >> 5) & 1) << 4;
3946 break;
8f06b2d8 3947
dffaa15c
AM		 3948 case '1': /* Sd, Dd */
3949 regno = (given >> 12) & 0x0000000f;
3950 if (single)
3951 {
3952 regno <<= 1;
3953 regno += (given >> 22) & 1;
3954 }
3955 else
3956 regno += ((given >> 22) & 1) << 4;
3957 break;
7df76b80 3958
dffaa15c
AM		 3959 case '2': /* Sn, Dn */
3960 regno = (given >> 16) & 0x0000000f;
3961 if (single)
3962 {
3963 regno <<= 1;
3964 regno += (given >> 7) & 1;
3965 }
3966 else
3967 regno += ((given >> 7) & 1) << 4;
3968 break;
a7f8487e 3969
dffaa15c
AM		 3970 case '3': /* List */
3971 func (stream, "{");
3972 regno = (given >> 12) & 0x0000000f;
3973 if (single)
3974 {
3975 regno <<= 1;
3976 regno += (given >> 22) & 1;
3977 }
3978 else
3979 regno += ((given >> 22) & 1) << 4;
3980 break;
a7f8487e 3981
dffaa15c
AM		 3982 default:
3983 abort ();
3984 }
0313a2b8 3985
dffaa15c 3986 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 3987
dffaa15c
AM		 3988 if (*c == '3')
3989 {
3990 int count = given & 0xff;
b34976b6 3991
dffaa15c
AM		 3992 if (single == 0)
3993 count >>= 1;
0313a2b8 3994
dffaa15c
AM		 3995 if (--count)
3996 {
3997 func (stream, "-%c%d",
3998 single ? 's' : 'd',
3999 regno + count);
4000 }
0313a2b8 4001
dffaa15c 4002 func (stream, "}");
0313a2b8 4003 }
dffaa15c
AM		 4004 else if (*c == '4')
4005 func (stream, ", %c%d", single ? 's' : 'd',
4006 regno + 1);
4007 }
4008 break;
b34976b6 4009
dffaa15c
AM		 4010 case 'L':
4011 switch (given & 0x00400100)
0313a2b8 4012 {
dffaa15c
AM		 4013 case 0x00000000: func (stream, "b"); break;
4014 case 0x00400000: func (stream, "h"); break;
4015 case 0x00000100: func (stream, "w"); break;
4016 case 0x00400100: func (stream, "d"); break;
4017 default:
4018 break;
0313a2b8 4019 }
dffaa15c 4020 break;
2d447fca 4021
dffaa15c
AM		 4022 case 'Z':
4023 {
4024 /* given (20, 23) | given (0, 3) */
4025 value = ((given >> 16) & 0xf0) | (given & 0xf);
4026 func (stream, "%d", (int) value);
4027 }
4028 break;
0313a2b8 4029
dffaa15c
AM		 4030 case 'l':
4031 /* This is like the 'A' operator, except that if
4032 the width field "M" is zero, then the offset is
4033 *not* multiplied by four. */
4034 {
4035 int offset = given & 0xff;
4036 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 4037
dffaa15c 4038 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 4039
dffaa15c
AM		 4040 if (multiplier > 1)
4041 {
4042 value_in_comment = offset * multiplier;
4043 if (NEGATIVE_BIT_SET)
4044 value_in_comment = - value_in_comment;
4045 }
0313a2b8 4046
dffaa15c
AM		 4047 if (offset)
4048 {
4049 if (PRE_BIT_SET)
4050 func (stream, ", #%s%d]%s",
4051 NEGATIVE_BIT_SET ? "-" : "",
4052 offset * multiplier,
4053 WRITEBACK_BIT_SET ? "!" : "");
4054 else
4055 func (stream, "], #%s%d",
4056 NEGATIVE_BIT_SET ? "-" : "",
4057 offset * multiplier);
4058 }
4059 else
4060 func (stream, "]");
4061 }
4062 break;
2d447fca 4063
dffaa15c
AM		 4064 case 'r':
4065 {
4066 int imm4 = (given >> 4) & 0xf;
4067 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
4068 int ubit = ! NEGATIVE_BIT_SET;
4069 const char *rm = arm_regnames [given & 0xf];
4070 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 4071
dffaa15c
AM		 4072 switch (puw_bits)
4073 {
4074 case 1:
4075 case 3:
4076 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
4077 if (imm4)
4078 func (stream, ", lsl #%d", imm4);
4079 break;
0313a2b8 4080
dffaa15c
AM		 4081 case 4:
4082 case 5:
4083 case 6:
4084 case 7:
4085 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
4086 if (imm4 > 0)
4087 func (stream, ", lsl #%d", imm4);
4088 func (stream, "]");
4089 if (puw_bits == 5 || puw_bits == 7)
4090 func (stream, "!");
4091 break;
2d447fca 4092
dffaa15c
AM		 4093 default:
4094 func (stream, "INVALID");
4095 }
4096 }
4097 break;
0313a2b8 4098
dffaa15c
AM		 4099 case 'i':
4100 {
4101 long imm5;
4102 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4103 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 4104 }
dffaa15c
AM		 4105 break;
4106
4107 default:
4108 abort ();
252b5132 4109 }
252b5132 4110 }
0313a2b8
NC		 4111 else
4112 func (stream, "%c", *c);
252b5132 4113 }
05413229
NC		 4114
4115 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4116 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 4117
ff4a8d2b
NC		 4118 if (is_unpredictable)
4119 func (stream, UNPREDICTABLE_INSTRUCTION);
4120
0313a2b8 4121 return TRUE;
252b5132 4122 }
8f06b2d8 4123 return FALSE;
252b5132
RH		 4124}
4125
05413229
NC		 4126/* Decodes and prints ARM addressing modes. Returns the offset
4127 used in the address, if any, if it is worthwhile printing the
4128 offset as a hexadecimal value in a comment at the end of the
4129 line of disassembly. */
4130
4131static signed long
62b3e311
PB		 4132print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4133{
4134 void *stream = info->stream;
4135 fprintf_ftype func = info->fprintf_func;
f8b960bc 4136 bfd_vma offset = 0;
62b3e311
PB		 4137
4138 if (((given & 0x000f0000) == 0x000f0000)
4139 && ((given & 0x02000000) == 0))
4140 {
05413229 4141 offset = given & 0xfff;
62b3e311
PB		 4142
4143 func (stream, "[pc");
4144
c1e26897 4145 if (PRE_BIT_SET)
62b3e311 4146 {
26d97720
NS		 4147 /* Pre-indexed. Elide offset of positive zero when
4148 non-writeback. */
4149 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4150 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4151
4152 if (NEGATIVE_BIT_SET)
4153 offset = -offset;
62b3e311
PB		 4154
4155 offset += pc + 8;
4156
4157 /* Cope with the possibility of write-back
4158 being used. Probably a very dangerous thing
4159 for the programmer to do, but who are we to
4160 argue ? */
26d97720 4161 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4162 }
c1e26897 4163 else /* Post indexed. */
62b3e311 4164 {
d908c8af 4165 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4166
c1e26897 4167 /* Ie ignore the offset. */
62b3e311
PB		 4168 offset = pc + 8;
4169 }
4170
4171 func (stream, "\t; ");
4172 info->print_address_func (offset, info);
05413229 4173 offset = 0;
62b3e311
PB		 4174 }
4175 else
4176 {
4177 func (stream, "[%s",
4178 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4179
4180 if (PRE_BIT_SET)
62b3e311
PB		 4181 {
4182 if ((given & 0x02000000) == 0)
4183 {
26d97720 4184 /* Elide offset of positive zero when non-writeback. */
05413229 4185 offset = given & 0xfff;
26d97720 4186 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4187 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4188 }
4189 else
4190 {
26d97720 4191 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4192 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4193 }
4194
4195 func (stream, "]%s",
c1e26897 4196 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4197 }
4198 else
4199 {
4200 if ((given & 0x02000000) == 0)
4201 {
26d97720 4202 /* Always show offset. */
05413229 4203 offset = given & 0xfff;
26d97720 4204 func (stream, "], #%s%d",
d908c8af 4205 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4206 }
4207 else
4208 {
4209 func (stream, "], %s",
c1e26897 4210 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4211 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4212 }
4213 }
84919466
MR		 4214 if (NEGATIVE_BIT_SET)
4215 offset = -offset;
62b3e311 4216 }
05413229
NC		 4217
4218 return (signed long) offset;
62b3e311
PB		 4219}
4220
16980d0b
JB		 4221/* Print one neon instruction on INFO->STREAM.
4222 Return TRUE if the instuction matched, FALSE if this is not a
4223 recognised neon instruction. */
4224
4225static bfd_boolean
4226print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4227{
4228 const struct opcode32 *insn;
4229 void *stream = info->stream;
4230 fprintf_ftype func = info->fprintf_func;
4231
4232 if (thumb)
4233 {
4234 if ((given & 0xef000000) == 0xef000000)
4235 {
0313a2b8 4236 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4237 unsigned long bit28 = given & (1 << 28);
4238
4239 given &= 0x00ffffff;
4240 if (bit28)
4241 given |= 0xf3000000;
4242 else
4243 given |= 0xf2000000;
4244 }
4245 else if ((given & 0xff000000) == 0xf9000000)
4246 given ^= 0xf9000000 ^ 0xf4000000;
4247 else
4248 return FALSE;
4249 }
43e65147 4250
16980d0b
JB		 4251 for (insn = neon_opcodes; insn->assembler; insn++)
4252 {
4253 if ((given & insn->mask) == insn->value)
4254 {
05413229 4255 signed long value_in_comment = 0;
e2efe87d 4256 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4257 const char *c;
4258
4259 for (c = insn->assembler; *c; c++)
4260 {
4261 if (*c == '%')
4262 {
4263 switch (*++c)
4264 {
4265 case '%':
4266 func (stream, "%%");
4267 break;
4268
e2efe87d
MGD		 4269 case 'u':
4270 if (thumb && ifthen_state)
4271 is_unpredictable = TRUE;
4272
4273 /* Fall through. */
c22aaad1
PB		 4274 case 'c':
4275 if (thumb && ifthen_state)
4276 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4277 break;
4278
16980d0b
JB		 4279 case 'A':
4280 {
43e65147 4281 static const unsigned char enc[16] =
16980d0b
JB		 4282 {
4283 0x4, 0x14, /* st4 0,1 */
4284 0x4, /* st1 2 */
4285 0x4, /* st2 3 */
4286 0x3, /* st3 4 */
4287 0x13, /* st3 5 */
4288 0x3, /* st1 6 */
4289 0x1, /* st1 7 */
4290 0x2, /* st2 8 */
4291 0x12, /* st2 9 */
4292 0x2, /* st1 10 */
4293 0, 0, 0, 0, 0
4294 };
4295 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4296 int rn = ((given >> 16) & 0xf);
4297 int rm = ((given >> 0) & 0xf);
4298 int align = ((given >> 4) & 0x3);
4299 int type = ((given >> 8) & 0xf);
4300 int n = enc[type] & 0xf;
4301 int stride = (enc[type] >> 4) + 1;
4302 int ix;
43e65147 4303
16980d0b
JB		 4304 func (stream, "{");
4305 if (stride > 1)
4306 for (ix = 0; ix != n; ix++)
4307 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4308 else if (n == 1)
4309 func (stream, "d%d", rd);
4310 else
4311 func (stream, "d%d-d%d", rd, rd + n - 1);
4312 func (stream, "}, [%s", arm_regnames[rn]);
4313 if (align)
8e560766 4314 func (stream, " :%d", 32 << align);
16980d0b
JB		 4315 func (stream, "]");
4316 if (rm == 0xd)
4317 func (stream, "!");
4318 else if (rm != 0xf)
4319 func (stream, ", %s", arm_regnames[rm]);
4320 }
4321 break;
43e65147 4322
16980d0b
JB		 4323 case 'B':
4324 {
4325 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4326 int rn = ((given >> 16) & 0xf);
4327 int rm = ((given >> 0) & 0xf);
4328 int idx_align = ((given >> 4) & 0xf);
4329 int align = 0;
4330 int size = ((given >> 10) & 0x3);
4331 int idx = idx_align >> (size + 1);
4332 int length = ((given >> 8) & 3) + 1;
4333 int stride = 1;
4334 int i;
4335
4336 if (length > 1 && size > 0)
4337 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4338
16980d0b
JB		 4339 switch (length)
4340 {
4341 case 1:
4342 {
4343 int amask = (1 << size) - 1;
4344 if ((idx_align & (1 << size)) != 0)
4345 return FALSE;
4346 if (size > 0)
4347 {
4348 if ((idx_align & amask) == amask)
4349 align = 8 << size;
4350 else if ((idx_align & amask) != 0)
4351 return FALSE;
4352 }
4353 }
4354 break;
43e65147 4355
16980d0b
JB		 4356 case 2:
4357 if (size == 2 && (idx_align & 2) != 0)
4358 return FALSE;
4359 align = (idx_align & 1) ? 16 << size : 0;
4360 break;
43e65147 4361
16980d0b
JB		 4362 case 3:
4363 if ((size == 2 && (idx_align & 3) != 0)
4364 || (idx_align & 1) != 0)
4365 return FALSE;
4366 break;
43e65147 4367
16980d0b
JB		 4368 case 4:
4369 if (size == 2)
4370 {
4371 if ((idx_align & 3) == 3)
4372 return FALSE;
4373 align = (idx_align & 3) * 64;
4374 }
4375 else
4376 align = (idx_align & 1) ? 32 << size : 0;
4377 break;
43e65147 4378
16980d0b
JB		 4379 default:
4380 abort ();
4381 }
43e65147 4382
16980d0b
JB		 4383 func (stream, "{");
4384 for (i = 0; i < length; i++)
4385 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4386 rd + i * stride, idx);
4387 func (stream, "}, [%s", arm_regnames[rn]);
4388 if (align)
8e560766 4389 func (stream, " :%d", align);
16980d0b
JB		 4390 func (stream, "]");
4391 if (rm == 0xd)
4392 func (stream, "!");
4393 else if (rm != 0xf)
4394 func (stream, ", %s", arm_regnames[rm]);
4395 }
4396 break;
43e65147 4397
16980d0b
JB		 4398 case 'C':
4399 {
4400 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4401 int rn = ((given >> 16) & 0xf);
4402 int rm = ((given >> 0) & 0xf);
4403 int align = ((given >> 4) & 0x1);
4404 int size = ((given >> 6) & 0x3);
4405 int type = ((given >> 8) & 0x3);
4406 int n = type + 1;
4407 int stride = ((given >> 5) & 0x1);
4408 int ix;
43e65147 4409
16980d0b
JB		 4410 if (stride && (n == 1))
4411 n++;
4412 else
4413 stride++;
43e65147 4414
16980d0b
JB		 4415 func (stream, "{");
4416 if (stride > 1)
4417 for (ix = 0; ix != n; ix++)
4418 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4419 else if (n == 1)
4420 func (stream, "d%d[]", rd);
4421 else
4422 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4423 func (stream, "}, [%s", arm_regnames[rn]);
4424 if (align)
4425 {
91d6fa6a 4426 align = (8 * (type + 1)) << size;
16980d0b
JB		 4427 if (type == 3)
4428 align = (size > 1) ? align >> 1 : align;
4429 if (type == 2 || (type == 0 && !size))
8e560766 4430 func (stream, " :<bad align %d>", align);
16980d0b 4431 else
8e560766 4432 func (stream, " :%d", align);
16980d0b
JB		 4433 }
4434 func (stream, "]");
4435 if (rm == 0xd)
4436 func (stream, "!");
4437 else if (rm != 0xf)
4438 func (stream, ", %s", arm_regnames[rm]);
4439 }
4440 break;
43e65147 4441
16980d0b
JB		 4442 case 'D':
4443 {
4444 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4445 int size = (given >> 20) & 3;
4446 int reg = raw_reg & ((4 << size) - 1);
4447 int ix = raw_reg >> size >> 2;
43e65147 4448
16980d0b
JB		 4449 func (stream, "d%d[%d]", reg, ix);
4450 }
4451 break;
43e65147 4452
16980d0b 4453 case 'E':
fe56b6ce 4454 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4455 {
4456 int bits = 0;
4457 int cmode = (given >> 8) & 0xf;
4458 int op = (given >> 5) & 0x1;
4459 unsigned long value = 0, hival = 0;
4460 unsigned shift;
4461 int size = 0;
0dbde4cf 4462 int isfloat = 0;
43e65147 4463
16980d0b
JB		 4464 bits |= ((given >> 24) & 1) << 7;
4465 bits |= ((given >> 16) & 7) << 4;
4466 bits |= ((given >> 0) & 15) << 0;
43e65147 4467
16980d0b
JB		 4468 if (cmode < 8)
4469 {
4470 shift = (cmode >> 1) & 3;
fe56b6ce 4471 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4472 size = 32;
4473 }
4474 else if (cmode < 12)
4475 {
4476 shift = (cmode >> 1) & 1;
fe56b6ce 4477 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4478 size = 16;
4479 }
4480 else if (cmode < 14)
4481 {
4482 shift = (cmode & 1) + 1;
fe56b6ce 4483 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4484 value |= (1ul << (8 * shift)) - 1;
4485 size = 32;
4486 }
4487 else if (cmode == 14)
4488 {
4489 if (op)
4490 {
fe56b6ce 4491 /* Bit replication into bytes. */
16980d0b
JB		 4492 int ix;
4493 unsigned long mask;
43e65147 4494
16980d0b
JB		 4495 value = 0;
4496 hival = 0;
4497 for (ix = 7; ix >= 0; ix--)
4498 {
4499 mask = ((bits >> ix) & 1) ? 0xff : 0;
4500 if (ix <= 3)
4501 value = (value << 8) | mask;
4502 else
4503 hival = (hival << 8) | mask;
4504 }
4505 size = 64;
4506 }
4507 else
4508 {
fe56b6ce
NC		 4509 /* Byte replication. */
4510 value = (unsigned long) bits;
16980d0b
JB		 4511 size = 8;
4512 }
4513 }
4514 else if (!op)
4515 {
fe56b6ce 4516 /* Floating point encoding. */
16980d0b 4517 int tmp;
43e65147 4518
fe56b6ce
NC		 4519 value = (unsigned long) (bits & 0x7f) << 19;
4520 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4521 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4522 value |= (unsigned long) tmp << 24;
16980d0b 4523 size = 32;
0dbde4cf 4524 isfloat = 1;
16980d0b
JB		 4525 }
4526 else
4527 {
4528 func (stream, "<illegal constant %.8x:%x:%x>",
4529 bits, cmode, op);
4530 size = 32;
4531 break;
4532 }
4533 switch (size)
4534 {
4535 case 8:
4536 func (stream, "#%ld\t; 0x%.2lx", value, value);
4537 break;
43e65147 4538
16980d0b
JB		 4539 case 16:
4540 func (stream, "#%ld\t; 0x%.4lx", value, value);
4541 break;
4542
4543 case 32:
0dbde4cf
JB		 4544 if (isfloat)
4545 {
4546 unsigned char valbytes[4];
4547 double fvalue;
43e65147 4548
0dbde4cf
JB		 4549 /* Do this a byte at a time so we don't have to
4550 worry about the host's endianness. */
4551 valbytes[0] = value & 0xff;
4552 valbytes[1] = (value >> 8) & 0xff;
4553 valbytes[2] = (value >> 16) & 0xff;
4554 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4555
4556 floatformat_to_double
c1e26897
NC		 4557 (& floatformat_ieee_single_little, valbytes,
4558 & fvalue);
43e65147 4559
0dbde4cf
JB		 4560 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4561 value);
4562 }
4563 else
4e9d3b81 4564 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4565 (long) (((value & 0x80000000L) != 0)
9d82ec38 4566 ? value | ~0xffffffffL : value),
c1e26897 4567 value);
16980d0b
JB		 4568 break;
4569
4570 case 64:
4571 func (stream, "#0x%.8lx%.8lx", hival, value);
4572 break;
43e65147 4573
16980d0b
JB		 4574 default:
4575 abort ();
4576 }
4577 }
4578 break;
43e65147 4579
16980d0b
JB		 4580 case 'F':
4581 {
4582 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4583 int num = (given >> 8) & 0x3;
43e65147 4584
16980d0b
JB		 4585 if (!num)
4586 func (stream, "{d%d}", regno);
4587 else if (num + regno >= 32)
4588 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4589 else
4590 func (stream, "{d%d-d%d}", regno, regno + num);
4591 }
4592 break;
7e8e6784 4593
16980d0b
JB		 4594
4595 case '0': case '1': case '2': case '3': case '4':
4596 case '5': case '6': case '7': case '8': case '9':
4597 {
4598 int width;
4599 unsigned long value;
4600
4601 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4602
16980d0b
JB		 4603 switch (*c)
4604 {
4605 case 'r':
4606 func (stream, "%s", arm_regnames[value]);
4607 break;
4608 case 'd':
4609 func (stream, "%ld", value);
05413229 4610 value_in_comment = value;
16980d0b
JB		 4611 break;
4612 case 'e':
4613 func (stream, "%ld", (1ul << width) - value);
4614 break;
43e65147 4615
16980d0b
JB		 4616 case 'S':
4617 case 'T':
4618 case 'U':
05413229 4619 /* Various width encodings. */
16980d0b
JB		 4620 {
4621 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4622 int limit;
4623 unsigned low, high;
4624
4625 c++;
4626 if (*c >= '0' && *c <= '9')
4627 limit = *c - '0';
4628 else if (*c >= 'a' && *c <= 'f')
4629 limit = *c - 'a' + 10;
4630 else
4631 abort ();
4632 low = limit >> 2;
4633 high = limit & 3;
4634
4635 if (value < low || value > high)
4636 func (stream, "<illegal width %d>", base << value);
4637 else
4638 func (stream, "%d", base << value);
4639 }
4640 break;
4641 case 'R':
4642 if (given & (1 << 6))
4643 goto Q;
4644 /* FALLTHROUGH */
4645 case 'D':
4646 func (stream, "d%ld", value);
4647 break;
4648 case 'Q':
4649 Q:
4650 if (value & 1)
4651 func (stream, "<illegal reg q%ld.5>", value >> 1);
4652 else
4653 func (stream, "q%ld", value >> 1);
4654 break;
43e65147 4655
16980d0b
JB		 4656 case '`':
4657 c++;
4658 if (value == 0)
4659 func (stream, "%c", *c);
4660 break;
4661 case '\'':
4662 c++;
4663 if (value == ((1ul << width) - 1))
4664 func (stream, "%c", *c);
4665 break;
4666 case '?':
fe56b6ce 4667 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4668 c += 1 << width;
4669 break;
4670 default:
4671 abort ();
4672 }
16980d0b 4673 }
dffaa15c
AM		 4674 break;
4675
4676 default:
4677 abort ();
16980d0b
JB		 4678 }
4679 }
4680 else
4681 func (stream, "%c", *c);
4682 }
05413229
NC		 4683
4684 if (value_in_comment > 32 || value_in_comment < -16)
4685 func (stream, "\t; 0x%lx", value_in_comment);
4686
e2efe87d
MGD		 4687 if (is_unpredictable)
4688 func (stream, UNPREDICTABLE_INSTRUCTION);
4689
16980d0b
JB		 4690 return TRUE;
4691 }
4692 }
4693 return FALSE;
4694}
4695
90ec0d68
MGD		 4696/* Return the name of a v7A special register. */
4697
43e65147 4698static const char *
90ec0d68
MGD		 4699banked_regname (unsigned reg)
4700{
4701 switch (reg)
4702 {
4703 case 15: return "CPSR";
43e65147 4704 case 32: return "R8_usr";
90ec0d68
MGD		 4705 case 33: return "R9_usr";
4706 case 34: return "R10_usr";
4707 case 35: return "R11_usr";
4708 case 36: return "R12_usr";
4709 case 37: return "SP_usr";
4710 case 38: return "LR_usr";
43e65147 4711 case 40: return "R8_fiq";
90ec0d68
MGD		 4712 case 41: return "R9_fiq";
4713 case 42: return "R10_fiq";
4714 case 43: return "R11_fiq";
4715 case 44: return "R12_fiq";
4716 case 45: return "SP_fiq";
4717 case 46: return "LR_fiq";
4718 case 48: return "LR_irq";
4719 case 49: return "SP_irq";
4720 case 50: return "LR_svc";
4721 case 51: return "SP_svc";
4722 case 52: return "LR_abt";
4723 case 53: return "SP_abt";
4724 case 54: return "LR_und";
4725 case 55: return "SP_und";
4726 case 60: return "LR_mon";
4727 case 61: return "SP_mon";
4728 case 62: return "ELR_hyp";
4729 case 63: return "SP_hyp";
4730 case 79: return "SPSR";
4731 case 110: return "SPSR_fiq";
4732 case 112: return "SPSR_irq";
4733 case 114: return "SPSR_svc";
4734 case 116: return "SPSR_abt";
4735 case 118: return "SPSR_und";
4736 case 124: return "SPSR_mon";
4737 case 126: return "SPSR_hyp";
4738 default: return NULL;
4739 }
4740}
4741
e797f7e0
MGD		 4742/* Return the name of the DMB/DSB option. */
4743static const char *
4744data_barrier_option (unsigned option)
4745{
4746 switch (option & 0xf)
4747 {
4748 case 0xf: return "sy";
4749 case 0xe: return "st";
4750 case 0xd: return "ld";
4751 case 0xb: return "ish";
4752 case 0xa: return "ishst";
4753 case 0x9: return "ishld";
4754 case 0x7: return "un";
4755 case 0x6: return "unst";
4756 case 0x5: return "nshld";
4757 case 0x3: return "osh";
4758 case 0x2: return "oshst";
4759 case 0x1: return "oshld";
4760 default: return NULL;
4761 }
4762}
4763
4a5329c6
ZW		 4764/* Print one ARM instruction from PC on INFO->STREAM. */
4765
4766static void
4767print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4768{
6b5d3a4d 4769 const struct opcode32 *insn;
6a51a8a8 4770 void *stream = info->stream;
6b5d3a4d 4771 fprintf_ftype func = info->fprintf_func;
b0e28b39 4772 struct arm_private_data *private_data = info->private_data;
252b5132 4773
16980d0b
JB		 4774 if (print_insn_coprocessor (pc, info, given, FALSE))
4775 return;
4776
4777 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4778 return;
4779
252b5132
RH		 4780 for (insn = arm_opcodes; insn->assembler; insn++)
4781 {
0313a2b8
NC		 4782 if ((given & insn->mask) != insn->value)
4783 continue;
823d2571
TG		 4784
4785 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4786 continue;
4787
4788 /* Special case: an instruction with all bits set in the condition field
4789 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4790 or by the catchall at the end of the table. */
4791 if ((given & 0xF0000000) != 0xF0000000
4792 || (insn->mask & 0xF0000000) == 0xF0000000
4793 || (insn->mask == 0 && insn->value == 0))
252b5132 4794 {
ff4a8d2b
NC		 4795 unsigned long u_reg = 16;
4796 unsigned long U_reg = 16;
ab8e2090 4797 bfd_boolean is_unpredictable = FALSE;
05413229 4798 signed long value_in_comment = 0;
6b5d3a4d 4799 const char *c;
b34976b6 4800
252b5132
RH		 4801 for (c = insn->assembler; *c; c++)
4802 {
4803 if (*c == '%')
4804 {
c1e26897
NC		 4805 bfd_boolean allow_unpredictable = FALSE;
4806
252b5132
RH		 4807 switch (*++c)
4808 {
4809 case '%':
4810 func (stream, "%%");
4811 break;
4812
4813 case 'a':
05413229 4814 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4815 break;
252b5132 4816
62b3e311
PB		 4817 case 'P':
4818 /* Set P address bit and use normal address
4819 printing routine. */
c1e26897 4820 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4821 break;
4822
c1e26897
NC		 4823 case 'S':
4824 allow_unpredictable = TRUE;
1a0670f3 4825 /* Fall through. */
252b5132
RH		 4826 case 's':
4827 if ((given & 0x004f0000) == 0x004f0000)
4828 {
58efb6c0 4829 /* PC relative with immediate offset. */
f8b960bc 4830 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4831
aefd8a40
NC		 4832 if (PRE_BIT_SET)
4833 {
26d97720
NS		 4834 /* Elide positive zero offset. */
4835 if (offset || NEGATIVE_BIT_SET)
4836 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4837 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4838 else
26d97720
NS		 4839 func (stream, "[pc]\t; ");
4840 if (NEGATIVE_BIT_SET)
4841 offset = -offset;
aefd8a40
NC		 4842 info->print_address_func (offset + pc + 8, info);
4843 }
4844 else
4845 {
26d97720
NS		 4846 /* Always show the offset. */
4847 func (stream, "[pc], #%s%d",
d908c8af 4848 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4849 if (! allow_unpredictable)
4850 is_unpredictable = TRUE;
aefd8a40 4851 }
252b5132
RH		 4852 }
4853 else
4854 {
fe56b6ce
NC		 4855 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4856
b34976b6 4857 func (stream, "[%s",
252b5132 4858 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4859
c1e26897 4860 if (PRE_BIT_SET)
252b5132 4861 {
c1e26897 4862 if (IMMEDIATE_BIT_SET)
252b5132 4863 {
26d97720
NS		 4864 /* Elide offset for non-writeback
4865 positive zero. */
4866 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4867 || offset)
4868 func (stream, ", #%s%d",
4869 NEGATIVE_BIT_SET ? "-" : "", offset);
4870
4871 if (NEGATIVE_BIT_SET)
4872 offset = -offset;
945ee430 4873
fe56b6ce 4874 value_in_comment = offset;
252b5132 4875 }
945ee430 4876 else
ff4a8d2b
NC		 4877 {
4878 /* Register Offset or Register Pre-Indexed. */
4879 func (stream, ", %s%s",
4880 NEGATIVE_BIT_SET ? "-" : "",
4881 arm_regnames[given & 0xf]);
4882
4883 /* Writing back to the register that is the source/
4884 destination of the load/store is unpredictable. */
4885 if (! allow_unpredictable
4886 && WRITEBACK_BIT_SET
4887 && ((given & 0xf) == ((given >> 12) & 0xf)))
4888 is_unpredictable = TRUE;
4889 }
252b5132 4890
b34976b6 4891 func (stream, "]%s",
c1e26897 4892 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4893 }
945ee430 4894 else
252b5132 4895 {
c1e26897 4896 if (IMMEDIATE_BIT_SET)
252b5132 4897 {
945ee430 4898 /* Immediate Post-indexed. */
aefd8a40 4899 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4900 func (stream, "], #%s%d",
4901 NEGATIVE_BIT_SET ? "-" : "", offset);
4902 if (NEGATIVE_BIT_SET)
4903 offset = -offset;
fe56b6ce 4904 value_in_comment = offset;
252b5132 4905 }
945ee430 4906 else
ff4a8d2b
NC		 4907 {
4908 /* Register Post-indexed. */
4909 func (stream, "], %s%s",
4910 NEGATIVE_BIT_SET ? "-" : "",
4911 arm_regnames[given & 0xf]);
4912
4913 /* Writing back to the register that is the source/
4914 destination of the load/store is unpredictable. */
4915 if (! allow_unpredictable
4916 && (given & 0xf) == ((given >> 12) & 0xf))
4917 is_unpredictable = TRUE;
4918 }
c1e26897 4919
07a28fab
NC		 4920 if (! allow_unpredictable)
4921 {
4922 /* Writeback is automatically implied by post- addressing.
4923 Setting the W bit is unnecessary and ARM specify it as
4924 being unpredictable. */
4925 if (WRITEBACK_BIT_SET
4926 /* Specifying the PC register as the post-indexed
4927 registers is also unpredictable. */
ab8e2090
NC		 4928 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4929 is_unpredictable = TRUE;
07a28fab 4930 }
252b5132
RH		 4931 }
4932 }
4933 break;
b34976b6 4934
252b5132 4935 case 'b':
6b5d3a4d 4936 {
f8b960bc 4937 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4938 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4939 }
252b5132
RH		 4940 break;
4941
4942 case 'c':
c22aaad1
PB		 4943 if (((given >> 28) & 0xf) != 0xe)
4944 func (stream, "%s",
4945 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4946 break;
4947
4948 case 'm':
4949 {
4950 int started = 0;
4951 int reg;
4952
4953 func (stream, "{");
4954 for (reg = 0; reg < 16; reg++)
4955 if ((given & (1 << reg)) != 0)
4956 {
4957 if (started)
4958 func (stream, ", ");
4959 started = 1;
4960 func (stream, "%s", arm_regnames[reg]);
4961 }
4962 func (stream, "}");
ab8e2090
NC		 4963 if (! started)
4964 is_unpredictable = TRUE;
252b5132
RH		 4965 }
4966 break;
4967
37b37b2d 4968 case 'q':
78c66db8 4969 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4970 break;
4971
252b5132
RH		 4972 case 'o':
4973 if ((given & 0x02000000) != 0)
4974 {
a415b1cd
JB		 4975 unsigned int rotate = (given & 0xf00) >> 7;
4976 unsigned int immed = (given & 0xff);
4977 unsigned int a, i;
4978
4979 a = (((immed << (32 - rotate))
4980 | (immed >> rotate)) & 0xffffffff);
4981 /* If there is another encoding with smaller rotate,
4982 the rotate should be specified directly. */
4983 for (i = 0; i < 32; i += 2)
4984 if ((a << i | a >> (32 - i)) <= 0xff)
4985 break;
4986
4987 if (i != rotate)
4988 func (stream, "#%d, %d", immed, rotate);
4989 else
4990 func (stream, "#%d", a);
4991 value_in_comment = a;
252b5132
RH		 4992 }
4993 else
78c66db8 4994 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4995 break;
4996
4997 case 'p':
4998 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4999 {
823d2571
TG		 5000 arm_feature_set arm_ext_v6 =
5001 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
5002
aefd8a40
NC		 5003 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
5004 mechanism for setting PSR flag bits. They are
5005 obsolete in V6 onwards. */
823d2571
TG		 5006 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
5007 arm_ext_v6))
aefd8a40 5008 func (stream, "p");
4ab90a7a
AV		 5009 else
5010 is_unpredictable = TRUE;
aefd8a40 5011 }
252b5132
RH		 5012 break;
5013
5014 case 't':
5015 if ((given & 0x01200000) == 0x00200000)
5016 func (stream, "t");
5017 break;
5018
252b5132 5019 case 'A':
05413229
NC		 5020 {
5021 int offset = given & 0xff;
f02232aa 5022
05413229 5023 value_in_comment = offset * 4;
c1e26897 5024 if (NEGATIVE_BIT_SET)
05413229 5025 value_in_comment = - value_in_comment;
f02232aa 5026
05413229 5027 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 5028
c1e26897 5029 if (PRE_BIT_SET)
05413229
NC		 5030 {
5031 if (offset)
fe56b6ce 5032 func (stream, ", #%d]%s",
d908c8af 5033 (int) value_in_comment,
c1e26897 5034 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 5035 else
5036 func (stream, "]");
5037 }
5038 else
5039 {
5040 func (stream, "]");
f02232aa 5041
c1e26897 5042 if (WRITEBACK_BIT_SET)
05413229
NC		 5043 {
5044 if (offset)
d908c8af 5045 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 5046 }
5047 else
fe56b6ce 5048 {
d908c8af 5049 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 5050 value_in_comment = offset;
5051 }
05413229
NC		 5052 }
5053 }
252b5132
RH		 5054 break;
5055
077b8428
NC		 5056 case 'B':
5057 /* Print ARM V5 BLX(1) address: pc+25 bits. */
5058 {
5059 bfd_vma address;
5060 bfd_vma offset = 0;
b34976b6 5061
c1e26897 5062 if (! NEGATIVE_BIT_SET)
077b8428
NC		 5063 /* Is signed, hi bits should be ones. */
5064 offset = (-1) ^ 0x00ffffff;
5065
5066 /* Offset is (SignExtend(offset field)<<2). */
5067 offset += given & 0x00ffffff;
5068 offset <<= 2;
5069 address = offset + pc + 8;
b34976b6 5070
8f06b2d8
PB		 5071 if (given & 0x01000000)
5072 /* H bit allows addressing to 2-byte boundaries. */
5073 address += 2;
b1ee46c5 5074
8f06b2d8 5075 info->print_address_func (address, info);
b1ee46c5 5076 }
b1ee46c5
AH		 5077 break;
5078
252b5132 5079 case 'C':
90ec0d68
MGD		 5080 if ((given & 0x02000200) == 0x200)
5081 {
5082 const char * name;
5083 unsigned sysm = (given & 0x004f0000) >> 16;
5084
5085 sysm |= (given & 0x300) >> 4;
5086 name = banked_regname (sysm);
5087
5088 if (name != NULL)
5089 func (stream, "%s", name);
5090 else
d908c8af 5091 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5092 }
5093 else
5094 {
43e65147 5095 func (stream, "%cPSR_",
90ec0d68
MGD		 5096 (given & 0x00400000) ? 'S' : 'C');
5097 if (given & 0x80000)
5098 func (stream, "f");
5099 if (given & 0x40000)
5100 func (stream, "s");
5101 if (given & 0x20000)
5102 func (stream, "x");
5103 if (given & 0x10000)
5104 func (stream, "c");
5105 }
252b5132
RH		 5106 break;
5107
62b3e311 5108 case 'U':
43e65147 5109 if ((given & 0xf0) == 0x60)
62b3e311 5110 {
52e7f43d
RE		 5111 switch (given & 0xf)
5112 {
5113 case 0xf: func (stream, "sy"); break;
5114 default:
5115 func (stream, "#%d", (int) given & 0xf);
5116 break;
5117 }
43e65147
L		 5118 }
5119 else
52e7f43d 5120 {
e797f7e0
MGD		 5121 const char * opt = data_barrier_option (given & 0xf);
5122 if (opt != NULL)
5123 func (stream, "%s", opt);
5124 else
52e7f43d 5125 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5126 }
5127 break;
5128
b34976b6 5129 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5130 case '5': case '6': case '7': case '8': case '9':
5131 {
16980d0b
JB		 5132 int width;
5133 unsigned long value;
252b5132 5134
16980d0b 5135 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5136
252b5132
RH		 5137 switch (*c)
5138 {
ab8e2090
NC		 5139 case 'R':
5140 if (value == 15)
5141 is_unpredictable = TRUE;
5142 /* Fall through. */
16980d0b 5143 case 'r':
9eb6c0f1
MGD		 5144 case 'T':
5145 /* We want register + 1 when decoding T. */
5146 if (*c == 'T')
5147 ++value;
5148
ff4a8d2b
NC		 5149 if (c[1] == 'u')
5150 {
5151 /* Eat the 'u' character. */
5152 ++ c;
5153
5154 if (u_reg == value)
5155 is_unpredictable = TRUE;
5156 u_reg = value;
5157 }
5158 if (c[1] == 'U')
5159 {
5160 /* Eat the 'U' character. */
5161 ++ c;
5162
5163 if (U_reg == value)
5164 is_unpredictable = TRUE;
5165 U_reg = value;
5166 }
16980d0b
JB		 5167 func (stream, "%s", arm_regnames[value]);
5168 break;
5169 case 'd':
5170 func (stream, "%ld", value);
05413229 5171 value_in_comment = value;
16980d0b
JB		 5172 break;
5173 case 'b':
5174 func (stream, "%ld", value * 8);
05413229 5175 value_in_comment = value * 8;
16980d0b
JB		 5176 break;
5177 case 'W':
5178 func (stream, "%ld", value + 1);
05413229 5179 value_in_comment = value + 1;
16980d0b
JB		 5180 break;
5181 case 'x':
5182 func (stream, "0x%08lx", value);
5183
5184 /* Some SWI instructions have special
5185 meanings. */
5186 if ((given & 0x0fffffff) == 0x0FF00000)
5187 func (stream, "\t; IMB");
5188 else if ((given & 0x0fffffff) == 0x0FF00001)
5189 func (stream, "\t; IMBRange");
5190 break;
5191 case 'X':
5192 func (stream, "%01lx", value & 0xf);
05413229 5193 value_in_comment = value;
252b5132
RH		 5194 break;
5195 case '`':
5196 c++;
16980d0b 5197 if (value == 0)
252b5132
RH		 5198 func (stream, "%c", *c);
5199 break;
5200 case '\'':
5201 c++;
16980d0b 5202 if (value == ((1ul << width) - 1))
252b5132
RH		 5203 func (stream, "%c", *c);
5204 break;
5205 case '?':
fe56b6ce 5206 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5207 c += 1 << width;
252b5132
RH		 5208 break;
5209 default:
5210 abort ();
5211 }
dffaa15c
AM		 5212 }
5213 break;
0dd132b6 5214
dffaa15c
AM		 5215 case 'e':
5216 {
5217 int imm;
0dd132b6 5218
dffaa15c
AM		 5219 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5220 func (stream, "%d", imm);
5221 value_in_comment = imm;
5222 }
5223 break;
fe56b6ce 5224
dffaa15c
AM		 5225 case 'E':
5226 /* LSB and WIDTH fields of BFI or BFC. The machine-
5227 language instruction encodes LSB and MSB. */
5228 {
5229 long msb = (given & 0x001f0000) >> 16;
5230 long lsb = (given & 0x00000f80) >> 7;
5231 long w = msb - lsb + 1;
0a003adc 5232
dffaa15c
AM		 5233 if (w > 0)
5234 func (stream, "#%lu, #%lu", lsb, w);
5235 else
5236 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5237 }
5238 break;
90ec0d68 5239
dffaa15c
AM		 5240 case 'R':
5241 /* Get the PSR/banked register name. */
5242 {
5243 const char * name;
5244 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 5245
dffaa15c
AM		 5246 sysm |= (given & 0x300) >> 4;
5247 name = banked_regname (sysm);
90ec0d68 5248
dffaa15c
AM		 5249 if (name != NULL)
5250 func (stream, "%s", name);
5251 else
5252 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5253 }
5254 break;
fe56b6ce 5255
dffaa15c
AM		 5256 case 'V':
5257 /* 16-bit unsigned immediate from a MOVT or MOVW
5258 instruction, encoded in bits 0:11 and 15:19. */
5259 {
5260 long hi = (given & 0x000f0000) >> 4;
5261 long lo = (given & 0x00000fff);
5262 long imm16 = hi | lo;
0a003adc 5263
dffaa15c
AM		 5264 func (stream, "#%lu", imm16);
5265 value_in_comment = imm16;
252b5132 5266 }
dffaa15c
AM		 5267 break;
5268
5269 default:
5270 abort ();
252b5132
RH		 5271 }
5272 }
5273 else
5274 func (stream, "%c", *c);
5275 }
05413229
NC		 5276
5277 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5278 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5279
5280 if (is_unpredictable)
5281 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5282
4a5329c6 5283 return;
252b5132
RH		 5284 }
5285 }
0b347048
TC		 5286 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5287 return;
252b5132
RH		 5288}
5289
4a5329c6 5290/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5291
4a5329c6
ZW		 5292static void
5293print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5294{
6b5d3a4d 5295 const struct opcode16 *insn;
6a51a8a8
AM		 5296 void *stream = info->stream;
5297 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5298
5299 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5300 if ((given & insn->mask) == insn->value)
5301 {
05413229 5302 signed long value_in_comment = 0;
6b5d3a4d 5303 const char *c = insn->assembler;
05413229 5304
c19d1205
ZW		 5305 for (; *c; c++)
5306 {
5307 int domaskpc = 0;
5308 int domasklr = 0;
5309
5310 if (*c != '%')
5311 {
5312 func (stream, "%c", *c);
5313 continue;
5314 }
252b5132 5315
c19d1205
ZW		 5316 switch (*++c)
5317 {
5318 case '%':
5319 func (stream, "%%");
5320 break;
b34976b6 5321
c22aaad1
PB		 5322 case 'c':
5323 if (ifthen_state)
5324 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5325 break;
5326
5327 case 'C':
5328 if (ifthen_state)
5329 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5330 else
5331 func (stream, "s");
5332 break;
5333
5334 case 'I':
5335 {
5336 unsigned int tmp;
5337
5338 ifthen_next_state = given & 0xff;
5339 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5340 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5341 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5342 }
5343 break;
5344
5345 case 'x':
5346 if (ifthen_next_state)
5347 func (stream, "\t; unpredictable branch in IT block\n");
5348 break;
5349
5350 case 'X':
5351 if (ifthen_state)
5352 func (stream, "\t; unpredictable <IT:%s>",
5353 arm_conditional[IFTHEN_COND]);
5354 break;
5355
c19d1205
ZW		 5356 case 'S':
5357 {
5358 long reg;
5359
5360 reg = (given >> 3) & 0x7;
5361 if (given & (1 << 6))
5362 reg += 8;
4f3c3dbb 5363
c19d1205
ZW		 5364 func (stream, "%s", arm_regnames[reg]);
5365 }
5366 break;
baf0cc5e 5367
c19d1205 5368 case 'D':
4f3c3dbb 5369 {
c19d1205
ZW		 5370 long reg;
5371
5372 reg = given & 0x7;
5373 if (given & (1 << 7))
5374 reg += 8;
5375
5376 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5377 }
c19d1205
ZW		 5378 break;
5379
5380 case 'N':
5381 if (given & (1 << 8))
5382 domasklr = 1;
5383 /* Fall through. */
5384 case 'O':
5385 if (*c == 'O' && (given & (1 << 8)))
5386 domaskpc = 1;
5387 /* Fall through. */
5388 case 'M':
5389 {
5390 int started = 0;
5391 int reg;
5392
5393 func (stream, "{");
5394
5395 /* It would be nice if we could spot
5396 ranges, and generate the rS-rE format: */
5397 for (reg = 0; (reg < 8); reg++)
5398 if ((given & (1 << reg)) != 0)
5399 {
5400 if (started)
5401 func (stream, ", ");
5402 started = 1;
5403 func (stream, "%s", arm_regnames[reg]);
5404 }
5405
5406 if (domasklr)
5407 {
5408 if (started)
5409 func (stream, ", ");
5410 started = 1;
d908c8af 5411 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5412 }
5413
5414 if (domaskpc)
5415 {
5416 if (started)
5417 func (stream, ", ");
d908c8af 5418 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5419 }
5420
5421 func (stream, "}");
5422 }
5423 break;
5424
4547cb56
NC		 5425 case 'W':
5426 /* Print writeback indicator for a LDMIA. We are doing a
5427 writeback if the base register is not in the register
5428 mask. */
5429 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5430 func (stream, "!");
dffaa15c 5431 break;
4547cb56 5432
c19d1205
ZW		 5433 case 'b':
5434 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5435 {
5436 bfd_vma address = (pc + 4
5437 + ((given & 0x00f8) >> 2)
5438 + ((given & 0x0200) >> 3));
5439 info->print_address_func (address, info);
5440 }
5441 break;
5442
5443 case 's':
5444 /* Right shift immediate -- bits 6..10; 1-31 print
5445 as themselves, 0 prints as 32. */
5446 {
5447 long imm = (given & 0x07c0) >> 6;
5448 if (imm == 0)
5449 imm = 32;
0fd3a477 5450 func (stream, "#%ld", imm);
c19d1205
ZW		 5451 }
5452 break;
5453
5454 case '0': case '1': case '2': case '3': case '4':
5455 case '5': case '6': case '7': case '8': case '9':
5456 {
5457 int bitstart = *c++ - '0';
5458 int bitend = 0;
5459
5460 while (*c >= '0' && *c <= '9')
5461 bitstart = (bitstart * 10) + *c++ - '0';
5462
5463 switch (*c)
5464 {
5465 case '-':
5466 {
f8b960bc 5467 bfd_vma reg;
c19d1205
ZW		 5468
5469 c++;
5470 while (*c >= '0' && *c <= '9')
5471 bitend = (bitend * 10) + *c++ - '0';
5472 if (!bitend)
5473 abort ();
5474 reg = given >> bitstart;
5475 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5476
c19d1205
ZW		 5477 switch (*c)
5478 {
5479 case 'r':
5480 func (stream, "%s", arm_regnames[reg]);
5481 break;
5482
5483 case 'd':
d908c8af 5484 func (stream, "%ld", (long) reg);
05413229 5485 value_in_comment = reg;
c19d1205
ZW		 5486 break;
5487
5488 case 'H':
d908c8af 5489 func (stream, "%ld", (long) (reg << 1));
05413229 5490 value_in_comment = reg << 1;
c19d1205
ZW		 5491 break;
5492
5493 case 'W':
d908c8af 5494 func (stream, "%ld", (long) (reg << 2));
05413229 5495 value_in_comment = reg << 2;
c19d1205
ZW		 5496 break;
5497
5498 case 'a':
5499 /* PC-relative address -- the bottom two
5500 bits of the address are dropped
5501 before the calculation. */
5502 info->print_address_func
5503 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5504 value_in_comment = 0;
c19d1205
ZW		 5505 break;
5506
5507 case 'x':
d908c8af 5508 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5509 break;
5510
c19d1205
ZW		 5511 case 'B':
5512 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5513 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5514 value_in_comment = 0;
c19d1205
ZW		 5515 break;
5516
5517 case 'c':
c22aaad1 5518 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5519 break;
5520
5521 default:
5522 abort ();
5523 }
5524 }
5525 break;
5526
5527 case '\'':
5528 c++;
5529 if ((given & (1 << bitstart)) != 0)
5530 func (stream, "%c", *c);
5531 break;
5532
5533 case '?':
5534 ++c;
5535 if ((given & (1 << bitstart)) != 0)
5536 func (stream, "%c", *c++);
5537 else
5538 func (stream, "%c", *++c);
5539 break;
5540
5541 default:
5542 abort ();
5543 }
5544 }
5545 break;
5546
5547 default:
5548 abort ();
5549 }
5550 }
05413229
NC		 5551
5552 if (value_in_comment > 32 || value_in_comment < -16)
5553 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5554 return;
c19d1205
ZW		 5555 }
5556
5557 /* No match. */
0b347048
TC		 5558 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5559 return;
c19d1205
ZW		 5560}
5561
62b3e311 5562/* Return the name of an V7M special register. */
fe56b6ce 5563
62b3e311
PB		 5564static const char *
5565psr_name (int regno)
5566{
5567 switch (regno)
5568 {
1a336194
TP		 5569 case 0x0: return "APSR";
5570 case 0x1: return "IAPSR";
5571 case 0x2: return "EAPSR";
5572 case 0x3: return "PSR";
5573 case 0x5: return "IPSR";
5574 case 0x6: return "EPSR";
5575 case 0x7: return "IEPSR";
5576 case 0x8: return "MSP";
5577 case 0x9: return "PSP";
5578 case 0xa: return "MSPLIM";
5579 case 0xb: return "PSPLIM";
5580 case 0x10: return "PRIMASK";
5581 case 0x11: return "BASEPRI";
5582 case 0x12: return "BASEPRI_MAX";
5583 case 0x13: return "FAULTMASK";
5584 case 0x14: return "CONTROL";
16a1fa25
TP		 5585 case 0x88: return "MSP_NS";
5586 case 0x89: return "PSP_NS";
1a336194
TP		 5587 case 0x8a: return "MSPLIM_NS";
5588 case 0x8b: return "PSPLIM_NS";
5589 case 0x90: return "PRIMASK_NS";
5590 case 0x91: return "BASEPRI_NS";
5591 case 0x93: return "FAULTMASK_NS";
5592 case 0x94: return "CONTROL_NS";
5593 case 0x98: return "SP_NS";
62b3e311
PB		 5594 default: return "<unknown>";
5595 }
5596}
5597
4a5329c6
ZW		 5598/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5599
5600static void
5601print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5602{
6b5d3a4d 5603 const struct opcode32 *insn;
c19d1205
ZW		 5604 void *stream = info->stream;
5605 fprintf_ftype func = info->fprintf_func;
5606
16980d0b
JB		 5607 if (print_insn_coprocessor (pc, info, given, TRUE))
5608 return;
5609
5610 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5611 return;
5612
c19d1205
ZW		 5613 for (insn = thumb32_opcodes; insn->assembler; insn++)
5614 if ((given & insn->mask) == insn->value)
5615 {
4b5a202f 5616 bfd_boolean is_clrm = FALSE;
ff4a8d2b 5617 bfd_boolean is_unpredictable = FALSE;
05413229 5618 signed long value_in_comment = 0;
6b5d3a4d 5619 const char *c = insn->assembler;
05413229 5620
c19d1205
ZW		 5621 for (; *c; c++)
5622 {
5623 if (*c != '%')
5624 {
5625 func (stream, "%c", *c);
5626 continue;
5627 }
5628
5629 switch (*++c)
5630 {
5631 case '%':
5632 func (stream, "%%");
5633 break;
5634
c22aaad1
PB		 5635 case 'c':
5636 if (ifthen_state)
5637 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5638 break;
5639
5640 case 'x':
5641 if (ifthen_next_state)
5642 func (stream, "\t; unpredictable branch in IT block\n");
5643 break;
5644
5645 case 'X':
5646 if (ifthen_state)
5647 func (stream, "\t; unpredictable <IT:%s>",
5648 arm_conditional[IFTHEN_COND]);
5649 break;
5650
c19d1205
ZW		 5651 case 'I':
5652 {
5653 unsigned int imm12 = 0;
fe56b6ce 5654
c19d1205
ZW		 5655 imm12 |= (given & 0x000000ffu);
5656 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5657 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5658 func (stream, "#%u", imm12);
5659 value_in_comment = imm12;
c19d1205
ZW		 5660 }
5661 break;
5662
5663 case 'M':
5664 {
5665 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5666
c19d1205
ZW		 5667 bits |= (given & 0x000000ffu);
5668 bits |= (given & 0x00007000u) >> 4;
5669 bits |= (given & 0x04000000u) >> 15;
5670 imm8 = (bits & 0x0ff);
5671 mod = (bits & 0xf00) >> 8;
5672 switch (mod)
5673 {
5674 case 0: imm = imm8; break;
c1e26897
NC		 5675 case 1: imm = ((imm8 << 16) | imm8); break;
5676 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5677 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5678 default:
5679 mod = (bits & 0xf80) >> 7;
5680 imm8 = (bits & 0x07f) | 0x80;
5681 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5682 }
fe56b6ce
NC		 5683 func (stream, "#%u", imm);
5684 value_in_comment = imm;
c19d1205
ZW		 5685 }
5686 break;
43e65147 5687
c19d1205
ZW		 5688 case 'J':
5689 {
5690 unsigned int imm = 0;
fe56b6ce 5691
c19d1205
ZW		 5692 imm |= (given & 0x000000ffu);
5693 imm |= (given & 0x00007000u) >> 4;
5694 imm |= (given & 0x04000000u) >> 15;
5695 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5696 func (stream, "#%u", imm);
5697 value_in_comment = imm;
c19d1205
ZW		 5698 }
5699 break;
5700
5701 case 'K':
5702 {
5703 unsigned int imm = 0;
fe56b6ce 5704
c19d1205
ZW		 5705 imm |= (given & 0x000f0000u) >> 16;
5706 imm |= (given & 0x00000ff0u) >> 0;
5707 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5708 func (stream, "#%u", imm);
5709 value_in_comment = imm;
c19d1205
ZW		 5710 }
5711 break;
5712
74db7efb
NC		 5713 case 'H':
5714 {
5715 unsigned int imm = 0;
5716
5717 imm |= (given & 0x000f0000u) >> 4;
5718 imm |= (given & 0x00000fffu) >> 0;
5719 func (stream, "#%u", imm);
5720 value_in_comment = imm;
5721 }
5722 break;
5723
90ec0d68
MGD		 5724 case 'V':
5725 {
5726 unsigned int imm = 0;
5727
5728 imm |= (given & 0x00000fffu);
5729 imm |= (given & 0x000f0000u) >> 4;
5730 func (stream, "#%u", imm);
5731 value_in_comment = imm;
5732 }
5733 break;
5734
c19d1205
ZW		 5735 case 'S':
5736 {
5737 unsigned int reg = (given & 0x0000000fu);
5738 unsigned int stp = (given & 0x00000030u) >> 4;
5739 unsigned int imm = 0;
5740 imm |= (given & 0x000000c0u) >> 6;
5741 imm |= (given & 0x00007000u) >> 10;
5742
5743 func (stream, "%s", arm_regnames[reg]);
5744 switch (stp)
5745 {
5746 case 0:
5747 if (imm > 0)
5748 func (stream, ", lsl #%u", imm);
5749 break;
5750
5751 case 1:
5752 if (imm == 0)
5753 imm = 32;
5754 func (stream, ", lsr #%u", imm);
5755 break;
5756
5757 case 2:
5758 if (imm == 0)
5759 imm = 32;
5760 func (stream, ", asr #%u", imm);
5761 break;
5762
5763 case 3:
5764 if (imm == 0)
5765 func (stream, ", rrx");
5766 else
5767 func (stream, ", ror #%u", imm);
5768 }
5769 }
5770 break;
5771
5772 case 'a':
5773 {
5774 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5775 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5776 unsigned int op = (given & 0x00000f00) >> 8;
5777 unsigned int i12 = (given & 0x00000fff);
5778 unsigned int i8 = (given & 0x000000ff);
5779 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5780 bfd_vma offset = 0;
c19d1205
ZW		 5781
5782 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5783 if (U) /* 12-bit positive immediate offset. */
5784 {
5785 offset = i12;
5786 if (Rn != 15)
5787 value_in_comment = offset;
5788 }
5789 else if (Rn == 15) /* 12-bit negative immediate offset. */
5790 offset = - (int) i12;
5791 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5792 {
5793 unsigned int Rm = (i8 & 0x0f);
5794 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5795
c19d1205
ZW		 5796 func (stream, ", %s", arm_regnames[Rm]);
5797 if (sh)
5798 func (stream, ", lsl #%u", sh);
5799 func (stream, "]");
5800 break;
5801 }
5802 else switch (op)
5803 {
05413229 5804 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5805 offset = i8;
5806 break;
5807
05413229 5808 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5809 offset = -i8;
5810 break;
5811
05413229 5812 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5813 offset = i8;
5814 writeback = TRUE;
5815 break;
5816
05413229 5817 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5818 offset = -i8;
5819 writeback = TRUE;
5820 break;
5821
05413229 5822 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5823 offset = i8;
5824 postind = TRUE;
5825 break;
5826
05413229 5827 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5828 offset = -i8;
5829 postind = TRUE;
5830 break;
5831
5832 default:
5833 func (stream, ", <undefined>]");
5834 goto skip;
5835 }
5836
5837 if (postind)
d908c8af 5838 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5839 else
5840 {
5841 if (offset)
d908c8af 5842 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5843 func (stream, writeback ? "]!" : "]");
5844 }
5845
5846 if (Rn == 15)
5847 {
5848 func (stream, "\t; ");
5849 info->print_address_func (((pc + 4) & ~3) + offset, info);
5850 }
5851 }
5852 skip:
5853 break;
5854
5855 case 'A':
5856 {
c1e26897
NC		 5857 unsigned int U = ! NEGATIVE_BIT_SET;
5858 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5859 unsigned int Rn = (given & 0x000f0000) >> 16;
5860 unsigned int off = (given & 0x000000ff);
5861
5862 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5863
5864 if (PRE_BIT_SET)
c19d1205
ZW		 5865 {
5866 if (off || !U)
05413229
NC		 5867 {
5868 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5869 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5870 }
c19d1205
ZW		 5871 func (stream, "]");
5872 if (W)
5873 func (stream, "!");
5874 }
5875 else
5876 {
5877 func (stream, "], ");
5878 if (W)
05413229
NC		 5879 {
5880 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5881 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5882 }
c19d1205 5883 else
fe56b6ce
NC		 5884 {
5885 func (stream, "{%u}", off);
5886 value_in_comment = off;
5887 }
c19d1205
ZW		 5888 }
5889 }
5890 break;
5891
5892 case 'w':
5893 {
5894 unsigned int Sbit = (given & 0x01000000) >> 24;
5895 unsigned int type = (given & 0x00600000) >> 21;
05413229 5896
c19d1205
ZW		 5897 switch (type)
5898 {
5899 case 0: func (stream, Sbit ? "sb" : "b"); break;
5900 case 1: func (stream, Sbit ? "sh" : "h"); break;
5901 case 2:
5902 if (Sbit)
5903 func (stream, "??");
5904 break;
5905 case 3:
5906 func (stream, "??");
5907 break;
5908 }
5909 }
5910 break;
5911
4b5a202f
AV		 5912 case 'n':
5913 is_clrm = TRUE;
5914 /* Fall through. */
c19d1205
ZW		 5915 case 'm':
5916 {
5917 int started = 0;
5918 int reg;
5919
5920 func (stream, "{");
5921 for (reg = 0; reg < 16; reg++)
5922 if ((given & (1 << reg)) != 0)
5923 {
5924 if (started)
5925 func (stream, ", ");
5926 started = 1;
4b5a202f
AV		 5927 if (is_clrm && reg == 13)
5928 func (stream, "(invalid: %s)", arm_regnames[reg]);
5929 else if (is_clrm && reg == 15)
5930 func (stream, "%s", "APSR");
5931 else
5932 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 5933 }
5934 func (stream, "}");
5935 }
5936 break;
5937
5938 case 'E':
5939 {
5940 unsigned int msb = (given & 0x0000001f);
5941 unsigned int lsb = 0;
fe56b6ce 5942
c19d1205
ZW		 5943 lsb |= (given & 0x000000c0u) >> 6;
5944 lsb |= (given & 0x00007000u) >> 10;
5945 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5946 }
5947 break;
5948
5949 case 'F':
5950 {
5951 unsigned int width = (given & 0x0000001f) + 1;
5952 unsigned int lsb = 0;
fe56b6ce 5953
c19d1205
ZW		 5954 lsb |= (given & 0x000000c0u) >> 6;
5955 lsb |= (given & 0x00007000u) >> 10;
5956 func (stream, "#%u, #%u", lsb, width);
5957 }
5958 break;
5959
e12437dc
AV		 5960 case 'G':
5961 {
5962 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
5963 func (stream, "%x", boff);
5964 }
5965 break;
5966
e5d6e09e
AV		 5967 case 'W':
5968 {
5969 unsigned int immA = (given & 0x001f0000u) >> 16;
5970 unsigned int immB = (given & 0x000007feu) >> 1;
5971 unsigned int immC = (given & 0x00000800u) >> 11;
5972 bfd_vma offset = 0;
5973
5974 offset |= immA << 12;
5975 offset |= immB << 2;
5976 offset |= immC << 1;
5977 /* Sign extend. */
5978 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
5979
5980 info->print_address_func (pc + 4 + offset, info);
5981 }
5982 break;
5983
1caf72a5
AV		 5984 case 'Y':
5985 {
5986 unsigned int immA = (given & 0x007f0000u) >> 16;
5987 unsigned int immB = (given & 0x000007feu) >> 1;
5988 unsigned int immC = (given & 0x00000800u) >> 11;
5989 bfd_vma offset = 0;
5990
5991 offset |= immA << 12;
5992 offset |= immB << 2;
5993 offset |= immC << 1;
5994 /* Sign extend. */
5995 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
5996
5997 info->print_address_func (pc + 4 + offset, info);
5998 }
5999 break;
6000
1889da70
AV		 6001 case 'Z':
6002 {
6003 unsigned int immA = (given & 0x00010000u) >> 16;
6004 unsigned int immB = (given & 0x000007feu) >> 1;
6005 unsigned int immC = (given & 0x00000800u) >> 11;
6006 bfd_vma offset = 0;
6007
6008 offset |= immA << 12;
6009 offset |= immB << 2;
6010 offset |= immC << 1;
6011 /* Sign extend. */
6012 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
6013
6014 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 6015
6016 unsigned int T = (given & 0x00020000u) >> 17;
6017 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
6018 unsigned int boffset = (T == 1) ? 4 : 2;
6019 func (stream, ", ");
6020 func (stream, "%x", endoffset + boffset);
1889da70
AV		 6021 }
6022 break;
6023
60f993ce
AV		 6024 case 'Q':
6025 {
6026 unsigned int immh = (given & 0x000007feu) >> 1;
6027 unsigned int imml = (given & 0x00000800u) >> 11;
6028 bfd_vma imm32 = 0;
6029
6030 imm32 |= immh << 2;
6031 imm32 |= imml << 1;
6032
6033 info->print_address_func (pc + 4 + imm32, info);
6034 }
6035 break;
6036
6037 case 'P':
6038 {
6039 unsigned int immh = (given & 0x000007feu) >> 1;
6040 unsigned int imml = (given & 0x00000800u) >> 11;
6041 bfd_vma imm32 = 0;
6042
6043 imm32 |= immh << 2;
6044 imm32 |= imml << 1;
6045
6046 info->print_address_func (pc + 4 - imm32, info);
6047 }
6048 break;
6049
c19d1205
ZW		 6050 case 'b':
6051 {
6052 unsigned int S = (given & 0x04000000u) >> 26;
6053 unsigned int J1 = (given & 0x00002000u) >> 13;
6054 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 6055 bfd_vma offset = 0;
c19d1205
ZW		 6056
6057 offset |= !S << 20;
6058 offset |= J2 << 19;
6059 offset |= J1 << 18;
6060 offset |= (given & 0x003f0000) >> 4;
6061 offset |= (given & 0x000007ff) << 1;
6062 offset -= (1 << 20);
6063
6064 info->print_address_func (pc + 4 + offset, info);
6065 }
6066 break;
6067
6068 case 'B':
6069 {
6070 unsigned int S = (given & 0x04000000u) >> 26;
6071 unsigned int I1 = (given & 0x00002000u) >> 13;
6072 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 6073 bfd_vma offset = 0;
c19d1205
ZW		 6074
6075 offset |= !S << 24;
6076 offset |= !(I1 ^ S) << 23;
6077 offset |= !(I2 ^ S) << 22;
6078 offset |= (given & 0x03ff0000u) >> 4;
6079 offset |= (given & 0x000007ffu) << 1;
6080 offset -= (1 << 24);
36b0c57d 6081 offset += pc + 4;
c19d1205 6082
36b0c57d
PB		 6083 /* BLX target addresses are always word aligned. */
6084 if ((given & 0x00001000u) == 0)
6085 offset &= ~2u;
6086
6087 info->print_address_func (offset, info);
c19d1205
ZW		 6088 }
6089 break;
6090
6091 case 's':
6092 {
6093 unsigned int shift = 0;
fe56b6ce 6094
c19d1205
ZW		 6095 shift |= (given & 0x000000c0u) >> 6;
6096 shift |= (given & 0x00007000u) >> 10;
c1e26897 6097 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 6098 func (stream, ", asr #%u", shift);
6099 else if (shift)
6100 func (stream, ", lsl #%u", shift);
6101 /* else print nothing - lsl #0 */
6102 }
6103 break;
6104
6105 case 'R':
6106 {
6107 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 6108
c19d1205
ZW		 6109 if (rot)
6110 func (stream, ", ror #%u", rot * 8);
6111 }
6112 break;
6113
62b3e311 6114 case 'U':
43e65147 6115 if ((given & 0xf0) == 0x60)
62b3e311 6116 {
52e7f43d
RE		 6117 switch (given & 0xf)
6118 {
6119 case 0xf: func (stream, "sy"); break;
6120 default:
6121 func (stream, "#%d", (int) given & 0xf);
6122 break;
6123 }
62b3e311 6124 }
43e65147 6125 else
52e7f43d 6126 {
e797f7e0
MGD		 6127 const char * opt = data_barrier_option (given & 0xf);
6128 if (opt != NULL)
6129 func (stream, "%s", opt);
6130 else
6131 func (stream, "#%d", (int) given & 0xf);
52e7f43d 6132 }
62b3e311
PB		 6133 break;
6134
6135 case 'C':
6136 if ((given & 0xff) == 0)
6137 {
6138 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
6139 if (given & 0x800)
6140 func (stream, "f");
6141 if (given & 0x400)
6142 func (stream, "s");
6143 if (given & 0x200)
6144 func (stream, "x");
6145 if (given & 0x100)
6146 func (stream, "c");
6147 }
90ec0d68
MGD		 6148 else if ((given & 0x20) == 0x20)
6149 {
6150 char const* name;
6151 unsigned sysm = (given & 0xf00) >> 8;
6152
6153 sysm |= (given & 0x30);
6154 sysm |= (given & 0x00100000) >> 14;
6155 name = banked_regname (sysm);
43e65147 6156
90ec0d68
MGD		 6157 if (name != NULL)
6158 func (stream, "%s", name);
6159 else
d908c8af 6160 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 6161 }
62b3e311
PB		 6162 else
6163 {
d908c8af 6164 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6165 }
6166 break;
6167
6168 case 'D':
90ec0d68
MGD		 6169 if (((given & 0xff) == 0)
6170 || ((given & 0x20) == 0x20))
6171 {
6172 char const* name;
6173 unsigned sm = (given & 0xf0000) >> 16;
6174
6175 sm |= (given & 0x30);
6176 sm |= (given & 0x00100000) >> 14;
6177 name = banked_regname (sm);
6178
6179 if (name != NULL)
6180 func (stream, "%s", name);
6181 else
d908c8af 6182 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 6183 }
62b3e311 6184 else
d908c8af 6185 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6186 break;
6187
c19d1205
ZW		 6188 case '0': case '1': case '2': case '3': case '4':
6189 case '5': case '6': case '7': case '8': case '9':
6190 {
16980d0b
JB		 6191 int width;
6192 unsigned long val;
c19d1205 6193
16980d0b 6194 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 6195
c19d1205
ZW		 6196 switch (*c)
6197 {
05413229
NC		 6198 case 'd':
6199 func (stream, "%lu", val);
6200 value_in_comment = val;
6201 break;
ff4a8d2b 6202
f0fba320
RL		 6203 case 'D':
6204 func (stream, "%lu", val + 1);
6205 value_in_comment = val + 1;
6206 break;
6207
05413229
NC		 6208 case 'W':
6209 func (stream, "%lu", val * 4);
6210 value_in_comment = val * 4;
6211 break;
ff4a8d2b 6212
f1c7f421
AV		 6213 case 'S':
6214 if (val == 13)
6215 is_unpredictable = TRUE;
6216 /* Fall through. */
ff4a8d2b
NC		 6217 case 'R':
6218 if (val == 15)
6219 is_unpredictable = TRUE;
6220 /* Fall through. */
6221 case 'r':
6222 func (stream, "%s", arm_regnames[val]);
6223 break;
c19d1205
ZW		 6224
6225 case 'c':
c22aaad1 6226 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6227 break;
6228
6229 case '\'':
c19d1205 6230 c++;
16980d0b
JB		 6231 if (val == ((1ul << width) - 1))
6232 func (stream, "%c", *c);
c19d1205 6233 break;
43e65147 6234
c19d1205 6235 case '`':
c19d1205 6236 c++;
16980d0b
JB		 6237 if (val == 0)
6238 func (stream, "%c", *c);
c19d1205
ZW		 6239 break;
6240
6241 case '?':
fe56b6ce 6242 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6243 c += 1 << width;
c19d1205 6244 break;
43e65147 6245
0bb027fd
RR		 6246 case 'x':
6247 func (stream, "0x%lx", val & 0xffffffffUL);
6248 break;
c19d1205
ZW		 6249
6250 default:
6251 abort ();
6252 }
6253 }
6254 break;
6255
32a94698
NC		 6256 case 'L':
6257 /* PR binutils/12534
6258 If we have a PC relative offset in an LDRD or STRD
6259 instructions then display the decoded address. */
6260 if (((given >> 16) & 0xf) == 0xf)
6261 {
6262 bfd_vma offset = (given & 0xff) * 4;
6263
6264 if ((given & (1 << 23)) == 0)
6265 offset = - offset;
6266 func (stream, "\t; ");
6267 info->print_address_func ((pc & ~3) + 4 + offset, info);
6268 }
6269 break;
6270
c19d1205
ZW		 6271 default:
6272 abort ();
6273 }
6274 }
05413229
NC		 6275
6276 if (value_in_comment > 32 || value_in_comment < -16)
6277 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6278
6279 if (is_unpredictable)
6280 func (stream, UNPREDICTABLE_INSTRUCTION);
6281
4a5329c6 6282 return;
c19d1205 6283 }
252b5132 6284
58efb6c0 6285 /* No match. */
0b347048
TC		 6286 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6287 return;
252b5132
RH		 6288}
6289
e821645d
DJ		 6290/* Print data bytes on INFO->STREAM. */
6291
6292static void
fe56b6ce
NC		 6293print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6294 struct disassemble_info *info,
e821645d
DJ		 6295 long given)
6296{
6297 switch (info->bytes_per_chunk)
6298 {
6299 case 1:
6300 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6301 break;
6302 case 2:
6303 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6304 break;
6305 case 4:
6306 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6307 break;
6308 default:
6309 abort ();
6310 }
6311}
6312
22a398e1 6313/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6314 being displayed in symbol relative addresses.
6315
6316 Also disallow private symbol, with __tagsym$$ prefix,
6317 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6318
6319bfd_boolean
6320arm_symbol_is_valid (asymbol * sym,
6321 struct disassemble_info * info ATTRIBUTE_UNUSED)
6322{
6323 const char * name;
43e65147 6324
22a398e1
NC		 6325 if (sym == NULL)
6326 return FALSE;
6327
6328 name = bfd_asymbol_name (sym);
6329
d8282f0e 6330 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6331}
6332
65b48a81 6333/* Parse the string of disassembler options. */
baf0cc5e 6334
65b48a81 6335static void
f995bbe8 6336parse_arm_disassembler_options (const char *options)
dd92f639 6337{
f995bbe8 6338 const char *opt;
b34976b6 6339
65b48a81 6340 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6341 {
65b48a81
PB		 6342 if (CONST_STRNEQ (opt, "reg-names-"))
6343 {
6344 unsigned int i;
6345 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6346 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6347 {
6348 regname_selected = i;
6349 break;
6350 }
b34976b6 6351
65b48a81 6352 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 6353 /* xgettext: c-format */
6354 opcodes_error_handler (_("unrecognised register name set: %s"),
6355 opt);
65b48a81
PB		 6356 }
6357 else if (CONST_STRNEQ (opt, "force-thumb"))
6358 force_thumb = 1;
6359 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6360 force_thumb = 0;
6361 else
a6743a54
AM		 6362 /* xgettext: c-format */
6363 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 6364 }
b34976b6 6365
dd92f639
NC		 6366 return;
6367}
6368
5bc5ae88
RL		 6369static bfd_boolean
6370mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6371 enum map_type *map_symbol);
6372
c22aaad1
PB		 6373/* Search back through the insn stream to determine if this instruction is
6374 conditionally executed. */
fe56b6ce 6375
c22aaad1 6376static void
fe56b6ce
NC		 6377find_ifthen_state (bfd_vma pc,
6378 struct disassemble_info *info,
c22aaad1
PB		 6379 bfd_boolean little)
6380{
6381 unsigned char b[2];
6382 unsigned int insn;
6383 int status;
6384 /* COUNT is twice the number of instructions seen. It will be odd if we
6385 just crossed an instruction boundary. */
6386 int count;
6387 int it_count;
6388 unsigned int seen_it;
6389 bfd_vma addr;
6390
6391 ifthen_address = pc;
6392 ifthen_state = 0;
6393
6394 addr = pc;
6395 count = 1;
6396 it_count = 0;
6397 seen_it = 0;
6398 /* Scan backwards looking for IT instructions, keeping track of where
6399 instruction boundaries are. We don't know if something is actually an
6400 IT instruction until we find a definite instruction boundary. */
6401 for (;;)
6402 {
fe56b6ce 6403 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6404 {
6405 /* A symbol must be on an instruction boundary, and will not
6406 be within an IT block. */
6407 if (seen_it && (count & 1))
6408 break;
6409
6410 return;
6411 }
6412 addr -= 2;
fe56b6ce 6413 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6414 if (status)
6415 return;
6416
6417 if (little)
6418 insn = (b[0]) | (b[1] << 8);
6419 else
6420 insn = (b[1]) | (b[0] << 8);
6421 if (seen_it)
6422 {
6423 if ((insn & 0xf800) < 0xe800)
6424 {
6425 /* Addr + 2 is an instruction boundary. See if this matches
6426 the expected boundary based on the position of the last
6427 IT candidate. */
6428 if (count & 1)
6429 break;
6430 seen_it = 0;
6431 }
6432 }
6433 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6434 {
5bc5ae88
RL		 6435 enum map_type type = MAP_ARM;
6436 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6437
6438 if (!found || (found && type == MAP_THUMB))
6439 {
6440 /* This could be an IT instruction. */
6441 seen_it = insn;
6442 it_count = count >> 1;
6443 }
c22aaad1
PB		 6444 }
6445 if ((insn & 0xf800) >= 0xe800)
6446 count++;
6447 else
6448 count = (count + 2) | 1;
6449 /* IT blocks contain at most 4 instructions. */
6450 if (count >= 8 && !seen_it)
6451 return;
6452 }
6453 /* We found an IT instruction. */
6454 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6455 if ((ifthen_state & 0xf) == 0)
6456 ifthen_state = 0;
6457}
6458
b0e28b39
DJ		 6459/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6460 mapping symbol. */
6461
6462static int
6463is_mapping_symbol (struct disassemble_info *info, int n,
6464 enum map_type *map_type)
6465{
6466 const char *name;
6467
6468 name = bfd_asymbol_name (info->symtab[n]);
6469 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6470 && (name[2] == 0 || name[2] == '.'))
6471 {
6472 *map_type = ((name[1] == 'a') ? MAP_ARM
6473 : (name[1] == 't') ? MAP_THUMB
6474 : MAP_DATA);
6475 return TRUE;
6476 }
6477
6478 return FALSE;
6479}
6480
6481/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6482 Returns nonzero if *MAP_TYPE was set. */
6483
6484static int
6485get_map_sym_type (struct disassemble_info *info,
6486 int n,
6487 enum map_type *map_type)
6488{
6489 /* If the symbol is in a different section, ignore it. */
6490 if (info->section != NULL && info->section != info->symtab[n]->section)
6491 return FALSE;
6492
6493 return is_mapping_symbol (info, n, map_type);
6494}
6495
6496/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6497 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6498
6499static int
fe56b6ce
NC		 6500get_sym_code_type (struct disassemble_info *info,
6501 int n,
e821645d 6502 enum map_type *map_type)
2087ad84
PB		 6503{
6504 elf_symbol_type *es;
6505 unsigned int type;
b0e28b39
DJ		 6506
6507 /* If the symbol is in a different section, ignore it. */
6508 if (info->section != NULL && info->section != info->symtab[n]->section)
6509 return FALSE;
2087ad84 6510
e821645d 6511 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6512 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6513
6514 /* If the symbol has function type then use that. */
34e77a92 6515 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6516 {
39d911fc
TP		 6517 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6518 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6519 *map_type = MAP_THUMB;
6520 else
6521 *map_type = MAP_ARM;
2087ad84
PB		 6522 return TRUE;
6523 }
6524
2087ad84
PB		 6525 return FALSE;
6526}
6527
5bc5ae88
RL		 6528/* Search the mapping symbol state for instruction at pc. This is only
6529 applicable for elf target.
6530
6531 There is an assumption Here, info->private_data contains the correct AND
6532 up-to-date information about current scan process. The information will be
6533 used to speed this search process.
6534
6535 Return TRUE if the mapping state can be determined, and map_symbol
6536 will be updated accordingly. Otherwise, return FALSE. */
6537
6538static bfd_boolean
6539mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6540 enum map_type *map_symbol)
6541{
796d6298
TC		 6542 bfd_vma addr, section_vma = 0;
6543 int n, last_sym = -1;
5bc5ae88 6544 bfd_boolean found = FALSE;
796d6298
TC		 6545 bfd_boolean can_use_search_opt_p = FALSE;
6546
6547 /* Default to DATA. A text section is required by the ABI to contain an
6548 INSN mapping symbol at the start. A data section has no such
6549 requirement, hence if no mapping symbol is found the section must
6550 contain only data. This however isn't very useful if the user has
6551 fully stripped the binaries. If this is the case use the section
6552 attributes to determine the default. If we have no section default to
6553 INSN as well, as we may be disassembling some raw bytes on a baremetal
6554 HEX file or similar. */
6555 enum map_type type = MAP_DATA;
6556 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6557 type = MAP_ARM;
5bc5ae88
RL		 6558 struct arm_private_data *private_data;
6559
796d6298 6560 if (info->private_data == NULL
5bc5ae88
RL		 6561 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6562 return FALSE;
6563
6564 private_data = info->private_data;
5bc5ae88 6565
796d6298
TC		 6566 /* First, look for mapping symbols. */
6567 if (info->symtab_size != 0)
6568 {
6569 if (pc <= private_data->last_mapping_addr)
6570 private_data->last_mapping_sym = -1;
6571
6572 /* Start scanning at the start of the function, or wherever
6573 we finished last time. */
6574 n = info->symtab_pos + 1;
6575
6576 /* If the last stop offset is different from the current one it means we
6577 are disassembling a different glob of bytes. As such the optimization
6578 would not be safe and we should start over. */
6579 can_use_search_opt_p
6580 = private_data->last_mapping_sym >= 0
6581 && info->stop_offset == private_data->last_stop_offset;
6582
6583 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6584 n = private_data->last_mapping_sym;
6585
6586 /* Look down while we haven't passed the location being disassembled.
6587 The reason for this is that there's no defined order between a symbol
6588 and an mapping symbol that may be at the same address. We may have to
6589 look at least one position ahead. */
6590 for (; n < info->symtab_size; n++)
6591 {
6592 addr = bfd_asymbol_value (info->symtab[n]);
6593 if (addr > pc)
6594 break;
6595 if (get_map_sym_type (info, n, &type))
6596 {
6597 last_sym = n;
6598 found = TRUE;
6599 }
6600 }
5bc5ae88 6601
796d6298
TC		 6602 if (!found)
6603 {
6604 n = info->symtab_pos;
6605 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6606 n = private_data->last_mapping_sym;
6607
6608 /* No mapping symbol found at this address. Look backwards
6609 for a preceeding one, but don't go pass the section start
6610 otherwise a data section with no mapping symbol can pick up
6611 a text mapping symbol of a preceeding section. The documentation
6612 says section can be NULL, in which case we will seek up all the
6613 way to the top. */
6614 if (info->section)
6615 section_vma = info->section->vma;
6616
6617 for (; n >= 0; n--)
6618 {
6619 addr = bfd_asymbol_value (info->symtab[n]);
6620 if (addr < section_vma)
6621 break;
6622
6623 if (get_map_sym_type (info, n, &type))
6624 {
6625 last_sym = n;
6626 found = TRUE;
6627 break;
6628 }
6629 }
6630 }
6631 }
6632
6633 /* If no mapping symbol was found, try looking up without a mapping
6634 symbol. This is done by walking up from the current PC to the nearest
6635 symbol. We don't actually have to loop here since symtab_pos will
6636 contain the nearest symbol already. */
6637 if (!found)
5bc5ae88 6638 {
796d6298
TC		 6639 n = info->symtab_pos;
6640 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 6641 {
796d6298
TC		 6642 last_sym = n;
6643 found = TRUE;
5bc5ae88
RL		 6644 }
6645 }
6646
796d6298
TC		 6647 private_data->last_mapping_sym = last_sym;
6648 private_data->last_type = type;
6649 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 6650
6651 *map_symbol = type;
6652 return found;
6653}
6654
0313a2b8
NC		 6655/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6656 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 6657 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 6658
6659 FIXME: This could more efficiently implemented as a constant array,
6660 although it would also be less robust. */
6661
6662static void
6663select_arm_features (unsigned long mach,
6664 arm_feature_set * features)
6665{
c0c468d5
TP		 6666 arm_feature_set arch_fset;
6667 const arm_feature_set fpu_any = FPU_ANY;
6668
1af1dd51
MW		 6669#undef ARM_SET_FEATURES
6670#define ARM_SET_FEATURES(FSET) \
6671 { \
6672 const arm_feature_set fset = FSET; \
c0c468d5 6673 arch_fset = fset; \
1af1dd51 6674 }
823d2571 6675
c0c468d5
TP		 6676 /* When several architecture versions share the same bfd_mach_arm_XXX value
6677 the most featureful is chosen. */
0313a2b8
NC		 6678 switch (mach)
6679 {
c0c468d5
TP		 6680 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6681 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6682 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6683 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6684 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6685 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6686 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6687 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6688 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6689 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 6690 case bfd_mach_arm_ep9312:
c0c468d5
TP		 6691 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6692 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 6693 break;
c0c468d5
TP		 6694 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6695 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6696 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6697 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
6698 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6699 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6700 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6701 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6702 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6703 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6704 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6705 case bfd_mach_arm_8:
6706 {
0632eeea
SD		 6707 /* Add bits for extensions that Armv8.5-A recognizes. */
6708 arm_feature_set armv8_5_ext_fset
6709 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6710 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6711 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 6712 break;
6713 }
6714 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6715 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6716 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
031254f2 6717 case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
c0c468d5
TP		 6718 /* If the machine type is unknown allow all architecture types and all
6719 extensions. */
6720 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6721 default:
6722 abort ();
6723 }
1af1dd51 6724#undef ARM_SET_FEATURES
c0c468d5
TP		 6725
6726 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6727 and thus on bfd_mach_arm_XXX value. Therefore for a given
6728 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
6729 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 6730}
6731
6732
58efb6c0
NC		 6733/* NOTE: There are no checks in these routines that
6734 the relevant number of data bytes exist. */
baf0cc5e 6735
58efb6c0 6736static int
4a5329c6 6737print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6738{
c19d1205
ZW		 6739 unsigned char b[4];
6740 long given;
6741 int status;
e821645d 6742 int is_thumb = FALSE;
b0e28b39 6743 int is_data = FALSE;
bd2e2557 6744 int little_code;
e821645d 6745 unsigned int size = 4;
4a5329c6 6746 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6747 bfd_boolean found = FALSE;
b0e28b39 6748 struct arm_private_data *private_data;
58efb6c0 6749
dd92f639
NC		 6750 if (info->disassembler_options)
6751 {
65b48a81 6752 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6753
58efb6c0 6754 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6755 info->disassembler_options = NULL;
6756 }
b34976b6 6757
0313a2b8
NC		 6758 /* PR 10288: Control which instructions will be disassembled. */
6759 if (info->private_data == NULL)
6760 {
b0e28b39 6761 static struct arm_private_data private;
0313a2b8
NC		 6762
6763 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6764 /* If the user did not use the -m command line switch then default to
6765 disassembling all types of ARM instruction.
43e65147 6766
0313a2b8
NC		 6767 The info->mach value has to be ignored as this will be based on
6768 the default archictecture for the target and/or hints in the notes
6769 section, but it will never be greater than the current largest arm
6770 machine value (iWMMXt2), which is only equivalent to the V5TE
6771 architecture. ARM architectures have advanced beyond the machine
6772 value encoding, and these newer architectures would be ignored if
6773 the machine value was used.
6774
6775 Ie the -m switch is used to restrict which instructions will be
6776 disassembled. If it is necessary to use the -m switch to tell
6777 objdump that an ARM binary is being disassembled, eg because the
6778 input is a raw binary file, but it is also desired to disassemble
6779 all ARM instructions then use "-marm". This will select the
6780 "unknown" arm architecture which is compatible with any ARM
6781 instruction. */
6782 info->mach = bfd_mach_arm_unknown;
6783
6784 /* Compute the architecture bitmask from the machine number.
6785 Note: This assumes that the machine number will not change
6786 during disassembly.... */
b0e28b39 6787 select_arm_features (info->mach, & private.features);
0313a2b8 6788
1fbaefec
PB		 6789 private.last_mapping_sym = -1;
6790 private.last_mapping_addr = 0;
796d6298 6791 private.last_stop_offset = 0;
b0e28b39
DJ		 6792
6793 info->private_data = & private;
0313a2b8 6794 }
b0e28b39
DJ		 6795
6796 private_data = info->private_data;
6797
bd2e2557
SS		 6798 /* Decide if our code is going to be little-endian, despite what the
6799 function argument might say. */
6800 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6801
b0e28b39
DJ		 6802 /* For ELF, consult the symbol table to determine what kind of code
6803 or data we have. */
8977d4b2 6804 if (info->symtab_size != 0
e821645d
DJ		 6805 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6806 {
6807 bfd_vma addr;
796d6298 6808 int n;
e821645d 6809 int last_sym = -1;
b0e28b39 6810 enum map_type type = MAP_ARM;
e821645d 6811
796d6298
TC		 6812 found = mapping_symbol_for_insn (pc, info, &type);
6813 last_sym = private_data->last_mapping_sym;
e821645d 6814
1fbaefec
PB		 6815 is_thumb = (private_data->last_type == MAP_THUMB);
6816 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6817
e821645d
DJ		 6818 /* Look a little bit ahead to see if we should print out
6819 two or four bytes of data. If there's a symbol,
6820 mapping or otherwise, after two bytes then don't
6821 print more. */
6822 if (is_data)
6823 {
6824 size = 4 - (pc & 3);
6825 for (n = last_sym + 1; n < info->symtab_size; n++)
6826 {
6827 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6828 if (addr > pc
6829 && (info->section == NULL
6830 || info->section == info->symtab[n]->section))
e821645d
DJ		 6831 {
6832 if (addr - pc < size)
6833 size = addr - pc;
6834 break;
6835 }
6836 }
6837 /* If the next symbol is after three bytes, we need to
6838 print only part of the data, so that we can use either
6839 .byte or .short. */
6840 if (size == 3)
6841 size = (pc & 1) ? 1 : 2;
6842 }
6843 }
6844
6845 if (info->symbols != NULL)
252b5132 6846 {
5876e06d
NC		 6847 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6848 {
2f0ca46a 6849 coff_symbol_type * cs;
b34976b6 6850
5876e06d
NC		 6851 cs = coffsymbol (*info->symbols);
6852 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6853 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6854 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6855 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6856 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6857 }
e821645d
DJ		 6858 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6859 && !found)
5876e06d 6860 {
2087ad84
PB		 6861 /* If no mapping symbol has been found then fall back to the type
6862 of the function symbol. */
e821645d
DJ		 6863 elf_symbol_type * es;
6864 unsigned int type;
2087ad84 6865
e821645d
DJ		 6866 es = *(elf_symbol_type **)(info->symbols);
6867 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6868
39d911fc
TP		 6869 is_thumb =
6870 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6871 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6872 }
e49d43ff
TG		 6873 else if (bfd_asymbol_flavour (*info->symbols)
6874 == bfd_target_mach_o_flavour)
6875 {
6876 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6877
6878 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6879 }
5876e06d 6880 }
b34976b6 6881
e821645d
DJ		 6882 if (force_thumb)
6883 is_thumb = TRUE;
6884
b8f9ee44
CL		 6885 if (is_data)
6886 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6887 else
6888 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6889
c19d1205 6890 info->bytes_per_line = 4;
252b5132 6891
1316c8b3
NC		 6892 /* PR 10263: Disassemble data if requested to do so by the user. */
6893 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6894 {
6895 int i;
6896
1316c8b3 6897 /* Size was already set above. */
e821645d
DJ		 6898 info->bytes_per_chunk = size;
6899 printer = print_insn_data;
6900
fe56b6ce 6901 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6902 given = 0;
6903 if (little)
6904 for (i = size - 1; i >= 0; i--)
6905 given = b[i] | (given << 8);
6906 else
6907 for (i = 0; i < (int) size; i++)
6908 given = b[i] | (given << 8);
6909 }
6910 else if (!is_thumb)
252b5132 6911 {
c19d1205
ZW		 6912 /* In ARM mode endianness is a straightforward issue: the instruction
6913 is four bytes long and is either ordered 0123 or 3210. */
6914 printer = print_insn_arm;
6915 info->bytes_per_chunk = 4;
4a5329c6 6916 size = 4;
c19d1205 6917
0313a2b8 6918 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6919 if (little_code)
c19d1205
ZW		 6920 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6921 else
6922 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6923 }
58efb6c0 6924 else
252b5132 6925 {
c19d1205
ZW		 6926 /* In Thumb mode we have the additional wrinkle of two
6927 instruction lengths. Fortunately, the bits that determine
6928 the length of the current instruction are always to be found
6929 in the first two bytes. */
4a5329c6 6930 printer = print_insn_thumb16;
c19d1205 6931 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6932 size = 2;
6933
fe56b6ce 6934 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6935 if (little_code)
9a2ff3f5
AM		 6936 given = (b[0]) | (b[1] << 8);
6937 else
6938 given = (b[1]) | (b[0] << 8);
6939
c19d1205 6940 if (!status)
252b5132 6941 {
c19d1205
ZW		 6942 /* These bit patterns signal a four-byte Thumb
6943 instruction. */
6944 if ((given & 0xF800) == 0xF800
6945 || (given & 0xF800) == 0xF000
6946 || (given & 0xF800) == 0xE800)
252b5132 6947 {
0313a2b8 6948 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6949 if (little_code)
c19d1205 6950 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6951 else
c19d1205
ZW		 6952 given = (b[1]) | (b[0] << 8) | (given << 16);
6953
6954 printer = print_insn_thumb32;
4a5329c6 6955 size = 4;
252b5132 6956 }
252b5132 6957 }
c22aaad1
PB		 6958
6959 if (ifthen_address != pc)
0313a2b8 6960 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6961
6962 if (ifthen_state)
6963 {
6964 if ((ifthen_state & 0xf) == 0x8)
6965 ifthen_next_state = 0;
6966 else
6967 ifthen_next_state = (ifthen_state & 0xe0)
6968 | ((ifthen_state & 0xf) << 1);
6969 }
252b5132 6970 }
b34976b6 6971
c19d1205
ZW		 6972 if (status)
6973 {
6974 info->memory_error_func (status, pc, info);
6975 return -1;
6976 }
6a56ec7e
NC		 6977 if (info->flags & INSN_HAS_RELOC)
6978 /* If the instruction has a reloc associated with it, then
6979 the offset field in the instruction will actually be the
6980 addend for the reloc. (We are using REL type relocs).
6981 In such cases, we can ignore the pc when computing
6982 addresses, since the addend is not currently pc-relative. */
6983 pc = 0;
b34976b6 6984
4a5329c6 6985 printer (pc, info, given);
c22aaad1
PB		 6986
6987 if (is_thumb)
6988 {
6989 ifthen_state = ifthen_next_state;
6990 ifthen_address += size;
6991 }
4a5329c6 6992 return size;
252b5132
RH		 6993}
6994
6995int
4a5329c6 6996print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6997{
bd2e2557
SS		 6998 /* Detect BE8-ness and record it in the disassembler info. */
6999 if (info->flavour == bfd_target_elf_flavour
7000 && info->section != NULL
7001 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
7002 info->endian_code = BFD_ENDIAN_LITTLE;
7003
b34976b6 7004 return print_insn (pc, info, FALSE);
58efb6c0 7005}
01c7f630 7006
58efb6c0 7007int
4a5329c6 7008print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 7009{
b34976b6 7010 return print_insn (pc, info, TRUE);
58efb6c0 7011}
252b5132 7012
471b9d15 7013const disasm_options_and_args_t *
65b48a81
PB		 7014disassembler_options_arm (void)
7015{
471b9d15 7016 static disasm_options_and_args_t *opts_and_args;
65b48a81 7017
471b9d15 7018 if (opts_and_args == NULL)
65b48a81 7019 {
471b9d15 7020 disasm_options_t *opts;
65b48a81 7021 unsigned int i;
471b9d15
MR		 7022
7023 opts_and_args = XNEW (disasm_options_and_args_t);
7024 opts_and_args->args = NULL;
7025
7026 opts = &opts_and_args->options;
65b48a81
PB		 7027 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
7028 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 7029 opts->arg = NULL;
65b48a81
PB		 7030 for (i = 0; i < NUM_ARM_OPTIONS; i++)
7031 {
7032 opts->name[i] = regnames[i].name;
7033 if (regnames[i].description != NULL)
7034 opts->description[i] = _(regnames[i].description);
7035 else
7036 opts->description[i] = NULL;
7037 }
7038 /* The array we return must be NULL terminated. */
7039 opts->name[i] = NULL;
7040 opts->description[i] = NULL;
7041 }
7042
471b9d15 7043 return opts_and_args;
65b48a81
PB		 7044}
7045
58efb6c0 7046void
4a5329c6 7047print_arm_disassembler_options (FILE *stream)
58efb6c0 7048{
65b48a81 7049 unsigned int i, max_len = 0;
58efb6c0
NC		 7050 fprintf (stream, _("\n\
7051The following ARM specific disassembler options are supported for use with\n\
7052the -M switch:\n"));
b34976b6 7053
65b48a81
PB		 7054 for (i = 0; i < NUM_ARM_OPTIONS; i++)
7055 {
7056 unsigned int len = strlen (regnames[i].name);
7057 if (max_len < len)
7058 max_len = len;
7059 }
58efb6c0 7060
65b48a81
PB		 7061 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
7062 fprintf (stream, " %s%*c %s\n",
7063 regnames[i].name,
7064 (int)(max_len - strlen (regnames[i].name)), ' ',
7065 _(regnames[i].description));
252b5132 7066}
A mirror of the official binutils-gdb repository