opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* ABM New Instructions required */
  91   CpuABM,
  92   /* SSE4.1 support required */
  93   CpuSSE4_1,
  94   /* SSE4.2 support required */
  95   CpuSSE4_2,
  96   /* AVX support required */
  97   CpuAVX,
  98   /* AVX2 support required */
  99   CpuAVX2,
 100   /* Intel AVX-512 Foundation Instructions support required */
 101   CpuAVX512F,
 102   /* Intel AVX-512 Conflict Detection Instructions support required */
 103   CpuAVX512CD,
 104   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 105      required */
 106   CpuAVX512ER,
 107   /* Intel AVX-512 Prefetch Instructions support required */
 108   CpuAVX512PF,
 109   /* Intel AVX-512 VL Instructions support required.  */
 110   CpuAVX512VL,
 111   /* Intel AVX-512 DQ Instructions support required.  */
 112   CpuAVX512DQ,
 113   /* Intel AVX-512 BW Instructions support required.  */
 114   CpuAVX512BW,
 115   /* Intel L1OM support required */
 116   CpuL1OM,
 117   /* Intel K1OM support required */
 118   CpuK1OM,
 119   /* Intel IAMCU support required */
 120   CpuIAMCU,
 121   /* Xsave/xrstor New Instructions support required */
 122   CpuXsave,
 123   /* Xsaveopt New Instructions support required */
 124   CpuXsaveopt,
 125   /* AES support required */
 126   CpuAES,
 127   /* PCLMUL support required */
 128   CpuPCLMUL,
 129   /* FMA support required */
 130   CpuFMA,
 131   /* FMA4 support required */
 132   CpuFMA4,
 133   /* XOP support required */
 134   CpuXOP,
 135   /* LWP support required */
 136   CpuLWP,
 137   /* BMI support required */
 138   CpuBMI,
 139   /* TBM support required */
 140   CpuTBM,
 141   /* MOVBE Instruction support required */
 142   CpuMovbe,
 143   /* CMPXCHG16B instruction support required.  */
 144   CpuCX16,
 145   /* EPT Instructions required */
 146   CpuEPT,
 147   /* RDTSCP Instruction support required */
 148   CpuRdtscp,
 149   /* FSGSBASE Instructions required */
 150   CpuFSGSBase,
 151   /* RDRND Instructions required */
 152   CpuRdRnd,
 153   /* F16C Instructions required */
 154   CpuF16C,
 155   /* Intel BMI2 support required */
 156   CpuBMI2,
 157   /* LZCNT support required */
 158   CpuLZCNT,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* mwaitx instruction required */
 212   CpuMWAITX,
 213   /* Clzero instruction required */
 214   CpuCLZERO,
 215   /* OSPKE instruction required */
 216   CpuOSPKE,
 217   /* RDPID instruction required */
 218   CpuRDPID,
 219   /* PTWRITE instruction required */
 220   CpuPTWRITE,
 221   /* CET instructions support required */
 222   CpuIBT,
 223   CpuSHSTK,
 224   /* GFNI instructions required */
 225   CpuGFNI,
 226   /* VAES instructions required */
 227   CpuVAES,
 228   /* VPCLMULQDQ instructions required */
 229   CpuVPCLMULQDQ,
 230   /* WBNOINVD instructions required */
 231   CpuWBNOINVD,
 232   /* PCONFIG instructions required */
 233   CpuPCONFIG,
 234   /* WAITPKG instructions required */
 235   CpuWAITPKG,
 236   /* CLDEMOTE instruction required */
 237   CpuCLDEMOTE,
 238   /* MOVDIRI instruction support required */
 239   CpuMOVDIRI,
 240   /* MOVDIRR64B instruction required */
 241   CpuMOVDIR64B,
 242   /* 64bit support required  */
 243   Cpu64,
 244   /* Not supported in the 64bit mode  */
 245   CpuNo64,
 246   /* The last bitfield in i386_cpu_flags.  */
 247   CpuMax = CpuNo64
 248 };
 249
 250 #define CpuNumOfUints \
 251   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 252 #define CpuNumOfBits \
 253   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 254
 255 /* If you get a compiler error for zero width of the unused field,
 256    comment it out.  */
 257 #define CpuUnused       (CpuMax + 1)
 258
 259 /* We can check if an instruction is available with array instead
 260    of bitfield. */
 261 typedef union i386_cpu_flags
 262 {
 263   struct
 264     {
 265       unsigned int cpui186:1;
 266       unsigned int cpui286:1;
 267       unsigned int cpui386:1;
 268       unsigned int cpui486:1;
 269       unsigned int cpui586:1;
 270       unsigned int cpui686:1;
 271       unsigned int cpucmov:1;
 272       unsigned int cpufxsr:1;
 273       unsigned int cpuclflush:1;
 274       unsigned int cpunop:1;
 275       unsigned int cpusyscall:1;
 276       unsigned int cpu8087:1;
 277       unsigned int cpu287:1;
 278       unsigned int cpu387:1;
 279       unsigned int cpu687:1;
 280       unsigned int cpufisttp:1;
 281       unsigned int cpummx:1;
 282       unsigned int cpusse:1;
 283       unsigned int cpusse2:1;
 284       unsigned int cpua3dnow:1;
 285       unsigned int cpua3dnowa:1;
 286       unsigned int cpusse3:1;
 287       unsigned int cpupadlock:1;
 288       unsigned int cpusvme:1;
 289       unsigned int cpuvmx:1;
 290       unsigned int cpusmx:1;
 291       unsigned int cpussse3:1;
 292       unsigned int cpusse4a:1;
 293       unsigned int cpuabm:1;
 294       unsigned int cpusse4_1:1;
 295       unsigned int cpusse4_2:1;
 296       unsigned int cpuavx:1;
 297       unsigned int cpuavx2:1;
 298       unsigned int cpuavx512f:1;
 299       unsigned int cpuavx512cd:1;
 300       unsigned int cpuavx512er:1;
 301       unsigned int cpuavx512pf:1;
 302       unsigned int cpuavx512vl:1;
 303       unsigned int cpuavx512dq:1;
 304       unsigned int cpuavx512bw:1;
 305       unsigned int cpul1om:1;
 306       unsigned int cpuk1om:1;
 307       unsigned int cpuiamcu:1;
 308       unsigned int cpuxsave:1;
 309       unsigned int cpuxsaveopt:1;
 310       unsigned int cpuaes:1;
 311       unsigned int cpupclmul:1;
 312       unsigned int cpufma:1;
 313       unsigned int cpufma4:1;
 314       unsigned int cpuxop:1;
 315       unsigned int cpulwp:1;
 316       unsigned int cpubmi:1;
 317       unsigned int cputbm:1;
 318       unsigned int cpumovbe:1;
 319       unsigned int cpucx16:1;
 320       unsigned int cpuept:1;
 321       unsigned int cpurdtscp:1;
 322       unsigned int cpufsgsbase:1;
 323       unsigned int cpurdrnd:1;
 324       unsigned int cpuf16c:1;
 325       unsigned int cpubmi2:1;
 326       unsigned int cpulzcnt:1;
 327       unsigned int cpuhle:1;
 328       unsigned int cpurtm:1;
 329       unsigned int cpuinvpcid:1;
 330       unsigned int cpuvmfunc:1;
 331       unsigned int cpumpx:1;
 332       unsigned int cpulm:1;
 333       unsigned int cpurdseed:1;
 334       unsigned int cpuadx:1;
 335       unsigned int cpuprfchw:1;
 336       unsigned int cpusmap:1;
 337       unsigned int cpusha:1;
 338       unsigned int cpuclflushopt:1;
 339       unsigned int cpuxsaves:1;
 340       unsigned int cpuxsavec:1;
 341       unsigned int cpuprefetchwt1:1;
 342       unsigned int cpuse1:1;
 343       unsigned int cpuclwb:1;
 344       unsigned int cpuavx512ifma:1;
 345       unsigned int cpuavx512vbmi:1;
 346       unsigned int cpuavx512_4fmaps:1;
 347       unsigned int cpuavx512_4vnniw:1;
 348       unsigned int cpuavx512_vpopcntdq:1;
 349       unsigned int cpuavx512_vbmi2:1;
 350       unsigned int cpuavx512_vnni:1;
 351       unsigned int cpuavx512_bitalg:1;
 352       unsigned int cpuavx512_bf16:1;
 353       unsigned int cpumwaitx:1;
 354       unsigned int cpuclzero:1;
 355       unsigned int cpuospke:1;
 356       unsigned int cpurdpid:1;
 357       unsigned int cpuptwrite:1;
 358       unsigned int cpuibt:1;
 359       unsigned int cpushstk:1;
 360       unsigned int cpugfni:1;
 361       unsigned int cpuvaes:1;
 362       unsigned int cpuvpclmulqdq:1;
 363       unsigned int cpuwbnoinvd:1;
 364       unsigned int cpupconfig:1;
 365       unsigned int cpuwaitpkg:1;
 366       unsigned int cpucldemote:1;
 367       unsigned int cpumovdiri:1;
 368       unsigned int cpumovdir64b:1;
 369       unsigned int cpu64:1;
 370       unsigned int cpuno64:1;
 371 #ifdef CpuUnused
 372       unsigned int unused:(CpuNumOfBits - CpuUnused);
 373 #endif
 374     } bitfield;
 375   unsigned int array[CpuNumOfUints];
 376 } i386_cpu_flags;
 377
 378 /* Position of opcode_modifier bits.  */
 379
 380 enum
 381 {
 382   /* has direction bit. */
 383   D = 0,
 384   /* set if operands can be words or dwords encoded the canonical way */
 385   W,
 386   /* load form instruction. Must be placed before store form.  */
 387   Load,
 388   /* insn has a modrm byte. */
 389   Modrm,
 390   /* register is in low 3 bits of opcode */
 391   ShortForm,
 392   /* special case for jump insns.  */
 393   Jump,
 394   /* call and jump */
 395   JumpDword,
 396   /* loop and jecxz */
 397   JumpByte,
 398   /* special case for intersegment leaps/calls */
 399   JumpInterSegment,
 400   /* FP insn memory format bit, sized by 0x4 */
 401   FloatMF,
 402   /* src/dest swap for floats. */
 403   FloatR,
 404   /* needs size prefix if in 32-bit mode */
 405 #define SIZE16 1
 406   /* needs size prefix if in 16-bit mode */
 407 #define SIZE32 2
 408   /* needs size prefix if in 64-bit mode */
 409 #define SIZE64 3
 410   Size,
 411   /* check register size.  */
 412   CheckRegSize,
 413   /* instruction ignores operand size prefix and in Intel mode ignores
 414      mnemonic size suffix check.  */
 415   IgnoreSize,
 416   /* default insn size depends on mode */
 417   DefaultSize,
 418   /* b suffix on instruction illegal */
 419   No_bSuf,
 420   /* w suffix on instruction illegal */
 421   No_wSuf,
 422   /* l suffix on instruction illegal */
 423   No_lSuf,
 424   /* s suffix on instruction illegal */
 425   No_sSuf,
 426   /* q suffix on instruction illegal */
 427   No_qSuf,
 428   /* long double suffix on instruction illegal */
 429   No_ldSuf,
 430   /* instruction needs FWAIT */
 431   FWait,
 432   /* quick test for string instructions */
 433   IsString,
 434   /* quick test if branch instruction is MPX supported */
 435   BNDPrefixOk,
 436   /* quick test if NOTRACK prefix is supported */
 437   NoTrackPrefixOk,
 438   /* quick test for lockable instructions */
 439   IsLockable,
 440   /* fake an extra reg operand for clr, imul and special register
 441      processing for some instructions.  */
 442   RegKludge,
 443   /* An implicit xmm0 as the first operand */
 444   Implicit1stXmm0,
 445   /* The HLE prefix is OK:
 446      1. With a LOCK prefix.
 447      2. With or without a LOCK prefix.
 448      3. With a RELEASE (0xf3) prefix.
 449    */
 450 #define HLEPrefixNone           0
 451 #define HLEPrefixLock           1
 452 #define HLEPrefixAny            2
 453 #define HLEPrefixRelease        3
 454   HLEPrefixOk,
 455   /* An instruction on which a "rep" prefix is acceptable.  */
 456   RepPrefixOk,
 457   /* Convert to DWORD */
 458   ToDword,
 459   /* Convert to QWORD */
 460   ToQword,
 461   /* Address prefix changes register operand */
 462   AddrPrefixOpReg,
 463   /* opcode is a prefix */
 464   IsPrefix,
 465   /* instruction has extension in 8 bit imm */
 466   ImmExt,
 467   /* instruction don't need Rex64 prefix.  */
 468   NoRex64,
 469   /* instruction require Rex64 prefix.  */
 470   Rex64,
 471   /* deprecated fp insn, gets a warning */
 472   Ugh,
 473   /* insn has VEX prefix:
 474         1: 128bit VEX prefix (or operand dependent).
 475         2: 256bit VEX prefix.
 476         3: Scalar VEX prefix.
 477    */
 478 #define VEX128          1
 479 #define VEX256          2
 480 #define VEXScalar       3
 481   Vex,
 482   /* How to encode VEX.vvvv:
 483      0: VEX.vvvv must be 1111b.
 484      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 485         the content of source registers will be preserved.
 486         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 487         where the content of first source register will be overwritten
 488         by the result.
 489         VEX.NDD2.  The second destination register operand is encoded in
 490         VEX.vvvv for instructions with 2 destination register operands.
 491         For assembler, there are no difference between VEX.NDS, VEX.DDS
 492         and VEX.NDD2.
 493      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 494      instructions with 1 destination register operand.
 495      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 496         of the operands can access a memory location.
 497    */
 498 #define VEXXDS  1
 499 #define VEXNDD  2
 500 #define VEXLWP  3
 501   VexVVVV,
 502   /* How the VEX.W bit is used:
 503      0: Set by the REX.W bit.
 504      1: VEX.W0.  Should always be 0.
 505      2: VEX.W1.  Should always be 1.
 506      3: VEX.WIG. The VEX.W bit is ignored.
 507    */
 508 #define VEXW0   1
 509 #define VEXW1   2
 510 #define VEXWIG  3
 511   VexW,
 512   /* VEX opcode prefix:
 513      0: VEX 0x0F opcode prefix.
 514      1: VEX 0x0F38 opcode prefix.
 515      2: VEX 0x0F3A opcode prefix
 516      3: XOP 0x08 opcode prefix.
 517      4: XOP 0x09 opcode prefix
 518      5: XOP 0x0A opcode prefix.
 519    */
 520 #define VEX0F           0
 521 #define VEX0F38         1
 522 #define VEX0F3A         2
 523 #define XOP08           3
 524 #define XOP09           4
 525 #define XOP0A           5
 526   VexOpcode,
 527   /* number of VEX source operands:
 528      0: <= 2 source operands.
 529      1: 2 XOP source operands.
 530      2: 3 source operands.
 531    */
 532 #define XOP2SOURCES     1
 533 #define VEX3SOURCES     2
 534   VexSources,
 535   /* Instruction with vector SIB byte:
 536         1: 128bit vector register.
 537         2: 256bit vector register.
 538         3: 512bit vector register.
 539    */
 540 #define VecSIB128       1
 541 #define VecSIB256       2
 542 #define VecSIB512       3
 543   VecSIB,
 544   /* SSE to AVX support required */
 545   SSE2AVX,
 546   /* No AVX equivalent */
 547   NoAVX,
 548
 549   /* insn has EVEX prefix:
 550         1: 512bit EVEX prefix.
 551         2: 128bit EVEX prefix.
 552         3: 256bit EVEX prefix.
 553         4: Length-ignored (LIG) EVEX prefix.
 554         5: Length determined from actual operands.
 555    */
 556 #define EVEX512                1
 557 #define EVEX128                2
 558 #define EVEX256                3
 559 #define EVEXLIG                4
 560 #define EVEXDYN                5
 561   EVex,
 562
 563   /* AVX512 masking support:
 564         1: Zeroing or merging masking depending on operands.
 565         2: Merging-masking.
 566         3: Both zeroing and merging masking.
 567    */
 568 #define DYNAMIC_MASKING 1
 569 #define MERGING_MASKING 2
 570 #define BOTH_MASKING    3
 571   Masking,
 572
 573   /* AVX512 broadcast support.  The number of bytes to broadcast is
 574      1 << (Broadcast - 1):
 575         1: Byte broadcast.
 576         2: Word broadcast.
 577         3: Dword broadcast.
 578         4: Qword broadcast.
 579    */
 580 #define BYTE_BROADCAST  1
 581 #define WORD_BROADCAST  2
 582 #define DWORD_BROADCAST 3
 583 #define QWORD_BROADCAST 4
 584   Broadcast,
 585
 586   /* Static rounding control is supported.  */
 587   StaticRounding,
 588
 589   /* Supress All Exceptions is supported.  */
 590   SAE,
 591
 592   /* Compressed Disp8*N attribute.  */
 593 #define DISP8_SHIFT_VL 7
 594   Disp8MemShift,
 595
 596   /* Default mask isn't allowed.  */
 597   NoDefMask,
 598
 599   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 600      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 601    */
 602   ImplicitQuadGroup,
 603
 604   /* Support encoding optimization.  */
 605   Optimize,
 606
 607   /* AT&T mnemonic.  */
 608   ATTMnemonic,
 609   /* AT&T syntax.  */
 610   ATTSyntax,
 611   /* Intel syntax.  */
 612   IntelSyntax,
 613   /* AMD64.  */
 614   AMD64,
 615   /* Intel64.  */
 616   Intel64,
 617   /* The last bitfield in i386_opcode_modifier.  */
 618   Opcode_Modifier_Max
 619 };
 620
 621 typedef struct i386_opcode_modifier
 622 {
 623   unsigned int d:1;
 624   unsigned int w:1;
 625   unsigned int load:1;
 626   unsigned int modrm:1;
 627   unsigned int shortform:1;
 628   unsigned int jump:1;
 629   unsigned int jumpdword:1;
 630   unsigned int jumpbyte:1;
 631   unsigned int jumpintersegment:1;
 632   unsigned int floatmf:1;
 633   unsigned int floatr:1;
 634   unsigned int size:2;
 635   unsigned int checkregsize:1;
 636   unsigned int ignoresize:1;
 637   unsigned int defaultsize:1;
 638   unsigned int no_bsuf:1;
 639   unsigned int no_wsuf:1;
 640   unsigned int no_lsuf:1;
 641   unsigned int no_ssuf:1;
 642   unsigned int no_qsuf:1;
 643   unsigned int no_ldsuf:1;
 644   unsigned int fwait:1;
 645   unsigned int isstring:1;
 646   unsigned int bndprefixok:1;
 647   unsigned int notrackprefixok:1;
 648   unsigned int islockable:1;
 649   unsigned int regkludge:1;
 650   unsigned int implicit1stxmm0:1;
 651   unsigned int hleprefixok:2;
 652   unsigned int repprefixok:1;
 653   unsigned int todword:1;
 654   unsigned int toqword:1;
 655   unsigned int addrprefixopreg:1;
 656   unsigned int isprefix:1;
 657   unsigned int immext:1;
 658   unsigned int norex64:1;
 659   unsigned int rex64:1;
 660   unsigned int ugh:1;
 661   unsigned int vex:2;
 662   unsigned int vexvvvv:2;
 663   unsigned int vexw:2;
 664   unsigned int vexopcode:3;
 665   unsigned int vexsources:2;
 666   unsigned int vecsib:2;
 667   unsigned int sse2avx:1;
 668   unsigned int noavx:1;
 669   unsigned int evex:3;
 670   unsigned int masking:2;
 671   unsigned int broadcast:3;
 672   unsigned int staticrounding:1;
 673   unsigned int sae:1;
 674   unsigned int disp8memshift:3;
 675   unsigned int nodefmask:1;
 676   unsigned int implicitquadgroup:1;
 677   unsigned int optimize:1;
 678   unsigned int attmnemonic:1;
 679   unsigned int attsyntax:1;
 680   unsigned int intelsyntax:1;
 681   unsigned int amd64:1;
 682   unsigned int intel64:1;
 683 } i386_opcode_modifier;
 684
 685 /* Position of operand_type bits.  */
 686
 687 enum
 688 {
 689   /* Register (qualified by Byte, Word, etc) */
 690   Reg = 0,
 691   /* MMX register */
 692   RegMMX,
 693   /* Vector registers */
 694   RegSIMD,
 695   /* Vector Mask registers */
 696   RegMask,
 697   /* Control register */
 698   Control,
 699   /* Debug register */
 700   Debug,
 701   /* Test register */
 702   Test,
 703   /* 2 bit segment register */
 704   SReg2,
 705   /* 3 bit segment register */
 706   SReg3,
 707   /* 1 bit immediate */
 708   Imm1,
 709   /* 8 bit immediate */
 710   Imm8,
 711   /* 8 bit immediate sign extended */
 712   Imm8S,
 713   /* 16 bit immediate */
 714   Imm16,
 715   /* 32 bit immediate */
 716   Imm32,
 717   /* 32 bit immediate sign extended */
 718   Imm32S,
 719   /* 64 bit immediate */
 720   Imm64,
 721   /* 8bit/16bit/32bit displacements are used in different ways,
 722      depending on the instruction.  For jumps, they specify the
 723      size of the PC relative displacement, for instructions with
 724      memory operand, they specify the size of the offset relative
 725      to the base register, and for instructions with memory offset
 726      such as `mov 1234,%al' they specify the size of the offset
 727      relative to the segment base.  */
 728   /* 8 bit displacement */
 729   Disp8,
 730   /* 16 bit displacement */
 731   Disp16,
 732   /* 32 bit displacement */
 733   Disp32,
 734   /* 32 bit signed displacement */
 735   Disp32S,
 736   /* 64 bit displacement */
 737   Disp64,
 738   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 739   Acc,
 740   /* Register which can be used for base or index in memory operand.  */
 741   BaseIndex,
 742   /* Register to hold in/out port addr = dx */
 743   InOutPortReg,
 744   /* Register to hold shift count = cl */
 745   ShiftCount,
 746   /* Absolute address for jump.  */
 747   JumpAbsolute,
 748   /* String insn operand with fixed es segment */
 749   EsSeg,
 750   /* RegMem is for instructions with a modrm byte where the register
 751      destination operand should be encoded in the mod and regmem fields.
 752      Normally, it will be encoded in the reg field. We add a RegMem
 753      flag to the destination register operand to indicate that it should
 754      be encoded in the regmem field.  */
 755   RegMem,
 756   /* Memory.  */
 757   Mem,
 758   /* BYTE size. */
 759   Byte,
 760   /* WORD size. 2 byte */
 761   Word,
 762   /* DWORD size. 4 byte */
 763   Dword,
 764   /* FWORD size. 6 byte */
 765   Fword,
 766   /* QWORD size. 8 byte */
 767   Qword,
 768   /* TBYTE size. 10 byte */
 769   Tbyte,
 770   /* XMMWORD size. */
 771   Xmmword,
 772   /* YMMWORD size. */
 773   Ymmword,
 774   /* ZMMWORD size.  */
 775   Zmmword,
 776   /* Unspecified memory size.  */
 777   Unspecified,
 778   /* Any memory size.  */
 779   Anysize,
 780
 781   /* Vector 4 bit immediate.  */
 782   Vec_Imm4,
 783
 784   /* Bound register.  */
 785   RegBND,
 786
 787   /* The number of bitfields in i386_operand_type.  */
 788   OTNum
 789 };
 790
 791 #define OTNumOfUints \
 792   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 793 #define OTNumOfBits \
 794   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 795
 796 /* If you get a compiler error for zero width of the unused field,
 797    comment it out.  */
 798 #define OTUnused                OTNum
 799
 800 typedef union i386_operand_type
 801 {
 802   struct
 803     {
 804       unsigned int reg:1;
 805       unsigned int regmmx:1;
 806       unsigned int regsimd:1;
 807       unsigned int regmask:1;
 808       unsigned int control:1;
 809       unsigned int debug:1;
 810       unsigned int test:1;
 811       unsigned int sreg2:1;
 812       unsigned int sreg3:1;
 813       unsigned int imm1:1;
 814       unsigned int imm8:1;
 815       unsigned int imm8s:1;
 816       unsigned int imm16:1;
 817       unsigned int imm32:1;
 818       unsigned int imm32s:1;
 819       unsigned int imm64:1;
 820       unsigned int disp8:1;
 821       unsigned int disp16:1;
 822       unsigned int disp32:1;
 823       unsigned int disp32s:1;
 824       unsigned int disp64:1;
 825       unsigned int acc:1;
 826       unsigned int baseindex:1;
 827       unsigned int inoutportreg:1;
 828       unsigned int shiftcount:1;
 829       unsigned int jumpabsolute:1;
 830       unsigned int esseg:1;
 831       unsigned int regmem:1;
 832       unsigned int byte:1;
 833       unsigned int word:1;
 834       unsigned int dword:1;
 835       unsigned int fword:1;
 836       unsigned int qword:1;
 837       unsigned int tbyte:1;
 838       unsigned int xmmword:1;
 839       unsigned int ymmword:1;
 840       unsigned int zmmword:1;
 841       unsigned int unspecified:1;
 842       unsigned int anysize:1;
 843       unsigned int vec_imm4:1;
 844       unsigned int regbnd:1;
 845 #ifdef OTUnused
 846       unsigned int unused:(OTNumOfBits - OTUnused);
 847 #endif
 848     } bitfield;
 849   unsigned int array[OTNumOfUints];
 850 } i386_operand_type;
 851
 852 typedef struct insn_template
 853 {
 854   /* instruction name sans width suffix ("mov" for movl insns) */
 855   char *name;
 856
 857   /* how many operands */
 858   unsigned int operands;
 859
 860   /* base_opcode is the fundamental opcode byte without optional
 861      prefix(es).  */
 862   unsigned int base_opcode;
 863 #define Opcode_D        0x2 /* Direction bit:
 864                                set if Reg --> Regmem;
 865                                unset if Regmem --> Reg. */
 866 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 867 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 868 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 869 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 870
 871   /* extension_opcode is the 3 bit extension for group <n> insns.
 872      This field is also used to store the 8-bit opcode suffix for the
 873      AMD 3DNow! instructions.
 874      If this template has no extension opcode (the usual case) use None
 875      Instructions */
 876   unsigned int extension_opcode;
 877 #define None 0xffff             /* If no extension_opcode is possible.  */
 878
 879   /* Opcode length.  */
 880   unsigned char opcode_length;
 881
 882   /* cpu feature flags */
 883   i386_cpu_flags cpu_flags;
 884
 885   /* the bits in opcode_modifier are used to generate the final opcode from
 886      the base_opcode.  These bits also are used to detect alternate forms of
 887      the same instruction */
 888   i386_opcode_modifier opcode_modifier;
 889
 890   /* operand_types[i] describes the type of operand i.  This is made
 891      by OR'ing together all of the possible type masks.  (e.g.
 892      'operand_types[i] = Reg|Imm' specifies that operand i can be
 893      either a register or an immediate operand.  */
 894   i386_operand_type operand_types[MAX_OPERANDS];
 895 }
 896 insn_template;
 897
 898 extern const insn_template i386_optab[];
 899
 900 /* these are for register name --> number & type hash lookup */
 901 typedef struct
 902 {
 903   char *reg_name;
 904   i386_operand_type reg_type;
 905   unsigned char reg_flags;
 906 #define RegRex      0x1  /* Extended register.  */
 907 #define RegRex64    0x2  /* Extended 8 bit register.  */
 908 #define RegVRex     0x4  /* Extended vector register.  */
 909   unsigned char reg_num;
 910 #define RegIP   ((unsigned char ) ~0)
 911 /* EIZ and RIZ are fake index registers.  */
 912 #define RegIZ   (RegIP - 1)
 913 /* FLAT is a fake segment register (Intel mode).  */
 914 #define RegFlat     ((unsigned char) ~0)
 915   signed char dw2_regnum[2];
 916 #define Dw2Inval (-1)
 917 }
 918 reg_entry;
 919
 920 /* Entries in i386_regtab.  */
 921 #define REGNAM_AL 1
 922 #define REGNAM_AX 25
 923 #define REGNAM_EAX 41
 924
 925 extern const reg_entry i386_regtab[];
 926 extern const unsigned int i386_regtab_size;
 927
 928 typedef struct
 929 {
 930   char *seg_name;
 931   unsigned int seg_prefix;
 932 }
 933 seg_entry;
 934
 935 extern const seg_entry cs;
 936 extern const seg_entry ds;
 937 extern const seg_entry ss;
 938 extern const seg_entry es;
 939 extern const seg_entry fs;
 940 extern const seg_entry gs;