iains [Thu, 17 Oct 2019 19:46:52 +0000 (19:46 +0000)]
[Darwin, PPC] Fix PR 65342.
The current Darwin load/store lo_sum patterns have neither predicate nor
constraint. This means that most parts of the backend, which rely on
recog() to validate the rtx, can produce invalid combinations/selections.
For 32bit cases this isn't a problem since we can load/store to unaligned
addresses using D-mode insns.
Conversely, for 64bit instructions that use DS mode, this can manifest as
assemble errors (for an assembler that checks the LO14 relocations), or as
crashes caused by wrong offsets (or worse, wrong content for the two LSBs).
What we want to check for "Y" on Darwin is:
- that the alignment of the Symbols' target is sufficient for DS mode
- that the offset is suitable for DS mode.
(while looking through the Mach-O PIC unspecs).
So, the patch removes the Darwin-specific lo_sum patterns (we begin using
the movdi_internal64 patterns). We also we need to extend the handling of the
mem_operand_gpr constraint to allow looking through Mach-O PIC UNSPECs in
the lo_sum cases.
jason [Thu, 17 Oct 2019 19:09:53 +0000 (19:09 +0000)]
* cp-gimplify.c (cp_gimplify_expr): Use get_initialized_tmp_var.
The comment for get_formal_tmp_var says that it shouldn't be used for
expressions whose value might change between initialization and use, and in
this case we're creating a temporary precisely because the value might
change, so we should use get_initialized_tmp_var instead.
I also noticed that many callers of get_initialized_tmp_var pass NULL for
post_p, so it seems appropriate to make it a default argument.
rguenth [Thu, 17 Oct 2019 17:30:49 +0000 (17:30 +0000)]
2019-10-17 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.
(STMT_VINFO_VEC_COND_REDUC_CODE): Likewise.
* tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not
initialize STMT_VINFO_VEC_COND_REDUC_CODE.
* tree-vect-loop.c (vect_is_simple_reduction): Set
STMT_VINFO_REDUC_CODE.
(vectorizable_reduction): Remove dead and redundant code, use
STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE.
redi [Thu, 17 Oct 2019 15:40:00 +0000 (15:40 +0000)]
Define [range.cmp] comparisons for C++20
Define std::identity, std::ranges::equal_to, std::ranges::not_equal_to,
std::ranges::greater, std::ranges::less, std::ranges::greater_equal and
std::ranges::less_equal.
* include/Makefile.am: Add new header.
* include/Makefile.in: Regenerate.
* include/bits/range_cmp.h: New header for C++20 function objects.
* include/std/functional: Include new header.
* testsuite/20_util/function_objects/identity/1.cc: New test.
* testsuite/20_util/function_objects/range.cmp/equal_to.cc: New test.
* testsuite/20_util/function_objects/range.cmp/greater.cc: New test.
* testsuite/20_util/function_objects/range.cmp/greater_equal.cc: New
test.
* testsuite/20_util/function_objects/range.cmp/less.cc: New test.
* testsuite/20_util/function_objects/range.cmp/less_equal.cc: New test.
* testsuite/20_util/function_objects/range.cmp/not_equal_to.cc: New
test.
gjl [Thu, 17 Oct 2019 15:06:22 +0000 (15:06 +0000)]
Fix breakage introduced by r276985.
* config/avr/avr.c (avr_option_override): Remove set of
PARAM_ALLOW_STORE_DATA_RACES.
* common/config/avr/avr-common.c (avr_option_optimization_table)
[OPT_LEVELS_ALL]: Turn on -fallow-store-data-races.
hjl [Thu, 17 Oct 2019 14:34:15 +0000 (14:34 +0000)]
i386: Add clear_ratio to processor_costs
i386.h has
#define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
It is impossible to have CLEAR_RATIO > 6. This patch adds clear_ratio
to processor_costs, sets it to the minimum of 6 and move_ratio in all
cost models and defines CLEAR_RATIO with clear_ratio.
* config/i386/i386.h (processor_costs): Add clear_ratio.
(CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio.
* config/i386/x86-tune-costs.h: Set clear_ratio to the minimum
of 6 and move_ratio in all cost models.
The container requirements say that for move assignment "All existing
elements of [the target] are either move assigned or destroyed". Some of
our containers currently use __make_move_if_noexcept which makes the
move depend on whether the element type is nothrow move constructible.
This is incorrect, because the standard says we must move assign, not
move or copy depending on the move constructor.
Use make_move_iterator instead so that we move unconditionally. This
ensures existing elements won't be copy assigned.
PR libstdc++/92124
* include/bits/forward_list.h
(_M_move_assign(forward_list&&, false_type)): Do not use
__make_move_if_noexcept, instead move unconditionally.
* include/bits/stl_deque.h (_M_move_assign2(deque&&, false_type)):
Likewise.
* include/bits/stl_list.h (_M_move_assign(list&&, false_type)):
Likewise.
* include/bits/stl_vector.h (_M_move_assign(vector&&, false_type)):
Likewise.
* testsuite/23_containers/vector/92124.cc: New test.
rearnsha [Thu, 17 Oct 2019 13:55:11 +0000 (13:55 +0000)]
[arm] Add default FPU for Marvell-pj4
According to GAS, the Marvell PJ4 CPU has a VFPv3-D16 floating point
unit, but GCC's CPU configuration tables omits this meaning that
-mfpu=auto will not correctly select the FPU. This patch fixes this
by adding the +fp option to the architecture specification for this
device.
* config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.
rsandifo [Thu, 17 Oct 2019 13:23:52 +0000 (13:23 +0000)]
[AArch64][SVE2] Support for EOR3 and variants of BSL
2019-10-17 Yuliang Wang <yuliang.wang@arm.com>
gcc/
* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
(aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
(aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
(aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
New combine patterns.
* config/aarch64/iterators.md (BSL_DUP): New int iterator for the
above.
(bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.
gcc/testsuite/
* gcc.target/aarch64/sve2/eor3_1.c: New test.
* gcc.target/aarch64/sve2/nlogic_1.c: As above.
* gcc.target/aarch64/sve2/nlogic_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_1.c: As above.
* gcc.target/aarch64/sve2/bitsel_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_3.c: As above.
* gcc.target/aarch64/sve2/bitsel_4.c: As above.
nathan [Thu, 17 Oct 2019 12:04:51 +0000 (12:04 +0000)]
[C++ PATCH] builtin fn creation
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01283.html
* decl.c (builtin_function_1): Merge into ...
(cxx_builtin_function): ... here. Nadger the decl before maybe
copying it. Set the context.
(cxx_builtin_function_ext_scope): Push to top level, then call
cxx_builtin_function.
wilson [Wed, 16 Oct 2019 21:01:25 +0000 (21:01 +0000)]
RISC-V: Include more registers in SIBCALL_REGS.
This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It
also adds the missing riscv_regno_to_class change.
Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions. I see about a 0.01% code size reduction for the
C and libstdc++ libraries.
gcc/
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
regs to SIBCALL_REGS.
* config/riscv/riscv.c (riscv_regno_to_class): Change argument
passing regs to SIBCALL_REGS.
msebor [Wed, 16 Oct 2019 19:24:36 +0000 (19:24 +0000)]
PR tree-optimization/83821 - local aggregate initialization defeats strlen optimization
gcc/ChangeLog:
PR tree-optimization/83821
* tree-ssa-strlen.c (maybe_invalidate): Add argument. Consider
the length of a string when available.
(handle_builtin_memset) Add argument.
(handle_store, strlen_check_and_optimize_call): Same.
(check_and_optimize_stmt): Same. Pass it to callees.
PR tree-optimization/91996
* gcc.dg/strlenopt-80.c: New test.
* gcc.dg/strlenopt-81.c: New test.
gcc/ChangeLog:
PR tree-optimization/91996
* tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
information.
(compare_nonzero_chars): Add an overload.
(count_nonzero_bytes): Add an argument. Call overload above.
Handle non-constant lengths in some range.
(handle_store): Add an argument.
(check_and_optimize_stmt): Pass an argument to handle_store.
rearnsha [Wed, 16 Oct 2019 16:44:34 +0000 (16:44 +0000)]
[arm] fix bootstrap failure due to uninitialized warning
The Arm port is failing bootstrap because GCC is now warning about an
unitialized array.
The code is complex enough that I certainly can't be sure the compiler
is wrong, so perhaps the best fix here is just to memset the entire
array before use.
* config/arm/arm.c (neon_valid_immediate): Clear bytes before use.
law [Wed, 16 Oct 2019 15:14:17 +0000 (15:14 +0000)]
* config/mips/mips.c (mips_expand_builtin_insn): Force the
operands which correspond to the same input-output register to
have the same pseudo assigned to them.
wilco [Wed, 16 Oct 2019 14:24:41 +0000 (14:24 +0000)]
[AArch64] Fix symbol offset limit
In aarch64_classify_symbol symbols are allowed large offsets on relocations.
This means the offset can use all of the +/-4GB offset, leaving no offset
available for the symbol itself. This results in relocation overflow and
link-time errors for simple expressions like &global_array + 0xffffff00.
To avoid this, unless the offset_within_block_p is true, limit the offset
to +/-1MB so that the symbol needs to be within a 3.9GB offset from its
references. For the tiny code model use a 64KB offset, allowing most of
the 1MB range for code/data between the symbol and its references.
gcc/
* config/aarch64/aarch64.c (aarch64_classify_symbol):
Apply reasonable limit to symbol offsets.
rguenth [Wed, 16 Oct 2019 14:21:06 +0000 (14:21 +0000)]
2019-10-16 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (vect_valid_reduction_input_p): Remove.
(vect_is_simple_reduction): Delay checking to
vectorizable_reduction and relax the checking.
(vectorizable_reduction): Check we have a simple use. Check
for bogus condition reductions.
* tree-vect-stmts.c (vect_transform_stmt): Make sure we
are looking at the last stmt in a pattern sequence when
filling in backedge PHI values.
* gcc.dg/vect/vect-cond-reduc-3.c: New testcase.
* gcc.dg/vect/vect-cond-reduc-4.c: Likewise.
guojiufu [Wed, 16 Oct 2019 13:35:41 +0000 (13:35 +0000)]
In PR70010, a function is marked with target(no-vsx) to disable VSX code
generation. To avoid VSX code generation, this function should not be
inlined into VSX function. To fix the bug, in the current logic when
checking whether the caller's ISA flags supports the callee's ISA flags, we
just need to add a test that enforces that the caller's ISA flags match
exactly the callee's flags, for those flags that were explicitly set in the
callee. If caller without target attribute then using options from command
line.
gcc/
2019-10-16 Peter Bergner <bergner@linux.ibm.com>
Jiufu Guo <guojiufu@linux.ibm.com>
PR target/70010
* config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if
the callee explicitly disables some isa_flags the caller is using.
gcc.testsuite/
2019-10-16 Peter Bergner <bergner@linux.ibm.com>
Jiufu Guo <guojiufu@linux.ibm.com>
PR target/70010
* gcc.target/powerpc/pr70010.c: New test.
* gcc.target/powerpc/pr70010-1.c: New test.
* gcc.target/powerpc/pr70010-2.c: New test.
* gcc.target/powerpc/pr70010-3.c: New test.
* gcc.target/powerpc/pr70010-4.c: New test.
rsandifo [Wed, 16 Oct 2019 10:53:40 +0000 (10:53 +0000)]
[AArch64] Add partial SVE vector modes
This patch adds extra vector modes that represent a half, quarter or
eighth of what an SVE vector can hold. This is useful for describing
the memory vector involved in an extending load or truncating store.
It might also be useful in future for representing "unpacked" SVE
registers, i.e. registers that contain values in the low bits of a
wider containing element.
The new modes could have the same width as an Advanced SIMD mode for
certain -msve-vector-bits=N options, so we need to ensure that they
come later in the mode list and that Advanced SIMD modes always "win".
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* genmodes.c (mode_data::order): New field.
(blank_mode): Update accordingly.
(VECTOR_MODES_WITH_PREFIX): Add an order parameter.
(make_vector_modes): Likewise.
(VECTOR_MODES): Update use accordingly.
(cmp_modes): Sort by the new order field ahead of sorting by size.
* config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI)
(VNx4QI, VNx4HI, VNx8QI): New partial vector modes.
* config/aarch64/aarch64.c (VEC_PARTIAL): New flag value.
(aarch64_classify_vector_mode): Handle the new partial modes.
(aarch64_vl_bytes): New function.
(aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR
when counting the number of registers in an SVE mode.
(aarch64_class_max_nregs): Likewise.
(aarch64_hard_regno_mode_ok): Don't allow partial vectors
in registers yet.
(aarch64_classify_address): Treat partial vectors analogously
to full vectors.
(aarch64_print_address_internal): Consolidate the printing of
MUL VL addresses, using aarch64_vl_bytes as the number of
bytes represented by "VL".
(aarch64_vector_mode_supported_p): Reject partial vector modes.
rsandifo [Wed, 16 Oct 2019 10:50:53 +0000 (10:50 +0000)]
[AArch64] Improve poly_int handling in aarch64_layout_frame
I'd used known_lt when converting these conditions to poly_int,
but on reflection that was a bad choice. The code isn't just
doing a range check; it specifically needs constants that will
fit in a certain encoding.
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Use is_constant
rather than known_lt when choosing frame layouts.
rsandifo [Wed, 16 Oct 2019 10:48:00 +0000 (10:48 +0000)]
[AArch64] Add an assert to aarch64_layout_frame
This patch adds an assert that all the individual *_adjust allocations
add up to the full frame size. With that safety net, it seemed slightly
clearer to use crtl->outgoing_args_size as the final adjustment where
appropriate, to match what's used in the comments.
This is a bit overkill on its own, but I need to add more cases for SVE.
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Assert
that all the adjustments add up to the full frame size.
Use crtl->outgoing_args_size directly as the final adjustment
where appropriate.
rsandifo [Wed, 16 Oct 2019 10:44:31 +0000 (10:44 +0000)]
[AArch64] Use frame reference in aarch64_layout_frame
Using the full path "cfun->machine->frame" in aarch64_layout_frame
led to awkward formatting in some follow-on patches, so it seemed
worth using a local reference instead.
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Use a local
"frame" reference instead of always referring directly to
"cfun->machine->frame".
redi [Wed, 16 Oct 2019 10:26:05 +0000 (10:26 +0000)]
Only use GCC-specific __is_same_as built-in conditionally
Clang doesn't support __is_same_as but provides __is_same instead.
Restore the original implementation (pre r276891) when neither of those
built-ins is available.
* include/bits/c++config (_GLIBCXX_BUILTIN_IS_SAME_AS): Define to
one of __is_same_as or __is_same when available.
* include/std/concepts (__detail::__same_as): Use std::is_same_v.
* include/std/type_traits (is_same) [_GLIBCXX_BUILTIN_IS_SAME_AS]:
Use new macro instead of __is_same_as.
(is_same) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Restore partial
specialization.
(is_same_v) [_GLIBCXX_BUILTIN_IS_SAME_AS]: Use new macro.
(is_same_v) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Use std::is_same.
rsandifo [Wed, 16 Oct 2019 09:50:44 +0000 (09:50 +0000)]
Deal with incoming POLY_INT_CST ranges (PR92033)
This patch makes value_range_base::set convert POLY_INT_CST bounds
into the worst-case INTEGER_CST bounds. The main case in which this
gives useful ranges is a lower bound of A + B * X becoming A when B >= 0.
E.g.:
danglin [Tue, 15 Oct 2019 22:17:14 +0000 (22:17 +0000)]
* config/pa/fptr.c (_dl_read_access_allowed): Change argument to
unsigned int. Adjust callers.
(__canonicalize_funcptr_for_compare): Change plabel type to volatile
unsigned int *. Load relocation offset before function pointer.
Add barrier to ensure ordering.
iains [Tue, 15 Oct 2019 20:15:38 +0000 (20:15 +0000)]
[Darwin] Update darwin_binds_local_p.
The use of default_binds_local_p had got out of sync with the varasm
changes, this restores the call to be direct. In practice, we add some
further tests to determine local binding - but this callback is used for
the initial assessments made by default_encode_section_info().
nathan [Tue, 15 Oct 2019 12:27:21 +0000 (12:27 +0000)]
[C++ PATCH] clone_function_decl breakup
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01083.html
This patch, from the modules branch, breaks out function cloning from the
method vector updating. We have a new function, build_clones,
which does the building, returning a count of the number of clones
(2 or 3). clone_function_decl separately adds them to the method
vector, if they should be added. I suppose this could have used
FOR_EVERY_CLONE, but I went with the counting scheme.
* class.c (build_clones): Break out of clone_function_decl. Just
build the clones.
(clone_function_decl): Call build_clones, then maybe add them to
the method vector.
jozefl [Tue, 15 Oct 2019 12:24:53 +0000 (12:24 +0000)]
2019-10-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/msp430/msp430.md (zero_extendqipsi2): New.
(zero_extendqisi2): Optimize case where src register and base dst
register are the same.
(zero_extendhipsi2): Don't use 430X insn for rYs->r case.
(zero_extendpsisi2): Optimize r->m case.
Add unnamed insn patterns to catch insns combine searches for when
optimizing pointer manipulation.
nathan [Tue, 15 Oct 2019 12:03:04 +0000 (12:03 +0000)]
[linemap PATCH] Constify lookup
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01080.html
looking up a line map takes a non-constant line_maps object, which is confusing.
This makes the caching fields mutable, so permits a constant object, as one might expect for a lookup.
rguenth [Tue, 15 Oct 2019 11:47:27 +0000 (11:47 +0000)]
2019-10-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/91929
* tree-ssa-pre.c (pre_expr_d::loc): New member.
(get_or_alloc_expr_for_name): Initialize it.
(get_or_alloc_expr_for_constant): Likewise.
(phi_translate_1): Copy it.
(create_expression_by_pieces): Use the original location
of the expression for the inserted stmt.
(compute_avail): Record the location of the stmt for the
expressions created.
nathan [Tue, 15 Oct 2019 11:20:06 +0000 (11:20 +0000)]
[C++ PATCH] build_clone cleanup
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01069.html
build_clone is recursive when applied to a template, but I found the control flow confusing. this makes it clearer and moves some decls to their initializers.
* class.c (build_clone): Refactor to clarify recursiveness.
rguenth [Tue, 15 Oct 2019 10:09:10 +0000 (10:09 +0000)]
2019-10-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/92094
* tree-vect-loop.c (vectorizable_reduction): For nested cycles
do not adjust the reduction definition def type.
* tree-vect-stmts.c (vect_transform_stmt): Verify the scalar stmt
defines the latch argument of the PHI.
PR tree-optimization/92085
* tree-if-conv.c (ifcvt_local_dce): Call gsi_next in else clause,
instead of calling it unconditionally after
delete_dead_or_redundant_assignment and fix indentation.
testsuite/
* gcc.dg/tree-ssa/pr92085-1.c: New test.
* gcc.dg/tree-ssa/pr92085-2.c: Likewise.
kargl [Tue, 15 Oct 2019 00:28:47 +0000 (00:28 +0000)]
2019-10-14 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/89943
decl.c (gfc_match_function_decl): Ignore duplicate BIND(C) for function
declaration in submodule. Implement at check for F2018 C1550.
(gfc_match_entry): Use temporary for locus, which allows removal of
one gfc_error_now().
(gfc_match_subroutine): Ignore duplicate BIND(C) for subroutine
declaration in submodule. Implement at check for F2018 C1550.
jsm28 [Tue, 15 Oct 2019 00:12:49 +0000 (00:12 +0000)]
Rename attribute-related functions and productions in C parser.
The C2x attribute syntax, [[ ]], appears in different places in the
syntax from GNU __attribute__, and, where they can appear in the same
place in the syntax, they do not always appertain to the same entity.
(For example, in "int func(void) ATTRS;", GNU attributes appertain to
the declaration but C2x attributes appertain to the function type.)
Thus, the C parser needs to handle the two kinds of attributes
separately, with each place in the syntax accepting whatever kinds of
attributes are appropriate there and applying them to the relevant
entities. This patch prepares for this by renaming parser functions
relating to attributes to make clear they are specifically about GNU
attributes and renaming syntax productions likewise to avoid confusing
with the C2x attributes syntax productions.
Where comments refer to attributes, this has only be changed where it
is clear that in the context they are referring specifically to the
gnu-attributes syntax. There may be other places that also end up
changing to refer to gnu-attributes as part of the C2x attributes
implementation, if more detailed examination of those places shows
they are also specific to gnu-attributes. (I do not expect code
dealing with semantics of attributes outside of the parser to need to
change; as for C++, it will be possible to use existing attributes
inside [[]] with the gnu:: form of the attribute name.)
Bootstrapped with no regressions on x86_64-pc-linux-gnu.
* c-parser.c (c_parser_attribute_any_word): Rename to
c_parser_gnu_attribute_any_word. All callers changed.
(c_parser_attribute): Rename to c_parser_gnu_attribute. All
callers changed.
(c_parser_attributes): Rename to c_parser_gnu_attributes. All
callers changed.
(c_parser_declaration_or_fndef, c_parser_declspecs)
(c_parser_enum_specifier, c_parser_struct_or_union_specifier)
(c_parser_struct_declaration, c_parser_declarator)
(c_parser_gnu_attribute, c_parser_compound_statement)
(c_parser_label, c_parser_statement, c_parser_objc_method_decl)
(c_parser_transaction_attributes): Add "gnu-" prefix to names of
attribute-related syntax productions.
ian [Mon, 14 Oct 2019 23:12:33 +0000 (23:12 +0000)]
compiler: revise exportdata fix for processing constant types
This patch is an addendum to the fix for issue 34577, which was not
sufficiently general. During export data processing, when looking at
the types of constants mentioned in inlinable function bodies, include
both locally defined constants and constant imported from other
packages.
tkoenig [Mon, 14 Oct 2019 21:37:34 +0000 (21:37 +0000)]
2019-10-14 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/92004
* array.c (expand_constructor): Set from_constructor on
expression.
* gfortran.h (gfc_symbol): Add maybe_array.
(gfc_expr): Add from_constructor.
* interface.c (maybe_dummy_array_arg): New function.
(compare_parameter): If the formal argument is generated from a
call, check the conditions where an array element could be
passed to an array. Adjust error message for assumed-shape
or pointer array. Use correct language for assumed shaped arrays.
(gfc_get_formal_from_actual_arglist): Set maybe_array on the
symbol if the actual argument is an array element fulfilling
the conditions of 15.5.2.4.
jason [Mon, 14 Oct 2019 20:13:49 +0000 (20:13 +0000)]
PR c++/91930 - ICE with constrained inherited default ctor.
The testcase was crashing because lazily_declare_fn was failing to add a
defaulted constructor, because the implicit declaration was less constrained
than the inherited default constructor. But when we have an inherited
constructor, we shouldn't be trying to declare a default constructor in the
first place, because it counts as "a user-declared constructor". With that
fixed I needed to adjust a couple of inherited constructor testcases that
previously had been diagnosing the default constructor as deleted rather
than not declared.
* name-lookup.c (do_class_using_decl): Set TYPE_HAS_USER_CONSTRUCTOR
for inherited constructor.
iains [Mon, 14 Oct 2019 19:18:34 +0000 (19:18 +0000)]
[Darwin, machopic 9/n] Minor code clean-ups.
Improve some comments, replace some asserts that have been in the code
base for years with checking-asserts.
gcc/ChangeLog:
2019-10-14 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.c: Use unsigned ints for the picbase label
counters, initialise the vars explicitly.
(update_pic_label_number_if_needed): Move a variable declaration
to where it's needed.
(machopic_output_function_base_name): Use a more strict checking
assert, and and unsigned int for the picbase label counter.
(machopic_get_function_picbase): Likewise.
rguenth [Mon, 14 Oct 2019 14:03:35 +0000 (14:03 +0000)]
2019-10-14 Richard Biener <rguenther@suse.de>
PR middle-end/92046
* dse.c (scan_insn): Use param max_active_local_stores.
(dse_step1): Get PARAM_MAX_DSE_ACTIVE_LOCAL_STORES and adjust
based on optimization level.
* loop-invariant.c (move_loop_invariants): Adjust
LOOP_INVARIANT_MAX_BBS_IN_LOOP based on optimization level.
* opts.c (default_options_optimization): Do not adjust
PARAM_MAX_DSE_ACTIVE_LOCAL_STORES and
LOOP_INVARIANT_MAX_BBS_IN_LOOP here.
wilco [Mon, 14 Oct 2019 12:25:00 +0000 (12:25 +0000)]
[ARM] Enable arm_legitimize_address for Thumb-2
Currently arm_legitimize_address doesn't handle Thumb-2 at all, resulting in
inefficient code. Since Thumb-2 supports similar address offsets use the Arm
legitimization code for Thumb-2 to get significant codesize and performance
gains. SPECINT2006 shows 0.4% gain on Cortex-A57, while SPECFP improves 0.2%.
wilco [Mon, 14 Oct 2019 12:21:14 +0000 (12:21 +0000)]
[ARM] Switch to default sched pressure algorithm
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. Building SPEC2006 showed significant codesize gains
with the default pressure algorithm, so switch back to that. PR77308 shows
~800 fewer instructions.
SPECINT2006 is ~0.6% faster on Cortex-A57 together with the other DImode
patches. Overall SPEC codesize is 1.1% smaller.
projects / thirdparty / gcc.git / log
