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KVM: add memslots argument to kvm_arch_memslots_updated
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
92a1f12d
JR		 102bool kvm_has_tsc_control;
103EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104u32 kvm_max_guest_tsc_khz;
105EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
cc578287
ZA		 107/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108static u32 tsc_tolerance_ppm = 250;
109module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
d0659d94
MT		 111/* lapic timer advance (tscdeadline mode only) in nanoseconds */
112unsigned int lapic_timer_advance_ns = 0;
113module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
16a96021
MT		 115static bool backwards_tsc_observed = false;
116
18863bdd
AK		 117#define KVM_NR_SHARED_MSRS 16
118
119struct kvm_shared_msrs_global {
120 int nr;
2bf78fa7 121 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 122};
123
124struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
2bf78fa7
SY		 127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 131};
132
133static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 134static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 135
417bc304 136struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 147 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 149 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 150 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 151 { "request_irq", VCPU_STAT(request_irq_exits) },
152 { "irq_exits", VCPU_STAT(irq_exits) },
153 { "host_state_reload", VCPU_STAT(host_state_reload) },
154 { "efer_reload", VCPU_STAT(efer_reload) },
155 { "fpu_reload", VCPU_STAT(fpu_reload) },
156 { "insn_emulation", VCPU_STAT(insn_emulation) },
157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 158 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 159 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164 { "mmu_flooded", VM_STAT(mmu_flooded) },
165 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 167 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 169 { "largepages", VM_STAT(lpages) },
417bc304
HB		 170 { NULL }
171};
172
2acf923e
DC		 173u64 __read_mostly host_xcr0;
174
b6785def 175static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 176
af585b92
GN		 177static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178{
179 int i;
180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181 vcpu->arch.apf.gfns[i] = ~0;
182}
183
18863bdd
AK		 184static void kvm_on_user_return(struct user_return_notifier *urn)
185{
186 unsigned slot;
18863bdd
AK		 187 struct kvm_shared_msrs *locals
188 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 189 struct kvm_shared_msr_values *values;
18863bdd
AK		 190
191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 192 values = &locals->values[slot];
193 if (values->host != values->curr) {
194 wrmsrl(shared_msrs_global.msrs[slot], values->host);
195 values->curr = values->host;
18863bdd
AK		 196 }
197 }
198 locals->registered = false;
199 user_return_notifier_unregister(urn);
200}
201
2bf78fa7 202static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 203{
18863bdd 204 u64 value;
013f6a5d
MT		 205 unsigned int cpu = smp_processor_id();
206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 207
2bf78fa7
SY		 208 /* only read, and nobody should modify it at this time,
209 * so don't need lock */
210 if (slot >= shared_msrs_global.nr) {
211 printk(KERN_ERR "kvm: invalid MSR slot!");
212 return;
213 }
214 rdmsrl_safe(msr, &value);
215 smsr->values[slot].host = value;
216 smsr->values[slot].curr = value;
217}
218
219void kvm_define_shared_msr(unsigned slot, u32 msr)
220{
0123be42 221 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 222 if (slot >= shared_msrs_global.nr)
223 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 224 shared_msrs_global.msrs[slot] = msr;
225 /* we need ensured the shared_msr_global have been updated */
226 smp_wmb();
18863bdd
AK		 227}
228EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230static void kvm_shared_msr_cpu_online(void)
231{
232 unsigned i;
18863bdd
AK		 233
234 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 235 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 236}
237
8b3c3104 238int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 239{
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 242 int err;
18863bdd 243
2bf78fa7 244 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 245 return 0;
2bf78fa7 246 smsr->values[slot].curr = value;
8b3c3104
AH		 247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248 if (err)
249 return 1;
250
18863bdd
AK		 251 if (!smsr->registered) {
252 smsr->urn.on_user_return = kvm_on_user_return;
253 user_return_notifier_register(&smsr->urn);
254 smsr->registered = true;
255 }
8b3c3104 256 return 0;
18863bdd
AK		 257}
258EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
13a34e06 260static void drop_user_return_notifiers(void)
3548bab5 261{
013f6a5d
MT		 262 unsigned int cpu = smp_processor_id();
263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 264
265 if (smsr->registered)
266 kvm_on_user_return(&smsr->urn);
267}
268
6866b83e
CO		 269u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270{
8a5a87d9 271 return vcpu->arch.apic_base;
6866b83e
CO		 272}
273EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
58cb628d
JK		 275int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276{
277 u64 old_state = vcpu->arch.apic_base &
278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279 u64 new_state = msr_info->data &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284 if (!msr_info->host_initiated &&
285 ((msr_info->data & reserved_bits) != 0 ||
286 new_state == X2APIC_ENABLE ||
287 (new_state == MSR_IA32_APICBASE_ENABLE &&
288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290 old_state == 0)))
291 return 1;
292
293 kvm_lapic_set_base(vcpu, msr_info->data);
294 return 0;
6866b83e
CO		 295}
296EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
2605fc21 298asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 299{
300 /* Fault while not rebooting. We want the trace. */
301 BUG();
302}
303EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
3fd28fce
ED		 305#define EXCPT_BENIGN 0
306#define EXCPT_CONTRIBUTORY 1
307#define EXCPT_PF 2
308
309static int exception_class(int vector)
310{
311 switch (vector) {
312 case PF_VECTOR:
313 return EXCPT_PF;
314 case DE_VECTOR:
315 case TS_VECTOR:
316 case NP_VECTOR:
317 case SS_VECTOR:
318 case GP_VECTOR:
319 return EXCPT_CONTRIBUTORY;
320 default:
321 break;
322 }
323 return EXCPT_BENIGN;
324}
325
d6e8c854
NA		 326#define EXCPT_FAULT 0
327#define EXCPT_TRAP 1
328#define EXCPT_ABORT 2
329#define EXCPT_INTERRUPT 3
330
331static int exception_type(int vector)
332{
333 unsigned int mask;
334
335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336 return EXCPT_INTERRUPT;
337
338 mask = 1 << vector;
339
340 /* #DB is trap, as instruction watchpoints are handled elsewhere */
341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342 return EXCPT_TRAP;
343
344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345 return EXCPT_ABORT;
346
347 /* Reserved exceptions will result in fault */
348 return EXCPT_FAULT;
349}
350
3fd28fce 351static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 352 unsigned nr, bool has_error, u32 error_code,
353 bool reinject)
3fd28fce
ED		 354{
355 u32 prev_nr;
356 int class1, class2;
357
3842d135
AK		 358 kvm_make_request(KVM_REQ_EVENT, vcpu);
359
3fd28fce
ED		 360 if (!vcpu->arch.exception.pending) {
361 queue:
3ffb2468
NA		 362 if (has_error && !is_protmode(vcpu))
363 has_error = false;
3fd28fce
ED		 364 vcpu->arch.exception.pending = true;
365 vcpu->arch.exception.has_error_code = has_error;
366 vcpu->arch.exception.nr = nr;
367 vcpu->arch.exception.error_code = error_code;
3f0fd292 368 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 369 return;
370 }
371
372 /* to check exception */
373 prev_nr = vcpu->arch.exception.nr;
374 if (prev_nr == DF_VECTOR) {
375 /* triple fault -> shutdown */
a8eeb04a 376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 377 return;
378 }
379 class1 = exception_class(prev_nr);
380 class2 = exception_class(nr);
381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383 /* generate double fault per SDM Table 5-5 */
384 vcpu->arch.exception.pending = true;
385 vcpu->arch.exception.has_error_code = true;
386 vcpu->arch.exception.nr = DF_VECTOR;
387 vcpu->arch.exception.error_code = 0;
388 } else
389 /* replace previous exception with a new one in a hope
390 that instruction re-execution will regenerate lost
391 exception */
392 goto queue;
393}
394
298101da
AK		 395void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396{
ce7ddec4 397 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 398}
399EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
ce7ddec4
JR		 401void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402{
403 kvm_multiple_exception(vcpu, nr, false, 0, true);
404}
405EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
db8fcefa 407void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 408{
db8fcefa
AP		 409 if (err)
410 kvm_inject_gp(vcpu, 0);
411 else
412 kvm_x86_ops->skip_emulated_instruction(vcpu);
413}
414EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 415
6389ee94 416void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 417{
418 ++vcpu->stat.pf_guest;
6389ee94
AK		 419 vcpu->arch.cr2 = fault->address;
420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 421}
27d6c865 422EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 423
ef54bcfe 424static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 425{
6389ee94
AK		 426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 428 else
6389ee94 429 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 430
431 return fault->nested_page_fault;
d4f8cf66
JR		 432}
433
3419ffc8
SY		 434void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435{
7460fb4a
AK		 436 atomic_inc(&vcpu->arch.nmi_queued);
437 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 438}
439EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
298101da
AK		 441void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442{
ce7ddec4 443 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 444}
445EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
ce7ddec4
JR		 447void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448{
449 kvm_multiple_exception(vcpu, nr, true, error_code, true);
450}
451EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
0a79b009
AK		 453/*
454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
455 * a #GP and return false.
456 */
457bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 458{
0a79b009
AK		 459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460 return true;
461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462 return false;
298101da 463}
0a79b009 464EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 465
16f8a6f9
NA		 466bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467{
468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469 return true;
470
471 kvm_queue_exception(vcpu, UD_VECTOR);
472 return false;
473}
474EXPORT_SYMBOL_GPL(kvm_require_dr);
475
ec92fe44
JR		 476/*
477 * This function will be used to read from the physical memory of the currently
478 * running guest. The difference to kvm_read_guest_page is that this function
479 * can read from guest physical or from the guest's guest physical memory.
480 */
481int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482 gfn_t ngfn, void *data, int offset, int len,
483 u32 access)
484{
54987b7a 485 struct x86_exception exception;
ec92fe44
JR		 486 gfn_t real_gfn;
487 gpa_t ngpa;
488
489 ngpa = gfn_to_gpa(ngfn);
54987b7a 490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 491 if (real_gfn == UNMAPPED_GVA)
492 return -EFAULT;
493
494 real_gfn = gpa_to_gfn(real_gfn);
495
496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497}
498EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
69b0049a 500static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 501 void *data, int offset, int len, u32 access)
502{
503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504 data, offset, len, access);
505}
506
a03490ed
CO		 507/*
508 * Load the pae pdptrs. Return true is they are all valid.
509 */
ff03a073 510int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 511{
512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514 int i;
515 int ret;
ff03a073 516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 517
ff03a073
JR		 518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519 offset * sizeof(u64), sizeof(pdpte),
520 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 521 if (ret < 0) {
522 ret = 0;
523 goto out;
524 }
525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 526 if (is_present_gpte(pdpte[i]) &&
20c466b5 527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 528 ret = 0;
529 goto out;
530 }
531 }
532 ret = 1;
533
ff03a073 534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 535 __set_bit(VCPU_EXREG_PDPTR,
536 (unsigned long *)&vcpu->arch.regs_avail);
537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 539out:
a03490ed
CO		 540
541 return ret;
542}
cc4b6871 543EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 544
d835dfec
AK		 545static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546{
ff03a073 547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 548 bool changed = true;
3d06b8bf
JR		 549 int offset;
550 gfn_t gfn;
d835dfec
AK		 551 int r;
552
553 if (is_long_mode(vcpu) || !is_pae(vcpu))
554 return false;
555
6de4f3ad
AK		 556 if (!test_bit(VCPU_EXREG_PDPTR,
557 (unsigned long *)&vcpu->arch.regs_avail))
558 return true;
559
9f8fe504
AK		 560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 564 if (r < 0)
565 goto out;
ff03a073 566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 567out:
d835dfec
AK		 568
569 return changed;
570}
571
49a9b07e 572int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 573{
aad82703 574 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 576
f9a48e6a
AK		 577 cr0 |= X86_CR0_ET;
578
ab344828 579#ifdef CONFIG_X86_64
0f12244f
GN		 580 if (cr0 & 0xffffffff00000000UL)
581 return 1;
ab344828
GN		 582#endif
583
584 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 585
0f12244f
GN		 586 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
587 return 1;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
590 return 1;
a03490ed
CO		 591
592 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
593#ifdef CONFIG_X86_64
f6801dff 594 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 595 int cs_db, cs_l;
596
0f12244f
GN		 597 if (!is_pae(vcpu))
598 return 1;
a03490ed 599 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 600 if (cs_l)
601 return 1;
a03490ed
CO		 602 } else
603#endif
ff03a073 604 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 605 kvm_read_cr3(vcpu)))
0f12244f 606 return 1;
a03490ed
CO		 607 }
608
ad756a16
MJ		 609 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
610 return 1;
611
a03490ed 612 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 613
d170c419 614 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 615 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 616 kvm_async_pf_hash_reset(vcpu);
617 }
e5f3f027 618
aad82703
SY		 619 if ((cr0 ^ old_cr0) & update_bits)
620 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 621 return 0;
622}
2d3ad1f4 623EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 624
2d3ad1f4 625void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 626{
49a9b07e 627 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 630
42bdf991
MT		 631static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
632{
633 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
634 !vcpu->guest_xcr0_loaded) {
635 /* kvm_set_xcr() also depends on this */
636 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
637 vcpu->guest_xcr0_loaded = 1;
638 }
639}
640
641static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
642{
643 if (vcpu->guest_xcr0_loaded) {
644 if (vcpu->arch.xcr0 != host_xcr0)
645 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
646 vcpu->guest_xcr0_loaded = 0;
647 }
648}
649
69b0049a 650static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 651{
56c103ec
LJ		 652 u64 xcr0 = xcr;
653 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 654 u64 valid_bits;
2acf923e
DC		 655
656 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
657 if (index != XCR_XFEATURE_ENABLED_MASK)
658 return 1;
2acf923e
DC		 659 if (!(xcr0 & XSTATE_FP))
660 return 1;
661 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
662 return 1;
46c34cb0
PB		 663
664 /*
665 * Do not allow the guest to set bits that we do not support
666 * saving. However, xcr0 bit 0 is always set, even if the
667 * emulated CPU does not support XSAVE (see fx_init).
668 */
669 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
670 if (xcr0 & ~valid_bits)
2acf923e 671 return 1;
46c34cb0 672
390bd528
LJ		 673 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
674 return 1;
675
612263b3
CP		 676 if (xcr0 & XSTATE_AVX512) {
677 if (!(xcr0 & XSTATE_YMM))
678 return 1;
679 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
680 return 1;
681 }
42bdf991 682 kvm_put_guest_xcr0(vcpu);
2acf923e 683 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 684
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
2acf923e
DC		 687 return 0;
688}
689
690int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
691{
764bcbc5
Z		 692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 694 kvm_inject_gp(vcpu, 0);
695 return 1;
696 }
697 return 0;
698}
699EXPORT_SYMBOL_GPL(kvm_set_xcr);
700
a83b29c6 701int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 702{
fc78f519 703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
edc90b7d
XG		 704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
705 X86_CR4_SMEP | X86_CR4_SMAP;
706
0f12244f
GN		 707 if (cr4 & CR4_RESERVED_BITS)
708 return 1;
a03490ed 709
2acf923e
DC		 710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711 return 1;
712
c68b734f
YW		 713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714 return 1;
715
97ec8c06
FW		 716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717 return 1;
718
afcbf13f 719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 720 return 1;
721
a03490ed 722 if (is_long_mode(vcpu)) {
0f12244f
GN		 723 if (!(cr4 & X86_CR4_PAE))
724 return 1;
a2edf57f
AK		 725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728 kvm_read_cr3(vcpu)))
0f12244f
GN		 729 return 1;
730
ad756a16
MJ		 731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732 if (!guest_cpuid_has_pcid(vcpu))
733 return 1;
734
735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737 return 1;
738 }
739
5e1746d6 740 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 741 return 1;
a03490ed 742
ad756a16
MJ		 743 if (((cr4 ^ old_cr4) & pdptr_bits) ||
744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 745 kvm_mmu_reset_context(vcpu);
0f12244f 746
2acf923e 747 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 748 kvm_update_cpuid(vcpu);
2acf923e 749
0f12244f
GN		 750 return 0;
751}
2d3ad1f4 752EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 753
2390218b 754int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 755{
ac146235 756#ifdef CONFIG_X86_64
9d88fca7 757 cr3 &= ~CR3_PCID_INVD;
ac146235 758#endif
9d88fca7 759
9f8fe504 760 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 761 kvm_mmu_sync_roots(vcpu);
77c3913b 762 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 763 return 0;
d835dfec
AK		 764 }
765
a03490ed 766 if (is_long_mode(vcpu)) {
d9f89b88
JK		 767 if (cr3 & CR3_L_MODE_RESERVED_BITS)
768 return 1;
769 } else if (is_pae(vcpu) && is_paging(vcpu) &&
770 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 771 return 1;
a03490ed 772
0f12244f 773 vcpu->arch.cr3 = cr3;
aff48baa 774 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 775 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 776 return 0;
777}
2d3ad1f4 778EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 779
eea1cff9 780int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 781{
0f12244f
GN		 782 if (cr8 & CR8_RESERVED_BITS)
783 return 1;
a03490ed
CO		 784 if (irqchip_in_kernel(vcpu->kvm))
785 kvm_lapic_set_tpr(vcpu, cr8);
786 else
ad312c7c 787 vcpu->arch.cr8 = cr8;
0f12244f
GN		 788 return 0;
789}
2d3ad1f4 790EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 791
2d3ad1f4 792unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 793{
794 if (irqchip_in_kernel(vcpu->kvm))
795 return kvm_lapic_get_cr8(vcpu);
796 else
ad312c7c 797 return vcpu->arch.cr8;
a03490ed 798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 800
ae561ede
NA		 801static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
802{
803 int i;
804
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
806 for (i = 0; i < KVM_NR_DB_REGS; i++)
807 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
808 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
809 }
810}
811
73aaf249
JK		 812static void kvm_update_dr6(struct kvm_vcpu *vcpu)
813{
814 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
815 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
816}
817
c8639010
JK		 818static void kvm_update_dr7(struct kvm_vcpu *vcpu)
819{
820 unsigned long dr7;
821
822 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
823 dr7 = vcpu->arch.guest_debug_dr7;
824 else
825 dr7 = vcpu->arch.dr7;
826 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 827 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
828 if (dr7 & DR7_BP_EN_MASK)
829 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 830}
831
6f43ed01
NA		 832static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
833{
834 u64 fixed = DR6_FIXED_1;
835
836 if (!guest_cpuid_has_rtm(vcpu))
837 fixed |= DR6_RTM;
838 return fixed;
839}
840
338dbc97 841static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 842{
843 switch (dr) {
844 case 0 ... 3:
845 vcpu->arch.db[dr] = val;
846 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
847 vcpu->arch.eff_db[dr] = val;
848 break;
849 case 4:
020df079
GN		 850 /* fall through */
851 case 6:
338dbc97
GN		 852 if (val & 0xffffffff00000000ULL)
853 return -1; /* #GP */
6f43ed01 854 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 855 kvm_update_dr6(vcpu);
020df079
GN		 856 break;
857 case 5:
020df079
GN		 858 /* fall through */
859 default: /* 7 */
338dbc97
GN		 860 if (val & 0xffffffff00000000ULL)
861 return -1; /* #GP */
020df079 862 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 863 kvm_update_dr7(vcpu);
020df079
GN		 864 break;
865 }
866
867 return 0;
868}
338dbc97
GN		 869
870int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
871{
16f8a6f9 872 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 873 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 874 return 1;
875 }
876 return 0;
338dbc97 877}
020df079
GN		 878EXPORT_SYMBOL_GPL(kvm_set_dr);
879
16f8a6f9 880int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 881{
882 switch (dr) {
883 case 0 ... 3:
884 *val = vcpu->arch.db[dr];
885 break;
886 case 4:
020df079
GN		 887 /* fall through */
888 case 6:
73aaf249
JK		 889 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
890 *val = vcpu->arch.dr6;
891 else
892 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 893 break;
894 case 5:
020df079
GN		 895 /* fall through */
896 default: /* 7 */
897 *val = vcpu->arch.dr7;
898 break;
899 }
338dbc97
GN		 900 return 0;
901}
020df079
GN		 902EXPORT_SYMBOL_GPL(kvm_get_dr);
903
022cd0e8
AK		 904bool kvm_rdpmc(struct kvm_vcpu *vcpu)
905{
906 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
907 u64 data;
908 int err;
909
910 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
911 if (err)
912 return err;
913 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
914 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
915 return err;
916}
917EXPORT_SYMBOL_GPL(kvm_rdpmc);
918
043405e1
CO		 919/*
920 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
921 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
922 *
923 * This list is modified at module load time to reflect the
e3267cbb
GC		 924 * capabilities of the host cpu. This capabilities test skips MSRs that are
925 * kvm-specific. Those are put in the beginning of the list.
043405e1 926 */
e3267cbb 927
e984097b 928#define KVM_SAVE_MSRS_BEGIN 12
043405e1 929static u32 msrs_to_save[] = {
e3267cbb 930 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 931 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 932 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 933 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 934 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 935 MSR_KVM_PV_EOI_EN,
043405e1 936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 937 MSR_STAR,
043405e1
CO		 938#ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940#endif
b3897a49 941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 943};
944
945static unsigned num_msrs_to_save;
946
f1d24831 947static const u32 emulated_msrs[] = {
ba904635 948 MSR_IA32_TSC_ADJUST,
a3e06bbe 949 MSR_IA32_TSCDEADLINE,
043405e1 950 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 951 MSR_IA32_MCG_STATUS,
952 MSR_IA32_MCG_CTL,
043405e1
CO		 953};
954
384bb783 955bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 956{
b69e8cae 957 if (efer & efer_reserved_bits)
384bb783 958 return false;
15c4a640 959
1b2fd70c
AG		 960 if (efer & EFER_FFXSR) {
961 struct kvm_cpuid_entry2 *feat;
962
963 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 964 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 965 return false;
1b2fd70c
AG		 966 }
967
d8017474
AG		 968 if (efer & EFER_SVME) {
969 struct kvm_cpuid_entry2 *feat;
970
971 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 972 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 973 return false;
d8017474
AG		 974 }
975
384bb783
JK		 976 return true;
977}
978EXPORT_SYMBOL_GPL(kvm_valid_efer);
979
980static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
981{
982 u64 old_efer = vcpu->arch.efer;
983
984 if (!kvm_valid_efer(vcpu, efer))
985 return 1;
986
987 if (is_paging(vcpu)
988 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
989 return 1;
990
15c4a640 991 efer &= ~EFER_LMA;
f6801dff 992 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 993
a3d204e2
SY		 994 kvm_x86_ops->set_efer(vcpu, efer);
995
aad82703
SY		 996 /* Update reserved bits */
997 if ((efer ^ old_efer) & EFER_NX)
998 kvm_mmu_reset_context(vcpu);
999
b69e8cae 1000 return 0;
15c4a640
CO		 1001}
1002
f2b4b7dd
JR		 1003void kvm_enable_efer_bits(u64 mask)
1004{
1005 efer_reserved_bits &= ~mask;
1006}
1007EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1008
15c4a640
CO		 1009/*
1010 * Writes msr value into into the appropriate "register".
1011 * Returns 0 on success, non-0 otherwise.
1012 * Assumes vcpu_load() was already called.
1013 */
8fe8ab46 1014int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1015{
854e8bb1
NA		 1016 switch (msr->index) {
1017 case MSR_FS_BASE:
1018 case MSR_GS_BASE:
1019 case MSR_KERNEL_GS_BASE:
1020 case MSR_CSTAR:
1021 case MSR_LSTAR:
1022 if (is_noncanonical_address(msr->data))
1023 return 1;
1024 break;
1025 case MSR_IA32_SYSENTER_EIP:
1026 case MSR_IA32_SYSENTER_ESP:
1027 /*
1028 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1029 * non-canonical address is written on Intel but not on
1030 * AMD (which ignores the top 32-bits, because it does
1031 * not implement 64-bit SYSENTER).
1032 *
1033 * 64-bit code should hence be able to write a non-canonical
1034 * value on AMD. Making the address canonical ensures that
1035 * vmentry does not fail on Intel after writing a non-canonical
1036 * value, and that something deterministic happens if the guest
1037 * invokes 64-bit SYSENTER.
1038 */
1039 msr->data = get_canonical(msr->data);
1040 }
8fe8ab46 1041 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1042}
854e8bb1 1043EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1044
313a3dc7
CO		 1045/*
1046 * Adapt set_msr() to msr_io()'s calling convention
1047 */
1048static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1049{
8fe8ab46
WA		 1050 struct msr_data msr;
1051
1052 msr.data = *data;
1053 msr.index = index;
1054 msr.host_initiated = true;
1055 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1056}
1057
16e8d74d
MT		 1058#ifdef CONFIG_X86_64
1059struct pvclock_gtod_data {
1060 seqcount_t seq;
1061
1062 struct { /* extract of a clocksource struct */
1063 int vclock_mode;
1064 cycle_t cycle_last;
1065 cycle_t mask;
1066 u32 mult;
1067 u32 shift;
1068 } clock;
1069
cbcf2dd3
TG		 1070 u64 boot_ns;
1071 u64 nsec_base;
16e8d74d
MT		 1072};
1073
1074static struct pvclock_gtod_data pvclock_gtod_data;
1075
1076static void update_pvclock_gtod(struct timekeeper *tk)
1077{
1078 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1079 u64 boot_ns;
1080
876e7881 1081 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1082
1083 write_seqcount_begin(&vdata->seq);
1084
1085 /* copy pvclock gtod data */
876e7881
PZ		 1086 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1087 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1088 vdata->clock.mask = tk->tkr_mono.mask;
1089 vdata->clock.mult = tk->tkr_mono.mult;
1090 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1091
cbcf2dd3 1092 vdata->boot_ns = boot_ns;
876e7881 1093 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1094
1095 write_seqcount_end(&vdata->seq);
1096}
1097#endif
1098
bab5bb39
NK		 1099void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1100{
1101 /*
1102 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1103 * vcpu_enter_guest. This function is only called from
1104 * the physical CPU that is running vcpu.
1105 */
1106 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1107}
16e8d74d 1108
18068523
GOC		 1109static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1110{
9ed3c444
AK		 1111 int version;
1112 int r;
50d0a0f9 1113 struct pvclock_wall_clock wc;
923de3cf 1114 struct timespec boot;
18068523
GOC		 1115
1116 if (!wall_clock)
1117 return;
1118
9ed3c444
AK		 1119 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1120 if (r)
1121 return;
1122
1123 if (version & 1)
1124 ++version; /* first time write, random junk */
1125
1126 ++version;
18068523 1127
18068523
GOC		 1128 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1129
50d0a0f9
GH		 1130 /*
1131 * The guest calculates current wall clock time by adding
34c238a1 1132 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1133 * wall clock specified here. guest system time equals host
1134 * system time for us, thus we must fill in host boot time here.
1135 */
923de3cf 1136 getboottime(&boot);
50d0a0f9 1137
4b648665
BR		 1138 if (kvm->arch.kvmclock_offset) {
1139 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1140 boot = timespec_sub(boot, ts);
1141 }
50d0a0f9
GH		 1142 wc.sec = boot.tv_sec;
1143 wc.nsec = boot.tv_nsec;
1144 wc.version = version;
18068523
GOC		 1145
1146 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1147
1148 version++;
1149 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1150}
1151
50d0a0f9
GH		 1152static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1153{
1154 uint32_t quotient, remainder;
1155
1156 /* Don't try to replace with do_div(), this one calculates
1157 * "(dividend << 32) / divisor" */
1158 __asm__ ( "divl %4"
1159 : "=a" (quotient), "=d" (remainder)
1160 : "0" (0), "1" (dividend), "r" (divisor) );
1161 return quotient;
1162}
1163
5f4e3f88
ZA		 1164static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1165 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1166{
5f4e3f88 1167 uint64_t scaled64;
50d0a0f9
GH		 1168 int32_t shift = 0;
1169 uint64_t tps64;
1170 uint32_t tps32;
1171
5f4e3f88
ZA		 1172 tps64 = base_khz * 1000LL;
1173 scaled64 = scaled_khz * 1000LL;
50933623 1174 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1175 tps64 >>= 1;
1176 shift--;
1177 }
1178
1179 tps32 = (uint32_t)tps64;
50933623
JK		 1180 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1181 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1182 scaled64 >>= 1;
1183 else
1184 tps32 <<= 1;
50d0a0f9
GH		 1185 shift++;
1186 }
1187
5f4e3f88
ZA		 1188 *pshift = shift;
1189 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1190
5f4e3f88
ZA		 1191 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1192 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1193}
1194
759379dd
ZA		 1195static inline u64 get_kernel_ns(void)
1196{
bb0b5812 1197 return ktime_get_boot_ns();
50d0a0f9
GH		 1198}
1199
d828199e 1200#ifdef CONFIG_X86_64
16e8d74d 1201static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1202#endif
16e8d74d 1203
c8076604 1204static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1205static unsigned long max_tsc_khz;
c8076604 1206
cc578287 1207static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1208{
cc578287
ZA		 1209 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1210 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1211}
1212
cc578287 1213static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1214{
cc578287
ZA		 1215 u64 v = (u64)khz * (1000000 + ppm);
1216 do_div(v, 1000000);
1217 return v;
1e993611
JR		 1218}
1219
cc578287 1220static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1221{
cc578287
ZA		 1222 u32 thresh_lo, thresh_hi;
1223 int use_scaling = 0;
217fc9cf 1224
03ba32ca
MT		 1225 /* tsc_khz can be zero if TSC calibration fails */
1226 if (this_tsc_khz == 0)
1227 return;
1228
c285545f
ZA		 1229 /* Compute a scale to convert nanoseconds in TSC cycles */
1230 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1231 &vcpu->arch.virtual_tsc_shift,
1232 &vcpu->arch.virtual_tsc_mult);
1233 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1234
1235 /*
1236 * Compute the variation in TSC rate which is acceptable
1237 * within the range of tolerance and decide if the
1238 * rate being applied is within that bounds of the hardware
1239 * rate. If so, no scaling or compensation need be done.
1240 */
1241 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1242 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1243 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1244 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1245 use_scaling = 1;
1246 }
1247 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1248}
1249
1250static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1251{
e26101b1 1252 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1253 vcpu->arch.virtual_tsc_mult,
1254 vcpu->arch.virtual_tsc_shift);
e26101b1 1255 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1256 return tsc;
1257}
1258
69b0049a 1259static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1260{
1261#ifdef CONFIG_X86_64
1262 bool vcpus_matched;
b48aa97e
MT		 1263 struct kvm_arch *ka = &vcpu->kvm->arch;
1264 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1265
1266 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1267 atomic_read(&vcpu->kvm->online_vcpus));
1268
7f187922
MT		 1269 /*
1270 * Once the masterclock is enabled, always perform request in
1271 * order to update it.
1272 *
1273 * In order to enable masterclock, the host clocksource must be TSC
1274 * and the vcpus need to have matched TSCs. When that happens,
1275 * perform request to enable masterclock.
1276 */
1277 if (ka->use_master_clock ||
1278 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1279 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1280
1281 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1282 atomic_read(&vcpu->kvm->online_vcpus),
1283 ka->use_master_clock, gtod->clock.vclock_mode);
1284#endif
1285}
1286
ba904635
WA		 1287static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1288{
1289 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1290 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1291}
1292
8fe8ab46 1293void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1294{
1295 struct kvm *kvm = vcpu->kvm;
f38e098f 1296 u64 offset, ns, elapsed;
99e3e30a 1297 unsigned long flags;
02626b6a 1298 s64 usdiff;
b48aa97e 1299 bool matched;
0d3da0d2 1300 bool already_matched;
8fe8ab46 1301 u64 data = msr->data;
99e3e30a 1302
038f8c11 1303 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1305 ns = get_kernel_ns();
f38e098f 1306 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1307
03ba32ca 1308 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1309 int faulted = 0;
1310
03ba32ca
MT		 1311 /* n.b - signed multiplication and division required */
1312 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1313#ifdef CONFIG_X86_64
03ba32ca 1314 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1315#else
03ba32ca 1316 /* do_div() only does unsigned */
8915aa27
MT		 1317 asm("1: idivl %[divisor]\n"
1318 "2: xor %%edx, %%edx\n"
1319 " movl $0, %[faulted]\n"
1320 "3:\n"
1321 ".section .fixup,\"ax\"\n"
1322 "4: movl $1, %[faulted]\n"
1323 " jmp 3b\n"
1324 ".previous\n"
1325
1326 _ASM_EXTABLE(1b, 4b)
1327
1328 : "=A"(usdiff), [faulted] "=r" (faulted)
1329 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1330
5d3cb0f6 1331#endif
03ba32ca
MT		 1332 do_div(elapsed, 1000);
1333 usdiff -= elapsed;
1334 if (usdiff < 0)
1335 usdiff = -usdiff;
8915aa27
MT		 1336
1337 /* idivl overflow => difference is larger than USEC_PER_SEC */
1338 if (faulted)
1339 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1340 } else
1341 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1342
1343 /*
5d3cb0f6
ZA		 1344 * Special case: TSC write with a small delta (1 second) of virtual
1345 * cycle time against real time is interpreted as an attempt to
1346 * synchronize the CPU.
1347 *
1348 * For a reliable TSC, we can match TSC offsets, and for an unstable
1349 * TSC, we add elapsed time in this computation. We could let the
1350 * compensation code attempt to catch up if we fall behind, but
1351 * it's better to try to match offsets from the beginning.
1352 */
02626b6a 1353 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1354 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1355 if (!check_tsc_unstable()) {
e26101b1 1356 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1357 pr_debug("kvm: matched tsc offset for %llu\n", data);
1358 } else {
857e4099 1359 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1360 data += delta;
1361 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1362 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1363 }
b48aa97e 1364 matched = true;
0d3da0d2 1365 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1366 } else {
1367 /*
1368 * We split periods of matched TSC writes into generations.
1369 * For each generation, we track the original measured
1370 * nanosecond time, offset, and write, so if TSCs are in
1371 * sync, we can match exact offset, and if not, we can match
4a969980 1372 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1373 *
1374 * These values are tracked in kvm->arch.cur_xxx variables.
1375 */
1376 kvm->arch.cur_tsc_generation++;
1377 kvm->arch.cur_tsc_nsec = ns;
1378 kvm->arch.cur_tsc_write = data;
1379 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1380 matched = false;
0d3da0d2 1381 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1382 kvm->arch.cur_tsc_generation, data);
f38e098f 1383 }
e26101b1
ZA		 1384
1385 /*
1386 * We also track th most recent recorded KHZ, write and time to
1387 * allow the matching interval to be extended at each write.
1388 */
f38e098f
ZA		 1389 kvm->arch.last_tsc_nsec = ns;
1390 kvm->arch.last_tsc_write = data;
5d3cb0f6 1391 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1392
b183aa58 1393 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1394
1395 /* Keep track of which generation this VCPU has synchronized to */
1396 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1397 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1398 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1399
ba904635
WA		 1400 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1401 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1402 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1403 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1404
1405 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1406 if (!matched) {
b48aa97e 1407 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1408 } else if (!already_matched) {
1409 kvm->arch.nr_vcpus_matched_tsc++;
1410 }
b48aa97e
MT		 1411
1412 kvm_track_tsc_matching(vcpu);
1413 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1414}
e26101b1 1415
99e3e30a
ZA		 1416EXPORT_SYMBOL_GPL(kvm_write_tsc);
1417
d828199e
MT		 1418#ifdef CONFIG_X86_64
1419
1420static cycle_t read_tsc(void)
1421{
1422 cycle_t ret;
1423 u64 last;
1424
1425 /*
1426 * Empirically, a fence (of type that depends on the CPU)
1427 * before rdtsc is enough to ensure that rdtsc is ordered
1428 * with respect to loads. The various CPU manuals are unclear
1429 * as to whether rdtsc can be reordered with later loads,
1430 * but no one has ever seen it happen.
1431 */
1432 rdtsc_barrier();
1433 ret = (cycle_t)vget_cycles();
1434
1435 last = pvclock_gtod_data.clock.cycle_last;
1436
1437 if (likely(ret >= last))
1438 return ret;
1439
1440 /*
1441 * GCC likes to generate cmov here, but this branch is extremely
1442 * predictable (it's just a funciton of time and the likely is
1443 * very likely) and there's a data dependence, so force GCC
1444 * to generate a branch instead. I don't barrier() because
1445 * we don't actually need a barrier, and if this function
1446 * ever gets inlined it will generate worse code.
1447 */
1448 asm volatile ("");
1449 return last;
1450}
1451
1452static inline u64 vgettsc(cycle_t *cycle_now)
1453{
1454 long v;
1455 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1456
1457 *cycle_now = read_tsc();
1458
1459 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1460 return v * gtod->clock.mult;
1461}
1462
cbcf2dd3 1463static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1464{
cbcf2dd3 1465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1466 unsigned long seq;
d828199e 1467 int mode;
cbcf2dd3 1468 u64 ns;
d828199e 1469
d828199e
MT		 1470 do {
1471 seq = read_seqcount_begin(&gtod->seq);
1472 mode = gtod->clock.vclock_mode;
cbcf2dd3 1473 ns = gtod->nsec_base;
d828199e
MT		 1474 ns += vgettsc(cycle_now);
1475 ns >>= gtod->clock.shift;
cbcf2dd3 1476 ns += gtod->boot_ns;
d828199e 1477 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1478 *t = ns;
d828199e
MT		 1479
1480 return mode;
1481}
1482
1483/* returns true if host is using tsc clocksource */
1484static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1485{
d828199e
MT		 1486 /* checked again under seqlock below */
1487 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1488 return false;
1489
cbcf2dd3 1490 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1491}
1492#endif
1493
1494/*
1495 *
b48aa97e
MT		 1496 * Assuming a stable TSC across physical CPUS, and a stable TSC
1497 * across virtual CPUs, the following condition is possible.
1498 * Each numbered line represents an event visible to both
d828199e
MT		 1499 * CPUs at the next numbered event.
1500 *
1501 * "timespecX" represents host monotonic time. "tscX" represents
1502 * RDTSC value.
1503 *
1504 * VCPU0 on CPU0 | VCPU1 on CPU1
1505 *
1506 * 1. read timespec0,tsc0
1507 * 2. | timespec1 = timespec0 + N
1508 * | tsc1 = tsc0 + M
1509 * 3. transition to guest | transition to guest
1510 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1511 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1512 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1513 *
1514 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1515 *
1516 * - ret0 < ret1
1517 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1518 * ...
1519 * - 0 < N - M => M < N
1520 *
1521 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1522 * always the case (the difference between two distinct xtime instances
1523 * might be smaller then the difference between corresponding TSC reads,
1524 * when updating guest vcpus pvclock areas).
1525 *
1526 * To avoid that problem, do not allow visibility of distinct
1527 * system_timestamp/tsc_timestamp values simultaneously: use a master
1528 * copy of host monotonic time values. Update that master copy
1529 * in lockstep.
1530 *
b48aa97e 1531 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1532 *
1533 */
1534
1535static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1536{
1537#ifdef CONFIG_X86_64
1538 struct kvm_arch *ka = &kvm->arch;
1539 int vclock_mode;
b48aa97e
MT		 1540 bool host_tsc_clocksource, vcpus_matched;
1541
1542 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1543 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1544
1545 /*
1546 * If the host uses TSC clock, then passthrough TSC as stable
1547 * to the guest.
1548 */
b48aa97e 1549 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1550 &ka->master_kernel_ns,
1551 &ka->master_cycle_now);
1552
16a96021 1553 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1554 && !backwards_tsc_observed
1555 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1556
d828199e
MT		 1557 if (ka->use_master_clock)
1558 atomic_set(&kvm_guest_has_master_clock, 1);
1559
1560 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1561 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1562 vcpus_matched);
d828199e
MT		 1563#endif
1564}
1565
2e762ff7
MT		 1566static void kvm_gen_update_masterclock(struct kvm *kvm)
1567{
1568#ifdef CONFIG_X86_64
1569 int i;
1570 struct kvm_vcpu *vcpu;
1571 struct kvm_arch *ka = &kvm->arch;
1572
1573 spin_lock(&ka->pvclock_gtod_sync_lock);
1574 kvm_make_mclock_inprogress_request(kvm);
1575 /* no guest entries from this point */
1576 pvclock_update_vm_gtod_copy(kvm);
1577
1578 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1580
1581 /* guest entries allowed */
1582 kvm_for_each_vcpu(i, vcpu, kvm)
1583 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1584
1585 spin_unlock(&ka->pvclock_gtod_sync_lock);
1586#endif
1587}
1588
34c238a1 1589static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1590{
d828199e 1591 unsigned long flags, this_tsc_khz;
18068523 1592 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1593 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1594 s64 kernel_ns;
d828199e 1595 u64 tsc_timestamp, host_tsc;
0b79459b 1596 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1597 u8 pvclock_flags;
d828199e
MT		 1598 bool use_master_clock;
1599
1600 kernel_ns = 0;
1601 host_tsc = 0;
18068523 1602
d828199e
MT		 1603 /*
1604 * If the host uses TSC clock, then passthrough TSC as stable
1605 * to the guest.
1606 */
1607 spin_lock(&ka->pvclock_gtod_sync_lock);
1608 use_master_clock = ka->use_master_clock;
1609 if (use_master_clock) {
1610 host_tsc = ka->master_cycle_now;
1611 kernel_ns = ka->master_kernel_ns;
1612 }
1613 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1614
1615 /* Keep irq disabled to prevent changes to the clock */
1616 local_irq_save(flags);
89cbc767 1617 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1618 if (unlikely(this_tsc_khz == 0)) {
1619 local_irq_restore(flags);
1620 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1621 return 1;
1622 }
d828199e
MT		 1623 if (!use_master_clock) {
1624 host_tsc = native_read_tsc();
1625 kernel_ns = get_kernel_ns();
1626 }
1627
1628 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1629
c285545f
ZA		 1630 /*
1631 * We may have to catch up the TSC to match elapsed wall clock
1632 * time for two reasons, even if kvmclock is used.
1633 * 1) CPU could have been running below the maximum TSC rate
1634 * 2) Broken TSC compensation resets the base at each VCPU
1635 * entry to avoid unknown leaps of TSC even when running
1636 * again on the same CPU. This may cause apparent elapsed
1637 * time to disappear, and the guest to stand still or run
1638 * very slowly.
1639 */
1640 if (vcpu->tsc_catchup) {
1641 u64 tsc = compute_guest_tsc(v, kernel_ns);
1642 if (tsc > tsc_timestamp) {
f1e2b260 1643 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1644 tsc_timestamp = tsc;
1645 }
50d0a0f9
GH		 1646 }
1647
18068523
GOC		 1648 local_irq_restore(flags);
1649
0b79459b 1650 if (!vcpu->pv_time_enabled)
c285545f 1651 return 0;
18068523 1652
e48672fa 1653 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1654 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1655 &vcpu->hv_clock.tsc_shift,
1656 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1657 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1658 }
1659
1660 /* With all the info we got, fill in the values */
1d5f066e 1661 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1662 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1663 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1664
09a0c3f1
OH		 1665 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1666 &guest_hv_clock, sizeof(guest_hv_clock))))
1667 return 0;
1668
5dca0d91
RK		 1669 /* This VCPU is paused, but it's legal for a guest to read another
1670 * VCPU's kvmclock, so we really have to follow the specification where
1671 * it says that version is odd if data is being modified, and even after
1672 * it is consistent.
1673 *
1674 * Version field updates must be kept separate. This is because
1675 * kvm_write_guest_cached might use a "rep movs" instruction, and
1676 * writes within a string instruction are weakly ordered. So there
1677 * are three writes overall.
1678 *
1679 * As a small optimization, only write the version field in the first
1680 * and third write. The vcpu->pv_time cache is still valid, because the
1681 * version field is the first in the struct.
18068523 1682 */
5dca0d91
RK		 1683 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1684
1685 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1686 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1687 &vcpu->hv_clock,
1688 sizeof(vcpu->hv_clock.version));
1689
1690 smp_wmb();
78c0337a
MT		 1691
1692 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1693 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1694
1695 if (vcpu->pvclock_set_guest_stopped_request) {
1696 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1697 vcpu->pvclock_set_guest_stopped_request = false;
1698 }
1699
d828199e
MT		 1700 /* If the host uses TSC clocksource, then it is stable */
1701 if (use_master_clock)
1702 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1703
78c0337a
MT		 1704 vcpu->hv_clock.flags = pvclock_flags;
1705
ce1a5e60
DM		 1706 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1707
0b79459b
AH		 1708 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1709 &vcpu->hv_clock,
1710 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1711
1712 smp_wmb();
1713
1714 vcpu->hv_clock.version++;
1715 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1716 &vcpu->hv_clock,
1717 sizeof(vcpu->hv_clock.version));
8cfdc000 1718 return 0;
c8076604
GH		 1719}
1720
0061d53d
MT		 1721/*
1722 * kvmclock updates which are isolated to a given vcpu, such as
1723 * vcpu->cpu migration, should not allow system_timestamp from
1724 * the rest of the vcpus to remain static. Otherwise ntp frequency
1725 * correction applies to one vcpu's system_timestamp but not
1726 * the others.
1727 *
1728 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1729 * We need to rate-limit these requests though, as they can
1730 * considerably slow guests that have a large number of vcpus.
1731 * The time for a remote vcpu to update its kvmclock is bound
1732 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1733 */
1734
7e44e449
AJ		 1735#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1736
1737static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1738{
1739 int i;
7e44e449
AJ		 1740 struct delayed_work *dwork = to_delayed_work(work);
1741 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1742 kvmclock_update_work);
1743 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1744 struct kvm_vcpu *vcpu;
1745
1746 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1748 kvm_vcpu_kick(vcpu);
1749 }
1750}
1751
7e44e449
AJ		 1752static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1753{
1754 struct kvm *kvm = v->kvm;
1755
105b21bb 1756 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1757 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1758 KVMCLOCK_UPDATE_DELAY);
1759}
1760
332967a3
AJ		 1761#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1762
1763static void kvmclock_sync_fn(struct work_struct *work)
1764{
1765 struct delayed_work *dwork = to_delayed_work(work);
1766 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1767 kvmclock_sync_work);
1768 struct kvm *kvm = container_of(ka, struct kvm, arch);
1769
1770 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1771 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1772 KVMCLOCK_SYNC_PERIOD);
1773}
1774
9ba075a6
AK		 1775static bool msr_mtrr_valid(unsigned msr)
1776{
1777 switch (msr) {
1778 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1779 case MSR_MTRRfix64K_00000:
1780 case MSR_MTRRfix16K_80000:
1781 case MSR_MTRRfix16K_A0000:
1782 case MSR_MTRRfix4K_C0000:
1783 case MSR_MTRRfix4K_C8000:
1784 case MSR_MTRRfix4K_D0000:
1785 case MSR_MTRRfix4K_D8000:
1786 case MSR_MTRRfix4K_E0000:
1787 case MSR_MTRRfix4K_E8000:
1788 case MSR_MTRRfix4K_F0000:
1789 case MSR_MTRRfix4K_F8000:
1790 case MSR_MTRRdefType:
1791 case MSR_IA32_CR_PAT:
1792 return true;
1793 case 0x2f8:
1794 return true;
1795 }
1796 return false;
1797}
1798
d6289b93
MT		 1799static bool valid_pat_type(unsigned t)
1800{
1801 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1802}
1803
1804static bool valid_mtrr_type(unsigned t)
1805{
1806 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1807}
1808
4566654b 1809bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1810{
1811 int i;
fd275235 1812 u64 mask;
d6289b93
MT		 1813
1814 if (!msr_mtrr_valid(msr))
1815 return false;
1816
1817 if (msr == MSR_IA32_CR_PAT) {
1818 for (i = 0; i < 8; i++)
1819 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1820 return false;
1821 return true;
1822 } else if (msr == MSR_MTRRdefType) {
1823 if (data & ~0xcff)
1824 return false;
1825 return valid_mtrr_type(data & 0xff);
1826 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1827 for (i = 0; i < 8 ; i++)
1828 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1829 return false;
1830 return true;
1831 }
1832
1833 /* variable MTRRs */
adfb5d27
WL		 1834 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1835
fd275235 1836 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1837 if ((msr & 1) == 0) {
adfb5d27 1838 /* MTRR base */
d7a2a246
WL		 1839 if (!valid_mtrr_type(data & 0xff))
1840 return false;
1841 mask |= 0xf00;
1842 } else
1843 /* MTRR mask */
1844 mask |= 0x7ff;
1845 if (data & mask) {
1846 kvm_inject_gp(vcpu, 0);
1847 return false;
1848 }
1849
adfb5d27 1850 return true;
d6289b93 1851}
4566654b 1852EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1853
efdfe536
XG		 1854static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr)
1855{
1856 struct mtrr_state_type *mtrr_state = &vcpu->arch.mtrr_state;
1857 unsigned char mtrr_enabled = mtrr_state->enabled;
1858 gfn_t start, end, mask;
1859 int index;
1860 bool is_fixed = true;
1861
1862 if (msr == MSR_IA32_CR_PAT || !tdp_enabled ||
1863 !kvm_arch_has_noncoherent_dma(vcpu->kvm))
1864 return;
1865
1866 if (!(mtrr_enabled & 0x2) && msr != MSR_MTRRdefType)
1867 return;
1868
1869 switch (msr) {
1870 case MSR_MTRRfix64K_00000:
1871 start = 0x0;
1872 end = 0x80000;
1873 break;
1874 case MSR_MTRRfix16K_80000:
1875 start = 0x80000;
1876 end = 0xa0000;
1877 break;
1878 case MSR_MTRRfix16K_A0000:
1879 start = 0xa0000;
1880 end = 0xc0000;
1881 break;
1882 case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000:
1883 index = msr - MSR_MTRRfix4K_C0000;
1884 start = 0xc0000 + index * (32 << 10);
1885 end = start + (32 << 10);
1886 break;
1887 case MSR_MTRRdefType:
1888 is_fixed = false;
1889 start = 0x0;
1890 end = ~0ULL;
1891 break;
1892 default:
1893 /* variable range MTRRs. */
1894 is_fixed = false;
1895 index = (msr - 0x200) / 2;
1896 start = (((u64)mtrr_state->var_ranges[index].base_hi) << 32) +
1897 (mtrr_state->var_ranges[index].base_lo & PAGE_MASK);
1898 mask = (((u64)mtrr_state->var_ranges[index].mask_hi) << 32) +
1899 (mtrr_state->var_ranges[index].mask_lo & PAGE_MASK);
1900 mask |= ~0ULL << cpuid_maxphyaddr(vcpu);
1901
1902 end = ((start & mask) | ~mask) + 1;
1903 }
1904
1905 if (is_fixed && !(mtrr_enabled & 0x1))
1906 return;
1907
1908 kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end));
1909}
1910
9ba075a6
AK		 1911static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1912{
0bed3b56
SY		 1913 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1914
4566654b 1915 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1916 return 1;
1917
0bed3b56
SY		 1918 if (msr == MSR_MTRRdefType) {
1919 vcpu->arch.mtrr_state.def_type = data;
1920 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1921 } else if (msr == MSR_MTRRfix64K_00000)
1922 p[0] = data;
1923 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1924 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1925 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1926 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1927 else if (msr == MSR_IA32_CR_PAT)
1928 vcpu->arch.pat = data;
1929 else { /* Variable MTRRs */
1930 int idx, is_mtrr_mask;
1931 u64 *pt;
1932
1933 idx = (msr - 0x200) / 2;
1934 is_mtrr_mask = msr - 0x200 - 2 * idx;
1935 if (!is_mtrr_mask)
1936 pt =
1937 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1938 else
1939 pt =
1940 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1941 *pt = data;
1942 }
1943
efdfe536 1944 update_mtrr(vcpu, msr);
9ba075a6
AK		 1945 return 0;
1946}
15c4a640 1947
890ca9ae 1948static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1949{
890ca9ae
HY		 1950 u64 mcg_cap = vcpu->arch.mcg_cap;
1951 unsigned bank_num = mcg_cap & 0xff;
1952
15c4a640 1953 switch (msr) {
15c4a640 1954 case MSR_IA32_MCG_STATUS:
890ca9ae 1955 vcpu->arch.mcg_status = data;
15c4a640 1956 break;
c7ac679c 1957 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1958 if (!(mcg_cap & MCG_CTL_P))
1959 return 1;
1960 if (data != 0 && data != ~(u64)0)
1961 return -1;
1962 vcpu->arch.mcg_ctl = data;
1963 break;
1964 default:
1965 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1966 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1967 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1968 /* only 0 or all 1s can be written to IA32_MCi_CTL
1969 * some Linux kernels though clear bit 10 in bank 4 to
1970 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1971 * this to avoid an uncatched #GP in the guest
1972 */
890ca9ae 1973 if ((offset & 0x3) == 0 &&
114be429 1974 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1975 return -1;
1976 vcpu->arch.mce_banks[offset] = data;
1977 break;
1978 }
1979 return 1;
1980 }
1981 return 0;
1982}
1983
ffde22ac
ES		 1984static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1985{
1986 struct kvm *kvm = vcpu->kvm;
1987 int lm = is_long_mode(vcpu);
1988 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1989 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1990 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1991 : kvm->arch.xen_hvm_config.blob_size_32;
1992 u32 page_num = data & ~PAGE_MASK;
1993 u64 page_addr = data & PAGE_MASK;
1994 u8 *page;
1995 int r;
1996
1997 r = -E2BIG;
1998 if (page_num >= blob_size)
1999 goto out;
2000 r = -ENOMEM;
ff5c2c03
SL		 2001 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2002 if (IS_ERR(page)) {
2003 r = PTR_ERR(page);
ffde22ac 2004 goto out;
ff5c2c03 2005 }
ffde22ac
ES		 2006 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
2007 goto out_free;
2008 r = 0;
2009out_free:
2010 kfree(page);
2011out:
2012 return r;
2013}
2014
55cd8e5a
GN		 2015static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
2016{
2017 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
2018}
2019
2020static bool kvm_hv_msr_partition_wide(u32 msr)
2021{
2022 bool r = false;
2023 switch (msr) {
2024 case HV_X64_MSR_GUEST_OS_ID:
2025 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 2026 case HV_X64_MSR_REFERENCE_TSC:
2027 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 2028 r = true;
2029 break;
2030 }
2031
2032 return r;
2033}
2034
2035static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2036{
2037 struct kvm *kvm = vcpu->kvm;
2038
2039 switch (msr) {
2040 case HV_X64_MSR_GUEST_OS_ID:
2041 kvm->arch.hv_guest_os_id = data;
2042 /* setting guest os id to zero disables hypercall page */
2043 if (!kvm->arch.hv_guest_os_id)
2044 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
2045 break;
2046 case HV_X64_MSR_HYPERCALL: {
2047 u64 gfn;
2048 unsigned long addr;
2049 u8 instructions[4];
2050
2051 /* if guest os id is not set hypercall should remain disabled */
2052 if (!kvm->arch.hv_guest_os_id)
2053 break;
2054 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2055 kvm->arch.hv_hypercall = data;
2056 break;
2057 }
2058 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2059 addr = gfn_to_hva(kvm, gfn);
2060 if (kvm_is_error_hva(addr))
2061 return 1;
2062 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2063 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2064 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2065 return 1;
2066 kvm->arch.hv_hypercall = data;
b94b64c9 2067 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2068 break;
2069 }
e984097b
VR		 2070 case HV_X64_MSR_REFERENCE_TSC: {
2071 u64 gfn;
2072 HV_REFERENCE_TSC_PAGE tsc_ref;
2073 memset(&tsc_ref, 0, sizeof(tsc_ref));
2074 kvm->arch.hv_tsc_page = data;
2075 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2076 break;
2077 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2078 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2079 &tsc_ref, sizeof(tsc_ref)))
2080 return 1;
2081 mark_page_dirty(kvm, gfn);
2082 break;
2083 }
55cd8e5a 2084 default:
a737f256
CD		 2085 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2086 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2087 return 1;
2088 }
2089 return 0;
2090}
2091
2092static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2093{
10388a07
GN		 2094 switch (msr) {
2095 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2096 u64 gfn;
10388a07 2097 unsigned long addr;
55cd8e5a 2098
10388a07
GN		 2099 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2100 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2101 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2102 return 1;
10388a07
GN		 2103 break;
2104 }
b3af1e88
VR		 2105 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2106 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2107 if (kvm_is_error_hva(addr))
2108 return 1;
8b0cedff 2109 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2110 return 1;
2111 vcpu->arch.hv_vapic = data;
b3af1e88 2112 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2113 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2114 return 1;
10388a07
GN		 2115 break;
2116 }
2117 case HV_X64_MSR_EOI:
2118 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2119 case HV_X64_MSR_ICR:
2120 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2121 case HV_X64_MSR_TPR:
2122 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2123 default:
a737f256
CD		 2124 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2125 "data 0x%llx\n", msr, data);
10388a07
GN		 2126 return 1;
2127 }
2128
2129 return 0;
55cd8e5a
GN		 2130}
2131
344d9588
GN		 2132static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2133{
2134 gpa_t gpa = data & ~0x3f;
2135
4a969980 2136 /* Bits 2:5 are reserved, Should be zero */
6adba527 2137 if (data & 0x3c)
344d9588
GN		 2138 return 1;
2139
2140 vcpu->arch.apf.msr_val = data;
2141
2142 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2143 kvm_clear_async_pf_completion_queue(vcpu);
2144 kvm_async_pf_hash_reset(vcpu);
2145 return 0;
2146 }
2147
8f964525
AH		 2148 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2149 sizeof(u32)))
344d9588
GN		 2150 return 1;
2151
6adba527 2152 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2153 kvm_async_pf_wakeup_all(vcpu);
2154 return 0;
2155}
2156
12f9a48f
GC		 2157static void kvmclock_reset(struct kvm_vcpu *vcpu)
2158{
0b79459b 2159 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2160}
2161
c9aaa895
GC		 2162static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2163{
2164 u64 delta;
2165
2166 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2167 return;
2168
2169 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2170 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2171 vcpu->arch.st.accum_steal = delta;
2172}
2173
2174static void record_steal_time(struct kvm_vcpu *vcpu)
2175{
2176 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2177 return;
2178
2179 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2180 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2181 return;
2182
2183 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2184 vcpu->arch.st.steal.version += 2;
2185 vcpu->arch.st.accum_steal = 0;
2186
2187 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2188 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2189}
2190
8fe8ab46 2191int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2192{
5753785f 2193 bool pr = false;
8fe8ab46
WA		 2194 u32 msr = msr_info->index;
2195 u64 data = msr_info->data;
5753785f 2196
15c4a640 2197 switch (msr) {
2e32b719
BP		 2198 case MSR_AMD64_NB_CFG:
2199 case MSR_IA32_UCODE_REV:
2200 case MSR_IA32_UCODE_WRITE:
2201 case MSR_VM_HSAVE_PA:
2202 case MSR_AMD64_PATCH_LOADER:
2203 case MSR_AMD64_BU_CFG2:
2204 break;
2205
15c4a640 2206 case MSR_EFER:
b69e8cae 2207 return set_efer(vcpu, data);
8f1589d9
AP		 2208 case MSR_K7_HWCR:
2209 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2210 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2211 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2212 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2213 if (data != 0) {
a737f256
CD		 2214 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2215 data);
8f1589d9
AP		 2216 return 1;
2217 }
15c4a640 2218 break;
f7c6d140
AP		 2219 case MSR_FAM10H_MMIO_CONF_BASE:
2220 if (data != 0) {
a737f256
CD		 2221 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2222 "0x%llx\n", data);
f7c6d140
AP		 2223 return 1;
2224 }
15c4a640 2225 break;
b5e2fec0
AG		 2226 case MSR_IA32_DEBUGCTLMSR:
2227 if (!data) {
2228 /* We support the non-activated case already */
2229 break;
2230 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2231 /* Values other than LBR and BTF are vendor-specific,
2232 thus reserved and should throw a #GP */
2233 return 1;
2234 }
a737f256
CD		 2235 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2236 __func__, data);
b5e2fec0 2237 break;
9ba075a6
AK		 2238 case 0x200 ... 0x2ff:
2239 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2240 case MSR_IA32_APICBASE:
58cb628d 2241 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2242 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2243 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2244 case MSR_IA32_TSCDEADLINE:
2245 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2246 break;
ba904635
WA		 2247 case MSR_IA32_TSC_ADJUST:
2248 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2249 if (!msr_info->host_initiated) {
d913b904 2250 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2251 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2252 }
2253 vcpu->arch.ia32_tsc_adjust_msr = data;
2254 }
2255 break;
15c4a640 2256 case MSR_IA32_MISC_ENABLE:
ad312c7c 2257 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2258 break;
11c6bffa 2259 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2260 case MSR_KVM_WALL_CLOCK:
2261 vcpu->kvm->arch.wall_clock = data;
2262 kvm_write_wall_clock(vcpu->kvm, data);
2263 break;
11c6bffa 2264 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2265 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2266 u64 gpa_offset;
54750f2c
MT		 2267 struct kvm_arch *ka = &vcpu->kvm->arch;
2268
12f9a48f 2269 kvmclock_reset(vcpu);
18068523 2270
54750f2c
MT		 2271 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2272 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2273
2274 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2275 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2276 &vcpu->requests);
2277
2278 ka->boot_vcpu_runs_old_kvmclock = tmp;
2279 }
2280
18068523 2281 vcpu->arch.time = data;
0061d53d 2282 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2283
2284 /* we verify if the enable bit is set... */
2285 if (!(data & 1))
2286 break;
2287
0b79459b 2288 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2289
0b79459b 2290 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2291 &vcpu->arch.pv_time, data & ~1ULL,
2292 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2293 vcpu->arch.pv_time_enabled = false;
2294 else
2295 vcpu->arch.pv_time_enabled = true;
32cad84f 2296
18068523
GOC		 2297 break;
2298 }
344d9588
GN		 2299 case MSR_KVM_ASYNC_PF_EN:
2300 if (kvm_pv_enable_async_pf(vcpu, data))
2301 return 1;
2302 break;
c9aaa895
GC		 2303 case MSR_KVM_STEAL_TIME:
2304
2305 if (unlikely(!sched_info_on()))
2306 return 1;
2307
2308 if (data & KVM_STEAL_RESERVED_MASK)
2309 return 1;
2310
2311 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2312 data & KVM_STEAL_VALID_BITS,
2313 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2314 return 1;
2315
2316 vcpu->arch.st.msr_val = data;
2317
2318 if (!(data & KVM_MSR_ENABLED))
2319 break;
2320
2321 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2322
2323 preempt_disable();
2324 accumulate_steal_time(vcpu);
2325 preempt_enable();
2326
2327 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2328
2329 break;
ae7a2a3f
MT		 2330 case MSR_KVM_PV_EOI_EN:
2331 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2332 return 1;
2333 break;
c9aaa895 2334
890ca9ae
HY		 2335 case MSR_IA32_MCG_CTL:
2336 case MSR_IA32_MCG_STATUS:
81760dcc 2337 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2338 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2339
2340 /* Performance counters are not protected by a CPUID bit,
2341 * so we should check all of them in the generic path for the sake of
2342 * cross vendor migration.
2343 * Writing a zero into the event select MSRs disables them,
2344 * which we perfectly emulate ;-). Any other value should be at least
2345 * reported, some guests depend on them.
2346 */
71db6023
AP		 2347 case MSR_K7_EVNTSEL0:
2348 case MSR_K7_EVNTSEL1:
2349 case MSR_K7_EVNTSEL2:
2350 case MSR_K7_EVNTSEL3:
2351 if (data != 0)
a737f256
CD		 2352 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2353 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2354 break;
2355 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2356 * so we ignore writes to make it happy.
2357 */
71db6023
AP		 2358 case MSR_K7_PERFCTR0:
2359 case MSR_K7_PERFCTR1:
2360 case MSR_K7_PERFCTR2:
2361 case MSR_K7_PERFCTR3:
a737f256
CD		 2362 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2363 "0x%x data 0x%llx\n", msr, data);
71db6023 2364 break;
5753785f
GN		 2365 case MSR_P6_PERFCTR0:
2366 case MSR_P6_PERFCTR1:
2367 pr = true;
2368 case MSR_P6_EVNTSEL0:
2369 case MSR_P6_EVNTSEL1:
2370 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2371 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2372
2373 if (pr || data != 0)
a737f256
CD		 2374 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2375 "0x%x data 0x%llx\n", msr, data);
5753785f 2376 break;
84e0cefa
JS		 2377 case MSR_K7_CLK_CTL:
2378 /*
2379 * Ignore all writes to this no longer documented MSR.
2380 * Writes are only relevant for old K7 processors,
2381 * all pre-dating SVM, but a recommended workaround from
4a969980 2382 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2383 * affected processor models on the command line, hence
2384 * the need to ignore the workaround.
2385 */
2386 break;
55cd8e5a
GN		 2387 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2388 if (kvm_hv_msr_partition_wide(msr)) {
2389 int r;
2390 mutex_lock(&vcpu->kvm->lock);
2391 r = set_msr_hyperv_pw(vcpu, msr, data);
2392 mutex_unlock(&vcpu->kvm->lock);
2393 return r;
2394 } else
2395 return set_msr_hyperv(vcpu, msr, data);
2396 break;
91c9c3ed 2397 case MSR_IA32_BBL_CR_CTL3:
2398 /* Drop writes to this legacy MSR -- see rdmsr
2399 * counterpart for further detail.
2400 */
a737f256 2401 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2402 break;
2b036c6b
BO		 2403 case MSR_AMD64_OSVW_ID_LENGTH:
2404 if (!guest_cpuid_has_osvw(vcpu))
2405 return 1;
2406 vcpu->arch.osvw.length = data;
2407 break;
2408 case MSR_AMD64_OSVW_STATUS:
2409 if (!guest_cpuid_has_osvw(vcpu))
2410 return 1;
2411 vcpu->arch.osvw.status = data;
2412 break;
15c4a640 2413 default:
ffde22ac
ES		 2414 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2415 return xen_hvm_config(vcpu, data);
f5132b01 2416 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2417 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2418 if (!ignore_msrs) {
a737f256
CD		 2419 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2420 msr, data);
ed85c068
AP		 2421 return 1;
2422 } else {
a737f256
CD		 2423 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2424 msr, data);
ed85c068
AP		 2425 break;
2426 }
15c4a640
CO		 2427 }
2428 return 0;
2429}
2430EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2431
2432
2433/*
2434 * Reads an msr value (of 'msr_index') into 'pdata'.
2435 * Returns 0 on success, non-0 otherwise.
2436 * Assumes vcpu_load() was already called.
2437 */
2438int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2439{
2440 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2441}
ff651cb6 2442EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2443
9ba075a6
AK		 2444static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2445{
0bed3b56
SY		 2446 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2447
9ba075a6
AK		 2448 if (!msr_mtrr_valid(msr))
2449 return 1;
2450
0bed3b56
SY		 2451 if (msr == MSR_MTRRdefType)
2452 *pdata = vcpu->arch.mtrr_state.def_type +
2453 (vcpu->arch.mtrr_state.enabled << 10);
2454 else if (msr == MSR_MTRRfix64K_00000)
2455 *pdata = p[0];
2456 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2457 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2458 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2459 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2460 else if (msr == MSR_IA32_CR_PAT)
2461 *pdata = vcpu->arch.pat;
2462 else { /* Variable MTRRs */
2463 int idx, is_mtrr_mask;
2464 u64 *pt;
2465
2466 idx = (msr - 0x200) / 2;
2467 is_mtrr_mask = msr - 0x200 - 2 * idx;
2468 if (!is_mtrr_mask)
2469 pt =
2470 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2471 else
2472 pt =
2473 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2474 *pdata = *pt;
2475 }
2476
9ba075a6
AK		 2477 return 0;
2478}
2479
890ca9ae 2480static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2481{
2482 u64 data;
890ca9ae
HY		 2483 u64 mcg_cap = vcpu->arch.mcg_cap;
2484 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2485
2486 switch (msr) {
15c4a640
CO		 2487 case MSR_IA32_P5_MC_ADDR:
2488 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2489 data = 0;
2490 break;
15c4a640 2491 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2492 data = vcpu->arch.mcg_cap;
2493 break;
c7ac679c 2494 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2495 if (!(mcg_cap & MCG_CTL_P))
2496 return 1;
2497 data = vcpu->arch.mcg_ctl;
2498 break;
2499 case MSR_IA32_MCG_STATUS:
2500 data = vcpu->arch.mcg_status;
2501 break;
2502 default:
2503 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2504 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2505 u32 offset = msr - MSR_IA32_MC0_CTL;
2506 data = vcpu->arch.mce_banks[offset];
2507 break;
2508 }
2509 return 1;
2510 }
2511 *pdata = data;
2512 return 0;
2513}
2514
55cd8e5a
GN		 2515static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2516{
2517 u64 data = 0;
2518 struct kvm *kvm = vcpu->kvm;
2519
2520 switch (msr) {
2521 case HV_X64_MSR_GUEST_OS_ID:
2522 data = kvm->arch.hv_guest_os_id;
2523 break;
2524 case HV_X64_MSR_HYPERCALL:
2525 data = kvm->arch.hv_hypercall;
2526 break;
e984097b
VR		 2527 case HV_X64_MSR_TIME_REF_COUNT: {
2528 data =
2529 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2530 break;
2531 }
2532 case HV_X64_MSR_REFERENCE_TSC:
2533 data = kvm->arch.hv_tsc_page;
2534 break;
55cd8e5a 2535 default:
a737f256 2536 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2537 return 1;
2538 }
2539
2540 *pdata = data;
2541 return 0;
2542}
2543
2544static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2545{
2546 u64 data = 0;
2547
2548 switch (msr) {
2549 case HV_X64_MSR_VP_INDEX: {
2550 int r;
2551 struct kvm_vcpu *v;
684851a1
TY		 2552 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2553 if (v == vcpu) {
55cd8e5a 2554 data = r;
684851a1
TY		 2555 break;
2556 }
2557 }
55cd8e5a
GN		 2558 break;
2559 }
10388a07
GN		 2560 case HV_X64_MSR_EOI:
2561 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2562 case HV_X64_MSR_ICR:
2563 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2564 case HV_X64_MSR_TPR:
2565 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2566 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2567 data = vcpu->arch.hv_vapic;
2568 break;
55cd8e5a 2569 default:
a737f256 2570 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2571 return 1;
2572 }
2573 *pdata = data;
2574 return 0;
2575}
2576
890ca9ae
HY		 2577int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2578{
2579 u64 data;
2580
2581 switch (msr) {
890ca9ae 2582 case MSR_IA32_PLATFORM_ID:
15c4a640 2583 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2584 case MSR_IA32_DEBUGCTLMSR:
2585 case MSR_IA32_LASTBRANCHFROMIP:
2586 case MSR_IA32_LASTBRANCHTOIP:
2587 case MSR_IA32_LASTINTFROMIP:
2588 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2589 case MSR_K8_SYSCFG:
2590 case MSR_K7_HWCR:
61a6bd67 2591 case MSR_VM_HSAVE_PA:
9e699624 2592 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2593 case MSR_K7_EVNTSEL1:
2594 case MSR_K7_EVNTSEL2:
2595 case MSR_K7_EVNTSEL3:
1f3ee616 2596 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2597 case MSR_K7_PERFCTR1:
2598 case MSR_K7_PERFCTR2:
2599 case MSR_K7_PERFCTR3:
1fdbd48c 2600 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2601 case MSR_AMD64_NB_CFG:
f7c6d140 2602 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2603 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2604 data = 0;
2605 break;
5753785f
GN		 2606 case MSR_P6_PERFCTR0:
2607 case MSR_P6_PERFCTR1:
2608 case MSR_P6_EVNTSEL0:
2609 case MSR_P6_EVNTSEL1:
2610 if (kvm_pmu_msr(vcpu, msr))
2611 return kvm_pmu_get_msr(vcpu, msr, pdata);
2612 data = 0;
2613 break;
742bc670
MT		 2614 case MSR_IA32_UCODE_REV:
2615 data = 0x100000000ULL;
2616 break;
9ba075a6
AK		 2617 case MSR_MTRRcap:
2618 data = 0x500 | KVM_NR_VAR_MTRR;
2619 break;
2620 case 0x200 ... 0x2ff:
2621 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2622 case 0xcd: /* fsb frequency */
2623 data = 3;
2624 break;
7b914098
JS		 2625 /*
2626 * MSR_EBC_FREQUENCY_ID
2627 * Conservative value valid for even the basic CPU models.
2628 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2629 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2630 * and 266MHz for model 3, or 4. Set Core Clock
2631 * Frequency to System Bus Frequency Ratio to 1 (bits
2632 * 31:24) even though these are only valid for CPU
2633 * models > 2, however guests may end up dividing or
2634 * multiplying by zero otherwise.
2635 */
2636 case MSR_EBC_FREQUENCY_ID:
2637 data = 1 << 24;
2638 break;
15c4a640
CO		 2639 case MSR_IA32_APICBASE:
2640 data = kvm_get_apic_base(vcpu);
2641 break;
0105d1a5
GN		 2642 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2643 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2644 break;
a3e06bbe
LJ		 2645 case MSR_IA32_TSCDEADLINE:
2646 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2647 break;
ba904635
WA		 2648 case MSR_IA32_TSC_ADJUST:
2649 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2650 break;
15c4a640 2651 case MSR_IA32_MISC_ENABLE:
ad312c7c 2652 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2653 break;
847f0ad8
AG		 2654 case MSR_IA32_PERF_STATUS:
2655 /* TSC increment by tick */
2656 data = 1000ULL;
2657 /* CPU multiplier */
2658 data |= (((uint64_t)4ULL) << 40);
2659 break;
15c4a640 2660 case MSR_EFER:
f6801dff 2661 data = vcpu->arch.efer;
15c4a640 2662 break;
18068523 2663 case MSR_KVM_WALL_CLOCK:
11c6bffa 2664 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2665 data = vcpu->kvm->arch.wall_clock;
2666 break;
2667 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2668 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2669 data = vcpu->arch.time;
2670 break;
344d9588
GN		 2671 case MSR_KVM_ASYNC_PF_EN:
2672 data = vcpu->arch.apf.msr_val;
2673 break;
c9aaa895
GC		 2674 case MSR_KVM_STEAL_TIME:
2675 data = vcpu->arch.st.msr_val;
2676 break;
1d92128f
MT		 2677 case MSR_KVM_PV_EOI_EN:
2678 data = vcpu->arch.pv_eoi.msr_val;
2679 break;
890ca9ae
HY		 2680 case MSR_IA32_P5_MC_ADDR:
2681 case MSR_IA32_P5_MC_TYPE:
2682 case MSR_IA32_MCG_CAP:
2683 case MSR_IA32_MCG_CTL:
2684 case MSR_IA32_MCG_STATUS:
81760dcc 2685 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2686 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2687 case MSR_K7_CLK_CTL:
2688 /*
2689 * Provide expected ramp-up count for K7. All other
2690 * are set to zero, indicating minimum divisors for
2691 * every field.
2692 *
2693 * This prevents guest kernels on AMD host with CPU
2694 * type 6, model 8 and higher from exploding due to
2695 * the rdmsr failing.
2696 */
2697 data = 0x20000000;
2698 break;
55cd8e5a
GN		 2699 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2700 if (kvm_hv_msr_partition_wide(msr)) {
2701 int r;
2702 mutex_lock(&vcpu->kvm->lock);
2703 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2704 mutex_unlock(&vcpu->kvm->lock);
2705 return r;
2706 } else
2707 return get_msr_hyperv(vcpu, msr, pdata);
2708 break;
91c9c3ed 2709 case MSR_IA32_BBL_CR_CTL3:
2710 /* This legacy MSR exists but isn't fully documented in current
2711 * silicon. It is however accessed by winxp in very narrow
2712 * scenarios where it sets bit #19, itself documented as
2713 * a "reserved" bit. Best effort attempt to source coherent
2714 * read data here should the balance of the register be
2715 * interpreted by the guest:
2716 *
2717 * L2 cache control register 3: 64GB range, 256KB size,
2718 * enabled, latency 0x1, configured
2719 */
2720 data = 0xbe702111;
2721 break;
2b036c6b
BO		 2722 case MSR_AMD64_OSVW_ID_LENGTH:
2723 if (!guest_cpuid_has_osvw(vcpu))
2724 return 1;
2725 data = vcpu->arch.osvw.length;
2726 break;
2727 case MSR_AMD64_OSVW_STATUS:
2728 if (!guest_cpuid_has_osvw(vcpu))
2729 return 1;
2730 data = vcpu->arch.osvw.status;
2731 break;
15c4a640 2732 default:
f5132b01
GN		 2733 if (kvm_pmu_msr(vcpu, msr))
2734 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2735 if (!ignore_msrs) {
a737f256 2736 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2737 return 1;
2738 } else {
a737f256 2739 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2740 data = 0;
2741 }
2742 break;
15c4a640
CO		 2743 }
2744 *pdata = data;
2745 return 0;
2746}
2747EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2748
313a3dc7
CO		 2749/*
2750 * Read or write a bunch of msrs. All parameters are kernel addresses.
2751 *
2752 * @return number of msrs set successfully.
2753 */
2754static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2755 struct kvm_msr_entry *entries,
2756 int (*do_msr)(struct kvm_vcpu *vcpu,
2757 unsigned index, u64 *data))
2758{
f656ce01 2759 int i, idx;
313a3dc7 2760
f656ce01 2761 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2762 for (i = 0; i < msrs->nmsrs; ++i)
2763 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2764 break;
f656ce01 2765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2766
313a3dc7
CO		 2767 return i;
2768}
2769
2770/*
2771 * Read or write a bunch of msrs. Parameters are user addresses.
2772 *
2773 * @return number of msrs set successfully.
2774 */
2775static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2776 int (*do_msr)(struct kvm_vcpu *vcpu,
2777 unsigned index, u64 *data),
2778 int writeback)
2779{
2780 struct kvm_msrs msrs;
2781 struct kvm_msr_entry *entries;
2782 int r, n;
2783 unsigned size;
2784
2785 r = -EFAULT;
2786 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2787 goto out;
2788
2789 r = -E2BIG;
2790 if (msrs.nmsrs >= MAX_IO_MSRS)
2791 goto out;
2792
313a3dc7 2793 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2794 entries = memdup_user(user_msrs->entries, size);
2795 if (IS_ERR(entries)) {
2796 r = PTR_ERR(entries);
313a3dc7 2797 goto out;
ff5c2c03 2798 }
313a3dc7
CO		 2799
2800 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2801 if (r < 0)
2802 goto out_free;
2803
2804 r = -EFAULT;
2805 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2806 goto out_free;
2807
2808 r = n;
2809
2810out_free:
7a73c028 2811 kfree(entries);
313a3dc7
CO		 2812out:
2813 return r;
2814}
2815
784aa3d7 2816int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2817{
2818 int r;
2819
2820 switch (ext) {
2821 case KVM_CAP_IRQCHIP:
2822 case KVM_CAP_HLT:
2823 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2824 case KVM_CAP_SET_TSS_ADDR:
07716717 2825 case KVM_CAP_EXT_CPUID:
9c15bb1d 2826 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2827 case KVM_CAP_CLOCKSOURCE:
7837699f 2828 case KVM_CAP_PIT:
a28e4f5a 2829 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2830 case KVM_CAP_MP_STATE:
ed848624 2831 case KVM_CAP_SYNC_MMU:
a355c85c 2832 case KVM_CAP_USER_NMI:
52d939a0 2833 case KVM_CAP_REINJECT_CONTROL:
4925663a 2834 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2835 case KVM_CAP_IOEVENTFD:
f848a5a8 2836 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2837 case KVM_CAP_PIT2:
e9f42757 2838 case KVM_CAP_PIT_STATE2:
b927a3ce 2839 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2840 case KVM_CAP_XEN_HVM:
afbcf7ab 2841 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2842 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2843 case KVM_CAP_HYPERV:
10388a07 2844 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2845 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2846 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2847 case KVM_CAP_DEBUGREGS:
d2be1651 2848 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2849 case KVM_CAP_XSAVE:
344d9588 2850 case KVM_CAP_ASYNC_PF:
92a1f12d 2851 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2852 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2853 case KVM_CAP_READONLY_MEM:
5f66b620 2854 case KVM_CAP_HYPERV_TIME:
100943c5 2855 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2856 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2857 case KVM_CAP_ENABLE_CAP_VM:
2858 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2859#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2860 case KVM_CAP_ASSIGN_DEV_IRQ:
2861 case KVM_CAP_PCI_2_3:
2862#endif
018d00d2
ZX		 2863 r = 1;
2864 break;
542472b5
LV		 2865 case KVM_CAP_COALESCED_MMIO:
2866 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2867 break;
774ead3a
AK		 2868 case KVM_CAP_VAPIC:
2869 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2870 break;
f725230a 2871 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2872 r = KVM_SOFT_MAX_VCPUS;
2873 break;
2874 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2875 r = KVM_MAX_VCPUS;
2876 break;
a988b910 2877 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2878 r = KVM_USER_MEM_SLOTS;
a988b910 2879 break;
a68a6a72
MT		 2880 case KVM_CAP_PV_MMU: /* obsolete */
2881 r = 0;
2f333bcb 2882 break;
4cee4b72 2883#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2884 case KVM_CAP_IOMMU:
a1b60c1c 2885 r = iommu_present(&pci_bus_type);
62c476c7 2886 break;
4cee4b72 2887#endif
890ca9ae
HY		 2888 case KVM_CAP_MCE:
2889 r = KVM_MAX_MCE_BANKS;
2890 break;
2d5b5a66
SY		 2891 case KVM_CAP_XCRS:
2892 r = cpu_has_xsave;
2893 break;
92a1f12d
JR		 2894 case KVM_CAP_TSC_CONTROL:
2895 r = kvm_has_tsc_control;
2896 break;
018d00d2
ZX		 2897 default:
2898 r = 0;
2899 break;
2900 }
2901 return r;
2902
2903}
2904
043405e1
CO		 2905long kvm_arch_dev_ioctl(struct file *filp,
2906 unsigned int ioctl, unsigned long arg)
2907{
2908 void __user *argp = (void __user *)arg;
2909 long r;
2910
2911 switch (ioctl) {
2912 case KVM_GET_MSR_INDEX_LIST: {
2913 struct kvm_msr_list __user *user_msr_list = argp;
2914 struct kvm_msr_list msr_list;
2915 unsigned n;
2916
2917 r = -EFAULT;
2918 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2919 goto out;
2920 n = msr_list.nmsrs;
2921 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2922 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2923 goto out;
2924 r = -E2BIG;
e125e7b6 2925 if (n < msr_list.nmsrs)
043405e1
CO		 2926 goto out;
2927 r = -EFAULT;
2928 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2929 num_msrs_to_save * sizeof(u32)))
2930 goto out;
e125e7b6 2931 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2932 &emulated_msrs,
2933 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2934 goto out;
2935 r = 0;
2936 break;
2937 }
9c15bb1d
BP		 2938 case KVM_GET_SUPPORTED_CPUID:
2939 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2940 struct kvm_cpuid2 __user *cpuid_arg = argp;
2941 struct kvm_cpuid2 cpuid;
2942
2943 r = -EFAULT;
2944 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2945 goto out;
9c15bb1d
BP		 2946
2947 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2948 ioctl);
674eea0f
AK		 2949 if (r)
2950 goto out;
2951
2952 r = -EFAULT;
2953 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2954 goto out;
2955 r = 0;
2956 break;
2957 }
890ca9ae
HY		 2958 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2959 u64 mce_cap;
2960
2961 mce_cap = KVM_MCE_CAP_SUPPORTED;
2962 r = -EFAULT;
2963 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2964 goto out;
2965 r = 0;
2966 break;
2967 }
043405e1
CO		 2968 default:
2969 r = -EINVAL;
2970 }
2971out:
2972 return r;
2973}
2974
f5f48ee1
SY		 2975static void wbinvd_ipi(void *garbage)
2976{
2977 wbinvd();
2978}
2979
2980static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2981{
e0f0bbc5 2982 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2983}
2984
313a3dc7
CO		 2985void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2986{
f5f48ee1
SY		 2987 /* Address WBINVD may be executed by guest */
2988 if (need_emulate_wbinvd(vcpu)) {
2989 if (kvm_x86_ops->has_wbinvd_exit())
2990 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2991 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2992 smp_call_function_single(vcpu->cpu,
2993 wbinvd_ipi, NULL, 1);
2994 }
2995
313a3dc7 2996 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2997
0dd6a6ed
ZA		 2998 /* Apply any externally detected TSC adjustments (due to suspend) */
2999 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3000 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3001 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3002 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3003 }
8f6055cb 3004
48434c20 3005 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 3006 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3007 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3008 if (tsc_delta < 0)
3009 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 3010 if (check_tsc_unstable()) {
b183aa58
ZA		 3011 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
3012 vcpu->arch.last_guest_tsc);
3013 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 3014 vcpu->arch.tsc_catchup = 1;
c285545f 3015 }
d98d07ca
MT		 3016 /*
3017 * On a host with synchronized TSC, there is no need to update
3018 * kvmclock on vcpu->cpu migration
3019 */
3020 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3021 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 3022 if (vcpu->cpu != cpu)
3023 kvm_migrate_timers(vcpu);
e48672fa 3024 vcpu->cpu = cpu;
6b7d7e76 3025 }
c9aaa895
GC		 3026
3027 accumulate_steal_time(vcpu);
3028 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3029}
3030
3031void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3032{
02daab21 3033 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 3034 kvm_put_guest_fpu(vcpu);
6f526ec5 3035 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 3036}
3037
313a3dc7
CO		 3038static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3039 struct kvm_lapic_state *s)
3040{
5a71785d 3041 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 3042 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 3043
3044 return 0;
3045}
3046
3047static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3048 struct kvm_lapic_state *s)
3049{
64eb0620 3050 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 3051 update_cr8_intercept(vcpu);
313a3dc7
CO		 3052
3053 return 0;
3054}
3055
f77bc6a4
ZX		 3056static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3057 struct kvm_interrupt *irq)
3058{
02cdb50f 3059 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3060 return -EINVAL;
3061 if (irqchip_in_kernel(vcpu->kvm))
3062 return -ENXIO;
f77bc6a4 3063
66fd3f7f 3064 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3065 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3066
f77bc6a4
ZX		 3067 return 0;
3068}
3069
c4abb7c9
JK		 3070static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3071{
c4abb7c9 3072 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3073
3074 return 0;
3075}
3076
b209749f
AK		 3077static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3078 struct kvm_tpr_access_ctl *tac)
3079{
3080 if (tac->flags)
3081 return -EINVAL;
3082 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3083 return 0;
3084}
3085
890ca9ae
HY		 3086static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3087 u64 mcg_cap)
3088{
3089 int r;
3090 unsigned bank_num = mcg_cap & 0xff, bank;
3091
3092 r = -EINVAL;
a9e38c3e 3093 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3094 goto out;
3095 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3096 goto out;
3097 r = 0;
3098 vcpu->arch.mcg_cap = mcg_cap;
3099 /* Init IA32_MCG_CTL to all 1s */
3100 if (mcg_cap & MCG_CTL_P)
3101 vcpu->arch.mcg_ctl = ~(u64)0;
3102 /* Init IA32_MCi_CTL to all 1s */
3103 for (bank = 0; bank < bank_num; bank++)
3104 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3105out:
3106 return r;
3107}
3108
3109static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3110 struct kvm_x86_mce *mce)
3111{
3112 u64 mcg_cap = vcpu->arch.mcg_cap;
3113 unsigned bank_num = mcg_cap & 0xff;
3114 u64 *banks = vcpu->arch.mce_banks;
3115
3116 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3117 return -EINVAL;
3118 /*
3119 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3120 * reporting is disabled
3121 */
3122 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3123 vcpu->arch.mcg_ctl != ~(u64)0)
3124 return 0;
3125 banks += 4 * mce->bank;
3126 /*
3127 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3128 * reporting is disabled for the bank
3129 */
3130 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3131 return 0;
3132 if (mce->status & MCI_STATUS_UC) {
3133 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3134 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3135 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3136 return 0;
3137 }
3138 if (banks[1] & MCI_STATUS_VAL)
3139 mce->status |= MCI_STATUS_OVER;
3140 banks[2] = mce->addr;
3141 banks[3] = mce->misc;
3142 vcpu->arch.mcg_status = mce->mcg_status;
3143 banks[1] = mce->status;
3144 kvm_queue_exception(vcpu, MC_VECTOR);
3145 } else if (!(banks[1] & MCI_STATUS_VAL)
3146 || !(banks[1] & MCI_STATUS_UC)) {
3147 if (banks[1] & MCI_STATUS_VAL)
3148 mce->status |= MCI_STATUS_OVER;
3149 banks[2] = mce->addr;
3150 banks[3] = mce->misc;
3151 banks[1] = mce->status;
3152 } else
3153 banks[1] |= MCI_STATUS_OVER;
3154 return 0;
3155}
3156
3cfc3092
JK		 3157static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3158 struct kvm_vcpu_events *events)
3159{
7460fb4a 3160 process_nmi(vcpu);
03b82a30
JK		 3161 events->exception.injected =
3162 vcpu->arch.exception.pending &&
3163 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3164 events->exception.nr = vcpu->arch.exception.nr;
3165 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3166 events->exception.pad = 0;
3cfc3092
JK		 3167 events->exception.error_code = vcpu->arch.exception.error_code;
3168
03b82a30
JK		 3169 events->interrupt.injected =
3170 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3171 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3172 events->interrupt.soft = 0;
37ccdcbe 3173 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3174
3175 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3176 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3177 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3178 events->nmi.pad = 0;
3cfc3092 3179
66450a21 3180 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3181
dab4b911 3182 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3183 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3184 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3185}
3186
3187static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3188 struct kvm_vcpu_events *events)
3189{
dab4b911 3190 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3191 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3192 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3193 return -EINVAL;
3194
7460fb4a 3195 process_nmi(vcpu);
3cfc3092
JK		 3196 vcpu->arch.exception.pending = events->exception.injected;
3197 vcpu->arch.exception.nr = events->exception.nr;
3198 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3199 vcpu->arch.exception.error_code = events->exception.error_code;
3200
3201 vcpu->arch.interrupt.pending = events->interrupt.injected;
3202 vcpu->arch.interrupt.nr = events->interrupt.nr;
3203 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3204 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3205 kvm_x86_ops->set_interrupt_shadow(vcpu,
3206 events->interrupt.shadow);
3cfc3092
JK		 3207
3208 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3209 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3210 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3211 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3212
66450a21
JK		 3213 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3214 kvm_vcpu_has_lapic(vcpu))
3215 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3216
3842d135
AK		 3217 kvm_make_request(KVM_REQ_EVENT, vcpu);
3218
3cfc3092
JK		 3219 return 0;
3220}
3221
a1efbe77
JK		 3222static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3223 struct kvm_debugregs *dbgregs)
3224{
73aaf249
JK		 3225 unsigned long val;
3226
a1efbe77 3227 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3228 kvm_get_dr(vcpu, 6, &val);
73aaf249 3229 dbgregs->dr6 = val;
a1efbe77
JK		 3230 dbgregs->dr7 = vcpu->arch.dr7;
3231 dbgregs->flags = 0;
97e69aa6 3232 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3233}
3234
3235static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3236 struct kvm_debugregs *dbgregs)
3237{
3238 if (dbgregs->flags)
3239 return -EINVAL;
3240
a1efbe77 3241 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3242 kvm_update_dr0123(vcpu);
a1efbe77 3243 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3244 kvm_update_dr6(vcpu);
a1efbe77 3245 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3246 kvm_update_dr7(vcpu);
a1efbe77 3247
a1efbe77
JK		 3248 return 0;
3249}
3250
df1daba7
PB		 3251#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3252
3253static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3254{
3255 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3256 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3257 u64 valid;
3258
3259 /*
3260 * Copy legacy XSAVE area, to avoid complications with CPUID
3261 * leaves 0 and 1 in the loop below.
3262 */
3263 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3264
3265 /* Set XSTATE_BV */
3266 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3267
3268 /*
3269 * Copy each region from the possibly compacted offset to the
3270 * non-compacted offset.
3271 */
3272 valid = xstate_bv & ~XSTATE_FPSSE;
3273 while (valid) {
3274 u64 feature = valid & -valid;
3275 int index = fls64(feature) - 1;
3276 void *src = get_xsave_addr(xsave, feature);
3277
3278 if (src) {
3279 u32 size, offset, ecx, edx;
3280 cpuid_count(XSTATE_CPUID, index,
3281 &size, &offset, &ecx, &edx);
3282 memcpy(dest + offset, src, size);
3283 }
3284
3285 valid -= feature;
3286 }
3287}
3288
3289static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3290{
3291 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3292 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3293 u64 valid;
3294
3295 /*
3296 * Copy legacy XSAVE area, to avoid complications with CPUID
3297 * leaves 0 and 1 in the loop below.
3298 */
3299 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3300
3301 /* Set XSTATE_BV and possibly XCOMP_BV. */
3302 xsave->xsave_hdr.xstate_bv = xstate_bv;
3303 if (cpu_has_xsaves)
3304 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3305
3306 /*
3307 * Copy each region from the non-compacted offset to the
3308 * possibly compacted offset.
3309 */
3310 valid = xstate_bv & ~XSTATE_FPSSE;
3311 while (valid) {
3312 u64 feature = valid & -valid;
3313 int index = fls64(feature) - 1;
3314 void *dest = get_xsave_addr(xsave, feature);
3315
3316 if (dest) {
3317 u32 size, offset, ecx, edx;
3318 cpuid_count(XSTATE_CPUID, index,
3319 &size, &offset, &ecx, &edx);
3320 memcpy(dest, src + offset, size);
3321 } else
3322 WARN_ON_ONCE(1);
3323
3324 valid -= feature;
3325 }
3326}
3327
2d5b5a66
SY		 3328static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3329 struct kvm_xsave *guest_xsave)
3330{
4344ee98 3331 if (cpu_has_xsave) {
df1daba7
PB		 3332 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3333 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3334 } else {
2d5b5a66
SY		 3335 memcpy(guest_xsave->region,
3336 &vcpu->arch.guest_fpu.state->fxsave,
3337 sizeof(struct i387_fxsave_struct));
3338 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3339 XSTATE_FPSSE;
3340 }
3341}
3342
3343static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3344 struct kvm_xsave *guest_xsave)
3345{
3346 u64 xstate_bv =
3347 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3348
d7876f1b
PB		 3349 if (cpu_has_xsave) {
3350 /*
3351 * Here we allow setting states that are not present in
3352 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3353 * with old userspace.
3354 */
4ff41732 3355 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3356 return -EINVAL;
df1daba7 3357 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3358 } else {
2d5b5a66
SY		 3359 if (xstate_bv & ~XSTATE_FPSSE)
3360 return -EINVAL;
3361 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3362 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3363 }
3364 return 0;
3365}
3366
3367static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3368 struct kvm_xcrs *guest_xcrs)
3369{
3370 if (!cpu_has_xsave) {
3371 guest_xcrs->nr_xcrs = 0;
3372 return;
3373 }
3374
3375 guest_xcrs->nr_xcrs = 1;
3376 guest_xcrs->flags = 0;
3377 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3378 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3379}
3380
3381static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3382 struct kvm_xcrs *guest_xcrs)
3383{
3384 int i, r = 0;
3385
3386 if (!cpu_has_xsave)
3387 return -EINVAL;
3388
3389 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3390 return -EINVAL;
3391
3392 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3393 /* Only support XCR0 currently */
c67a04cb 3394 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3395 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3396 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3397 break;
3398 }
3399 if (r)
3400 r = -EINVAL;
3401 return r;
3402}
3403
1c0b28c2
EM		 3404/*
3405 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3406 * stopped by the hypervisor. This function will be called from the host only.
3407 * EINVAL is returned when the host attempts to set the flag for a guest that
3408 * does not support pv clocks.
3409 */
3410static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3411{
0b79459b 3412 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3413 return -EINVAL;
51d59c6b 3414 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3415 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3416 return 0;
3417}
3418
313a3dc7
CO		 3419long kvm_arch_vcpu_ioctl(struct file *filp,
3420 unsigned int ioctl, unsigned long arg)
3421{
3422 struct kvm_vcpu *vcpu = filp->private_data;
3423 void __user *argp = (void __user *)arg;
3424 int r;
d1ac91d8
AK		 3425 union {
3426 struct kvm_lapic_state *lapic;
3427 struct kvm_xsave *xsave;
3428 struct kvm_xcrs *xcrs;
3429 void *buffer;
3430 } u;
3431
3432 u.buffer = NULL;
313a3dc7
CO		 3433 switch (ioctl) {
3434 case KVM_GET_LAPIC: {
2204ae3c
MT		 3435 r = -EINVAL;
3436 if (!vcpu->arch.apic)
3437 goto out;
d1ac91d8 3438 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3439
b772ff36 3440 r = -ENOMEM;
d1ac91d8 3441 if (!u.lapic)
b772ff36 3442 goto out;
d1ac91d8 3443 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3444 if (r)
3445 goto out;
3446 r = -EFAULT;
d1ac91d8 3447 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3448 goto out;
3449 r = 0;
3450 break;
3451 }
3452 case KVM_SET_LAPIC: {
2204ae3c
MT		 3453 r = -EINVAL;
3454 if (!vcpu->arch.apic)
3455 goto out;
ff5c2c03 3456 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3457 if (IS_ERR(u.lapic))
3458 return PTR_ERR(u.lapic);
ff5c2c03 3459
d1ac91d8 3460 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3461 break;
3462 }
f77bc6a4
ZX		 3463 case KVM_INTERRUPT: {
3464 struct kvm_interrupt irq;
3465
3466 r = -EFAULT;
3467 if (copy_from_user(&irq, argp, sizeof irq))
3468 goto out;
3469 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3470 break;
3471 }
c4abb7c9
JK		 3472 case KVM_NMI: {
3473 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3474 break;
3475 }
313a3dc7
CO		 3476 case KVM_SET_CPUID: {
3477 struct kvm_cpuid __user *cpuid_arg = argp;
3478 struct kvm_cpuid cpuid;
3479
3480 r = -EFAULT;
3481 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3482 goto out;
3483 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3484 break;
3485 }
07716717
DK		 3486 case KVM_SET_CPUID2: {
3487 struct kvm_cpuid2 __user *cpuid_arg = argp;
3488 struct kvm_cpuid2 cpuid;
3489
3490 r = -EFAULT;
3491 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3492 goto out;
3493 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3494 cpuid_arg->entries);
07716717
DK		 3495 break;
3496 }
3497 case KVM_GET_CPUID2: {
3498 struct kvm_cpuid2 __user *cpuid_arg = argp;
3499 struct kvm_cpuid2 cpuid;
3500
3501 r = -EFAULT;
3502 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3503 goto out;
3504 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3505 cpuid_arg->entries);
07716717
DK		 3506 if (r)
3507 goto out;
3508 r = -EFAULT;
3509 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3510 goto out;
3511 r = 0;
3512 break;
3513 }
313a3dc7
CO		 3514 case KVM_GET_MSRS:
3515 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3516 break;
3517 case KVM_SET_MSRS:
3518 r = msr_io(vcpu, argp, do_set_msr, 0);
3519 break;
b209749f
AK		 3520 case KVM_TPR_ACCESS_REPORTING: {
3521 struct kvm_tpr_access_ctl tac;
3522
3523 r = -EFAULT;
3524 if (copy_from_user(&tac, argp, sizeof tac))
3525 goto out;
3526 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3527 if (r)
3528 goto out;
3529 r = -EFAULT;
3530 if (copy_to_user(argp, &tac, sizeof tac))
3531 goto out;
3532 r = 0;
3533 break;
3534 };
b93463aa
AK		 3535 case KVM_SET_VAPIC_ADDR: {
3536 struct kvm_vapic_addr va;
3537
3538 r = -EINVAL;
3539 if (!irqchip_in_kernel(vcpu->kvm))
3540 goto out;
3541 r = -EFAULT;
3542 if (copy_from_user(&va, argp, sizeof va))
3543 goto out;
fda4e2e8 3544 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3545 break;
3546 }
890ca9ae
HY		 3547 case KVM_X86_SETUP_MCE: {
3548 u64 mcg_cap;
3549
3550 r = -EFAULT;
3551 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3552 goto out;
3553 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3554 break;
3555 }
3556 case KVM_X86_SET_MCE: {
3557 struct kvm_x86_mce mce;
3558
3559 r = -EFAULT;
3560 if (copy_from_user(&mce, argp, sizeof mce))
3561 goto out;
3562 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3563 break;
3564 }
3cfc3092
JK		 3565 case KVM_GET_VCPU_EVENTS: {
3566 struct kvm_vcpu_events events;
3567
3568 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3569
3570 r = -EFAULT;
3571 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3572 break;
3573 r = 0;
3574 break;
3575 }
3576 case KVM_SET_VCPU_EVENTS: {
3577 struct kvm_vcpu_events events;
3578
3579 r = -EFAULT;
3580 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3581 break;
3582
3583 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3584 break;
3585 }
a1efbe77
JK		 3586 case KVM_GET_DEBUGREGS: {
3587 struct kvm_debugregs dbgregs;
3588
3589 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3590
3591 r = -EFAULT;
3592 if (copy_to_user(argp, &dbgregs,
3593 sizeof(struct kvm_debugregs)))
3594 break;
3595 r = 0;
3596 break;
3597 }
3598 case KVM_SET_DEBUGREGS: {
3599 struct kvm_debugregs dbgregs;
3600
3601 r = -EFAULT;
3602 if (copy_from_user(&dbgregs, argp,
3603 sizeof(struct kvm_debugregs)))
3604 break;
3605
3606 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3607 break;
3608 }
2d5b5a66 3609 case KVM_GET_XSAVE: {
d1ac91d8 3610 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3611 r = -ENOMEM;
d1ac91d8 3612 if (!u.xsave)
2d5b5a66
SY		 3613 break;
3614
d1ac91d8 3615 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3616
3617 r = -EFAULT;
d1ac91d8 3618 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3619 break;
3620 r = 0;
3621 break;
3622 }
3623 case KVM_SET_XSAVE: {
ff5c2c03 3624 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3625 if (IS_ERR(u.xsave))
3626 return PTR_ERR(u.xsave);
2d5b5a66 3627
d1ac91d8 3628 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3629 break;
3630 }
3631 case KVM_GET_XCRS: {
d1ac91d8 3632 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3633 r = -ENOMEM;
d1ac91d8 3634 if (!u.xcrs)
2d5b5a66
SY		 3635 break;
3636
d1ac91d8 3637 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3638
3639 r = -EFAULT;
d1ac91d8 3640 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3641 sizeof(struct kvm_xcrs)))
3642 break;
3643 r = 0;
3644 break;
3645 }
3646 case KVM_SET_XCRS: {
ff5c2c03 3647 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3648 if (IS_ERR(u.xcrs))
3649 return PTR_ERR(u.xcrs);
2d5b5a66 3650
d1ac91d8 3651 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3652 break;
3653 }
92a1f12d
JR		 3654 case KVM_SET_TSC_KHZ: {
3655 u32 user_tsc_khz;
3656
3657 r = -EINVAL;
92a1f12d
JR		 3658 user_tsc_khz = (u32)arg;
3659
3660 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3661 goto out;
3662
cc578287
ZA		 3663 if (user_tsc_khz == 0)
3664 user_tsc_khz = tsc_khz;
3665
3666 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3667
3668 r = 0;
3669 goto out;
3670 }
3671 case KVM_GET_TSC_KHZ: {
cc578287 3672 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3673 goto out;
3674 }
1c0b28c2
EM		 3675 case KVM_KVMCLOCK_CTRL: {
3676 r = kvm_set_guest_paused(vcpu);
3677 goto out;
3678 }
313a3dc7
CO		 3679 default:
3680 r = -EINVAL;
3681 }
3682out:
d1ac91d8 3683 kfree(u.buffer);
313a3dc7
CO		 3684 return r;
3685}
3686
5b1c1493
CO		 3687int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3688{
3689 return VM_FAULT_SIGBUS;
3690}
3691
1fe779f8
CO		 3692static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3693{
3694 int ret;
3695
3696 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3697 return -EINVAL;
1fe779f8
CO		 3698 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3699 return ret;
3700}
3701
b927a3ce
SY		 3702static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3703 u64 ident_addr)
3704{
3705 kvm->arch.ept_identity_map_addr = ident_addr;
3706 return 0;
3707}
3708
1fe779f8
CO		 3709static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3710 u32 kvm_nr_mmu_pages)
3711{
3712 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3713 return -EINVAL;
3714
79fac95e 3715 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3716
3717 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3718 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3719
79fac95e 3720 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3721 return 0;
3722}
3723
3724static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3725{
39de71ec 3726 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3727}
3728
1fe779f8
CO		 3729static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3730{
3731 int r;
3732
3733 r = 0;
3734 switch (chip->chip_id) {
3735 case KVM_IRQCHIP_PIC_MASTER:
3736 memcpy(&chip->chip.pic,
3737 &pic_irqchip(kvm)->pics[0],
3738 sizeof(struct kvm_pic_state));
3739 break;
3740 case KVM_IRQCHIP_PIC_SLAVE:
3741 memcpy(&chip->chip.pic,
3742 &pic_irqchip(kvm)->pics[1],
3743 sizeof(struct kvm_pic_state));
3744 break;
3745 case KVM_IRQCHIP_IOAPIC:
eba0226b 3746 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3747 break;
3748 default:
3749 r = -EINVAL;
3750 break;
3751 }
3752 return r;
3753}
3754
3755static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3756{
3757 int r;
3758
3759 r = 0;
3760 switch (chip->chip_id) {
3761 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3762 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3763 memcpy(&pic_irqchip(kvm)->pics[0],
3764 &chip->chip.pic,
3765 sizeof(struct kvm_pic_state));
f4f51050 3766 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3767 break;
3768 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3769 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3770 memcpy(&pic_irqchip(kvm)->pics[1],
3771 &chip->chip.pic,
3772 sizeof(struct kvm_pic_state));
f4f51050 3773 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3774 break;
3775 case KVM_IRQCHIP_IOAPIC:
eba0226b 3776 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3777 break;
3778 default:
3779 r = -EINVAL;
3780 break;
3781 }
3782 kvm_pic_update_irq(pic_irqchip(kvm));
3783 return r;
3784}
3785
e0f63cb9
SY		 3786static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3787{
3788 int r = 0;
3789
894a9c55 3790 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3791 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3792 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3793 return r;
3794}
3795
3796static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3797{
3798 int r = 0;
3799
894a9c55 3800 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3801 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3802 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3803 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3804 return r;
3805}
3806
3807static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3808{
3809 int r = 0;
3810
3811 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3812 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3813 sizeof(ps->channels));
3814 ps->flags = kvm->arch.vpit->pit_state.flags;
3815 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3816 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3817 return r;
3818}
3819
3820static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3821{
3822 int r = 0, start = 0;
3823 u32 prev_legacy, cur_legacy;
3824 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3825 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3826 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3827 if (!prev_legacy && cur_legacy)
3828 start = 1;
3829 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3830 sizeof(kvm->arch.vpit->pit_state.channels));
3831 kvm->arch.vpit->pit_state.flags = ps->flags;
3832 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3833 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3834 return r;
3835}
3836
52d939a0
MT		 3837static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3838 struct kvm_reinject_control *control)
3839{
3840 if (!kvm->arch.vpit)
3841 return -ENXIO;
894a9c55 3842 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3843 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3844 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3845 return 0;
3846}
3847
95d4c16c 3848/**
60c34612
TY		 3849 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3850 * @kvm: kvm instance
3851 * @log: slot id and address to which we copy the log
95d4c16c 3852 *
e108ff2f
PB		 3853 * Steps 1-4 below provide general overview of dirty page logging. See
3854 * kvm_get_dirty_log_protect() function description for additional details.
3855 *
3856 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3857 * always flush the TLB (step 4) even if previous step failed and the dirty
3858 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3859 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3860 * writes will be marked dirty for next log read.
95d4c16c 3861 *
60c34612
TY		 3862 * 1. Take a snapshot of the bit and clear it if needed.
3863 * 2. Write protect the corresponding page.
e108ff2f
PB		 3864 * 3. Copy the snapshot to the userspace.
3865 * 4. Flush TLB's if needed.
5bb064dc 3866 */
60c34612 3867int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3868{
60c34612 3869 bool is_dirty = false;
e108ff2f 3870 int r;
5bb064dc 3871
79fac95e 3872 mutex_lock(&kvm->slots_lock);
5bb064dc 3873
88178fd4
KH		 3874 /*
3875 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3876 */
3877 if (kvm_x86_ops->flush_log_dirty)
3878 kvm_x86_ops->flush_log_dirty(kvm);
3879
e108ff2f 3880 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3881
3882 /*
3883 * All the TLBs can be flushed out of mmu lock, see the comments in
3884 * kvm_mmu_slot_remove_write_access().
3885 */
e108ff2f 3886 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3887 if (is_dirty)
3888 kvm_flush_remote_tlbs(kvm);
3889
79fac95e 3890 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3891 return r;
3892}
3893
aa2fbe6d
YZ		 3894int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3895 bool line_status)
23d43cf9
CD		 3896{
3897 if (!irqchip_in_kernel(kvm))
3898 return -ENXIO;
3899
3900 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3901 irq_event->irq, irq_event->level,
3902 line_status);
23d43cf9
CD		 3903 return 0;
3904}
3905
90de4a18
NA		 3906static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3907 struct kvm_enable_cap *cap)
3908{
3909 int r;
3910
3911 if (cap->flags)
3912 return -EINVAL;
3913
3914 switch (cap->cap) {
3915 case KVM_CAP_DISABLE_QUIRKS:
3916 kvm->arch.disabled_quirks = cap->args[0];
3917 r = 0;
3918 break;
3919 default:
3920 r = -EINVAL;
3921 break;
3922 }
3923 return r;
3924}
3925
1fe779f8
CO		 3926long kvm_arch_vm_ioctl(struct file *filp,
3927 unsigned int ioctl, unsigned long arg)
3928{
3929 struct kvm *kvm = filp->private_data;
3930 void __user *argp = (void __user *)arg;
367e1319 3931 int r = -ENOTTY;
f0d66275
DH		 3932 /*
3933 * This union makes it completely explicit to gcc-3.x
3934 * that these two variables' stack usage should be
3935 * combined, not added together.
3936 */
3937 union {
3938 struct kvm_pit_state ps;
e9f42757 3939 struct kvm_pit_state2 ps2;
c5ff41ce 3940 struct kvm_pit_config pit_config;
f0d66275 3941 } u;
1fe779f8
CO		 3942
3943 switch (ioctl) {
3944 case KVM_SET_TSS_ADDR:
3945 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3946 break;
b927a3ce
SY		 3947 case KVM_SET_IDENTITY_MAP_ADDR: {
3948 u64 ident_addr;
3949
3950 r = -EFAULT;
3951 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3952 goto out;
3953 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3954 break;
3955 }
1fe779f8
CO		 3956 case KVM_SET_NR_MMU_PAGES:
3957 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3958 break;
3959 case KVM_GET_NR_MMU_PAGES:
3960 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3961 break;
3ddea128
MT		 3962 case KVM_CREATE_IRQCHIP: {
3963 struct kvm_pic *vpic;
3964
3965 mutex_lock(&kvm->lock);
3966 r = -EEXIST;
3967 if (kvm->arch.vpic)
3968 goto create_irqchip_unlock;
3e515705
AK		 3969 r = -EINVAL;
3970 if (atomic_read(&kvm->online_vcpus))
3971 goto create_irqchip_unlock;
1fe779f8 3972 r = -ENOMEM;
3ddea128
MT		 3973 vpic = kvm_create_pic(kvm);
3974 if (vpic) {
1fe779f8
CO		 3975 r = kvm_ioapic_init(kvm);
3976 if (r) {
175504cd 3977 mutex_lock(&kvm->slots_lock);
72bb2fcd 3978 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3979 &vpic->dev_master);
3980 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3981 &vpic->dev_slave);
3982 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3983 &vpic->dev_eclr);
175504cd 3984 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3985 kfree(vpic);
3986 goto create_irqchip_unlock;
1fe779f8
CO		 3987 }
3988 } else
3ddea128
MT		 3989 goto create_irqchip_unlock;
3990 smp_wmb();
3991 kvm->arch.vpic = vpic;
3992 smp_wmb();
399ec807
AK		 3993 r = kvm_setup_default_irq_routing(kvm);
3994 if (r) {
175504cd 3995 mutex_lock(&kvm->slots_lock);
3ddea128 3996 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3997 kvm_ioapic_destroy(kvm);
3998 kvm_destroy_pic(kvm);
3ddea128 3999 mutex_unlock(&kvm->irq_lock);
175504cd 4000 mutex_unlock(&kvm->slots_lock);
399ec807 4001 }
3ddea128
MT		 4002 create_irqchip_unlock:
4003 mutex_unlock(&kvm->lock);
1fe779f8 4004 break;
3ddea128 4005 }
7837699f 4006 case KVM_CREATE_PIT:
c5ff41ce
JK		 4007 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4008 goto create_pit;
4009 case KVM_CREATE_PIT2:
4010 r = -EFAULT;
4011 if (copy_from_user(&u.pit_config, argp,
4012 sizeof(struct kvm_pit_config)))
4013 goto out;
4014 create_pit:
79fac95e 4015 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 4016 r = -EEXIST;
4017 if (kvm->arch.vpit)
4018 goto create_pit_unlock;
7837699f 4019 r = -ENOMEM;
c5ff41ce 4020 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4021 if (kvm->arch.vpit)
4022 r = 0;
269e05e4 4023 create_pit_unlock:
79fac95e 4024 mutex_unlock(&kvm->slots_lock);
7837699f 4025 break;
1fe779f8
CO		 4026 case KVM_GET_IRQCHIP: {
4027 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4028 struct kvm_irqchip *chip;
1fe779f8 4029
ff5c2c03
SL		 4030 chip = memdup_user(argp, sizeof(*chip));
4031 if (IS_ERR(chip)) {
4032 r = PTR_ERR(chip);
1fe779f8 4033 goto out;
ff5c2c03
SL		 4034 }
4035
1fe779f8
CO		 4036 r = -ENXIO;
4037 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4038 goto get_irqchip_out;
4039 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4040 if (r)
f0d66275 4041 goto get_irqchip_out;
1fe779f8 4042 r = -EFAULT;
f0d66275
DH		 4043 if (copy_to_user(argp, chip, sizeof *chip))
4044 goto get_irqchip_out;
1fe779f8 4045 r = 0;
f0d66275
DH		 4046 get_irqchip_out:
4047 kfree(chip);
1fe779f8
CO		 4048 break;
4049 }
4050 case KVM_SET_IRQCHIP: {
4051 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4052 struct kvm_irqchip *chip;
1fe779f8 4053
ff5c2c03
SL		 4054 chip = memdup_user(argp, sizeof(*chip));
4055 if (IS_ERR(chip)) {
4056 r = PTR_ERR(chip);
1fe779f8 4057 goto out;
ff5c2c03
SL		 4058 }
4059
1fe779f8
CO		 4060 r = -ENXIO;
4061 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4062 goto set_irqchip_out;
4063 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4064 if (r)
f0d66275 4065 goto set_irqchip_out;
1fe779f8 4066 r = 0;
f0d66275
DH		 4067 set_irqchip_out:
4068 kfree(chip);
1fe779f8
CO		 4069 break;
4070 }
e0f63cb9 4071 case KVM_GET_PIT: {
e0f63cb9 4072 r = -EFAULT;
f0d66275 4073 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4074 goto out;
4075 r = -ENXIO;
4076 if (!kvm->arch.vpit)
4077 goto out;
f0d66275 4078 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4079 if (r)
4080 goto out;
4081 r = -EFAULT;
f0d66275 4082 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4083 goto out;
4084 r = 0;
4085 break;
4086 }
4087 case KVM_SET_PIT: {
e0f63cb9 4088 r = -EFAULT;
f0d66275 4089 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4090 goto out;
4091 r = -ENXIO;
4092 if (!kvm->arch.vpit)
4093 goto out;
f0d66275 4094 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4095 break;
4096 }
e9f42757
BK		 4097 case KVM_GET_PIT2: {
4098 r = -ENXIO;
4099 if (!kvm->arch.vpit)
4100 goto out;
4101 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4102 if (r)
4103 goto out;
4104 r = -EFAULT;
4105 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4106 goto out;
4107 r = 0;
4108 break;
4109 }
4110 case KVM_SET_PIT2: {
4111 r = -EFAULT;
4112 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4113 goto out;
4114 r = -ENXIO;
4115 if (!kvm->arch.vpit)
4116 goto out;
4117 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4118 break;
4119 }
52d939a0
MT		 4120 case KVM_REINJECT_CONTROL: {
4121 struct kvm_reinject_control control;
4122 r = -EFAULT;
4123 if (copy_from_user(&control, argp, sizeof(control)))
4124 goto out;
4125 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4126 break;
4127 }
ffde22ac
ES		 4128 case KVM_XEN_HVM_CONFIG: {
4129 r = -EFAULT;
4130 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4131 sizeof(struct kvm_xen_hvm_config)))
4132 goto out;
4133 r = -EINVAL;
4134 if (kvm->arch.xen_hvm_config.flags)
4135 goto out;
4136 r = 0;
4137 break;
4138 }
afbcf7ab 4139 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4140 struct kvm_clock_data user_ns;
4141 u64 now_ns;
4142 s64 delta;
4143
4144 r = -EFAULT;
4145 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4146 goto out;
4147
4148 r = -EINVAL;
4149 if (user_ns.flags)
4150 goto out;
4151
4152 r = 0;
395c6b0a 4153 local_irq_disable();
759379dd 4154 now_ns = get_kernel_ns();
afbcf7ab 4155 delta = user_ns.clock - now_ns;
395c6b0a 4156 local_irq_enable();
afbcf7ab 4157 kvm->arch.kvmclock_offset = delta;
2e762ff7 4158 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4159 break;
4160 }
4161 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4162 struct kvm_clock_data user_ns;
4163 u64 now_ns;
4164
395c6b0a 4165 local_irq_disable();
759379dd 4166 now_ns = get_kernel_ns();
afbcf7ab 4167 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4168 local_irq_enable();
afbcf7ab 4169 user_ns.flags = 0;
97e69aa6 4170 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4171
4172 r = -EFAULT;
4173 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4174 goto out;
4175 r = 0;
4176 break;
4177 }
90de4a18
NA		 4178 case KVM_ENABLE_CAP: {
4179 struct kvm_enable_cap cap;
afbcf7ab 4180
90de4a18
NA		 4181 r = -EFAULT;
4182 if (copy_from_user(&cap, argp, sizeof(cap)))
4183 goto out;
4184 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4185 break;
4186 }
1fe779f8 4187 default:
c274e03a 4188 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4189 }
4190out:
4191 return r;
4192}
4193
a16b043c 4194static void kvm_init_msr_list(void)
043405e1
CO		 4195{
4196 u32 dummy[2];
4197 unsigned i, j;
4198
e3267cbb
GC		 4199 /* skip the first msrs in the list. KVM-specific */
4200 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4201 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4202 continue;
93c4adc7
PB		 4203
4204 /*
4205 * Even MSRs that are valid in the host may not be exposed
4206 * to the guests in some cases. We could work around this
4207 * in VMX with the generic MSR save/load machinery, but it
4208 * is not really worthwhile since it will really only
4209 * happen with nested virtualization.
4210 */
4211 switch (msrs_to_save[i]) {
4212 case MSR_IA32_BNDCFGS:
4213 if (!kvm_x86_ops->mpx_supported())
4214 continue;
4215 break;
4216 default:
4217 break;
4218 }
4219
043405e1
CO		 4220 if (j < i)
4221 msrs_to_save[j] = msrs_to_save[i];
4222 j++;
4223 }
4224 num_msrs_to_save = j;
4225}
4226
bda9020e
MT		 4227static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4228 const void *v)
bbd9b64e 4229{
70252a10
AK		 4230 int handled = 0;
4231 int n;
4232
4233 do {
4234 n = min(len, 8);
4235 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4236 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4237 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4238 break;
4239 handled += n;
4240 addr += n;
4241 len -= n;
4242 v += n;
4243 } while (len);
bbd9b64e 4244
70252a10 4245 return handled;
bbd9b64e
CO		 4246}
4247
bda9020e 4248static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4249{
70252a10
AK		 4250 int handled = 0;
4251 int n;
4252
4253 do {
4254 n = min(len, 8);
4255 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4256 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4257 addr, n, v))
4258 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4259 break;
4260 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4261 handled += n;
4262 addr += n;
4263 len -= n;
4264 v += n;
4265 } while (len);
bbd9b64e 4266
70252a10 4267 return handled;
bbd9b64e
CO		 4268}
4269
2dafc6c2
GN		 4270static void kvm_set_segment(struct kvm_vcpu *vcpu,
4271 struct kvm_segment *var, int seg)
4272{
4273 kvm_x86_ops->set_segment(vcpu, var, seg);
4274}
4275
4276void kvm_get_segment(struct kvm_vcpu *vcpu,
4277 struct kvm_segment *var, int seg)
4278{
4279 kvm_x86_ops->get_segment(vcpu, var, seg);
4280}
4281
54987b7a
PB		 4282gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4283 struct x86_exception *exception)
02f59dc9
JR		 4284{
4285 gpa_t t_gpa;
02f59dc9
JR		 4286
4287 BUG_ON(!mmu_is_nested(vcpu));
4288
4289 /* NPT walks are always user-walks */
4290 access |= PFERR_USER_MASK;
54987b7a 4291 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4292
4293 return t_gpa;
4294}
4295
ab9ae313
AK		 4296gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4297 struct x86_exception *exception)
1871c602
GN		 4298{
4299 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4300 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4301}
4302
ab9ae313
AK		 4303 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4304 struct x86_exception *exception)
1871c602
GN		 4305{
4306 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4307 access |= PFERR_FETCH_MASK;
ab9ae313 4308 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4309}
4310
ab9ae313
AK		 4311gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4312 struct x86_exception *exception)
1871c602
GN		 4313{
4314 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4315 access |= PFERR_WRITE_MASK;
ab9ae313 4316 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4317}
4318
4319/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4320gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4321 struct x86_exception *exception)
1871c602 4322{
ab9ae313 4323 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4324}
4325
4326static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4327 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4328 struct x86_exception *exception)
bbd9b64e
CO		 4329{
4330 void *data = val;
10589a46 4331 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4332
4333 while (bytes) {
14dfe855 4334 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4335 exception);
bbd9b64e 4336 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4337 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4338 int ret;
4339
bcc55cba 4340 if (gpa == UNMAPPED_GVA)
ab9ae313 4341 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4342 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4343 offset, toread);
10589a46 4344 if (ret < 0) {
c3cd7ffa 4345 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4346 goto out;
4347 }
bbd9b64e 4348
77c2002e
IE		 4349 bytes -= toread;
4350 data += toread;
4351 addr += toread;
bbd9b64e 4352 }
10589a46 4353out:
10589a46 4354 return r;
bbd9b64e 4355}
77c2002e 4356
1871c602 4357/* used for instruction fetching */
0f65dd70
AK		 4358static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4359 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4360 struct x86_exception *exception)
1871c602 4361{
0f65dd70 4362 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4363 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4364 unsigned offset;
4365 int ret;
0f65dd70 4366
44583cba
PB		 4367 /* Inline kvm_read_guest_virt_helper for speed. */
4368 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4369 exception);
4370 if (unlikely(gpa == UNMAPPED_GVA))
4371 return X86EMUL_PROPAGATE_FAULT;
4372
4373 offset = addr & (PAGE_SIZE-1);
4374 if (WARN_ON(offset + bytes > PAGE_SIZE))
4375 bytes = (unsigned)PAGE_SIZE - offset;
4376 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4377 offset, bytes);
4378 if (unlikely(ret < 0))
4379 return X86EMUL_IO_NEEDED;
4380
4381 return X86EMUL_CONTINUE;
1871c602
GN		 4382}
4383
064aea77 4384int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4385 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4386 struct x86_exception *exception)
1871c602 4387{
0f65dd70 4388 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4389 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4390
1871c602 4391 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4392 exception);
1871c602 4393}
064aea77 4394EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4395
0f65dd70
AK		 4396static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4397 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4398 struct x86_exception *exception)
1871c602 4399{
0f65dd70 4400 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4401 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4402}
4403
6a4d7550 4404int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4405 gva_t addr, void *val,
2dafc6c2 4406 unsigned int bytes,
bcc55cba 4407 struct x86_exception *exception)
77c2002e 4408{
0f65dd70 4409 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4410 void *data = val;
4411 int r = X86EMUL_CONTINUE;
4412
4413 while (bytes) {
14dfe855
JR		 4414 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4415 PFERR_WRITE_MASK,
ab9ae313 4416 exception);
77c2002e
IE		 4417 unsigned offset = addr & (PAGE_SIZE-1);
4418 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4419 int ret;
4420
bcc55cba 4421 if (gpa == UNMAPPED_GVA)
ab9ae313 4422 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4423 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4424 if (ret < 0) {
c3cd7ffa 4425 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4426 goto out;
4427 }
4428
4429 bytes -= towrite;
4430 data += towrite;
4431 addr += towrite;
4432 }
4433out:
4434 return r;
4435}
6a4d7550 4436EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4437
af7cc7d1
XG		 4438static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4439 gpa_t *gpa, struct x86_exception *exception,
4440 bool write)
4441{
97d64b78
AK		 4442 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4443 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4444
97d64b78 4445 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4446 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4447 vcpu->arch.access, access)) {
bebb106a
XG		 4448 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4449 (gva & (PAGE_SIZE - 1));
4f022648 4450 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4451 return 1;
4452 }
4453
af7cc7d1
XG		 4454 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4455
4456 if (*gpa == UNMAPPED_GVA)
4457 return -1;
4458
4459 /* For APIC access vmexit */
4460 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4461 return 1;
4462
4f022648
XG		 4463 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4464 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4465 return 1;
4f022648 4466 }
bebb106a 4467
af7cc7d1
XG		 4468 return 0;
4469}
4470
3200f405 4471int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4472 const void *val, int bytes)
bbd9b64e
CO		 4473{
4474 int ret;
4475
4476 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4477 if (ret < 0)
bbd9b64e 4478 return 0;
f57f2ef5 4479 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4480 return 1;
4481}
4482
77d197b2
XG		 4483struct read_write_emulator_ops {
4484 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4485 int bytes);
4486 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4487 void *val, int bytes);
4488 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4489 int bytes, void *val);
4490 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4491 void *val, int bytes);
4492 bool write;
4493};
4494
4495static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4496{
4497 if (vcpu->mmio_read_completed) {
77d197b2 4498 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4499 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4500 vcpu->mmio_read_completed = 0;
4501 return 1;
4502 }
4503
4504 return 0;
4505}
4506
4507static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4508 void *val, int bytes)
4509{
4510 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4511}
4512
4513static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4514 void *val, int bytes)
4515{
4516 return emulator_write_phys(vcpu, gpa, val, bytes);
4517}
4518
4519static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4520{
4521 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4522 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4523}
4524
4525static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4526 void *val, int bytes)
4527{
4528 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4529 return X86EMUL_IO_NEEDED;
4530}
4531
4532static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4533 void *val, int bytes)
4534{
f78146b0
AK		 4535 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4536
87da7e66 4537 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4538 return X86EMUL_CONTINUE;
4539}
4540
0fbe9b0b 4541static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4542 .read_write_prepare = read_prepare,
4543 .read_write_emulate = read_emulate,
4544 .read_write_mmio = vcpu_mmio_read,
4545 .read_write_exit_mmio = read_exit_mmio,
4546};
4547
0fbe9b0b 4548static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4549 .read_write_emulate = write_emulate,
4550 .read_write_mmio = write_mmio,
4551 .read_write_exit_mmio = write_exit_mmio,
4552 .write = true,
4553};
4554
22388a3c
XG		 4555static int emulator_read_write_onepage(unsigned long addr, void *val,
4556 unsigned int bytes,
4557 struct x86_exception *exception,
4558 struct kvm_vcpu *vcpu,
0fbe9b0b 4559 const struct read_write_emulator_ops *ops)
bbd9b64e 4560{
af7cc7d1
XG		 4561 gpa_t gpa;
4562 int handled, ret;
22388a3c 4563 bool write = ops->write;
f78146b0 4564 struct kvm_mmio_fragment *frag;
10589a46 4565
22388a3c 4566 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4567
af7cc7d1 4568 if (ret < 0)
bbd9b64e 4569 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4570
4571 /* For APIC access vmexit */
af7cc7d1 4572 if (ret)
bbd9b64e
CO		 4573 goto mmio;
4574
22388a3c 4575 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4576 return X86EMUL_CONTINUE;
4577
4578mmio:
4579 /*
4580 * Is this MMIO handled locally?
4581 */
22388a3c 4582 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4583 if (handled == bytes)
bbd9b64e 4584 return X86EMUL_CONTINUE;
bbd9b64e 4585
70252a10
AK		 4586 gpa += handled;
4587 bytes -= handled;
4588 val += handled;
4589
87da7e66
XG		 4590 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4591 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4592 frag->gpa = gpa;
4593 frag->data = val;
4594 frag->len = bytes;
f78146b0 4595 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4596}
4597
52eb5a6d
XL		 4598static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4599 unsigned long addr,
22388a3c
XG		 4600 void *val, unsigned int bytes,
4601 struct x86_exception *exception,
0fbe9b0b 4602 const struct read_write_emulator_ops *ops)
bbd9b64e 4603{
0f65dd70 4604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4605 gpa_t gpa;
4606 int rc;
4607
4608 if (ops->read_write_prepare &&
4609 ops->read_write_prepare(vcpu, val, bytes))
4610 return X86EMUL_CONTINUE;
4611
4612 vcpu->mmio_nr_fragments = 0;
0f65dd70 4613
bbd9b64e
CO		 4614 /* Crossing a page boundary? */
4615 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4616 int now;
bbd9b64e
CO		 4617
4618 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4619 rc = emulator_read_write_onepage(addr, val, now, exception,
4620 vcpu, ops);
4621
bbd9b64e
CO		 4622 if (rc != X86EMUL_CONTINUE)
4623 return rc;
4624 addr += now;
bac15531
NA		 4625 if (ctxt->mode != X86EMUL_MODE_PROT64)
4626 addr = (u32)addr;
bbd9b64e
CO		 4627 val += now;
4628 bytes -= now;
4629 }
22388a3c 4630
f78146b0
AK		 4631 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4632 vcpu, ops);
4633 if (rc != X86EMUL_CONTINUE)
4634 return rc;
4635
4636 if (!vcpu->mmio_nr_fragments)
4637 return rc;
4638
4639 gpa = vcpu->mmio_fragments[0].gpa;
4640
4641 vcpu->mmio_needed = 1;
4642 vcpu->mmio_cur_fragment = 0;
4643
87da7e66 4644 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4645 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4646 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4647 vcpu->run->mmio.phys_addr = gpa;
4648
4649 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4650}
4651
4652static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4653 unsigned long addr,
4654 void *val,
4655 unsigned int bytes,
4656 struct x86_exception *exception)
4657{
4658 return emulator_read_write(ctxt, addr, val, bytes,
4659 exception, &read_emultor);
4660}
4661
52eb5a6d 4662static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4663 unsigned long addr,
4664 const void *val,
4665 unsigned int bytes,
4666 struct x86_exception *exception)
4667{
4668 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4669 exception, &write_emultor);
bbd9b64e 4670}
bbd9b64e 4671
daea3e73
AK		 4672#define CMPXCHG_TYPE(t, ptr, old, new) \
4673 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4674
4675#ifdef CONFIG_X86_64
4676# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4677#else
4678# define CMPXCHG64(ptr, old, new) \
9749a6c0 4679 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4680#endif
4681
0f65dd70
AK		 4682static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4683 unsigned long addr,
bbd9b64e
CO		 4684 const void *old,
4685 const void *new,
4686 unsigned int bytes,
0f65dd70 4687 struct x86_exception *exception)
bbd9b64e 4688{
0f65dd70 4689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4690 gpa_t gpa;
4691 struct page *page;
4692 char *kaddr;
4693 bool exchanged;
2bacc55c 4694
daea3e73
AK		 4695 /* guests cmpxchg8b have to be emulated atomically */
4696 if (bytes > 8 || (bytes & (bytes - 1)))
4697 goto emul_write;
10589a46 4698
daea3e73 4699 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4700
daea3e73
AK		 4701 if (gpa == UNMAPPED_GVA ||
4702 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4703 goto emul_write;
2bacc55c 4704
daea3e73
AK		 4705 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4706 goto emul_write;
72dc67a6 4707
daea3e73 4708 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4709 if (is_error_page(page))
c19b8bd6 4710 goto emul_write;
72dc67a6 4711
8fd75e12 4712 kaddr = kmap_atomic(page);
daea3e73
AK		 4713 kaddr += offset_in_page(gpa);
4714 switch (bytes) {
4715 case 1:
4716 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4717 break;
4718 case 2:
4719 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4720 break;
4721 case 4:
4722 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4723 break;
4724 case 8:
4725 exchanged = CMPXCHG64(kaddr, old, new);
4726 break;
4727 default:
4728 BUG();
2bacc55c 4729 }
8fd75e12 4730 kunmap_atomic(kaddr);
daea3e73
AK		 4731 kvm_release_page_dirty(page);
4732
4733 if (!exchanged)
4734 return X86EMUL_CMPXCHG_FAILED;
4735
d3714010 4736 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4737 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4738
4739 return X86EMUL_CONTINUE;
4a5f48f6 4740
3200f405 4741emul_write:
daea3e73 4742 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4743
0f65dd70 4744 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4745}
4746
cf8f70bf
GN		 4747static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4748{
4749 /* TODO: String I/O for in kernel device */
4750 int r;
4751
4752 if (vcpu->arch.pio.in)
e32edf4f 4753 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4754 vcpu->arch.pio.size, pd);
4755 else
e32edf4f 4756 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4757 vcpu->arch.pio.port, vcpu->arch.pio.size,
4758 pd);
4759 return r;
4760}
4761
6f6fbe98
XG		 4762static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4763 unsigned short port, void *val,
4764 unsigned int count, bool in)
cf8f70bf 4765{
cf8f70bf 4766 vcpu->arch.pio.port = port;
6f6fbe98 4767 vcpu->arch.pio.in = in;
7972995b 4768 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4769 vcpu->arch.pio.size = size;
4770
4771 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4772 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4773 return 1;
4774 }
4775
4776 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4777 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4778 vcpu->run->io.size = size;
4779 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4780 vcpu->run->io.count = count;
4781 vcpu->run->io.port = port;
4782
4783 return 0;
4784}
4785
6f6fbe98
XG		 4786static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4787 int size, unsigned short port, void *val,
4788 unsigned int count)
cf8f70bf 4789{
ca1d4a9e 4790 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4791 int ret;
ca1d4a9e 4792
6f6fbe98
XG		 4793 if (vcpu->arch.pio.count)
4794 goto data_avail;
cf8f70bf 4795
6f6fbe98
XG		 4796 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4797 if (ret) {
4798data_avail:
4799 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4800 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4801 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4802 return 1;
4803 }
4804
cf8f70bf
GN		 4805 return 0;
4806}
4807
6f6fbe98
XG		 4808static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4809 int size, unsigned short port,
4810 const void *val, unsigned int count)
4811{
4812 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4813
4814 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4815 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4816 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4817}
4818
bbd9b64e
CO		 4819static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4820{
4821 return kvm_x86_ops->get_segment_base(vcpu, seg);
4822}
4823
3cb16fe7 4824static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4825{
3cb16fe7 4826 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4827}
4828
5cb56059 4829int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4830{
4831 if (!need_emulate_wbinvd(vcpu))
4832 return X86EMUL_CONTINUE;
4833
4834 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4835 int cpu = get_cpu();
4836
4837 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4838 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4839 wbinvd_ipi, NULL, 1);
2eec7343 4840 put_cpu();
f5f48ee1 4841 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4842 } else
4843 wbinvd();
f5f48ee1
SY		 4844 return X86EMUL_CONTINUE;
4845}
5cb56059
JS		 4846
4847int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4848{
4849 kvm_x86_ops->skip_emulated_instruction(vcpu);
4850 return kvm_emulate_wbinvd_noskip(vcpu);
4851}
f5f48ee1
SY		 4852EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4853
5cb56059
JS		 4854
4855
bcaf5cc5
AK		 4856static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4857{
5cb56059 4858 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4859}
4860
52eb5a6d
XL		 4861static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4862 unsigned long *dest)
bbd9b64e 4863{
16f8a6f9 4864 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4865}
4866
52eb5a6d
XL		 4867static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4868 unsigned long value)
bbd9b64e 4869{
338dbc97 4870
717746e3 4871 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4872}
4873
52a46617 4874static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4875{
52a46617 4876 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4877}
4878
717746e3 4879static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4880{
717746e3 4881 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4882 unsigned long value;
4883
4884 switch (cr) {
4885 case 0:
4886 value = kvm_read_cr0(vcpu);
4887 break;
4888 case 2:
4889 value = vcpu->arch.cr2;
4890 break;
4891 case 3:
9f8fe504 4892 value = kvm_read_cr3(vcpu);
52a46617
GN		 4893 break;
4894 case 4:
4895 value = kvm_read_cr4(vcpu);
4896 break;
4897 case 8:
4898 value = kvm_get_cr8(vcpu);
4899 break;
4900 default:
a737f256 4901 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4902 return 0;
4903 }
4904
4905 return value;
4906}
4907
717746e3 4908static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4909{
717746e3 4910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4911 int res = 0;
4912
52a46617
GN		 4913 switch (cr) {
4914 case 0:
49a9b07e 4915 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4916 break;
4917 case 2:
4918 vcpu->arch.cr2 = val;
4919 break;
4920 case 3:
2390218b 4921 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4922 break;
4923 case 4:
a83b29c6 4924 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4925 break;
4926 case 8:
eea1cff9 4927 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4928 break;
4929 default:
a737f256 4930 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4931 res = -1;
52a46617 4932 }
0f12244f
GN		 4933
4934 return res;
52a46617
GN		 4935}
4936
717746e3 4937static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4938{
717746e3 4939 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4940}
4941
4bff1e86 4942static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4943{
4bff1e86 4944 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4945}
4946
4bff1e86 4947static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4948{
4bff1e86 4949 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4950}
4951
1ac9d0cf
AK		 4952static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4953{
4954 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4955}
4956
4957static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4958{
4959 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4960}
4961
4bff1e86
AK		 4962static unsigned long emulator_get_cached_segment_base(
4963 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4964{
4bff1e86 4965 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4966}
4967
1aa36616
AK		 4968static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4969 struct desc_struct *desc, u32 *base3,
4970 int seg)
2dafc6c2
GN		 4971{
4972 struct kvm_segment var;
4973
4bff1e86 4974 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4975 *selector = var.selector;
2dafc6c2 4976
378a8b09
GN		 4977 if (var.unusable) {
4978 memset(desc, 0, sizeof(*desc));
2dafc6c2 4979 return false;
378a8b09 4980 }
2dafc6c2
GN		 4981
4982 if (var.g)
4983 var.limit >>= 12;
4984 set_desc_limit(desc, var.limit);
4985 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4986#ifdef CONFIG_X86_64
4987 if (base3)
4988 *base3 = var.base >> 32;
4989#endif
2dafc6c2
GN		 4990 desc->type = var.type;
4991 desc->s = var.s;
4992 desc->dpl = var.dpl;
4993 desc->p = var.present;
4994 desc->avl = var.avl;
4995 desc->l = var.l;
4996 desc->d = var.db;
4997 desc->g = var.g;
4998
4999 return true;
5000}
5001
1aa36616
AK		 5002static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5003 struct desc_struct *desc, u32 base3,
5004 int seg)
2dafc6c2 5005{
4bff1e86 5006 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5007 struct kvm_segment var;
5008
1aa36616 5009 var.selector = selector;
2dafc6c2 5010 var.base = get_desc_base(desc);
5601d05b
GN		 5011#ifdef CONFIG_X86_64
5012 var.base |= ((u64)base3) << 32;
5013#endif
2dafc6c2
GN		 5014 var.limit = get_desc_limit(desc);
5015 if (desc->g)
5016 var.limit = (var.limit << 12) | 0xfff;
5017 var.type = desc->type;
2dafc6c2
GN		 5018 var.dpl = desc->dpl;
5019 var.db = desc->d;
5020 var.s = desc->s;
5021 var.l = desc->l;
5022 var.g = desc->g;
5023 var.avl = desc->avl;
5024 var.present = desc->p;
5025 var.unusable = !var.present;
5026 var.padding = 0;
5027
5028 kvm_set_segment(vcpu, &var, seg);
5029 return;
5030}
5031
717746e3
AK		 5032static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5033 u32 msr_index, u64 *pdata)
5034{
5035 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
5036}
5037
5038static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5039 u32 msr_index, u64 data)
5040{
8fe8ab46
WA		 5041 struct msr_data msr;
5042
5043 msr.data = data;
5044 msr.index = msr_index;
5045 msr.host_initiated = false;
5046 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5047}
5048
67f4d428
NA		 5049static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5050 u32 pmc)
5051{
5052 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
5053}
5054
222d21aa
AK		 5055static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5056 u32 pmc, u64 *pdata)
5057{
5058 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
5059}
5060
6c3287f7
AK		 5061static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5062{
5063 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5064}
5065
5037f6f3
AK		 5066static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5067{
5068 preempt_disable();
5197b808 5069 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5070 /*
5071 * CR0.TS may reference the host fpu state, not the guest fpu state,
5072 * so it may be clear at this point.
5073 */
5074 clts();
5075}
5076
5077static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5078{
5079 preempt_enable();
5080}
5081
2953538e 5082static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5083 struct x86_instruction_info *info,
c4f035c6
AK		 5084 enum x86_intercept_stage stage)
5085{
2953538e 5086 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5087}
5088
0017f93a 5089static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5090 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5091{
0017f93a 5092 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5093}
5094
dd856efa
AK		 5095static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5096{
5097 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5098}
5099
5100static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5101{
5102 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5103}
5104
801806d9
NA		 5105static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5106{
5107 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5108}
5109
0225fb50 5110static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5111 .read_gpr = emulator_read_gpr,
5112 .write_gpr = emulator_write_gpr,
1871c602 5113 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5114 .write_std = kvm_write_guest_virt_system,
1871c602 5115 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5116 .read_emulated = emulator_read_emulated,
5117 .write_emulated = emulator_write_emulated,
5118 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5119 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5120 .pio_in_emulated = emulator_pio_in_emulated,
5121 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5122 .get_segment = emulator_get_segment,
5123 .set_segment = emulator_set_segment,
5951c442 5124 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5125 .get_gdt = emulator_get_gdt,
160ce1f1 5126 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5127 .set_gdt = emulator_set_gdt,
5128 .set_idt = emulator_set_idt,
52a46617
GN		 5129 .get_cr = emulator_get_cr,
5130 .set_cr = emulator_set_cr,
9c537244 5131 .cpl = emulator_get_cpl,
35aa5375
GN		 5132 .get_dr = emulator_get_dr,
5133 .set_dr = emulator_set_dr,
717746e3
AK		 5134 .set_msr = emulator_set_msr,
5135 .get_msr = emulator_get_msr,
67f4d428 5136 .check_pmc = emulator_check_pmc,
222d21aa 5137 .read_pmc = emulator_read_pmc,
6c3287f7 5138 .halt = emulator_halt,
bcaf5cc5 5139 .wbinvd = emulator_wbinvd,
d6aa1000 5140 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5141 .get_fpu = emulator_get_fpu,
5142 .put_fpu = emulator_put_fpu,
c4f035c6 5143 .intercept = emulator_intercept,
bdb42f5a 5144 .get_cpuid = emulator_get_cpuid,
801806d9 5145 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5146};
5147
95cb2295
GN		 5148static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5149{
37ccdcbe 5150 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5151 /*
5152 * an sti; sti; sequence only disable interrupts for the first
5153 * instruction. So, if the last instruction, be it emulated or
5154 * not, left the system with the INT_STI flag enabled, it
5155 * means that the last instruction is an sti. We should not
5156 * leave the flag on in this case. The same goes for mov ss
5157 */
37ccdcbe
PB		 5158 if (int_shadow & mask)
5159 mask = 0;
6addfc42 5160 if (unlikely(int_shadow || mask)) {
95cb2295 5161 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5162 if (!mask)
5163 kvm_make_request(KVM_REQ_EVENT, vcpu);
5164 }
95cb2295
GN		 5165}
5166
ef54bcfe 5167static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5168{
5169 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5170 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5171 return kvm_propagate_fault(vcpu, &ctxt->exception);
5172
5173 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5174 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5175 ctxt->exception.error_code);
54b8486f 5176 else
da9cb575 5177 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5178 return false;
54b8486f
GN		 5179}
5180
8ec4722d
MG		 5181static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5182{
adf52235 5183 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5184 int cs_db, cs_l;
5185
8ec4722d
MG		 5186 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5187
adf52235
TY		 5188 ctxt->eflags = kvm_get_rflags(vcpu);
5189 ctxt->eip = kvm_rip_read(vcpu);
5190 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5191 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5192 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5193 cs_db ? X86EMUL_MODE_PROT32 :
5194 X86EMUL_MODE_PROT16;
5195 ctxt->guest_mode = is_guest_mode(vcpu);
5196
dd856efa 5197 init_decode_cache(ctxt);
7ae441ea 5198 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5199}
5200
71f9833b 5201int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5202{
9d74191a 5203 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5204 int ret;
5205
5206 init_emulate_ctxt(vcpu);
5207
9dac77fa
AK		 5208 ctxt->op_bytes = 2;
5209 ctxt->ad_bytes = 2;
5210 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5211 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5212
5213 if (ret != X86EMUL_CONTINUE)
5214 return EMULATE_FAIL;
5215
9dac77fa 5216 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5217 kvm_rip_write(vcpu, ctxt->eip);
5218 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5219
5220 if (irq == NMI_VECTOR)
7460fb4a 5221 vcpu->arch.nmi_pending = 0;
63995653
MG		 5222 else
5223 vcpu->arch.interrupt.pending = false;
5224
5225 return EMULATE_DONE;
5226}
5227EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5228
6d77dbfc
GN		 5229static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5230{
fc3a9157
JR		 5231 int r = EMULATE_DONE;
5232
6d77dbfc
GN		 5233 ++vcpu->stat.insn_emulation_fail;
5234 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5235 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5236 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5237 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5238 vcpu->run->internal.ndata = 0;
5239 r = EMULATE_FAIL;
5240 }
6d77dbfc 5241 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5242
5243 return r;
6d77dbfc
GN		 5244}
5245
93c05d3e 5246static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5247 bool write_fault_to_shadow_pgtable,
5248 int emulation_type)
a6f177ef 5249{
95b3cf69 5250 gpa_t gpa = cr2;
8e3d9d06 5251 pfn_t pfn;
a6f177ef 5252
991eebf9
GN		 5253 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5254 return false;
5255
95b3cf69
XG		 5256 if (!vcpu->arch.mmu.direct_map) {
5257 /*
5258 * Write permission should be allowed since only
5259 * write access need to be emulated.
5260 */
5261 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5262
95b3cf69
XG		 5263 /*
5264 * If the mapping is invalid in guest, let cpu retry
5265 * it to generate fault.
5266 */
5267 if (gpa == UNMAPPED_GVA)
5268 return true;
5269 }
a6f177ef 5270
8e3d9d06
XG		 5271 /*
5272 * Do not retry the unhandleable instruction if it faults on the
5273 * readonly host memory, otherwise it will goto a infinite loop:
5274 * retry instruction -> write #PF -> emulation fail -> retry
5275 * instruction -> ...
5276 */
5277 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5278
5279 /*
5280 * If the instruction failed on the error pfn, it can not be fixed,
5281 * report the error to userspace.
5282 */
5283 if (is_error_noslot_pfn(pfn))
5284 return false;
5285
5286 kvm_release_pfn_clean(pfn);
5287
5288 /* The instructions are well-emulated on direct mmu. */
5289 if (vcpu->arch.mmu.direct_map) {
5290 unsigned int indirect_shadow_pages;
5291
5292 spin_lock(&vcpu->kvm->mmu_lock);
5293 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5294 spin_unlock(&vcpu->kvm->mmu_lock);
5295
5296 if (indirect_shadow_pages)
5297 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5298
a6f177ef 5299 return true;
8e3d9d06 5300 }
a6f177ef 5301
95b3cf69
XG		 5302 /*
5303 * if emulation was due to access to shadowed page table
5304 * and it failed try to unshadow page and re-enter the
5305 * guest to let CPU execute the instruction.
5306 */
5307 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5308
5309 /*
5310 * If the access faults on its page table, it can not
5311 * be fixed by unprotecting shadow page and it should
5312 * be reported to userspace.
5313 */
5314 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5315}
5316
1cb3f3ae
XG		 5317static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5318 unsigned long cr2, int emulation_type)
5319{
5320 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5321 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5322
5323 last_retry_eip = vcpu->arch.last_retry_eip;
5324 last_retry_addr = vcpu->arch.last_retry_addr;
5325
5326 /*
5327 * If the emulation is caused by #PF and it is non-page_table
5328 * writing instruction, it means the VM-EXIT is caused by shadow
5329 * page protected, we can zap the shadow page and retry this
5330 * instruction directly.
5331 *
5332 * Note: if the guest uses a non-page-table modifying instruction
5333 * on the PDE that points to the instruction, then we will unmap
5334 * the instruction and go to an infinite loop. So, we cache the
5335 * last retried eip and the last fault address, if we meet the eip
5336 * and the address again, we can break out of the potential infinite
5337 * loop.
5338 */
5339 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5340
5341 if (!(emulation_type & EMULTYPE_RETRY))
5342 return false;
5343
5344 if (x86_page_table_writing_insn(ctxt))
5345 return false;
5346
5347 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5348 return false;
5349
5350 vcpu->arch.last_retry_eip = ctxt->eip;
5351 vcpu->arch.last_retry_addr = cr2;
5352
5353 if (!vcpu->arch.mmu.direct_map)
5354 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5355
22368028 5356 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5357
5358 return true;
5359}
5360
716d51ab
GN		 5361static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5362static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5363
4a1e10d5
PB		 5364static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5365 unsigned long *db)
5366{
5367 u32 dr6 = 0;
5368 int i;
5369 u32 enable, rwlen;
5370
5371 enable = dr7;
5372 rwlen = dr7 >> 16;
5373 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5374 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5375 dr6 |= (1 << i);
5376 return dr6;
5377}
5378
6addfc42 5379static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5380{
5381 struct kvm_run *kvm_run = vcpu->run;
5382
5383 /*
6addfc42
PB		 5384 * rflags is the old, "raw" value of the flags. The new value has
5385 * not been saved yet.
663f4c61
PB		 5386 *
5387 * This is correct even for TF set by the guest, because "the
5388 * processor will not generate this exception after the instruction
5389 * that sets the TF flag".
5390 */
663f4c61
PB		 5391 if (unlikely(rflags & X86_EFLAGS_TF)) {
5392 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5393 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5394 DR6_RTM;
663f4c61
PB		 5395 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5396 kvm_run->debug.arch.exception = DB_VECTOR;
5397 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5398 *r = EMULATE_USER_EXIT;
5399 } else {
5400 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5401 /*
5402 * "Certain debug exceptions may clear bit 0-3. The
5403 * remaining contents of the DR6 register are never
5404 * cleared by the processor".
5405 */
5406 vcpu->arch.dr6 &= ~15;
6f43ed01 5407 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5408 kvm_queue_exception(vcpu, DB_VECTOR);
5409 }
5410 }
5411}
5412
4a1e10d5
PB		 5413static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5414{
4a1e10d5
PB		 5415 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5416 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5417 struct kvm_run *kvm_run = vcpu->run;
5418 unsigned long eip = kvm_get_linear_rip(vcpu);
5419 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5420 vcpu->arch.guest_debug_dr7,
5421 vcpu->arch.eff_db);
5422
5423 if (dr6 != 0) {
6f43ed01 5424 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5425 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5426 kvm_run->debug.arch.exception = DB_VECTOR;
5427 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5428 *r = EMULATE_USER_EXIT;
5429 return true;
5430 }
5431 }
5432
4161a569
NA		 5433 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5434 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5435 unsigned long eip = kvm_get_linear_rip(vcpu);
5436 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5437 vcpu->arch.dr7,
5438 vcpu->arch.db);
5439
5440 if (dr6 != 0) {
5441 vcpu->arch.dr6 &= ~15;
6f43ed01 5442 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5443 kvm_queue_exception(vcpu, DB_VECTOR);
5444 *r = EMULATE_DONE;
5445 return true;
5446 }
5447 }
5448
5449 return false;
5450}
5451
51d8b661
AP		 5452int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5453 unsigned long cr2,
dc25e89e
AP		 5454 int emulation_type,
5455 void *insn,
5456 int insn_len)
bbd9b64e 5457{
95cb2295 5458 int r;
9d74191a 5459 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5460 bool writeback = true;
93c05d3e 5461 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5462
93c05d3e
XG		 5463 /*
5464 * Clear write_fault_to_shadow_pgtable here to ensure it is
5465 * never reused.
5466 */
5467 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5468 kvm_clear_exception_queue(vcpu);
8d7d8102 5469
571008da 5470 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5471 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5472
5473 /*
5474 * We will reenter on the same instruction since
5475 * we do not set complete_userspace_io. This does not
5476 * handle watchpoints yet, those would be handled in
5477 * the emulate_ops.
5478 */
5479 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5480 return r;
5481
9d74191a
TY		 5482 ctxt->interruptibility = 0;
5483 ctxt->have_exception = false;
e0ad0b47 5484 ctxt->exception.vector = -1;
9d74191a 5485 ctxt->perm_ok = false;
bbd9b64e 5486
b51e974f 5487 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5488
9d74191a 5489 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5490
e46479f8 5491 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5492 ++vcpu->stat.insn_emulation;
1d2887e2 5493 if (r != EMULATION_OK) {
4005996e
AK		 5494 if (emulation_type & EMULTYPE_TRAP_UD)
5495 return EMULATE_FAIL;
991eebf9
GN		 5496 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5497 emulation_type))
bbd9b64e 5498 return EMULATE_DONE;
6d77dbfc
GN		 5499 if (emulation_type & EMULTYPE_SKIP)
5500 return EMULATE_FAIL;
5501 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5502 }
5503 }
5504
ba8afb6b 5505 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5506 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5507 if (ctxt->eflags & X86_EFLAGS_RF)
5508 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5509 return EMULATE_DONE;
5510 }
5511
1cb3f3ae
XG		 5512 if (retry_instruction(ctxt, cr2, emulation_type))
5513 return EMULATE_DONE;
5514
7ae441ea 5515 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5516 changes registers values during IO operation */
7ae441ea
GN		 5517 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5518 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5519 emulator_invalidate_register_cache(ctxt);
7ae441ea 5520 }
4d2179e1 5521
5cd21917 5522restart:
9d74191a 5523 r = x86_emulate_insn(ctxt);
bbd9b64e 5524
775fde86
JR		 5525 if (r == EMULATION_INTERCEPTED)
5526 return EMULATE_DONE;
5527
d2ddd1c4 5528 if (r == EMULATION_FAILED) {
991eebf9
GN		 5529 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5530 emulation_type))
c3cd7ffa
GN		 5531 return EMULATE_DONE;
5532
6d77dbfc 5533 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5534 }
5535
9d74191a 5536 if (ctxt->have_exception) {
d2ddd1c4 5537 r = EMULATE_DONE;
ef54bcfe
PB		 5538 if (inject_emulated_exception(vcpu))
5539 return r;
d2ddd1c4 5540 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5541 if (!vcpu->arch.pio.in) {
5542 /* FIXME: return into emulator if single-stepping. */
3457e419 5543 vcpu->arch.pio.count = 0;
0912c977 5544 } else {
7ae441ea 5545 writeback = false;
716d51ab
GN		 5546 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5547 }
ac0a48c3 5548 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5549 } else if (vcpu->mmio_needed) {
5550 if (!vcpu->mmio_is_write)
5551 writeback = false;
ac0a48c3 5552 r = EMULATE_USER_EXIT;
716d51ab 5553 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5554 } else if (r == EMULATION_RESTART)
5cd21917 5555 goto restart;
d2ddd1c4
GN		 5556 else
5557 r = EMULATE_DONE;
f850e2e6 5558
7ae441ea 5559 if (writeback) {
6addfc42 5560 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5561 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5562 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5563 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5564 if (r == EMULATE_DONE)
6addfc42 5565 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5566 if (!ctxt->have_exception ||
5567 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5568 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5569
5570 /*
5571 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5572 * do nothing, and it will be requested again as soon as
5573 * the shadow expires. But we still need to check here,
5574 * because POPF has no interrupt shadow.
5575 */
5576 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5577 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5578 } else
5579 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5580
5581 return r;
de7d789a 5582}
51d8b661 5583EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5584
cf8f70bf 5585int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5586{
cf8f70bf 5587 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5588 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5589 size, port, &val, 1);
cf8f70bf 5590 /* do not return to emulator after return from userspace */
7972995b 5591 vcpu->arch.pio.count = 0;
de7d789a
CO		 5592 return ret;
5593}
cf8f70bf 5594EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5595
8cfdc000
ZA		 5596static void tsc_bad(void *info)
5597{
0a3aee0d 5598 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5599}
5600
5601static void tsc_khz_changed(void *data)
c8076604 5602{
8cfdc000
ZA		 5603 struct cpufreq_freqs *freq = data;
5604 unsigned long khz = 0;
5605
5606 if (data)
5607 khz = freq->new;
5608 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5609 khz = cpufreq_quick_get(raw_smp_processor_id());
5610 if (!khz)
5611 khz = tsc_khz;
0a3aee0d 5612 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5613}
5614
c8076604
GH		 5615static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5616 void *data)
5617{
5618 struct cpufreq_freqs *freq = data;
5619 struct kvm *kvm;
5620 struct kvm_vcpu *vcpu;
5621 int i, send_ipi = 0;
5622
8cfdc000
ZA		 5623 /*
5624 * We allow guests to temporarily run on slowing clocks,
5625 * provided we notify them after, or to run on accelerating
5626 * clocks, provided we notify them before. Thus time never
5627 * goes backwards.
5628 *
5629 * However, we have a problem. We can't atomically update
5630 * the frequency of a given CPU from this function; it is
5631 * merely a notifier, which can be called from any CPU.
5632 * Changing the TSC frequency at arbitrary points in time
5633 * requires a recomputation of local variables related to
5634 * the TSC for each VCPU. We must flag these local variables
5635 * to be updated and be sure the update takes place with the
5636 * new frequency before any guests proceed.
5637 *
5638 * Unfortunately, the combination of hotplug CPU and frequency
5639 * change creates an intractable locking scenario; the order
5640 * of when these callouts happen is undefined with respect to
5641 * CPU hotplug, and they can race with each other. As such,
5642 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5643 * undefined; you can actually have a CPU frequency change take
5644 * place in between the computation of X and the setting of the
5645 * variable. To protect against this problem, all updates of
5646 * the per_cpu tsc_khz variable are done in an interrupt
5647 * protected IPI, and all callers wishing to update the value
5648 * must wait for a synchronous IPI to complete (which is trivial
5649 * if the caller is on the CPU already). This establishes the
5650 * necessary total order on variable updates.
5651 *
5652 * Note that because a guest time update may take place
5653 * anytime after the setting of the VCPU's request bit, the
5654 * correct TSC value must be set before the request. However,
5655 * to ensure the update actually makes it to any guest which
5656 * starts running in hardware virtualization between the set
5657 * and the acquisition of the spinlock, we must also ping the
5658 * CPU after setting the request bit.
5659 *
5660 */
5661
c8076604
GH		 5662 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5663 return 0;
5664 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5665 return 0;
8cfdc000
ZA		 5666
5667 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5668
2f303b74 5669 spin_lock(&kvm_lock);
c8076604 5670 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5671 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5672 if (vcpu->cpu != freq->cpu)
5673 continue;
c285545f 5674 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5675 if (vcpu->cpu != smp_processor_id())
8cfdc000 5676 send_ipi = 1;
c8076604
GH		 5677 }
5678 }
2f303b74 5679 spin_unlock(&kvm_lock);
c8076604
GH		 5680
5681 if (freq->old < freq->new && send_ipi) {
5682 /*
5683 * We upscale the frequency. Must make the guest
5684 * doesn't see old kvmclock values while running with
5685 * the new frequency, otherwise we risk the guest sees
5686 * time go backwards.
5687 *
5688 * In case we update the frequency for another cpu
5689 * (which might be in guest context) send an interrupt
5690 * to kick the cpu out of guest context. Next time
5691 * guest context is entered kvmclock will be updated,
5692 * so the guest will not see stale values.
5693 */
8cfdc000 5694 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5695 }
5696 return 0;
5697}
5698
5699static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5700 .notifier_call = kvmclock_cpufreq_notifier
5701};
5702
5703static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5704 unsigned long action, void *hcpu)
5705{
5706 unsigned int cpu = (unsigned long)hcpu;
5707
5708 switch (action) {
5709 case CPU_ONLINE:
5710 case CPU_DOWN_FAILED:
5711 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5712 break;
5713 case CPU_DOWN_PREPARE:
5714 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5715 break;
5716 }
5717 return NOTIFY_OK;
5718}
5719
5720static struct notifier_block kvmclock_cpu_notifier_block = {
5721 .notifier_call = kvmclock_cpu_notifier,
5722 .priority = -INT_MAX
c8076604
GH		 5723};
5724
b820cc0c
ZA		 5725static void kvm_timer_init(void)
5726{
5727 int cpu;
5728
c285545f 5729 max_tsc_khz = tsc_khz;
460dd42e
SB		 5730
5731 cpu_notifier_register_begin();
b820cc0c 5732 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5733#ifdef CONFIG_CPU_FREQ
5734 struct cpufreq_policy policy;
5735 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5736 cpu = get_cpu();
5737 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5738 if (policy.cpuinfo.max_freq)
5739 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5740 put_cpu();
c285545f 5741#endif
b820cc0c
ZA		 5742 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5743 CPUFREQ_TRANSITION_NOTIFIER);
5744 }
c285545f 5745 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5746 for_each_online_cpu(cpu)
5747 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5748
5749 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5750 cpu_notifier_register_done();
5751
b820cc0c
ZA		 5752}
5753
ff9d07a0
ZY		 5754static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5755
f5132b01 5756int kvm_is_in_guest(void)
ff9d07a0 5757{
086c9855 5758 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5759}
5760
5761static int kvm_is_user_mode(void)
5762{
5763 int user_mode = 3;
dcf46b94 5764
086c9855
AS		 5765 if (__this_cpu_read(current_vcpu))
5766 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5767
ff9d07a0
ZY		 5768 return user_mode != 0;
5769}
5770
5771static unsigned long kvm_get_guest_ip(void)
5772{
5773 unsigned long ip = 0;
dcf46b94 5774
086c9855
AS		 5775 if (__this_cpu_read(current_vcpu))
5776 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5777
ff9d07a0
ZY		 5778 return ip;
5779}
5780
5781static struct perf_guest_info_callbacks kvm_guest_cbs = {
5782 .is_in_guest = kvm_is_in_guest,
5783 .is_user_mode = kvm_is_user_mode,
5784 .get_guest_ip = kvm_get_guest_ip,
5785};
5786
5787void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5788{
086c9855 5789 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5790}
5791EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5792
5793void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5794{
086c9855 5795 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5796}
5797EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5798
ce88decf
XG		 5799static void kvm_set_mmio_spte_mask(void)
5800{
5801 u64 mask;
5802 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5803
5804 /*
5805 * Set the reserved bits and the present bit of an paging-structure
5806 * entry to generate page fault with PFER.RSV = 1.
5807 */
885032b9 5808 /* Mask the reserved physical address bits. */
d1431483 5809 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5810
5811 /* Bit 62 is always reserved for 32bit host. */
5812 mask |= 0x3ull << 62;
5813
5814 /* Set the present bit. */
ce88decf
XG		 5815 mask |= 1ull;
5816
5817#ifdef CONFIG_X86_64
5818 /*
5819 * If reserved bit is not supported, clear the present bit to disable
5820 * mmio page fault.
5821 */
5822 if (maxphyaddr == 52)
5823 mask &= ~1ull;
5824#endif
5825
5826 kvm_mmu_set_mmio_spte_mask(mask);
5827}
5828
16e8d74d
MT		 5829#ifdef CONFIG_X86_64
5830static void pvclock_gtod_update_fn(struct work_struct *work)
5831{
d828199e
MT		 5832 struct kvm *kvm;
5833
5834 struct kvm_vcpu *vcpu;
5835 int i;
5836
2f303b74 5837 spin_lock(&kvm_lock);
d828199e
MT		 5838 list_for_each_entry(kvm, &vm_list, vm_list)
5839 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5840 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5841 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5842 spin_unlock(&kvm_lock);
16e8d74d
MT		 5843}
5844
5845static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5846
5847/*
5848 * Notification about pvclock gtod data update.
5849 */
5850static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5851 void *priv)
5852{
5853 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5854 struct timekeeper *tk = priv;
5855
5856 update_pvclock_gtod(tk);
5857
5858 /* disable master clock if host does not trust, or does not
5859 * use, TSC clocksource
5860 */
5861 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5862 atomic_read(&kvm_guest_has_master_clock) != 0)
5863 queue_work(system_long_wq, &pvclock_gtod_work);
5864
5865 return 0;
5866}
5867
5868static struct notifier_block pvclock_gtod_notifier = {
5869 .notifier_call = pvclock_gtod_notify,
5870};
5871#endif
5872
f8c16bba 5873int kvm_arch_init(void *opaque)
043405e1 5874{
b820cc0c 5875 int r;
6b61edf7 5876 struct kvm_x86_ops *ops = opaque;
f8c16bba 5877
f8c16bba
ZX		 5878 if (kvm_x86_ops) {
5879 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5880 r = -EEXIST;
5881 goto out;
f8c16bba
ZX		 5882 }
5883
5884 if (!ops->cpu_has_kvm_support()) {
5885 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5886 r = -EOPNOTSUPP;
5887 goto out;
f8c16bba
ZX		 5888 }
5889 if (ops->disabled_by_bios()) {
5890 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5891 r = -EOPNOTSUPP;
5892 goto out;
f8c16bba
ZX		 5893 }
5894
013f6a5d
MT		 5895 r = -ENOMEM;
5896 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5897 if (!shared_msrs) {
5898 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5899 goto out;
5900 }
5901
97db56ce
AK		 5902 r = kvm_mmu_module_init();
5903 if (r)
013f6a5d 5904 goto out_free_percpu;
97db56ce 5905
ce88decf 5906 kvm_set_mmio_spte_mask();
97db56ce 5907
f8c16bba 5908 kvm_x86_ops = ops;
920c8377 5909
7b52345e 5910 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5911 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5912
b820cc0c 5913 kvm_timer_init();
c8076604 5914
ff9d07a0
ZY		 5915 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5916
2acf923e
DC		 5917 if (cpu_has_xsave)
5918 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5919
c5cc421b 5920 kvm_lapic_init();
16e8d74d
MT		 5921#ifdef CONFIG_X86_64
5922 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5923#endif
5924
f8c16bba 5925 return 0;
56c6d28a 5926
013f6a5d
MT		 5927out_free_percpu:
5928 free_percpu(shared_msrs);
56c6d28a 5929out:
56c6d28a 5930 return r;
043405e1 5931}
8776e519 5932
f8c16bba
ZX		 5933void kvm_arch_exit(void)
5934{
ff9d07a0
ZY		 5935 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5936
888d256e
JK		 5937 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5938 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5939 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5940 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5941#ifdef CONFIG_X86_64
5942 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5943#endif
f8c16bba 5944 kvm_x86_ops = NULL;
56c6d28a 5945 kvm_mmu_module_exit();
013f6a5d 5946 free_percpu(shared_msrs);
56c6d28a 5947}
f8c16bba 5948
5cb56059 5949int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5950{
5951 ++vcpu->stat.halt_exits;
5952 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5953 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5954 return 1;
5955 } else {
5956 vcpu->run->exit_reason = KVM_EXIT_HLT;
5957 return 0;
5958 }
5959}
5cb56059
JS		 5960EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5961
5962int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5963{
5964 kvm_x86_ops->skip_emulated_instruction(vcpu);
5965 return kvm_vcpu_halt(vcpu);
5966}
8776e519
HB		 5967EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5968
55cd8e5a
GN		 5969int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5970{
5971 u64 param, ingpa, outgpa, ret;
5972 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5973 bool fast, longmode;
55cd8e5a
GN		 5974
5975 /*
5976 * hypercall generates UD from non zero cpl and real mode
5977 * per HYPER-V spec
5978 */
3eeb3288 5979 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5980 kvm_queue_exception(vcpu, UD_VECTOR);
5981 return 0;
5982 }
5983
a449c7aa 5984 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5985
5986 if (!longmode) {
ccd46936
GN		 5987 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5988 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5989 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5990 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5991 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5992 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5993 }
5994#ifdef CONFIG_X86_64
5995 else {
5996 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5997 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5998 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5999 }
6000#endif
6001
6002 code = param & 0xffff;
6003 fast = (param >> 16) & 0x1;
6004 rep_cnt = (param >> 32) & 0xfff;
6005 rep_idx = (param >> 48) & 0xfff;
6006
6007 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
6008
c25bc163
GN		 6009 switch (code) {
6010 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
6011 kvm_vcpu_on_spin(vcpu);
6012 break;
6013 default:
6014 res = HV_STATUS_INVALID_HYPERCALL_CODE;
6015 break;
6016 }
55cd8e5a
GN		 6017
6018 ret = res | (((u64)rep_done & 0xfff) << 32);
6019 if (longmode) {
6020 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6021 } else {
6022 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
6023 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
6024 }
6025
6026 return 1;
6027}
6028
6aef266c
SV		 6029/*
6030 * kvm_pv_kick_cpu_op: Kick a vcpu.
6031 *
6032 * @apicid - apicid of vcpu to be kicked.
6033 */
6034static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6035{
24d2166b 6036 struct kvm_lapic_irq lapic_irq;
6aef266c 6037
24d2166b
R		 6038 lapic_irq.shorthand = 0;
6039 lapic_irq.dest_mode = 0;
6040 lapic_irq.dest_id = apicid;
93bbf0b8 6041 lapic_irq.msi_redir_hint = false;
6aef266c 6042
24d2166b 6043 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6044 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6045}
6046
8776e519
HB		 6047int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6048{
6049 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6050 int op_64_bit, r = 1;
8776e519 6051
5cb56059
JS		 6052 kvm_x86_ops->skip_emulated_instruction(vcpu);
6053
55cd8e5a
GN		 6054 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6055 return kvm_hv_hypercall(vcpu);
6056
5fdbf976
MT		 6057 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6058 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6059 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6060 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6061 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6062
229456fc 6063 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6064
a449c7aa
NA		 6065 op_64_bit = is_64_bit_mode(vcpu);
6066 if (!op_64_bit) {
8776e519
HB		 6067 nr &= 0xFFFFFFFF;
6068 a0 &= 0xFFFFFFFF;
6069 a1 &= 0xFFFFFFFF;
6070 a2 &= 0xFFFFFFFF;
6071 a3 &= 0xFFFFFFFF;
6072 }
6073
07708c4a
JK		 6074 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6075 ret = -KVM_EPERM;
6076 goto out;
6077 }
6078
8776e519 6079 switch (nr) {
b93463aa
AK		 6080 case KVM_HC_VAPIC_POLL_IRQ:
6081 ret = 0;
6082 break;
6aef266c
SV		 6083 case KVM_HC_KICK_CPU:
6084 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6085 ret = 0;
6086 break;
8776e519
HB		 6087 default:
6088 ret = -KVM_ENOSYS;
6089 break;
6090 }
07708c4a 6091out:
a449c7aa
NA		 6092 if (!op_64_bit)
6093 ret = (u32)ret;
5fdbf976 6094 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6095 ++vcpu->stat.hypercalls;
2f333bcb 6096 return r;
8776e519
HB		 6097}
6098EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6099
b6785def 6100static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6101{
d6aa1000 6102 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6103 char instruction[3];
5fdbf976 6104 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6105
8776e519 6106 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6107
9d74191a 6108 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6109}
6110
b6c7a5dc
HB		 6111/*
6112 * Check if userspace requested an interrupt window, and that the
6113 * interrupt window is open.
6114 *
6115 * No need to exit to userspace if we already have an interrupt queued.
6116 */
851ba692 6117static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6118{
8061823a 6119 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6120 vcpu->run->request_interrupt_window &&
5df56646 6121 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6122}
6123
851ba692 6124static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6125{
851ba692
AK		 6126 struct kvm_run *kvm_run = vcpu->run;
6127
91586a3b 6128 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6129 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6130 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6131 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6132 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6133 else
b6c7a5dc 6134 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6135 kvm_arch_interrupt_allowed(vcpu) &&
6136 !kvm_cpu_has_interrupt(vcpu) &&
6137 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6138}
6139
95ba8273
GN		 6140static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6141{
6142 int max_irr, tpr;
6143
6144 if (!kvm_x86_ops->update_cr8_intercept)
6145 return;
6146
88c808fd
AK		 6147 if (!vcpu->arch.apic)
6148 return;
6149
8db3baa2
GN		 6150 if (!vcpu->arch.apic->vapic_addr)
6151 max_irr = kvm_lapic_find_highest_irr(vcpu);
6152 else
6153 max_irr = -1;
95ba8273
GN		 6154
6155 if (max_irr != -1)
6156 max_irr >>= 4;
6157
6158 tpr = kvm_lapic_get_cr8(vcpu);
6159
6160 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6161}
6162
b6b8a145 6163static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6164{
b6b8a145
JK		 6165 int r;
6166
95ba8273 6167 /* try to reinject previous events if any */
b59bb7bd 6168 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6169 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6170 vcpu->arch.exception.has_error_code,
6171 vcpu->arch.exception.error_code);
d6e8c854
NA		 6172
6173 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6174 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6175 X86_EFLAGS_RF);
6176
6bdf0662
NA		 6177 if (vcpu->arch.exception.nr == DB_VECTOR &&
6178 (vcpu->arch.dr7 & DR7_GD)) {
6179 vcpu->arch.dr7 &= ~DR7_GD;
6180 kvm_update_dr7(vcpu);
6181 }
6182
b59bb7bd
GN		 6183 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6184 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6185 vcpu->arch.exception.error_code,
6186 vcpu->arch.exception.reinject);
b6b8a145 6187 return 0;
b59bb7bd
GN		 6188 }
6189
95ba8273
GN		 6190 if (vcpu->arch.nmi_injected) {
6191 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6192 return 0;
95ba8273
GN		 6193 }
6194
6195 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6196 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6197 return 0;
6198 }
6199
6200 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6201 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6202 if (r != 0)
6203 return r;
95ba8273
GN		 6204 }
6205
6206 /* try to inject new event if pending */
6207 if (vcpu->arch.nmi_pending) {
6208 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6209 --vcpu->arch.nmi_pending;
95ba8273
GN		 6210 vcpu->arch.nmi_injected = true;
6211 kvm_x86_ops->set_nmi(vcpu);
6212 }
c7c9c56c 6213 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6214 /*
6215 * Because interrupts can be injected asynchronously, we are
6216 * calling check_nested_events again here to avoid a race condition.
6217 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6218 * proposal and current concerns. Perhaps we should be setting
6219 * KVM_REQ_EVENT only on certain events and not unconditionally?
6220 */
6221 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6222 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6223 if (r != 0)
6224 return r;
6225 }
95ba8273 6226 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6227 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6228 false);
6229 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6230 }
6231 }
b6b8a145 6232 return 0;
95ba8273
GN		 6233}
6234
7460fb4a
AK		 6235static void process_nmi(struct kvm_vcpu *vcpu)
6236{
6237 unsigned limit = 2;
6238
6239 /*
6240 * x86 is limited to one NMI running, and one NMI pending after it.
6241 * If an NMI is already in progress, limit further NMIs to just one.
6242 * Otherwise, allow two (and we'll inject the first one immediately).
6243 */
6244 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6245 limit = 1;
6246
6247 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6248 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6249 kvm_make_request(KVM_REQ_EVENT, vcpu);
6250}
6251
3d81bc7e 6252static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6253{
6254 u64 eoi_exit_bitmap[4];
cf9e65b7 6255 u32 tmr[8];
c7c9c56c 6256
3d81bc7e
YZ		 6257 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6258 return;
c7c9c56c
YZ		 6259
6260 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6261 memset(tmr, 0, 32);
c7c9c56c 6262
cf9e65b7 6263 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6264 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6265 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6266}
6267
a70656b6
RK		 6268static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6269{
6270 ++vcpu->stat.tlb_flush;
6271 kvm_x86_ops->tlb_flush(vcpu);
6272}
6273
4256f43f
TC		 6274void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6275{
c24ae0dc
TC		 6276 struct page *page = NULL;
6277
f439ed27
PB		 6278 if (!irqchip_in_kernel(vcpu->kvm))
6279 return;
6280
4256f43f
TC		 6281 if (!kvm_x86_ops->set_apic_access_page_addr)
6282 return;
6283
c24ae0dc 6284 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6285 if (is_error_page(page))
6286 return;
c24ae0dc
TC		 6287 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6288
6289 /*
6290 * Do not pin apic access page in memory, the MMU notifier
6291 * will call us again if it is migrated or swapped out.
6292 */
6293 put_page(page);
4256f43f
TC		 6294}
6295EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6296
fe71557a
TC		 6297void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6298 unsigned long address)
6299{
c24ae0dc
TC		 6300 /*
6301 * The physical address of apic access page is stored in the VMCS.
6302 * Update it when it becomes invalid.
6303 */
6304 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6305 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6306}
6307
9357d939 6308/*
362c698f 6309 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6310 * exiting to the userspace. Otherwise, the value will be returned to the
6311 * userspace.
6312 */
851ba692 6313static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6314{
6315 int r;
6a8b1d13 6316 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6317 vcpu->run->request_interrupt_window;
730dca42 6318 bool req_immediate_exit = false;
b6c7a5dc 6319
3e007509 6320 if (vcpu->requests) {
a8eeb04a 6321 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6322 kvm_mmu_unload(vcpu);
a8eeb04a 6323 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6324 __kvm_migrate_timers(vcpu);
d828199e
MT		 6325 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6326 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6327 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6328 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6329 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6330 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6331 if (unlikely(r))
6332 goto out;
6333 }
a8eeb04a 6334 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6335 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6336 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6337 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6338 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6339 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6340 r = 0;
6341 goto out;
6342 }
a8eeb04a 6343 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6344 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6345 r = 0;
6346 goto out;
6347 }
a8eeb04a 6348 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6349 vcpu->fpu_active = 0;
6350 kvm_x86_ops->fpu_deactivate(vcpu);
6351 }
af585b92
GN		 6352 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6353 /* Page is swapped out. Do synthetic halt */
6354 vcpu->arch.apf.halted = true;
6355 r = 1;
6356 goto out;
6357 }
c9aaa895
GC		 6358 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6359 record_steal_time(vcpu);
7460fb4a
AK		 6360 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6361 process_nmi(vcpu);
f5132b01
GN		 6362 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6363 kvm_handle_pmu_event(vcpu);
6364 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6365 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6366 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6367 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6368 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6369 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6370 }
b93463aa 6371
b463a6f7 6372 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6373 kvm_apic_accept_events(vcpu);
6374 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6375 r = 1;
6376 goto out;
6377 }
6378
b6b8a145
JK		 6379 if (inject_pending_event(vcpu, req_int_win) != 0)
6380 req_immediate_exit = true;
b463a6f7 6381 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6382 else if (vcpu->arch.nmi_pending)
c9a7953f 6383 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6384 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6385 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6386
6387 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6388 /*
6389 * Update architecture specific hints for APIC
6390 * virtual interrupt delivery.
6391 */
6392 if (kvm_x86_ops->hwapic_irr_update)
6393 kvm_x86_ops->hwapic_irr_update(vcpu,
6394 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6395 update_cr8_intercept(vcpu);
6396 kvm_lapic_sync_to_vapic(vcpu);
6397 }
6398 }
6399
d8368af8
AK		 6400 r = kvm_mmu_reload(vcpu);
6401 if (unlikely(r)) {
d905c069 6402 goto cancel_injection;
d8368af8
AK		 6403 }
6404
b6c7a5dc
HB		 6405 preempt_disable();
6406
6407 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6408 if (vcpu->fpu_active)
6409 kvm_load_guest_fpu(vcpu);
2acf923e 6410 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6411
6b7e2d09
XG		 6412 vcpu->mode = IN_GUEST_MODE;
6413
01b71917
MT		 6414 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6415
6b7e2d09
XG		 6416 /* We should set ->mode before check ->requests,
6417 * see the comment in make_all_cpus_request.
6418 */
01b71917 6419 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6420
d94e1dc9 6421 local_irq_disable();
32f88400 6422
6b7e2d09 6423 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6424 || need_resched() || signal_pending(current)) {
6b7e2d09 6425 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6426 smp_wmb();
6c142801
AK		 6427 local_irq_enable();
6428 preempt_enable();
01b71917 6429 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6430 r = 1;
d905c069 6431 goto cancel_injection;
6c142801
AK		 6432 }
6433
d6185f20
NHE		 6434 if (req_immediate_exit)
6435 smp_send_reschedule(vcpu->cpu);
6436
ccf73aaf 6437 __kvm_guest_enter();
b6c7a5dc 6438
42dbaa5a 6439 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6440 set_debugreg(0, 7);
6441 set_debugreg(vcpu->arch.eff_db[0], 0);
6442 set_debugreg(vcpu->arch.eff_db[1], 1);
6443 set_debugreg(vcpu->arch.eff_db[2], 2);
6444 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6445 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6446 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6447 }
b6c7a5dc 6448
229456fc 6449 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6450 wait_lapic_expire(vcpu);
851ba692 6451 kvm_x86_ops->run(vcpu);
b6c7a5dc 6452
c77fb5fe
PB		 6453 /*
6454 * Do this here before restoring debug registers on the host. And
6455 * since we do this before handling the vmexit, a DR access vmexit
6456 * can (a) read the correct value of the debug registers, (b) set
6457 * KVM_DEBUGREG_WONT_EXIT again.
6458 */
6459 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6460 int i;
6461
6462 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6463 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6464 for (i = 0; i < KVM_NR_DB_REGS; i++)
6465 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6466 }
6467
24f1e32c
FW		 6468 /*
6469 * If the guest has used debug registers, at least dr7
6470 * will be disabled while returning to the host.
6471 * If we don't have active breakpoints in the host, we don't
6472 * care about the messed up debug address registers. But if
6473 * we have some of them active, restore the old state.
6474 */
59d8eb53 6475 if (hw_breakpoint_active())
24f1e32c 6476 hw_breakpoint_restore();
42dbaa5a 6477
886b470c
MT		 6478 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6479 native_read_tsc());
1d5f066e 6480
6b7e2d09 6481 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6482 smp_wmb();
a547c6db
YZ		 6483
6484 /* Interrupt is enabled by handle_external_intr() */
6485 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6486
6487 ++vcpu->stat.exits;
6488
6489 /*
6490 * We must have an instruction between local_irq_enable() and
6491 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6492 * the interrupt shadow. The stat.exits increment will do nicely.
6493 * But we need to prevent reordering, hence this barrier():
6494 */
6495 barrier();
6496
6497 kvm_guest_exit();
6498
6499 preempt_enable();
6500
f656ce01 6501 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6502
b6c7a5dc
HB		 6503 /*
6504 * Profile KVM exit RIPs:
6505 */
6506 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6507 unsigned long rip = kvm_rip_read(vcpu);
6508 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6509 }
6510
cc578287
ZA		 6511 if (unlikely(vcpu->arch.tsc_always_catchup))
6512 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6513
5cfb1d5a
MT		 6514 if (vcpu->arch.apic_attention)
6515 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6516
851ba692 6517 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6518 return r;
6519
6520cancel_injection:
6521 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6522 if (unlikely(vcpu->arch.apic_attention))
6523 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6524out:
6525 return r;
6526}
b6c7a5dc 6527
362c698f
PB		 6528static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6529{
9c8fd1ba
PB		 6530 if (!kvm_arch_vcpu_runnable(vcpu)) {
6531 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6532 kvm_vcpu_block(vcpu);
6533 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6534 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6535 return 1;
6536 }
362c698f
PB		 6537
6538 kvm_apic_accept_events(vcpu);
6539 switch(vcpu->arch.mp_state) {
6540 case KVM_MP_STATE_HALTED:
6541 vcpu->arch.pv.pv_unhalted = false;
6542 vcpu->arch.mp_state =
6543 KVM_MP_STATE_RUNNABLE;
6544 case KVM_MP_STATE_RUNNABLE:
6545 vcpu->arch.apf.halted = false;
6546 break;
6547 case KVM_MP_STATE_INIT_RECEIVED:
6548 break;
6549 default:
6550 return -EINTR;
6551 break;
6552 }
6553 return 1;
6554}
09cec754 6555
362c698f 6556static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6557{
6558 int r;
f656ce01 6559 struct kvm *kvm = vcpu->kvm;
d7690175 6560
f656ce01 6561 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6562
362c698f 6563 for (;;) {
af585b92
GN		 6564 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6565 !vcpu->arch.apf.halted)
851ba692 6566 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6567 else
6568 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6569 if (r <= 0)
6570 break;
6571
6572 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6573 if (kvm_cpu_has_pending_timer(vcpu))
6574 kvm_inject_pending_timer_irqs(vcpu);
6575
851ba692 6576 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6577 r = -EINTR;
851ba692 6578 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6579 ++vcpu->stat.request_irq_exits;
362c698f 6580 break;
09cec754 6581 }
af585b92
GN		 6582
6583 kvm_check_async_pf_completion(vcpu);
6584
09cec754
GN		 6585 if (signal_pending(current)) {
6586 r = -EINTR;
851ba692 6587 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6588 ++vcpu->stat.signal_exits;
362c698f 6589 break;
09cec754
GN		 6590 }
6591 if (need_resched()) {
f656ce01 6592 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6593 cond_resched();
f656ce01 6594 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6595 }
b6c7a5dc
HB		 6596 }
6597
f656ce01 6598 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6599
6600 return r;
6601}
6602
716d51ab
GN		 6603static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6604{
6605 int r;
6606 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6607 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6608 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6609 if (r != EMULATE_DONE)
6610 return 0;
6611 return 1;
6612}
6613
6614static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6615{
6616 BUG_ON(!vcpu->arch.pio.count);
6617
6618 return complete_emulated_io(vcpu);
6619}
6620
f78146b0
AK		 6621/*
6622 * Implements the following, as a state machine:
6623 *
6624 * read:
6625 * for each fragment
87da7e66
XG		 6626 * for each mmio piece in the fragment
6627 * write gpa, len
6628 * exit
6629 * copy data
f78146b0
AK		 6630 * execute insn
6631 *
6632 * write:
6633 * for each fragment
87da7e66
XG		 6634 * for each mmio piece in the fragment
6635 * write gpa, len
6636 * copy data
6637 * exit
f78146b0 6638 */
716d51ab 6639static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6640{
6641 struct kvm_run *run = vcpu->run;
f78146b0 6642 struct kvm_mmio_fragment *frag;
87da7e66 6643 unsigned len;
5287f194 6644
716d51ab 6645 BUG_ON(!vcpu->mmio_needed);
5287f194 6646
716d51ab 6647 /* Complete previous fragment */
87da7e66
XG		 6648 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6649 len = min(8u, frag->len);
716d51ab 6650 if (!vcpu->mmio_is_write)
87da7e66
XG		 6651 memcpy(frag->data, run->mmio.data, len);
6652
6653 if (frag->len <= 8) {
6654 /* Switch to the next fragment. */
6655 frag++;
6656 vcpu->mmio_cur_fragment++;
6657 } else {
6658 /* Go forward to the next mmio piece. */
6659 frag->data += len;
6660 frag->gpa += len;
6661 frag->len -= len;
6662 }
6663
a08d3b3b 6664 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6665 vcpu->mmio_needed = 0;
0912c977
PB		 6666
6667 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6668 if (vcpu->mmio_is_write)
716d51ab
GN		 6669 return 1;
6670 vcpu->mmio_read_completed = 1;
6671 return complete_emulated_io(vcpu);
6672 }
87da7e66 6673
716d51ab
GN		 6674 run->exit_reason = KVM_EXIT_MMIO;
6675 run->mmio.phys_addr = frag->gpa;
6676 if (vcpu->mmio_is_write)
87da7e66
XG		 6677 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6678 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6679 run->mmio.is_write = vcpu->mmio_is_write;
6680 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6681 return 0;
5287f194
AK		 6682}
6683
716d51ab 6684
b6c7a5dc
HB		 6685int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6686{
6687 int r;
6688 sigset_t sigsaved;
6689
e5c30142
AK		 6690 if (!tsk_used_math(current) && init_fpu(current))
6691 return -ENOMEM;
6692
ac9f6dc0
AK		 6693 if (vcpu->sigset_active)
6694 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6695
a4535290 6696 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6697 kvm_vcpu_block(vcpu);
66450a21 6698 kvm_apic_accept_events(vcpu);
d7690175 6699 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6700 r = -EAGAIN;
6701 goto out;
b6c7a5dc
HB		 6702 }
6703
b6c7a5dc 6704 /* re-sync apic's tpr */
eea1cff9
AP		 6705 if (!irqchip_in_kernel(vcpu->kvm)) {
6706 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6707 r = -EINVAL;
6708 goto out;
6709 }
6710 }
b6c7a5dc 6711
716d51ab
GN		 6712 if (unlikely(vcpu->arch.complete_userspace_io)) {
6713 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6714 vcpu->arch.complete_userspace_io = NULL;
6715 r = cui(vcpu);
6716 if (r <= 0)
6717 goto out;
6718 } else
6719 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6720
362c698f 6721 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6722
6723out:
f1d86e46 6724 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6725 if (vcpu->sigset_active)
6726 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6727
b6c7a5dc
HB		 6728 return r;
6729}
6730
6731int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6732{
7ae441ea
GN		 6733 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6734 /*
6735 * We are here if userspace calls get_regs() in the middle of
6736 * instruction emulation. Registers state needs to be copied
4a969980 6737 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6738 * that usually, but some bad designed PV devices (vmware
6739 * backdoor interface) need this to work
6740 */
dd856efa 6741 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6742 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6743 }
5fdbf976
MT		 6744 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6745 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6746 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6747 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6748 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6749 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6750 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6751 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6752#ifdef CONFIG_X86_64
5fdbf976
MT		 6753 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6754 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6755 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6756 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6757 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6758 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6759 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6760 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6761#endif
6762
5fdbf976 6763 regs->rip = kvm_rip_read(vcpu);
91586a3b 6764 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6765
b6c7a5dc
HB		 6766 return 0;
6767}
6768
6769int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6770{
7ae441ea
GN		 6771 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6772 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6773
5fdbf976
MT		 6774 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6775 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6776 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6777 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6778 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6779 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6780 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6781 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6782#ifdef CONFIG_X86_64
5fdbf976
MT		 6783 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6784 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6785 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6786 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6787 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6788 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6789 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6790 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6791#endif
6792
5fdbf976 6793 kvm_rip_write(vcpu, regs->rip);
91586a3b 6794 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6795
b4f14abd
JK		 6796 vcpu->arch.exception.pending = false;
6797
3842d135
AK		 6798 kvm_make_request(KVM_REQ_EVENT, vcpu);
6799
b6c7a5dc
HB		 6800 return 0;
6801}
6802
b6c7a5dc
HB		 6803void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6804{
6805 struct kvm_segment cs;
6806
3e6e0aab 6807 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6808 *db = cs.db;
6809 *l = cs.l;
6810}
6811EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6812
6813int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6814 struct kvm_sregs *sregs)
6815{
89a27f4d 6816 struct desc_ptr dt;
b6c7a5dc 6817
3e6e0aab
GT		 6818 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6819 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6820 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6821 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6822 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6823 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6824
3e6e0aab
GT		 6825 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6826 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6827
6828 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6829 sregs->idt.limit = dt.size;
6830 sregs->idt.base = dt.address;
b6c7a5dc 6831 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6832 sregs->gdt.limit = dt.size;
6833 sregs->gdt.base = dt.address;
b6c7a5dc 6834
4d4ec087 6835 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6836 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6837 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6838 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6839 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6840 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6841 sregs->apic_base = kvm_get_apic_base(vcpu);
6842
923c61bb 6843 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6844
36752c9b 6845 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6846 set_bit(vcpu->arch.interrupt.nr,
6847 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6848
b6c7a5dc
HB		 6849 return 0;
6850}
6851
62d9f0db
MT		 6852int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6853 struct kvm_mp_state *mp_state)
6854{
66450a21 6855 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6856 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6857 vcpu->arch.pv.pv_unhalted)
6858 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6859 else
6860 mp_state->mp_state = vcpu->arch.mp_state;
6861
62d9f0db
MT		 6862 return 0;
6863}
6864
6865int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6866 struct kvm_mp_state *mp_state)
6867{
66450a21
JK		 6868 if (!kvm_vcpu_has_lapic(vcpu) &&
6869 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6870 return -EINVAL;
6871
6872 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6873 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6874 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6875 } else
6876 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6877 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6878 return 0;
6879}
6880
7f3d35fd
KW		 6881int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6882 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6883{
9d74191a 6884 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6885 int ret;
e01c2426 6886
8ec4722d 6887 init_emulate_ctxt(vcpu);
c697518a 6888
7f3d35fd 6889 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6890 has_error_code, error_code);
c697518a 6891
c697518a 6892 if (ret)
19d04437 6893 return EMULATE_FAIL;
37817f29 6894
9d74191a
TY		 6895 kvm_rip_write(vcpu, ctxt->eip);
6896 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6897 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6898 return EMULATE_DONE;
37817f29
IE		 6899}
6900EXPORT_SYMBOL_GPL(kvm_task_switch);
6901
b6c7a5dc
HB		 6902int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6903 struct kvm_sregs *sregs)
6904{
58cb628d 6905 struct msr_data apic_base_msr;
b6c7a5dc 6906 int mmu_reset_needed = 0;
63f42e02 6907 int pending_vec, max_bits, idx;
89a27f4d 6908 struct desc_ptr dt;
b6c7a5dc 6909
6d1068b3
PM		 6910 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6911 return -EINVAL;
6912
89a27f4d
GN		 6913 dt.size = sregs->idt.limit;
6914 dt.address = sregs->idt.base;
b6c7a5dc 6915 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6916 dt.size = sregs->gdt.limit;
6917 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6918 kvm_x86_ops->set_gdt(vcpu, &dt);
6919
ad312c7c 6920 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6921 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6922 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6923 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6924
2d3ad1f4 6925 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6926
f6801dff 6927 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6928 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6929 apic_base_msr.data = sregs->apic_base;
6930 apic_base_msr.host_initiated = true;
6931 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6932
4d4ec087 6933 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6934 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6935 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6936
fc78f519 6937 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6938 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6939 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6940 kvm_update_cpuid(vcpu);
63f42e02
XG		 6941
6942 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6943 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6944 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6945 mmu_reset_needed = 1;
6946 }
63f42e02 6947 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6948
6949 if (mmu_reset_needed)
6950 kvm_mmu_reset_context(vcpu);
6951
a50abc3b 6952 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6953 pending_vec = find_first_bit(
6954 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6955 if (pending_vec < max_bits) {
66fd3f7f 6956 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6957 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6958 }
6959
3e6e0aab
GT		 6960 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6961 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6962 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6963 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6964 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6965 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6966
3e6e0aab
GT		 6967 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6968 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6969
5f0269f5
ME		 6970 update_cr8_intercept(vcpu);
6971
9c3e4aab 6972 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6973 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6974 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6975 !is_protmode(vcpu))
9c3e4aab
MT		 6976 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6977
3842d135
AK		 6978 kvm_make_request(KVM_REQ_EVENT, vcpu);
6979
b6c7a5dc
HB		 6980 return 0;
6981}
6982
d0bfb940
JK		 6983int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6984 struct kvm_guest_debug *dbg)
b6c7a5dc 6985{
355be0b9 6986 unsigned long rflags;
ae675ef0 6987 int i, r;
b6c7a5dc 6988
4f926bf2
JK		 6989 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6990 r = -EBUSY;
6991 if (vcpu->arch.exception.pending)
2122ff5e 6992 goto out;
4f926bf2
JK		 6993 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6994 kvm_queue_exception(vcpu, DB_VECTOR);
6995 else
6996 kvm_queue_exception(vcpu, BP_VECTOR);
6997 }
6998
91586a3b
JK		 6999 /*
7000 * Read rflags as long as potentially injected trace flags are still
7001 * filtered out.
7002 */
7003 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7004
7005 vcpu->guest_debug = dbg->control;
7006 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7007 vcpu->guest_debug = 0;
7008
7009 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7010 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7011 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7012 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7013 } else {
7014 for (i = 0; i < KVM_NR_DB_REGS; i++)
7015 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7016 }
c8639010 7017 kvm_update_dr7(vcpu);
ae675ef0 7018
f92653ee
JK		 7019 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7020 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7021 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7022
91586a3b
JK		 7023 /*
7024 * Trigger an rflags update that will inject or remove the trace
7025 * flags.
7026 */
7027 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7028
c8639010 7029 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7030
4f926bf2 7031 r = 0;
d0bfb940 7032
2122ff5e 7033out:
b6c7a5dc
HB		 7034
7035 return r;
7036}
7037
8b006791
ZX		 7038/*
7039 * Translate a guest virtual address to a guest physical address.
7040 */
7041int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7042 struct kvm_translation *tr)
7043{
7044 unsigned long vaddr = tr->linear_address;
7045 gpa_t gpa;
f656ce01 7046 int idx;
8b006791 7047
f656ce01 7048 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7049 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7050 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7051 tr->physical_address = gpa;
7052 tr->valid = gpa != UNMAPPED_GVA;
7053 tr->writeable = 1;
7054 tr->usermode = 0;
8b006791
ZX		 7055
7056 return 0;
7057}
7058
d0752060
HB		 7059int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7060{
98918833
SY		 7061 struct i387_fxsave_struct *fxsave =
7062 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7063
d0752060
HB		 7064 memcpy(fpu->fpr, fxsave->st_space, 128);
7065 fpu->fcw = fxsave->cwd;
7066 fpu->fsw = fxsave->swd;
7067 fpu->ftwx = fxsave->twd;
7068 fpu->last_opcode = fxsave->fop;
7069 fpu->last_ip = fxsave->rip;
7070 fpu->last_dp = fxsave->rdp;
7071 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7072
d0752060
HB		 7073 return 0;
7074}
7075
7076int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7077{
98918833
SY		 7078 struct i387_fxsave_struct *fxsave =
7079 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7080
d0752060
HB		 7081 memcpy(fxsave->st_space, fpu->fpr, 128);
7082 fxsave->cwd = fpu->fcw;
7083 fxsave->swd = fpu->fsw;
7084 fxsave->twd = fpu->ftwx;
7085 fxsave->fop = fpu->last_opcode;
7086 fxsave->rip = fpu->last_ip;
7087 fxsave->rdp = fpu->last_dp;
7088 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7089
d0752060
HB		 7090 return 0;
7091}
7092
d28bc9dd 7093int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7094{
10ab25cd
JK		 7095 int err;
7096
7097 err = fpu_alloc(&vcpu->arch.guest_fpu);
7098 if (err)
7099 return err;
7100
d28bc9dd
NA		 7101 if (!init_event)
7102 fpu_finit(&vcpu->arch.guest_fpu);
7103
df1daba7
PB		 7104 if (cpu_has_xsaves)
7105 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7106 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7107
2acf923e
DC		 7108 /*
7109 * Ensure guest xcr0 is valid for loading
7110 */
7111 vcpu->arch.xcr0 = XSTATE_FP;
7112
ad312c7c 7113 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7114
7115 return 0;
d0752060
HB		 7116}
7117EXPORT_SYMBOL_GPL(fx_init);
7118
98918833
SY		 7119static void fx_free(struct kvm_vcpu *vcpu)
7120{
7121 fpu_free(&vcpu->arch.guest_fpu);
7122}
7123
d0752060
HB		 7124void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7125{
2608d7a1 7126 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7127 return;
7128
2acf923e
DC		 7129 /*
7130 * Restore all possible states in the guest,
7131 * and assume host would use all available bits.
7132 * Guest xcr0 would be loaded later.
7133 */
7134 kvm_put_guest_xcr0(vcpu);
d0752060 7135 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7136 __kernel_fpu_begin();
98918833 7137 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7138 trace_kvm_fpu(1);
d0752060 7139}
d0752060
HB		 7140
7141void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7142{
2acf923e
DC		 7143 kvm_put_guest_xcr0(vcpu);
7144
653f52c3
RR		 7145 if (!vcpu->guest_fpu_loaded) {
7146 vcpu->fpu_counter = 0;
d0752060 7147 return;
653f52c3 7148 }
d0752060
HB		 7149
7150 vcpu->guest_fpu_loaded = 0;
98918833 7151 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7152 __kernel_fpu_end();
f096ed85 7153 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7154 /*
7155 * If using eager FPU mode, or if the guest is a frequent user
7156 * of the FPU, just leave the FPU active for next time.
7157 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7158 * the FPU in bursts will revert to loading it on demand.
7159 */
a9b4fb7e 7160 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7161 if (++vcpu->fpu_counter < 5)
7162 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7163 }
0c04851c 7164 trace_kvm_fpu(0);
d0752060 7165}
e9b11c17
ZX		 7166
7167void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7168{
12f9a48f 7169 kvmclock_reset(vcpu);
7f1ea208 7170
f5f48ee1 7171 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7172 fx_free(vcpu);
e9b11c17
ZX		 7173 kvm_x86_ops->vcpu_free(vcpu);
7174}
7175
7176struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7177 unsigned int id)
7178{
c447e76b
LL		 7179 struct kvm_vcpu *vcpu;
7180
6755bae8
ZA		 7181 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7182 printk_once(KERN_WARNING
7183 "kvm: SMP vm created on host with unstable TSC; "
7184 "guest TSC will not be reliable\n");
c447e76b
LL		 7185
7186 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7187
7188 /*
7189 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7190 * deactivated soon if it doesn't.
7191 */
7192 kvm_x86_ops->fpu_activate(vcpu);
7193 return vcpu;
26e5215f 7194}
e9b11c17 7195
26e5215f
AK		 7196int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7197{
7198 int r;
e9b11c17 7199
0bed3b56 7200 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7201 r = vcpu_load(vcpu);
7202 if (r)
7203 return r;
d28bc9dd 7204 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7205 kvm_mmu_setup(vcpu);
e9b11c17 7206 vcpu_put(vcpu);
e9b11c17 7207
26e5215f 7208 return r;
e9b11c17
ZX		 7209}
7210
31928aa5 7211void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7212{
8fe8ab46 7213 struct msr_data msr;
332967a3 7214 struct kvm *kvm = vcpu->kvm;
42897d86 7215
31928aa5
DD		 7216 if (vcpu_load(vcpu))
7217 return;
8fe8ab46
WA		 7218 msr.data = 0x0;
7219 msr.index = MSR_IA32_TSC;
7220 msr.host_initiated = true;
7221 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7222 vcpu_put(vcpu);
7223
332967a3
AJ		 7224 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7225 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7226}
7227
d40ccc62 7228void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7229{
9fc77441 7230 int r;
344d9588
GN		 7231 vcpu->arch.apf.msr_val = 0;
7232
9fc77441
MT		 7233 r = vcpu_load(vcpu);
7234 BUG_ON(r);
e9b11c17
ZX		 7235 kvm_mmu_unload(vcpu);
7236 vcpu_put(vcpu);
7237
98918833 7238 fx_free(vcpu);
e9b11c17
ZX		 7239 kvm_x86_ops->vcpu_free(vcpu);
7240}
7241
d28bc9dd 7242void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7243{
7460fb4a
AK		 7244 atomic_set(&vcpu->arch.nmi_queued, 0);
7245 vcpu->arch.nmi_pending = 0;
448fa4a9 7246 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7247 kvm_clear_interrupt_queue(vcpu);
7248 kvm_clear_exception_queue(vcpu);
448fa4a9 7249
42dbaa5a 7250 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7251 kvm_update_dr0123(vcpu);
6f43ed01 7252 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7253 kvm_update_dr6(vcpu);
42dbaa5a 7254 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7255 kvm_update_dr7(vcpu);
42dbaa5a 7256
1119022c
NA		 7257 vcpu->arch.cr2 = 0;
7258
3842d135 7259 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7260 vcpu->arch.apf.msr_val = 0;
c9aaa895 7261 vcpu->arch.st.msr_val = 0;
3842d135 7262
12f9a48f
GC		 7263 kvmclock_reset(vcpu);
7264
af585b92
GN		 7265 kvm_clear_async_pf_completion_queue(vcpu);
7266 kvm_async_pf_hash_reset(vcpu);
7267 vcpu->arch.apf.halted = false;
3842d135 7268
d28bc9dd
NA		 7269 if (!init_event)
7270 kvm_pmu_reset(vcpu);
f5132b01 7271
66f7b72e
JS		 7272 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7273 vcpu->arch.regs_avail = ~0;
7274 vcpu->arch.regs_dirty = ~0;
7275
d28bc9dd 7276 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7277}
7278
2b4a273b 7279void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7280{
7281 struct kvm_segment cs;
7282
7283 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7284 cs.selector = vector << 8;
7285 cs.base = vector << 12;
7286 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7287 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7288}
7289
13a34e06 7290int kvm_arch_hardware_enable(void)
e9b11c17 7291{
ca84d1a2
ZA		 7292 struct kvm *kvm;
7293 struct kvm_vcpu *vcpu;
7294 int i;
0dd6a6ed
ZA		 7295 int ret;
7296 u64 local_tsc;
7297 u64 max_tsc = 0;
7298 bool stable, backwards_tsc = false;
18863bdd
AK		 7299
7300 kvm_shared_msr_cpu_online();
13a34e06 7301 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7302 if (ret != 0)
7303 return ret;
7304
7305 local_tsc = native_read_tsc();
7306 stable = !check_tsc_unstable();
7307 list_for_each_entry(kvm, &vm_list, vm_list) {
7308 kvm_for_each_vcpu(i, vcpu, kvm) {
7309 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7310 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7311 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7312 backwards_tsc = true;
7313 if (vcpu->arch.last_host_tsc > max_tsc)
7314 max_tsc = vcpu->arch.last_host_tsc;
7315 }
7316 }
7317 }
7318
7319 /*
7320 * Sometimes, even reliable TSCs go backwards. This happens on
7321 * platforms that reset TSC during suspend or hibernate actions, but
7322 * maintain synchronization. We must compensate. Fortunately, we can
7323 * detect that condition here, which happens early in CPU bringup,
7324 * before any KVM threads can be running. Unfortunately, we can't
7325 * bring the TSCs fully up to date with real time, as we aren't yet far
7326 * enough into CPU bringup that we know how much real time has actually
7327 * elapsed; our helper function, get_kernel_ns() will be using boot
7328 * variables that haven't been updated yet.
7329 *
7330 * So we simply find the maximum observed TSC above, then record the
7331 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7332 * the adjustment will be applied. Note that we accumulate
7333 * adjustments, in case multiple suspend cycles happen before some VCPU
7334 * gets a chance to run again. In the event that no KVM threads get a
7335 * chance to run, we will miss the entire elapsed period, as we'll have
7336 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7337 * loose cycle time. This isn't too big a deal, since the loss will be
7338 * uniform across all VCPUs (not to mention the scenario is extremely
7339 * unlikely). It is possible that a second hibernate recovery happens
7340 * much faster than a first, causing the observed TSC here to be
7341 * smaller; this would require additional padding adjustment, which is
7342 * why we set last_host_tsc to the local tsc observed here.
7343 *
7344 * N.B. - this code below runs only on platforms with reliable TSC,
7345 * as that is the only way backwards_tsc is set above. Also note
7346 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7347 * have the same delta_cyc adjustment applied if backwards_tsc
7348 * is detected. Note further, this adjustment is only done once,
7349 * as we reset last_host_tsc on all VCPUs to stop this from being
7350 * called multiple times (one for each physical CPU bringup).
7351 *
4a969980 7352 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7353 * will be compensated by the logic in vcpu_load, which sets the TSC to
7354 * catchup mode. This will catchup all VCPUs to real time, but cannot
7355 * guarantee that they stay in perfect synchronization.
7356 */
7357 if (backwards_tsc) {
7358 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7359 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7360 list_for_each_entry(kvm, &vm_list, vm_list) {
7361 kvm_for_each_vcpu(i, vcpu, kvm) {
7362 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7363 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7364 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7365 }
7366
7367 /*
7368 * We have to disable TSC offset matching.. if you were
7369 * booting a VM while issuing an S4 host suspend....
7370 * you may have some problem. Solving this issue is
7371 * left as an exercise to the reader.
7372 */
7373 kvm->arch.last_tsc_nsec = 0;
7374 kvm->arch.last_tsc_write = 0;
7375 }
7376
7377 }
7378 return 0;
e9b11c17
ZX		 7379}
7380
13a34e06 7381void kvm_arch_hardware_disable(void)
e9b11c17 7382{
13a34e06
RK		 7383 kvm_x86_ops->hardware_disable();
7384 drop_user_return_notifiers();
e9b11c17
ZX		 7385}
7386
7387int kvm_arch_hardware_setup(void)
7388{
9e9c3fe4
NA		 7389 int r;
7390
7391 r = kvm_x86_ops->hardware_setup();
7392 if (r != 0)
7393 return r;
7394
7395 kvm_init_msr_list();
7396 return 0;
e9b11c17
ZX		 7397}
7398
7399void kvm_arch_hardware_unsetup(void)
7400{
7401 kvm_x86_ops->hardware_unsetup();
7402}
7403
7404void kvm_arch_check_processor_compat(void *rtn)
7405{
7406 kvm_x86_ops->check_processor_compatibility(rtn);
7407}
7408
3e515705
AK		 7409bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7410{
7411 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7412}
7413
54e9818f
GN		 7414struct static_key kvm_no_apic_vcpu __read_mostly;
7415
e9b11c17
ZX		 7416int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7417{
7418 struct page *page;
7419 struct kvm *kvm;
7420 int r;
7421
7422 BUG_ON(vcpu->kvm == NULL);
7423 kvm = vcpu->kvm;
7424
6aef266c 7425 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7426 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7427 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7428 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7429 else
a4535290 7430 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7431
7432 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7433 if (!page) {
7434 r = -ENOMEM;
7435 goto fail;
7436 }
ad312c7c 7437 vcpu->arch.pio_data = page_address(page);
e9b11c17 7438
cc578287 7439 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7440
e9b11c17
ZX		 7441 r = kvm_mmu_create(vcpu);
7442 if (r < 0)
7443 goto fail_free_pio_data;
7444
7445 if (irqchip_in_kernel(kvm)) {
7446 r = kvm_create_lapic(vcpu);
7447 if (r < 0)
7448 goto fail_mmu_destroy;
54e9818f
GN		 7449 } else
7450 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7451
890ca9ae
HY		 7452 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7453 GFP_KERNEL);
7454 if (!vcpu->arch.mce_banks) {
7455 r = -ENOMEM;
443c39bc 7456 goto fail_free_lapic;
890ca9ae
HY		 7457 }
7458 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7459
f1797359
WY		 7460 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7461 r = -ENOMEM;
f5f48ee1 7462 goto fail_free_mce_banks;
f1797359 7463 }
f5f48ee1 7464
d28bc9dd 7465 r = fx_init(vcpu, false);
66f7b72e
JS		 7466 if (r)
7467 goto fail_free_wbinvd_dirty_mask;
7468
ba904635 7469 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7470 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7471
7472 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7473 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7474
5a4f55cd
EK		 7475 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7476
74545705
RK		 7477 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7478
af585b92 7479 kvm_async_pf_hash_reset(vcpu);
f5132b01 7480 kvm_pmu_init(vcpu);
af585b92 7481
e9b11c17 7482 return 0;
66f7b72e
JS		 7483fail_free_wbinvd_dirty_mask:
7484 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7485fail_free_mce_banks:
7486 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7487fail_free_lapic:
7488 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7489fail_mmu_destroy:
7490 kvm_mmu_destroy(vcpu);
7491fail_free_pio_data:
ad312c7c 7492 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7493fail:
7494 return r;
7495}
7496
7497void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7498{
f656ce01
MT		 7499 int idx;
7500
f5132b01 7501 kvm_pmu_destroy(vcpu);
36cb93fd 7502 kfree(vcpu->arch.mce_banks);
e9b11c17 7503 kvm_free_lapic(vcpu);
f656ce01 7504 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7505 kvm_mmu_destroy(vcpu);
f656ce01 7506 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7507 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7508 if (!irqchip_in_kernel(vcpu->kvm))
7509 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7510}
d19a9cd2 7511
e790d9ef
RK		 7512void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7513{
ae97a3b8 7514 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7515}
7516
e08b9637 7517int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7518{
e08b9637
CO		 7519 if (type)
7520 return -EINVAL;
7521
6ef768fa 7522 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7523 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7524 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7525 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7526 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7527
5550af4d
SY		 7528 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7529 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7530 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7531 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7532 &kvm->arch.irq_sources_bitmap);
5550af4d 7533
038f8c11 7534 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7535 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7536 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7537
7538 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7539
7e44e449 7540 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7541 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7542
d89f5eff 7543 return 0;
d19a9cd2
ZX		 7544}
7545
7546static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7547{
9fc77441
MT		 7548 int r;
7549 r = vcpu_load(vcpu);
7550 BUG_ON(r);
d19a9cd2
ZX		 7551 kvm_mmu_unload(vcpu);
7552 vcpu_put(vcpu);
7553}
7554
7555static void kvm_free_vcpus(struct kvm *kvm)
7556{
7557 unsigned int i;
988a2cae 7558 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7559
7560 /*
7561 * Unpin any mmu pages first.
7562 */
af585b92
GN		 7563 kvm_for_each_vcpu(i, vcpu, kvm) {
7564 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7565 kvm_unload_vcpu_mmu(vcpu);
af585b92 7566 }
988a2cae
GN		 7567 kvm_for_each_vcpu(i, vcpu, kvm)
7568 kvm_arch_vcpu_free(vcpu);
7569
7570 mutex_lock(&kvm->lock);
7571 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7572 kvm->vcpus[i] = NULL;
d19a9cd2 7573
988a2cae
GN		 7574 atomic_set(&kvm->online_vcpus, 0);
7575 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7576}
7577
ad8ba2cd
SY		 7578void kvm_arch_sync_events(struct kvm *kvm)
7579{
332967a3 7580 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7581 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7582 kvm_free_all_assigned_devices(kvm);
aea924f6 7583 kvm_free_pit(kvm);
ad8ba2cd
SY		 7584}
7585
d19a9cd2
ZX		 7586void kvm_arch_destroy_vm(struct kvm *kvm)
7587{
27469d29
AH		 7588 if (current->mm == kvm->mm) {
7589 /*
7590 * Free memory regions allocated on behalf of userspace,
7591 * unless the the memory map has changed due to process exit
7592 * or fd copying.
7593 */
7594 struct kvm_userspace_memory_region mem;
7595 memset(&mem, 0, sizeof(mem));
7596 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7597 kvm_set_memory_region(kvm, &mem);
7598
7599 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7600 kvm_set_memory_region(kvm, &mem);
7601
7602 mem.slot = TSS_PRIVATE_MEMSLOT;
7603 kvm_set_memory_region(kvm, &mem);
7604 }
6eb55818 7605 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7606 kfree(kvm->arch.vpic);
7607 kfree(kvm->arch.vioapic);
d19a9cd2 7608 kvm_free_vcpus(kvm);
1e08ec4a 7609 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7610}
0de10343 7611
5587027c 7612void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7613 struct kvm_memory_slot *dont)
7614{
7615 int i;
7616
d89cc617
TY		 7617 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7618 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7619 kvfree(free->arch.rmap[i]);
d89cc617 7620 free->arch.rmap[i] = NULL;
77d11309 7621 }
d89cc617
TY		 7622 if (i == 0)
7623 continue;
7624
7625 if (!dont || free->arch.lpage_info[i - 1] !=
7626 dont->arch.lpage_info[i - 1]) {
548ef284 7627 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7628 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7629 }
7630 }
7631}
7632
5587027c
AK		 7633int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7634 unsigned long npages)
db3fe4eb
TY		 7635{
7636 int i;
7637
d89cc617 7638 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7639 unsigned long ugfn;
7640 int lpages;
d89cc617 7641 int level = i + 1;
db3fe4eb
TY		 7642
7643 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7644 slot->base_gfn, level) + 1;
7645
d89cc617
TY		 7646 slot->arch.rmap[i] =
7647 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7648 if (!slot->arch.rmap[i])
77d11309 7649 goto out_free;
d89cc617
TY		 7650 if (i == 0)
7651 continue;
77d11309 7652
d89cc617
TY		 7653 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7654 sizeof(*slot->arch.lpage_info[i - 1]));
7655 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7656 goto out_free;
7657
7658 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7659 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7660 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7661 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7662 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7663 /*
7664 * If the gfn and userspace address are not aligned wrt each
7665 * other, or if explicitly asked to, disable large page
7666 * support for this slot
7667 */
7668 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7669 !kvm_largepages_enabled()) {
7670 unsigned long j;
7671
7672 for (j = 0; j < lpages; ++j)
d89cc617 7673 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7674 }
7675 }
7676
7677 return 0;
7678
7679out_free:
d89cc617 7680 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7681 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7682 slot->arch.rmap[i] = NULL;
7683 if (i == 0)
7684 continue;
7685
548ef284 7686 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7687 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7688 }
7689 return -ENOMEM;
7690}
7691
15f46015 7692void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7693{
e6dff7d1
TY		 7694 /*
7695 * memslots->generation has been incremented.
7696 * mmio generation may have reached its maximum value.
7697 */
7698 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7699}
7700
f7784b8e
MT		 7701int kvm_arch_prepare_memory_region(struct kvm *kvm,
7702 struct kvm_memory_slot *memslot,
09170a49 7703 const struct kvm_userspace_memory_region *mem,
7b6195a9 7704 enum kvm_mr_change change)
0de10343 7705{
7a905b14
TY		 7706 /*
7707 * Only private memory slots need to be mapped here since
7708 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7709 */
7b6195a9 7710 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7711 unsigned long userspace_addr;
604b38ac 7712
7a905b14
TY		 7713 /*
7714 * MAP_SHARED to prevent internal slot pages from being moved
7715 * by fork()/COW.
7716 */
7b6195a9 7717 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7718 PROT_READ | PROT_WRITE,
7719 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7720
7a905b14
TY		 7721 if (IS_ERR((void *)userspace_addr))
7722 return PTR_ERR((void *)userspace_addr);
604b38ac 7723
7a905b14 7724 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7725 }
7726
f7784b8e
MT		 7727 return 0;
7728}
7729
88178fd4
KH		 7730static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7731 struct kvm_memory_slot *new)
7732{
7733 /* Still write protect RO slot */
7734 if (new->flags & KVM_MEM_READONLY) {
7735 kvm_mmu_slot_remove_write_access(kvm, new);
7736 return;
7737 }
7738
7739 /*
7740 * Call kvm_x86_ops dirty logging hooks when they are valid.
7741 *
7742 * kvm_x86_ops->slot_disable_log_dirty is called when:
7743 *
7744 * - KVM_MR_CREATE with dirty logging is disabled
7745 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7746 *
7747 * The reason is, in case of PML, we need to set D-bit for any slots
7748 * with dirty logging disabled in order to eliminate unnecessary GPA
7749 * logging in PML buffer (and potential PML buffer full VMEXT). This
7750 * guarantees leaving PML enabled during guest's lifetime won't have
7751 * any additonal overhead from PML when guest is running with dirty
7752 * logging disabled for memory slots.
7753 *
7754 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7755 * to dirty logging mode.
7756 *
7757 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7758 *
7759 * In case of write protect:
7760 *
7761 * Write protect all pages for dirty logging.
7762 *
7763 * All the sptes including the large sptes which point to this
7764 * slot are set to readonly. We can not create any new large
7765 * spte on this slot until the end of the logging.
7766 *
7767 * See the comments in fast_page_fault().
7768 */
7769 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7770 if (kvm_x86_ops->slot_enable_log_dirty)
7771 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7772 else
7773 kvm_mmu_slot_remove_write_access(kvm, new);
7774 } else {
7775 if (kvm_x86_ops->slot_disable_log_dirty)
7776 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7777 }
7778}
7779
f7784b8e 7780void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7781 const struct kvm_userspace_memory_region *mem,
8482644a
TY		 7782 const struct kvm_memory_slot *old,
7783 enum kvm_mr_change change)
f7784b8e 7784{
9f6b8029 7785 struct kvm_memslots *slots;
1c91cad4 7786 struct kvm_memory_slot *new;
8482644a 7787 int nr_mmu_pages = 0;
f7784b8e 7788
8482644a 7789 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7790 int ret;
7791
8482644a
TY		 7792 ret = vm_munmap(old->userspace_addr,
7793 old->npages * PAGE_SIZE);
f7784b8e
MT		 7794 if (ret < 0)
7795 printk(KERN_WARNING
7796 "kvm_vm_ioctl_set_memory_region: "
7797 "failed to munmap memory\n");
7798 }
7799
48c0e4e9
XG		 7800 if (!kvm->arch.n_requested_mmu_pages)
7801 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7802
48c0e4e9 7803 if (nr_mmu_pages)
0de10343 7804 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4
KH		 7805
7806 /* It's OK to get 'new' slot here as it has already been installed */
9f6b8029
PB		 7807 slots = kvm_memslots(kvm);
7808 new = id_to_memslot(slots, mem->slot);
1c91cad4 7809
3ea3b7fa
WL		 7810 /*
7811 * Dirty logging tracks sptes in 4k granularity, meaning that large
7812 * sptes have to be split. If live migration is successful, the guest
7813 * in the source machine will be destroyed and large sptes will be
7814 * created in the destination. However, if the guest continues to run
7815 * in the source machine (for example if live migration fails), small
7816 * sptes will remain around and cause bad performance.
7817 *
7818 * Scan sptes if dirty logging has been stopped, dropping those
7819 * which can be collapsed into a single large-page spte. Later
7820 * page faults will create the large-page sptes.
7821 */
7822 if ((change != KVM_MR_DELETE) &&
7823 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7824 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7825 kvm_mmu_zap_collapsible_sptes(kvm, new);
7826
c972f3b1 7827 /*
88178fd4 7828 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7829 *
88178fd4
KH		 7830 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7831 * been zapped so no dirty logging staff is needed for old slot. For
7832 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7833 * new and it's also covered when dealing with the new slot.
c972f3b1 7834 */
88178fd4
KH		 7835 if (change != KVM_MR_DELETE)
7836 kvm_mmu_slot_apply_flags(kvm, new);
0de10343 7837}
1d737c8a 7838
2df72e9b 7839void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7840{
6ca18b69 7841 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7842}
7843
2df72e9b
MT		 7844void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7845 struct kvm_memory_slot *slot)
7846{
6ca18b69 7847 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7848}
7849
1d737c8a
ZX		 7850int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7851{
b6b8a145
JK		 7852 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7853 kvm_x86_ops->check_nested_events(vcpu, false);
7854
af585b92
GN		 7855 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7856 !vcpu->arch.apf.halted)
7857 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7858 || kvm_apic_has_events(vcpu)
6aef266c 7859 || vcpu->arch.pv.pv_unhalted
7460fb4a 7860 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7861 (kvm_arch_interrupt_allowed(vcpu) &&
7862 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7863}
5736199a 7864
b6d33834 7865int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7866{
b6d33834 7867 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7868}
78646121
GN		 7869
7870int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7871{
7872 return kvm_x86_ops->interrupt_allowed(vcpu);
7873}
229456fc 7874
82b32774 7875unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7876{
82b32774
NA		 7877 if (is_64_bit_mode(vcpu))
7878 return kvm_rip_read(vcpu);
7879 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7880 kvm_rip_read(vcpu));
7881}
7882EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7883
82b32774
NA		 7884bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7885{
7886 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7887}
7888EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7889
94fe45da
JK		 7890unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7891{
7892 unsigned long rflags;
7893
7894 rflags = kvm_x86_ops->get_rflags(vcpu);
7895 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7896 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7897 return rflags;
7898}
7899EXPORT_SYMBOL_GPL(kvm_get_rflags);
7900
6addfc42 7901static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7902{
7903 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7904 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7905 rflags |= X86_EFLAGS_TF;
94fe45da 7906 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7907}
7908
7909void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7910{
7911 __kvm_set_rflags(vcpu, rflags);
3842d135 7912 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7913}
7914EXPORT_SYMBOL_GPL(kvm_set_rflags);
7915
56028d08
GN		 7916void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7917{
7918 int r;
7919
fb67e14f 7920 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7921 work->wakeup_all)
56028d08
GN		 7922 return;
7923
7924 r = kvm_mmu_reload(vcpu);
7925 if (unlikely(r))
7926 return;
7927
fb67e14f
XG		 7928 if (!vcpu->arch.mmu.direct_map &&
7929 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7930 return;
7931
56028d08
GN		 7932 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7933}
7934
af585b92
GN		 7935static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7936{
7937 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7938}
7939
7940static inline u32 kvm_async_pf_next_probe(u32 key)
7941{
7942 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7943}
7944
7945static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7946{
7947 u32 key = kvm_async_pf_hash_fn(gfn);
7948
7949 while (vcpu->arch.apf.gfns[key] != ~0)
7950 key = kvm_async_pf_next_probe(key);
7951
7952 vcpu->arch.apf.gfns[key] = gfn;
7953}
7954
7955static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7956{
7957 int i;
7958 u32 key = kvm_async_pf_hash_fn(gfn);
7959
7960 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7961 (vcpu->arch.apf.gfns[key] != gfn &&
7962 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7963 key = kvm_async_pf_next_probe(key);
7964
7965 return key;
7966}
7967
7968bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7969{
7970 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7971}
7972
7973static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7974{
7975 u32 i, j, k;
7976
7977 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7978 while (true) {
7979 vcpu->arch.apf.gfns[i] = ~0;
7980 do {
7981 j = kvm_async_pf_next_probe(j);
7982 if (vcpu->arch.apf.gfns[j] == ~0)
7983 return;
7984 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7985 /*
7986 * k lies cyclically in ]i,j]
7987 * | i.k.j |
7988 * |....j i.k.| or |.k..j i...|
7989 */
7990 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7991 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7992 i = j;
7993 }
7994}
7995
7c90705b
GN		 7996static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7997{
7998
7999 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8000 sizeof(val));
8001}
8002
af585b92
GN		 8003void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8004 struct kvm_async_pf *work)
8005{
6389ee94
AK		 8006 struct x86_exception fault;
8007
7c90705b 8008 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8009 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8010
8011 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8012 (vcpu->arch.apf.send_user_only &&
8013 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8014 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8015 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8016 fault.vector = PF_VECTOR;
8017 fault.error_code_valid = true;
8018 fault.error_code = 0;
8019 fault.nested_page_fault = false;
8020 fault.address = work->arch.token;
8021 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8022 }
af585b92
GN		 8023}
8024
8025void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8026 struct kvm_async_pf *work)
8027{
6389ee94
AK		 8028 struct x86_exception fault;
8029
7c90705b 8030 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8031 if (work->wakeup_all)
7c90705b
GN		 8032 work->arch.token = ~0; /* broadcast wakeup */
8033 else
8034 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8035
8036 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8037 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8038 fault.vector = PF_VECTOR;
8039 fault.error_code_valid = true;
8040 fault.error_code = 0;
8041 fault.nested_page_fault = false;
8042 fault.address = work->arch.token;
8043 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8044 }
e6d53e3b 8045 vcpu->arch.apf.halted = false;
a4fa1635 8046 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8047}
8048
8049bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8050{
8051 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8052 return true;
8053 else
8054 return !kvm_event_needs_reinjection(vcpu) &&
8055 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8056}
8057
e0f0bbc5
AW		 8058void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8059{
8060 atomic_inc(&kvm->arch.noncoherent_dma_count);
8061}
8062EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8063
8064void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8065{
8066 atomic_dec(&kvm->arch.noncoherent_dma_count);
8067}
8068EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8069
8070bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8071{
8072 return atomic_read(&kvm->arch.noncoherent_dma_count);
8073}
8074EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8075
229456fc
MT		 8076EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8077EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8078EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8079EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8080EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8081EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8082EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8083EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8084EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8085EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8086EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8087EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8088EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8089EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8090EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git