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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
acd5c798 | 47 | |
3d261580 | 48 | #include "gdb_assert.h" |
acd5c798 | 49 | #include "gdb_string.h" |
3d261580 | 50 | |
d2a7c97a | 51 | #include "i386-tdep.h" |
61113f8b | 52 | #include "i387-tdep.h" |
d2a7c97a | 53 | |
7ad10968 HZ |
54 | #include "record.h" |
55 | #include <stdint.h> | |
56 | ||
90884b2b L |
57 | #include "features/i386/i386.c" |
58 | ||
c4fc7f1b | 59 | /* Register names. */ |
c40e1eab | 60 | |
90884b2b | 61 | static const char *i386_register_names[] = |
fc633446 MK |
62 | { |
63 | "eax", "ecx", "edx", "ebx", | |
64 | "esp", "ebp", "esi", "edi", | |
65 | "eip", "eflags", "cs", "ss", | |
66 | "ds", "es", "fs", "gs", | |
67 | "st0", "st1", "st2", "st3", | |
68 | "st4", "st5", "st6", "st7", | |
69 | "fctrl", "fstat", "ftag", "fiseg", | |
70 | "fioff", "foseg", "fooff", "fop", | |
71 | "xmm0", "xmm1", "xmm2", "xmm3", | |
72 | "xmm4", "xmm5", "xmm6", "xmm7", | |
73 | "mxcsr" | |
74 | }; | |
75 | ||
c4fc7f1b | 76 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 77 | |
90884b2b | 78 | static const char *i386_mmx_names[] = |
28fc6740 AC |
79 | { |
80 | "mm0", "mm1", "mm2", "mm3", | |
81 | "mm4", "mm5", "mm6", "mm7" | |
82 | }; | |
c40e1eab | 83 | |
1ba53b71 L |
84 | /* Register names for byte pseudo-registers. */ |
85 | ||
86 | static const char *i386_byte_names[] = | |
87 | { | |
88 | "al", "cl", "dl", "bl", | |
89 | "ah", "ch", "dh", "bh" | |
90 | }; | |
91 | ||
92 | /* Register names for word pseudo-registers. */ | |
93 | ||
94 | static const char *i386_word_names[] = | |
95 | { | |
96 | "ax", "cx", "dx", "bx", | |
97 | "sp", "bp", "si", "di" | |
98 | }; | |
99 | ||
100 | /* MMX register? */ | |
c40e1eab | 101 | |
28fc6740 | 102 | static int |
5716833c | 103 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 104 | { |
1ba53b71 L |
105 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
106 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
107 | |
108 | if (mm0_regnum < 0) | |
109 | return 0; | |
110 | ||
1ba53b71 L |
111 | regnum -= mm0_regnum; |
112 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
113 | } | |
114 | ||
115 | /* Byte register? */ | |
116 | ||
117 | int | |
118 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
119 | { | |
120 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
121 | ||
122 | regnum -= tdep->al_regnum; | |
123 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
124 | } | |
125 | ||
126 | /* Word register? */ | |
127 | ||
128 | int | |
129 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
130 | { | |
131 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
132 | ||
133 | regnum -= tdep->ax_regnum; | |
134 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
135 | } | |
136 | ||
137 | /* Dword register? */ | |
138 | ||
139 | int | |
140 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
141 | { | |
142 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
143 | int eax_regnum = tdep->eax_regnum; | |
144 | ||
145 | if (eax_regnum < 0) | |
146 | return 0; | |
147 | ||
148 | regnum -= eax_regnum; | |
149 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
150 | } |
151 | ||
5716833c | 152 | /* SSE register? */ |
23a34459 | 153 | |
5716833c MK |
154 | static int |
155 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 156 | { |
5716833c MK |
157 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
158 | ||
20a6ec49 | 159 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
160 | return 0; |
161 | ||
20a6ec49 MD |
162 | return (I387_XMM0_REGNUM (tdep) <= regnum |
163 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
164 | } |
165 | ||
5716833c MK |
166 | static int |
167 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 168 | { |
5716833c MK |
169 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
170 | ||
20a6ec49 | 171 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
172 | return 0; |
173 | ||
20a6ec49 | 174 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
175 | } |
176 | ||
5716833c | 177 | /* FP register? */ |
23a34459 AC |
178 | |
179 | int | |
20a6ec49 | 180 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 181 | { |
20a6ec49 MD |
182 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
183 | ||
184 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
185 | return 0; |
186 | ||
20a6ec49 MD |
187 | return (I387_ST0_REGNUM (tdep) <= regnum |
188 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
189 | } |
190 | ||
191 | int | |
20a6ec49 | 192 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 193 | { |
20a6ec49 MD |
194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
195 | ||
196 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
197 | return 0; |
198 | ||
20a6ec49 MD |
199 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
200 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
201 | } |
202 | ||
30b0e2d8 | 203 | /* Return the name of register REGNUM. */ |
fc633446 | 204 | |
1ba53b71 | 205 | const char * |
90884b2b | 206 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 207 | { |
1ba53b71 L |
208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
209 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
210 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
211 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
212 | return i386_byte_names[regnum - tdep->al_regnum]; | |
213 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
214 | return i386_word_names[regnum - tdep->ax_regnum]; | |
215 | ||
216 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
217 | } |
218 | ||
c4fc7f1b | 219 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
220 | number used by GDB. */ |
221 | ||
8201327c | 222 | static int |
d3f73121 | 223 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 224 | { |
20a6ec49 MD |
225 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
226 | ||
c4fc7f1b MK |
227 | /* This implements what GCC calls the "default" register map |
228 | (dbx_register_map[]). */ | |
229 | ||
85540d8c MK |
230 | if (reg >= 0 && reg <= 7) |
231 | { | |
9872ad24 JB |
232 | /* General-purpose registers. The debug info calls %ebp |
233 | register 4, and %esp register 5. */ | |
234 | if (reg == 4) | |
235 | return 5; | |
236 | else if (reg == 5) | |
237 | return 4; | |
238 | else return reg; | |
85540d8c MK |
239 | } |
240 | else if (reg >= 12 && reg <= 19) | |
241 | { | |
242 | /* Floating-point registers. */ | |
20a6ec49 | 243 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
244 | } |
245 | else if (reg >= 21 && reg <= 28) | |
246 | { | |
247 | /* SSE registers. */ | |
20a6ec49 | 248 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
249 | } |
250 | else if (reg >= 29 && reg <= 36) | |
251 | { | |
252 | /* MMX registers. */ | |
20a6ec49 | 253 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
254 | } |
255 | ||
256 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 257 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
258 | } |
259 | ||
c4fc7f1b MK |
260 | /* Convert SVR4 register number REG to the appropriate register number |
261 | used by GDB. */ | |
85540d8c | 262 | |
8201327c | 263 | static int |
d3f73121 | 264 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 265 | { |
20a6ec49 MD |
266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
267 | ||
c4fc7f1b MK |
268 | /* This implements the GCC register map that tries to be compatible |
269 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
270 | ||
271 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
272 | numbers the floating point registers differently. */ |
273 | if (reg >= 0 && reg <= 9) | |
274 | { | |
acd5c798 | 275 | /* General-purpose registers. */ |
85540d8c MK |
276 | return reg; |
277 | } | |
278 | else if (reg >= 11 && reg <= 18) | |
279 | { | |
280 | /* Floating-point registers. */ | |
20a6ec49 | 281 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 282 | } |
c6f4c129 | 283 | else if (reg >= 21 && reg <= 36) |
85540d8c | 284 | { |
c4fc7f1b | 285 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 286 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
287 | } |
288 | ||
c6f4c129 JB |
289 | switch (reg) |
290 | { | |
20a6ec49 MD |
291 | case 37: return I387_FCTRL_REGNUM (tdep); |
292 | case 38: return I387_FSTAT_REGNUM (tdep); | |
293 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
294 | case 40: return I386_ES_REGNUM; |
295 | case 41: return I386_CS_REGNUM; | |
296 | case 42: return I386_SS_REGNUM; | |
297 | case 43: return I386_DS_REGNUM; | |
298 | case 44: return I386_FS_REGNUM; | |
299 | case 45: return I386_GS_REGNUM; | |
300 | } | |
301 | ||
85540d8c | 302 | /* This will hopefully provoke a warning. */ |
d3f73121 | 303 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 304 | } |
5716833c | 305 | |
fc338970 | 306 | \f |
917317f4 | 307 | |
fc338970 MK |
308 | /* This is the variable that is set with "set disassembly-flavor", and |
309 | its legitimate values. */ | |
53904c9e AC |
310 | static const char att_flavor[] = "att"; |
311 | static const char intel_flavor[] = "intel"; | |
312 | static const char *valid_flavors[] = | |
c5aa993b | 313 | { |
c906108c SS |
314 | att_flavor, |
315 | intel_flavor, | |
316 | NULL | |
317 | }; | |
53904c9e | 318 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 319 | \f |
c906108c | 320 | |
acd5c798 MK |
321 | /* Use the program counter to determine the contents and size of a |
322 | breakpoint instruction. Return a pointer to a string of bytes that | |
323 | encode a breakpoint instruction, store the length of the string in | |
324 | *LEN and optionally adjust *PC to point to the correct memory | |
325 | location for inserting the breakpoint. | |
c906108c | 326 | |
acd5c798 MK |
327 | On the i386 we have a single breakpoint that fits in a single byte |
328 | and can be inserted anywhere. | |
c906108c | 329 | |
acd5c798 | 330 | This function is 64-bit safe. */ |
63c0089f MK |
331 | |
332 | static const gdb_byte * | |
67d57894 | 333 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 334 | { |
63c0089f MK |
335 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
336 | ||
acd5c798 MK |
337 | *len = sizeof (break_insn); |
338 | return break_insn; | |
c906108c | 339 | } |
237fc4c9 PA |
340 | \f |
341 | /* Displaced instruction handling. */ | |
342 | ||
1903f0e6 DE |
343 | /* Skip the legacy instruction prefixes in INSN. |
344 | Not all prefixes are valid for any particular insn | |
345 | but we needn't care, the insn will fault if it's invalid. | |
346 | The result is a pointer to the first opcode byte, | |
347 | or NULL if we run off the end of the buffer. */ | |
348 | ||
349 | static gdb_byte * | |
350 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
351 | { | |
352 | gdb_byte *end = insn + max_len; | |
353 | ||
354 | while (insn < end) | |
355 | { | |
356 | switch (*insn) | |
357 | { | |
358 | case DATA_PREFIX_OPCODE: | |
359 | case ADDR_PREFIX_OPCODE: | |
360 | case CS_PREFIX_OPCODE: | |
361 | case DS_PREFIX_OPCODE: | |
362 | case ES_PREFIX_OPCODE: | |
363 | case FS_PREFIX_OPCODE: | |
364 | case GS_PREFIX_OPCODE: | |
365 | case SS_PREFIX_OPCODE: | |
366 | case LOCK_PREFIX_OPCODE: | |
367 | case REPE_PREFIX_OPCODE: | |
368 | case REPNE_PREFIX_OPCODE: | |
369 | ++insn; | |
370 | continue; | |
371 | default: | |
372 | return insn; | |
373 | } | |
374 | } | |
375 | ||
376 | return NULL; | |
377 | } | |
237fc4c9 PA |
378 | |
379 | static int | |
1903f0e6 | 380 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
381 | { |
382 | /* jmp far (absolute address in operand) */ | |
383 | if (insn[0] == 0xea) | |
384 | return 1; | |
385 | ||
386 | if (insn[0] == 0xff) | |
387 | { | |
388 | /* jump near, absolute indirect (/4) */ | |
389 | if ((insn[1] & 0x38) == 0x20) | |
390 | return 1; | |
391 | ||
392 | /* jump far, absolute indirect (/5) */ | |
393 | if ((insn[1] & 0x38) == 0x28) | |
394 | return 1; | |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | static int | |
1903f0e6 | 401 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
402 | { |
403 | /* call far, absolute */ | |
404 | if (insn[0] == 0x9a) | |
405 | return 1; | |
406 | ||
407 | if (insn[0] == 0xff) | |
408 | { | |
409 | /* Call near, absolute indirect (/2) */ | |
410 | if ((insn[1] & 0x38) == 0x10) | |
411 | return 1; | |
412 | ||
413 | /* Call far, absolute indirect (/3) */ | |
414 | if ((insn[1] & 0x38) == 0x18) | |
415 | return 1; | |
416 | } | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | static int | |
1903f0e6 | 422 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
423 | { |
424 | switch (insn[0]) | |
425 | { | |
426 | case 0xc2: /* ret near, pop N bytes */ | |
427 | case 0xc3: /* ret near */ | |
428 | case 0xca: /* ret far, pop N bytes */ | |
429 | case 0xcb: /* ret far */ | |
430 | case 0xcf: /* iret */ | |
431 | return 1; | |
432 | ||
433 | default: | |
434 | return 0; | |
435 | } | |
436 | } | |
437 | ||
438 | static int | |
1903f0e6 | 439 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
440 | { |
441 | if (i386_absolute_call_p (insn)) | |
442 | return 1; | |
443 | ||
444 | /* call near, relative */ | |
445 | if (insn[0] == 0xe8) | |
446 | return 1; | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
237fc4c9 PA |
451 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
452 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 453 | |
237fc4c9 | 454 | static int |
1903f0e6 | 455 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
456 | { |
457 | if (insn[0] == 0xcd) | |
458 | { | |
459 | *lengthp = 2; | |
460 | return 1; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | /* Fix up the state of registers and memory after having single-stepped | |
467 | a displaced instruction. */ | |
1903f0e6 | 468 | |
237fc4c9 PA |
469 | void |
470 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
471 | struct displaced_step_closure *closure, | |
472 | CORE_ADDR from, CORE_ADDR to, | |
473 | struct regcache *regs) | |
474 | { | |
e17a4113 UW |
475 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
476 | ||
237fc4c9 PA |
477 | /* The offset we applied to the instruction's address. |
478 | This could well be negative (when viewed as a signed 32-bit | |
479 | value), but ULONGEST won't reflect that, so take care when | |
480 | applying it. */ | |
481 | ULONGEST insn_offset = to - from; | |
482 | ||
483 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
484 | copy of the instruction. */ | |
485 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
486 | /* The start of the insn, needed in case we see some prefixes. */ |
487 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
488 | |
489 | if (debug_displaced) | |
490 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 491 | "displaced: fixup (%s, %s), " |
237fc4c9 | 492 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
493 | paddress (gdbarch, from), paddress (gdbarch, to), |
494 | insn[0], insn[1]); | |
237fc4c9 PA |
495 | |
496 | /* The list of issues to contend with here is taken from | |
497 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
498 | Yay for Free Software! */ | |
499 | ||
500 | /* Relocate the %eip, if necessary. */ | |
501 | ||
1903f0e6 DE |
502 | /* The instruction recognizers we use assume any leading prefixes |
503 | have been skipped. */ | |
504 | { | |
505 | /* This is the size of the buffer in closure. */ | |
506 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
507 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
508 | /* If there are too many prefixes, just ignore the insn. | |
509 | It will fault when run. */ | |
510 | if (opcode != NULL) | |
511 | insn = opcode; | |
512 | } | |
513 | ||
237fc4c9 PA |
514 | /* Except in the case of absolute or indirect jump or call |
515 | instructions, or a return instruction, the new eip is relative to | |
516 | the displaced instruction; make it relative. Well, signal | |
517 | handler returns don't need relocation either, but we use the | |
518 | value of %eip to recognize those; see below. */ | |
519 | if (! i386_absolute_jmp_p (insn) | |
520 | && ! i386_absolute_call_p (insn) | |
521 | && ! i386_ret_p (insn)) | |
522 | { | |
523 | ULONGEST orig_eip; | |
524 | ULONGEST insn_len; | |
525 | ||
526 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
527 | ||
528 | /* A signal trampoline system call changes the %eip, resuming | |
529 | execution of the main program after the signal handler has | |
530 | returned. That makes them like 'return' instructions; we | |
531 | shouldn't relocate %eip. | |
532 | ||
533 | But most system calls don't, and we do need to relocate %eip. | |
534 | ||
535 | Our heuristic for distinguishing these cases: if stepping | |
536 | over the system call instruction left control directly after | |
537 | the instruction, the we relocate --- control almost certainly | |
538 | doesn't belong in the displaced copy. Otherwise, we assume | |
539 | the instruction has put control where it belongs, and leave | |
540 | it unrelocated. Goodness help us if there are PC-relative | |
541 | system calls. */ | |
542 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 543 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
544 | { |
545 | if (debug_displaced) | |
546 | fprintf_unfiltered (gdb_stdlog, | |
547 | "displaced: syscall changed %%eip; " | |
548 | "not relocating\n"); | |
549 | } | |
550 | else | |
551 | { | |
552 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
553 | ||
1903f0e6 DE |
554 | /* If we just stepped over a breakpoint insn, we don't backup |
555 | the pc on purpose; this is to match behaviour without | |
556 | stepping. */ | |
237fc4c9 PA |
557 | |
558 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
559 | ||
560 | if (debug_displaced) | |
561 | fprintf_unfiltered (gdb_stdlog, | |
562 | "displaced: " | |
5af949e3 UW |
563 | "relocated %%eip from %s to %s\n", |
564 | paddress (gdbarch, orig_eip), | |
565 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
566 | } |
567 | } | |
568 | ||
569 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
570 | pushed value, and should be cleared. We'll leave this for later, | |
571 | since GDB already messes up the TF flag when stepping over a | |
572 | pushfl. */ | |
573 | ||
574 | /* If the instruction was a call, the return address now atop the | |
575 | stack is the address following the copied instruction. We need | |
576 | to make it the address following the original instruction. */ | |
577 | if (i386_call_p (insn)) | |
578 | { | |
579 | ULONGEST esp; | |
580 | ULONGEST retaddr; | |
581 | const ULONGEST retaddr_len = 4; | |
582 | ||
583 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 584 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 585 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 586 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
587 | |
588 | if (debug_displaced) | |
589 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
590 | "displaced: relocated return addr at %s to %s\n", |
591 | paddress (gdbarch, esp), | |
592 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
593 | } |
594 | } | |
fc338970 | 595 | \f |
acd5c798 MK |
596 | #ifdef I386_REGNO_TO_SYMMETRY |
597 | #error "The Sequent Symmetry is no longer supported." | |
598 | #endif | |
c906108c | 599 | |
acd5c798 MK |
600 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
601 | and %esp "belong" to the calling function. Therefore these | |
602 | registers should be saved if they're going to be modified. */ | |
c906108c | 603 | |
acd5c798 MK |
604 | /* The maximum number of saved registers. This should include all |
605 | registers mentioned above, and %eip. */ | |
a3386186 | 606 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
607 | |
608 | struct i386_frame_cache | |
c906108c | 609 | { |
acd5c798 MK |
610 | /* Base address. */ |
611 | CORE_ADDR base; | |
772562f8 | 612 | LONGEST sp_offset; |
acd5c798 MK |
613 | CORE_ADDR pc; |
614 | ||
fd13a04a AC |
615 | /* Saved registers. */ |
616 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 617 | CORE_ADDR saved_sp; |
e0c62198 | 618 | int saved_sp_reg; |
acd5c798 MK |
619 | int pc_in_eax; |
620 | ||
621 | /* Stack space reserved for local variables. */ | |
622 | long locals; | |
623 | }; | |
624 | ||
625 | /* Allocate and initialize a frame cache. */ | |
626 | ||
627 | static struct i386_frame_cache * | |
fd13a04a | 628 | i386_alloc_frame_cache (void) |
acd5c798 MK |
629 | { |
630 | struct i386_frame_cache *cache; | |
631 | int i; | |
632 | ||
633 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
634 | ||
635 | /* Base address. */ | |
636 | cache->base = 0; | |
637 | cache->sp_offset = -4; | |
638 | cache->pc = 0; | |
639 | ||
fd13a04a AC |
640 | /* Saved registers. We initialize these to -1 since zero is a valid |
641 | offset (that's where %ebp is supposed to be stored). */ | |
642 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
643 | cache->saved_regs[i] = -1; | |
acd5c798 | 644 | cache->saved_sp = 0; |
e0c62198 | 645 | cache->saved_sp_reg = -1; |
acd5c798 MK |
646 | cache->pc_in_eax = 0; |
647 | ||
648 | /* Frameless until proven otherwise. */ | |
649 | cache->locals = -1; | |
650 | ||
651 | return cache; | |
652 | } | |
c906108c | 653 | |
acd5c798 MK |
654 | /* If the instruction at PC is a jump, return the address of its |
655 | target. Otherwise, return PC. */ | |
c906108c | 656 | |
acd5c798 | 657 | static CORE_ADDR |
e17a4113 | 658 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 659 | { |
e17a4113 | 660 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 661 | gdb_byte op; |
acd5c798 MK |
662 | long delta = 0; |
663 | int data16 = 0; | |
c906108c | 664 | |
8defab1a | 665 | target_read_memory (pc, &op, 1); |
acd5c798 | 666 | if (op == 0x66) |
c906108c | 667 | { |
c906108c | 668 | data16 = 1; |
e17a4113 | 669 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
670 | } |
671 | ||
acd5c798 | 672 | switch (op) |
c906108c SS |
673 | { |
674 | case 0xe9: | |
fc338970 | 675 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
676 | if (data16) |
677 | { | |
e17a4113 | 678 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 679 | |
fc338970 MK |
680 | /* Include the size of the jmp instruction (including the |
681 | 0x66 prefix). */ | |
acd5c798 | 682 | delta += 4; |
c906108c SS |
683 | } |
684 | else | |
685 | { | |
e17a4113 | 686 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 687 | |
acd5c798 MK |
688 | /* Include the size of the jmp instruction. */ |
689 | delta += 5; | |
c906108c SS |
690 | } |
691 | break; | |
692 | case 0xeb: | |
fc338970 | 693 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 694 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 695 | |
acd5c798 | 696 | delta += data16 + 2; |
c906108c SS |
697 | break; |
698 | } | |
c906108c | 699 | |
acd5c798 MK |
700 | return pc + delta; |
701 | } | |
fc338970 | 702 | |
acd5c798 MK |
703 | /* Check whether PC points at a prologue for a function returning a |
704 | structure or union. If so, it updates CACHE and returns the | |
705 | address of the first instruction after the code sequence that | |
706 | removes the "hidden" argument from the stack or CURRENT_PC, | |
707 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 708 | |
acd5c798 MK |
709 | static CORE_ADDR |
710 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
711 | struct i386_frame_cache *cache) | |
c906108c | 712 | { |
acd5c798 MK |
713 | /* Functions that return a structure or union start with: |
714 | ||
715 | popl %eax 0x58 | |
716 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
717 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
718 | ||
719 | (the System V compiler puts out the second `xchg' instruction, | |
720 | and the assembler doesn't try to optimize it, so the 'sib' form | |
721 | gets generated). This sequence is used to get the address of the | |
722 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
723 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
724 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
725 | gdb_byte buf[4]; | |
726 | gdb_byte op; | |
c906108c | 727 | |
acd5c798 MK |
728 | if (current_pc <= pc) |
729 | return pc; | |
730 | ||
8defab1a | 731 | target_read_memory (pc, &op, 1); |
c906108c | 732 | |
acd5c798 MK |
733 | if (op != 0x58) /* popl %eax */ |
734 | return pc; | |
c906108c | 735 | |
8defab1a | 736 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
737 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
738 | return pc; | |
c906108c | 739 | |
acd5c798 | 740 | if (current_pc == pc) |
c906108c | 741 | { |
acd5c798 MK |
742 | cache->sp_offset += 4; |
743 | return current_pc; | |
c906108c SS |
744 | } |
745 | ||
acd5c798 | 746 | if (current_pc == pc + 1) |
c906108c | 747 | { |
acd5c798 MK |
748 | cache->pc_in_eax = 1; |
749 | return current_pc; | |
750 | } | |
751 | ||
752 | if (buf[1] == proto1[1]) | |
753 | return pc + 4; | |
754 | else | |
755 | return pc + 5; | |
756 | } | |
757 | ||
758 | static CORE_ADDR | |
759 | i386_skip_probe (CORE_ADDR pc) | |
760 | { | |
761 | /* A function may start with | |
fc338970 | 762 | |
acd5c798 MK |
763 | pushl constant |
764 | call _probe | |
765 | addl $4, %esp | |
fc338970 | 766 | |
acd5c798 MK |
767 | followed by |
768 | ||
769 | pushl %ebp | |
fc338970 | 770 | |
acd5c798 | 771 | etc. */ |
63c0089f MK |
772 | gdb_byte buf[8]; |
773 | gdb_byte op; | |
fc338970 | 774 | |
8defab1a | 775 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
776 | |
777 | if (op == 0x68 || op == 0x6a) | |
778 | { | |
779 | int delta; | |
c906108c | 780 | |
acd5c798 MK |
781 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
782 | four-byte operand, depending on the opcode. */ | |
c906108c | 783 | if (op == 0x68) |
acd5c798 | 784 | delta = 5; |
c906108c | 785 | else |
acd5c798 | 786 | delta = 2; |
c906108c | 787 | |
acd5c798 MK |
788 | /* Read the following 8 bytes, which should be `call _probe' (6 |
789 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
790 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 791 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 792 | pc += delta + sizeof (buf); |
c906108c SS |
793 | } |
794 | ||
acd5c798 MK |
795 | return pc; |
796 | } | |
797 | ||
92dd43fa MK |
798 | /* GCC 4.1 and later, can put code in the prologue to realign the |
799 | stack pointer. Check whether PC points to such code, and update | |
800 | CACHE accordingly. Return the first instruction after the code | |
801 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
802 | recognize the code, return PC. */ | |
803 | ||
804 | static CORE_ADDR | |
805 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
806 | struct i386_frame_cache *cache) | |
807 | { | |
e0c62198 L |
808 | /* There are 2 code sequences to re-align stack before the frame |
809 | gets set up: | |
810 | ||
811 | 1. Use a caller-saved saved register: | |
812 | ||
813 | leal 4(%esp), %reg | |
814 | andl $-XXX, %esp | |
815 | pushl -4(%reg) | |
816 | ||
817 | 2. Use a callee-saved saved register: | |
818 | ||
819 | pushl %reg | |
820 | leal 8(%esp), %reg | |
821 | andl $-XXX, %esp | |
822 | pushl -4(%reg) | |
823 | ||
824 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
825 | ||
826 | 0x83 0xe4 0xf0 andl $-16, %esp | |
827 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
828 | */ | |
829 | ||
830 | gdb_byte buf[14]; | |
831 | int reg; | |
832 | int offset, offset_and; | |
833 | static int regnums[8] = { | |
834 | I386_EAX_REGNUM, /* %eax */ | |
835 | I386_ECX_REGNUM, /* %ecx */ | |
836 | I386_EDX_REGNUM, /* %edx */ | |
837 | I386_EBX_REGNUM, /* %ebx */ | |
838 | I386_ESP_REGNUM, /* %esp */ | |
839 | I386_EBP_REGNUM, /* %ebp */ | |
840 | I386_ESI_REGNUM, /* %esi */ | |
841 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 842 | }; |
92dd43fa | 843 | |
e0c62198 L |
844 | if (target_read_memory (pc, buf, sizeof buf)) |
845 | return pc; | |
846 | ||
847 | /* Check caller-saved saved register. The first instruction has | |
848 | to be "leal 4(%esp), %reg". */ | |
849 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
850 | { | |
851 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
852 | if ((buf[1] & 0xc7) != 0x44) | |
853 | return pc; | |
854 | ||
855 | /* REG has register number. */ | |
856 | reg = (buf[1] >> 3) & 7; | |
857 | offset = 4; | |
858 | } | |
859 | else | |
860 | { | |
861 | /* Check callee-saved saved register. The first instruction | |
862 | has to be "pushl %reg". */ | |
863 | if ((buf[0] & 0xf8) != 0x50) | |
864 | return pc; | |
865 | ||
866 | /* Get register. */ | |
867 | reg = buf[0] & 0x7; | |
868 | ||
869 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
870 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
871 | return pc; | |
872 | ||
873 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
874 | if ((buf[2] & 0xc7) != 0x44) | |
875 | return pc; | |
876 | ||
877 | /* REG has register number. Registers in pushl and leal have to | |
878 | be the same. */ | |
879 | if (reg != ((buf[2] >> 3) & 7)) | |
880 | return pc; | |
881 | ||
882 | offset = 5; | |
883 | } | |
884 | ||
885 | /* Rigister can't be %esp nor %ebp. */ | |
886 | if (reg == 4 || reg == 5) | |
887 | return pc; | |
888 | ||
889 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
890 | if (buf[offset + 1] != 0xe4 | |
891 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
892 | return pc; | |
893 | ||
894 | offset_and = offset; | |
895 | offset += buf[offset] == 0x81 ? 6 : 3; | |
896 | ||
897 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
898 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
899 | if (buf[offset] != 0xff | |
900 | || buf[offset + 2] != 0xfc | |
901 | || (buf[offset + 1] & 0xf8) != 0x70) | |
902 | return pc; | |
903 | ||
904 | /* R/M has register. Registers in leal and pushl have to be the | |
905 | same. */ | |
906 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
907 | return pc; |
908 | ||
e0c62198 L |
909 | if (current_pc > pc + offset_and) |
910 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 911 | |
e0c62198 | 912 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
913 | } |
914 | ||
37bdc87e | 915 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 916 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
917 | |
918 | /* Instruction description. */ | |
919 | struct i386_insn | |
920 | { | |
921 | size_t len; | |
237fc4c9 PA |
922 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
923 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
924 | }; |
925 | ||
926 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
927 | the first instruction description that matches. Otherwise, return | |
928 | NULL. */ | |
929 | ||
930 | static struct i386_insn * | |
931 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
932 | { | |
933 | struct i386_insn *insn; | |
63c0089f | 934 | gdb_byte op; |
37bdc87e | 935 | |
8defab1a | 936 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
937 | |
938 | for (insn = skip_insns; insn->len > 0; insn++) | |
939 | { | |
940 | if ((op & insn->mask[0]) == insn->insn[0]) | |
941 | { | |
237fc4c9 | 942 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 943 | int insn_matched = 1; |
37bdc87e MK |
944 | size_t i; |
945 | ||
946 | gdb_assert (insn->len > 1); | |
237fc4c9 | 947 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 948 | |
8defab1a | 949 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
950 | for (i = 1; i < insn->len; i++) |
951 | { | |
952 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 953 | insn_matched = 0; |
37bdc87e | 954 | } |
613e8135 MK |
955 | |
956 | if (insn_matched) | |
957 | return insn; | |
37bdc87e MK |
958 | } |
959 | } | |
960 | ||
961 | return NULL; | |
962 | } | |
963 | ||
964 | /* Some special instructions that might be migrated by GCC into the | |
965 | part of the prologue that sets up the new stack frame. Because the | |
966 | stack frame hasn't been setup yet, no registers have been saved | |
967 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
968 | touched. */ | |
969 | ||
970 | struct i386_insn i386_frame_setup_skip_insns[] = | |
971 | { | |
972 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
973 | ||
974 | ??? Should we handle 16-bit operand-sizes here? */ | |
975 | ||
976 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
977 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
978 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
979 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
980 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
981 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
982 | { 5, { 0xb8 }, { 0xfe } }, | |
983 | /* `movl imm32, %edx' */ | |
984 | { 5, { 0xba }, { 0xff } }, | |
985 | ||
986 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
987 | encoding for `mov m32, %eax'. | |
988 | ||
989 | ??? Should we handle SIB adressing here? | |
990 | ??? Should we handle 16-bit operand-sizes here? */ | |
991 | ||
992 | /* `movl m32, %eax' */ | |
993 | { 5, { 0xa1 }, { 0xff } }, | |
994 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
995 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
996 | /* `movl m32, %edx' */ | |
997 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
998 | ||
999 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1000 | Because of the symmetry, there are actually two ways to encode | |
1001 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1002 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1003 | ||
1004 | /* `subl %eax, %eax' */ | |
1005 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1006 | /* `subl %ecx, %ecx' */ | |
1007 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1008 | /* `subl %edx, %edx' */ | |
1009 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1010 | /* `xorl %eax, %eax' */ | |
1011 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1012 | /* `xorl %ecx, %ecx' */ | |
1013 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1014 | /* `xorl %edx, %edx' */ | |
1015 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1016 | { 0 } | |
1017 | }; | |
1018 | ||
e11481da PM |
1019 | |
1020 | /* Check whether PC points to a no-op instruction. */ | |
1021 | static CORE_ADDR | |
1022 | i386_skip_noop (CORE_ADDR pc) | |
1023 | { | |
1024 | gdb_byte op; | |
1025 | int check = 1; | |
1026 | ||
8defab1a | 1027 | target_read_memory (pc, &op, 1); |
e11481da PM |
1028 | |
1029 | while (check) | |
1030 | { | |
1031 | check = 0; | |
1032 | /* Ignore `nop' instruction. */ | |
1033 | if (op == 0x90) | |
1034 | { | |
1035 | pc += 1; | |
8defab1a | 1036 | target_read_memory (pc, &op, 1); |
e11481da PM |
1037 | check = 1; |
1038 | } | |
1039 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1040 | Microsoft system dlls often start with | |
1041 | a `mov %edi,%edi' instruction. | |
1042 | The 5 bytes before the function start are | |
1043 | filled with `nop' instructions. | |
1044 | This pattern can be used for hot-patching: | |
1045 | The `mov %edi, %edi' instruction can be replaced by a | |
1046 | near jump to the location of the 5 `nop' instructions | |
1047 | which can be replaced by a 32-bit jump to anywhere | |
1048 | in the 32-bit address space. */ | |
1049 | ||
1050 | else if (op == 0x8b) | |
1051 | { | |
8defab1a | 1052 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
1053 | if (op == 0xff) |
1054 | { | |
1055 | pc += 2; | |
8defab1a | 1056 | target_read_memory (pc, &op, 1); |
e11481da PM |
1057 | check = 1; |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | return pc; | |
1062 | } | |
1063 | ||
acd5c798 MK |
1064 | /* Check whether PC points at a code that sets up a new stack frame. |
1065 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1066 | instruction after the sequence that sets up the frame or LIMIT, |
1067 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1068 | |
1069 | static CORE_ADDR | |
e17a4113 UW |
1070 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1071 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1072 | struct i386_frame_cache *cache) |
1073 | { | |
e17a4113 | 1074 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1075 | struct i386_insn *insn; |
63c0089f | 1076 | gdb_byte op; |
26604a34 | 1077 | int skip = 0; |
acd5c798 | 1078 | |
37bdc87e MK |
1079 | if (limit <= pc) |
1080 | return limit; | |
acd5c798 | 1081 | |
8defab1a | 1082 | target_read_memory (pc, &op, 1); |
acd5c798 | 1083 | |
c906108c | 1084 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1085 | { |
acd5c798 MK |
1086 | /* Take into account that we've executed the `pushl %ebp' that |
1087 | starts this instruction sequence. */ | |
fd13a04a | 1088 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1089 | cache->sp_offset += 4; |
37bdc87e | 1090 | pc++; |
acd5c798 MK |
1091 | |
1092 | /* If that's all, return now. */ | |
37bdc87e MK |
1093 | if (limit <= pc) |
1094 | return limit; | |
26604a34 | 1095 | |
b4632131 | 1096 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1097 | GCC into the prologue and skip them. At this point in the |
1098 | prologue, code should only touch the scratch registers %eax, | |
1099 | %ecx and %edx, so while the number of posibilities is sheer, | |
1100 | it is limited. | |
5daa5b4e | 1101 | |
26604a34 MK |
1102 | Make sure we only skip these instructions if we later see the |
1103 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1104 | while (pc + skip < limit) |
26604a34 | 1105 | { |
37bdc87e MK |
1106 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1107 | if (insn == NULL) | |
1108 | break; | |
b4632131 | 1109 | |
37bdc87e | 1110 | skip += insn->len; |
26604a34 MK |
1111 | } |
1112 | ||
37bdc87e MK |
1113 | /* If that's all, return now. */ |
1114 | if (limit <= pc + skip) | |
1115 | return limit; | |
1116 | ||
8defab1a | 1117 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1118 | |
26604a34 | 1119 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1120 | switch (op) |
c906108c SS |
1121 | { |
1122 | case 0x8b: | |
e17a4113 UW |
1123 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1124 | != 0xec) | |
37bdc87e | 1125 | return pc; |
c906108c SS |
1126 | break; |
1127 | case 0x89: | |
e17a4113 UW |
1128 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1129 | != 0xe5) | |
37bdc87e | 1130 | return pc; |
c906108c SS |
1131 | break; |
1132 | default: | |
37bdc87e | 1133 | return pc; |
c906108c | 1134 | } |
acd5c798 | 1135 | |
26604a34 MK |
1136 | /* OK, we actually have a frame. We just don't know how large |
1137 | it is yet. Set its size to zero. We'll adjust it if | |
1138 | necessary. We also now commit to skipping the special | |
1139 | instructions mentioned before. */ | |
acd5c798 | 1140 | cache->locals = 0; |
37bdc87e | 1141 | pc += (skip + 2); |
acd5c798 MK |
1142 | |
1143 | /* If that's all, return now. */ | |
37bdc87e MK |
1144 | if (limit <= pc) |
1145 | return limit; | |
acd5c798 | 1146 | |
fc338970 MK |
1147 | /* Check for stack adjustment |
1148 | ||
acd5c798 | 1149 | subl $XXX, %esp |
fc338970 | 1150 | |
fd35795f | 1151 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1152 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1153 | target_read_memory (pc, &op, 1); |
c906108c SS |
1154 | if (op == 0x83) |
1155 | { | |
fd35795f | 1156 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1157 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1158 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1159 | return pc; |
acd5c798 | 1160 | |
37bdc87e MK |
1161 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1162 | make sense to be negative). */ | |
e17a4113 | 1163 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1164 | return pc + 3; |
c906108c SS |
1165 | } |
1166 | else if (op == 0x81) | |
1167 | { | |
fd35795f | 1168 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1169 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1170 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1171 | return pc; |
acd5c798 | 1172 | |
fd35795f | 1173 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1174 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1175 | return pc + 6; |
c906108c SS |
1176 | } |
1177 | else | |
1178 | { | |
acd5c798 | 1179 | /* Some instruction other than `subl'. */ |
37bdc87e | 1180 | return pc; |
c906108c SS |
1181 | } |
1182 | } | |
37bdc87e | 1183 | else if (op == 0xc8) /* enter */ |
c906108c | 1184 | { |
e17a4113 | 1185 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1186 | return pc + 4; |
c906108c | 1187 | } |
21d0e8a4 | 1188 | |
acd5c798 | 1189 | return pc; |
21d0e8a4 MK |
1190 | } |
1191 | ||
acd5c798 MK |
1192 | /* Check whether PC points at code that saves registers on the stack. |
1193 | If so, it updates CACHE and returns the address of the first | |
1194 | instruction after the register saves or CURRENT_PC, whichever is | |
1195 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1196 | |
1197 | static CORE_ADDR | |
acd5c798 MK |
1198 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1199 | struct i386_frame_cache *cache) | |
6bff26de | 1200 | { |
99ab4326 | 1201 | CORE_ADDR offset = 0; |
63c0089f | 1202 | gdb_byte op; |
99ab4326 | 1203 | int i; |
c0d1d883 | 1204 | |
99ab4326 MK |
1205 | if (cache->locals > 0) |
1206 | offset -= cache->locals; | |
1207 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1208 | { | |
8defab1a | 1209 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1210 | if (op < 0x50 || op > 0x57) |
1211 | break; | |
0d17c81d | 1212 | |
99ab4326 MK |
1213 | offset -= 4; |
1214 | cache->saved_regs[op - 0x50] = offset; | |
1215 | cache->sp_offset += 4; | |
1216 | pc++; | |
6bff26de MK |
1217 | } |
1218 | ||
acd5c798 | 1219 | return pc; |
22797942 AC |
1220 | } |
1221 | ||
acd5c798 MK |
1222 | /* Do a full analysis of the prologue at PC and update CACHE |
1223 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1224 | address where the analysis stopped. | |
ed84f6c1 | 1225 | |
fc338970 MK |
1226 | We handle these cases: |
1227 | ||
1228 | The startup sequence can be at the start of the function, or the | |
1229 | function can start with a branch to startup code at the end. | |
1230 | ||
1231 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1232 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1233 | once used in the System V compiler). | |
1234 | ||
1235 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1236 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1237 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1238 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1239 | |
1240 | Next, the registers used by this function are pushed. With the | |
1241 | System V compiler they will always be in the order: %edi, %esi, | |
1242 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1243 | restore %eax); however, the code below is willing to see the pushes | |
1244 | in any order, and will handle up to 8 of them. | |
1245 | ||
1246 | If the setup sequence is at the end of the function, then the next | |
1247 | instruction will be a branch back to the start. */ | |
c906108c | 1248 | |
acd5c798 | 1249 | static CORE_ADDR |
e17a4113 UW |
1250 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1251 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1252 | struct i386_frame_cache *cache) |
c906108c | 1253 | { |
e11481da | 1254 | pc = i386_skip_noop (pc); |
e17a4113 | 1255 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1256 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1257 | pc = i386_skip_probe (pc); | |
92dd43fa | 1258 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1259 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1260 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1261 | } |
1262 | ||
fc338970 | 1263 | /* Return PC of first real instruction. */ |
c906108c | 1264 | |
3a1e71e3 | 1265 | static CORE_ADDR |
6093d2eb | 1266 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1267 | { |
e17a4113 UW |
1268 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1269 | ||
63c0089f | 1270 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1271 | { |
1272 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1273 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1274 | }; |
acd5c798 MK |
1275 | struct i386_frame_cache cache; |
1276 | CORE_ADDR pc; | |
63c0089f | 1277 | gdb_byte op; |
acd5c798 | 1278 | int i; |
c5aa993b | 1279 | |
acd5c798 | 1280 | cache.locals = -1; |
e17a4113 | 1281 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1282 | if (cache.locals < 0) |
1283 | return start_pc; | |
c5aa993b | 1284 | |
acd5c798 | 1285 | /* Found valid frame setup. */ |
c906108c | 1286 | |
fc338970 MK |
1287 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1288 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1289 | %ebx: |
1290 | ||
fc338970 MK |
1291 | call 0x0 |
1292 | popl %ebx | |
1293 | movl %ebx,x(%ebp) (optional) | |
1294 | addl y,%ebx | |
1295 | ||
c906108c SS |
1296 | This code is with the rest of the prologue (at the end of the |
1297 | function), so we have to skip it to get to the first real | |
1298 | instruction at the start of the function. */ | |
c5aa993b | 1299 | |
c906108c SS |
1300 | for (i = 0; i < 6; i++) |
1301 | { | |
8defab1a | 1302 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1303 | if (pic_pat[i] != op) |
c906108c SS |
1304 | break; |
1305 | } | |
1306 | if (i == 6) | |
1307 | { | |
acd5c798 MK |
1308 | int delta = 6; |
1309 | ||
8defab1a | 1310 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1311 | |
c5aa993b | 1312 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1313 | { |
e17a4113 | 1314 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1315 | |
fc338970 | 1316 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1317 | delta += 3; |
fc338970 | 1318 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1319 | delta += 6; |
fc338970 | 1320 | else /* Unexpected instruction. */ |
acd5c798 MK |
1321 | delta = 0; |
1322 | ||
8defab1a | 1323 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1324 | } |
acd5c798 | 1325 | |
c5aa993b | 1326 | /* addl y,%ebx */ |
acd5c798 | 1327 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1328 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1329 | == 0xc3) | |
c906108c | 1330 | { |
acd5c798 | 1331 | pc += delta + 6; |
c906108c SS |
1332 | } |
1333 | } | |
c5aa993b | 1334 | |
e63bbc88 MK |
1335 | /* If the function starts with a branch (to startup code at the end) |
1336 | the last instruction should bring us back to the first | |
1337 | instruction of the real code. */ | |
e17a4113 UW |
1338 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1339 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1340 | |
1341 | return pc; | |
c906108c SS |
1342 | } |
1343 | ||
4309257c PM |
1344 | /* Check that the code pointed to by PC corresponds to a call to |
1345 | __main, skip it if so. Return PC otherwise. */ | |
1346 | ||
1347 | CORE_ADDR | |
1348 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1349 | { | |
e17a4113 | 1350 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1351 | gdb_byte op; |
1352 | ||
1353 | target_read_memory (pc, &op, 1); | |
1354 | if (op == 0xe8) | |
1355 | { | |
1356 | gdb_byte buf[4]; | |
1357 | ||
1358 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1359 | { | |
1360 | /* Make sure address is computed correctly as a 32bit | |
1361 | integer even if CORE_ADDR is 64 bit wide. */ | |
1362 | struct minimal_symbol *s; | |
e17a4113 | 1363 | CORE_ADDR call_dest; |
4309257c | 1364 | |
e17a4113 | 1365 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1366 | call_dest = call_dest & 0xffffffffU; |
1367 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1368 | if (s != NULL | |
1369 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1370 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1371 | pc += 5; | |
1372 | } | |
1373 | } | |
1374 | ||
1375 | return pc; | |
1376 | } | |
1377 | ||
acd5c798 | 1378 | /* This function is 64-bit safe. */ |
93924b6b | 1379 | |
acd5c798 MK |
1380 | static CORE_ADDR |
1381 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1382 | { |
63c0089f | 1383 | gdb_byte buf[8]; |
acd5c798 | 1384 | |
875f8d0e | 1385 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1386 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1387 | } |
acd5c798 | 1388 | \f |
93924b6b | 1389 | |
acd5c798 | 1390 | /* Normal frames. */ |
c5aa993b | 1391 | |
acd5c798 | 1392 | static struct i386_frame_cache * |
10458914 | 1393 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1394 | { |
e17a4113 UW |
1395 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1396 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1397 | struct i386_frame_cache *cache; |
63c0089f | 1398 | gdb_byte buf[4]; |
acd5c798 MK |
1399 | int i; |
1400 | ||
1401 | if (*this_cache) | |
1402 | return *this_cache; | |
1403 | ||
fd13a04a | 1404 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1405 | *this_cache = cache; |
1406 | ||
1407 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1408 | which holds the base address for the current stack frame. | |
1409 | However, for functions that don't need it, the frame pointer is | |
1410 | optional. For these "frameless" functions the frame pointer is | |
1411 | actually the frame pointer of the calling frame. Signal | |
1412 | trampolines are just a special case of a "frameless" function. | |
1413 | They (usually) share their frame pointer with the frame that was | |
1414 | in progress when the signal occurred. */ | |
1415 | ||
10458914 | 1416 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1417 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 MK |
1418 | if (cache->base == 0) |
1419 | return cache; | |
1420 | ||
1421 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1422 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1423 | |
10458914 | 1424 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1425 | if (cache->pc != 0) |
e17a4113 UW |
1426 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1427 | cache); | |
acd5c798 | 1428 | |
e0c62198 | 1429 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1430 | { |
e0c62198 L |
1431 | /* Saved stack pointer has been saved. */ |
1432 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
e17a4113 | 1433 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
92dd43fa MK |
1434 | } |
1435 | ||
acd5c798 MK |
1436 | if (cache->locals < 0) |
1437 | { | |
1438 | /* We didn't find a valid frame, which means that CACHE->base | |
1439 | currently holds the frame pointer for our calling frame. If | |
1440 | we're at the start of a function, or somewhere half-way its | |
1441 | prologue, the function's frame probably hasn't been fully | |
1442 | setup yet. Try to reconstruct the base address for the stack | |
1443 | frame by looking at the stack pointer. For truly "frameless" | |
1444 | functions this might work too. */ | |
1445 | ||
e0c62198 | 1446 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1447 | { |
1448 | /* We're halfway aligning the stack. */ | |
1449 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1450 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1451 | ||
1452 | /* This will be added back below. */ | |
1453 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1454 | } | |
7618e12b DJ |
1455 | else if (cache->pc != 0 |
1456 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1457 | { |
7618e12b DJ |
1458 | /* We're in a known function, but did not find a frame |
1459 | setup. Assume that the function does not use %ebp. | |
1460 | Alternatively, we may have jumped to an invalid | |
1461 | address; in that case there is definitely no new | |
1462 | frame in %ebp. */ | |
10458914 | 1463 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1464 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1465 | + cache->sp_offset; | |
92dd43fa | 1466 | } |
7618e12b DJ |
1467 | else |
1468 | /* We're in an unknown function. We could not find the start | |
1469 | of the function to analyze the prologue; our best option is | |
1470 | to assume a typical frame layout with the caller's %ebp | |
1471 | saved. */ | |
1472 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1473 | } |
1474 | ||
1475 | /* Now that we have the base address for the stack frame we can | |
1476 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1477 | if (cache->saved_sp == 0) |
1478 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1479 | |
acd5c798 MK |
1480 | /* Adjust all the saved registers such that they contain addresses |
1481 | instead of offsets. */ | |
1482 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1483 | if (cache->saved_regs[i] != -1) |
1484 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1485 | |
1486 | return cache; | |
a7769679 MK |
1487 | } |
1488 | ||
3a1e71e3 | 1489 | static void |
10458914 | 1490 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1491 | struct frame_id *this_id) |
c906108c | 1492 | { |
10458914 | 1493 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1494 | |
1495 | /* This marks the outermost frame. */ | |
1496 | if (cache->base == 0) | |
1497 | return; | |
1498 | ||
3e210248 | 1499 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1500 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1501 | } | |
1502 | ||
10458914 DJ |
1503 | static struct value * |
1504 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1505 | int regnum) | |
acd5c798 | 1506 | { |
10458914 | 1507 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1508 | |
1509 | gdb_assert (regnum >= 0); | |
1510 | ||
1511 | /* The System V ABI says that: | |
1512 | ||
1513 | "The flags register contains the system flags, such as the | |
1514 | direction flag and the carry flag. The direction flag must be | |
1515 | set to the forward (that is, zero) direction before entry and | |
1516 | upon exit from a function. Other user flags have no specified | |
1517 | role in the standard calling sequence and are not preserved." | |
1518 | ||
1519 | To guarantee the "upon exit" part of that statement we fake a | |
1520 | saved flags register that has its direction flag cleared. | |
1521 | ||
1522 | Note that GCC doesn't seem to rely on the fact that the direction | |
1523 | flag is cleared after a function return; it always explicitly | |
1524 | clears the flag before operations where it matters. | |
1525 | ||
1526 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1527 | right thing to do. The way we fake the flags register here makes | |
1528 | it impossible to change it. */ | |
1529 | ||
1530 | if (regnum == I386_EFLAGS_REGNUM) | |
1531 | { | |
10458914 | 1532 | ULONGEST val; |
c5aa993b | 1533 | |
10458914 DJ |
1534 | val = get_frame_register_unsigned (this_frame, regnum); |
1535 | val &= ~(1 << 10); | |
1536 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1537 | } |
1211c4e4 | 1538 | |
acd5c798 | 1539 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1540 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1541 | |
1542 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1543 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1544 | |
fd13a04a | 1545 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1546 | return frame_unwind_got_memory (this_frame, regnum, |
1547 | cache->saved_regs[regnum]); | |
fd13a04a | 1548 | |
10458914 | 1549 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1550 | } |
1551 | ||
1552 | static const struct frame_unwind i386_frame_unwind = | |
1553 | { | |
1554 | NORMAL_FRAME, | |
1555 | i386_frame_this_id, | |
10458914 DJ |
1556 | i386_frame_prev_register, |
1557 | NULL, | |
1558 | default_frame_sniffer | |
acd5c798 | 1559 | }; |
06da04c6 MS |
1560 | |
1561 | /* Normal frames, but in a function epilogue. */ | |
1562 | ||
1563 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1564 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1565 | the function's stack frame. */ | |
1566 | ||
1567 | static int | |
1568 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1569 | { | |
1570 | gdb_byte insn; | |
1571 | ||
1572 | if (target_read_memory (pc, &insn, 1)) | |
1573 | return 0; /* Can't read memory at pc. */ | |
1574 | ||
1575 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1576 | return 0; | |
1577 | ||
1578 | return 1; | |
1579 | } | |
1580 | ||
1581 | static int | |
1582 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1583 | struct frame_info *this_frame, | |
1584 | void **this_prologue_cache) | |
1585 | { | |
1586 | if (frame_relative_level (this_frame) == 0) | |
1587 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1588 | get_frame_pc (this_frame)); | |
1589 | else | |
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | static struct i386_frame_cache * | |
1594 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1595 | { | |
1596 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1597 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1598 | struct i386_frame_cache *cache; | |
1599 | gdb_byte buf[4]; | |
1600 | ||
1601 | if (*this_cache) | |
1602 | return *this_cache; | |
1603 | ||
1604 | cache = i386_alloc_frame_cache (); | |
1605 | *this_cache = cache; | |
1606 | ||
1607 | /* Cache base will be %esp plus cache->sp_offset (-4). */ | |
1608 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); | |
1609 | cache->base = extract_unsigned_integer (buf, 4, | |
1610 | byte_order) + cache->sp_offset; | |
1611 | ||
1612 | /* Cache pc will be the frame func. */ | |
1613 | cache->pc = get_frame_pc (this_frame); | |
1614 | ||
1615 | /* The saved %esp will be at cache->base plus 8. */ | |
1616 | cache->saved_sp = cache->base + 8; | |
1617 | ||
1618 | /* The saved %eip will be at cache->base plus 4. */ | |
1619 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; | |
1620 | ||
1621 | return cache; | |
1622 | } | |
1623 | ||
1624 | static void | |
1625 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1626 | void **this_cache, | |
1627 | struct frame_id *this_id) | |
1628 | { | |
1629 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, | |
1630 | this_cache); | |
1631 | ||
1632 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1633 | } | |
1634 | ||
1635 | static const struct frame_unwind i386_epilogue_frame_unwind = | |
1636 | { | |
1637 | NORMAL_FRAME, | |
1638 | i386_epilogue_frame_this_id, | |
1639 | i386_frame_prev_register, | |
1640 | NULL, | |
1641 | i386_epilogue_frame_sniffer | |
1642 | }; | |
acd5c798 MK |
1643 | \f |
1644 | ||
1645 | /* Signal trampolines. */ | |
1646 | ||
1647 | static struct i386_frame_cache * | |
10458914 | 1648 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1649 | { |
e17a4113 UW |
1650 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1651 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1652 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1653 | struct i386_frame_cache *cache; |
acd5c798 | 1654 | CORE_ADDR addr; |
63c0089f | 1655 | gdb_byte buf[4]; |
acd5c798 MK |
1656 | |
1657 | if (*this_cache) | |
1658 | return *this_cache; | |
1659 | ||
fd13a04a | 1660 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1661 | |
10458914 | 1662 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1663 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
acd5c798 | 1664 | |
10458914 | 1665 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1666 | if (tdep->sc_reg_offset) |
1667 | { | |
1668 | int i; | |
1669 | ||
1670 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1671 | ||
1672 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1673 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1674 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1675 | } |
1676 | else | |
1677 | { | |
fd13a04a AC |
1678 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1679 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1680 | } |
acd5c798 MK |
1681 | |
1682 | *this_cache = cache; | |
1683 | return cache; | |
1684 | } | |
1685 | ||
1686 | static void | |
10458914 | 1687 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1688 | struct frame_id *this_id) |
1689 | { | |
1690 | struct i386_frame_cache *cache = | |
10458914 | 1691 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1692 | |
3e210248 | 1693 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1694 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1695 | } |
1696 | ||
10458914 DJ |
1697 | static struct value * |
1698 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1699 | void **this_cache, int regnum) | |
acd5c798 MK |
1700 | { |
1701 | /* Make sure we've initialized the cache. */ | |
10458914 | 1702 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1703 | |
10458914 | 1704 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1705 | } |
c0d1d883 | 1706 | |
10458914 DJ |
1707 | static int |
1708 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1709 | struct frame_info *this_frame, | |
1710 | void **this_prologue_cache) | |
acd5c798 | 1711 | { |
10458914 | 1712 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1713 | |
911bc6ee MK |
1714 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1715 | handler. */ | |
1716 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1717 | return 0; |
1c3545ae | 1718 | |
911bc6ee MK |
1719 | if (tdep->sigtramp_p != NULL) |
1720 | { | |
10458914 DJ |
1721 | if (tdep->sigtramp_p (this_frame)) |
1722 | return 1; | |
911bc6ee MK |
1723 | } |
1724 | ||
1725 | if (tdep->sigtramp_start != 0) | |
1726 | { | |
10458914 | 1727 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1728 | |
1729 | gdb_assert (tdep->sigtramp_end != 0); | |
1730 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1731 | return 1; |
911bc6ee | 1732 | } |
acd5c798 | 1733 | |
10458914 | 1734 | return 0; |
acd5c798 | 1735 | } |
10458914 DJ |
1736 | |
1737 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1738 | { | |
1739 | SIGTRAMP_FRAME, | |
1740 | i386_sigtramp_frame_this_id, | |
1741 | i386_sigtramp_frame_prev_register, | |
1742 | NULL, | |
1743 | i386_sigtramp_frame_sniffer | |
1744 | }; | |
acd5c798 MK |
1745 | \f |
1746 | ||
1747 | static CORE_ADDR | |
10458914 | 1748 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1749 | { |
10458914 | 1750 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1751 | |
1752 | return cache->base; | |
1753 | } | |
1754 | ||
1755 | static const struct frame_base i386_frame_base = | |
1756 | { | |
1757 | &i386_frame_unwind, | |
1758 | i386_frame_base_address, | |
1759 | i386_frame_base_address, | |
1760 | i386_frame_base_address | |
1761 | }; | |
1762 | ||
acd5c798 | 1763 | static struct frame_id |
10458914 | 1764 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1765 | { |
acd5c798 MK |
1766 | CORE_ADDR fp; |
1767 | ||
10458914 | 1768 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1769 | |
3e210248 | 1770 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1771 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1772 | } |
fc338970 | 1773 | \f |
c906108c | 1774 | |
fc338970 MK |
1775 | /* Figure out where the longjmp will land. Slurp the args out of the |
1776 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1777 | structure from which we extract the address that we will land at. |
28bcfd30 | 1778 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1779 | success. */ |
c906108c | 1780 | |
8201327c | 1781 | static int |
60ade65d | 1782 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1783 | { |
436675d3 | 1784 | gdb_byte buf[4]; |
c906108c | 1785 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 1786 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 1787 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 1788 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 1789 | |
8201327c MK |
1790 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1791 | longjmp will land. */ | |
1792 | if (jb_pc_offset == -1) | |
c906108c SS |
1793 | return 0; |
1794 | ||
436675d3 | 1795 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1796 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1797 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
1798 | return 0; |
1799 | ||
e17a4113 | 1800 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1801 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 1802 | return 0; |
c906108c | 1803 | |
e17a4113 | 1804 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
1805 | return 1; |
1806 | } | |
fc338970 | 1807 | \f |
c906108c | 1808 | |
7ccc1c74 JM |
1809 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1810 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1811 | unions containing such types must be 16-byte-aligned; other | |
1812 | arguments are 4-byte-aligned. */ | |
1813 | ||
1814 | static int | |
1815 | i386_16_byte_align_p (struct type *type) | |
1816 | { | |
1817 | type = check_typedef (type); | |
1818 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1819 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1820 | && TYPE_LENGTH (type) == 16) | |
1821 | return 1; | |
1822 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1823 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1824 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1825 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1826 | { | |
1827 | int i; | |
1828 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1829 | { | |
1830 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1831 | return 1; | |
1832 | } | |
1833 | } | |
1834 | return 0; | |
1835 | } | |
1836 | ||
3a1e71e3 | 1837 | static CORE_ADDR |
7d9b040b | 1838 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1839 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1840 | struct value **args, CORE_ADDR sp, int struct_return, | |
1841 | CORE_ADDR struct_addr) | |
22f8ba57 | 1842 | { |
e17a4113 | 1843 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1844 | gdb_byte buf[4]; |
acd5c798 | 1845 | int i; |
7ccc1c74 JM |
1846 | int write_pass; |
1847 | int args_space = 0; | |
acd5c798 | 1848 | |
7ccc1c74 JM |
1849 | /* Determine the total space required for arguments and struct |
1850 | return address in a first pass (allowing for 16-byte-aligned | |
1851 | arguments), then push arguments in a second pass. */ | |
1852 | ||
1853 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1854 | { |
7ccc1c74 JM |
1855 | int args_space_used = 0; |
1856 | int have_16_byte_aligned_arg = 0; | |
1857 | ||
1858 | if (struct_return) | |
1859 | { | |
1860 | if (write_pass) | |
1861 | { | |
1862 | /* Push value address. */ | |
e17a4113 | 1863 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
1864 | write_memory (sp, buf, 4); |
1865 | args_space_used += 4; | |
1866 | } | |
1867 | else | |
1868 | args_space += 4; | |
1869 | } | |
1870 | ||
1871 | for (i = 0; i < nargs; i++) | |
1872 | { | |
1873 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1874 | |
7ccc1c74 JM |
1875 | if (write_pass) |
1876 | { | |
1877 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1878 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1879 | |
7ccc1c74 JM |
1880 | write_memory (sp + args_space_used, |
1881 | value_contents_all (args[i]), len); | |
1882 | /* The System V ABI says that: | |
acd5c798 | 1883 | |
7ccc1c74 JM |
1884 | "An argument's size is increased, if necessary, to make it a |
1885 | multiple of [32-bit] words. This may require tail padding, | |
1886 | depending on the size of the argument." | |
22f8ba57 | 1887 | |
7ccc1c74 JM |
1888 | This makes sure the stack stays word-aligned. */ |
1889 | args_space_used += align_up (len, 4); | |
1890 | } | |
1891 | else | |
1892 | { | |
1893 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1894 | { | |
1895 | args_space = align_up (args_space, 16); | |
1896 | have_16_byte_aligned_arg = 1; | |
1897 | } | |
1898 | args_space += align_up (len, 4); | |
1899 | } | |
1900 | } | |
1901 | ||
1902 | if (!write_pass) | |
1903 | { | |
1904 | if (have_16_byte_aligned_arg) | |
1905 | args_space = align_up (args_space, 16); | |
1906 | sp -= args_space; | |
1907 | } | |
22f8ba57 MK |
1908 | } |
1909 | ||
acd5c798 MK |
1910 | /* Store return address. */ |
1911 | sp -= 4; | |
e17a4113 | 1912 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
1913 | write_memory (sp, buf, 4); |
1914 | ||
1915 | /* Finally, update the stack pointer... */ | |
e17a4113 | 1916 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
1917 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
1918 | ||
1919 | /* ...and fake a frame pointer. */ | |
1920 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1921 | ||
3e210248 AC |
1922 | /* MarkK wrote: This "+ 8" is all over the place: |
1923 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1924 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1925 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
1926 | definition of the stack address of a frame. Otherwise frame id |
1927 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
1928 | stack address *before* the function call as a frame's CFA. On |
1929 | the i386, when %ebp is used as a frame pointer, the offset | |
1930 | between the contents %ebp and the CFA as defined by GCC. */ | |
1931 | return sp + 8; | |
22f8ba57 MK |
1932 | } |
1933 | ||
1a309862 MK |
1934 | /* These registers are used for returning integers (and on some |
1935 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1936 | size and alignment match an integer type). */ |
acd5c798 MK |
1937 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1938 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1939 | |
c5e656c1 MK |
1940 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1941 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1942 | |
3a1e71e3 | 1943 | static void |
c5e656c1 | 1944 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1945 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1946 | { |
c5e656c1 | 1947 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1948 | int len = TYPE_LENGTH (type); |
63c0089f | 1949 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1950 | |
1e8d0a7b | 1951 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1952 | { |
5716833c | 1953 | if (tdep->st0_regnum < 0) |
1a309862 | 1954 | { |
8a3fe4f8 | 1955 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1956 | memset (valbuf, 0, len); |
ef9dff19 | 1957 | return; |
1a309862 MK |
1958 | } |
1959 | ||
c6ba6f0d MK |
1960 | /* Floating-point return values can be found in %st(0). Convert |
1961 | its contents to the desired type. This is probably not | |
1962 | exactly how it would happen on the target itself, but it is | |
1963 | the best we can do. */ | |
acd5c798 | 1964 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 1965 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
1966 | } |
1967 | else | |
c5aa993b | 1968 | { |
875f8d0e UW |
1969 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1970 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1971 | |
1972 | if (len <= low_size) | |
00f8375e | 1973 | { |
0818c12a | 1974 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1975 | memcpy (valbuf, buf, len); |
1976 | } | |
d4f3574e SS |
1977 | else if (len <= (low_size + high_size)) |
1978 | { | |
0818c12a | 1979 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1980 | memcpy (valbuf, buf, low_size); |
0818c12a | 1981 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1982 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1983 | } |
1984 | else | |
8e65ff28 | 1985 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1986 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1987 | } |
1988 | } | |
1989 | ||
c5e656c1 MK |
1990 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1991 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1992 | |
3a1e71e3 | 1993 | static void |
c5e656c1 | 1994 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1995 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1996 | { |
c5e656c1 | 1997 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1998 | int len = TYPE_LENGTH (type); |
1999 | ||
1e8d0a7b | 2000 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2001 | { |
3d7f4f49 | 2002 | ULONGEST fstat; |
63c0089f | 2003 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2004 | |
5716833c | 2005 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2006 | { |
8a3fe4f8 | 2007 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2008 | return; |
2009 | } | |
2010 | ||
635b0cc1 MK |
2011 | /* Returning floating-point values is a bit tricky. Apart from |
2012 | storing the return value in %st(0), we have to simulate the | |
2013 | state of the FPU at function return point. */ | |
2014 | ||
c6ba6f0d MK |
2015 | /* Convert the value found in VALBUF to the extended |
2016 | floating-point format used by the FPU. This is probably | |
2017 | not exactly how it would happen on the target itself, but | |
2018 | it is the best we can do. */ | |
27067745 | 2019 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2020 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2021 | |
635b0cc1 MK |
2022 | /* Set the top of the floating-point register stack to 7. The |
2023 | actual value doesn't really matter, but 7 is what a normal | |
2024 | function return would end up with if the program started out | |
2025 | with a freshly initialized FPU. */ | |
20a6ec49 | 2026 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2027 | fstat |= (7 << 11); |
20a6ec49 | 2028 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2029 | |
635b0cc1 MK |
2030 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2031 | the floating-point register stack to 7, the appropriate value | |
2032 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2033 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2034 | } |
2035 | else | |
2036 | { | |
875f8d0e UW |
2037 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2038 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2039 | |
2040 | if (len <= low_size) | |
3d7f4f49 | 2041 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2042 | else if (len <= (low_size + high_size)) |
2043 | { | |
3d7f4f49 MK |
2044 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2045 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2046 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2047 | } |
2048 | else | |
8e65ff28 | 2049 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2050 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2051 | } |
2052 | } | |
fc338970 | 2053 | \f |
ef9dff19 | 2054 | |
8201327c MK |
2055 | /* This is the variable that is set with "set struct-convention", and |
2056 | its legitimate values. */ | |
2057 | static const char default_struct_convention[] = "default"; | |
2058 | static const char pcc_struct_convention[] = "pcc"; | |
2059 | static const char reg_struct_convention[] = "reg"; | |
2060 | static const char *valid_conventions[] = | |
2061 | { | |
2062 | default_struct_convention, | |
2063 | pcc_struct_convention, | |
2064 | reg_struct_convention, | |
2065 | NULL | |
2066 | }; | |
2067 | static const char *struct_convention = default_struct_convention; | |
2068 | ||
0e4377e1 JB |
2069 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2070 | a union type, or an array type, should be returned in registers | |
2071 | for architecture GDBARCH. */ | |
c5e656c1 | 2072 | |
8201327c | 2073 | static int |
c5e656c1 | 2074 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2075 | { |
c5e656c1 MK |
2076 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2077 | enum type_code code = TYPE_CODE (type); | |
2078 | int len = TYPE_LENGTH (type); | |
8201327c | 2079 | |
0e4377e1 JB |
2080 | gdb_assert (code == TYPE_CODE_STRUCT |
2081 | || code == TYPE_CODE_UNION | |
2082 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2083 | |
2084 | if (struct_convention == pcc_struct_convention | |
2085 | || (struct_convention == default_struct_convention | |
2086 | && tdep->struct_return == pcc_struct_return)) | |
2087 | return 0; | |
2088 | ||
9edde48e MK |
2089 | /* Structures consisting of a single `float', `double' or 'long |
2090 | double' member are returned in %st(0). */ | |
2091 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2092 | { | |
2093 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2094 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2095 | return (len == 4 || len == 8 || len == 12); | |
2096 | } | |
2097 | ||
c5e656c1 MK |
2098 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2099 | } | |
2100 | ||
2101 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2102 | should be returned. If it is supposed to be returned in registers, | |
2103 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2104 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2105 | from WRITEBUF into REGCACHE. */ | |
2106 | ||
2107 | static enum return_value_convention | |
c055b101 CV |
2108 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2109 | struct type *type, struct regcache *regcache, | |
2110 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2111 | { |
2112 | enum type_code code = TYPE_CODE (type); | |
2113 | ||
5daa78cc TJB |
2114 | if (((code == TYPE_CODE_STRUCT |
2115 | || code == TYPE_CODE_UNION | |
2116 | || code == TYPE_CODE_ARRAY) | |
2117 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2118 | /* 128-bit decimal float uses the struct return convention. */ | |
2119 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2120 | { |
2121 | /* The System V ABI says that: | |
2122 | ||
2123 | "A function that returns a structure or union also sets %eax | |
2124 | to the value of the original address of the caller's area | |
2125 | before it returns. Thus when the caller receives control | |
2126 | again, the address of the returned object resides in register | |
2127 | %eax and can be used to access the object." | |
2128 | ||
2129 | So the ABI guarantees that we can always find the return | |
2130 | value just after the function has returned. */ | |
2131 | ||
0e4377e1 JB |
2132 | /* Note that the ABI doesn't mention functions returning arrays, |
2133 | which is something possible in certain languages such as Ada. | |
2134 | In this case, the value is returned as if it was wrapped in | |
2135 | a record, so the convention applied to records also applies | |
2136 | to arrays. */ | |
2137 | ||
31db7b6c MK |
2138 | if (readbuf) |
2139 | { | |
2140 | ULONGEST addr; | |
2141 | ||
2142 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2143 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2144 | } | |
2145 | ||
2146 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2147 | } | |
c5e656c1 MK |
2148 | |
2149 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2150 | `float', `double' or 'long double' member. These structures are |
2151 | returned in %st(0). For these structures, we call ourselves | |
2152 | recursively, changing TYPE into the type of the first member of | |
2153 | the structure. Since that should work for all structures that | |
2154 | have only one member, we don't bother to check the member's type | |
2155 | here. */ | |
c5e656c1 MK |
2156 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2157 | { | |
2158 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2159 | return i386_return_value (gdbarch, func_type, type, regcache, |
2160 | readbuf, writebuf); | |
c5e656c1 MK |
2161 | } |
2162 | ||
2163 | if (readbuf) | |
2164 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2165 | if (writebuf) | |
2166 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2167 | |
c5e656c1 | 2168 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2169 | } |
2170 | \f | |
2171 | ||
27067745 UW |
2172 | struct type * |
2173 | i387_ext_type (struct gdbarch *gdbarch) | |
2174 | { | |
2175 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2176 | ||
2177 | if (!tdep->i387_ext_type) | |
90884b2b L |
2178 | { |
2179 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2180 | gdb_assert (tdep->i387_ext_type != NULL); | |
2181 | } | |
27067745 UW |
2182 | |
2183 | return tdep->i387_ext_type; | |
2184 | } | |
2185 | ||
794ac428 | 2186 | /* Construct vector type for MMX registers. */ |
90884b2b | 2187 | static struct type * |
794ac428 UW |
2188 | i386_mmx_type (struct gdbarch *gdbarch) |
2189 | { | |
2190 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2191 | ||
2192 | if (!tdep->i386_mmx_type) | |
2193 | { | |
df4df182 UW |
2194 | const struct builtin_type *bt = builtin_type (gdbarch); |
2195 | ||
794ac428 UW |
2196 | /* The type we're building is this: */ |
2197 | #if 0 | |
2198 | union __gdb_builtin_type_vec64i | |
2199 | { | |
2200 | int64_t uint64; | |
2201 | int32_t v2_int32[2]; | |
2202 | int16_t v4_int16[4]; | |
2203 | int8_t v8_int8[8]; | |
2204 | }; | |
2205 | #endif | |
2206 | ||
2207 | struct type *t; | |
2208 | ||
e9bb382b UW |
2209 | t = arch_composite_type (gdbarch, |
2210 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2211 | |
2212 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2213 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2214 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2215 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2216 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2217 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2218 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2219 | |
876cecd0 | 2220 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2221 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2222 | tdep->i386_mmx_type = t; | |
2223 | } | |
2224 | ||
2225 | return tdep->i386_mmx_type; | |
2226 | } | |
2227 | ||
d7a0d72c | 2228 | /* Return the GDB type object for the "standard" data type of data in |
90884b2b | 2229 | register REGNUM. */ |
d7a0d72c | 2230 | |
3a1e71e3 | 2231 | static struct type * |
90884b2b | 2232 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2233 | { |
1ba53b71 L |
2234 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2235 | return i386_mmx_type (gdbarch); | |
2236 | else | |
2237 | { | |
2238 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2239 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2240 | return bt->builtin_int8; | |
2241 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2242 | return bt->builtin_int16; | |
2243 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2244 | return bt->builtin_int32; | |
2245 | } | |
2246 | ||
2247 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2248 | } |
2249 | ||
28fc6740 | 2250 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2251 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2252 | |
2253 | static int | |
c86c27af | 2254 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2255 | { |
5716833c MK |
2256 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2257 | int mmxreg, fpreg; | |
28fc6740 AC |
2258 | ULONGEST fstat; |
2259 | int tos; | |
c86c27af | 2260 | |
5716833c | 2261 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2262 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2263 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2264 | fpreg = (mmxreg + tos) % 8; |
2265 | ||
20a6ec49 | 2266 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2267 | } |
2268 | ||
1ba53b71 | 2269 | void |
28fc6740 | 2270 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2271 | int regnum, gdb_byte *buf) |
28fc6740 | 2272 | { |
1ba53b71 L |
2273 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2274 | ||
5716833c | 2275 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2276 | { |
c86c27af MK |
2277 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2278 | ||
28fc6740 | 2279 | /* Extract (always little endian). */ |
1ba53b71 L |
2280 | regcache_raw_read (regcache, fpnum, raw_buf); |
2281 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2282 | } |
2283 | else | |
1ba53b71 L |
2284 | { |
2285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2286 | ||
2287 | if (i386_word_regnum_p (gdbarch, regnum)) | |
2288 | { | |
2289 | int gpnum = regnum - tdep->ax_regnum; | |
2290 | ||
2291 | /* Extract (always little endian). */ | |
2292 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2293 | memcpy (buf, raw_buf, 2); | |
2294 | } | |
2295 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2296 | { | |
2297 | /* Check byte pseudo registers last since this function will | |
2298 | be called from amd64_pseudo_register_read, which handles | |
2299 | byte pseudo registers differently. */ | |
2300 | int gpnum = regnum - tdep->al_regnum; | |
2301 | ||
2302 | /* Extract (always little endian). We read both lower and | |
2303 | upper registers. */ | |
2304 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2305 | if (gpnum >= 4) | |
2306 | memcpy (buf, raw_buf + 1, 1); | |
2307 | else | |
2308 | memcpy (buf, raw_buf, 1); | |
2309 | } | |
2310 | else | |
2311 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2312 | } | |
28fc6740 AC |
2313 | } |
2314 | ||
1ba53b71 | 2315 | void |
28fc6740 | 2316 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2317 | int regnum, const gdb_byte *buf) |
28fc6740 | 2318 | { |
1ba53b71 L |
2319 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2320 | ||
5716833c | 2321 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2322 | { |
c86c27af MK |
2323 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2324 | ||
28fc6740 | 2325 | /* Read ... */ |
1ba53b71 | 2326 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2327 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2328 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2329 | /* ... Write. */ |
1ba53b71 | 2330 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2331 | } |
2332 | else | |
1ba53b71 L |
2333 | { |
2334 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2335 | ||
2336 | if (i386_word_regnum_p (gdbarch, regnum)) | |
2337 | { | |
2338 | int gpnum = regnum - tdep->ax_regnum; | |
2339 | ||
2340 | /* Read ... */ | |
2341 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2342 | /* ... Modify ... (always little endian). */ | |
2343 | memcpy (raw_buf, buf, 2); | |
2344 | /* ... Write. */ | |
2345 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2346 | } | |
2347 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2348 | { | |
2349 | /* Check byte pseudo registers last since this function will | |
2350 | be called from amd64_pseudo_register_read, which handles | |
2351 | byte pseudo registers differently. */ | |
2352 | int gpnum = regnum - tdep->al_regnum; | |
2353 | ||
2354 | /* Read ... We read both lower and upper registers. */ | |
2355 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2356 | /* ... Modify ... (always little endian). */ | |
2357 | if (gpnum >= 4) | |
2358 | memcpy (raw_buf + 1, buf, 1); | |
2359 | else | |
2360 | memcpy (raw_buf, buf, 1); | |
2361 | /* ... Write. */ | |
2362 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2363 | } | |
2364 | else | |
2365 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2366 | } | |
28fc6740 | 2367 | } |
ff2e87ac AC |
2368 | \f |
2369 | ||
ff2e87ac AC |
2370 | /* Return the register number of the register allocated by GCC after |
2371 | REGNUM, or -1 if there is no such register. */ | |
2372 | ||
2373 | static int | |
2374 | i386_next_regnum (int regnum) | |
2375 | { | |
2376 | /* GCC allocates the registers in the order: | |
2377 | ||
2378 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2379 | ||
2380 | Since storing a variable in %esp doesn't make any sense we return | |
2381 | -1 for %ebp and for %esp itself. */ | |
2382 | static int next_regnum[] = | |
2383 | { | |
2384 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2385 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2386 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2387 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2388 | -1, -1, /* Slots for %esp and %ebp. */ | |
2389 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2390 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2391 | }; | |
2392 | ||
de5b9bb9 | 2393 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2394 | return next_regnum[regnum]; |
28fc6740 | 2395 | |
ff2e87ac AC |
2396 | return -1; |
2397 | } | |
2398 | ||
2399 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2400 | needs any special handling. */ | |
d7a0d72c | 2401 | |
3a1e71e3 | 2402 | static int |
0abe36f5 | 2403 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2404 | { |
de5b9bb9 MK |
2405 | int len = TYPE_LENGTH (type); |
2406 | ||
ff2e87ac AC |
2407 | /* Values may be spread across multiple registers. Most debugging |
2408 | formats aren't expressive enough to specify the locations, so | |
2409 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2410 | have a length that is a multiple of the word size, since GCC |
2411 | doesn't seem to put any other types into registers. */ | |
2412 | if (len > 4 && len % 4 == 0) | |
2413 | { | |
2414 | int last_regnum = regnum; | |
2415 | ||
2416 | while (len > 4) | |
2417 | { | |
2418 | last_regnum = i386_next_regnum (last_regnum); | |
2419 | len -= 4; | |
2420 | } | |
2421 | ||
2422 | if (last_regnum != -1) | |
2423 | return 1; | |
2424 | } | |
ff2e87ac | 2425 | |
0abe36f5 | 2426 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2427 | } |
2428 | ||
ff2e87ac AC |
2429 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2430 | return its contents in TO. */ | |
ac27f131 | 2431 | |
3a1e71e3 | 2432 | static void |
ff2e87ac | 2433 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2434 | struct type *type, gdb_byte *to) |
ac27f131 | 2435 | { |
20a6ec49 | 2436 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2437 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2438 | |
ff2e87ac AC |
2439 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2440 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2441 | |
20a6ec49 | 2442 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2443 | { |
d532c08f MK |
2444 | i387_register_to_value (frame, regnum, type, to); |
2445 | return; | |
8d7f6b4a | 2446 | } |
ff2e87ac | 2447 | |
fd35795f | 2448 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2449 | |
2450 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2451 | |
de5b9bb9 MK |
2452 | while (len > 0) |
2453 | { | |
2454 | gdb_assert (regnum != -1); | |
20a6ec49 | 2455 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2456 | |
42835c2b | 2457 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2458 | regnum = i386_next_regnum (regnum); |
2459 | len -= 4; | |
42835c2b | 2460 | to += 4; |
de5b9bb9 | 2461 | } |
ac27f131 MK |
2462 | } |
2463 | ||
ff2e87ac AC |
2464 | /* Write the contents FROM of a value of type TYPE into register |
2465 | REGNUM in frame FRAME. */ | |
ac27f131 | 2466 | |
3a1e71e3 | 2467 | static void |
ff2e87ac | 2468 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2469 | struct type *type, const gdb_byte *from) |
ac27f131 | 2470 | { |
de5b9bb9 | 2471 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2472 | |
20a6ec49 | 2473 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2474 | { |
d532c08f MK |
2475 | i387_value_to_register (frame, regnum, type, from); |
2476 | return; | |
2477 | } | |
3d261580 | 2478 | |
fd35795f | 2479 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2480 | |
2481 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2482 | |
de5b9bb9 MK |
2483 | while (len > 0) |
2484 | { | |
2485 | gdb_assert (regnum != -1); | |
875f8d0e | 2486 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2487 | |
42835c2b | 2488 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2489 | regnum = i386_next_regnum (regnum); |
2490 | len -= 4; | |
42835c2b | 2491 | from += 4; |
de5b9bb9 | 2492 | } |
ac27f131 | 2493 | } |
ff2e87ac | 2494 | \f |
7fdafb5a MK |
2495 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2496 | in the general-purpose register set REGSET to register cache | |
2497 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2498 | |
20187ed5 | 2499 | void |
473f17b0 MK |
2500 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2501 | int regnum, const void *gregs, size_t len) | |
2502 | { | |
9ea75c57 | 2503 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2504 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2505 | int i; |
2506 | ||
2507 | gdb_assert (len == tdep->sizeof_gregset); | |
2508 | ||
2509 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2510 | { | |
2511 | if ((regnum == i || regnum == -1) | |
2512 | && tdep->gregset_reg_offset[i] != -1) | |
2513 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2514 | } | |
2515 | } | |
2516 | ||
7fdafb5a MK |
2517 | /* Collect register REGNUM from the register cache REGCACHE and store |
2518 | it in the buffer specified by GREGS and LEN as described by the | |
2519 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2520 | all registers in REGSET. */ | |
2521 | ||
2522 | void | |
2523 | i386_collect_gregset (const struct regset *regset, | |
2524 | const struct regcache *regcache, | |
2525 | int regnum, void *gregs, size_t len) | |
2526 | { | |
2527 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2528 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2529 | int i; |
2530 | ||
2531 | gdb_assert (len == tdep->sizeof_gregset); | |
2532 | ||
2533 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2534 | { | |
2535 | if ((regnum == i || regnum == -1) | |
2536 | && tdep->gregset_reg_offset[i] != -1) | |
2537 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2538 | } | |
2539 | } | |
2540 | ||
2541 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2542 | in the floating-point register set REGSET to register cache | |
2543 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2544 | |
2545 | static void | |
2546 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2547 | int regnum, const void *fpregs, size_t len) | |
2548 | { | |
9ea75c57 | 2549 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2550 | |
66a72d25 MK |
2551 | if (len == I387_SIZEOF_FXSAVE) |
2552 | { | |
2553 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2554 | return; | |
2555 | } | |
2556 | ||
473f17b0 MK |
2557 | gdb_assert (len == tdep->sizeof_fpregset); |
2558 | i387_supply_fsave (regcache, regnum, fpregs); | |
2559 | } | |
8446b36a | 2560 | |
2f305df1 MK |
2561 | /* Collect register REGNUM from the register cache REGCACHE and store |
2562 | it in the buffer specified by FPREGS and LEN as described by the | |
2563 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2564 | all registers in REGSET. */ | |
7fdafb5a MK |
2565 | |
2566 | static void | |
2567 | i386_collect_fpregset (const struct regset *regset, | |
2568 | const struct regcache *regcache, | |
2569 | int regnum, void *fpregs, size_t len) | |
2570 | { | |
2571 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2572 | ||
2573 | if (len == I387_SIZEOF_FXSAVE) | |
2574 | { | |
2575 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2576 | return; | |
2577 | } | |
2578 | ||
2579 | gdb_assert (len == tdep->sizeof_fpregset); | |
2580 | i387_collect_fsave (regcache, regnum, fpregs); | |
2581 | } | |
2582 | ||
8446b36a MK |
2583 | /* Return the appropriate register set for the core section identified |
2584 | by SECT_NAME and SECT_SIZE. */ | |
2585 | ||
2586 | const struct regset * | |
2587 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2588 | const char *sect_name, size_t sect_size) | |
2589 | { | |
2590 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2591 | ||
2592 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2593 | { | |
2594 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2595 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2596 | i386_collect_gregset); | |
8446b36a MK |
2597 | return tdep->gregset; |
2598 | } | |
2599 | ||
66a72d25 MK |
2600 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2601 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2602 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2603 | { |
2604 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2605 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2606 | i386_collect_fpregset); | |
8446b36a MK |
2607 | return tdep->fpregset; |
2608 | } | |
2609 | ||
2610 | return NULL; | |
2611 | } | |
473f17b0 | 2612 | \f |
fc338970 | 2613 | |
fc338970 | 2614 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2615 | |
2616 | CORE_ADDR | |
e17a4113 UW |
2617 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
2618 | CORE_ADDR pc, char *name) | |
c906108c | 2619 | { |
e17a4113 UW |
2620 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2621 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2622 | ||
2623 | /* jmp *(dest) */ | |
2624 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 2625 | { |
e17a4113 UW |
2626 | unsigned long indirect = |
2627 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 2628 | struct minimal_symbol *indsym = |
fc338970 | 2629 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2630 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2631 | |
c5aa993b | 2632 | if (symname) |
c906108c | 2633 | { |
c5aa993b JM |
2634 | if (strncmp (symname, "__imp_", 6) == 0 |
2635 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
2636 | return name ? 1 : |
2637 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
2638 | } |
2639 | } | |
fc338970 | 2640 | return 0; /* Not a trampoline. */ |
c906108c | 2641 | } |
fc338970 MK |
2642 | \f |
2643 | ||
10458914 DJ |
2644 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2645 | routine. */ | |
8201327c | 2646 | |
4bd207ef | 2647 | int |
10458914 | 2648 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2649 | { |
10458914 | 2650 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2651 | char *name; |
2652 | ||
2653 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2654 | return (name && strcmp ("_sigtramp", name) == 0); |
2655 | } | |
2656 | \f | |
2657 | ||
fc338970 MK |
2658 | /* We have two flavours of disassembly. The machinery on this page |
2659 | deals with switching between those. */ | |
c906108c SS |
2660 | |
2661 | static int | |
a89aa300 | 2662 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2663 | { |
5e3397bb MK |
2664 | gdb_assert (disassembly_flavor == att_flavor |
2665 | || disassembly_flavor == intel_flavor); | |
2666 | ||
2667 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2668 | constified, cast to prevent a compiler warning. */ | |
2669 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2670 | |
2671 | return print_insn_i386 (pc, info); | |
7a292a7a | 2672 | } |
fc338970 | 2673 | \f |
3ce1502b | 2674 | |
8201327c MK |
2675 | /* There are a few i386 architecture variants that differ only |
2676 | slightly from the generic i386 target. For now, we don't give them | |
2677 | their own source file, but include them here. As a consequence, | |
2678 | they'll always be included. */ | |
3ce1502b | 2679 | |
8201327c | 2680 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2681 | |
10458914 DJ |
2682 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2683 | routine. */ | |
911bc6ee | 2684 | |
8201327c | 2685 | static int |
10458914 | 2686 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2687 | { |
10458914 | 2688 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2689 | char *name; |
2690 | ||
acd5c798 MK |
2691 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2692 | currently unknown. */ | |
911bc6ee | 2693 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2694 | return (name && (strcmp ("_sigreturn", name) == 0 |
2695 | || strcmp ("_sigacthandler", name) == 0 | |
2696 | || strcmp ("sigvechandler", name) == 0)); | |
2697 | } | |
d2a7c97a | 2698 | |
10458914 DJ |
2699 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2700 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2701 | |
3a1e71e3 | 2702 | static CORE_ADDR |
10458914 | 2703 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2704 | { |
e17a4113 UW |
2705 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2706 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 2707 | gdb_byte buf[4]; |
acd5c798 | 2708 | CORE_ADDR sp; |
3ce1502b | 2709 | |
10458914 | 2710 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2711 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 2712 | |
e17a4113 | 2713 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
2714 | } |
2715 | \f | |
3ce1502b | 2716 | |
8201327c | 2717 | /* Generic ELF. */ |
d2a7c97a | 2718 | |
8201327c MK |
2719 | void |
2720 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2721 | { | |
c4fc7f1b MK |
2722 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2723 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2724 | } |
3ce1502b | 2725 | |
8201327c | 2726 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2727 | |
8201327c MK |
2728 | void |
2729 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2730 | { | |
2731 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2732 | |
8201327c MK |
2733 | /* System V Release 4 uses ELF. */ |
2734 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2735 | |
dfe01d39 | 2736 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2737 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2738 | ||
911bc6ee | 2739 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2740 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2741 | tdep->sc_pc_offset = 36 + 14 * 4; |
2742 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2743 | |
8201327c | 2744 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2745 | } |
2746 | ||
8201327c | 2747 | /* DJGPP. */ |
3ce1502b | 2748 | |
3a1e71e3 | 2749 | static void |
8201327c | 2750 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2751 | { |
8201327c | 2752 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2753 | |
911bc6ee MK |
2754 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2755 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2756 | |
8201327c | 2757 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
2758 | |
2759 | /* DJGPP does not support the SSE registers. */ | |
2760 | tdep->num_xmm_regs = 0; | |
90884b2b | 2761 | set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I387_NUM_REGS); |
3d22076f EZ |
2762 | |
2763 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
2764 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
2765 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
2766 | set_gdbarch_sdb_reg_to_regnum. */ | |
2767 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2768 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3ce1502b | 2769 | } |
8201327c | 2770 | \f |
2acceee2 | 2771 | |
38c968cf AC |
2772 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2773 | and "sse". */ | |
2774 | ||
2775 | static struct reggroup *i386_sse_reggroup; | |
2776 | static struct reggroup *i386_mmx_reggroup; | |
2777 | ||
2778 | static void | |
2779 | i386_init_reggroups (void) | |
2780 | { | |
2781 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2782 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2783 | } | |
2784 | ||
2785 | static void | |
2786 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2787 | { | |
2788 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2789 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2790 | reggroup_add (gdbarch, general_reggroup); | |
2791 | reggroup_add (gdbarch, float_reggroup); | |
2792 | reggroup_add (gdbarch, all_reggroup); | |
2793 | reggroup_add (gdbarch, save_reggroup); | |
2794 | reggroup_add (gdbarch, restore_reggroup); | |
2795 | reggroup_add (gdbarch, vector_reggroup); | |
2796 | reggroup_add (gdbarch, system_reggroup); | |
2797 | } | |
2798 | ||
2799 | int | |
2800 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2801 | struct reggroup *group) | |
2802 | { | |
1ba53b71 L |
2803 | int sse_regnum_p, fp_regnum_p, mmx_regnum_p, byte_regnum_p, |
2804 | word_regnum_p, dword_regnum_p; | |
acd5c798 | 2805 | |
1ba53b71 L |
2806 | /* Don't include pseudo registers, except for MMX, in any register |
2807 | groups. */ | |
2808 | byte_regnum_p = i386_byte_regnum_p (gdbarch, regnum); | |
2809 | if (byte_regnum_p) | |
2810 | return 0; | |
2811 | ||
2812 | word_regnum_p = i386_word_regnum_p (gdbarch, regnum); | |
2813 | if (word_regnum_p) | |
2814 | return 0; | |
2815 | ||
2816 | dword_regnum_p = i386_dword_regnum_p (gdbarch, regnum); | |
2817 | if (dword_regnum_p) | |
2818 | return 0; | |
2819 | ||
2820 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
2821 | if (group == i386_mmx_reggroup) |
2822 | return mmx_regnum_p; | |
1ba53b71 L |
2823 | |
2824 | sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) | |
2825 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
2826 | if (group == i386_sse_reggroup) |
2827 | return sse_regnum_p; | |
2828 | if (group == vector_reggroup) | |
1ba53b71 L |
2829 | return mmx_regnum_p || sse_regnum_p; |
2830 | ||
2831 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
2832 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
2833 | if (group == float_reggroup) |
2834 | return fp_regnum_p; | |
1ba53b71 | 2835 | |
38c968cf | 2836 | if (group == general_reggroup) |
1ba53b71 L |
2837 | return (!fp_regnum_p |
2838 | && !mmx_regnum_p | |
2839 | && !sse_regnum_p | |
2840 | && !byte_regnum_p | |
2841 | && !word_regnum_p | |
2842 | && !dword_regnum_p); | |
acd5c798 | 2843 | |
38c968cf AC |
2844 | return default_register_reggroup_p (gdbarch, regnum, group); |
2845 | } | |
38c968cf | 2846 | \f |
acd5c798 | 2847 | |
f837910f MK |
2848 | /* Get the ARGIth function argument for the current function. */ |
2849 | ||
42c466d7 | 2850 | static CORE_ADDR |
143985b7 AF |
2851 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2852 | struct type *type) | |
2853 | { | |
e17a4113 UW |
2854 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2855 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 2856 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 2857 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
2858 | } |
2859 | ||
514f746b AR |
2860 | static void |
2861 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
2862 | { | |
2863 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
2864 | ||
2865 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
2866 | adjust the PC in the regcache. */ | |
2867 | current_pc += 1; | |
2868 | regcache_write_pc (regcache, current_pc); | |
2869 | } | |
2870 | ||
2871 | ||
7ad10968 HZ |
2872 | #define PREFIX_REPZ 0x01 |
2873 | #define PREFIX_REPNZ 0x02 | |
2874 | #define PREFIX_LOCK 0x04 | |
2875 | #define PREFIX_DATA 0x08 | |
2876 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 2877 | |
7ad10968 HZ |
2878 | /* operand size */ |
2879 | enum | |
2880 | { | |
2881 | OT_BYTE = 0, | |
2882 | OT_WORD, | |
2883 | OT_LONG, | |
cf648174 | 2884 | OT_QUAD, |
7ad10968 | 2885 | }; |
473f17b0 | 2886 | |
7ad10968 HZ |
2887 | /* i386 arith/logic operations */ |
2888 | enum | |
2889 | { | |
2890 | OP_ADDL, | |
2891 | OP_ORL, | |
2892 | OP_ADCL, | |
2893 | OP_SBBL, | |
2894 | OP_ANDL, | |
2895 | OP_SUBL, | |
2896 | OP_XORL, | |
2897 | OP_CMPL, | |
2898 | }; | |
5716833c | 2899 | |
7ad10968 HZ |
2900 | struct i386_record_s |
2901 | { | |
cf648174 | 2902 | struct gdbarch *gdbarch; |
7ad10968 | 2903 | struct regcache *regcache; |
df61f520 | 2904 | CORE_ADDR orig_addr; |
7ad10968 HZ |
2905 | CORE_ADDR addr; |
2906 | int aflag; | |
2907 | int dflag; | |
2908 | int override; | |
2909 | uint8_t modrm; | |
2910 | uint8_t mod, reg, rm; | |
2911 | int ot; | |
cf648174 HZ |
2912 | uint8_t rex_x; |
2913 | uint8_t rex_b; | |
2914 | int rip_offset; | |
2915 | int popl_esp_hack; | |
2916 | const int *regmap; | |
7ad10968 | 2917 | }; |
5716833c | 2918 | |
7ad10968 HZ |
2919 | /* Parse "modrm" part in current memory address that irp->addr point to |
2920 | Return -1 if something wrong. */ | |
5716833c | 2921 | |
7ad10968 HZ |
2922 | static int |
2923 | i386_record_modrm (struct i386_record_s *irp) | |
2924 | { | |
cf648174 | 2925 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 2926 | |
7ad10968 HZ |
2927 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
2928 | { | |
2929 | if (record_debug) | |
2930 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
2931 | "addr %s len = 1.\n"), |
2932 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2933 | return -1; |
2934 | } | |
2935 | irp->addr++; | |
2936 | irp->mod = (irp->modrm >> 6) & 3; | |
2937 | irp->reg = (irp->modrm >> 3) & 7; | |
2938 | irp->rm = irp->modrm & 7; | |
5716833c | 2939 | |
7ad10968 HZ |
2940 | return 0; |
2941 | } | |
d2a7c97a | 2942 | |
7ad10968 HZ |
2943 | /* Get the memory address that current instruction write to and set it to |
2944 | the argument "addr". | |
2945 | Return -1 if something wrong. */ | |
8201327c | 2946 | |
7ad10968 | 2947 | static int |
cf648174 | 2948 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 2949 | { |
cf648174 | 2950 | struct gdbarch *gdbarch = irp->gdbarch; |
648d0c8b MS |
2951 | int8_t addr8; |
2952 | int16_t addr16; | |
2953 | int32_t addr32; | |
2954 | ULONGEST addr64; | |
21d0e8a4 | 2955 | |
7ad10968 HZ |
2956 | *addr = 0; |
2957 | if (irp->aflag) | |
2958 | { | |
2959 | /* 32 bits */ | |
2960 | int havesib = 0; | |
2961 | uint8_t scale = 0; | |
648d0c8b | 2962 | uint8_t byte; |
7ad10968 HZ |
2963 | uint8_t index = 0; |
2964 | uint8_t base = irp->rm; | |
896fb97d | 2965 | |
7ad10968 HZ |
2966 | if (base == 4) |
2967 | { | |
2968 | havesib = 1; | |
648d0c8b | 2969 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
2970 | { |
2971 | if (record_debug) | |
2972 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2973 | "at addr %s len = 1.\n"), |
2974 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2975 | return -1; |
2976 | } | |
2977 | irp->addr++; | |
648d0c8b MS |
2978 | scale = (byte >> 6) & 3; |
2979 | index = ((byte >> 3) & 7) | irp->rex_x; | |
2980 | base = (byte & 7); | |
7ad10968 | 2981 | } |
cf648174 | 2982 | base |= irp->rex_b; |
21d0e8a4 | 2983 | |
7ad10968 HZ |
2984 | switch (irp->mod) |
2985 | { | |
2986 | case 0: | |
2987 | if ((base & 7) == 5) | |
2988 | { | |
2989 | base = 0xff; | |
648d0c8b | 2990 | if (target_read_memory (irp->addr, (gdb_byte *) &addr32, 4)) |
7ad10968 HZ |
2991 | { |
2992 | if (record_debug) | |
2993 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
2994 | "memory at addr %s len = 4.\n"), |
2995 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2996 | return -1; |
2997 | } | |
2998 | irp->addr += 4; | |
648d0c8b | 2999 | *addr = addr32; |
cf648174 HZ |
3000 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
3001 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 HZ |
3002 | } |
3003 | else | |
3004 | { | |
3005 | *addr = 0; | |
3006 | } | |
3007 | break; | |
3008 | case 1: | |
648d0c8b | 3009 | if (target_read_memory (irp->addr, &addr8, 1)) |
7ad10968 HZ |
3010 | { |
3011 | if (record_debug) | |
3012 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3013 | "at addr %s len = 1.\n"), |
3014 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3015 | return -1; |
3016 | } | |
3017 | irp->addr++; | |
648d0c8b | 3018 | *addr = addr8; |
7ad10968 HZ |
3019 | break; |
3020 | case 2: | |
648d0c8b | 3021 | if (target_read_memory (irp->addr, (gdb_byte *) &addr32, 4)) |
7ad10968 HZ |
3022 | { |
3023 | if (record_debug) | |
3024 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3025 | "at addr %s len = 4.\n"), |
3026 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3027 | return -1; |
3028 | } | |
648d0c8b | 3029 | *addr = addr32; |
7ad10968 HZ |
3030 | irp->addr += 4; |
3031 | break; | |
3032 | } | |
356a6b3e | 3033 | |
648d0c8b | 3034 | addr64 = 0; |
7ad10968 | 3035 | if (base != 0xff) |
cf648174 HZ |
3036 | { |
3037 | if (base == 4 && irp->popl_esp_hack) | |
3038 | *addr += irp->popl_esp_hack; | |
3039 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
648d0c8b | 3040 | &addr64); |
7ad10968 | 3041 | } |
cf648174 HZ |
3042 | if (irp->aflag == 2) |
3043 | { | |
648d0c8b | 3044 | *addr += addr64; |
cf648174 HZ |
3045 | } |
3046 | else | |
648d0c8b | 3047 | *addr = (uint32_t) (addr64 + *addr); |
c4fc7f1b | 3048 | |
7ad10968 HZ |
3049 | if (havesib && (index != 4 || scale != 0)) |
3050 | { | |
cf648174 | 3051 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
648d0c8b | 3052 | &addr64); |
cf648174 | 3053 | if (irp->aflag == 2) |
648d0c8b | 3054 | *addr += addr64 << scale; |
cf648174 | 3055 | else |
648d0c8b | 3056 | *addr = (uint32_t) (*addr + (addr64 << scale)); |
7ad10968 HZ |
3057 | } |
3058 | } | |
3059 | else | |
3060 | { | |
3061 | /* 16 bits */ | |
3062 | switch (irp->mod) | |
3063 | { | |
3064 | case 0: | |
3065 | if (irp->rm == 6) | |
3066 | { | |
648d0c8b | 3067 | if (target_read_memory (irp->addr, (gdb_byte *) &addr16, 2)) |
7ad10968 HZ |
3068 | { |
3069 | if (record_debug) | |
3070 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3071 | "memory at addr %s len = 2.\n"), |
3072 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3073 | return -1; |
3074 | } | |
3075 | irp->addr += 2; | |
648d0c8b | 3076 | *addr = addr16; |
7ad10968 HZ |
3077 | irp->rm = 0; |
3078 | goto no_rm; | |
3079 | } | |
3080 | else | |
3081 | { | |
3082 | *addr = 0; | |
3083 | } | |
3084 | break; | |
3085 | case 1: | |
648d0c8b | 3086 | if (target_read_memory (irp->addr, &addr8, 1)) |
7ad10968 HZ |
3087 | { |
3088 | if (record_debug) | |
3089 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3090 | "at addr %s len = 1.\n"), |
3091 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3092 | return -1; |
3093 | } | |
3094 | irp->addr++; | |
648d0c8b | 3095 | *addr = addr8; |
7ad10968 HZ |
3096 | break; |
3097 | case 2: | |
648d0c8b | 3098 | if (target_read_memory (irp->addr, (gdb_byte *) &addr16, 2)) |
7ad10968 HZ |
3099 | { |
3100 | if (record_debug) | |
3101 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3102 | "at addr %s len = 2.\n"), |
3103 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3104 | return -1; |
3105 | } | |
3106 | irp->addr += 2; | |
648d0c8b | 3107 | *addr = addr16; |
7ad10968 HZ |
3108 | break; |
3109 | } | |
c4fc7f1b | 3110 | |
7ad10968 HZ |
3111 | switch (irp->rm) |
3112 | { | |
3113 | case 0: | |
cf648174 HZ |
3114 | regcache_raw_read_unsigned (irp->regcache, |
3115 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
648d0c8b MS |
3116 | &addr64); |
3117 | *addr = (uint32_t) (*addr + addr64); | |
cf648174 HZ |
3118 | regcache_raw_read_unsigned (irp->regcache, |
3119 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
648d0c8b MS |
3120 | &addr64); |
3121 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3122 | break; |
3123 | case 1: | |
cf648174 HZ |
3124 | regcache_raw_read_unsigned (irp->regcache, |
3125 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
648d0c8b MS |
3126 | &addr64); |
3127 | *addr = (uint32_t) (*addr + addr64); | |
cf648174 HZ |
3128 | regcache_raw_read_unsigned (irp->regcache, |
3129 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b MS |
3130 | &addr64); |
3131 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3132 | break; |
3133 | case 2: | |
cf648174 HZ |
3134 | regcache_raw_read_unsigned (irp->regcache, |
3135 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
648d0c8b MS |
3136 | &addr64); |
3137 | *addr = (uint32_t) (*addr + addr64); | |
cf648174 HZ |
3138 | regcache_raw_read_unsigned (irp->regcache, |
3139 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
648d0c8b MS |
3140 | &addr64); |
3141 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3142 | break; |
3143 | case 3: | |
cf648174 HZ |
3144 | regcache_raw_read_unsigned (irp->regcache, |
3145 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
648d0c8b MS |
3146 | &addr64); |
3147 | *addr = (uint32_t) (*addr + addr64); | |
cf648174 HZ |
3148 | regcache_raw_read_unsigned (irp->regcache, |
3149 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b MS |
3150 | &addr64); |
3151 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3152 | break; |
3153 | case 4: | |
cf648174 HZ |
3154 | regcache_raw_read_unsigned (irp->regcache, |
3155 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
648d0c8b MS |
3156 | &addr64); |
3157 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3158 | break; |
3159 | case 5: | |
cf648174 HZ |
3160 | regcache_raw_read_unsigned (irp->regcache, |
3161 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b MS |
3162 | &addr64); |
3163 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3164 | break; |
3165 | case 6: | |
cf648174 HZ |
3166 | regcache_raw_read_unsigned (irp->regcache, |
3167 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
648d0c8b MS |
3168 | &addr64); |
3169 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3170 | break; |
3171 | case 7: | |
cf648174 HZ |
3172 | regcache_raw_read_unsigned (irp->regcache, |
3173 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
648d0c8b MS |
3174 | &addr64); |
3175 | *addr = (uint32_t) (*addr + addr64); | |
7ad10968 HZ |
3176 | break; |
3177 | } | |
3178 | *addr &= 0xffff; | |
3179 | } | |
c4fc7f1b | 3180 | |
01fe1b41 | 3181 | no_rm: |
7ad10968 HZ |
3182 | return 0; |
3183 | } | |
c4fc7f1b | 3184 | |
7ad10968 HZ |
3185 | /* Record the value of the memory that willbe changed in current instruction |
3186 | to "record_arch_list". | |
3187 | Return -1 if something wrong. */ | |
356a6b3e | 3188 | |
7ad10968 HZ |
3189 | static int |
3190 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3191 | { | |
cf648174 HZ |
3192 | struct gdbarch *gdbarch = irp->gdbarch; |
3193 | uint64_t addr; | |
356a6b3e | 3194 | |
d7877f7e | 3195 | if (irp->override >= 0) |
7ad10968 | 3196 | { |
df61f520 HZ |
3197 | warning (_("Process record ignores the memory change " |
3198 | "of instruction at address %s because it " | |
3199 | "can't get the value of the segment register."), | |
3200 | paddress (gdbarch, irp->orig_addr)); | |
7ad10968 HZ |
3201 | return 0; |
3202 | } | |
61113f8b | 3203 | |
7ad10968 HZ |
3204 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3205 | return -1; | |
96297dab | 3206 | |
7ad10968 HZ |
3207 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3208 | return -1; | |
a62cc96e | 3209 | |
7ad10968 HZ |
3210 | return 0; |
3211 | } | |
b6197528 | 3212 | |
cf648174 HZ |
3213 | /* Record the push operation to "record_arch_list". |
3214 | Return -1 if something wrong. */ | |
3215 | ||
3216 | static int | |
3217 | i386_record_push (struct i386_record_s *irp, int size) | |
3218 | { | |
648d0c8b | 3219 | ULONGEST addr; |
cf648174 HZ |
3220 | |
3221 | if (record_arch_list_add_reg (irp->regcache, | |
3222 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3223 | return -1; | |
3224 | regcache_raw_read_unsigned (irp->regcache, | |
3225 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
3226 | &addr); |
3227 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
3228 | return -1; |
3229 | ||
3230 | return 0; | |
3231 | } | |
3232 | ||
0289bdd7 MS |
3233 | |
3234 | /* Defines contents to record. */ | |
3235 | #define I386_SAVE_FPU_REGS 0xfffd | |
3236 | #define I386_SAVE_FPU_ENV 0xfffe | |
3237 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3238 | ||
3239 | /* Record the value of floating point registers which will be changed by the | |
3240 | current instruction to "record_arch_list". Return -1 if something is wrong. | |
3241 | */ | |
3242 | ||
3243 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3244 | struct i386_record_s *ir, | |
3245 | uint32_t iregnum) | |
3246 | { | |
3247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3248 | int i; | |
3249 | ||
3250 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3251 | happen. Currently we store st0-st7 registers, but we need not store all | |
3252 | registers all the time, in future we use ftag register and record only | |
3253 | those who are not marked as an empty. */ | |
3254 | ||
3255 | if (I386_SAVE_FPU_REGS == iregnum) | |
3256 | { | |
3257 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3258 | { | |
3259 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3260 | return -1; | |
3261 | } | |
3262 | } | |
3263 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3264 | { | |
3265 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3266 | { | |
3267 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3268 | return -1; | |
3269 | } | |
3270 | } | |
3271 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3272 | { | |
3273 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3274 | { | |
3275 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3276 | return -1; | |
3277 | } | |
3278 | } | |
3279 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3280 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3281 | { | |
3282 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3283 | return -1; | |
3284 | } | |
3285 | else | |
3286 | { | |
3287 | /* Parameter error. */ | |
3288 | return -1; | |
3289 | } | |
3290 | if(I386_SAVE_FPU_ENV != iregnum) | |
3291 | { | |
3292 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3293 | { | |
3294 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3295 | return -1; | |
3296 | } | |
3297 | } | |
3298 | return 0; | |
3299 | } | |
3300 | ||
7ad10968 HZ |
3301 | /* Parse the current instruction and record the values of the registers and |
3302 | memory that will be changed in current instruction to "record_arch_list". | |
3303 | Return -1 if something wrong. */ | |
8201327c | 3304 | |
cf648174 HZ |
3305 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3306 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3307 | ||
a6b808b4 | 3308 | int |
7ad10968 | 3309 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 3310 | CORE_ADDR input_addr) |
7ad10968 HZ |
3311 | { |
3312 | int prefixes = 0; | |
580879fc | 3313 | int regnum = 0; |
425b824a MS |
3314 | uint32_t opcode; |
3315 | uint8_t opcode8; | |
648d0c8b | 3316 | ULONGEST addr; |
7ad10968 | 3317 | struct i386_record_s ir; |
0289bdd7 | 3318 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3319 | int rex = 0; |
3320 | uint8_t rex_w = -1; | |
3321 | uint8_t rex_r = 0; | |
7ad10968 | 3322 | |
8408d274 | 3323 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 3324 | ir.regcache = regcache; |
648d0c8b MS |
3325 | ir.addr = input_addr; |
3326 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
3327 | ir.aflag = 1; |
3328 | ir.dflag = 1; | |
cf648174 HZ |
3329 | ir.override = -1; |
3330 | ir.popl_esp_hack = 0; | |
3331 | ir.regmap = gdbarch_tdep (gdbarch)->record_regmap; | |
3332 | ir.gdbarch = gdbarch; | |
7ad10968 HZ |
3333 | |
3334 | if (record_debug > 1) | |
3335 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3336 | "addr = %s\n", |
3337 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3338 | |
3339 | /* prefixes */ | |
3340 | while (1) | |
3341 | { | |
425b824a | 3342 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3343 | { |
3344 | if (record_debug) | |
3345 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3346 | "addr %s len = 1.\n"), |
3347 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3348 | return -1; |
3349 | } | |
3350 | ir.addr++; | |
425b824a | 3351 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 3352 | { |
01fe1b41 | 3353 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
3354 | prefixes |= PREFIX_REPZ; |
3355 | break; | |
01fe1b41 | 3356 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
3357 | prefixes |= PREFIX_REPNZ; |
3358 | break; | |
01fe1b41 | 3359 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
3360 | prefixes |= PREFIX_LOCK; |
3361 | break; | |
01fe1b41 | 3362 | case CS_PREFIX_OPCODE: |
cf648174 | 3363 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 3364 | break; |
01fe1b41 | 3365 | case SS_PREFIX_OPCODE: |
cf648174 | 3366 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 3367 | break; |
01fe1b41 | 3368 | case DS_PREFIX_OPCODE: |
cf648174 | 3369 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 3370 | break; |
01fe1b41 | 3371 | case ES_PREFIX_OPCODE: |
cf648174 | 3372 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 3373 | break; |
01fe1b41 | 3374 | case FS_PREFIX_OPCODE: |
cf648174 | 3375 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 3376 | break; |
01fe1b41 | 3377 | case GS_PREFIX_OPCODE: |
cf648174 | 3378 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 3379 | break; |
01fe1b41 | 3380 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
3381 | prefixes |= PREFIX_DATA; |
3382 | break; | |
01fe1b41 | 3383 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
3384 | prefixes |= PREFIX_ADDR; |
3385 | break; | |
d691bec7 MS |
3386 | case 0x40: /* i386 inc %eax */ |
3387 | case 0x41: /* i386 inc %ecx */ | |
3388 | case 0x42: /* i386 inc %edx */ | |
3389 | case 0x43: /* i386 inc %ebx */ | |
3390 | case 0x44: /* i386 inc %esp */ | |
3391 | case 0x45: /* i386 inc %ebp */ | |
3392 | case 0x46: /* i386 inc %esi */ | |
3393 | case 0x47: /* i386 inc %edi */ | |
3394 | case 0x48: /* i386 dec %eax */ | |
3395 | case 0x49: /* i386 dec %ecx */ | |
3396 | case 0x4a: /* i386 dec %edx */ | |
3397 | case 0x4b: /* i386 dec %ebx */ | |
3398 | case 0x4c: /* i386 dec %esp */ | |
3399 | case 0x4d: /* i386 dec %ebp */ | |
3400 | case 0x4e: /* i386 dec %esi */ | |
3401 | case 0x4f: /* i386 dec %edi */ | |
3402 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
3403 | { |
3404 | /* REX */ | |
3405 | rex = 1; | |
425b824a MS |
3406 | rex_w = (opcode8 >> 3) & 1; |
3407 | rex_r = (opcode8 & 0x4) << 1; | |
3408 | ir.rex_x = (opcode8 & 0x2) << 2; | |
3409 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 3410 | } |
d691bec7 MS |
3411 | else /* 32 bit target */ |
3412 | goto out_prefixes; | |
cf648174 | 3413 | break; |
7ad10968 HZ |
3414 | default: |
3415 | goto out_prefixes; | |
3416 | break; | |
3417 | } | |
3418 | } | |
01fe1b41 | 3419 | out_prefixes: |
cf648174 HZ |
3420 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
3421 | { | |
3422 | ir.dflag = 2; | |
3423 | } | |
3424 | else | |
3425 | { | |
3426 | if (prefixes & PREFIX_DATA) | |
3427 | ir.dflag ^= 1; | |
3428 | } | |
7ad10968 HZ |
3429 | if (prefixes & PREFIX_ADDR) |
3430 | ir.aflag ^= 1; | |
cf648174 HZ |
3431 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3432 | ir.aflag = 2; | |
7ad10968 HZ |
3433 | |
3434 | /* now check op code */ | |
425b824a | 3435 | opcode = (uint32_t) opcode8; |
01fe1b41 | 3436 | reswitch: |
7ad10968 HZ |
3437 | switch (opcode) |
3438 | { | |
3439 | case 0x0f: | |
425b824a | 3440 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3441 | { |
3442 | if (record_debug) | |
3443 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3444 | "addr %s len = 1.\n"), |
3445 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3446 | return -1; |
3447 | } | |
3448 | ir.addr++; | |
425b824a | 3449 | opcode = (uint16_t) opcode8 | 0x0f00; |
7ad10968 HZ |
3450 | goto reswitch; |
3451 | break; | |
93924b6b | 3452 | |
a38bba38 | 3453 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
3454 | case 0x01: |
3455 | case 0x02: | |
3456 | case 0x03: | |
3457 | case 0x04: | |
3458 | case 0x05: | |
3459 | case 0x08: | |
3460 | case 0x09: | |
3461 | case 0x0a: | |
3462 | case 0x0b: | |
3463 | case 0x0c: | |
3464 | case 0x0d: | |
3465 | case 0x10: | |
3466 | case 0x11: | |
3467 | case 0x12: | |
3468 | case 0x13: | |
3469 | case 0x14: | |
3470 | case 0x15: | |
3471 | case 0x18: | |
3472 | case 0x19: | |
3473 | case 0x1a: | |
3474 | case 0x1b: | |
3475 | case 0x1c: | |
3476 | case 0x1d: | |
3477 | case 0x20: | |
3478 | case 0x21: | |
3479 | case 0x22: | |
3480 | case 0x23: | |
3481 | case 0x24: | |
3482 | case 0x25: | |
3483 | case 0x28: | |
3484 | case 0x29: | |
3485 | case 0x2a: | |
3486 | case 0x2b: | |
3487 | case 0x2c: | |
3488 | case 0x2d: | |
3489 | case 0x30: | |
3490 | case 0x31: | |
3491 | case 0x32: | |
3492 | case 0x33: | |
3493 | case 0x34: | |
3494 | case 0x35: | |
3495 | case 0x38: | |
3496 | case 0x39: | |
3497 | case 0x3a: | |
3498 | case 0x3b: | |
3499 | case 0x3c: | |
3500 | case 0x3d: | |
3501 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3502 | { | |
3503 | if ((opcode & 1) == 0) | |
3504 | ir.ot = OT_BYTE; | |
3505 | else | |
3506 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3507 | |
7ad10968 HZ |
3508 | switch ((opcode >> 1) & 3) |
3509 | { | |
a38bba38 | 3510 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
3511 | if (i386_record_modrm (&ir)) |
3512 | return -1; | |
3513 | if (ir.mod != 3) | |
3514 | { | |
3515 | if (i386_record_lea_modrm (&ir)) | |
3516 | return -1; | |
3517 | } | |
3518 | else | |
3519 | { | |
cf648174 HZ |
3520 | ir.rm |= ir.rex_b; |
3521 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3522 | ir.rm &= 0x3; |
cf648174 | 3523 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3524 | } |
3525 | break; | |
a38bba38 | 3526 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
3527 | if (i386_record_modrm (&ir)) |
3528 | return -1; | |
cf648174 HZ |
3529 | ir.reg |= rex_r; |
3530 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3531 | ir.reg &= 0x3; |
cf648174 | 3532 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3533 | break; |
a38bba38 | 3534 | case 2: /* OP A, Iv */ |
cf648174 | 3535 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3536 | break; |
3537 | } | |
3538 | } | |
cf648174 | 3539 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3540 | break; |
42fdc8df | 3541 | |
a38bba38 | 3542 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
3543 | case 0x81: |
3544 | case 0x82: | |
3545 | case 0x83: | |
3546 | if (i386_record_modrm (&ir)) | |
3547 | return -1; | |
8201327c | 3548 | |
7ad10968 HZ |
3549 | if (ir.reg != OP_CMPL) |
3550 | { | |
3551 | if ((opcode & 1) == 0) | |
3552 | ir.ot = OT_BYTE; | |
3553 | else | |
3554 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3555 | |
7ad10968 HZ |
3556 | if (ir.mod != 3) |
3557 | { | |
cf648174 HZ |
3558 | if (opcode == 0x83) |
3559 | ir.rip_offset = 1; | |
3560 | else | |
3561 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3562 | if (i386_record_lea_modrm (&ir)) |
3563 | return -1; | |
3564 | } | |
3565 | else | |
cf648174 | 3566 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 3567 | } |
cf648174 | 3568 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3569 | break; |
5e3397bb | 3570 | |
a38bba38 | 3571 | case 0x40: /* inc */ |
7ad10968 HZ |
3572 | case 0x41: |
3573 | case 0x42: | |
3574 | case 0x43: | |
3575 | case 0x44: | |
3576 | case 0x45: | |
3577 | case 0x46: | |
3578 | case 0x47: | |
a38bba38 MS |
3579 | |
3580 | case 0x48: /* dec */ | |
7ad10968 HZ |
3581 | case 0x49: |
3582 | case 0x4a: | |
3583 | case 0x4b: | |
3584 | case 0x4c: | |
3585 | case 0x4d: | |
3586 | case 0x4e: | |
3587 | case 0x4f: | |
a38bba38 | 3588 | |
cf648174 HZ |
3589 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
3590 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 3591 | break; |
acd5c798 | 3592 | |
a38bba38 | 3593 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
3594 | case 0xf7: |
3595 | if ((opcode & 1) == 0) | |
3596 | ir.ot = OT_BYTE; | |
3597 | else | |
3598 | ir.ot = ir.dflag + OT_WORD; | |
3599 | if (i386_record_modrm (&ir)) | |
3600 | return -1; | |
acd5c798 | 3601 | |
cf648174 HZ |
3602 | if (ir.mod != 3 && ir.reg == 0) |
3603 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3604 | ||
7ad10968 HZ |
3605 | switch (ir.reg) |
3606 | { | |
a38bba38 | 3607 | case 0: /* test */ |
cf648174 | 3608 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3609 | break; |
a38bba38 MS |
3610 | case 2: /* not */ |
3611 | case 3: /* neg */ | |
7ad10968 HZ |
3612 | if (ir.mod != 3) |
3613 | { | |
3614 | if (i386_record_lea_modrm (&ir)) | |
3615 | return -1; | |
3616 | } | |
3617 | else | |
3618 | { | |
cf648174 HZ |
3619 | ir.rm |= ir.rex_b; |
3620 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3621 | ir.rm &= 0x3; |
cf648174 | 3622 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3623 | } |
a38bba38 | 3624 | if (ir.reg == 3) /* neg */ |
cf648174 | 3625 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3626 | break; |
a38bba38 MS |
3627 | case 4: /* mul */ |
3628 | case 5: /* imul */ | |
3629 | case 6: /* div */ | |
3630 | case 7: /* idiv */ | |
cf648174 | 3631 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 3632 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
3633 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
3634 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3635 | break; |
3636 | default: | |
3637 | ir.addr -= 2; | |
3638 | opcode = opcode << 8 | ir.modrm; | |
3639 | goto no_support; | |
3640 | break; | |
3641 | } | |
3642 | break; | |
3643 | ||
a38bba38 MS |
3644 | case 0xfe: /* GRP4 */ |
3645 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
3646 | if (i386_record_modrm (&ir)) |
3647 | return -1; | |
3648 | if (ir.reg >= 2 && opcode == 0xfe) | |
3649 | { | |
3650 | ir.addr -= 2; | |
3651 | opcode = opcode << 8 | ir.modrm; | |
3652 | goto no_support; | |
3653 | } | |
7ad10968 HZ |
3654 | switch (ir.reg) |
3655 | { | |
a38bba38 MS |
3656 | case 0: /* inc */ |
3657 | case 1: /* dec */ | |
cf648174 HZ |
3658 | if ((opcode & 1) == 0) |
3659 | ir.ot = OT_BYTE; | |
3660 | else | |
3661 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3662 | if (ir.mod != 3) |
3663 | { | |
3664 | if (i386_record_lea_modrm (&ir)) | |
3665 | return -1; | |
3666 | } | |
3667 | else | |
3668 | { | |
cf648174 HZ |
3669 | ir.rm |= ir.rex_b; |
3670 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3671 | ir.rm &= 0x3; |
cf648174 | 3672 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3673 | } |
cf648174 | 3674 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3675 | break; |
a38bba38 | 3676 | case 2: /* call */ |
cf648174 HZ |
3677 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3678 | ir.dflag = 2; | |
3679 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3680 | return -1; |
cf648174 | 3681 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3682 | break; |
a38bba38 | 3683 | case 3: /* lcall */ |
cf648174 HZ |
3684 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
3685 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3686 | return -1; |
cf648174 | 3687 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3688 | break; |
a38bba38 MS |
3689 | case 4: /* jmp */ |
3690 | case 5: /* ljmp */ | |
cf648174 HZ |
3691 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
3692 | break; | |
a38bba38 | 3693 | case 6: /* push */ |
cf648174 HZ |
3694 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3695 | ir.dflag = 2; | |
3696 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3697 | return -1; | |
7ad10968 HZ |
3698 | break; |
3699 | default: | |
3700 | ir.addr -= 2; | |
3701 | opcode = opcode << 8 | ir.modrm; | |
3702 | goto no_support; | |
3703 | break; | |
3704 | } | |
3705 | break; | |
3706 | ||
a38bba38 | 3707 | case 0x84: /* test */ |
7ad10968 HZ |
3708 | case 0x85: |
3709 | case 0xa8: | |
3710 | case 0xa9: | |
cf648174 | 3711 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3712 | break; |
3713 | ||
a38bba38 | 3714 | case 0x98: /* CWDE/CBW */ |
cf648174 | 3715 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3716 | break; |
3717 | ||
a38bba38 | 3718 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
3719 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3720 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3721 | break; |
3722 | ||
a38bba38 | 3723 | case 0x0faf: /* imul */ |
7ad10968 HZ |
3724 | case 0x69: |
3725 | case 0x6b: | |
3726 | ir.ot = ir.dflag + OT_WORD; | |
3727 | if (i386_record_modrm (&ir)) | |
3728 | return -1; | |
cf648174 HZ |
3729 | if (opcode == 0x69) |
3730 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3731 | else if (opcode == 0x6b) | |
3732 | ir.rip_offset = 1; | |
3733 | ir.reg |= rex_r; | |
3734 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3735 | ir.reg &= 0x3; |
cf648174 HZ |
3736 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3737 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3738 | break; |
3739 | ||
a38bba38 | 3740 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
3741 | case 0x0fc1: |
3742 | if ((opcode & 1) == 0) | |
3743 | ir.ot = OT_BYTE; | |
3744 | else | |
3745 | ir.ot = ir.dflag + OT_WORD; | |
3746 | if (i386_record_modrm (&ir)) | |
3747 | return -1; | |
cf648174 | 3748 | ir.reg |= rex_r; |
7ad10968 HZ |
3749 | if (ir.mod == 3) |
3750 | { | |
cf648174 | 3751 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3752 | ir.reg &= 0x3; |
cf648174 HZ |
3753 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3754 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3755 | ir.rm &= 0x3; |
cf648174 | 3756 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3757 | } |
3758 | else | |
3759 | { | |
3760 | if (i386_record_lea_modrm (&ir)) | |
3761 | return -1; | |
cf648174 | 3762 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3763 | ir.reg &= 0x3; |
cf648174 | 3764 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3765 | } |
cf648174 | 3766 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3767 | break; |
3768 | ||
a38bba38 | 3769 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
3770 | case 0x0fb1: |
3771 | if ((opcode & 1) == 0) | |
3772 | ir.ot = OT_BYTE; | |
3773 | else | |
3774 | ir.ot = ir.dflag + OT_WORD; | |
3775 | if (i386_record_modrm (&ir)) | |
3776 | return -1; | |
3777 | if (ir.mod == 3) | |
3778 | { | |
cf648174 HZ |
3779 | ir.reg |= rex_r; |
3780 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
3781 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3782 | ir.reg &= 0x3; |
cf648174 | 3783 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
3784 | } |
3785 | else | |
3786 | { | |
cf648174 | 3787 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3788 | if (i386_record_lea_modrm (&ir)) |
3789 | return -1; | |
3790 | } | |
cf648174 | 3791 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3792 | break; |
3793 | ||
a38bba38 | 3794 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
3795 | if (i386_record_modrm (&ir)) |
3796 | return -1; | |
3797 | if (ir.mod == 3) | |
3798 | { | |
3799 | ir.addr -= 2; | |
3800 | opcode = opcode << 8 | ir.modrm; | |
3801 | goto no_support; | |
3802 | } | |
cf648174 HZ |
3803 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3804 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3805 | if (i386_record_lea_modrm (&ir)) |
3806 | return -1; | |
cf648174 | 3807 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3808 | break; |
3809 | ||
a38bba38 | 3810 | case 0x50: /* push */ |
7ad10968 HZ |
3811 | case 0x51: |
3812 | case 0x52: | |
3813 | case 0x53: | |
3814 | case 0x54: | |
3815 | case 0x55: | |
3816 | case 0x56: | |
3817 | case 0x57: | |
3818 | case 0x68: | |
3819 | case 0x6a: | |
cf648174 HZ |
3820 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3821 | ir.dflag = 2; | |
3822 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3823 | return -1; | |
3824 | break; | |
3825 | ||
a38bba38 MS |
3826 | case 0x06: /* push es */ |
3827 | case 0x0e: /* push cs */ | |
3828 | case 0x16: /* push ss */ | |
3829 | case 0x1e: /* push ds */ | |
cf648174 HZ |
3830 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3831 | { | |
3832 | ir.addr -= 1; | |
3833 | goto no_support; | |
3834 | } | |
3835 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3836 | return -1; | |
3837 | break; | |
3838 | ||
a38bba38 MS |
3839 | case 0x0fa0: /* push fs */ |
3840 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
3841 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3842 | { | |
3843 | ir.addr -= 2; | |
3844 | goto no_support; | |
3845 | } | |
3846 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3847 | return -1; |
cf648174 HZ |
3848 | break; |
3849 | ||
a38bba38 | 3850 | case 0x60: /* pusha */ |
cf648174 HZ |
3851 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3852 | { | |
3853 | ir.addr -= 1; | |
3854 | goto no_support; | |
3855 | } | |
3856 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
3857 | return -1; |
3858 | break; | |
3859 | ||
a38bba38 | 3860 | case 0x58: /* pop */ |
7ad10968 HZ |
3861 | case 0x59: |
3862 | case 0x5a: | |
3863 | case 0x5b: | |
3864 | case 0x5c: | |
3865 | case 0x5d: | |
3866 | case 0x5e: | |
3867 | case 0x5f: | |
cf648174 HZ |
3868 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3869 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
3870 | break; |
3871 | ||
a38bba38 | 3872 | case 0x61: /* popa */ |
cf648174 HZ |
3873 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3874 | { | |
3875 | ir.addr -= 1; | |
3876 | goto no_support; | |
7ad10968 | 3877 | } |
425b824a MS |
3878 | for (regnum = X86_RECORD_REAX_REGNUM; |
3879 | regnum <= X86_RECORD_REDI_REGNUM; | |
3880 | regnum++) | |
3881 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
3882 | break; |
3883 | ||
a38bba38 | 3884 | case 0x8f: /* pop */ |
cf648174 HZ |
3885 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3886 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
3887 | else | |
3888 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3889 | if (i386_record_modrm (&ir)) |
3890 | return -1; | |
3891 | if (ir.mod == 3) | |
cf648174 | 3892 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
3893 | else |
3894 | { | |
cf648174 | 3895 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
3896 | if (i386_record_lea_modrm (&ir)) |
3897 | return -1; | |
3898 | } | |
cf648174 | 3899 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
3900 | break; |
3901 | ||
a38bba38 | 3902 | case 0xc8: /* enter */ |
cf648174 HZ |
3903 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
3904 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
3905 | ir.dflag = 2; | |
3906 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
3907 | return -1; |
3908 | break; | |
3909 | ||
a38bba38 | 3910 | case 0xc9: /* leave */ |
cf648174 HZ |
3911 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3912 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
3913 | break; |
3914 | ||
a38bba38 | 3915 | case 0x07: /* pop es */ |
cf648174 HZ |
3916 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3917 | { | |
3918 | ir.addr -= 1; | |
3919 | goto no_support; | |
3920 | } | |
3921 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3922 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
3923 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3924 | break; |
3925 | ||
a38bba38 | 3926 | case 0x17: /* pop ss */ |
cf648174 HZ |
3927 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3928 | { | |
3929 | ir.addr -= 1; | |
3930 | goto no_support; | |
3931 | } | |
3932 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3933 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
3934 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3935 | break; |
3936 | ||
a38bba38 | 3937 | case 0x1f: /* pop ds */ |
cf648174 HZ |
3938 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3939 | { | |
3940 | ir.addr -= 1; | |
3941 | goto no_support; | |
3942 | } | |
3943 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3944 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
3945 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3946 | break; |
3947 | ||
a38bba38 | 3948 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
3949 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3950 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
3951 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3952 | break; |
3953 | ||
a38bba38 | 3954 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
3955 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3956 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
3957 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3958 | break; |
3959 | ||
a38bba38 | 3960 | case 0x88: /* mov */ |
7ad10968 HZ |
3961 | case 0x89: |
3962 | case 0xc6: | |
3963 | case 0xc7: | |
3964 | if ((opcode & 1) == 0) | |
3965 | ir.ot = OT_BYTE; | |
3966 | else | |
3967 | ir.ot = ir.dflag + OT_WORD; | |
3968 | ||
3969 | if (i386_record_modrm (&ir)) | |
3970 | return -1; | |
3971 | ||
3972 | if (ir.mod != 3) | |
3973 | { | |
cf648174 HZ |
3974 | if (opcode == 0xc6 || opcode == 0xc7) |
3975 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3976 | if (i386_record_lea_modrm (&ir)) |
3977 | return -1; | |
3978 | } | |
3979 | else | |
3980 | { | |
cf648174 HZ |
3981 | if (opcode == 0xc6 || opcode == 0xc7) |
3982 | ir.rm |= ir.rex_b; | |
3983 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3984 | ir.rm &= 0x3; |
cf648174 | 3985 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3986 | } |
7ad10968 | 3987 | break; |
cf648174 | 3988 | |
a38bba38 | 3989 | case 0x8a: /* mov */ |
7ad10968 HZ |
3990 | case 0x8b: |
3991 | if ((opcode & 1) == 0) | |
3992 | ir.ot = OT_BYTE; | |
3993 | else | |
3994 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3995 | if (i386_record_modrm (&ir)) |
3996 | return -1; | |
cf648174 HZ |
3997 | ir.reg |= rex_r; |
3998 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3999 | ir.reg &= 0x3; |
cf648174 HZ |
4000 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4001 | break; | |
7ad10968 | 4002 | |
a38bba38 | 4003 | case 0x8c: /* mov seg */ |
cf648174 | 4004 | if (i386_record_modrm (&ir)) |
7ad10968 | 4005 | return -1; |
cf648174 HZ |
4006 | if (ir.reg > 5) |
4007 | { | |
4008 | ir.addr -= 2; | |
4009 | opcode = opcode << 8 | ir.modrm; | |
4010 | goto no_support; | |
4011 | } | |
4012 | ||
4013 | if (ir.mod == 3) | |
4014 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4015 | else | |
4016 | { | |
4017 | ir.ot = OT_WORD; | |
4018 | if (i386_record_lea_modrm (&ir)) | |
4019 | return -1; | |
4020 | } | |
7ad10968 HZ |
4021 | break; |
4022 | ||
a38bba38 | 4023 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4024 | if (i386_record_modrm (&ir)) |
4025 | return -1; | |
7ad10968 HZ |
4026 | switch (ir.reg) |
4027 | { | |
4028 | case 0: | |
425b824a | 4029 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4030 | break; |
4031 | case 2: | |
425b824a | 4032 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4033 | break; |
4034 | case 3: | |
425b824a | 4035 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4036 | break; |
4037 | case 4: | |
425b824a | 4038 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4039 | break; |
4040 | case 5: | |
425b824a | 4041 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4042 | break; |
4043 | default: | |
4044 | ir.addr -= 2; | |
4045 | opcode = opcode << 8 | ir.modrm; | |
4046 | goto no_support; | |
4047 | break; | |
4048 | } | |
425b824a | 4049 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 4050 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4051 | break; |
4052 | ||
a38bba38 MS |
4053 | case 0x0fb6: /* movzbS */ |
4054 | case 0x0fb7: /* movzwS */ | |
4055 | case 0x0fbe: /* movsbS */ | |
4056 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4057 | if (i386_record_modrm (&ir)) |
4058 | return -1; | |
cf648174 | 4059 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4060 | break; |
4061 | ||
a38bba38 | 4062 | case 0x8d: /* lea */ |
7ad10968 HZ |
4063 | if (i386_record_modrm (&ir)) |
4064 | return -1; | |
4065 | if (ir.mod == 3) | |
4066 | { | |
4067 | ir.addr -= 2; | |
4068 | opcode = opcode << 8 | ir.modrm; | |
4069 | goto no_support; | |
4070 | } | |
7ad10968 | 4071 | ir.ot = ir.dflag; |
cf648174 HZ |
4072 | ir.reg |= rex_r; |
4073 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4074 | ir.reg &= 0x3; |
cf648174 | 4075 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4076 | break; |
4077 | ||
a38bba38 | 4078 | case 0xa0: /* mov EAX */ |
7ad10968 | 4079 | case 0xa1: |
a38bba38 MS |
4080 | |
4081 | case 0xd7: /* xlat */ | |
cf648174 | 4082 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4083 | break; |
4084 | ||
a38bba38 | 4085 | case 0xa2: /* mov EAX */ |
7ad10968 | 4086 | case 0xa3: |
d7877f7e | 4087 | if (ir.override >= 0) |
cf648174 | 4088 | { |
df61f520 | 4089 | warning (_("Process record ignores the memory change " |
926569ae | 4090 | "of instruction at address %s because " |
df61f520 HZ |
4091 | "it can't get the value of the segment " |
4092 | "register."), | |
4093 | paddress (gdbarch, ir.orig_addr)); | |
cf648174 HZ |
4094 | } |
4095 | else | |
4096 | { | |
4097 | if ((opcode & 1) == 0) | |
4098 | ir.ot = OT_BYTE; | |
4099 | else | |
4100 | ir.ot = ir.dflag + OT_WORD; | |
4101 | if (ir.aflag == 2) | |
4102 | { | |
648d0c8b MS |
4103 | uint64_t addr64; |
4104 | ||
4105 | if (target_read_memory (ir.addr, (gdb_byte *) &addr64, 8)) | |
cf648174 HZ |
4106 | { |
4107 | if (record_debug) | |
4108 | printf_unfiltered (_("Process record: error reading " | |
4109 | "memory at addr 0x%s len = 8.\n"), | |
4110 | paddress (gdbarch, ir.addr)); | |
4111 | return -1; | |
4112 | } | |
4113 | ir.addr += 8; | |
648d0c8b | 4114 | addr = addr64; |
cf648174 HZ |
4115 | } |
4116 | else if (ir.aflag) | |
4117 | { | |
955db0c0 MS |
4118 | uint32_t addr32; |
4119 | ||
4120 | if (target_read_memory (ir.addr, (gdb_byte *) &addr32, 4)) | |
cf648174 HZ |
4121 | { |
4122 | if (record_debug) | |
4123 | printf_unfiltered (_("Process record: error reading " | |
4124 | "memory at addr 0x%s len = 4.\n"), | |
4125 | paddress (gdbarch, ir.addr)); | |
4126 | return -1; | |
4127 | } | |
4128 | ir.addr += 4; | |
648d0c8b | 4129 | addr = addr32; |
cf648174 HZ |
4130 | } |
4131 | else | |
4132 | { | |
955db0c0 MS |
4133 | uint16_t addr16; |
4134 | ||
4135 | if (target_read_memory (ir.addr, (gdb_byte *) &addr16, 2)) | |
cf648174 HZ |
4136 | { |
4137 | if (record_debug) | |
4138 | printf_unfiltered (_("Process record: error reading " | |
4139 | "memory at addr 0x%s len = 2.\n"), | |
4140 | paddress (gdbarch, ir.addr)); | |
4141 | return -1; | |
4142 | } | |
4143 | ir.addr += 2; | |
648d0c8b | 4144 | addr = addr16; |
cf648174 | 4145 | } |
648d0c8b | 4146 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
4147 | return -1; |
4148 | } | |
7ad10968 HZ |
4149 | break; |
4150 | ||
a38bba38 | 4151 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4152 | case 0xb1: |
4153 | case 0xb2: | |
4154 | case 0xb3: | |
4155 | case 0xb4: | |
4156 | case 0xb5: | |
4157 | case 0xb6: | |
4158 | case 0xb7: | |
cf648174 HZ |
4159 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4160 | ? ((opcode & 0x7) | ir.rex_b) | |
4161 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4162 | break; |
4163 | ||
a38bba38 | 4164 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4165 | case 0xb9: |
4166 | case 0xba: | |
4167 | case 0xbb: | |
4168 | case 0xbc: | |
4169 | case 0xbd: | |
4170 | case 0xbe: | |
4171 | case 0xbf: | |
cf648174 | 4172 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4173 | break; |
4174 | ||
a38bba38 | 4175 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4176 | case 0x92: |
4177 | case 0x93: | |
4178 | case 0x94: | |
4179 | case 0x95: | |
4180 | case 0x96: | |
4181 | case 0x97: | |
cf648174 HZ |
4182 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4183 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4184 | break; |
4185 | ||
a38bba38 | 4186 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4187 | case 0x87: |
4188 | if ((opcode & 1) == 0) | |
4189 | ir.ot = OT_BYTE; | |
4190 | else | |
4191 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4192 | if (i386_record_modrm (&ir)) |
4193 | return -1; | |
7ad10968 HZ |
4194 | if (ir.mod == 3) |
4195 | { | |
86839d38 | 4196 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4197 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4198 | ir.rm &= 0x3; | |
4199 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4200 | } |
4201 | else | |
4202 | { | |
4203 | if (i386_record_lea_modrm (&ir)) | |
4204 | return -1; | |
4205 | } | |
cf648174 HZ |
4206 | ir.reg |= rex_r; |
4207 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4208 | ir.reg &= 0x3; |
cf648174 | 4209 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4210 | break; |
4211 | ||
a38bba38 MS |
4212 | case 0xc4: /* les Gv */ |
4213 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4214 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4215 | { | |
4216 | ir.addr -= 1; | |
4217 | goto no_support; | |
4218 | } | |
a38bba38 MS |
4219 | case 0x0fb2: /* lss Gv */ |
4220 | case 0x0fb4: /* lfs Gv */ | |
4221 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4222 | if (i386_record_modrm (&ir)) |
4223 | return -1; | |
4224 | if (ir.mod == 3) | |
4225 | { | |
4226 | if (opcode > 0xff) | |
4227 | ir.addr -= 3; | |
4228 | else | |
4229 | ir.addr -= 2; | |
4230 | opcode = opcode << 8 | ir.modrm; | |
4231 | goto no_support; | |
4232 | } | |
7ad10968 HZ |
4233 | switch (opcode) |
4234 | { | |
a38bba38 | 4235 | case 0xc4: /* les Gv */ |
425b824a | 4236 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 4237 | break; |
a38bba38 | 4238 | case 0xc5: /* lds Gv */ |
425b824a | 4239 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 4240 | break; |
a38bba38 | 4241 | case 0x0fb2: /* lss Gv */ |
425b824a | 4242 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 4243 | break; |
a38bba38 | 4244 | case 0x0fb4: /* lfs Gv */ |
425b824a | 4245 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 4246 | break; |
a38bba38 | 4247 | case 0x0fb5: /* lgs Gv */ |
425b824a | 4248 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4249 | break; |
4250 | } | |
425b824a | 4251 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
4252 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4253 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4254 | break; |
4255 | ||
a38bba38 | 4256 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4257 | case 0xc1: |
4258 | case 0xd0: | |
4259 | case 0xd1: | |
4260 | case 0xd2: | |
4261 | case 0xd3: | |
4262 | if ((opcode & 1) == 0) | |
4263 | ir.ot = OT_BYTE; | |
4264 | else | |
4265 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4266 | if (i386_record_modrm (&ir)) |
4267 | return -1; | |
7ad10968 HZ |
4268 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4269 | { | |
4270 | if (i386_record_lea_modrm (&ir)) | |
4271 | return -1; | |
4272 | } | |
4273 | else | |
4274 | { | |
cf648174 HZ |
4275 | ir.rm |= ir.rex_b; |
4276 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4277 | ir.rm &= 0x3; |
cf648174 | 4278 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4279 | } |
cf648174 | 4280 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4281 | break; |
4282 | ||
4283 | case 0x0fa4: | |
4284 | case 0x0fa5: | |
4285 | case 0x0fac: | |
4286 | case 0x0fad: | |
4287 | if (i386_record_modrm (&ir)) | |
4288 | return -1; | |
4289 | if (ir.mod == 3) | |
4290 | { | |
4291 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4292 | return -1; | |
4293 | } | |
4294 | else | |
4295 | { | |
4296 | if (i386_record_lea_modrm (&ir)) | |
4297 | return -1; | |
4298 | } | |
4299 | break; | |
4300 | ||
a38bba38 | 4301 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4302 | case 0xd9: |
4303 | case 0xda: | |
4304 | case 0xdb: | |
4305 | case 0xdc: | |
4306 | case 0xdd: | |
4307 | case 0xde: | |
4308 | case 0xdf: | |
4309 | if (i386_record_modrm (&ir)) | |
4310 | return -1; | |
4311 | ir.reg |= ((opcode & 7) << 3); | |
4312 | if (ir.mod != 3) | |
4313 | { | |
0289bdd7 | 4314 | /* Memory. */ |
955db0c0 | 4315 | uint64_t addr64; |
7ad10968 | 4316 | |
955db0c0 | 4317 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
4318 | return -1; |
4319 | switch (ir.reg) | |
4320 | { | |
7ad10968 | 4321 | case 0x02: |
0289bdd7 MS |
4322 | case 0x12: |
4323 | case 0x22: | |
4324 | case 0x32: | |
4325 | /* For fcom, ficom nothing to do. */ | |
4326 | break; | |
7ad10968 | 4327 | case 0x03: |
0289bdd7 MS |
4328 | case 0x13: |
4329 | case 0x23: | |
4330 | case 0x33: | |
4331 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
4332 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4333 | return -1; | |
4334 | break; | |
4335 | case 0x00: | |
4336 | case 0x01: | |
7ad10968 HZ |
4337 | case 0x04: |
4338 | case 0x05: | |
4339 | case 0x06: | |
4340 | case 0x07: | |
4341 | case 0x10: | |
4342 | case 0x11: | |
7ad10968 HZ |
4343 | case 0x14: |
4344 | case 0x15: | |
4345 | case 0x16: | |
4346 | case 0x17: | |
4347 | case 0x20: | |
4348 | case 0x21: | |
7ad10968 HZ |
4349 | case 0x24: |
4350 | case 0x25: | |
4351 | case 0x26: | |
4352 | case 0x27: | |
4353 | case 0x30: | |
4354 | case 0x31: | |
7ad10968 HZ |
4355 | case 0x34: |
4356 | case 0x35: | |
4357 | case 0x36: | |
4358 | case 0x37: | |
0289bdd7 MS |
4359 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
4360 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
4361 | of code, always affects st(0) register. */ | |
4362 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4363 | return -1; | |
7ad10968 HZ |
4364 | break; |
4365 | case 0x08: | |
4366 | case 0x0a: | |
4367 | case 0x0b: | |
4368 | case 0x18: | |
4369 | case 0x19: | |
4370 | case 0x1a: | |
4371 | case 0x1b: | |
0289bdd7 | 4372 | case 0x1d: |
7ad10968 HZ |
4373 | case 0x28: |
4374 | case 0x29: | |
4375 | case 0x2a: | |
4376 | case 0x2b: | |
4377 | case 0x38: | |
4378 | case 0x39: | |
4379 | case 0x3a: | |
4380 | case 0x3b: | |
0289bdd7 MS |
4381 | case 0x3c: |
4382 | case 0x3d: | |
7ad10968 HZ |
4383 | switch (ir.reg & 7) |
4384 | { | |
4385 | case 0: | |
0289bdd7 MS |
4386 | /* Handling fld, fild. */ |
4387 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4388 | return -1; | |
7ad10968 HZ |
4389 | break; |
4390 | case 1: | |
4391 | switch (ir.reg >> 4) | |
4392 | { | |
4393 | case 0: | |
955db0c0 | 4394 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
4395 | return -1; |
4396 | break; | |
4397 | case 2: | |
955db0c0 | 4398 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
4399 | return -1; |
4400 | break; | |
4401 | case 3: | |
0289bdd7 | 4402 | break; |
7ad10968 | 4403 | default: |
955db0c0 | 4404 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4405 | return -1; |
4406 | break; | |
4407 | } | |
4408 | break; | |
4409 | default: | |
4410 | switch (ir.reg >> 4) | |
4411 | { | |
4412 | case 0: | |
955db0c0 | 4413 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
4414 | return -1; |
4415 | if (3 == (ir.reg & 7)) | |
4416 | { | |
4417 | /* For fstp m32fp. */ | |
4418 | if (i386_record_floats (gdbarch, &ir, | |
4419 | I386_SAVE_FPU_REGS)) | |
4420 | return -1; | |
4421 | } | |
4422 | break; | |
7ad10968 | 4423 | case 1: |
955db0c0 | 4424 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 4425 | return -1; |
0289bdd7 MS |
4426 | if ((3 == (ir.reg & 7)) |
4427 | || (5 == (ir.reg & 7)) | |
4428 | || (7 == (ir.reg & 7))) | |
4429 | { | |
4430 | /* For fstp insn. */ | |
4431 | if (i386_record_floats (gdbarch, &ir, | |
4432 | I386_SAVE_FPU_REGS)) | |
4433 | return -1; | |
4434 | } | |
7ad10968 HZ |
4435 | break; |
4436 | case 2: | |
955db0c0 | 4437 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4438 | return -1; |
0289bdd7 MS |
4439 | if (3 == (ir.reg & 7)) |
4440 | { | |
4441 | /* For fstp m64fp. */ | |
4442 | if (i386_record_floats (gdbarch, &ir, | |
4443 | I386_SAVE_FPU_REGS)) | |
4444 | return -1; | |
4445 | } | |
7ad10968 HZ |
4446 | break; |
4447 | case 3: | |
0289bdd7 MS |
4448 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
4449 | { | |
4450 | /* For fistp, fbld, fild, fbstp. */ | |
4451 | if (i386_record_floats (gdbarch, &ir, | |
4452 | I386_SAVE_FPU_REGS)) | |
4453 | return -1; | |
4454 | } | |
4455 | /* Fall through */ | |
7ad10968 | 4456 | default: |
955db0c0 | 4457 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4458 | return -1; |
4459 | break; | |
4460 | } | |
4461 | break; | |
4462 | } | |
4463 | break; | |
4464 | case 0x0c: | |
0289bdd7 MS |
4465 | /* Insn fldenv. */ |
4466 | if (i386_record_floats (gdbarch, &ir, | |
4467 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4468 | return -1; | |
4469 | break; | |
7ad10968 | 4470 | case 0x0d: |
0289bdd7 MS |
4471 | /* Insn fldcw. */ |
4472 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
4473 | return -1; | |
4474 | break; | |
7ad10968 | 4475 | case 0x2c: |
0289bdd7 MS |
4476 | /* Insn frstor. */ |
4477 | if (i386_record_floats (gdbarch, &ir, | |
4478 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4479 | return -1; | |
7ad10968 HZ |
4480 | break; |
4481 | case 0x0e: | |
4482 | if (ir.dflag) | |
4483 | { | |
955db0c0 | 4484 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
4485 | return -1; |
4486 | } | |
4487 | else | |
4488 | { | |
955db0c0 | 4489 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
4490 | return -1; |
4491 | } | |
4492 | break; | |
4493 | case 0x0f: | |
4494 | case 0x2f: | |
955db0c0 | 4495 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 4496 | return -1; |
0289bdd7 MS |
4497 | /* Insn fstp, fbstp. */ |
4498 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4499 | return -1; | |
7ad10968 HZ |
4500 | break; |
4501 | case 0x1f: | |
4502 | case 0x3e: | |
955db0c0 | 4503 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
4504 | return -1; |
4505 | break; | |
4506 | case 0x2e: | |
4507 | if (ir.dflag) | |
4508 | { | |
955db0c0 | 4509 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 4510 | return -1; |
955db0c0 | 4511 | addr64 += 28; |
7ad10968 HZ |
4512 | } |
4513 | else | |
4514 | { | |
955db0c0 | 4515 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 4516 | return -1; |
955db0c0 | 4517 | addr64 += 14; |
7ad10968 | 4518 | } |
955db0c0 | 4519 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 4520 | return -1; |
0289bdd7 MS |
4521 | /* Insn fsave. */ |
4522 | if (i386_record_floats (gdbarch, &ir, | |
4523 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4524 | return -1; | |
7ad10968 HZ |
4525 | break; |
4526 | case 0x3f: | |
955db0c0 | 4527 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4528 | return -1; |
0289bdd7 MS |
4529 | /* Insn fistp. */ |
4530 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4531 | return -1; | |
7ad10968 HZ |
4532 | break; |
4533 | default: | |
4534 | ir.addr -= 2; | |
4535 | opcode = opcode << 8 | ir.modrm; | |
4536 | goto no_support; | |
4537 | break; | |
4538 | } | |
4539 | } | |
0289bdd7 MS |
4540 | /* Opcode is an extension of modR/M byte. */ |
4541 | else | |
4542 | { | |
4543 | switch (opcode) | |
4544 | { | |
4545 | case 0xd8: | |
4546 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4547 | return -1; | |
4548 | break; | |
4549 | case 0xd9: | |
4550 | if (0x0c == (ir.modrm >> 4)) | |
4551 | { | |
4552 | if ((ir.modrm & 0x0f) <= 7) | |
4553 | { | |
4554 | if (i386_record_floats (gdbarch, &ir, | |
4555 | I386_SAVE_FPU_REGS)) | |
4556 | return -1; | |
4557 | } | |
4558 | else | |
4559 | { | |
4560 | if (i386_record_floats (gdbarch, &ir, | |
4561 | I387_ST0_REGNUM (tdep))) | |
4562 | return -1; | |
4563 | /* If only st(0) is changing, then we have already | |
4564 | recorded. */ | |
4565 | if ((ir.modrm & 0x0f) - 0x08) | |
4566 | { | |
4567 | if (i386_record_floats (gdbarch, &ir, | |
4568 | I387_ST0_REGNUM (tdep) + | |
4569 | ((ir.modrm & 0x0f) - 0x08))) | |
4570 | return -1; | |
4571 | } | |
4572 | } | |
4573 | } | |
4574 | else | |
4575 | { | |
4576 | switch (ir.modrm) | |
4577 | { | |
4578 | case 0xe0: | |
4579 | case 0xe1: | |
4580 | case 0xf0: | |
4581 | case 0xf5: | |
4582 | case 0xf8: | |
4583 | case 0xfa: | |
4584 | case 0xfc: | |
4585 | case 0xfe: | |
4586 | case 0xff: | |
4587 | if (i386_record_floats (gdbarch, &ir, | |
4588 | I387_ST0_REGNUM (tdep))) | |
4589 | return -1; | |
4590 | break; | |
4591 | case 0xf1: | |
4592 | case 0xf2: | |
4593 | case 0xf3: | |
4594 | case 0xf4: | |
4595 | case 0xf6: | |
4596 | case 0xf7: | |
4597 | case 0xe8: | |
4598 | case 0xe9: | |
4599 | case 0xea: | |
4600 | case 0xeb: | |
4601 | case 0xec: | |
4602 | case 0xed: | |
4603 | case 0xee: | |
4604 | case 0xf9: | |
4605 | case 0xfb: | |
4606 | if (i386_record_floats (gdbarch, &ir, | |
4607 | I386_SAVE_FPU_REGS)) | |
4608 | return -1; | |
4609 | break; | |
4610 | case 0xfd: | |
4611 | if (i386_record_floats (gdbarch, &ir, | |
4612 | I387_ST0_REGNUM (tdep))) | |
4613 | return -1; | |
4614 | if (i386_record_floats (gdbarch, &ir, | |
4615 | I387_ST0_REGNUM (tdep) + 1)) | |
4616 | return -1; | |
4617 | break; | |
4618 | } | |
4619 | } | |
4620 | break; | |
4621 | case 0xda: | |
4622 | if (0xe9 == ir.modrm) | |
4623 | { | |
4624 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4625 | return -1; | |
4626 | } | |
4627 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4628 | { | |
4629 | if (i386_record_floats (gdbarch, &ir, | |
4630 | I387_ST0_REGNUM (tdep))) | |
4631 | return -1; | |
4632 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4633 | { | |
4634 | if (i386_record_floats (gdbarch, &ir, | |
4635 | I387_ST0_REGNUM (tdep) + | |
4636 | (ir.modrm & 0x0f))) | |
4637 | return -1; | |
4638 | } | |
4639 | else if ((ir.modrm & 0x0f) - 0x08) | |
4640 | { | |
4641 | if (i386_record_floats (gdbarch, &ir, | |
4642 | I387_ST0_REGNUM (tdep) + | |
4643 | ((ir.modrm & 0x0f) - 0x08))) | |
4644 | return -1; | |
4645 | } | |
4646 | } | |
4647 | break; | |
4648 | case 0xdb: | |
4649 | if (0xe3 == ir.modrm) | |
4650 | { | |
4651 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
4652 | return -1; | |
4653 | } | |
4654 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4655 | { | |
4656 | if (i386_record_floats (gdbarch, &ir, | |
4657 | I387_ST0_REGNUM (tdep))) | |
4658 | return -1; | |
4659 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4660 | { | |
4661 | if (i386_record_floats (gdbarch, &ir, | |
4662 | I387_ST0_REGNUM (tdep) + | |
4663 | (ir.modrm & 0x0f))) | |
4664 | return -1; | |
4665 | } | |
4666 | else if ((ir.modrm & 0x0f) - 0x08) | |
4667 | { | |
4668 | if (i386_record_floats (gdbarch, &ir, | |
4669 | I387_ST0_REGNUM (tdep) + | |
4670 | ((ir.modrm & 0x0f) - 0x08))) | |
4671 | return -1; | |
4672 | } | |
4673 | } | |
4674 | break; | |
4675 | case 0xdc: | |
4676 | if ((0x0c == ir.modrm >> 4) | |
4677 | || (0x0d == ir.modrm >> 4) | |
4678 | || (0x0f == ir.modrm >> 4)) | |
4679 | { | |
4680 | if ((ir.modrm & 0x0f) <= 7) | |
4681 | { | |
4682 | if (i386_record_floats (gdbarch, &ir, | |
4683 | I387_ST0_REGNUM (tdep) + | |
4684 | (ir.modrm & 0x0f))) | |
4685 | return -1; | |
4686 | } | |
4687 | else | |
4688 | { | |
4689 | if (i386_record_floats (gdbarch, &ir, | |
4690 | I387_ST0_REGNUM (tdep) + | |
4691 | ((ir.modrm & 0x0f) - 0x08))) | |
4692 | return -1; | |
4693 | } | |
4694 | } | |
4695 | break; | |
4696 | case 0xdd: | |
4697 | if (0x0c == ir.modrm >> 4) | |
4698 | { | |
4699 | if (i386_record_floats (gdbarch, &ir, | |
4700 | I387_FTAG_REGNUM (tdep))) | |
4701 | return -1; | |
4702 | } | |
4703 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4704 | { | |
4705 | if ((ir.modrm & 0x0f) <= 7) | |
4706 | { | |
4707 | if (i386_record_floats (gdbarch, &ir, | |
4708 | I387_ST0_REGNUM (tdep) + | |
4709 | (ir.modrm & 0x0f))) | |
4710 | return -1; | |
4711 | } | |
4712 | else | |
4713 | { | |
4714 | if (i386_record_floats (gdbarch, &ir, | |
4715 | I386_SAVE_FPU_REGS)) | |
4716 | return -1; | |
4717 | } | |
4718 | } | |
4719 | break; | |
4720 | case 0xde: | |
4721 | if ((0x0c == ir.modrm >> 4) | |
4722 | || (0x0e == ir.modrm >> 4) | |
4723 | || (0x0f == ir.modrm >> 4) | |
4724 | || (0xd9 == ir.modrm)) | |
4725 | { | |
4726 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4727 | return -1; | |
4728 | } | |
4729 | break; | |
4730 | case 0xdf: | |
4731 | if (0xe0 == ir.modrm) | |
4732 | { | |
4733 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4734 | return -1; | |
4735 | } | |
4736 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4737 | { | |
4738 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4739 | return -1; | |
4740 | } | |
4741 | break; | |
4742 | } | |
4743 | } | |
7ad10968 | 4744 | break; |
7ad10968 | 4745 | /* string ops */ |
a38bba38 | 4746 | case 0xa4: /* movsS */ |
7ad10968 | 4747 | case 0xa5: |
a38bba38 | 4748 | case 0xaa: /* stosS */ |
7ad10968 | 4749 | case 0xab: |
a38bba38 | 4750 | case 0x6c: /* insS */ |
7ad10968 | 4751 | case 0x6d: |
cf648174 | 4752 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 4753 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
4754 | &addr); |
4755 | if (addr) | |
cf648174 | 4756 | { |
77d7dc92 HZ |
4757 | ULONGEST es, ds; |
4758 | ||
4759 | if ((opcode & 1) == 0) | |
4760 | ir.ot = OT_BYTE; | |
4761 | else | |
4762 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
4763 | regcache_raw_read_unsigned (ir.regcache, |
4764 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 4765 | &addr); |
77d7dc92 | 4766 | |
d7877f7e HZ |
4767 | regcache_raw_read_unsigned (ir.regcache, |
4768 | ir.regmap[X86_RECORD_ES_REGNUM], | |
4769 | &es); | |
4770 | regcache_raw_read_unsigned (ir.regcache, | |
4771 | ir.regmap[X86_RECORD_DS_REGNUM], | |
4772 | &ds); | |
4773 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
4774 | { |
4775 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
df61f520 | 4776 | warning (_("Process record ignores the memory " |
926569ae | 4777 | "change of instruction at address %s " |
df61f520 HZ |
4778 | "because it can't get the value of the " |
4779 | "ES segment register."), | |
4780 | paddress (gdbarch, ir.orig_addr)); | |
4781 | } | |
4782 | else | |
4783 | { | |
648d0c8b | 4784 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 4785 | return -1; |
77d7dc92 HZ |
4786 | } |
4787 | ||
4788 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4789 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
4790 | if (opcode == 0xa4 || opcode == 0xa5) |
4791 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4792 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4793 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4794 | } | |
cf648174 | 4795 | break; |
7ad10968 | 4796 | |
a38bba38 | 4797 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
4798 | case 0xa7: |
4799 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4800 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4801 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4802 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
4803 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4804 | break; |
4805 | ||
a38bba38 | 4806 | case 0xac: /* lodsS */ |
7ad10968 | 4807 | case 0xad: |
cf648174 HZ |
4808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4809 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4810 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4811 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4812 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4813 | break; |
4814 | ||
a38bba38 | 4815 | case 0xae: /* scasS */ |
7ad10968 | 4816 | case 0xaf: |
cf648174 | 4817 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 4818 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4819 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4820 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4821 | break; |
4822 | ||
a38bba38 | 4823 | case 0x6e: /* outsS */ |
cf648174 HZ |
4824 | case 0x6f: |
4825 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4826 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4827 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4828 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4829 | break; |
4830 | ||
a38bba38 | 4831 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
4832 | case 0xe5: |
4833 | case 0xec: | |
4834 | case 0xed: | |
cf648174 HZ |
4835 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4836 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4837 | break; |
4838 | ||
4839 | case 0xe6: | |
4840 | case 0xe7: | |
4841 | case 0xee: | |
4842 | case 0xef: | |
4843 | break; | |
4844 | ||
4845 | /* control */ | |
a38bba38 MS |
4846 | case 0xc2: /* ret im */ |
4847 | case 0xc3: /* ret */ | |
cf648174 HZ |
4848 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4849 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4850 | break; | |
4851 | ||
a38bba38 MS |
4852 | case 0xca: /* lret im */ |
4853 | case 0xcb: /* lret */ | |
4854 | case 0xcf: /* iret */ | |
cf648174 HZ |
4855 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4856 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4857 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4858 | break; |
4859 | ||
a38bba38 | 4860 | case 0xe8: /* call im */ |
cf648174 HZ |
4861 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4862 | ir.dflag = 2; | |
4863 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4864 | return -1; | |
7ad10968 HZ |
4865 | break; |
4866 | ||
a38bba38 | 4867 | case 0x9a: /* lcall im */ |
cf648174 HZ |
4868 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4869 | { | |
4870 | ir.addr -= 1; | |
4871 | goto no_support; | |
4872 | } | |
4873 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
4874 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4875 | return -1; | |
7ad10968 HZ |
4876 | break; |
4877 | ||
a38bba38 MS |
4878 | case 0xe9: /* jmp im */ |
4879 | case 0xea: /* ljmp im */ | |
4880 | case 0xeb: /* jmp Jb */ | |
4881 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
4882 | case 0x71: |
4883 | case 0x72: | |
4884 | case 0x73: | |
4885 | case 0x74: | |
4886 | case 0x75: | |
4887 | case 0x76: | |
4888 | case 0x77: | |
4889 | case 0x78: | |
4890 | case 0x79: | |
4891 | case 0x7a: | |
4892 | case 0x7b: | |
4893 | case 0x7c: | |
4894 | case 0x7d: | |
4895 | case 0x7e: | |
4896 | case 0x7f: | |
a38bba38 | 4897 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
4898 | case 0x0f81: |
4899 | case 0x0f82: | |
4900 | case 0x0f83: | |
4901 | case 0x0f84: | |
4902 | case 0x0f85: | |
4903 | case 0x0f86: | |
4904 | case 0x0f87: | |
4905 | case 0x0f88: | |
4906 | case 0x0f89: | |
4907 | case 0x0f8a: | |
4908 | case 0x0f8b: | |
4909 | case 0x0f8c: | |
4910 | case 0x0f8d: | |
4911 | case 0x0f8e: | |
4912 | case 0x0f8f: | |
4913 | break; | |
4914 | ||
a38bba38 | 4915 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
4916 | case 0x0f91: |
4917 | case 0x0f92: | |
4918 | case 0x0f93: | |
4919 | case 0x0f94: | |
4920 | case 0x0f95: | |
4921 | case 0x0f96: | |
4922 | case 0x0f97: | |
4923 | case 0x0f98: | |
4924 | case 0x0f99: | |
4925 | case 0x0f9a: | |
4926 | case 0x0f9b: | |
4927 | case 0x0f9c: | |
4928 | case 0x0f9d: | |
4929 | case 0x0f9e: | |
4930 | case 0x0f9f: | |
cf648174 | 4931 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4932 | ir.ot = OT_BYTE; |
4933 | if (i386_record_modrm (&ir)) | |
4934 | return -1; | |
4935 | if (ir.mod == 3) | |
cf648174 HZ |
4936 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
4937 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
4938 | else |
4939 | { | |
4940 | if (i386_record_lea_modrm (&ir)) | |
4941 | return -1; | |
4942 | } | |
4943 | break; | |
4944 | ||
a38bba38 | 4945 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
4946 | case 0x0f41: |
4947 | case 0x0f42: | |
4948 | case 0x0f43: | |
4949 | case 0x0f44: | |
4950 | case 0x0f45: | |
4951 | case 0x0f46: | |
4952 | case 0x0f47: | |
4953 | case 0x0f48: | |
4954 | case 0x0f49: | |
4955 | case 0x0f4a: | |
4956 | case 0x0f4b: | |
4957 | case 0x0f4c: | |
4958 | case 0x0f4d: | |
4959 | case 0x0f4e: | |
4960 | case 0x0f4f: | |
4961 | if (i386_record_modrm (&ir)) | |
4962 | return -1; | |
cf648174 | 4963 | ir.reg |= rex_r; |
7ad10968 HZ |
4964 | if (ir.dflag == OT_BYTE) |
4965 | ir.reg &= 0x3; | |
cf648174 | 4966 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4967 | break; |
4968 | ||
4969 | /* flags */ | |
a38bba38 | 4970 | case 0x9c: /* pushf */ |
cf648174 HZ |
4971 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4972 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4973 | ir.dflag = 2; | |
4974 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4975 | return -1; | |
7ad10968 HZ |
4976 | break; |
4977 | ||
a38bba38 | 4978 | case 0x9d: /* popf */ |
cf648174 HZ |
4979 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4980 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4981 | break; |
4982 | ||
a38bba38 | 4983 | case 0x9e: /* sahf */ |
cf648174 HZ |
4984 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4985 | { | |
4986 | ir.addr -= 1; | |
4987 | goto no_support; | |
4988 | } | |
a38bba38 MS |
4989 | case 0xf5: /* cmc */ |
4990 | case 0xf8: /* clc */ | |
4991 | case 0xf9: /* stc */ | |
4992 | case 0xfc: /* cld */ | |
4993 | case 0xfd: /* std */ | |
cf648174 | 4994 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4995 | break; |
4996 | ||
a38bba38 | 4997 | case 0x9f: /* lahf */ |
cf648174 HZ |
4998 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4999 | { | |
5000 | ir.addr -= 1; | |
5001 | goto no_support; | |
5002 | } | |
5003 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5004 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5005 | break; |
5006 | ||
5007 | /* bit operations */ | |
a38bba38 | 5008 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5009 | ir.ot = ir.dflag + OT_WORD; |
5010 | if (i386_record_modrm (&ir)) | |
5011 | return -1; | |
5012 | if (ir.reg < 4) | |
5013 | { | |
cf648174 | 5014 | ir.addr -= 2; |
7ad10968 HZ |
5015 | opcode = opcode << 8 | ir.modrm; |
5016 | goto no_support; | |
5017 | } | |
cf648174 | 5018 | if (ir.reg != 4) |
7ad10968 | 5019 | { |
cf648174 HZ |
5020 | if (ir.mod == 3) |
5021 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5022 | else |
5023 | { | |
cf648174 | 5024 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5025 | return -1; |
5026 | } | |
5027 | } | |
cf648174 | 5028 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5029 | break; |
5030 | ||
a38bba38 | 5031 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5032 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5033 | break; | |
5034 | ||
a38bba38 MS |
5035 | case 0x0fab: /* bts */ |
5036 | case 0x0fb3: /* btr */ | |
5037 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5038 | ir.ot = ir.dflag + OT_WORD; |
5039 | if (i386_record_modrm (&ir)) | |
5040 | return -1; | |
5041 | if (ir.mod == 3) | |
5042 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5043 | else | |
5044 | { | |
955db0c0 MS |
5045 | uint64_t addr64; |
5046 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
5047 | return -1; |
5048 | regcache_raw_read_unsigned (ir.regcache, | |
5049 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 5050 | &addr); |
cf648174 HZ |
5051 | switch (ir.dflag) |
5052 | { | |
5053 | case 0: | |
648d0c8b | 5054 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
5055 | break; |
5056 | case 1: | |
648d0c8b | 5057 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
5058 | break; |
5059 | case 2: | |
648d0c8b | 5060 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
5061 | break; |
5062 | } | |
955db0c0 | 5063 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
5064 | return -1; |
5065 | if (i386_record_lea_modrm (&ir)) | |
5066 | return -1; | |
5067 | } | |
5068 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5069 | break; |
5070 | ||
a38bba38 MS |
5071 | case 0x0fbc: /* bsf */ |
5072 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5073 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5074 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5075 | break; |
5076 | ||
5077 | /* bcd */ | |
a38bba38 MS |
5078 | case 0x27: /* daa */ |
5079 | case 0x2f: /* das */ | |
5080 | case 0x37: /* aaa */ | |
5081 | case 0x3f: /* aas */ | |
5082 | case 0xd4: /* aam */ | |
5083 | case 0xd5: /* aad */ | |
cf648174 HZ |
5084 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5085 | { | |
5086 | ir.addr -= 1; | |
5087 | goto no_support; | |
5088 | } | |
5089 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5090 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5091 | break; |
5092 | ||
5093 | /* misc */ | |
a38bba38 | 5094 | case 0x90: /* nop */ |
7ad10968 HZ |
5095 | if (prefixes & PREFIX_LOCK) |
5096 | { | |
5097 | ir.addr -= 1; | |
5098 | goto no_support; | |
5099 | } | |
5100 | break; | |
5101 | ||
a38bba38 | 5102 | case 0x9b: /* fwait */ |
425b824a | 5103 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
5104 | { |
5105 | if (record_debug) | |
5106 | printf_unfiltered (_("Process record: error reading memory at " | |
5107 | "addr 0x%s len = 1.\n"), | |
5108 | paddress (gdbarch, ir.addr)); | |
5109 | return -1; | |
5110 | } | |
425b824a | 5111 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
5112 | ir.addr++; |
5113 | goto reswitch; | |
7ad10968 HZ |
5114 | break; |
5115 | ||
7ad10968 | 5116 | /* XXX */ |
a38bba38 | 5117 | case 0xcc: /* int3 */ |
7ad10968 HZ |
5118 | printf_unfiltered (_("Process record doesn't support instruction " |
5119 | "int3.\n")); | |
5120 | ir.addr -= 1; | |
5121 | goto no_support; | |
5122 | break; | |
5123 | ||
7ad10968 | 5124 | /* XXX */ |
a38bba38 | 5125 | case 0xcd: /* int */ |
7ad10968 HZ |
5126 | { |
5127 | int ret; | |
425b824a MS |
5128 | uint8_t interrupt; |
5129 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
5130 | { |
5131 | if (record_debug) | |
5132 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5133 | "at addr %s len = 1.\n"), |
5134 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5135 | return -1; |
5136 | } | |
5137 | ir.addr++; | |
425b824a | 5138 | if (interrupt != 0x80 |
7ad10968 HZ |
5139 | || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) |
5140 | { | |
5141 | printf_unfiltered (_("Process record doesn't support " | |
5142 | "instruction int 0x%02x.\n"), | |
425b824a | 5143 | interrupt); |
7ad10968 HZ |
5144 | ir.addr -= 2; |
5145 | goto no_support; | |
5146 | } | |
5147 | ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); | |
5148 | if (ret) | |
5149 | return ret; | |
5150 | } | |
5151 | break; | |
5152 | ||
7ad10968 | 5153 | /* XXX */ |
a38bba38 | 5154 | case 0xce: /* into */ |
7ad10968 HZ |
5155 | printf_unfiltered (_("Process record doesn't support " |
5156 | "instruction into.\n")); | |
5157 | ir.addr -= 1; | |
5158 | goto no_support; | |
5159 | break; | |
5160 | ||
a38bba38 MS |
5161 | case 0xfa: /* cli */ |
5162 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5163 | break; |
5164 | ||
a38bba38 | 5165 | case 0x62: /* bound */ |
7ad10968 HZ |
5166 | printf_unfiltered (_("Process record doesn't support " |
5167 | "instruction bound.\n")); | |
5168 | ir.addr -= 1; | |
5169 | goto no_support; | |
5170 | break; | |
5171 | ||
a38bba38 | 5172 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5173 | case 0x0fc9: |
5174 | case 0x0fca: | |
5175 | case 0x0fcb: | |
5176 | case 0x0fcc: | |
5177 | case 0x0fcd: | |
5178 | case 0x0fce: | |
5179 | case 0x0fcf: | |
cf648174 | 5180 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5181 | break; |
5182 | ||
a38bba38 | 5183 | case 0xd6: /* salc */ |
cf648174 HZ |
5184 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5185 | { | |
5186 | ir.addr -= 1; | |
5187 | goto no_support; | |
5188 | } | |
5189 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5190 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5191 | break; |
5192 | ||
a38bba38 MS |
5193 | case 0xe0: /* loopnz */ |
5194 | case 0xe1: /* loopz */ | |
5195 | case 0xe2: /* loop */ | |
5196 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5197 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5198 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5199 | break; |
5200 | ||
a38bba38 | 5201 | case 0x0f30: /* wrmsr */ |
7ad10968 HZ |
5202 | printf_unfiltered (_("Process record doesn't support " |
5203 | "instruction wrmsr.\n")); | |
5204 | ir.addr -= 2; | |
5205 | goto no_support; | |
5206 | break; | |
5207 | ||
a38bba38 | 5208 | case 0x0f32: /* rdmsr */ |
7ad10968 HZ |
5209 | printf_unfiltered (_("Process record doesn't support " |
5210 | "instruction rdmsr.\n")); | |
5211 | ir.addr -= 2; | |
5212 | goto no_support; | |
5213 | break; | |
5214 | ||
a38bba38 | 5215 | case 0x0f31: /* rdtsc */ |
7ad10968 HZ |
5216 | printf_unfiltered (_("Process record doesn't support " |
5217 | "instruction rdtsc.\n")); | |
5218 | ir.addr -= 2; | |
5219 | goto no_support; | |
5220 | break; | |
5221 | ||
a38bba38 | 5222 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5223 | { |
5224 | int ret; | |
cf648174 HZ |
5225 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5226 | { | |
5227 | ir.addr -= 2; | |
5228 | goto no_support; | |
5229 | } | |
7ad10968 HZ |
5230 | if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) |
5231 | { | |
5232 | printf_unfiltered (_("Process record doesn't support " | |
5233 | "instruction sysenter.\n")); | |
5234 | ir.addr -= 2; | |
5235 | goto no_support; | |
5236 | } | |
5237 | ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); | |
5238 | if (ret) | |
5239 | return ret; | |
5240 | } | |
5241 | break; | |
5242 | ||
a38bba38 | 5243 | case 0x0f35: /* sysexit */ |
7ad10968 HZ |
5244 | printf_unfiltered (_("Process record doesn't support " |
5245 | "instruction sysexit.\n")); | |
5246 | ir.addr -= 2; | |
5247 | goto no_support; | |
5248 | break; | |
5249 | ||
a38bba38 | 5250 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5251 | { |
5252 | int ret; | |
5253 | if (gdbarch_tdep (gdbarch)->i386_syscall_record == NULL) | |
5254 | { | |
5255 | printf_unfiltered (_("Process record doesn't support " | |
5256 | "instruction syscall.\n")); | |
5257 | ir.addr -= 2; | |
5258 | goto no_support; | |
5259 | } | |
5260 | ret = gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache); | |
5261 | if (ret) | |
5262 | return ret; | |
5263 | } | |
5264 | break; | |
5265 | ||
a38bba38 | 5266 | case 0x0f07: /* sysret */ |
cf648174 HZ |
5267 | printf_unfiltered (_("Process record doesn't support " |
5268 | "instruction sysret.\n")); | |
5269 | ir.addr -= 2; | |
5270 | goto no_support; | |
5271 | break; | |
5272 | ||
a38bba38 | 5273 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5274 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5275 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5276 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5277 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5278 | break; |
5279 | ||
a38bba38 | 5280 | case 0xf4: /* hlt */ |
7ad10968 HZ |
5281 | printf_unfiltered (_("Process record doesn't support " |
5282 | "instruction hlt.\n")); | |
5283 | ir.addr -= 1; | |
5284 | goto no_support; | |
5285 | break; | |
5286 | ||
5287 | case 0x0f00: | |
5288 | if (i386_record_modrm (&ir)) | |
5289 | return -1; | |
5290 | switch (ir.reg) | |
5291 | { | |
a38bba38 MS |
5292 | case 0: /* sldt */ |
5293 | case 1: /* str */ | |
7ad10968 | 5294 | if (ir.mod == 3) |
cf648174 | 5295 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5296 | else |
5297 | { | |
5298 | ir.ot = OT_WORD; | |
5299 | if (i386_record_lea_modrm (&ir)) | |
5300 | return -1; | |
5301 | } | |
5302 | break; | |
a38bba38 MS |
5303 | case 2: /* lldt */ |
5304 | case 3: /* ltr */ | |
7ad10968 | 5305 | break; |
a38bba38 MS |
5306 | case 4: /* verr */ |
5307 | case 5: /* verw */ | |
cf648174 | 5308 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5309 | break; |
5310 | default: | |
5311 | ir.addr -= 3; | |
5312 | opcode = opcode << 8 | ir.modrm; | |
5313 | goto no_support; | |
5314 | break; | |
5315 | } | |
5316 | break; | |
5317 | ||
5318 | case 0x0f01: | |
5319 | if (i386_record_modrm (&ir)) | |
5320 | return -1; | |
5321 | switch (ir.reg) | |
5322 | { | |
a38bba38 | 5323 | case 0: /* sgdt */ |
7ad10968 | 5324 | { |
955db0c0 | 5325 | uint64_t addr64; |
7ad10968 HZ |
5326 | |
5327 | if (ir.mod == 3) | |
5328 | { | |
5329 | ir.addr -= 3; | |
5330 | opcode = opcode << 8 | ir.modrm; | |
5331 | goto no_support; | |
5332 | } | |
d7877f7e | 5333 | if (ir.override >= 0) |
7ad10968 | 5334 | { |
df61f520 HZ |
5335 | warning (_("Process record ignores the memory " |
5336 | "change of instruction at " | |
5337 | "address %s because it can't get " | |
5338 | "the value of the segment " | |
5339 | "register."), | |
5340 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5341 | } |
5342 | else | |
5343 | { | |
955db0c0 | 5344 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5345 | return -1; |
955db0c0 | 5346 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5347 | return -1; |
955db0c0 | 5348 | addr64 += 2; |
cf648174 HZ |
5349 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5350 | { | |
955db0c0 | 5351 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5352 | return -1; |
5353 | } | |
5354 | else | |
5355 | { | |
955db0c0 | 5356 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5357 | return -1; |
5358 | } | |
7ad10968 HZ |
5359 | } |
5360 | } | |
5361 | break; | |
5362 | case 1: | |
5363 | if (ir.mod == 3) | |
5364 | { | |
5365 | switch (ir.rm) | |
5366 | { | |
a38bba38 | 5367 | case 0: /* monitor */ |
7ad10968 | 5368 | break; |
a38bba38 | 5369 | case 1: /* mwait */ |
cf648174 | 5370 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5371 | break; |
5372 | default: | |
5373 | ir.addr -= 3; | |
5374 | opcode = opcode << 8 | ir.modrm; | |
5375 | goto no_support; | |
5376 | break; | |
5377 | } | |
5378 | } | |
5379 | else | |
5380 | { | |
5381 | /* sidt */ | |
d7877f7e | 5382 | if (ir.override >= 0) |
7ad10968 | 5383 | { |
df61f520 HZ |
5384 | warning (_("Process record ignores the memory " |
5385 | "change of instruction at " | |
5386 | "address %s because it can't get " | |
5387 | "the value of the segment " | |
5388 | "register."), | |
5389 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5390 | } |
5391 | else | |
5392 | { | |
955db0c0 | 5393 | uint64_t addr64; |
7ad10968 | 5394 | |
955db0c0 | 5395 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5396 | return -1; |
955db0c0 | 5397 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5398 | return -1; |
955db0c0 | 5399 | addr64 += 2; |
cf648174 HZ |
5400 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5401 | { | |
955db0c0 | 5402 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5403 | return -1; |
5404 | } | |
5405 | else | |
5406 | { | |
955db0c0 | 5407 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5408 | return -1; |
5409 | } | |
7ad10968 HZ |
5410 | } |
5411 | } | |
5412 | break; | |
a38bba38 | 5413 | case 2: /* lgdt */ |
3800e645 MS |
5414 | if (ir.mod == 3) |
5415 | { | |
5416 | /* xgetbv */ | |
5417 | if (ir.rm == 0) | |
5418 | { | |
5419 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5420 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5421 | break; | |
5422 | } | |
5423 | /* xsetbv */ | |
5424 | else if (ir.rm == 1) | |
5425 | break; | |
5426 | } | |
a38bba38 | 5427 | case 3: /* lidt */ |
7ad10968 HZ |
5428 | if (ir.mod == 3) |
5429 | { | |
5430 | ir.addr -= 3; | |
5431 | opcode = opcode << 8 | ir.modrm; | |
5432 | goto no_support; | |
5433 | } | |
5434 | break; | |
a38bba38 | 5435 | case 4: /* smsw */ |
7ad10968 HZ |
5436 | if (ir.mod == 3) |
5437 | { | |
cf648174 | 5438 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
5439 | return -1; |
5440 | } | |
5441 | else | |
5442 | { | |
5443 | ir.ot = OT_WORD; | |
5444 | if (i386_record_lea_modrm (&ir)) | |
5445 | return -1; | |
5446 | } | |
cf648174 | 5447 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5448 | break; |
a38bba38 | 5449 | case 6: /* lmsw */ |
cf648174 HZ |
5450 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5451 | break; | |
a38bba38 | 5452 | case 7: /* invlpg */ |
cf648174 HZ |
5453 | if (ir.mod == 3) |
5454 | { | |
5455 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
5456 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5457 | else | |
5458 | { | |
5459 | ir.addr -= 3; | |
5460 | opcode = opcode << 8 | ir.modrm; | |
5461 | goto no_support; | |
5462 | } | |
5463 | } | |
5464 | else | |
5465 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5466 | break; | |
5467 | default: | |
5468 | ir.addr -= 3; | |
5469 | opcode = opcode << 8 | ir.modrm; | |
5470 | goto no_support; | |
7ad10968 HZ |
5471 | break; |
5472 | } | |
5473 | break; | |
5474 | ||
a38bba38 MS |
5475 | case 0x0f08: /* invd */ |
5476 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
5477 | break; |
5478 | ||
a38bba38 | 5479 | case 0x63: /* arpl */ |
7ad10968 HZ |
5480 | if (i386_record_modrm (&ir)) |
5481 | return -1; | |
cf648174 HZ |
5482 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
5483 | { | |
5484 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
5485 | ? (ir.reg | rex_r) : ir.rm); | |
5486 | } | |
7ad10968 | 5487 | else |
cf648174 HZ |
5488 | { |
5489 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
5490 | if (i386_record_lea_modrm (&ir)) | |
5491 | return -1; | |
5492 | } | |
5493 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
5494 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5495 | break; |
5496 | ||
a38bba38 MS |
5497 | case 0x0f02: /* lar */ |
5498 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
5499 | if (i386_record_modrm (&ir)) |
5500 | return -1; | |
cf648174 HZ |
5501 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5502 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5503 | break; |
5504 | ||
5505 | case 0x0f18: | |
cf648174 HZ |
5506 | if (i386_record_modrm (&ir)) |
5507 | return -1; | |
5508 | if (ir.mod == 3 && ir.reg == 3) | |
5509 | { | |
5510 | ir.addr -= 3; | |
5511 | opcode = opcode << 8 | ir.modrm; | |
5512 | goto no_support; | |
5513 | } | |
7ad10968 HZ |
5514 | break; |
5515 | ||
7ad10968 HZ |
5516 | case 0x0f19: |
5517 | case 0x0f1a: | |
5518 | case 0x0f1b: | |
5519 | case 0x0f1c: | |
5520 | case 0x0f1d: | |
5521 | case 0x0f1e: | |
5522 | case 0x0f1f: | |
a38bba38 | 5523 | /* nop (multi byte) */ |
7ad10968 HZ |
5524 | break; |
5525 | ||
a38bba38 MS |
5526 | case 0x0f20: /* mov reg, crN */ |
5527 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
5528 | if (i386_record_modrm (&ir)) |
5529 | return -1; | |
5530 | if ((ir.modrm & 0xc0) != 0xc0) | |
5531 | { | |
cf648174 | 5532 | ir.addr -= 3; |
7ad10968 HZ |
5533 | opcode = opcode << 8 | ir.modrm; |
5534 | goto no_support; | |
5535 | } | |
5536 | switch (ir.reg) | |
5537 | { | |
5538 | case 0: | |
5539 | case 2: | |
5540 | case 3: | |
5541 | case 4: | |
5542 | case 8: | |
5543 | if (opcode & 2) | |
cf648174 | 5544 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5545 | else |
cf648174 | 5546 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5547 | break; |
5548 | default: | |
cf648174 | 5549 | ir.addr -= 3; |
7ad10968 HZ |
5550 | opcode = opcode << 8 | ir.modrm; |
5551 | goto no_support; | |
5552 | break; | |
5553 | } | |
5554 | break; | |
5555 | ||
a38bba38 MS |
5556 | case 0x0f21: /* mov reg, drN */ |
5557 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
5558 | if (i386_record_modrm (&ir)) |
5559 | return -1; | |
5560 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5561 | || ir.reg == 5 || ir.reg >= 8) | |
5562 | { | |
cf648174 | 5563 | ir.addr -= 3; |
7ad10968 HZ |
5564 | opcode = opcode << 8 | ir.modrm; |
5565 | goto no_support; | |
5566 | } | |
5567 | if (opcode & 2) | |
cf648174 | 5568 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5569 | else |
cf648174 | 5570 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5571 | break; |
5572 | ||
a38bba38 | 5573 | case 0x0f06: /* clts */ |
cf648174 | 5574 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5575 | break; |
5576 | ||
5577 | /* MMX/SSE/SSE2/PNI support */ | |
5578 | /* XXX */ | |
5579 | ||
5580 | default: | |
5581 | if (opcode > 0xff) | |
5582 | ir.addr -= 2; | |
5583 | else | |
5584 | ir.addr -= 1; | |
5585 | goto no_support; | |
5586 | break; | |
5587 | } | |
5588 | ||
cf648174 HZ |
5589 | /* In the future, maybe still need to deal with need_dasm. */ |
5590 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
5591 | if (record_arch_list_add_end ()) |
5592 | return -1; | |
5593 | ||
5594 | return 0; | |
5595 | ||
01fe1b41 | 5596 | no_support: |
7ad10968 | 5597 | printf_unfiltered (_("Process record doesn't support instruction 0x%02x " |
5af949e3 UW |
5598 | "at address %s.\n"), |
5599 | (unsigned int) (opcode), paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5600 | return -1; |
5601 | } | |
5602 | ||
cf648174 HZ |
5603 | static const int i386_record_regmap[] = |
5604 | { | |
5605 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
5606 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
5607 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5608 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
5609 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
5610 | }; | |
5611 | ||
7a697b8d SS |
5612 | /* Check that the given address appears suitable for a fast |
5613 | tracepoint, which on x86 means that we need an instruction of at | |
5614 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
5615 | jump and not have to worry about program jumps to an address in the | |
5616 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
5617 | of instruction to replace, and 0 if not, plus an explanatory | |
5618 | string. */ | |
5619 | ||
5620 | static int | |
5621 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
5622 | CORE_ADDR addr, int *isize, char **msg) | |
5623 | { | |
5624 | int len, jumplen; | |
5625 | static struct ui_file *gdb_null = NULL; | |
5626 | ||
5627 | /* This is based on the target agent using a 4-byte relative jump. | |
5628 | Alternate future possibilities include 8-byte offset for x86-84, | |
5629 | or 3-byte jumps if the program has trampoline space close by. */ | |
5630 | jumplen = 5; | |
5631 | ||
5632 | /* Dummy file descriptor for the disassembler. */ | |
5633 | if (!gdb_null) | |
5634 | gdb_null = ui_file_new (); | |
5635 | ||
5636 | /* Check for fit. */ | |
5637 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
5638 | if (len < jumplen) | |
5639 | { | |
5640 | /* Return a bit of target-specific detail to add to the caller's | |
5641 | generic failure message. */ | |
5642 | if (msg) | |
5643 | *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"), | |
5644 | len, jumplen); | |
5645 | return 0; | |
5646 | } | |
5647 | ||
5648 | if (isize) | |
5649 | *isize = len; | |
5650 | if (msg) | |
5651 | *msg = NULL; | |
5652 | return 1; | |
5653 | } | |
5654 | ||
90884b2b L |
5655 | static int |
5656 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
5657 | struct tdesc_arch_data *tdesc_data) | |
5658 | { | |
5659 | const struct target_desc *tdesc = tdep->tdesc; | |
5660 | const struct tdesc_feature *feature_core, *feature_vector; | |
5661 | int i, num_regs, valid_p; | |
5662 | ||
5663 | if (! tdesc_has_registers (tdesc)) | |
5664 | return 0; | |
5665 | ||
5666 | /* Get core registers. */ | |
5667 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
5668 | ||
5669 | /* Get SSE registers. */ | |
5670 | feature_vector = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); | |
5671 | ||
5672 | if (feature_core == NULL || feature_vector == NULL) | |
5673 | return 0; | |
5674 | ||
5675 | valid_p = 1; | |
5676 | ||
5677 | num_regs = tdep->num_core_regs; | |
5678 | for (i = 0; i < num_regs; i++) | |
5679 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
5680 | tdep->register_names[i]); | |
5681 | ||
5682 | /* Need to include %mxcsr, so add one. */ | |
5683 | num_regs += tdep->num_xmm_regs + 1; | |
5684 | for (; i < num_regs; i++) | |
5685 | valid_p &= tdesc_numbered_register (feature_vector, tdesc_data, i, | |
5686 | tdep->register_names[i]); | |
5687 | ||
5688 | return valid_p; | |
5689 | } | |
5690 | ||
7ad10968 HZ |
5691 | \f |
5692 | static struct gdbarch * | |
5693 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5694 | { | |
5695 | struct gdbarch_tdep *tdep; | |
5696 | struct gdbarch *gdbarch; | |
90884b2b L |
5697 | struct tdesc_arch_data *tdesc_data; |
5698 | const struct target_desc *tdesc; | |
1ba53b71 | 5699 | int mm0_regnum; |
7ad10968 HZ |
5700 | |
5701 | /* If there is already a candidate, use it. */ | |
5702 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
5703 | if (arches != NULL) | |
5704 | return arches->gdbarch; | |
5705 | ||
5706 | /* Allocate space for the new architecture. */ | |
5707 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
5708 | gdbarch = gdbarch_alloc (&info, tdep); | |
5709 | ||
5710 | /* General-purpose registers. */ | |
5711 | tdep->gregset = NULL; | |
5712 | tdep->gregset_reg_offset = NULL; | |
5713 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
5714 | tdep->sizeof_gregset = 0; | |
5715 | ||
5716 | /* Floating-point registers. */ | |
5717 | tdep->fpregset = NULL; | |
5718 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
5719 | ||
5720 | /* The default settings include the FPU registers, the MMX registers | |
5721 | and the SSE registers. This can be overridden for a specific ABI | |
5722 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
5723 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
5724 | will show up in the output of "info all-registers". Ideally we | |
5725 | should try to autodetect whether they are available, such that we | |
5726 | can prevent "info all-registers" from displaying registers that | |
5727 | aren't available. | |
5728 | ||
5729 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
5730 | [the SSE registers] always (even when they don't exist) or never | |
5731 | showing them to the user (even when they do exist), I prefer the | |
5732 | former over the latter. */ | |
5733 | ||
5734 | tdep->st0_regnum = I386_ST0_REGNUM; | |
5735 | ||
7ad10968 HZ |
5736 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
5737 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
5738 | ||
5739 | tdep->jb_pc_offset = -1; | |
5740 | tdep->struct_return = pcc_struct_return; | |
5741 | tdep->sigtramp_start = 0; | |
5742 | tdep->sigtramp_end = 0; | |
5743 | tdep->sigtramp_p = i386_sigtramp_p; | |
5744 | tdep->sigcontext_addr = NULL; | |
5745 | tdep->sc_reg_offset = NULL; | |
5746 | tdep->sc_pc_offset = -1; | |
5747 | tdep->sc_sp_offset = -1; | |
5748 | ||
cf648174 HZ |
5749 | tdep->record_regmap = i386_record_regmap; |
5750 | ||
7ad10968 HZ |
5751 | /* The format used for `long double' on almost all i386 targets is |
5752 | the i387 extended floating-point format. In fact, of all targets | |
5753 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
5754 | on having a `long double' that's not `long' at all. */ | |
5755 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
5756 | ||
5757 | /* Although the i387 extended floating-point has only 80 significant | |
5758 | bits, a `long double' actually takes up 96, probably to enforce | |
5759 | alignment. */ | |
5760 | set_gdbarch_long_double_bit (gdbarch, 96); | |
5761 | ||
7ad10968 HZ |
5762 | /* Register numbers of various important registers. */ |
5763 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
5764 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
5765 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
5766 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
5767 | ||
5768 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
5769 | numbering schemes on the i386: dbx and SVR4. These schemes | |
5770 | differ in how they number %ebp, %esp, %eflags, and the | |
5771 | floating-point registers, and are implemented by the arrays | |
5772 | dbx_register_map[] and svr4_dbx_register_map in | |
5773 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
5774 | gcc/config/i386.c, which it designates as the "default" register | |
5775 | map used in 64bit mode. This last register numbering scheme is | |
5776 | implemented in dbx64_register_map, and is used for AMD64; see | |
5777 | amd64-tdep.c. | |
5778 | ||
5779 | Currently, each GCC i386 target always uses the same register | |
5780 | numbering scheme across all its supported debugging formats | |
5781 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
5782 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
5783 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
5784 | respective config header in a manner independent of the requested | |
5785 | output debugging format. | |
5786 | ||
5787 | This does not match the arrangement below, which presumes that | |
5788 | the SDB and stabs numbering schemes differ from the DWARF and | |
5789 | DWARF 2 ones. The reason for this arrangement is that it is | |
5790 | likely to get the numbering scheme for the target's | |
5791 | default/native debug format right. For targets where GCC is the | |
5792 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
5793 | targets where the native toolchain uses a different numbering | |
5794 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
5795 | the defaults below will have to be overridden, like | |
5796 | i386_elf_init_abi() does. */ | |
5797 | ||
5798 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
5799 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5800 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5801 | ||
5802 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
5803 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
5804 | ||
5805 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
5806 | be in use on any of the supported i386 targets. */ | |
5807 | ||
5808 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
5809 | ||
5810 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
5811 | ||
5812 | /* Call dummy code. */ | |
5813 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
5814 | ||
5815 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
5816 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
5817 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
5818 | ||
5819 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
5820 | ||
5821 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
5822 | ||
5823 | /* Stack grows downward. */ | |
5824 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
5825 | ||
5826 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
5827 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
5828 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
5829 | ||
5830 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
5831 | ||
7ad10968 HZ |
5832 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
5833 | ||
5834 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
5835 | ||
5836 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
5837 | ||
5838 | /* Add the i386 register groups. */ | |
5839 | i386_add_reggroups (gdbarch); | |
90884b2b | 5840 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 5841 | |
143985b7 AF |
5842 | /* Helper for function argument information. */ |
5843 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
5844 | ||
06da04c6 MS |
5845 | /* Hook the function epilogue frame unwinder. This unwinder is |
5846 | appended to the list first, so that it supercedes the Dwarf | |
5847 | unwinder in function epilogues (where the Dwarf unwinder | |
5848 | currently fails). */ | |
5849 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
5850 | ||
5851 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
5852 | to the list before the prologue-based unwinders, so that Dwarf | |
5853 | CFI info will be used if it is available. */ | |
10458914 | 5854 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 5855 | |
acd5c798 | 5856 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 5857 | |
1ba53b71 | 5858 | /* Pseudo registers may be changed by amd64_init_abi. */ |
90884b2b L |
5859 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
5860 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
5861 | ||
5862 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
5863 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
5864 | ||
5865 | /* The default ABI includes general-purpose registers, | |
5866 | floating-point registers, and the SSE registers. */ | |
5867 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
5868 | ||
5869 | /* Get the x86 target description from INFO. */ | |
5870 | tdesc = info.target_desc; | |
5871 | if (! tdesc_has_registers (tdesc)) | |
5872 | tdesc = tdesc_i386; | |
5873 | tdep->tdesc = tdesc; | |
5874 | ||
5875 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
5876 | tdep->register_names = i386_register_names; | |
5877 | ||
1ba53b71 L |
5878 | tdep->num_byte_regs = 8; |
5879 | tdep->num_word_regs = 8; | |
5880 | tdep->num_dword_regs = 0; | |
5881 | tdep->num_mmx_regs = 8; | |
5882 | ||
90884b2b L |
5883 | tdesc_data = tdesc_data_alloc (); |
5884 | ||
3ce1502b | 5885 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 5886 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 5887 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 5888 | |
1ba53b71 L |
5889 | /* Wire in pseudo registers. Number of pseudo registers may be |
5890 | changed. */ | |
5891 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
5892 | + tdep->num_word_regs | |
5893 | + tdep->num_dword_regs | |
5894 | + tdep->num_mmx_regs)); | |
5895 | ||
90884b2b L |
5896 | /* Target description may be changed. */ |
5897 | tdesc = tdep->tdesc; | |
5898 | ||
5899 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) | |
5900 | { | |
5901 | tdesc_data_cleanup (tdesc_data); | |
5902 | xfree (tdep); | |
5903 | gdbarch_free (gdbarch); | |
5904 | return NULL; | |
5905 | } | |
5906 | ||
5907 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
5908 | ||
5909 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
5910 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
5911 | ||
1ba53b71 L |
5912 | /* Make %al the first pseudo-register. */ |
5913 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
5914 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
5915 | ||
5916 | mm0_regnum = tdep->ax_regnum + tdep->num_word_regs; | |
5917 | if (tdep->num_dword_regs) | |
5918 | { | |
5919 | /* Support dword pseudo-registesr if it hasn't been disabled, */ | |
5920 | tdep->eax_regnum = mm0_regnum; | |
5921 | mm0_regnum = tdep->eax_regnum + tdep->num_dword_regs; | |
5922 | } | |
5923 | else | |
5924 | tdep->eax_regnum = -1; | |
5925 | ||
5926 | if (tdep->num_mmx_regs != 0) | |
5927 | { | |
5928 | /* Support MMX pseudo-registesr if MMX hasn't been disabled, */ | |
5929 | tdep->mm0_regnum = mm0_regnum; | |
5930 | } | |
5931 | else | |
5932 | tdep->mm0_regnum = -1; | |
5933 | ||
06da04c6 | 5934 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
10458914 DJ |
5935 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
5936 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 5937 | |
8446b36a MK |
5938 | /* If we have a register mapping, enable the generic core file |
5939 | support, unless it has already been enabled. */ | |
5940 | if (tdep->gregset_reg_offset | |
5941 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
5942 | set_gdbarch_regset_from_core_section (gdbarch, | |
5943 | i386_regset_from_core_section); | |
5944 | ||
514f746b AR |
5945 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
5946 | i386_skip_permanent_breakpoint); | |
5947 | ||
7a697b8d SS |
5948 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
5949 | i386_fast_tracepoint_valid_at); | |
5950 | ||
a62cc96e AC |
5951 | return gdbarch; |
5952 | } | |
5953 | ||
8201327c MK |
5954 | static enum gdb_osabi |
5955 | i386_coff_osabi_sniffer (bfd *abfd) | |
5956 | { | |
762c5349 MK |
5957 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
5958 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
5959 | return GDB_OSABI_GO32; |
5960 | ||
5961 | return GDB_OSABI_UNKNOWN; | |
5962 | } | |
8201327c MK |
5963 | \f |
5964 | ||
28e9e0f0 MK |
5965 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
5966 | void _initialize_i386_tdep (void); | |
5967 | ||
c906108c | 5968 | void |
fba45db2 | 5969 | _initialize_i386_tdep (void) |
c906108c | 5970 | { |
a62cc96e AC |
5971 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
5972 | ||
fc338970 | 5973 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
5974 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
5975 | &disassembly_flavor, _("\ | |
5976 | Set the disassembly flavor."), _("\ | |
5977 | Show the disassembly flavor."), _("\ | |
5978 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
5979 | NULL, | |
5980 | NULL, /* FIXME: i18n: */ | |
5981 | &setlist, &showlist); | |
8201327c MK |
5982 | |
5983 | /* Add the variable that controls the convention for returning | |
5984 | structs. */ | |
7ab04401 AC |
5985 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
5986 | &struct_convention, _("\ | |
5987 | Set the convention for returning small structs."), _("\ | |
5988 | Show the convention for returning small structs."), _("\ | |
5989 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
5990 | is \"default\"."), | |
5991 | NULL, | |
5992 | NULL, /* FIXME: i18n: */ | |
5993 | &setlist, &showlist); | |
8201327c MK |
5994 | |
5995 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
5996 | i386_coff_osabi_sniffer); | |
8201327c | 5997 | |
05816f70 | 5998 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 5999 | i386_svr4_init_abi); |
05816f70 | 6000 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 6001 | i386_go32_init_abi); |
38c968cf | 6002 | |
209bd28e | 6003 | /* Initialize the i386-specific register groups. */ |
38c968cf | 6004 | i386_init_reggroups (); |
90884b2b L |
6005 | |
6006 | /* Initialize the standard target descriptions. */ | |
6007 | initialize_tdesc_i386 (); | |
c906108c | 6008 | } |