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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
f9f0c9e2 BZ |
11 | * |
12 | * VT8231 south bridge support and general clean up to allow it | |
13 | * Copyright (c) 2018-2020 BALATON Zoltan | |
edf79e66 HC |
14 | */ |
15 | ||
0430891c | 16 | #include "qemu/osdep.h" |
0d09e41a | 17 | #include "hw/isa/vt82c686.h" |
83c9f4ca | 18 | #include "hw/pci/pci.h" |
a27bd6c7 | 19 | #include "hw/qdev-properties.h" |
9eb6abbf | 20 | #include "hw/ide/pci.h" |
0d09e41a | 21 | #include "hw/isa/isa.h" |
98cf824b | 22 | #include "hw/isa/superio.h" |
3dc31cb8 BZ |
23 | #include "hw/intc/i8259.h" |
24 | #include "hw/irq.h" | |
25 | #include "hw/dma/i8257.h" | |
26 | #include "hw/timer/i8254.h" | |
27 | #include "hw/rtc/mc146818rtc.h" | |
d6454270 | 28 | #include "migration/vmstate.h" |
0d09e41a PB |
29 | #include "hw/isa/apm.h" |
30 | #include "hw/acpi/acpi.h" | |
31 | #include "hw/i2c/pm_smbus.h" | |
9307d06d | 32 | #include "qapi/error.h" |
2c4c556e | 33 | #include "qemu/log.h" |
0b8fa32f | 34 | #include "qemu/module.h" |
911629e6 | 35 | #include "qemu/range.h" |
1de7afc9 | 36 | #include "qemu/timer.h" |
ff413a1f | 37 | #include "trace.h" |
edf79e66 | 38 | |
e1a69736 BZ |
39 | #define TYPE_VIA_PM "via-pm" |
40 | OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) | |
edf79e66 | 41 | |
e1a69736 | 42 | struct ViaPMState { |
edf79e66 | 43 | PCIDevice dev; |
a2902821 | 44 | MemoryRegion io; |
355bf2e5 | 45 | ACPIREGS ar; |
edf79e66 | 46 | APMState apm; |
edf79e66 | 47 | PMSMBus smb; |
db1015e9 | 48 | }; |
edf79e66 | 49 | |
e1a69736 | 50 | static void pm_io_space_update(ViaPMState *s) |
edf79e66 | 51 | { |
3ab1eea6 | 52 | uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; |
edf79e66 | 53 | |
a2902821 | 54 | memory_region_transaction_begin(); |
3ab1eea6 BZ |
55 | memory_region_set_address(&s->io, pmbase); |
56 | memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); | |
a2902821 | 57 | memory_region_transaction_commit(); |
edf79e66 HC |
58 | } |
59 | ||
e1a69736 | 60 | static void smb_io_space_update(ViaPMState *s) |
911629e6 BZ |
61 | { |
62 | uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; | |
63 | ||
64 | memory_region_transaction_begin(); | |
65 | memory_region_set_address(&s->smb.io, smbase); | |
66 | memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); | |
67 | memory_region_transaction_commit(); | |
68 | } | |
69 | ||
edf79e66 HC |
70 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
71 | { | |
e1a69736 | 72 | ViaPMState *s = opaque; |
edf79e66 HC |
73 | |
74 | pm_io_space_update(s); | |
911629e6 | 75 | smb_io_space_update(s); |
edf79e66 HC |
76 | return 0; |
77 | } | |
78 | ||
79 | static const VMStateDescription vmstate_acpi = { | |
80 | .name = "vt82c686b_pm", | |
81 | .version_id = 1, | |
82 | .minimum_version_id = 1, | |
edf79e66 | 83 | .post_load = vmstate_acpi_post_load, |
d49805ae | 84 | .fields = (VMStateField[]) { |
e1a69736 BZ |
85 | VMSTATE_PCI_DEVICE(dev, ViaPMState), |
86 | VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), | |
87 | VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), | |
88 | VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), | |
89 | VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), | |
90 | VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), | |
91 | VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), | |
edf79e66 HC |
92 | VMSTATE_END_OF_LIST() |
93 | } | |
94 | }; | |
95 | ||
94349bff BZ |
96 | static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) |
97 | { | |
e1a69736 | 98 | ViaPMState *s = VIA_PM(d); |
911629e6 | 99 | |
94349bff BZ |
100 | trace_via_pm_write(addr, val, len); |
101 | pci_default_write_config(d, addr, val, len); | |
3ab1eea6 BZ |
102 | if (ranges_overlap(addr, len, 0x48, 4)) { |
103 | uint32_t v = pci_get_long(s->dev.config + 0x48); | |
104 | pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); | |
105 | } | |
106 | if (range_covers_byte(addr, len, 0x41)) { | |
107 | pm_io_space_update(s); | |
108 | } | |
911629e6 BZ |
109 | if (ranges_overlap(addr, len, 0x90, 4)) { |
110 | uint32_t v = pci_get_long(s->dev.config + 0x90); | |
111 | pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); | |
112 | } | |
113 | if (range_covers_byte(addr, len, 0xd2)) { | |
114 | s->dev.config[0xd2] &= 0xf; | |
115 | smb_io_space_update(s); | |
116 | } | |
94349bff BZ |
117 | } |
118 | ||
35e360ed BZ |
119 | static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) |
120 | { | |
121 | trace_via_pm_io_write(addr, data, size); | |
122 | } | |
123 | ||
124 | static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) | |
125 | { | |
126 | trace_via_pm_io_read(addr, 0, size); | |
127 | return 0; | |
128 | } | |
129 | ||
130 | static const MemoryRegionOps pm_io_ops = { | |
131 | .read = pm_io_read, | |
132 | .write = pm_io_write, | |
133 | .endianness = DEVICE_NATIVE_ENDIAN, | |
134 | .impl = { | |
135 | .min_access_size = 1, | |
136 | .max_access_size = 1, | |
137 | }, | |
138 | }; | |
139 | ||
e1a69736 | 140 | static void pm_update_sci(ViaPMState *s) |
94349bff BZ |
141 | { |
142 | int sci_level, pmsts; | |
143 | ||
144 | pmsts = acpi_pm1_evt_get_sts(&s->ar); | |
145 | sci_level = (((pmsts & s->ar.pm1.evt.en) & | |
146 | (ACPI_BITMASK_RT_CLOCK_ENABLE | | |
147 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
148 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
149 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
0fae92a3 IY |
150 | if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) { |
151 | /* | |
152 | * FIXME: | |
153 | * Fix device model that realizes this PM device and remove | |
154 | * this work around. | |
155 | * The device model should wire SCI and setup | |
156 | * PCI_INTERRUPT_PIN properly. | |
157 | * If PIN# = 0(interrupt pin isn't used), don't raise SCI as | |
158 | * work around. | |
159 | */ | |
160 | pci_set_irq(&s->dev, sci_level); | |
161 | } | |
94349bff BZ |
162 | /* schedule a timer interruption if needed */ |
163 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && | |
164 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); | |
165 | } | |
166 | ||
167 | static void pm_tmr_timer(ACPIREGS *ar) | |
168 | { | |
e1a69736 | 169 | ViaPMState *s = container_of(ar, ViaPMState, ar); |
94349bff BZ |
170 | pm_update_sci(s); |
171 | } | |
172 | ||
e1a69736 | 173 | static void via_pm_reset(DeviceState *d) |
911629e6 | 174 | { |
e1a69736 | 175 | ViaPMState *s = VIA_PM(d); |
911629e6 | 176 | |
9af8e529 BZ |
177 | memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, |
178 | PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); | |
179 | /* Power Management IO base */ | |
180 | pci_set_long(s->dev.config + 0x48, 1); | |
911629e6 BZ |
181 | /* SMBus IO base */ |
182 | pci_set_long(s->dev.config + 0x90, 1); | |
911629e6 | 183 | |
44421c60 IY |
184 | acpi_pm1_evt_reset(&s->ar); |
185 | acpi_pm1_cnt_reset(&s->ar); | |
186 | acpi_pm_tmr_reset(&s->ar); | |
187 | pm_update_sci(s); | |
188 | ||
3ab1eea6 | 189 | pm_io_space_update(s); |
911629e6 BZ |
190 | smb_io_space_update(s); |
191 | } | |
192 | ||
e1a69736 | 193 | static void via_pm_realize(PCIDevice *dev, Error **errp) |
edf79e66 | 194 | { |
e1a69736 | 195 | ViaPMState *s = VIA_PM(dev); |
edf79e66 | 196 | |
3ab1eea6 | 197 | pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | |
edf79e66 HC |
198 | PCI_STATUS_DEVSEL_MEDIUM); |
199 | ||
a30c34d2 | 200 | pm_smbus_init(DEVICE(s), &s->smb, false); |
911629e6 BZ |
201 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); |
202 | memory_region_set_enabled(&s->smb.io, false); | |
edf79e66 | 203 | |
42d8a3cf | 204 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 205 | |
e1a69736 | 206 | memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); |
35e360ed | 207 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); |
a2902821 | 208 | memory_region_set_enabled(&s->io, false); |
edf79e66 | 209 | |
77d58b1e | 210 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 211 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
6be8cf56 | 212 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); |
edf79e66 HC |
213 | } |
214 | ||
e1a69736 BZ |
215 | typedef struct via_pm_init_info { |
216 | uint16_t device_id; | |
217 | } ViaPMInitInfo; | |
218 | ||
40021f08 AL |
219 | static void via_pm_class_init(ObjectClass *klass, void *data) |
220 | { | |
39bffca2 | 221 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 222 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
e1a69736 | 223 | ViaPMInitInfo *info = data; |
40021f08 | 224 | |
e1a69736 | 225 | k->realize = via_pm_realize; |
40021f08 AL |
226 | k->config_write = pm_write_config; |
227 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
e1a69736 | 228 | k->device_id = info->device_id; |
40021f08 AL |
229 | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
230 | k->revision = 0x40; | |
e1a69736 | 231 | dc->reset = via_pm_reset; |
084bf4b4 BZ |
232 | /* Reason: part of VIA south bridge, does not exist stand alone */ |
233 | dc->user_creatable = false; | |
39bffca2 | 234 | dc->vmsd = &vmstate_acpi; |
40021f08 AL |
235 | } |
236 | ||
8c43a6f0 | 237 | static const TypeInfo via_pm_info = { |
e1a69736 | 238 | .name = TYPE_VIA_PM, |
39bffca2 | 239 | .parent = TYPE_PCI_DEVICE, |
e1a69736 BZ |
240 | .instance_size = sizeof(ViaPMState), |
241 | .abstract = true, | |
fd3b02c8 EH |
242 | .interfaces = (InterfaceInfo[]) { |
243 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
244 | { }, | |
245 | }, | |
edf79e66 HC |
246 | }; |
247 | ||
e1a69736 BZ |
248 | static const ViaPMInitInfo vt82c686b_pm_init_info = { |
249 | .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, | |
250 | }; | |
251 | ||
252 | static const TypeInfo vt82c686b_pm_info = { | |
253 | .name = TYPE_VT82C686B_PM, | |
254 | .parent = TYPE_VIA_PM, | |
255 | .class_init = via_pm_class_init, | |
256 | .class_data = (void *)&vt82c686b_pm_init_info, | |
257 | }; | |
258 | ||
259 | static const ViaPMInitInfo vt8231_pm_init_info = { | |
260 | .device_id = PCI_DEVICE_ID_VIA_8231_PM, | |
261 | }; | |
262 | ||
263 | static const TypeInfo vt8231_pm_info = { | |
264 | .name = TYPE_VT8231_PM, | |
265 | .parent = TYPE_VIA_PM, | |
266 | .class_init = via_pm_class_init, | |
267 | .class_data = (void *)&vt8231_pm_init_info, | |
268 | }; | |
269 | ||
94349bff | 270 | |
f028c2de BZ |
271 | #define TYPE_VIA_SUPERIO "via-superio" |
272 | OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO) | |
273 | ||
274 | struct ViaSuperIOState { | |
275 | ISASuperIODevice superio; | |
94349bff | 276 | uint8_t regs[0x100]; |
f028c2de | 277 | const MemoryRegionOps *io_ops; |
94349bff | 278 | MemoryRegion io; |
f028c2de BZ |
279 | }; |
280 | ||
281 | static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable) | |
282 | { | |
283 | memory_region_set_enabled(&s->io, enable); | |
284 | } | |
285 | ||
286 | static void via_superio_realize(DeviceState *d, Error **errp) | |
287 | { | |
288 | ViaSuperIOState *s = VIA_SUPERIO(d); | |
289 | ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s); | |
290 | Error *local_err = NULL; | |
291 | ||
292 | assert(s->io_ops); | |
293 | ic->parent_realize(d, &local_err); | |
294 | if (local_err) { | |
295 | error_propagate(errp, local_err); | |
296 | return; | |
297 | } | |
298 | memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2); | |
299 | memory_region_set_enabled(&s->io, false); | |
300 | /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */ | |
301 | memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0, | |
302 | &s->io); | |
303 | } | |
304 | ||
305 | static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size) | |
306 | { | |
307 | ViaSuperIOState *sc = opaque; | |
308 | uint8_t idx = sc->regs[0]; | |
309 | uint8_t val = sc->regs[idx]; | |
310 | ||
311 | if (addr == 0) { | |
312 | return idx; | |
313 | } | |
314 | if (addr == 1 && idx == 0) { | |
315 | val = 0; /* reading reg 0 where we store index value */ | |
316 | } | |
317 | trace_via_superio_read(idx, val); | |
318 | return val; | |
319 | } | |
94349bff | 320 | |
f028c2de | 321 | static void via_superio_class_init(ObjectClass *klass, void *data) |
94349bff | 322 | { |
f028c2de BZ |
323 | DeviceClass *dc = DEVICE_CLASS(klass); |
324 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
325 | ||
326 | sc->parent_realize = dc->realize; | |
327 | dc->realize = via_superio_realize; | |
328 | } | |
329 | ||
330 | static const TypeInfo via_superio_info = { | |
331 | .name = TYPE_VIA_SUPERIO, | |
332 | .parent = TYPE_ISA_SUPERIO, | |
333 | .instance_size = sizeof(ViaSuperIOState), | |
334 | .class_size = sizeof(ISASuperIOClass), | |
335 | .class_init = via_superio_class_init, | |
336 | .abstract = true, | |
337 | }; | |
338 | ||
339 | #define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" | |
94349bff | 340 | |
f028c2de BZ |
341 | static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr, |
342 | uint64_t data, unsigned size) | |
94349bff | 343 | { |
f028c2de | 344 | ViaSuperIOState *sc = opaque; |
c953bf71 | 345 | uint8_t idx = sc->regs[0]; |
94349bff | 346 | |
cc2b4550 BZ |
347 | if (addr == 0) { /* config index register */ |
348 | sc->regs[0] = data; | |
2b98dca9 BZ |
349 | return; |
350 | } | |
cc2b4550 BZ |
351 | |
352 | /* config data register */ | |
353 | trace_via_superio_write(idx, data); | |
2b98dca9 BZ |
354 | switch (idx) { |
355 | case 0x00 ... 0xdf: | |
356 | case 0xe4: | |
357 | case 0xe5: | |
358 | case 0xe9 ... 0xed: | |
359 | case 0xf3: | |
360 | case 0xf5: | |
361 | case 0xf7: | |
362 | case 0xf9 ... 0xfb: | |
363 | case 0xfd ... 0xff: | |
b7741b77 BZ |
364 | /* ignore write to read only registers */ |
365 | return; | |
2b98dca9 BZ |
366 | /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ |
367 | default: | |
2c4c556e BZ |
368 | qemu_log_mask(LOG_UNIMP, |
369 | "via_superio_cfg: unimplemented register 0x%x\n", idx); | |
2b98dca9 BZ |
370 | break; |
371 | } | |
cc2b4550 | 372 | sc->regs[idx] = data; |
94349bff BZ |
373 | } |
374 | ||
f028c2de BZ |
375 | static const MemoryRegionOps vt82c686b_superio_cfg_ops = { |
376 | .read = via_superio_cfg_read, | |
377 | .write = vt82c686b_superio_cfg_write, | |
94349bff BZ |
378 | .endianness = DEVICE_NATIVE_ENDIAN, |
379 | .impl = { | |
380 | .min_access_size = 1, | |
381 | .max_access_size = 1, | |
382 | }, | |
383 | }; | |
384 | ||
f028c2de BZ |
385 | static void vt82c686b_superio_reset(DeviceState *dev) |
386 | { | |
387 | ViaSuperIOState *s = VIA_SUPERIO(dev); | |
388 | ||
389 | memset(s->regs, 0, sizeof(s->regs)); | |
390 | /* Device ID */ | |
391 | vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); | |
392 | vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); | |
393 | /* Function select - all disabled */ | |
394 | vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); | |
395 | vt82c686b_superio_cfg_write(s, 1, 0x03, 1); | |
396 | /* Floppy ctrl base addr 0x3f0-7 */ | |
397 | vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); | |
398 | vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); | |
399 | /* Parallel port base addr 0x378-f */ | |
400 | vt82c686b_superio_cfg_write(s, 0, 0xe6, 1); | |
401 | vt82c686b_superio_cfg_write(s, 1, 0xde, 1); | |
402 | /* Serial port 1 base addr 0x3f8-f */ | |
403 | vt82c686b_superio_cfg_write(s, 0, 0xe7, 1); | |
404 | vt82c686b_superio_cfg_write(s, 1, 0xfe, 1); | |
405 | /* Serial port 2 base addr 0x2f8-f */ | |
406 | vt82c686b_superio_cfg_write(s, 0, 0xe8, 1); | |
407 | vt82c686b_superio_cfg_write(s, 1, 0xbe, 1); | |
408 | ||
409 | vt82c686b_superio_cfg_write(s, 0, 0, 1); | |
410 | } | |
411 | ||
412 | static void vt82c686b_superio_init(Object *obj) | |
413 | { | |
414 | VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops; | |
415 | } | |
416 | ||
417 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) | |
94349bff | 418 | { |
f028c2de BZ |
419 | DeviceClass *dc = DEVICE_CLASS(klass); |
420 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
421 | ||
422 | dc->reset = vt82c686b_superio_reset; | |
423 | sc->serial.count = 2; | |
424 | sc->parallel.count = 1; | |
425 | sc->ide.count = 0; /* emulated by via-ide */ | |
426 | sc->floppy.count = 1; | |
427 | } | |
428 | ||
429 | static const TypeInfo vt82c686b_superio_info = { | |
430 | .name = TYPE_VT82C686B_SUPERIO, | |
431 | .parent = TYPE_VIA_SUPERIO, | |
432 | .instance_size = sizeof(ViaSuperIOState), | |
433 | .instance_init = vt82c686b_superio_init, | |
434 | .class_size = sizeof(ISASuperIOClass), | |
435 | .class_init = vt82c686b_superio_class_init, | |
436 | }; | |
437 | ||
94349bff | 438 | |
ab74864f BZ |
439 | #define TYPE_VT8231_SUPERIO "vt8231-superio" |
440 | ||
441 | static void vt8231_superio_cfg_write(void *opaque, hwaddr addr, | |
442 | uint64_t data, unsigned size) | |
443 | { | |
444 | ViaSuperIOState *sc = opaque; | |
c953bf71 | 445 | uint8_t idx = sc->regs[0]; |
94349bff | 446 | |
ab74864f BZ |
447 | if (addr == 0) { /* config index register */ |
448 | sc->regs[0] = data; | |
449 | return; | |
c953bf71 | 450 | } |
ab74864f BZ |
451 | |
452 | /* config data register */ | |
453 | trace_via_superio_write(idx, data); | |
454 | switch (idx) { | |
455 | case 0x00 ... 0xdf: | |
456 | case 0xe7 ... 0xef: | |
457 | case 0xf0 ... 0xf1: | |
458 | case 0xf5: | |
459 | case 0xf8: | |
460 | case 0xfd: | |
461 | /* ignore write to read only registers */ | |
462 | return; | |
463 | default: | |
464 | qemu_log_mask(LOG_UNIMP, | |
465 | "via_superio_cfg: unimplemented register 0x%x\n", idx); | |
466 | break; | |
c953bf71 | 467 | } |
ab74864f | 468 | sc->regs[idx] = data; |
94349bff BZ |
469 | } |
470 | ||
ab74864f BZ |
471 | static const MemoryRegionOps vt8231_superio_cfg_ops = { |
472 | .read = via_superio_cfg_read, | |
473 | .write = vt8231_superio_cfg_write, | |
94349bff BZ |
474 | .endianness = DEVICE_NATIVE_ENDIAN, |
475 | .impl = { | |
476 | .min_access_size = 1, | |
477 | .max_access_size = 1, | |
478 | }, | |
479 | }; | |
480 | ||
ab74864f BZ |
481 | static void vt8231_superio_reset(DeviceState *dev) |
482 | { | |
483 | ViaSuperIOState *s = VIA_SUPERIO(dev); | |
484 | ||
485 | memset(s->regs, 0, sizeof(s->regs)); | |
486 | /* Device ID */ | |
487 | s->regs[0xf0] = 0x3c; | |
488 | /* Device revision */ | |
489 | s->regs[0xf1] = 0x01; | |
490 | /* Function select - all disabled */ | |
491 | vt8231_superio_cfg_write(s, 0, 0xf2, 1); | |
492 | vt8231_superio_cfg_write(s, 1, 0x03, 1); | |
493 | /* Serial port base addr */ | |
494 | vt8231_superio_cfg_write(s, 0, 0xf4, 1); | |
495 | vt8231_superio_cfg_write(s, 1, 0xfe, 1); | |
496 | /* Parallel port base addr */ | |
497 | vt8231_superio_cfg_write(s, 0, 0xf6, 1); | |
498 | vt8231_superio_cfg_write(s, 1, 0xde, 1); | |
499 | /* Floppy ctrl base addr */ | |
500 | vt8231_superio_cfg_write(s, 0, 0xf7, 1); | |
501 | vt8231_superio_cfg_write(s, 1, 0xfc, 1); | |
502 | ||
503 | vt8231_superio_cfg_write(s, 0, 0, 1); | |
504 | } | |
505 | ||
506 | static void vt8231_superio_init(Object *obj) | |
507 | { | |
508 | VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops; | |
509 | } | |
94349bff | 510 | |
ab74864f BZ |
511 | static uint16_t vt8231_superio_serial_iobase(ISASuperIODevice *sio, |
512 | uint8_t index) | |
513 | { | |
514 | return 0x2f8; /* FIXME: This should be settable via registers f2-f4 */ | |
515 | } | |
94349bff | 516 | |
ab74864f BZ |
517 | static void vt8231_superio_class_init(ObjectClass *klass, void *data) |
518 | { | |
519 | DeviceClass *dc = DEVICE_CLASS(klass); | |
520 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
521 | ||
522 | dc->reset = vt8231_superio_reset; | |
523 | sc->serial.count = 1; | |
524 | sc->serial.get_iobase = vt8231_superio_serial_iobase; | |
525 | sc->parallel.count = 1; | |
526 | sc->ide.count = 0; /* emulated by via-ide */ | |
527 | sc->floppy.count = 1; | |
528 | } | |
529 | ||
530 | static const TypeInfo vt8231_superio_info = { | |
531 | .name = TYPE_VT8231_SUPERIO, | |
532 | .parent = TYPE_VIA_SUPERIO, | |
533 | .instance_size = sizeof(ViaSuperIOState), | |
534 | .instance_init = vt8231_superio_init, | |
535 | .class_size = sizeof(ISASuperIOClass), | |
536 | .class_init = vt8231_superio_class_init, | |
537 | }; | |
538 | ||
539 | ||
2e84e107 BZ |
540 | #define TYPE_VIA_ISA "via-isa" |
541 | OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA) | |
94349bff | 542 | |
2e84e107 | 543 | struct ViaISAState { |
94349bff | 544 | PCIDevice dev; |
3dc31cb8 | 545 | qemu_irq cpu_intr; |
a4d65b70 | 546 | qemu_irq *isa_irqs; |
8e4022a8 | 547 | ViaSuperIOState via_sio; |
9eb6abbf | 548 | PCIIDEState ide; |
94349bff BZ |
549 | }; |
550 | ||
2e84e107 BZ |
551 | static const VMStateDescription vmstate_via = { |
552 | .name = "via-isa", | |
553 | .version_id = 1, | |
554 | .minimum_version_id = 1, | |
555 | .fields = (VMStateField[]) { | |
556 | VMSTATE_PCI_DEVICE(dev, ViaISAState), | |
557 | VMSTATE_END_OF_LIST() | |
558 | } | |
559 | }; | |
560 | ||
9eb6abbf BB |
561 | static void via_isa_init(Object *obj) |
562 | { | |
563 | ViaISAState *s = VIA_ISA(obj); | |
564 | ||
565 | object_initialize_child(obj, "ide", &s->ide, TYPE_VIA_IDE); | |
566 | } | |
567 | ||
2e84e107 BZ |
568 | static const TypeInfo via_isa_info = { |
569 | .name = TYPE_VIA_ISA, | |
570 | .parent = TYPE_PCI_DEVICE, | |
571 | .instance_size = sizeof(ViaISAState), | |
9eb6abbf | 572 | .instance_init = via_isa_init, |
2e84e107 BZ |
573 | .abstract = true, |
574 | .interfaces = (InterfaceInfo[]) { | |
575 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
576 | { }, | |
577 | }, | |
94349bff BZ |
578 | }; |
579 | ||
a4d65b70 BZ |
580 | void via_isa_set_irq(PCIDevice *d, int n, int level) |
581 | { | |
582 | ViaISAState *s = VIA_ISA(d); | |
583 | qemu_set_irq(s->isa_irqs[n], level); | |
584 | } | |
585 | ||
3dc31cb8 BZ |
586 | static void via_isa_request_i8259_irq(void *opaque, int irq, int level) |
587 | { | |
2e84e107 | 588 | ViaISAState *s = opaque; |
3dc31cb8 BZ |
589 | qemu_set_irq(s->cpu_intr, level); |
590 | } | |
591 | ||
3a2f166f BZ |
592 | static void via_isa_realize(PCIDevice *d, Error **errp) |
593 | { | |
594 | ViaISAState *s = VIA_ISA(d); | |
595 | DeviceState *dev = DEVICE(d); | |
9eb6abbf | 596 | PCIBus *pci_bus = pci_get_bus(d); |
3a2f166f | 597 | qemu_irq *isa_irq; |
91ba92d1 | 598 | ISABus *isa_bus; |
3a2f166f BZ |
599 | int i; |
600 | ||
601 | qdev_init_gpio_out(dev, &s->cpu_intr, 1); | |
602 | isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); | |
dd28cc87 | 603 | isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d), |
c1561d1d BB |
604 | errp); |
605 | ||
606 | if (!isa_bus) { | |
607 | return; | |
608 | } | |
609 | ||
91ba92d1 BB |
610 | s->isa_irqs = i8259_init(isa_bus, *isa_irq); |
611 | isa_bus_irqs(isa_bus, s->isa_irqs); | |
612 | i8254_pit_init(isa_bus, 0x40, 0, NULL); | |
613 | i8257_dma_init(isa_bus, 0); | |
614 | mc146818_rtc_init(isa_bus, 2000, NULL); | |
3a2f166f BZ |
615 | |
616 | for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { | |
617 | if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { | |
618 | d->wmask[i] = 0; | |
619 | } | |
620 | } | |
8e4022a8 BB |
621 | |
622 | /* Super I/O */ | |
91ba92d1 | 623 | if (!qdev_realize(DEVICE(&s->via_sio), BUS(isa_bus), errp)) { |
8e4022a8 BB |
624 | return; |
625 | } | |
9eb6abbf BB |
626 | |
627 | /* Function 1: IDE */ | |
628 | qdev_prop_set_int32(DEVICE(&s->ide), "addr", d->devfn + 1); | |
629 | if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { | |
630 | return; | |
631 | } | |
3a2f166f BZ |
632 | } |
633 | ||
2e84e107 BZ |
634 | /* TYPE_VT82C686B_ISA */ |
635 | ||
94349bff BZ |
636 | static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, |
637 | uint32_t val, int len) | |
638 | { | |
2e84e107 | 639 | ViaISAState *s = VIA_ISA(d); |
94349bff BZ |
640 | |
641 | trace_via_isa_write(addr, val, len); | |
642 | pci_default_write_config(d, addr, val, len); | |
643 | if (addr == 0x85) { | |
644 | /* BIT(1): enable or disable superio config io ports */ | |
8e4022a8 | 645 | via_superio_io_enable(&s->via_sio, val & BIT(1)); |
94349bff BZ |
646 | } |
647 | } | |
648 | ||
94349bff BZ |
649 | static void vt82c686b_isa_reset(DeviceState *dev) |
650 | { | |
2e84e107 | 651 | ViaISAState *s = VIA_ISA(dev); |
94349bff BZ |
652 | uint8_t *pci_conf = s->dev.config; |
653 | ||
654 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
655 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
656 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
657 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
658 | ||
659 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
660 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
661 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
662 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
663 | pci_conf[0x59] = 0x04; | |
664 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
665 | pci_conf[0x5f] = 0x04; | |
666 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
94349bff BZ |
667 | } |
668 | ||
8e4022a8 | 669 | static void vt82c686b_init(Object *obj) |
edf79e66 | 670 | { |
8e4022a8 | 671 | ViaISAState *s = VIA_ISA(obj); |
edf79e66 | 672 | |
8e4022a8 | 673 | object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT82C686B_SUPERIO); |
edf79e66 HC |
674 | } |
675 | ||
2e84e107 | 676 | static void vt82c686b_class_init(ObjectClass *klass, void *data) |
40021f08 | 677 | { |
39bffca2 | 678 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
679 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
680 | ||
8e4022a8 | 681 | k->realize = via_isa_realize; |
40021f08 AL |
682 | k->config_write = vt82c686b_write_config; |
683 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
2e84e107 | 684 | k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA; |
40021f08 AL |
685 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
686 | k->revision = 0x40; | |
9dc1a769 | 687 | dc->reset = vt82c686b_isa_reset; |
39bffca2 | 688 | dc->desc = "ISA bridge"; |
39bffca2 | 689 | dc->vmsd = &vmstate_via; |
2e84e107 | 690 | /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */ |
e90f2a8c | 691 | dc->user_creatable = false; |
40021f08 AL |
692 | } |
693 | ||
2e84e107 | 694 | static const TypeInfo vt82c686b_isa_info = { |
0f798461 | 695 | .name = TYPE_VT82C686B_ISA, |
2e84e107 BZ |
696 | .parent = TYPE_VIA_ISA, |
697 | .instance_size = sizeof(ViaISAState), | |
8e4022a8 | 698 | .instance_init = vt82c686b_init, |
2e84e107 | 699 | .class_init = vt82c686b_class_init, |
edf79e66 HC |
700 | }; |
701 | ||
f9f0c9e2 | 702 | /* TYPE_VT8231_ISA */ |
94349bff | 703 | |
f9f0c9e2 BZ |
704 | static void vt8231_write_config(PCIDevice *d, uint32_t addr, |
705 | uint32_t val, int len) | |
98cf824b | 706 | { |
f9f0c9e2 | 707 | ViaISAState *s = VIA_ISA(d); |
98cf824b | 708 | |
f9f0c9e2 BZ |
709 | trace_via_isa_write(addr, val, len); |
710 | pci_default_write_config(d, addr, val, len); | |
711 | if (addr == 0x50) { | |
712 | /* BIT(2): enable or disable superio config io ports */ | |
8e4022a8 | 713 | via_superio_io_enable(&s->via_sio, val & BIT(2)); |
f9f0c9e2 | 714 | } |
98cf824b PMD |
715 | } |
716 | ||
f9f0c9e2 BZ |
717 | static void vt8231_isa_reset(DeviceState *dev) |
718 | { | |
719 | ViaISAState *s = VIA_ISA(dev); | |
720 | uint8_t *pci_conf = s->dev.config; | |
721 | ||
722 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
723 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
724 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
725 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
726 | ||
727 | pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */ | |
728 | pci_conf[0x67] = 0x08; /* Fast IR Config */ | |
729 | pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */ | |
730 | } | |
731 | ||
8e4022a8 | 732 | static void vt8231_init(Object *obj) |
f9f0c9e2 | 733 | { |
8e4022a8 | 734 | ViaISAState *s = VIA_ISA(obj); |
f9f0c9e2 | 735 | |
8e4022a8 | 736 | object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT8231_SUPERIO); |
f9f0c9e2 BZ |
737 | } |
738 | ||
739 | static void vt8231_class_init(ObjectClass *klass, void *data) | |
740 | { | |
741 | DeviceClass *dc = DEVICE_CLASS(klass); | |
742 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
743 | ||
8e4022a8 | 744 | k->realize = via_isa_realize; |
f9f0c9e2 BZ |
745 | k->config_write = vt8231_write_config; |
746 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
747 | k->device_id = PCI_DEVICE_ID_VIA_8231_ISA; | |
748 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
749 | k->revision = 0x10; | |
750 | dc->reset = vt8231_isa_reset; | |
751 | dc->desc = "ISA bridge"; | |
752 | dc->vmsd = &vmstate_via; | |
753 | /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ | |
754 | dc->user_creatable = false; | |
755 | } | |
756 | ||
757 | static const TypeInfo vt8231_isa_info = { | |
758 | .name = TYPE_VT8231_ISA, | |
759 | .parent = TYPE_VIA_ISA, | |
760 | .instance_size = sizeof(ViaISAState), | |
8e4022a8 | 761 | .instance_init = vt8231_init, |
f9f0c9e2 | 762 | .class_init = vt8231_class_init, |
98cf824b PMD |
763 | }; |
764 | ||
94349bff | 765 | |
83f7d43a | 766 | static void vt82c686b_register_types(void) |
edf79e66 | 767 | { |
83f7d43a | 768 | type_register_static(&via_pm_info); |
e1a69736 BZ |
769 | type_register_static(&vt82c686b_pm_info); |
770 | type_register_static(&vt8231_pm_info); | |
94349bff | 771 | type_register_static(&via_superio_info); |
f028c2de | 772 | type_register_static(&vt82c686b_superio_info); |
ab74864f | 773 | type_register_static(&vt8231_superio_info); |
2e84e107 BZ |
774 | type_register_static(&via_isa_info); |
775 | type_register_static(&vt82c686b_isa_info); | |
f9f0c9e2 | 776 | type_register_static(&vt8231_isa_info); |
edf79e66 | 777 | } |
83f7d43a AF |
778 | |
779 | type_init(vt82c686b_register_types) |