]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/ChangeLog
Fix ravenscar-thread.c for multi-target
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0c115f84
AM
12020-01-30 Alan Modra <amodra@gmail.com>
2
3 * m32c-ibld.c: Regenerate.
4
bd434cc4
JM
52020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
6
7 * bpf-opc.c: Regenerate.
8
aeab2b26
JB
92020-01-30 Jan Beulich <jbeulich@suse.com>
10
11 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
12 (dis386): Use them to replace C2/C3 table entries.
13 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
14 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
15 ones. Use Size64 instead of DefaultSize on Intel64 ones.
16 * i386-tbl.h: Re-generate.
17
62b3f548
JB
182020-01-30 Jan Beulich <jbeulich@suse.com>
19
20 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
21 forms.
22 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
23 DefaultSize.
24 * i386-tbl.h: Re-generate.
25
1bd8ae10
AM
262020-01-30 Alan Modra <amodra@gmail.com>
27
28 * tic4x-dis.c (tic4x_dp): Make unsigned.
29
bc31405e
L
302020-01-27 H.J. Lu <hongjiu.lu@intel.com>
31 Jan Beulich <jbeulich@suse.com>
32
33 PR binutils/25445
34 * i386-dis.c (MOVSXD_Fixup): New function.
35 (movsxd_mode): New enum.
36 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
37 (intel_operand_size): Handle movsxd_mode.
38 (OP_E_register): Likewise.
39 (OP_G): Likewise.
40 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
41 register on movsxd. Add movsxd with 16-bit destination register
42 for AMD64 and Intel64 ISAs.
43 * i386-tbl.h: Regenerated.
44
7568c93b
TC
452020-01-27 Tamar Christina <tamar.christina@arm.com>
46
47 PR 25403
48 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
49 * aarch64-asm-2.c: Regenerate
50 * aarch64-dis-2.c: Likewise.
51 * aarch64-opc-2.c: Likewise.
52
c006a730
JB
532020-01-21 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl (sysret): Drop DefaultSize.
56 * i386-tbl.h: Re-generate.
57
c906a69a
JB
582020-01-21 Jan Beulich <jbeulich@suse.com>
59
60 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
61 Dword.
62 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
63 * i386-tbl.h: Re-generate.
64
26916852
NC
652020-01-20 Nick Clifton <nickc@redhat.com>
66
67 * po/de.po: Updated German translation.
68 * po/pt_BR.po: Updated Brazilian Portuguese translation.
69 * po/uk.po: Updated Ukranian translation.
70
4d6cbb64
AM
712020-01-20 Alan Modra <amodra@gmail.com>
72
73 * hppa-dis.c (fput_const): Remove useless cast.
74
2bddb71a
AM
752020-01-20 Alan Modra <amodra@gmail.com>
76
77 * arm-dis.c (print_insn_arm): Wrap 'T' value.
78
1b1bb2c6
NC
792020-01-18 Nick Clifton <nickc@redhat.com>
80
81 * configure: Regenerate.
82 * po/opcodes.pot: Regenerate.
83
ae774686
NC
842020-01-18 Nick Clifton <nickc@redhat.com>
85
86 Binutils 2.34 branch created.
87
07f1f3aa
CB
882020-01-17 Christian Biesinger <cbiesinger@google.com>
89
90 * opintl.h: Fix spelling error (seperate).
91
42e04b36
L
922020-01-17 H.J. Lu <hongjiu.lu@intel.com>
93
94 * i386-opc.tbl: Add {vex} pseudo prefix.
95 * i386-tbl.h: Regenerated.
96
2da2eaf4
AV
972020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
98
99 PR 25376
100 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
101 (neon_opcodes): Likewise.
102 (select_arm_features): Make sure we enable MVE bits when selecting
103 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
104 any architecture.
105
d0849eed
JB
1062020-01-16 Jan Beulich <jbeulich@suse.com>
107
108 * i386-opc.tbl: Drop stale comment from XOP section.
109
9cf70a44
JB
1102020-01-16 Jan Beulich <jbeulich@suse.com>
111
112 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
113 (extractps): Add VexWIG to SSE2AVX forms.
114 * i386-tbl.h: Re-generate.
115
4814632e
JB
1162020-01-16 Jan Beulich <jbeulich@suse.com>
117
118 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
119 Size64 from and use VexW1 on SSE2AVX forms.
120 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
121 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
122 * i386-tbl.h: Re-generate.
123
aad09917
AM
1242020-01-15 Alan Modra <amodra@gmail.com>
125
126 * tic4x-dis.c (tic4x_version): Make unsigned long.
127 (optab, optab_special, registernames): New file scope vars.
128 (tic4x_print_register): Set up registernames rather than
129 malloc'd registertable.
130 (tic4x_disassemble): Delete optable and optable_special. Use
131 optab and optab_special instead. Throw away old optab,
132 optab_special and registernames when info->mach changes.
133
7a6bf3be
SB
1342020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
135
136 PR 25377
137 * z80-dis.c (suffix): Use .db instruction to generate double
138 prefix.
139
ca1eaac0
AM
1402020-01-14 Alan Modra <amodra@gmail.com>
141
142 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
143 values to unsigned before shifting.
144
1d67fe3b
TT
1452020-01-13 Thomas Troeger <tstroege@gmx.de>
146
147 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
148 flow instructions.
149 (print_insn_thumb16, print_insn_thumb32): Likewise.
150 (print_insn): Initialize the insn info.
151 * i386-dis.c (print_insn): Initialize the insn info fields, and
152 detect jumps.
153
5e4f7e05
CZ
1542012-01-13 Claudiu Zissulescu <claziss@gmail.com>
155
156 * arc-opc.c (C_NE): Make it required.
157
b9fe6b8a
CZ
1582012-01-13 Claudiu Zissulescu <claziss@gmail.com>
159
160 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
161 reserved register name.
162
90dee485
AM
1632020-01-13 Alan Modra <amodra@gmail.com>
164
165 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
166 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
167
febda64f
AM
1682020-01-13 Alan Modra <amodra@gmail.com>
169
170 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
171 result of wasm_read_leb128 in a uint64_t and check that bits
172 are not lost when copying to other locals. Use uint32_t for
173 most locals. Use PRId64 when printing int64_t.
174
df08b588
AM
1752020-01-13 Alan Modra <amodra@gmail.com>
176
177 * score-dis.c: Formatting.
178 * score7-dis.c: Formatting.
179
b2c759ce
AM
1802020-01-13 Alan Modra <amodra@gmail.com>
181
182 * score-dis.c (print_insn_score48): Use unsigned variables for
183 unsigned values. Don't left shift negative values.
184 (print_insn_score32): Likewise.
185 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
186
5496abe1
AM
1872020-01-13 Alan Modra <amodra@gmail.com>
188
189 * tic4x-dis.c (tic4x_print_register): Remove dead code.
190
202e762b
AM
1912020-01-13 Alan Modra <amodra@gmail.com>
192
193 * fr30-ibld.c: Regenerate.
194
7ef412cf
AM
1952020-01-13 Alan Modra <amodra@gmail.com>
196
197 * xgate-dis.c (print_insn): Don't left shift signed value.
198 (ripBits): Formatting, use 1u.
199
7f578b95
AM
2002020-01-10 Alan Modra <amodra@gmail.com>
201
202 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
203 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
204
441af85b
AM
2052020-01-10 Alan Modra <amodra@gmail.com>
206
207 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
208 and XRREG value earlier to avoid a shift with negative exponent.
209 * m10200-dis.c (disassemble): Similarly.
210
bce58db4
NC
2112020-01-09 Nick Clifton <nickc@redhat.com>
212
213 PR 25224
214 * z80-dis.c (ld_ii_ii): Use correct cast.
215
40c75bc8
SB
2162020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
217
218 PR 25224
219 * z80-dis.c (ld_ii_ii): Use character constant when checking
220 opcode byte value.
221
d835a58b
JB
2222020-01-09 Jan Beulich <jbeulich@suse.com>
223
224 * i386-dis.c (SEP_Fixup): New.
225 (SEP): Define.
226 (dis386_twobyte): Use it for sysenter/sysexit.
227 (enum x86_64_isa): Change amd64 enumerator to value 1.
228 (OP_J): Compare isa64 against intel64 instead of amd64.
229 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
230 forms.
231 * i386-tbl.h: Re-generate.
232
030a2e78
AM
2332020-01-08 Alan Modra <amodra@gmail.com>
234
235 * z8k-dis.c: Include libiberty.h
236 (instr_data_s): Make max_fetched unsigned.
237 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
238 Don't exceed byte_info bounds.
239 (output_instr): Make num_bytes unsigned.
240 (unpack_instr): Likewise for nibl_count and loop.
241 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
242 idx unsigned.
243 * z8k-opc.h: Regenerate.
244
bb82aefe
SV
2452020-01-07 Shahab Vahedi <shahab@synopsys.com>
246
247 * arc-tbl.h (llock): Use 'LLOCK' as class.
248 (llockd): Likewise.
249 (scond): Use 'SCOND' as class.
250 (scondd): Likewise.
251 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
252 (scondd): Likewise.
253
cc6aa1a6
AM
2542020-01-06 Alan Modra <amodra@gmail.com>
255
256 * m32c-ibld.c: Regenerate.
257
660e62b1
AM
2582020-01-06 Alan Modra <amodra@gmail.com>
259
260 PR 25344
261 * z80-dis.c (suffix): Don't use a local struct buffer copy.
262 Peek at next byte to prevent recursion on repeated prefix bytes.
263 Ensure uninitialised "mybuf" is not accessed.
264 (print_insn_z80): Don't zero n_fetch and n_used here,..
265 (print_insn_z80_buf): ..do it here instead.
266
c9ae58fe
AM
2672020-01-04 Alan Modra <amodra@gmail.com>
268
269 * m32r-ibld.c: Regenerate.
270
5f57d4ec
AM
2712020-01-04 Alan Modra <amodra@gmail.com>
272
273 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
274
2c5c1196
AM
2752020-01-04 Alan Modra <amodra@gmail.com>
276
277 * crx-dis.c (match_opcode): Avoid shift left of signed value.
278
2e98c6c5
AM
2792020-01-04 Alan Modra <amodra@gmail.com>
280
281 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
282
567dfba2
JB
2832020-01-03 Jan Beulich <jbeulich@suse.com>
284
5437a02a
JB
285 * aarch64-tbl.h (aarch64_opcode_table): Use
286 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
287
2882020-01-03 Jan Beulich <jbeulich@suse.com>
289
290 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB
291 forms of SUDOT and USDOT.
292
8c45011a
JB
2932020-01-03 Jan Beulich <jbeulich@suse.com>
294
5437a02a 295 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB
296 uzip{1,2}.
297 * opcodes/aarch64-dis-2.c: Re-generate.
298
f4950f76
JB
2992020-01-03 Jan Beulich <jbeulich@suse.com>
300
5437a02a 301 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB
302 FMMLA encoding.
303 * opcodes/aarch64-dis-2.c: Re-generate.
304
6655dba2
SB
3052020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
306
307 * z80-dis.c: Add support for eZ80 and Z80 instructions.
308
b14ce8bf
AM
3092020-01-01 Alan Modra <amodra@gmail.com>
310
311 Update year range in copyright notice of all files.
312
0b114740 313For older changes see ChangeLog-2019
3499769a 314\f
0b114740 315Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM
316
317Copying and distribution of this file, with or without modification,
318are permitted in any medium without royalty provided the copyright
319notice and this notice are preserved.
320
321Local Variables:
322mode: change-log
323left-margin: 8
324fill-column: 74
325version-control: never
326End: