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[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
4c0deff4
NC		 12000-05-24 Michael Hayes <mhayes@cygnus.com>
2
3 * mips.igen (do_dmultx): Fix typo.
4
eb2d80b4
AC		 5Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
6
7 * configure: Regenerated to track ../common/aclocal.m4 changes.
8
dd37a34b
AC		 9Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
10
11 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
12
4c0deff4
NC		 132000-04-12 Frank Ch. Eigler <fche@redhat.com>
14
15 * sim-main.h (GPR_CLEAR): Define macro.
16
e30db738
AC		 17Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
18
19 * interp.c (decode_coproc): Output long using %lx and not %s.
20
cb7450ea
FCE		 212000-03-21 Frank Ch. Eigler <fche@redhat.com>
22
23 * interp.c (sim_open): Sort & extend dummy memory regions for
24 --board=jmr3904 for eCos.
25
a3027dd7
FCE		 262000-03-02 Frank Ch. Eigler <fche@redhat.com>
27
28 * configure: Regenerated.
29
30Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
31
32 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
33 calls, conditional on the simulator being in verbose mode.
34
dfcd3bfb
JM		 35Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
36
37 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
38 cache don't get ReservedInstruction traps.
39
c2d11a7d
JM		 401999-11-29 Mark Salter <msalter@cygnus.com>
41
42 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
43 to clear status bits in sdisr register. This is how the hardware works.
44
45 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
46 being used by cygmon.
47
4ce44c66
JM		 481999-11-11 Andrew Haley <aph@cygnus.com>
49
50 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
51 instructions.
52
cff3e48b
JM		 53Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
54
55 * mips.igen (MULT): Correct previous mis-applied patch.
56
d4f3574e
SS		 57Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
58
59 * mips.igen (delayslot32): Handle sequence like
60 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
61 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
62 (MULT): Actually pass the third register...
63
641999-09-03 Mark Salter <msalter@cygnus.com>
65
66 * interp.c (sim_open): Added more memory aliases for additional
67 hardware being touched by cygmon on jmr3904 board.
68
69Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
70
71 * configure: Regenerated to track ../common/aclocal.m4 changes.
72
a0b3c4fd
JM		 73Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
74
75 * interp.c (sim_store_register): Handle case where client - GDB -
76 specifies that a 4 byte register is 8 bytes in size.
77 (sim_fetch_register): Ditto.
78
adf40b2e
JM		 791999-07-14 Frank Ch. Eigler <fche@cygnus.com>
80
81 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
82 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
83 (idt_monitor_base): Base address for IDT monitor traps.
84 (pmon_monitor_base): Ditto for PMON.
85 (lsipmon_monitor_base): Ditto for LSI PMON.
86 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
87 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
88 (sim_firmware_command): New function.
89 (mips_option_handler): Call it for OPTION_FIRMWARE.
90 (sim_open): Allocate memory for idt_monitor region. If "--board"
91 option was given, add no monitor by default. Add BREAK hooks only if
92 monitors are also there.
93
43e526b9
JM		 94Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
95
96 * interp.c (sim_monitor): Flush output before reading input.
97
98Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
99
100 * tconfig.in (SIM_HANDLES_LMA): Always define.
101
102Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
103
104 From Mark Salter <msalter@cygnus.com>:
105 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
106 (sim_open): Add setup for BSP board.
107
9846de1b
JM		 108Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
109
110 * mips.igen (MULT, MULTU): Add syntax for two operand version.
111 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
112 them as unimplemented.
113
cd0fc7c3
SS		 1141999-05-08 Felix Lee <flee@cygnus.com>
115
116 * configure: Regenerated to track ../common/aclocal.m4 changes.
117
7a292a7a
SS		 1181999-04-21 Frank Ch. Eigler <fche@cygnus.com>
119
120 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
121
122Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
123
124 * configure.in: Any mips64vr5*-*-* target should have
125 -DTARGET_ENABLE_FR=1.
126 (default_endian): Any mips64vr*el-*-* target should default to
127 LITTLE_ENDIAN.
128 * configure: Re-generate.
129
1301999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
131
132 * mips.igen (ldl): Extend from _16_, not 32.
133
134Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
135
136 * interp.c (sim_store_register): Force registers written to by GDB
137 into an un-interpreted state.
138
c906108c
SS		 1391999-02-05 Frank Ch. Eigler <fche@cygnus.com>
140
141 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
142 CPU, start periodic background I/O polls.
143 (tx3904sio_poll): New function: periodic I/O poller.
144
1451998-12-30 Frank Ch. Eigler <fche@cygnus.com>
146
147 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
148
149Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
150
151 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
152 case statement.
153
1541998-12-29 Frank Ch. Eigler <fche@cygnus.com>
155
156 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
157 (load_word): Call SIM_CORE_SIGNAL hook on error.
158 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
159 starting. For exception dispatching, pass PC instead of NULL_CIA.
160 (decode_coproc): Use COP0_BADVADDR to store faulting address.
161 * sim-main.h (COP0_BADVADDR): Define.
162 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
163 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
164 (_sim_cpu): Add exc_* fields to store register value snapshots.
165 * mips.igen (*): Replace memory-related SignalException* calls
166 with references to SIM_CORE_SIGNAL hook.
167
168 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
169 fix.
170 * sim-main.c (*): Minor warning cleanups.
171
1721998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
173
174 * m16.igen (DADDIU5): Correct type-o.
175
176Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
177
178 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
179 variables.
180
181Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
182
183 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
184 to include path.
185 (interp.o): Add dependency on itable.h
186 (oengine.c, gencode): Delete remaining references.
187 (BUILT_SRC_FROM_GEN): Clean up.
188
1891998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
190
191 * vr4run.c: New.
192 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
193 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
194 tmp-run-hack) : New.
195 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
196 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
197 Drop the "64" qualifier to get the HACK generator working.
198 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
199 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
200 qualifier to get the hack generator working.
201 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
202 (DSLL): Use do_dsll.
203 (DSLLV): Use do_dsllv.
204 (DSRA): Use do_dsra.
205 (DSRL): Use do_dsrl.
206 (DSRLV): Use do_dsrlv.
207 (BC1): Move *vr4100 to get the HACK generator working.
208 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
209 get the HACK generator working.
210 (MACC) Rename to get the HACK generator working.
211 (DMACC,MACCS,DMACCS): Add the 64.
212
2131998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
214
215 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
216 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
217
2181998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
219
220 * mips/interp.c (DEBUG): Cleanups.
221
2221998-12-10 Frank Ch. Eigler <fche@cygnus.com>
223
224 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
225 (tx3904sio_tickle): fflush after a stdout character output.
226
2271998-12-03 Frank Ch. Eigler <fche@cygnus.com>
228
229 * interp.c (sim_close): Uninstall modules.
230
231Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
232
233 * sim-main.h, interp.c (sim_monitor): Change to global
234 function.
235
236Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
237
238 * configure.in (vr4100): Only include vr4100 instructions in
239 simulator.
240 * configure: Re-generate.
241 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
242
243Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
244
245 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
246 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
247 true alternative.
248
249 * configure.in (sim_default_gen, sim_use_gen): Replace with
250 sim_gen.
251 (--enable-sim-igen): Delete config option. Always using IGEN.
252 * configure: Re-generate.
253
254 * Makefile.in (gencode): Kill, kill, kill.
255 * gencode.c: Ditto.
256
257Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
258
259 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
260 bit mips16 igen simulator.
261 * configure: Re-generate.
262
263 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
264 as part of vr4100 ISA.
265 * vr.igen: Mark all instructions as 64 bit only.
266
267Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
268
269 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
270 Pacify GCC.
271
272Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
273
274 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
275 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
276 * configure: Re-generate.
277
278 * m16.igen (BREAK): Define breakpoint instruction.
279 (JALX32): Mark instruction as mips16 and not r3900.
280 * mips.igen (C.cond.fmt): Fix typo in instruction format.
281
282 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
283
284Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
285
286 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
287 insn as a debug breakpoint.
288
289 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
290 pending.slot_size.
291 (PENDING_SCHED): Clean up trace statement.
292 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
293 (PENDING_FILL): Delay write by only one cycle.
294 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
295
296 * sim-main.c (pending_tick): Clean up trace statements. Add trace
297 of pending writes.
298 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
299 32 & 64.
300 (pending_tick): Move incrementing of index to FOR statement.
301 (pending_tick): Only update PENDING_OUT after a write has occured.
302
303 * configure.in: Add explicit mips-lsi-* target. Use gencode to
304 build simulator.
305 * configure: Re-generate.
306
307 * interp.c (sim_engine_run OLD): Delete explicit call to
308 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
309
310Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
311
312 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
313 interrupt level number to match changed SignalExceptionInterrupt
314 macro.
315
316Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
317
318 * interp.c: #include "itable.h" if WITH_IGEN.
319 (get_insn_name): New function.
320 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
321 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
322
323Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
324
325 * configure: Rebuilt to inhale new common/aclocal.m4.
326
327Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
328
329 * dv-tx3904sio.c: Include sim-assert.h.
330
331Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
332
333 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
334 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
335 Reorganize target-specific sim-hardware checks.
336 * configure: rebuilt.
337 * interp.c (sim_open): For tx39 target boards, set
338 OPERATING_ENVIRONMENT, add tx3904sio devices.
339 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
340 ROM executables. Install dv-sockser into sim-modules list.
341
342 * dv-tx3904irc.c: Compiler warning clean-up.
343 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
344 frequent hw-trace messages.
345
346Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
347
348 * vr.igen (MulAcc): Identify as a vr4100 specific function.
349
350Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
351
352 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
353
354 * vr.igen: New file.
355 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
356 * mips.igen: Define vr4100 model. Include vr.igen.
357Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
358
359 * mips.igen (check_mf_hilo): Correct check.
360
361Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
362
363 * sim-main.h (interrupt_event): Add prototype.
364
365 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
366 register_ptr, register_value.
367 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
368
369 * sim-main.h (tracefh): Make extern.
370
371Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
372
373 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
374 Reduce unnecessarily high timer event frequency.
375 * dv-tx3904cpu.c: Ditto for interrupt event.
376
377Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
378
379 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
380 to allay warnings.
381 (interrupt_event): Made non-static.
382
383 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
384 interchange of configuration values for external vs. internal
385 clock dividers.
386
387Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
388
389 * mips.igen (BREAK): Moved code to here for
390 simulator-reserved break instructions.
391 * gencode.c (build_instruction): Ditto.
392 * interp.c (signal_exception): Code moved from here. Non-
393 reserved instructions now use exception vector, rather
394 than halting sim.
395 * sim-main.h: Moved magic constants to here.
396
397Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
398
399 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
400 register upon non-zero interrupt event level, clear upon zero
401 event value.
402 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
403 by passing zero event value.
404 (*_io_{read,write}_buffer): Endianness fixes.
405 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
406 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
407
408 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
409 serial I/O and timer module at base address 0xFFFF0000.
410
411Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
412
413 * mips.igen (SWC1) : Correct the handling of ReverseEndian
414 and BigEndianCPU.
415
416Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
417
418 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
419 parts.
420 * configure: Update.
421
422Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
423
424 * dv-tx3904tmr.c: New file - implements tx3904 timer.
425 * dv-tx3904{irc,cpu}.c: Mild reformatting.
426 * configure.in: Include tx3904tmr in hw_device list.
427 * configure: Rebuilt.
428 * interp.c (sim_open): Instantiate three timer instances.
429 Fix address typo of tx3904irc instance.
430
431Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
432
433 * interp.c (signal_exception): SystemCall exception now uses
434 the exception vector.
435
436Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
437
438 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
439 to allay warnings.
440
441Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
442
443 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
444
445Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
446
447 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
448
449 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
450 sim-main.h. Declare a struct hw_descriptor instead of struct
451 hw_device_descriptor.
452
453Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
454
455 * mips.igen (do_store_left, do_load_left): Compute nr of left and
456 right bits and then re-align left hand bytes to correct byte
457 lanes. Fix incorrect computation in do_store_left when loading
458 bytes from second word.
459
460Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
461
462 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
463 * interp.c (sim_open): Only create a device tree when HW is
464 enabled.
465
466 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
467 * interp.c (signal_exception): Ditto.
468
469Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
470
471 * gencode.c: Mark BEGEZALL as LIKELY.
472
473Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
474
475 * sim-main.h (ALU32_END): Sign extend 32 bit results.
476 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
477
478Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
479
480 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
481 modules. Recognize TX39 target with "mips*tx39" pattern.
482 * configure: Rebuilt.
483 * sim-main.h (*): Added many macros defining bits in
484 TX39 control registers.
485 (SignalInterrupt): Send actual PC instead of NULL.
486 (SignalNMIReset): New exception type.
487 * interp.c (board): New variable for future use to identify
488 a particular board being simulated.
489 (mips_option_handler,mips_options): Added "--board" option.
490 (interrupt_event): Send actual PC.
491 (sim_open): Make memory layout conditional on board setting.
492 (signal_exception): Initial implementation of hardware interrupt
493 handling. Accept another break instruction variant for simulator
494 exit.
495 (decode_coproc): Implement RFE instruction for TX39.
496 (mips.igen): Decode RFE instruction as such.
497 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
498 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
499 bbegin to implement memory map.
500 * dv-tx3904cpu.c: New file.
501 * dv-tx3904irc.c: New file.
502
503Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
504
505 * mips.igen (check_mt_hilo): Create a separate r3900 version.
506
507Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
508
509 * tx.igen (madd,maddu): Replace calls to check_op_hilo
510 with calls to check_div_hilo.
511
512Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
513
514 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
515 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
516 Add special r3900 version of do_mult_hilo.
517 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
518 with calls to check_mult_hilo.
519 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
520 with calls to check_div_hilo.
521
522Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
523
524 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
525 Document a replacement.
526
527Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
528
529 * interp.c (sim_monitor): Make mon_printf work.
530
531Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
532
533 * sim-main.h (INSN_NAME): New arg `cpu'.
534
535Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
536
537 * configure: Regenerated to track ../common/aclocal.m4 changes.
538
539Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
540
541 * configure: Regenerated to track ../common/aclocal.m4 changes.
542 * config.in: Ditto.
543
544Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
545
546 * acconfig.h: New file.
547 * configure.in: Reverted change of Apr 24; use sinclude again.
548
549Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
550
551 * configure: Regenerated to track ../common/aclocal.m4 changes.
552 * config.in: Ditto.
553
554Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
555
556 * configure.in: Don't call sinclude.
557
558Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
559
560 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
561
562Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
563
564 * mips.igen (ERET): Implement.
565
566 * interp.c (decode_coproc): Return sign-extended EPC.
567
568 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
569
570 * interp.c (signal_exception): Do not ignore Trap.
571 (signal_exception): On TRAP, restart at exception address.
572 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
573 (signal_exception): Update.
574 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
575 so that TRAP instructions are caught.
576
577Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
578
579 * sim-main.h (struct hilo_access, struct hilo_history): Define,
580 contains HI/LO access history.
581 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
582 (HIACCESS, LOACCESS): Delete, replace with
583 (HIHISTORY, LOHISTORY): New macros.
584 (CHECKHILO): Delete all, moved to mips.igen
585
586 * gencode.c (build_instruction): Do not generate checks for
587 correct HI/LO register usage.
588
589 * interp.c (old_engine_run): Delete checks for correct HI/LO
590 register usage.
591
592 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
593 check_mf_cycles): New functions.
594 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
595 do_divu, domultx, do_mult, do_multu): Use.
596
597 * tx.igen ("madd", "maddu"): Use.
598
599Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
600
601 * mips.igen (DSRAV): Use function do_dsrav.
602 (SRAV): Use new function do_srav.
603
604 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
605 (B): Sign extend 11 bit immediate.
606 (EXT-B*): Shift 16 bit immediate left by 1.
607 (ADDIU*): Don't sign extend immediate value.
608
609Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
610
611 * m16run.c (sim_engine_run): Restore CIA after handling an event.
612
613 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
614 functions.
615
616 * mips.igen (delayslot32, nullify_next_insn): New functions.
617 (m16.igen): Always include.
618 (do_*): Add more tracing.
619
620 * m16.igen (delayslot16): Add NIA argument, could be called by a
621 32 bit MIPS16 instruction.
622
623 * interp.c (ifetch16): Move function from here.
624 * sim-main.c (ifetch16): To here.
625
626 * sim-main.c (ifetch16, ifetch32): Update to match current
627 implementations of LH, LW.
628 (signal_exception): Don't print out incorrect hex value of illegal
629 instruction.
630
631Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
632
633 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
634 instruction.
635
636 * m16.igen: Implement MIPS16 instructions.
637
638 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
639 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
640 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
641 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
642 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
643 bodies of corresponding code from 32 bit insn to these. Also used
644 by MIPS16 versions of functions.
645
646 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
647 (IMEM16): Drop NR argument from macro.
648
649Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
650
651 * Makefile.in (SIM_OBJS): Add sim-main.o.
652
653 * sim-main.h (address_translation, load_memory, store_memory,
654 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
655 as INLINE_SIM_MAIN.
656 (pr_addr, pr_uword64): Declare.
657 (sim-main.c): Include when H_REVEALS_MODULE_P.
658
659 * interp.c (address_translation, load_memory, store_memory,
660 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
661 from here.
662 * sim-main.c: To here. Fix compilation problems.
663
664 * configure.in: Enable inlining.
665 * configure: Re-config.
666
667Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
668
669 * configure: Regenerated to track ../common/aclocal.m4 changes.
670
671Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
672
673 * mips.igen: Include tx.igen.
674 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
675 * tx.igen: New file, contains MADD and MADDU.
676
677 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
678 the hardwired constant `7'.
679 (store_memory): Ditto.
680 (LOADDRMASK): Move definition to sim-main.h.
681
682 mips.igen (MTC0): Enable for r3900.
683 (ADDU): Add trace.
684
685 mips.igen (do_load_byte): Delete.
686 (do_load, do_store, do_load_left, do_load_write, do_store_left,
687 do_store_right): New functions.
688 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
689
690 configure.in: Let the tx39 use igen again.
691 configure: Update.
692
693Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
694
695 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
696 not an address sized quantity. Return zero for cache sizes.
697
698Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
699
700 * mips.igen (r3900): r3900 does not support 64 bit integer
701 operations.
702
703Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
704
705 * configure.in (mipstx39*-*-*): Use gencode simulator rather
706 than igen one.
707 * configure : Rebuild.
708
709Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
710
711 * configure: Regenerated to track ../common/aclocal.m4 changes.
712
713Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
716
717Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
718
719 * configure: Regenerated to track ../common/aclocal.m4 changes.
720 * config.in: Regenerated to track ../common/aclocal.m4 changes.
721
722Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
723
724 * configure: Regenerated to track ../common/aclocal.m4 changes.
725
726Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
727
728 * interp.c (Max, Min): Comment out functions. Not yet used.
729
730Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
731
732 * configure: Regenerated to track ../common/aclocal.m4 changes.
733
734Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
735
736 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
737 configurable settings for stand-alone simulator.
738
739 * configure.in: Added X11 search, just in case.
740
741 * configure: Regenerated.
742
743Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
744
745 * interp.c (sim_write, sim_read, load_memory, store_memory):
746 Replace sim_core_*_map with read_map, write_map, exec_map resp.
747
748Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
749
750 * sim-main.h (GETFCC): Return an unsigned value.
751
752Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * mips.igen (DIV): Fix check for -1 / MIN_INT.
755 (DADD): Result destination is RD not RT.
756
757Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
758
759 * sim-main.h (HIACCESS, LOACCESS): Always define.
760
761 * mdmx.igen (Maxi, Mini): Rename Max, Min.
762
763 * interp.c (sim_info): Delete.
764
765Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
766
767 * interp.c (DECLARE_OPTION_HANDLER): Use it.
768 (mips_option_handler): New argument `cpu'.
769 (sim_open): Update call to sim_add_option_table.
770
771Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
772
773 * mips.igen (CxC1): Add tracing.
774
775Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * sim-main.h (Max, Min): Declare.
778
779 * interp.c (Max, Min): New functions.
780
781 * mips.igen (BC1): Add tracing.
782
783Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
784
785 * interp.c Added memory map for stack in vr4100
786
787Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
788
789 * interp.c (load_memory): Add missing "break"'s.
790
791Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
792
793 * interp.c (sim_store_register, sim_fetch_register): Pass in
794 length parameter. Return -1.
795
796Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
797
798 * interp.c: Added hardware init hook, fixed warnings.
799
800Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
801
802 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
803
804Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
805
806 * interp.c (ifetch16): New function.
807
808 * sim-main.h (IMEM32): Rename IMEM.
809 (IMEM16_IMMED): Define.
810 (IMEM16): Define.
811 (DELAY_SLOT): Update.
812
813 * m16run.c (sim_engine_run): New file.
814
815 * m16.igen: All instructions except LB.
816 (LB): Call do_load_byte.
817 * mips.igen (do_load_byte): New function.
818 (LB): Call do_load_byte.
819
820 * mips.igen: Move spec for insn bit size and high bit from here.
821 * Makefile.in (tmp-igen, tmp-m16): To here.
822
823 * m16.dc: New file, decode mips16 instructions.
824
825 * Makefile.in (SIM_NO_ALL): Define.
826 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
827
828Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
829
830 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
831 point unit to 32 bit registers.
832 * configure: Re-generate.
833
834Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
835
836 * configure.in (sim_use_gen): Make IGEN the default simulator
837 generator for generic 32 and 64 bit mips targets.
838 * configure: Re-generate.
839
840Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
841
842 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
843 bitsize.
844
845 * interp.c (sim_fetch_register, sim_store_register): Read/write
846 FGR from correct location.
847 (sim_open): Set size of FGR's according to
848 WITH_TARGET_FLOATING_POINT_BITSIZE.
849
850 * sim-main.h (FGR): Store floating point registers in a separate
851 array.
852
853Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
854
855 * configure: Regenerated to track ../common/aclocal.m4 changes.
856
857Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
858
859 * interp.c (ColdReset): Call PENDING_INVALIDATE.
860
861 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
862
863 * interp.c (pending_tick): New function. Deliver pending writes.
864
865 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
866 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
867 it can handle mixed sized quantites and single bits.
868
869Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
870
871 * interp.c (oengine.h): Do not include when building with IGEN.
872 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
873 (sim_info): Ditto for PROCESSOR_64BIT.
874 (sim_monitor): Replace ut_reg with unsigned_word.
875 (*): Ditto for t_reg.
876 (LOADDRMASK): Define.
877 (sim_open): Remove defunct check that host FP is IEEE compliant,
878 using software to emulate floating point.
879 (value_fpr, ...): Always compile, was conditional on HASFPU.
880
881Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
882
883 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
884 size.
885
886 * interp.c (SD, CPU): Define.
887 (mips_option_handler): Set flags in each CPU.
888 (interrupt_event): Assume CPU 0 is the one being iterrupted.
889 (sim_close): Do not clear STATE, deleted anyway.
890 (sim_write, sim_read): Assume CPU zero's vm should be used for
891 data transfers.
892 (sim_create_inferior): Set the PC for all processors.
893 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
894 argument.
895 (mips16_entry): Pass correct nr of args to store_word, load_word.
896 (ColdReset): Cold reset all cpu's.
897 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
898 (sim_monitor, load_memory, store_memory, signal_exception): Use
899 `CPU' instead of STATE_CPU.
900
901
902 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
903 SD or CPU_.
904
905 * sim-main.h (signal_exception): Add sim_cpu arg.
906 (SignalException*): Pass both SD and CPU to signal_exception.
907 * interp.c (signal_exception): Update.
908
909 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
910 Ditto
911 (sync_operation, prefetch, cache_op, store_memory, load_memory,
912 address_translation): Ditto
913 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
914
915Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
916
917 * configure: Regenerated to track ../common/aclocal.m4 changes.
918
919Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * interp.c (sim_engine_run): Add `nr_cpus' argument.
922
923 * mips.igen (model): Map processor names onto BFD name.
924
925 * sim-main.h (CPU_CIA): Delete.
926 (SET_CIA, GET_CIA): Define
927
928Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
929
930 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
931 regiser.
932
933 * configure.in (default_endian): Configure a big-endian simulator
934 by default.
935 * configure: Re-generate.
936
937Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
938
939 * configure: Regenerated to track ../common/aclocal.m4 changes.
940
941Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
942
943 * interp.c (sim_monitor): Handle Densan monitor outbyte
944 and inbyte functions.
945
9461997-12-29 Felix Lee <flee@cygnus.com>
947
948 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
949
950Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
951
952 * Makefile.in (tmp-igen): Arrange for $zero to always be
953 reset to zero after every instruction.
954
955Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
956
957 * configure: Regenerated to track ../common/aclocal.m4 changes.
958 * config.in: Ditto.
959
960Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
961
962 * mips.igen (MSUB): Fix to work like MADD.
963 * gencode.c (MSUB): Similarly.
964
965Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
966
967 * configure: Regenerated to track ../common/aclocal.m4 changes.
968
969Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
970
971 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
972
973Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
974
975 * sim-main.h (sim-fpu.h): Include.
976
977 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
978 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
979 using host independant sim_fpu module.
980
981Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
982
983 * interp.c (signal_exception): Report internal errors with SIGABRT
984 not SIGQUIT.
985
986 * sim-main.h (C0_CONFIG): New register.
987 (signal.h): No longer include.
988
989 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
990
991Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
992
993 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
994
995Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
996
997 * mips.igen: Tag vr5000 instructions.
998 (ANDI): Was missing mipsIV model, fix assembler syntax.
999 (do_c_cond_fmt): New function.
1000 (C.cond.fmt): Handle mips I-III which do not support CC field
1001 separatly.
1002 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1003 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1004 in IV3.2 spec.
1005 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1006 vr5000 which saves LO in a GPR separatly.
1007
1008 * configure.in (enable-sim-igen): For vr5000, select vr5000
1009 specific instructions.
1010 * configure: Re-generate.
1011
1012Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1013
1014 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1015
1016 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1017 fmt_uninterpreted_64 bit cases to switch. Convert to
1018 fmt_formatted,
1019
1020 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1021
1022 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1023 as specified in IV3.2 spec.
1024 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1025
1026Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1027
1028 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1029 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1030 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1031 PENDING_FILL versions of instructions. Simplify.
1032 (X): New function.
1033 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1034 instructions.
1035 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1036 a signed value.
1037 (MTHI, MFHI): Disable code checking HI-LO.
1038
1039 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1040 global.
1041 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1042
1043Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1044
1045 * gencode.c (build_mips16_operands): Replace IPC with cia.
1046
1047 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1048 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1049 IPC to `cia'.
1050 (UndefinedResult): Replace function with macro/function
1051 combination.
1052 (sim_engine_run): Don't save PC in IPC.
1053
1054 * sim-main.h (IPC): Delete.
1055
1056
1057 * interp.c (signal_exception, store_word, load_word,
1058 address_translation, load_memory, store_memory, cache_op,
1059 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1060 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1061 current instruction address - cia - argument.
1062 (sim_read, sim_write): Call address_translation directly.
1063 (sim_engine_run): Rename variable vaddr to cia.
1064 (signal_exception): Pass cia to sim_monitor
1065
1066 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1067 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1068 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1069
1070 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1071 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1072 SIM_ASSERT.
1073
1074 * interp.c (signal_exception): Pass restart address to
1075 sim_engine_restart.
1076
1077 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1078 idecode.o): Add dependency.
1079
1080 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1081 Delete definitions
1082 (DELAY_SLOT): Update NIA not PC with branch address.
1083 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1084
1085 * mips.igen: Use CIA not PC in branch calculations.
1086 (illegal): Call SignalException.
1087 (BEQ, ADDIU): Fix assembler.
1088
1089Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1090
1091 * m16.igen (JALX): Was missing.
1092
1093 * configure.in (enable-sim-igen): New configuration option.
1094 * configure: Re-generate.
1095
1096 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1097
1098 * interp.c (load_memory, store_memory): Delete parameter RAW.
1099 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1100 bypassing {load,store}_memory.
1101
1102 * sim-main.h (ByteSwapMem): Delete definition.
1103
1104 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1105
1106 * interp.c (sim_do_command, sim_commands): Delete mips specific
1107 commands. Handled by module sim-options.
1108
1109 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1110 (WITH_MODULO_MEMORY): Define.
1111
1112 * interp.c (sim_info): Delete code printing memory size.
1113
1114 * interp.c (mips_size): Nee sim_size, delete function.
1115 (power2): Delete.
1116 (monitor, monitor_base, monitor_size): Delete global variables.
1117 (sim_open, sim_close): Delete code creating monitor and other
1118 memory regions. Use sim-memopts module, via sim_do_commandf, to
1119 manage memory regions.
1120 (load_memory, store_memory): Use sim-core for memory model.
1121
1122 * interp.c (address_translation): Delete all memory map code
1123 except line forcing 32 bit addresses.
1124
1125Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1126
1127 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1128 trace options.
1129
1130 * interp.c (logfh, logfile): Delete globals.
1131 (sim_open, sim_close): Delete code opening & closing log file.
1132 (mips_option_handler): Delete -l and -n options.
1133 (OPTION mips_options): Ditto.
1134
1135 * interp.c (OPTION mips_options): Rename option trace to dinero.
1136 (mips_option_handler): Update.
1137
1138Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1139
1140 * interp.c (fetch_str): New function.
1141 (sim_monitor): Rewrite using sim_read & sim_write.
1142 (sim_open): Check magic number.
1143 (sim_open): Write monitor vectors into memory using sim_write.
1144 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1145 (sim_read, sim_write): Simplify - transfer data one byte at a
1146 time.
1147 (load_memory, store_memory): Clarify meaning of parameter RAW.
1148
1149 * sim-main.h (isHOST): Defete definition.
1150 (isTARGET): Mark as depreciated.
1151 (address_translation): Delete parameter HOST.
1152
1153 * interp.c (address_translation): Delete parameter HOST.
1154
1155Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1156
1157 * mips.igen:
1158
1159 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1160 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1161
1162Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1163
1164 * mips.igen: Add model filter field to records.
1165
1166Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1167
1168 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1169
1170 interp.c (sim_engine_run): Do not compile function sim_engine_run
1171 when WITH_IGEN == 1.
1172
1173 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1174 target architecture.
1175
1176 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1177 igen. Replace with configuration variables sim_igen_flags /
1178 sim_m16_flags.
1179
1180 * m16.igen: New file. Copy mips16 insns here.
1181 * mips.igen: From here.
1182
1183Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1184
1185 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1186 to top.
1187 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1188
1189Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1190
1191 * gencode.c (build_instruction): Follow sim_write's lead in using
1192 BigEndianMem instead of !ByteSwapMem.
1193
1194Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1195
1196 * configure.in (sim_gen): Dependent on target, select type of
1197 generator. Always select old style generator.
1198
1199 configure: Re-generate.
1200
1201 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1202 targets.
1203 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1204 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1205 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1206 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1207 SIM_@sim_gen@_*, set by autoconf.
1208
1209Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1210
1211 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1212
1213 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1214 CURRENT_FLOATING_POINT instead.
1215
1216 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1217 (address_translation): Raise exception InstructionFetch when
1218 translation fails and isINSTRUCTION.
1219
1220 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1221 sim_engine_run): Change type of of vaddr and paddr to
1222 address_word.
1223 (address_translation, prefetch, load_memory, store_memory,
1224 cache_op): Change type of vAddr and pAddr to address_word.
1225
1226 * gencode.c (build_instruction): Change type of vaddr and paddr to
1227 address_word.
1228
1229Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1230
1231 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1232 macro to obtain result of ALU op.
1233
1234Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1235
1236 * interp.c (sim_info): Call profile_print.
1237
1238Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1241
1242 * sim-main.h (WITH_PROFILE): Do not define, defined in
1243 common/sim-config.h. Use sim-profile module.
1244 (simPROFILE): Delete defintion.
1245
1246 * interp.c (PROFILE): Delete definition.
1247 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1248 (sim_close): Delete code writing profile histogram.
1249 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1250 Delete.
1251 (sim_engine_run): Delete code profiling the PC.
1252
1253Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1254
1255 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1256
1257 * interp.c (sim_monitor): Make register pointers of type
1258 unsigned_word*.
1259
1260 * sim-main.h: Make registers of type unsigned_word not
1261 signed_word.
1262
1263Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1264
1265 * interp.c (sync_operation): Rename from SyncOperation, make
1266 global, add SD argument.
1267 (prefetch): Rename from Prefetch, make global, add SD argument.
1268 (decode_coproc): Make global.
1269
1270 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1271
1272 * gencode.c (build_instruction): Generate DecodeCoproc not
1273 decode_coproc calls.
1274
1275 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1276 (SizeFGR): Move to sim-main.h
1277 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1278 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1279 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1280 sim-main.h.
1281 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1282 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1283 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1284 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1285 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1286 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1287
1288 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1289 exception.
1290 (sim-alu.h): Include.
1291 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1292 (sim_cia): Typedef to instruction_address.
1293
1294Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1295
1296 * Makefile.in (interp.o): Rename generated file engine.c to
1297 oengine.c.
1298
1299 * interp.c: Update.
1300
1301Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1302
1303 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1304
1305Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1306
1307 * gencode.c (build_instruction): For "FPSQRT", output correct
1308 number of arguments to Recip.
1309
1310Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1311
1312 * Makefile.in (interp.o): Depends on sim-main.h
1313
1314 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1315
1316 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1317 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1318 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1319 STATE, DSSTATE): Define
1320 (GPR, FGRIDX, ..): Define.
1321
1322 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1323 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1324 (GPR, FGRIDX, ...): Delete macros.
1325
1326 * interp.c: Update names to match defines from sim-main.h
1327
1328Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329
1330 * interp.c (sim_monitor): Add SD argument.
1331 (sim_warning): Delete. Replace calls with calls to
1332 sim_io_eprintf.
1333 (sim_error): Delete. Replace calls with sim_io_error.
1334 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1335 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1336 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1337 argument.
1338 (mips_size): Rename from sim_size. Add SD argument.
1339
1340 * interp.c (simulator): Delete global variable.
1341 (callback): Delete global variable.
1342 (mips_option_handler, sim_open, sim_write, sim_read,
1343 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1344 sim_size,sim_monitor): Use sim_io_* not callback->*.
1345 (sim_open): ZALLOC simulator struct.
1346 (PROFILE): Do not define.
1347
1348Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1349
1350 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1351 support.h with corresponding code.
1352
1353 * sim-main.h (word64, uword64), support.h: Move definition to
1354 sim-main.h.
1355 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1356
1357 * support.h: Delete
1358 * Makefile.in: Update dependencies
1359 * interp.c: Do not include.
1360
1361Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1362
1363 * interp.c (address_translation, load_memory, store_memory,
1364 cache_op): Rename to from AddressTranslation et.al., make global,
1365 add SD argument
1366
1367 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1368 CacheOp): Define.
1369
1370 * interp.c (SignalException): Rename to signal_exception, make
1371 global.
1372
1373 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1374
1375 * sim-main.h (SignalException, SignalExceptionInterrupt,
1376 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1377 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1378 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1379 Define.
1380
1381 * interp.c, support.h: Use.
1382
1383Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1384
1385 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1386 to value_fpr / store_fpr. Add SD argument.
1387 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1388 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1389
1390 * sim-main.h (ValueFPR, StoreFPR): Define.
1391
1392Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * interp.c (sim_engine_run): Check consistency between configure
1395 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1396 and HASFPU.
1397
1398 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1399 (mips_fpu): Configure WITH_FLOATING_POINT.
1400 (mips_endian): Configure WITH_TARGET_ENDIAN.
1401 * configure: Update.
1402
1403Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1404
1405 * configure: Regenerated to track ../common/aclocal.m4 changes.
1406
1407Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1408
1409 * configure: Regenerated.
1410
1411Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1412
1413 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1414
1415Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1416
1417 * gencode.c (print_igen_insn_models): Assume certain architectures
1418 include all mips* instructions.
1419 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1420 instruction.
1421
1422 * Makefile.in (tmp.igen): Add target. Generate igen input from
1423 gencode file.
1424
1425 * gencode.c (FEATURE_IGEN): Define.
1426 (main): Add --igen option. Generate output in igen format.
1427 (process_instructions): Format output according to igen option.
1428 (print_igen_insn_format): New function.
1429 (print_igen_insn_models): New function.
1430 (process_instructions): Only issue warnings and ignore
1431 instructions when no FEATURE_IGEN.
1432
1433Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1436 MIPS targets.
1437
1438Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * configure: Regenerated to track ../common/aclocal.m4 changes.
1441
1442Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1445 SIM_RESERVED_BITS): Delete, moved to common.
1446 (SIM_EXTRA_CFLAGS): Update.
1447
1448Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1449
1450 * configure.in: Configure non-strict memory alignment.
1451 * configure: Regenerated to track ../common/aclocal.m4 changes.
1452
1453Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * configure: Regenerated to track ../common/aclocal.m4 changes.
1456
1457Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1458
1459 * gencode.c (SDBBP,DERET): Added (3900) insns.
1460 (RFE): Turn on for 3900.
1461 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1462 (dsstate): Made global.
1463 (SUBTARGET_R3900): Added.
1464 (CANCELDELAYSLOT): New.
1465 (SignalException): Ignore SystemCall rather than ignore and
1466 terminate. Add DebugBreakPoint handling.
1467 (decode_coproc): New insns RFE, DERET; and new registers Debug
1468 and DEPC protected by SUBTARGET_R3900.
1469 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1470 bits explicitly.
1471 * Makefile.in,configure.in: Add mips subtarget option.
1472 * configure: Update.
1473
1474Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1475
1476 * gencode.c: Add r3900 (tx39).
1477
1478
1479Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1480
1481 * gencode.c (build_instruction): Don't need to subtract 4 for
1482 JALR, just 2.
1483
1484Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1485
1486 * interp.c: Correct some HASFPU problems.
1487
1488Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489
1490 * configure: Regenerated to track ../common/aclocal.m4 changes.
1491
1492Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1493
1494 * interp.c (mips_options): Fix samples option short form, should
1495 be `x'.
1496
1497Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * interp.c (sim_info): Enable info code. Was just returning.
1500
1501Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1504 MFC0.
1505
1506Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1509 constants.
1510 (build_instruction): Ditto for LL.
1511
1512Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1513
1514 * configure: Regenerated to track ../common/aclocal.m4 changes.
1515
1516Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * configure: Regenerated to track ../common/aclocal.m4 changes.
1519 * config.in: Ditto.
1520
1521Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * interp.c (sim_open): Add call to sim_analyze_program, update
1524 call to sim_config.
1525
1526Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1527
1528 * interp.c (sim_kill): Delete.
1529 (sim_create_inferior): Add ABFD argument. Set PC from same.
1530 (sim_load): Move code initializing trap handlers from here.
1531 (sim_open): To here.
1532 (sim_load): Delete, use sim-hload.c.
1533
1534 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1535
1536Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * configure: Regenerated to track ../common/aclocal.m4 changes.
1539 * config.in: Ditto.
1540
1541Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * interp.c (sim_open): Add ABFD argument.
1544 (sim_load): Move call to sim_config from here.
1545 (sim_open): To here. Check return status.
1546
1547Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1548
1549 * gencode.c (build_instruction): Two arg MADD should
1550 not assign result to $0.
1551
1552Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1553
1554 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1555 * sim/mips/configure.in: Regenerate.
1556
1557Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1558
1559 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1560 signed8, unsigned8 et.al. types.
1561
1562 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1563 hosts when selecting subreg.
1564
1565Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1566
1567 * interp.c (sim_engine_run): Reset the ZERO register to zero
1568 regardless of FEATURE_WARN_ZERO.
1569 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1570
1571Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1572
1573 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1574 (SignalException): For BreakPoints ignore any mode bits and just
1575 save the PC.
1576 (SignalException): Always set the CAUSE register.
1577
1578Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1579
1580 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1581 exception has been taken.
1582
1583 * interp.c: Implement the ERET and mt/f sr instructions.
1584
1585Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * interp.c (SignalException): Don't bother restarting an
1588 interrupt.
1589
1590Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591
1592 * interp.c (SignalException): Really take an interrupt.
1593 (interrupt_event): Only deliver interrupts when enabled.
1594
1595Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1596
1597 * interp.c (sim_info): Only print info when verbose.
1598 (sim_info) Use sim_io_printf for output.
1599
1600Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1603 mips architectures.
1604
1605Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1606
1607 * interp.c (sim_do_command): Check for common commands if a
1608 simulator specific command fails.
1609
1610Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1611
1612 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1613 and simBE when DEBUG is defined.
1614
1615Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1616
1617 * interp.c (interrupt_event): New function. Pass exception event
1618 onto exception handler.
1619
1620 * configure.in: Check for stdlib.h.
1621 * configure: Regenerate.
1622
1623 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1624 variable declaration.
1625 (build_instruction): Initialize memval1.
1626 (build_instruction): Add UNUSED attribute to byte, bigend,
1627 reverse.
1628 (build_operands): Ditto.
1629
1630 * interp.c: Fix GCC warnings.
1631 (sim_get_quit_code): Delete.
1632
1633 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1634 * Makefile.in: Ditto.
1635 * configure: Re-generate.
1636
1637 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1638
1639Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * interp.c (mips_option_handler): New function parse argumes using
1642 sim-options.
1643 (myname): Replace with STATE_MY_NAME.
1644 (sim_open): Delete check for host endianness - performed by
1645 sim_config.
1646 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1647 (sim_open): Move much of the initialization from here.
1648 (sim_load): To here. After the image has been loaded and
1649 endianness set.
1650 (sim_open): Move ColdReset from here.
1651 (sim_create_inferior): To here.
1652 (sim_open): Make FP check less dependant on host endianness.
1653
1654 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1655 run.
1656 * interp.c (sim_set_callbacks): Delete.
1657
1658 * interp.c (membank, membank_base, membank_size): Replace with
1659 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1660 (sim_open): Remove call to callback->init. gdb/run do this.
1661
1662 * interp.c: Update
1663
1664 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1665
1666 * interp.c (big_endian_p): Delete, replaced by
1667 current_target_byte_order.
1668
1669Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670
1671 * interp.c (host_read_long, host_read_word, host_swap_word,
1672 host_swap_long): Delete. Using common sim-endian.
1673 (sim_fetch_register, sim_store_register): Use H2T.
1674 (pipeline_ticks): Delete. Handled by sim-events.
1675 (sim_info): Update.
1676 (sim_engine_run): Update.
1677
1678Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1679
1680 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1681 reason from here.
1682 (SignalException): To here. Signal using sim_engine_halt.
1683 (sim_stop_reason): Delete, moved to common.
1684
1685Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1686
1687 * interp.c (sim_open): Add callback argument.
1688 (sim_set_callbacks): Delete SIM_DESC argument.
1689 (sim_size): Ditto.
1690
1691Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1692
1693 * Makefile.in (SIM_OBJS): Add common modules.
1694
1695 * interp.c (sim_set_callbacks): Also set SD callback.
1696 (set_endianness, xfer_*, swap_*): Delete.
1697 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1698 Change to functions using sim-endian macros.
1699 (control_c, sim_stop): Delete, use common version.
1700 (simulate): Convert into.
1701 (sim_engine_run): This function.
1702 (sim_resume): Delete.
1703
1704 * interp.c (simulation): New variable - the simulator object.
1705 (sim_kind): Delete global - merged into simulation.
1706 (sim_load): Cleanup. Move PC assignment from here.
1707 (sim_create_inferior): To here.
1708
1709 * sim-main.h: New file.
1710 * interp.c (sim-main.h): Include.
1711
1712Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1713
1714 * configure: Regenerated to track ../common/aclocal.m4 changes.
1715
1716Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1717
1718 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1719
1720Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1721
1722 * gencode.c (build_instruction): DIV instructions: check
1723 for division by zero and integer overflow before using
1724 host's division operation.
1725
1726Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1727
1728 * Makefile.in (SIM_OBJS): Add sim-load.o.
1729 * interp.c: #include bfd.h.
1730 (target_byte_order): Delete.
1731 (sim_kind, myname, big_endian_p): New static locals.
1732 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1733 after argument parsing. Recognize -E arg, set endianness accordingly.
1734 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1735 load file into simulator. Set PC from bfd.
1736 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1737 (set_endianness): Use big_endian_p instead of target_byte_order.
1738
1739Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * interp.c (sim_size): Delete prototype - conflicts with
1742 definition in remote-sim.h. Correct definition.
1743
1744Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1745
1746 * configure: Regenerated to track ../common/aclocal.m4 changes.
1747 * config.in: Ditto.
1748
1749Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1750
1751 * interp.c (sim_open): New arg `kind'.
1752
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1754
1755Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1756
1757 * configure: Regenerated to track ../common/aclocal.m4 changes.
1758
1759Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1760
1761 * interp.c (sim_open): Set optind to 0 before calling getopt.
1762
1763Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1764
1765 * configure: Regenerated to track ../common/aclocal.m4 changes.
1766
1767Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1768
1769 * interp.c : Replace uses of pr_addr with pr_uword64
1770 where the bit length is always 64 independent of SIM_ADDR.
1771 (pr_uword64) : added.
1772
1773Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1774
1775 * configure: Re-generate.
1776
1777Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1778
1779 * configure: Regenerate to track ../common/aclocal.m4 changes.
1780
1781Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1782
1783 * interp.c (sim_open): New SIM_DESC result. Argument is now
1784 in argv form.
1785 (other sim_*): New SIM_DESC argument.
1786
1787Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1788
1789 * interp.c: Fix printing of addresses for non-64-bit targets.
1790 (pr_addr): Add function to print address based on size.
1791
1792Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1793
1794 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1795
1796Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1797
1798 * gencode.c (build_mips16_operands): Correct computation of base
1799 address for extended PC relative instruction.
1800
1801Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1802
1803 * interp.c (mips16_entry): Add support for floating point cases.
1804 (SignalException): Pass floating point cases to mips16_entry.
1805 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1806 registers.
1807 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1808 or fmt_word.
1809 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1810 and then set the state to fmt_uninterpreted.
1811 (COP_SW): Temporarily set the state to fmt_word while calling
1812 ValueFPR.
1813
1814Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1815
1816 * gencode.c (build_instruction): The high order may be set in the
1817 comparison flags at any ISA level, not just ISA 4.
1818
1819Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1820
1821 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1822 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1823 * configure.in: sinclude ../common/aclocal.m4.
1824 * configure: Regenerated.
1825
1826Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1827
1828 * configure: Rebuild after change to aclocal.m4.
1829
1830Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1831
1832 * configure configure.in Makefile.in: Update to new configure
1833 scheme which is more compatible with WinGDB builds.
1834 * configure.in: Improve comment on how to run autoconf.
1835 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1836 * Makefile.in: Use autoconf substitution to install common
1837 makefile fragment.
1838
1839Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1840
1841 * gencode.c (build_instruction): Use BigEndianCPU instead of
1842 ByteSwapMem.
1843
1844Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1845
1846 * interp.c (sim_monitor): Make output to stdout visible in
1847 wingdb's I/O log window.
1848
1849Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1850
1851 * support.h: Undo previous change to SIGTRAP
1852 and SIGQUIT values.
1853
1854Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1855
1856 * interp.c (store_word, load_word): New static functions.
1857 (mips16_entry): New static function.
1858 (SignalException): Look for mips16 entry and exit instructions.
1859 (simulate): Use the correct index when setting fpr_state after
1860 doing a pending move.
1861
1862Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1863
1864 * interp.c: Fix byte-swapping code throughout to work on
1865 both little- and big-endian hosts.
1866
1867Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1868
1869 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1870 with gdb/config/i386/xm-windows.h.
1871
1872Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1873
1874 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1875 that messes up arithmetic shifts.
1876
1877Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1878
1879 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1880 SIGTRAP and SIGQUIT for _WIN32.
1881
1882Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1883
1884 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1885 force a 64 bit multiplication.
1886 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1887 destination register is 0, since that is the default mips16 nop
1888 instruction.
1889
1890Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1891
1892 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1893 (build_endian_shift): Don't check proc64.
1894 (build_instruction): Always set memval to uword64. Cast op2 to
1895 uword64 when shifting it left in memory instructions. Always use
1896 the same code for stores--don't special case proc64.
1897
1898 * gencode.c (build_mips16_operands): Fix base PC value for PC
1899 relative operands.
1900 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1901 jal instruction.
1902 * interp.c (simJALDELAYSLOT): Define.
1903 (JALDELAYSLOT): Define.
1904 (INDELAYSLOT, INJALDELAYSLOT): Define.
1905 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1906
1907Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1908
1909 * interp.c (sim_open): add flush_cache as a PMON routine
1910 (sim_monitor): handle flush_cache by ignoring it
1911
1912Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1913
1914 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1915 BigEndianMem.
1916 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1917 (BigEndianMem): Rename to ByteSwapMem and change sense.
1918 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1919 BigEndianMem references to !ByteSwapMem.
1920 (set_endianness): New function, with prototype.
1921 (sim_open): Call set_endianness.
1922 (sim_info): Use simBE instead of BigEndianMem.
1923 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1924 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1925 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1926 ifdefs, keeping the prototype declaration.
1927 (swap_word): Rewrite correctly.
1928 (ColdReset): Delete references to CONFIG. Delete endianness related
1929 code; moved to set_endianness.
1930
1931Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1932
1933 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1934 * interp.c (CHECKHILO): Define away.
1935 (simSIGINT): New macro.
1936 (membank_size): Increase from 1MB to 2MB.
1937 (control_c): New function.
1938 (sim_resume): Rename parameter signal to signal_number. Add local
1939 variable prev. Call signal before and after simulate.
1940 (sim_stop_reason): Add simSIGINT support.
1941 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1942 functions always.
1943 (sim_warning): Delete call to SignalException. Do call printf_filtered
1944 if logfh is NULL.
1945 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1946 a call to sim_warning.
1947
1948Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1949
1950 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1951 16 bit instructions.
1952
1953Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1954
1955 Add support for mips16 (16 bit MIPS implementation):
1956 * gencode.c (inst_type): Add mips16 instruction encoding types.
1957 (GETDATASIZEINSN): Define.
1958 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1959 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1960 mtlo.
1961 (MIPS16_DECODE): New table, for mips16 instructions.
1962 (bitmap_val): New static function.
1963 (struct mips16_op): Define.
1964 (mips16_op_table): New table, for mips16 operands.
1965 (build_mips16_operands): New static function.
1966 (process_instructions): If PC is odd, decode a mips16
1967 instruction. Break out instruction handling into new
1968 build_instruction function.
1969 (build_instruction): New static function, broken out of
1970 process_instructions. Check modifiers rather than flags for SHIFT
1971 bit count and m[ft]{hi,lo} direction.
1972 (usage): Pass program name to fprintf.
1973 (main): Remove unused variable this_option_optind. Change
1974 ``*loptarg++'' to ``loptarg++''.
1975 (my_strtoul): Parenthesize && within ||.
1976 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1977 (simulate): If PC is odd, fetch a 16 bit instruction, and
1978 increment PC by 2 rather than 4.
1979 * configure.in: Add case for mips16*-*-*.
1980 * configure: Rebuild.
1981
1982Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1983
1984 * interp.c: Allow -t to enable tracing in standalone simulator.
1985 Fix garbage output in trace file and error messages.
1986
1987Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1988
1989 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1990 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1991 * configure.in: Simplify using macros in ../common/aclocal.m4.
1992 * configure: Regenerated.
1993 * tconfig.in: New file.
1994
1995Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1996
1997 * interp.c: Fix bugs in 64-bit port.
1998 Use ansi function declarations for msvc compiler.
1999 Initialize and test file pointer in trace code.
2000 Prevent duplicate definition of LAST_EMED_REGNUM.
2001
2002Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2003
2004 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2005
2006Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2007
2008 * interp.c (SignalException): Check for explicit terminating
2009 breakpoint value.
2010 * gencode.c: Pass instruction value through SignalException()
2011 calls for Trap, Breakpoint and Syscall.
2012
2013Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2014
2015 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2016 only used on those hosts that provide it.
2017 * configure.in: Add sqrt() to list of functions to be checked for.
2018 * config.in: Re-generated.
2019 * configure: Re-generated.
2020
2021Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2022
2023 * gencode.c (process_instructions): Call build_endian_shift when
2024 expanding STORE RIGHT, to fix swr.
2025 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2026 clear the high bits.
2027 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2028 Fix float to int conversions to produce signed values.
2029
2030Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2031
2032 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2033 (process_instructions): Correct handling of nor instruction.
2034 Correct shift count for 32 bit shift instructions. Correct sign
2035 extension for arithmetic shifts to not shift the number of bits in
2036 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2037 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2038 Fix madd.
2039 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2040 It's OK to have a mult follow a mult. What's not OK is to have a
2041 mult follow an mfhi.
2042 (Convert): Comment out incorrect rounding code.
2043
2044Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2045
2046 * interp.c (sim_monitor): Improved monitor printf
2047 simulation. Tidied up simulator warnings, and added "--log" option
2048 for directing warning message output.
2049 * gencode.c: Use sim_warning() rather than WARNING macro.
2050
2051Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2052
2053 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2054 getopt1.o, rather than on gencode.c. Link objects together.
2055 Don't link against -liberty.
2056 (gencode.o, getopt.o, getopt1.o): New targets.
2057 * gencode.c: Include <ctype.h> and "ansidecl.h".
2058 (AND): Undefine after including "ansidecl.h".
2059 (ULONG_MAX): Define if not defined.
2060 (OP_*): Don't define macros; now defined in opcode/mips.h.
2061 (main): Call my_strtoul rather than strtoul.
2062 (my_strtoul): New static function.
2063
2064Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2065
2066 * gencode.c (process_instructions): Generate word64 and uword64
2067 instead of `long long' and `unsigned long long' data types.
2068 * interp.c: #include sysdep.h to get signals, and define default
2069 for SIGBUS.
2070 * (Convert): Work around for Visual-C++ compiler bug with type
2071 conversion.
2072 * support.h: Make things compile under Visual-C++ by using
2073 __int64 instead of `long long'. Change many refs to long long
2074 into word64/uword64 typedefs.
2075
2076Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2077
2078 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2079 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2080 (docdir): Removed.
2081 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2082 (AC_PROG_INSTALL): Added.
2083 (AC_PROG_CC): Moved to before configure.host call.
2084 * configure: Rebuilt.
2085
2086Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2087
2088 * configure.in: Define @SIMCONF@ depending on mips target.
2089 * configure: Rebuild.
2090 * Makefile.in (run): Add @SIMCONF@ to control simulator
2091 construction.
2092 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2093 * interp.c: Remove some debugging, provide more detailed error
2094 messages, update memory accesses to use LOADDRMASK.
2095
2096Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2097
2098 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2099 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2100 stamp-h.
2101 * configure: Rebuild.
2102 * config.in: New file, generated by autoheader.
2103 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2104 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2105 HAVE_ANINT and HAVE_AINT, as appropriate.
2106 * Makefile.in (run): Use @LIBS@ rather than -lm.
2107 (interp.o): Depend upon config.h.
2108 (Makefile): Just rebuild Makefile.
2109 (clean): Remove stamp-h.
2110 (mostlyclean): Make the same as clean, not as distclean.
2111 (config.h, stamp-h): New targets.
2112
2113Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2114
2115 * interp.c (ColdReset): Fix boolean test. Make all simulator
2116 globals static.
2117
2118Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2119
2120 * interp.c (xfer_direct_word, xfer_direct_long,
2121 swap_direct_word, swap_direct_long, xfer_big_word,
2122 xfer_big_long, xfer_little_word, xfer_little_long,
2123 swap_word,swap_long): Added.
2124 * interp.c (ColdReset): Provide function indirection to
2125 host<->simulated_target transfer routines.
2126 * interp.c (sim_store_register, sim_fetch_register): Updated to
2127 make use of indirected transfer routines.
2128
2129Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2130
2131 * gencode.c (process_instructions): Ensure FP ABS instruction
2132 recognised.
2133 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2134 system call support.
2135
2136Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2137
2138 * interp.c (sim_do_command): Complain if callback structure not
2139 initialised.
2140
2141Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2142
2143 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2144 support for Sun hosts.
2145 * Makefile.in (gencode): Ensure the host compiler and libraries
2146 used for cross-hosted build.
2147
2148Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2149
2150 * interp.c, gencode.c: Some more (TODO) tidying.
2151
2152Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2153
2154 * gencode.c, interp.c: Replaced explicit long long references with
2155 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2156 * support.h (SET64LO, SET64HI): Macros added.
2157
2158Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2159
2160 * configure: Regenerate with autoconf 2.7.
2161
2162Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2163
2164 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2165 * support.h: Remove superfluous "1" from #if.
2166 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2167
2168Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2169
2170 * interp.c (StoreFPR): Control UndefinedResult() call on
2171 WARN_RESULT manifest.
2172
2173Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2174
2175 * gencode.c: Tidied instruction decoding, and added FP instruction
2176 support.
2177
2178 * interp.c: Added dineroIII, and BSD profiling support. Also
2179 run-time FP handling.
2180
2181Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2182
2183 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2184 gencode.c, interp.c, support.h: created.
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