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target/sh4: Use translator_use_goto_tb
[thirdparty/qemu.git] / target / sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
5650b549 10 version 2.1 of the License, or (at your option) any later version.
7a3f1944
FB		 11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
dcb32f1d 27#include "tcg/tcg-op.h"
f08b6170 28#include "exec/cpu_ldst.h"
7a3f1944 29
2ef6175a 30#include "exec/helper-gen.h"
a7812ae4 31
c5e6ccdf 32#include "exec/translator.h"
508127e2 33#include "exec/log.h"
0cc1f4bf 34#include "asi.h"
a7e30d84
LV		 35
36
7a3f1944
FB		 37#define DEBUG_DISAS
38
72cbca10
FB		 39#define DYNAMIC_PC 1 /* dynamic pc value */
40#define JUMP_PC 2 /* dynamic pc value which takes only two values
41 according to jump_pc[T2] */
42
46bb0137
MCA		 43#define DISAS_EXIT DISAS_TARGET_0
44
1a2fb1c0 45/* global register indexes */
1bcea73e 46static TCGv_ptr cpu_regwptr;
25517f99
PB		 47static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
48static TCGv_i32 cpu_cc_op;
a7812ae4 49static TCGv_i32 cpu_psr;
d2dc4069
RH		 50static TCGv cpu_fsr, cpu_pc, cpu_npc;
51static TCGv cpu_regs[32];
255e1fcb
BS		 52static TCGv cpu_y;
53#ifndef CONFIG_USER_ONLY
54static TCGv cpu_tbr;
55#endif
5793f2a4 56static TCGv cpu_cond;
dc99a3f2 57#ifdef TARGET_SPARC64
a6d567e5 58static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 59static TCGv cpu_gsr;
255e1fcb 60static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4 61static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
255e1fcb
BS		 62#else
63static TCGv cpu_wim;
dc99a3f2 64#endif
714547bb 65/* Floating point registers */
30038fd8 66static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 67
022c62cb 68#include "exec/gen-icount.h"
2e70f6ef 69
7a3f1944 70typedef struct DisasContext {
af00be49 71 DisasContextBase base;
0f8a249a
BS		 72 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
73 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 74 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
e8af50a3 75 int mem_idx;
c9b459aa
AT		 76 bool fpu_enabled;
77 bool address_mask_32bit;
c9b459aa
AT		 78#ifndef CONFIG_USER_ONLY
79 bool supervisor;
80#ifdef TARGET_SPARC64
81 bool hypervisor;
82#endif
83#endif
84
8393617c 85 uint32_t cc_op; /* current CC operation */
5578ceab 86 sparc_def_t *def;
30038fd8 87 TCGv_i32 t32[3];
88023616 88 TCGv ttl[5];
30038fd8 89 int n_t32;
88023616 90 int n_ttl;
a6d567e5 91#ifdef TARGET_SPARC64
f9c816c0 92 int fprs_dirty;
a6d567e5
RH		 93 int asi;
94#endif
7a3f1944
FB		 95} DisasContext;
96
416fcaea
RH		 97typedef struct {
98 TCGCond cond;
99 bool is_bool;
100 bool g1, g2;
101 TCGv c1, c2;
102} DisasCompare;
103
3475187d 104// This function uses non-native bit order
dc1a6971
BS		 105#define GET_FIELD(X, FROM, TO) \
106 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 107
3475187d 108// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 109#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 110 GET_FIELD(X, 31 - (TO), 31 - (FROM))
111
112#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 113#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 114
115#ifdef TARGET_SPARC64
0387d928 116#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 117#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 118#else
c185970a 119#define DFPREG(r) (r & 0x1e)
1f587329 120#define QFPREG(r) (r & 0x1c)
3475187d
FB		 121#endif
122
b158a785
BS		 123#define UA2005_HTRAP_MASK 0xff
124#define V8_TRAP_MASK 0x7f
125
3475187d
FB		 126static int sign_extend(int x, int len)
127{
128 len = 32 - len;
129 return (x << len) >> len;
130}
131
7a3f1944
FB		 132#define IS_IMM (insn & (1<<13))
133
2ae23e17
RH		 134static inline TCGv_i32 get_temp_i32(DisasContext *dc)
135{
136 TCGv_i32 t;
137 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
138 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
139 return t;
140}
141
142static inline TCGv get_temp_tl(DisasContext *dc)
143{
144 TCGv t;
145 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
146 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
147 return t;
148}
149
f9c816c0 150static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
141ae5c1
RH		 151{
152#if defined(TARGET_SPARC64)
f9c816c0
RH		 153 int bit = (rd < 32) ? 1 : 2;
154 /* If we know we've already set this bit within the TB,
155 we can avoid setting it again. */
156 if (!(dc->fprs_dirty & bit)) {
157 dc->fprs_dirty |= bit;
158 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
159 }
141ae5c1
RH		 160#endif
161}
162
ff07ec83 163/* floating point registers moves */
208ae657
RH		 164static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
165{
30038fd8
RH		 166#if TCG_TARGET_REG_BITS == 32
167 if (src & 1) {
168 return TCGV_LOW(cpu_fpr[src / 2]);
169 } else {
170 return TCGV_HIGH(cpu_fpr[src / 2]);
171 }
172#else
dc41aa7d 173 TCGv_i32 ret = get_temp_i32(dc);
30038fd8 174 if (src & 1) {
dc41aa7d 175 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 176 } else {
dc41aa7d 177 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 178 }
dc41aa7d 179 return ret;
30038fd8 180#endif
208ae657
RH		 181}
182
183static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
184{
30038fd8
RH		 185#if TCG_TARGET_REG_BITS == 32
186 if (dst & 1) {
187 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
188 } else {
189 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
190 }
191#else
dc41aa7d 192 TCGv_i64 t = (TCGv_i64)v;
30038fd8
RH		 193 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
194 (dst & 1 ? 0 : 32), 32);
195#endif
f9c816c0 196 gen_update_fprs_dirty(dc, dst);
208ae657
RH		 197}
198
ba5f5179 199static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 200{
ba5f5179 201 return get_temp_i32(dc);
208ae657
RH		 202}
203
96eda024
RH		 204static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
205{
96eda024 206 src = DFPREG(src);
30038fd8 207 return cpu_fpr[src / 2];
96eda024
RH		 208}
209
210static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
211{
212 dst = DFPREG(dst);
30038fd8 213 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
f9c816c0 214 gen_update_fprs_dirty(dc, dst);
96eda024
RH		 215}
216
3886b8a3 217static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 218{
3886b8a3 219 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 220}
221
ff07ec83
BS		 222static void gen_op_load_fpr_QT0(unsigned int src)
223{
30038fd8
RH		 224 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
225 offsetof(CPU_QuadU, ll.upper));
226 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
227 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 228}
229
230static void gen_op_load_fpr_QT1(unsigned int src)
231{
30038fd8
RH		 232 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
233 offsetof(CPU_QuadU, ll.upper));
234 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
235 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 236}
237
238static void gen_op_store_QT0_fpr(unsigned int dst)
239{
30038fd8
RH		 240 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
241 offsetof(CPU_QuadU, ll.upper));
242 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
243 offsetof(CPU_QuadU, ll.lower));
ff07ec83 244}
1f587329 245
f939ffe5
RH		 246static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
247 TCGv_i64 v1, TCGv_i64 v2)
248{
249 dst = QFPREG(dst);
250
251 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
252 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
253 gen_update_fprs_dirty(dc, dst);
254}
255
ac11f776 256#ifdef TARGET_SPARC64
f939ffe5
RH		 257static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
258{
259 src = QFPREG(src);
260 return cpu_fpr[src / 2];
261}
262
263static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
264{
265 src = QFPREG(src);
266 return cpu_fpr[src / 2 + 1];
267}
268
f9c816c0 269static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
ac11f776
RH		 270{
271 rd = QFPREG(rd);
272 rs = QFPREG(rs);
273
30038fd8
RH		 274 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
275 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
f9c816c0 276 gen_update_fprs_dirty(dc, rd);
ac11f776
RH		 277}
278#endif
279
81ad8ba2
BS		 280/* moves */
281#ifdef CONFIG_USER_ONLY
3475187d 282#define supervisor(dc) 0
81ad8ba2 283#ifdef TARGET_SPARC64
e9ebed4d 284#define hypervisor(dc) 0
81ad8ba2 285#endif
3475187d 286#else
81ad8ba2 287#ifdef TARGET_SPARC64
c9b459aa
AT		 288#define hypervisor(dc) (dc->hypervisor)
289#define supervisor(dc) (dc->supervisor | dc->hypervisor)
6f27aba6 290#else
c9b459aa 291#define supervisor(dc) (dc->supervisor)
3475187d 292#endif
81ad8ba2
BS		 293#endif
294
2cade6a3
BS		 295#ifdef TARGET_SPARC64
296#ifndef TARGET_ABI32
297#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 298#else
2cade6a3
BS		 299#define AM_CHECK(dc) (1)
300#endif
1a2fb1c0 301#endif
3391c818 302
2cade6a3
BS		 303static inline void gen_address_mask(DisasContext *dc, TCGv addr)
304{
305#ifdef TARGET_SPARC64
306 if (AM_CHECK(dc))
307 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
308#endif
309}
310
88023616
RH		 311static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
312{
d2dc4069
RH		 313 if (reg > 0) {
314 assert(reg < 32);
315 return cpu_regs[reg];
316 } else {
88023616 317 TCGv t = get_temp_tl(dc);
d2dc4069 318 tcg_gen_movi_tl(t, 0);
88023616 319 return t;
88023616
RH		 320 }
321}
322
323static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
324{
325 if (reg > 0) {
d2dc4069
RH		 326 assert(reg < 32);
327 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 328 }
329}
330
331static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
332{
d2dc4069
RH		 333 if (reg > 0) {
334 assert(reg < 32);
335 return cpu_regs[reg];
88023616 336 } else {
d2dc4069 337 return get_temp_tl(dc);
88023616
RH		 338 }
339}
340
90aa39a1
SF		 341static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
342 target_ulong npc)
343{
af00be49 344 if (unlikely(s->base.singlestep_enabled || singlestep)) {
90aa39a1
SF		 345 return false;
346 }
347
348#ifndef CONFIG_USER_ONLY
af00be49
EC		 349 return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) &&
350 (npc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK);
90aa39a1
SF		 351#else
352 return true;
353#endif
354}
355
5fafdf24 356static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 357 target_ulong pc, target_ulong npc)
358{
90aa39a1 359 if (use_goto_tb(s, pc, npc)) {
6e256c93 360 /* jump to same page: we can use a direct jump */
57fec1fe 361 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 362 tcg_gen_movi_tl(cpu_pc, pc);
363 tcg_gen_movi_tl(cpu_npc, npc);
07ea28b4 364 tcg_gen_exit_tb(s->base.tb, tb_num);
6e256c93
FB		 365 } else {
366 /* jump to another page: currently not optimized */
2f5680ee
BS		 367 tcg_gen_movi_tl(cpu_pc, pc);
368 tcg_gen_movi_tl(cpu_npc, npc);
07ea28b4 369 tcg_gen_exit_tb(NULL, 0);
6e256c93
FB		 370 }
371}
372
19f329ad 373// XXX suboptimal
a7812ae4 374static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 375{
8911f501 376 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 377 tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
19f329ad
BS		 378}
379
a7812ae4 380static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 381{
8911f501 382 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 383 tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
19f329ad
BS		 384}
385
a7812ae4 386static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 387{
8911f501 388 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 389 tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
19f329ad
BS		 390}
391
a7812ae4 392static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 393{
8911f501 394 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 395 tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
19f329ad
BS		 396}
397
4af984a7 398static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 399{
4af984a7 400 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 401 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 402 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 403 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 404}
405
70c48285 406static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 407{
70c48285
RH		 408 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
409
410 /* Carry is computed from a previous add: (dst < src) */
411#if TARGET_LONG_BITS == 64
412 cc_src1_32 = tcg_temp_new_i32();
413 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 414 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
415 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 416#else
417 cc_src1_32 = cpu_cc_dst;
418 cc_src2_32 = cpu_cc_src;
419#endif
420
421 carry_32 = tcg_temp_new_i32();
422 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
423
424#if TARGET_LONG_BITS == 64
425 tcg_temp_free_i32(cc_src1_32);
426 tcg_temp_free_i32(cc_src2_32);
427#endif
428
429 return carry_32;
41d72852
BS		 430}
431
70c48285 432static TCGv_i32 gen_sub32_carry32(void)
41d72852 433{
70c48285
RH		 434 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
435
436 /* Carry is computed from a previous borrow: (src1 < src2) */
437#if TARGET_LONG_BITS == 64
438 cc_src1_32 = tcg_temp_new_i32();
439 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 440 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
441 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 442#else
443 cc_src1_32 = cpu_cc_src;
444 cc_src2_32 = cpu_cc_src2;
445#endif
446
447 carry_32 = tcg_temp_new_i32();
448 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
449
450#if TARGET_LONG_BITS == 64
451 tcg_temp_free_i32(cc_src1_32);
452 tcg_temp_free_i32(cc_src2_32);
453#endif
454
455 return carry_32;
456}
457
458static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
459 TCGv src2, int update_cc)
460{
461 TCGv_i32 carry_32;
462 TCGv carry;
463
464 switch (dc->cc_op) {
465 case CC_OP_DIV:
466 case CC_OP_LOGIC:
467 /* Carry is known to be zero. Fall back to plain ADD. */
468 if (update_cc) {
469 gen_op_add_cc(dst, src1, src2);
470 } else {
471 tcg_gen_add_tl(dst, src1, src2);
472 }
473 return;
474
475 case CC_OP_ADD:
476 case CC_OP_TADD:
477 case CC_OP_TADDTV:
15fe216f
RH		 478 if (TARGET_LONG_BITS == 32) {
479 /* We can re-use the host's hardware carry generation by using
480 an ADD2 opcode. We discard the low part of the output.
481 Ideally we'd combine this operation with the add that
482 generated the carry in the first place. */
483 carry = tcg_temp_new();
484 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
485 tcg_temp_free(carry);
70c48285
RH		 486 goto add_done;
487 }
70c48285
RH		 488 carry_32 = gen_add32_carry32();
489 break;
490
491 case CC_OP_SUB:
492 case CC_OP_TSUB:
493 case CC_OP_TSUBTV:
494 carry_32 = gen_sub32_carry32();
495 break;
496
497 default:
498 /* We need external help to produce the carry. */
499 carry_32 = tcg_temp_new_i32();
2ffd9176 500 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 501 break;
502 }
503
504#if TARGET_LONG_BITS == 64
505 carry = tcg_temp_new();
506 tcg_gen_extu_i32_i64(carry, carry_32);
507#else
508 carry = carry_32;
509#endif
510
511 tcg_gen_add_tl(dst, src1, src2);
512 tcg_gen_add_tl(dst, dst, carry);
513
514 tcg_temp_free_i32(carry_32);
515#if TARGET_LONG_BITS == 64
516 tcg_temp_free(carry);
517#endif
518
70c48285 519 add_done:
70c48285
RH		 520 if (update_cc) {
521 tcg_gen_mov_tl(cpu_cc_src, src1);
522 tcg_gen_mov_tl(cpu_cc_src2, src2);
523 tcg_gen_mov_tl(cpu_cc_dst, dst);
524 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
525 dc->cc_op = CC_OP_ADDX;
526 }
dc99a3f2
BS		 527}
528
41d72852 529static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 530{
4af984a7 531 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 532 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 533 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 534 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 535}
536
70c48285
RH		 537static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
538 TCGv src2, int update_cc)
41d72852 539{
70c48285
RH		 540 TCGv_i32 carry_32;
541 TCGv carry;
41d72852 542
70c48285
RH		 543 switch (dc->cc_op) {
544 case CC_OP_DIV:
545 case CC_OP_LOGIC:
546 /* Carry is known to be zero. Fall back to plain SUB. */
547 if (update_cc) {
548 gen_op_sub_cc(dst, src1, src2);
549 } else {
550 tcg_gen_sub_tl(dst, src1, src2);
551 }
552 return;
553
554 case CC_OP_ADD:
555 case CC_OP_TADD:
556 case CC_OP_TADDTV:
557 carry_32 = gen_add32_carry32();
558 break;
559
560 case CC_OP_SUB:
561 case CC_OP_TSUB:
562 case CC_OP_TSUBTV:
15fe216f
RH		 563 if (TARGET_LONG_BITS == 32) {
564 /* We can re-use the host's hardware carry generation by using
565 a SUB2 opcode. We discard the low part of the output.
566 Ideally we'd combine this operation with the add that
567 generated the carry in the first place. */
568 carry = tcg_temp_new();
569 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
570 tcg_temp_free(carry);
70c48285
RH		 571 goto sub_done;
572 }
70c48285
RH		 573 carry_32 = gen_sub32_carry32();
574 break;
575
576 default:
577 /* We need external help to produce the carry. */
578 carry_32 = tcg_temp_new_i32();
2ffd9176 579 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 580 break;
581 }
582
583#if TARGET_LONG_BITS == 64
584 carry = tcg_temp_new();
585 tcg_gen_extu_i32_i64(carry, carry_32);
586#else
587 carry = carry_32;
588#endif
589
590 tcg_gen_sub_tl(dst, src1, src2);
591 tcg_gen_sub_tl(dst, dst, carry);
592
593 tcg_temp_free_i32(carry_32);
594#if TARGET_LONG_BITS == 64
595 tcg_temp_free(carry);
596#endif
597
70c48285 598 sub_done:
70c48285
RH		 599 if (update_cc) {
600 tcg_gen_mov_tl(cpu_cc_src, src1);
601 tcg_gen_mov_tl(cpu_cc_src2, src2);
602 tcg_gen_mov_tl(cpu_cc_dst, dst);
603 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
604 dc->cc_op = CC_OP_SUBX;
605 }
dc99a3f2
BS		 606}
607
4af984a7 608static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 609{
de9e9d9f 610 TCGv r_temp, zero, t0;
d9bdab86 611
a7812ae4 612 r_temp = tcg_temp_new();
de9e9d9f 613 t0 = tcg_temp_new();
d9bdab86
BS		 614
615 /* old op:
616 if (!(env->y & 1))
617 T1 = 0;
618 */
6cb675b0 619 zero = tcg_const_tl(0);
72ccba79 620 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 621 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 622 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 623 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
624 zero, cpu_cc_src2);
625 tcg_temp_free(zero);
d9bdab86
BS		 626
627 // b2 = T0 & 1;
628 // env->y = (b2 << 31) | (env->y >> 1);
0b1183e3 629 tcg_gen_extract_tl(t0, cpu_y, 1, 31);
08d64e0d 630 tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
d9bdab86
BS		 631
632 // b1 = N ^ V;
de9e9d9f 633 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 634 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 635 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 636 tcg_temp_free(r_temp);
d9bdab86
BS		 637
638 // T0 = (b1 << 31) | (T0 >> 1);
639 // src1 = T0;
de9e9d9f 640 tcg_gen_shli_tl(t0, t0, 31);
6f551262 641 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 642 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
643 tcg_temp_free(t0);
d9bdab86 644
5c6a0628 645 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 646
5c6a0628 647 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 648}
649
fb170183 650static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 651{
528692a8 652#if TARGET_LONG_BITS == 32
fb170183 653 if (sign_ext) {
528692a8 654 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 655 } else {
528692a8 656 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 657 }
528692a8
RH		 658#else
659 TCGv t0 = tcg_temp_new_i64();
660 TCGv t1 = tcg_temp_new_i64();
fb170183 661
528692a8
RH		 662 if (sign_ext) {
663 tcg_gen_ext32s_i64(t0, src1);
664 tcg_gen_ext32s_i64(t1, src2);
665 } else {
666 tcg_gen_ext32u_i64(t0, src1);
667 tcg_gen_ext32u_i64(t1, src2);
668 }
fb170183 669
528692a8
RH		 670 tcg_gen_mul_i64(dst, t0, t1);
671 tcg_temp_free(t0);
672 tcg_temp_free(t1);
fb170183 673
528692a8
RH		 674 tcg_gen_shri_i64(cpu_y, dst, 32);
675#endif
8879d139
BS		 676}
677
fb170183 678static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 679{
fb170183
IK		 680 /* zero-extend truncated operands before multiplication */
681 gen_op_multiply(dst, src1, src2, 0);
682}
8879d139 683
fb170183
IK		 684static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
685{
686 /* sign-extend truncated operands before multiplication */
687 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 688}
689
19f329ad
BS		 690// 1
691static inline void gen_op_eval_ba(TCGv dst)
692{
693 tcg_gen_movi_tl(dst, 1);
694}
695
696// Z
a7812ae4 697static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 698{
699 gen_mov_reg_Z(dst, src);
700}
701
702// Z | (N ^ V)
a7812ae4 703static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 704{
de9e9d9f
RH		 705 TCGv t0 = tcg_temp_new();
706 gen_mov_reg_N(t0, src);
19f329ad 707 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 708 tcg_gen_xor_tl(dst, dst, t0);
709 gen_mov_reg_Z(t0, src);
710 tcg_gen_or_tl(dst, dst, t0);
711 tcg_temp_free(t0);
19f329ad
BS		 712}
713
714// N ^ V
a7812ae4 715static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 716{
de9e9d9f
RH		 717 TCGv t0 = tcg_temp_new();
718 gen_mov_reg_V(t0, src);
19f329ad 719 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 720 tcg_gen_xor_tl(dst, dst, t0);
721 tcg_temp_free(t0);
19f329ad
BS		 722}
723
724// C | Z
a7812ae4 725static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 726{
de9e9d9f
RH		 727 TCGv t0 = tcg_temp_new();
728 gen_mov_reg_Z(t0, src);
19f329ad 729 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 730 tcg_gen_or_tl(dst, dst, t0);
731 tcg_temp_free(t0);
19f329ad
BS		 732}
733
734// C
a7812ae4 735static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 736{
737 gen_mov_reg_C(dst, src);
738}
739
740// V
a7812ae4 741static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 742{
743 gen_mov_reg_V(dst, src);
744}
745
746// 0
747static inline void gen_op_eval_bn(TCGv dst)
748{
749 tcg_gen_movi_tl(dst, 0);
750}
751
752// N
a7812ae4 753static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 754{
755 gen_mov_reg_N(dst, src);
756}
757
758// !Z
a7812ae4 759static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 760{
761 gen_mov_reg_Z(dst, src);
762 tcg_gen_xori_tl(dst, dst, 0x1);
763}
764
765// !(Z | (N ^ V))
a7812ae4 766static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 767{
de9e9d9f 768 gen_op_eval_ble(dst, src);
19f329ad
BS		 769 tcg_gen_xori_tl(dst, dst, 0x1);
770}
771
772// !(N ^ V)
a7812ae4 773static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 774{
de9e9d9f 775 gen_op_eval_bl(dst, src);
19f329ad
BS		 776 tcg_gen_xori_tl(dst, dst, 0x1);
777}
778
779// !(C | Z)
a7812ae4 780static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 781{
de9e9d9f 782 gen_op_eval_bleu(dst, src);
19f329ad
BS		 783 tcg_gen_xori_tl(dst, dst, 0x1);
784}
785
786// !C
a7812ae4 787static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 788{
789 gen_mov_reg_C(dst, src);
790 tcg_gen_xori_tl(dst, dst, 0x1);
791}
792
793// !N
a7812ae4 794static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 795{
796 gen_mov_reg_N(dst, src);
797 tcg_gen_xori_tl(dst, dst, 0x1);
798}
799
800// !V
a7812ae4 801static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 802{
803 gen_mov_reg_V(dst, src);
804 tcg_gen_xori_tl(dst, dst, 0x1);
805}
806
807/*
808 FPSR bit field FCC1 | FCC0:
809 0 =
810 1 <
811 2 >
812 3 unordered
813*/
814static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
815 unsigned int fcc_offset)
816{
ba6a9d8c 817 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 818 tcg_gen_andi_tl(reg, reg, 0x1);
819}
820
821static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
822 unsigned int fcc_offset)
823{
ba6a9d8c 824 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 825 tcg_gen_andi_tl(reg, reg, 0x1);
826}
827
828// !0: FCC0 | FCC1
829static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
830 unsigned int fcc_offset)
831{
de9e9d9f 832 TCGv t0 = tcg_temp_new();
19f329ad 833 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 834 gen_mov_reg_FCC1(t0, src, fcc_offset);
835 tcg_gen_or_tl(dst, dst, t0);
836 tcg_temp_free(t0);
19f329ad
BS		 837}
838
839// 1 or 2: FCC0 ^ FCC1
840static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
841 unsigned int fcc_offset)
842{
de9e9d9f 843 TCGv t0 = tcg_temp_new();
19f329ad 844 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 845 gen_mov_reg_FCC1(t0, src, fcc_offset);
846 tcg_gen_xor_tl(dst, dst, t0);
847 tcg_temp_free(t0);
19f329ad
BS		 848}
849
850// 1 or 3: FCC0
851static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
852 unsigned int fcc_offset)
853{
854 gen_mov_reg_FCC0(dst, src, fcc_offset);
855}
856
857// 1: FCC0 & !FCC1
858static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
859 unsigned int fcc_offset)
860{
de9e9d9f 861 TCGv t0 = tcg_temp_new();
19f329ad 862 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 863 gen_mov_reg_FCC1(t0, src, fcc_offset);
864 tcg_gen_andc_tl(dst, dst, t0);
865 tcg_temp_free(t0);
19f329ad
BS		 866}
867
868// 2 or 3: FCC1
869static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
870 unsigned int fcc_offset)
871{
872 gen_mov_reg_FCC1(dst, src, fcc_offset);
873}
874
875// 2: !FCC0 & FCC1
876static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
877 unsigned int fcc_offset)
878{
de9e9d9f 879 TCGv t0 = tcg_temp_new();
19f329ad 880 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 881 gen_mov_reg_FCC1(t0, src, fcc_offset);
882 tcg_gen_andc_tl(dst, t0, dst);
883 tcg_temp_free(t0);
19f329ad
BS		 884}
885
886// 3: FCC0 & FCC1
887static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
888 unsigned int fcc_offset)
889{
de9e9d9f 890 TCGv t0 = tcg_temp_new();
19f329ad 891 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 892 gen_mov_reg_FCC1(t0, src, fcc_offset);
893 tcg_gen_and_tl(dst, dst, t0);
894 tcg_temp_free(t0);
19f329ad
BS		 895}
896
897// 0: !(FCC0 | FCC1)
898static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
899 unsigned int fcc_offset)
900{
de9e9d9f 901 TCGv t0 = tcg_temp_new();
19f329ad 902 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 903 gen_mov_reg_FCC1(t0, src, fcc_offset);
904 tcg_gen_or_tl(dst, dst, t0);
19f329ad 905 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 906 tcg_temp_free(t0);
19f329ad
BS		 907}
908
909// 0 or 3: !(FCC0 ^ FCC1)
910static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
911 unsigned int fcc_offset)
912{
de9e9d9f 913 TCGv t0 = tcg_temp_new();
19f329ad 914 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 915 gen_mov_reg_FCC1(t0, src, fcc_offset);
916 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 917 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 918 tcg_temp_free(t0);
19f329ad
BS		 919}
920
921// 0 or 2: !FCC0
922static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
923 unsigned int fcc_offset)
924{
925 gen_mov_reg_FCC0(dst, src, fcc_offset);
926 tcg_gen_xori_tl(dst, dst, 0x1);
927}
928
929// !1: !(FCC0 & !FCC1)
930static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
931 unsigned int fcc_offset)
932{
de9e9d9f 933 TCGv t0 = tcg_temp_new();
19f329ad 934 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 935 gen_mov_reg_FCC1(t0, src, fcc_offset);
936 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 937 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 938 tcg_temp_free(t0);
19f329ad
BS		 939}
940
941// 0 or 1: !FCC1
942static inline void gen_op_eval_fble(TCGv dst, TCGv src,
943 unsigned int fcc_offset)
944{
945 gen_mov_reg_FCC1(dst, src, fcc_offset);
946 tcg_gen_xori_tl(dst, dst, 0x1);
947}
948
949// !2: !(!FCC0 & FCC1)
950static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
951 unsigned int fcc_offset)
952{
de9e9d9f 953 TCGv t0 = tcg_temp_new();
19f329ad 954 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 955 gen_mov_reg_FCC1(t0, src, fcc_offset);
956 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 957 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 958 tcg_temp_free(t0);
19f329ad
BS		 959}
960
961// !3: !(FCC0 & FCC1)
962static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
963 unsigned int fcc_offset)
964{
de9e9d9f 965 TCGv t0 = tcg_temp_new();
19f329ad 966 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 967 gen_mov_reg_FCC1(t0, src, fcc_offset);
968 tcg_gen_and_tl(dst, dst, t0);
19f329ad 969 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 970 tcg_temp_free(t0);
19f329ad
BS		 971}
972
46525e1f 973static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 974 target_ulong pc2, TCGv r_cond)
83469015 975{
42a268c2 976 TCGLabel *l1 = gen_new_label();
83469015 977
cb63669a 978 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 979
6e256c93 980 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 981
982 gen_set_label(l1);
6e256c93 983 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 984}
985
bfa31b76 986static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 987{
42a268c2 988 TCGLabel *l1 = gen_new_label();
bfa31b76 989 target_ulong npc = dc->npc;
83469015 990
bfa31b76 991 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 992
bfa31b76 993 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 994
995 gen_set_label(l1);
bfa31b76
RH		 996 gen_goto_tb(dc, 1, npc + 4, npc + 8);
997
af00be49 998 dc->base.is_jmp = DISAS_NORETURN;
83469015
FB		 999}
1000
2bf2e019
RH		 1001static void gen_branch_n(DisasContext *dc, target_ulong pc1)
1002{
1003 target_ulong npc = dc->npc;
1004
1005 if (likely(npc != DYNAMIC_PC)) {
1006 dc->pc = npc;
1007 dc->jump_pc[0] = pc1;
1008 dc->jump_pc[1] = npc + 4;
1009 dc->npc = JUMP_PC;
1010 } else {
1011 TCGv t, z;
1012
1013 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1014
1015 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1016 t = tcg_const_tl(pc1);
1017 z = tcg_const_tl(0);
1018 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
1019 tcg_temp_free(t);
1020 tcg_temp_free(z);
1021
1022 dc->pc = DYNAMIC_PC;
1023 }
1024}
1025
2e655fe7 1026static inline void gen_generic_branch(DisasContext *dc)
83469015 1027{
61316742
RH		 1028 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1029 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1030 TCGv zero = tcg_const_tl(0);
19f329ad 1031
61316742 1032 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1033
61316742
RH		 1034 tcg_temp_free(npc0);
1035 tcg_temp_free(npc1);
1036 tcg_temp_free(zero);
83469015
FB		 1037}
1038
4af984a7
BS		 1039/* call this function before using the condition register as it may
1040 have been set for a jump */
dee8913c 1041static inline void flush_cond(DisasContext *dc)
83469015
FB		 1042{
1043 if (dc->npc == JUMP_PC) {
2e655fe7 1044 gen_generic_branch(dc);
83469015
FB		 1045 dc->npc = DYNAMIC_PC;
1046 }
1047}
1048
934da7ee 1049static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1050{
1051 if (dc->npc == JUMP_PC) {
2e655fe7 1052 gen_generic_branch(dc);
72cbca10
FB		 1053 dc->npc = DYNAMIC_PC;
1054 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1055 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1056 }
1057}
1058
20132b96 1059static inline void update_psr(DisasContext *dc)
72cbca10 1060{
cfa90513
BS		 1061 if (dc->cc_op != CC_OP_FLAGS) {
1062 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1063 gen_helper_compute_psr(cpu_env);
cfa90513 1064 }
20132b96
RH		 1065}
1066
1067static inline void save_state(DisasContext *dc)
1068{
1069 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1070 save_npc(dc);
72cbca10
FB		 1071}
1072
4fbe0067
RH		 1073static void gen_exception(DisasContext *dc, int which)
1074{
1075 TCGv_i32 t;
1076
1077 save_state(dc);
1078 t = tcg_const_i32(which);
1079 gen_helper_raise_exception(cpu_env, t);
1080 tcg_temp_free_i32(t);
af00be49 1081 dc->base.is_jmp = DISAS_NORETURN;
4fbe0067
RH		 1082}
1083
35e94905
RH		 1084static void gen_check_align(TCGv addr, int mask)
1085{
1086 TCGv_i32 r_mask = tcg_const_i32(mask);
1087 gen_helper_check_align(cpu_env, addr, r_mask);
1088 tcg_temp_free_i32(r_mask);
1089}
1090
13a6dd00 1091static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1092{
1093 if (dc->npc == JUMP_PC) {
2e655fe7 1094 gen_generic_branch(dc);
48d5c82b 1095 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1096 dc->pc = DYNAMIC_PC;
1097 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1098 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1099 dc->pc = DYNAMIC_PC;
1100 } else {
1101 dc->pc = dc->npc;
1102 }
1103}
1104
38bc628b
BS		 1105static inline void gen_op_next_insn(void)
1106{
48d5c82b
BS		 1107 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1108 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1109}
1110
416fcaea
RH		 1111static void free_compare(DisasCompare *cmp)
1112{
1113 if (!cmp->g1) {
1114 tcg_temp_free(cmp->c1);
1115 }
1116 if (!cmp->g2) {
1117 tcg_temp_free(cmp->c2);
1118 }
1119}
1120
2a484ecf 1121static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1122 DisasContext *dc)
19f329ad 1123{
2a484ecf 1124 static int subcc_cond[16] = {
96b5a3d3 1125 TCG_COND_NEVER,
2a484ecf
RH		 1126 TCG_COND_EQ,
1127 TCG_COND_LE,
1128 TCG_COND_LT,
1129 TCG_COND_LEU,
1130 TCG_COND_LTU,
1131 -1, /* neg */
1132 -1, /* overflow */
96b5a3d3 1133 TCG_COND_ALWAYS,
2a484ecf
RH		 1134 TCG_COND_NE,
1135 TCG_COND_GT,
1136 TCG_COND_GE,
1137 TCG_COND_GTU,
1138 TCG_COND_GEU,
1139 -1, /* pos */
1140 -1, /* no overflow */
1141 };
1142
96b5a3d3
RH		 1143 static int logic_cond[16] = {
1144 TCG_COND_NEVER,
1145 TCG_COND_EQ, /* eq: Z */
1146 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1147 TCG_COND_LT, /* lt: N ^ V -> N */
1148 TCG_COND_EQ, /* leu: C | Z -> Z */
1149 TCG_COND_NEVER, /* ltu: C -> 0 */
1150 TCG_COND_LT, /* neg: N */
1151 TCG_COND_NEVER, /* vs: V -> 0 */
1152 TCG_COND_ALWAYS,
1153 TCG_COND_NE, /* ne: !Z */
1154 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1155 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1156 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1157 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1158 TCG_COND_GE, /* pos: !N */
1159 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1160 };
1161
a7812ae4 1162 TCGv_i32 r_src;
416fcaea
RH		 1163 TCGv r_dst;
1164
3475187d 1165#ifdef TARGET_SPARC64
2a484ecf 1166 if (xcc) {
dc99a3f2 1167 r_src = cpu_xcc;
2a484ecf 1168 } else {
dc99a3f2 1169 r_src = cpu_psr;
2a484ecf 1170 }
3475187d 1171#else
dc99a3f2 1172 r_src = cpu_psr;
3475187d 1173#endif
2a484ecf 1174
8393617c 1175 switch (dc->cc_op) {
96b5a3d3
RH		 1176 case CC_OP_LOGIC:
1177 cmp->cond = logic_cond[cond];
1178 do_compare_dst_0:
1179 cmp->is_bool = false;
1180 cmp->g2 = false;
1181 cmp->c2 = tcg_const_tl(0);
1182#ifdef TARGET_SPARC64
1183 if (!xcc) {
1184 cmp->g1 = false;
1185 cmp->c1 = tcg_temp_new();
1186 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1187 break;
1188 }
1189#endif
1190 cmp->g1 = true;
1191 cmp->c1 = cpu_cc_dst;
1192 break;
1193
2a484ecf
RH		 1194 case CC_OP_SUB:
1195 switch (cond) {
1196 case 6: /* neg */
1197 case 14: /* pos */
1198 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1199 goto do_compare_dst_0;
2a484ecf 1200
2a484ecf
RH		 1201 case 7: /* overflow */
1202 case 15: /* !overflow */
1203 goto do_dynamic;
1204
1205 default:
1206 cmp->cond = subcc_cond[cond];
1207 cmp->is_bool = false;
1208#ifdef TARGET_SPARC64
1209 if (!xcc) {
1210 /* Note that sign-extension works for unsigned compares as
1211 long as both operands are sign-extended. */
1212 cmp->g1 = cmp->g2 = false;
1213 cmp->c1 = tcg_temp_new();
1214 cmp->c2 = tcg_temp_new();
1215 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1216 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1217 break;
2a484ecf
RH		 1218 }
1219#endif
1220 cmp->g1 = cmp->g2 = true;
1221 cmp->c1 = cpu_cc_src;
1222 cmp->c2 = cpu_cc_src2;
1223 break;
1224 }
8393617c 1225 break;
2a484ecf 1226
8393617c 1227 default:
2a484ecf 1228 do_dynamic:
2ffd9176 1229 gen_helper_compute_psr(cpu_env);
8393617c 1230 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1231 /* FALLTHRU */
1232
1233 case CC_OP_FLAGS:
1234 /* We're going to generate a boolean result. */
1235 cmp->cond = TCG_COND_NE;
1236 cmp->is_bool = true;
1237 cmp->g1 = cmp->g2 = false;
1238 cmp->c1 = r_dst = tcg_temp_new();
1239 cmp->c2 = tcg_const_tl(0);
1240
1241 switch (cond) {
1242 case 0x0:
1243 gen_op_eval_bn(r_dst);
1244 break;
1245 case 0x1:
1246 gen_op_eval_be(r_dst, r_src);
1247 break;
1248 case 0x2:
1249 gen_op_eval_ble(r_dst, r_src);
1250 break;
1251 case 0x3:
1252 gen_op_eval_bl(r_dst, r_src);
1253 break;
1254 case 0x4:
1255 gen_op_eval_bleu(r_dst, r_src);
1256 break;
1257 case 0x5:
1258 gen_op_eval_bcs(r_dst, r_src);
1259 break;
1260 case 0x6:
1261 gen_op_eval_bneg(r_dst, r_src);
1262 break;
1263 case 0x7:
1264 gen_op_eval_bvs(r_dst, r_src);
1265 break;
1266 case 0x8:
1267 gen_op_eval_ba(r_dst);
1268 break;
1269 case 0x9:
1270 gen_op_eval_bne(r_dst, r_src);
1271 break;
1272 case 0xa:
1273 gen_op_eval_bg(r_dst, r_src);
1274 break;
1275 case 0xb:
1276 gen_op_eval_bge(r_dst, r_src);
1277 break;
1278 case 0xc:
1279 gen_op_eval_bgu(r_dst, r_src);
1280 break;
1281 case 0xd:
1282 gen_op_eval_bcc(r_dst, r_src);
1283 break;
1284 case 0xe:
1285 gen_op_eval_bpos(r_dst, r_src);
1286 break;
1287 case 0xf:
1288 gen_op_eval_bvc(r_dst, r_src);
1289 break;
1290 }
19f329ad
BS		 1291 break;
1292 }
1293}
7a3f1944 1294
416fcaea 1295static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1296{
19f329ad 1297 unsigned int offset;
416fcaea
RH		 1298 TCGv r_dst;
1299
1300 /* For now we still generate a straight boolean result. */
1301 cmp->cond = TCG_COND_NE;
1302 cmp->is_bool = true;
1303 cmp->g1 = cmp->g2 = false;
1304 cmp->c1 = r_dst = tcg_temp_new();
1305 cmp->c2 = tcg_const_tl(0);
19f329ad 1306
19f329ad
BS		 1307 switch (cc) {
1308 default:
1309 case 0x0:
1310 offset = 0;
1311 break;
1312 case 0x1:
1313 offset = 32 - 10;
1314 break;
1315 case 0x2:
1316 offset = 34 - 10;
1317 break;
1318 case 0x3:
1319 offset = 36 - 10;
1320 break;
1321 }
1322
1323 switch (cond) {
1324 case 0x0:
1325 gen_op_eval_bn(r_dst);
1326 break;
1327 case 0x1:
87e92502 1328 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1329 break;
1330 case 0x2:
87e92502 1331 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1332 break;
1333 case 0x3:
87e92502 1334 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1335 break;
1336 case 0x4:
87e92502 1337 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1338 break;
1339 case 0x5:
87e92502 1340 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1341 break;
1342 case 0x6:
87e92502 1343 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1344 break;
1345 case 0x7:
87e92502 1346 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1347 break;
1348 case 0x8:
1349 gen_op_eval_ba(r_dst);
1350 break;
1351 case 0x9:
87e92502 1352 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1353 break;
1354 case 0xa:
87e92502 1355 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1356 break;
1357 case 0xb:
87e92502 1358 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1359 break;
1360 case 0xc:
87e92502 1361 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1362 break;
1363 case 0xd:
87e92502 1364 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1365 break;
1366 case 0xe:
87e92502 1367 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1368 break;
1369 case 0xf:
87e92502 1370 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1371 break;
1372 }
e8af50a3 1373}
00f219bf 1374
416fcaea
RH		 1375static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1376 DisasContext *dc)
1377{
1378 DisasCompare cmp;
1379 gen_compare(&cmp, cc, cond, dc);
1380
1381 /* The interface is to return a boolean in r_dst. */
1382 if (cmp.is_bool) {
1383 tcg_gen_mov_tl(r_dst, cmp.c1);
1384 } else {
1385 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1386 }
1387
1388 free_compare(&cmp);
1389}
1390
1391static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1392{
1393 DisasCompare cmp;
1394 gen_fcompare(&cmp, cc, cond);
1395
1396 /* The interface is to return a boolean in r_dst. */
1397 if (cmp.is_bool) {
1398 tcg_gen_mov_tl(r_dst, cmp.c1);
1399 } else {
1400 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1401 }
1402
1403 free_compare(&cmp);
1404}
1405
19f329ad 1406#ifdef TARGET_SPARC64
00f219bf
BS		 1407// Inverted logic
1408static const int gen_tcg_cond_reg[8] = {
1409 -1,
1410 TCG_COND_NE,
1411 TCG_COND_GT,
1412 TCG_COND_GE,
1413 -1,
1414 TCG_COND_EQ,
1415 TCG_COND_LE,
1416 TCG_COND_LT,
1417};
19f329ad 1418
416fcaea
RH		 1419static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1420{
1421 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1422 cmp->is_bool = false;
1423 cmp->g1 = true;
1424 cmp->g2 = false;
1425 cmp->c1 = r_src;
1426 cmp->c2 = tcg_const_tl(0);
1427}
1428
4af984a7 1429static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1430{
416fcaea
RH		 1431 DisasCompare cmp;
1432 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1433
416fcaea
RH		 1434 /* The interface is to return a boolean in r_dst. */
1435 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1436
1437 free_compare(&cmp);
19f329ad 1438}
3475187d 1439#endif
cf495bcf 1440
d4a288ef 1441static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1442{
cf495bcf 1443 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1444 target_ulong target = dc->pc + offset;
5fafdf24 1445
22036a49
AT		 1446#ifdef TARGET_SPARC64
1447 if (unlikely(AM_CHECK(dc))) {
1448 target &= 0xffffffffULL;
1449 }
1450#endif
cf495bcf 1451 if (cond == 0x0) {
0f8a249a
BS		 1452 /* unconditional not taken */
1453 if (a) {
1454 dc->pc = dc->npc + 4;
1455 dc->npc = dc->pc + 4;
1456 } else {
1457 dc->pc = dc->npc;
1458 dc->npc = dc->pc + 4;
1459 }
cf495bcf 1460 } else if (cond == 0x8) {
0f8a249a
BS		 1461 /* unconditional taken */
1462 if (a) {
1463 dc->pc = target;
1464 dc->npc = dc->pc + 4;
1465 } else {
1466 dc->pc = dc->npc;
1467 dc->npc = target;
c27e2752 1468 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1469 }
cf495bcf 1470 } else {
dee8913c 1471 flush_cond(dc);
d4a288ef 1472 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1473 if (a) {
bfa31b76 1474 gen_branch_a(dc, target);
0f8a249a 1475 } else {
2bf2e019 1476 gen_branch_n(dc, target);
0f8a249a 1477 }
cf495bcf 1478 }
7a3f1944
FB		 1479}
1480
d4a288ef 1481static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1482{
1483 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1484 target_ulong target = dc->pc + offset;
1485
22036a49
AT		 1486#ifdef TARGET_SPARC64
1487 if (unlikely(AM_CHECK(dc))) {
1488 target &= 0xffffffffULL;
1489 }
1490#endif
e8af50a3 1491 if (cond == 0x0) {
0f8a249a
BS		 1492 /* unconditional not taken */
1493 if (a) {
1494 dc->pc = dc->npc + 4;
1495 dc->npc = dc->pc + 4;
1496 } else {
1497 dc->pc = dc->npc;
1498 dc->npc = dc->pc + 4;
1499 }
e8af50a3 1500 } else if (cond == 0x8) {
0f8a249a
BS		 1501 /* unconditional taken */
1502 if (a) {
1503 dc->pc = target;
1504 dc->npc = dc->pc + 4;
1505 } else {
1506 dc->pc = dc->npc;
1507 dc->npc = target;
c27e2752 1508 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1509 }
e8af50a3 1510 } else {
dee8913c 1511 flush_cond(dc);
d4a288ef 1512 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1513 if (a) {
bfa31b76 1514 gen_branch_a(dc, target);
0f8a249a 1515 } else {
2bf2e019 1516 gen_branch_n(dc, target);
0f8a249a 1517 }
e8af50a3
FB		 1518 }
1519}
1520
3475187d 1521#ifdef TARGET_SPARC64
4af984a7 1522static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1523 TCGv r_reg)
7a3f1944 1524{
3475187d
FB		 1525 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1526 target_ulong target = dc->pc + offset;
1527
22036a49
AT		 1528 if (unlikely(AM_CHECK(dc))) {
1529 target &= 0xffffffffULL;
1530 }
dee8913c 1531 flush_cond(dc);
d4a288ef 1532 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1533 if (a) {
bfa31b76 1534 gen_branch_a(dc, target);
3475187d 1535 } else {
2bf2e019 1536 gen_branch_n(dc, target);
3475187d 1537 }
7a3f1944
FB		 1538}
1539
a7812ae4 1540static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1541{
714547bb
BS		 1542 switch (fccno) {
1543 case 0:
7385aed2 1544 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1545 break;
1546 case 1:
7385aed2 1547 gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1548 break;
1549 case 2:
7385aed2 1550 gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1551 break;
1552 case 3:
7385aed2 1553 gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1554 break;
1555 }
7e8c2b6c
BS		 1556}
1557
03fb8cfc 1558static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1559{
a7812ae4
PB		 1560 switch (fccno) {
1561 case 0:
7385aed2 1562 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1563 break;
1564 case 1:
7385aed2 1565 gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1566 break;
1567 case 2:
7385aed2 1568 gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1569 break;
1570 case 3:
7385aed2 1571 gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1572 break;
1573 }
7e8c2b6c
BS		 1574}
1575
7e8c2b6c
BS		 1576static inline void gen_op_fcmpq(int fccno)
1577{
a7812ae4
PB		 1578 switch (fccno) {
1579 case 0:
7385aed2 1580 gen_helper_fcmpq(cpu_fsr, cpu_env);
a7812ae4
PB		 1581 break;
1582 case 1:
7385aed2 1583 gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1584 break;
1585 case 2:
7385aed2 1586 gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1587 break;
1588 case 3:
7385aed2 1589 gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1590 break;
1591 }
7e8c2b6c 1592}
7e8c2b6c 1593
a7812ae4 1594static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1595{
714547bb
BS		 1596 switch (fccno) {
1597 case 0:
7385aed2 1598 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1599 break;
1600 case 1:
7385aed2 1601 gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1602 break;
1603 case 2:
7385aed2 1604 gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1605 break;
1606 case 3:
7385aed2 1607 gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1608 break;
1609 }
7e8c2b6c
BS		 1610}
1611
03fb8cfc 1612static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1613{
a7812ae4
PB		 1614 switch (fccno) {
1615 case 0:
7385aed2 1616 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1617 break;
1618 case 1:
7385aed2 1619 gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1620 break;
1621 case 2:
7385aed2 1622 gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1623 break;
1624 case 3:
7385aed2 1625 gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1626 break;
1627 }
7e8c2b6c
BS		 1628}
1629
7e8c2b6c
BS		 1630static inline void gen_op_fcmpeq(int fccno)
1631{
a7812ae4
PB		 1632 switch (fccno) {
1633 case 0:
7385aed2 1634 gen_helper_fcmpeq(cpu_fsr, cpu_env);
a7812ae4
PB		 1635 break;
1636 case 1:
7385aed2 1637 gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1638 break;
1639 case 2:
7385aed2 1640 gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1641 break;
1642 case 3:
7385aed2 1643 gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1644 break;
1645 }
7e8c2b6c 1646}
7e8c2b6c
BS		 1647
1648#else
1649
714547bb 1650static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1651{
7385aed2 1652 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1653}
1654
03fb8cfc 1655static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1656{
7385aed2 1657 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1658}
1659
7e8c2b6c
BS		 1660static inline void gen_op_fcmpq(int fccno)
1661{
7385aed2 1662 gen_helper_fcmpq(cpu_fsr, cpu_env);
7e8c2b6c 1663}
7e8c2b6c 1664
714547bb 1665static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1666{
7385aed2 1667 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1668}
1669
03fb8cfc 1670static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1671{
7385aed2 1672 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1673}
1674
7e8c2b6c
BS		 1675static inline void gen_op_fcmpeq(int fccno)
1676{
7385aed2 1677 gen_helper_fcmpeq(cpu_fsr, cpu_env);
7e8c2b6c
BS		 1678}
1679#endif
1680
4fbe0067 1681static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1682{
47ad35f1 1683 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1684 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1685 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1686}
1687
5b12f1e8 1688static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1689{
1690#if !defined(CONFIG_USER_ONLY)
1691 if (!dc->fpu_enabled) {
4fbe0067 1692 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1693 return 1;
1694 }
1695#endif
1696 return 0;
1697}
1698
7e8c2b6c
BS		 1699static inline void gen_op_clear_ieee_excp_and_FTT(void)
1700{
47ad35f1 1701 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1702}
1703
61f17f6e
RH		 1704static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1705 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1706{
1707 TCGv_i32 dst, src;
1708
61f17f6e 1709 src = gen_load_fpr_F(dc, rs);
ba5f5179 1710 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1711
1712 gen(dst, cpu_env, src);
7385aed2 1713 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1714
61f17f6e
RH		 1715 gen_store_fpr_F(dc, rd, dst);
1716}
1717
1718static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1719 void (*gen)(TCGv_i32, TCGv_i32))
1720{
1721 TCGv_i32 dst, src;
1722
1723 src = gen_load_fpr_F(dc, rs);
ba5f5179 1724 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1725
1726 gen(dst, src);
1727
1728 gen_store_fpr_F(dc, rd, dst);
1729}
1730
1731static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1732 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1733{
1734 TCGv_i32 dst, src1, src2;
1735
61f17f6e
RH		 1736 src1 = gen_load_fpr_F(dc, rs1);
1737 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1738 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1739
1740 gen(dst, cpu_env, src1, src2);
7385aed2 1741 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1742
61f17f6e
RH		 1743 gen_store_fpr_F(dc, rd, dst);
1744}
1745
1746#ifdef TARGET_SPARC64
1747static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1748 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1749{
1750 TCGv_i32 dst, src1, src2;
1751
1752 src1 = gen_load_fpr_F(dc, rs1);
1753 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1754 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1755
1756 gen(dst, src1, src2);
1757
1758 gen_store_fpr_F(dc, rd, dst);
1759}
1760#endif
1761
1762static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1763 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1764{
1765 TCGv_i64 dst, src;
1766
61f17f6e 1767 src = gen_load_fpr_D(dc, rs);
3886b8a3 1768 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1769
1770 gen(dst, cpu_env, src);
7385aed2 1771 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1772
61f17f6e
RH		 1773 gen_store_fpr_D(dc, rd, dst);
1774}
1775
1776#ifdef TARGET_SPARC64
1777static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1778 void (*gen)(TCGv_i64, TCGv_i64))
1779{
1780 TCGv_i64 dst, src;
1781
1782 src = gen_load_fpr_D(dc, rs);
3886b8a3 1783 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1784
1785 gen(dst, src);
1786
1787 gen_store_fpr_D(dc, rd, dst);
1788}
1789#endif
1790
1791static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1792 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1793{
1794 TCGv_i64 dst, src1, src2;
1795
61f17f6e
RH		 1796 src1 = gen_load_fpr_D(dc, rs1);
1797 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1798 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1799
1800 gen(dst, cpu_env, src1, src2);
7385aed2 1801 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1802
61f17f6e
RH		 1803 gen_store_fpr_D(dc, rd, dst);
1804}
1805
1806#ifdef TARGET_SPARC64
1807static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1808 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1809{
1810 TCGv_i64 dst, src1, src2;
1811
1812 src1 = gen_load_fpr_D(dc, rs1);
1813 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1814 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1815
1816 gen(dst, src1, src2);
1817
1818 gen_store_fpr_D(dc, rd, dst);
1819}
f888300b 1820
2dedf314
RH		 1821static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1822 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1823{
1824 TCGv_i64 dst, src1, src2;
1825
1826 src1 = gen_load_fpr_D(dc, rs1);
1827 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1828 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1829
1830 gen(dst, cpu_gsr, src1, src2);
1831
1832 gen_store_fpr_D(dc, rd, dst);
1833}
1834
f888300b
RH		 1835static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1836 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1837{
1838 TCGv_i64 dst, src0, src1, src2;
1839
1840 src1 = gen_load_fpr_D(dc, rs1);
1841 src2 = gen_load_fpr_D(dc, rs2);
1842 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1843 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1844
1845 gen(dst, src0, src1, src2);
1846
1847 gen_store_fpr_D(dc, rd, dst);
1848}
61f17f6e
RH		 1849#endif
1850
1851static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1852 void (*gen)(TCGv_ptr))
1853{
61f17f6e
RH		 1854 gen_op_load_fpr_QT1(QFPREG(rs));
1855
1856 gen(cpu_env);
7385aed2 1857 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1858
61f17f6e 1859 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1860 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1861}
1862
1863#ifdef TARGET_SPARC64
1864static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1865 void (*gen)(TCGv_ptr))
1866{
1867 gen_op_load_fpr_QT1(QFPREG(rs));
1868
1869 gen(cpu_env);
1870
1871 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1872 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1873}
1874#endif
1875
1876static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1877 void (*gen)(TCGv_ptr))
1878{
61f17f6e
RH		 1879 gen_op_load_fpr_QT0(QFPREG(rs1));
1880 gen_op_load_fpr_QT1(QFPREG(rs2));
1881
1882 gen(cpu_env);
7385aed2 1883 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1884
61f17f6e 1885 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1886 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1887}
1888
1889static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1890 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1891{
1892 TCGv_i64 dst;
1893 TCGv_i32 src1, src2;
1894
61f17f6e
RH		 1895 src1 = gen_load_fpr_F(dc, rs1);
1896 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1897 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1898
1899 gen(dst, cpu_env, src1, src2);
7385aed2 1900 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1901
61f17f6e
RH		 1902 gen_store_fpr_D(dc, rd, dst);
1903}
1904
1905static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1906 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1907{
1908 TCGv_i64 src1, src2;
1909
61f17f6e
RH		 1910 src1 = gen_load_fpr_D(dc, rs1);
1911 src2 = gen_load_fpr_D(dc, rs2);
1912
1913 gen(cpu_env, src1, src2);
7385aed2 1914 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1915
61f17f6e 1916 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1917 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1918}
1919
1920#ifdef TARGET_SPARC64
1921static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1922 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1923{
1924 TCGv_i64 dst;
1925 TCGv_i32 src;
1926
61f17f6e 1927 src = gen_load_fpr_F(dc, rs);
3886b8a3 1928 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1929
1930 gen(dst, cpu_env, src);
7385aed2 1931 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1932
61f17f6e
RH		 1933 gen_store_fpr_D(dc, rd, dst);
1934}
1935#endif
1936
1937static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1938 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1939{
1940 TCGv_i64 dst;
1941 TCGv_i32 src;
1942
1943 src = gen_load_fpr_F(dc, rs);
3886b8a3 1944 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1945
1946 gen(dst, cpu_env, src);
1947
1948 gen_store_fpr_D(dc, rd, dst);
1949}
1950
1951static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1952 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1953{
1954 TCGv_i32 dst;
1955 TCGv_i64 src;
1956
61f17f6e 1957 src = gen_load_fpr_D(dc, rs);
ba5f5179 1958 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1959
1960 gen(dst, cpu_env, src);
7385aed2 1961 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1962
61f17f6e
RH		 1963 gen_store_fpr_F(dc, rd, dst);
1964}
1965
1966static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1967 void (*gen)(TCGv_i32, TCGv_ptr))
1968{
1969 TCGv_i32 dst;
1970
61f17f6e 1971 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1972 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1973
1974 gen(dst, cpu_env);
7385aed2 1975 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1976
61f17f6e
RH		 1977 gen_store_fpr_F(dc, rd, dst);
1978}
1979
1980static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1981 void (*gen)(TCGv_i64, TCGv_ptr))
1982{
1983 TCGv_i64 dst;
1984
61f17f6e 1985 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1986 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1987
1988 gen(dst, cpu_env);
7385aed2 1989 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1990
61f17f6e
RH		 1991 gen_store_fpr_D(dc, rd, dst);
1992}
1993
1994static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1995 void (*gen)(TCGv_ptr, TCGv_i32))
1996{
1997 TCGv_i32 src;
1998
1999 src = gen_load_fpr_F(dc, rs);
2000
2001 gen(cpu_env, src);
2002
2003 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2004 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2005}
2006
2007static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
2008 void (*gen)(TCGv_ptr, TCGv_i64))
2009{
2010 TCGv_i64 src;
2011
2012 src = gen_load_fpr_D(dc, rs);
2013
2014 gen(cpu_env, src);
2015
2016 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2017 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2018}
2019
4fb554bc 2020static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
14776ab5 2021 TCGv addr, int mmu_idx, MemOp memop)
4fb554bc 2022{
4fb554bc 2023 gen_address_mask(dc, addr);
da1bcae6 2024 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
4fb554bc
RH		 2025}
2026
fbb4bbb6
RH		 2027static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
2028{
da1bcae6 2029 TCGv m1 = tcg_const_tl(0xff);
fbb4bbb6 2030 gen_address_mask(dc, addr);
da1bcae6
RH		 2031 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
2032 tcg_temp_free(m1);
fbb4bbb6
RH		 2033}
2034
1a2fb1c0 2035/* asi moves */
22e70060 2036#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
7ec1e5ea
RH		 2037typedef enum {
2038 GET_ASI_HELPER,
2039 GET_ASI_EXCP,
f0913be0 2040 GET_ASI_DIRECT,
e4dc0052 2041 GET_ASI_DTWINX,
ca5ce572
RH		 2042 GET_ASI_BLOCK,
2043 GET_ASI_SHORT,
34810610
RH		 2044 GET_ASI_BCOPY,
2045 GET_ASI_BFILL,
7ec1e5ea
RH		 2046} ASIType;
2047
2048typedef struct {
2049 ASIType type;
a6d567e5 2050 int asi;
f0913be0 2051 int mem_idx;
14776ab5 2052 MemOp memop;
7ec1e5ea 2053} DisasASI;
1a2fb1c0 2054
14776ab5 2055static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
7ec1e5ea
RH		 2056{
2057 int asi = GET_FIELD(insn, 19, 26);
2058 ASIType type = GET_ASI_HELPER;
f0913be0 2059 int mem_idx = dc->mem_idx;
7ec1e5ea
RH		 2060
2061#ifndef TARGET_SPARC64
2062 /* Before v9, all asis are immediate and privileged. */
1a2fb1c0 2063 if (IS_IMM) {
22e70060 2064 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2065 type = GET_ASI_EXCP;
2066 } else if (supervisor(dc)
2067 /* Note that LEON accepts ASI_USERDATA in user mode, for
2068 use with CASA. Also note that previous versions of
0cc1f4bf
RH		 2069 QEMU allowed (and old versions of gcc emitted) ASI_P
2070 for LEON, which is incorrect. */
2071 || (asi == ASI_USERDATA
7ec1e5ea 2072 && (dc->def->features & CPU_FEATURE_CASA))) {
f0913be0
RH		 2073 switch (asi) {
2074 case ASI_USERDATA: /* User data access */
2075 mem_idx = MMU_USER_IDX;
2076 type = GET_ASI_DIRECT;
2077 break;
2078 case ASI_KERNELDATA: /* Supervisor data access */
2079 mem_idx = MMU_KERNEL_IDX;
2080 type = GET_ASI_DIRECT;
2081 break;
7f87c905
RH		 2082 case ASI_M_BYPASS: /* MMU passthrough */
2083 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
2084 mem_idx = MMU_PHYS_IDX;
2085 type = GET_ASI_DIRECT;
2086 break;
34810610
RH		 2087 case ASI_M_BCOPY: /* Block copy, sta access */
2088 mem_idx = MMU_KERNEL_IDX;
2089 type = GET_ASI_BCOPY;
2090 break;
2091 case ASI_M_BFILL: /* Block fill, stda access */
2092 mem_idx = MMU_KERNEL_IDX;
2093 type = GET_ASI_BFILL;
2094 break;
f0913be0 2095 }
6e10f37c
KF		 2096
2097 /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the
2098 * permissions check in get_physical_address(..).
2099 */
2100 mem_idx = (dc->mem_idx == MMU_PHYS_IDX) ? MMU_PHYS_IDX : mem_idx;
1a2fb1c0 2101 } else {
7ec1e5ea
RH		 2102 gen_exception(dc, TT_PRIV_INSN);
2103 type = GET_ASI_EXCP;
2104 }
2105#else
2106 if (IS_IMM) {
2107 asi = dc->asi;
1a2fb1c0 2108 }
f0913be0
RH		 2109 /* With v9, all asis below 0x80 are privileged. */
2110 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
2111 down that bit into DisasContext. For the moment that's ok,
2112 since the direct implementations below doesn't have any ASIs
2113 in the restricted [0x30, 0x7f] range, and the check will be
2114 done properly in the helper. */
2115 if (!supervisor(dc) && asi < 0x80) {
2116 gen_exception(dc, TT_PRIV_ACT);
2117 type = GET_ASI_EXCP;
2118 } else {
2119 switch (asi) {
7f87c905
RH		 2120 case ASI_REAL: /* Bypass */
2121 case ASI_REAL_IO: /* Bypass, non-cacheable */
2122 case ASI_REAL_L: /* Bypass LE */
2123 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2124 case ASI_TWINX_REAL: /* Real address, twinx */
2125 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
34a6e13d
RH		 2126 case ASI_QUAD_LDD_PHYS:
2127 case ASI_QUAD_LDD_PHYS_L:
7f87c905
RH		 2128 mem_idx = MMU_PHYS_IDX;
2129 break;
f0913be0
RH		 2130 case ASI_N: /* Nucleus */
2131 case ASI_NL: /* Nucleus LE */
e4dc0052
RH		 2132 case ASI_TWINX_N:
2133 case ASI_TWINX_NL:
34a6e13d
RH		 2134 case ASI_NUCLEUS_QUAD_LDD:
2135 case ASI_NUCLEUS_QUAD_LDD_L:
9a10756d 2136 if (hypervisor(dc)) {
84f8f587 2137 mem_idx = MMU_PHYS_IDX;
9a10756d
AT		 2138 } else {
2139 mem_idx = MMU_NUCLEUS_IDX;
2140 }
f0913be0
RH		 2141 break;
2142 case ASI_AIUP: /* As if user primary */
2143 case ASI_AIUPL: /* As if user primary LE */
e4dc0052
RH		 2144 case ASI_TWINX_AIUP:
2145 case ASI_TWINX_AIUP_L:
ca5ce572
RH		 2146 case ASI_BLK_AIUP_4V:
2147 case ASI_BLK_AIUP_L_4V:
2148 case ASI_BLK_AIUP:
2149 case ASI_BLK_AIUPL:
f0913be0
RH		 2150 mem_idx = MMU_USER_IDX;
2151 break;
2152 case ASI_AIUS: /* As if user secondary */
2153 case ASI_AIUSL: /* As if user secondary LE */
e4dc0052
RH		 2154 case ASI_TWINX_AIUS:
2155 case ASI_TWINX_AIUS_L:
ca5ce572
RH		 2156 case ASI_BLK_AIUS_4V:
2157 case ASI_BLK_AIUS_L_4V:
2158 case ASI_BLK_AIUS:
2159 case ASI_BLK_AIUSL:
f0913be0
RH		 2160 mem_idx = MMU_USER_SECONDARY_IDX;
2161 break;
2162 case ASI_S: /* Secondary */
2163 case ASI_SL: /* Secondary LE */
e4dc0052
RH		 2164 case ASI_TWINX_S:
2165 case ASI_TWINX_SL:
ca5ce572
RH		 2166 case ASI_BLK_COMMIT_S:
2167 case ASI_BLK_S:
2168 case ASI_BLK_SL:
2169 case ASI_FL8_S:
2170 case ASI_FL8_SL:
2171 case ASI_FL16_S:
2172 case ASI_FL16_SL:
f0913be0
RH		 2173 if (mem_idx == MMU_USER_IDX) {
2174 mem_idx = MMU_USER_SECONDARY_IDX;
2175 } else if (mem_idx == MMU_KERNEL_IDX) {
2176 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2177 }
2178 break;
2179 case ASI_P: /* Primary */
2180 case ASI_PL: /* Primary LE */
e4dc0052
RH		 2181 case ASI_TWINX_P:
2182 case ASI_TWINX_PL:
ca5ce572
RH		 2183 case ASI_BLK_COMMIT_P:
2184 case ASI_BLK_P:
2185 case ASI_BLK_PL:
2186 case ASI_FL8_P:
2187 case ASI_FL8_PL:
2188 case ASI_FL16_P:
2189 case ASI_FL16_PL:
f0913be0
RH		 2190 break;
2191 }
2192 switch (asi) {
7f87c905
RH		 2193 case ASI_REAL:
2194 case ASI_REAL_IO:
2195 case ASI_REAL_L:
2196 case ASI_REAL_IO_L:
f0913be0
RH		 2197 case ASI_N:
2198 case ASI_NL:
2199 case ASI_AIUP:
2200 case ASI_AIUPL:
2201 case ASI_AIUS:
2202 case ASI_AIUSL:
2203 case ASI_S:
2204 case ASI_SL:
2205 case ASI_P:
2206 case ASI_PL:
2207 type = GET_ASI_DIRECT;
2208 break;
7f87c905
RH		 2209 case ASI_TWINX_REAL:
2210 case ASI_TWINX_REAL_L:
e4dc0052
RH		 2211 case ASI_TWINX_N:
2212 case ASI_TWINX_NL:
2213 case ASI_TWINX_AIUP:
2214 case ASI_TWINX_AIUP_L:
2215 case ASI_TWINX_AIUS:
2216 case ASI_TWINX_AIUS_L:
2217 case ASI_TWINX_P:
2218 case ASI_TWINX_PL:
2219 case ASI_TWINX_S:
2220 case ASI_TWINX_SL:
34a6e13d
RH		 2221 case ASI_QUAD_LDD_PHYS:
2222 case ASI_QUAD_LDD_PHYS_L:
2223 case ASI_NUCLEUS_QUAD_LDD:
2224 case ASI_NUCLEUS_QUAD_LDD_L:
e4dc0052
RH		 2225 type = GET_ASI_DTWINX;
2226 break;
ca5ce572
RH		 2227 case ASI_BLK_COMMIT_P:
2228 case ASI_BLK_COMMIT_S:
2229 case ASI_BLK_AIUP_4V:
2230 case ASI_BLK_AIUP_L_4V:
2231 case ASI_BLK_AIUP:
2232 case ASI_BLK_AIUPL:
2233 case ASI_BLK_AIUS_4V:
2234 case ASI_BLK_AIUS_L_4V:
2235 case ASI_BLK_AIUS:
2236 case ASI_BLK_AIUSL:
2237 case ASI_BLK_S:
2238 case ASI_BLK_SL:
2239 case ASI_BLK_P:
2240 case ASI_BLK_PL:
2241 type = GET_ASI_BLOCK;
2242 break;
2243 case ASI_FL8_S:
2244 case ASI_FL8_SL:
2245 case ASI_FL8_P:
2246 case ASI_FL8_PL:
2247 memop = MO_UB;
2248 type = GET_ASI_SHORT;
2249 break;
2250 case ASI_FL16_S:
2251 case ASI_FL16_SL:
2252 case ASI_FL16_P:
2253 case ASI_FL16_PL:
2254 memop = MO_TEUW;
2255 type = GET_ASI_SHORT;
2256 break;
f0913be0
RH		 2257 }
2258 /* The little-endian asis all have bit 3 set. */
2259 if (asi & 8) {
2260 memop ^= MO_BSWAP;
2261 }
2262 }
7ec1e5ea
RH		 2263#endif
2264
f0913be0 2265 return (DisasASI){ type, asi, mem_idx, memop };
0425bee5
BS		 2266}
2267
22e70060 2268static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
14776ab5 2269 int insn, MemOp memop)
0425bee5 2270{
f0913be0 2271 DisasASI da = get_asi(dc, insn, memop);
0425bee5 2272
7ec1e5ea
RH		 2273 switch (da.type) {
2274 case GET_ASI_EXCP:
2275 break;
e4dc0052
RH		 2276 case GET_ASI_DTWINX: /* Reserved for ldda. */
2277 gen_exception(dc, TT_ILL_INSN);
2278 break;
f0913be0
RH		 2279 case GET_ASI_DIRECT:
2280 gen_address_mask(dc, addr);
2281 tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
2282 break;
7ec1e5ea
RH		 2283 default:
2284 {
2285 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2286 TCGv_i32 r_mop = tcg_const_i32(memop);
7ec1e5ea
RH		 2287
2288 save_state(dc);
22e70060 2289#ifdef TARGET_SPARC64
6850811e 2290 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop);
22e70060 2291#else
7ec1e5ea
RH		 2292 {
2293 TCGv_i64 t64 = tcg_temp_new_i64();
6850811e 2294 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
7ec1e5ea
RH		 2295 tcg_gen_trunc_i64_tl(dst, t64);
2296 tcg_temp_free_i64(t64);
2297 }
22e70060 2298#endif
6850811e 2299 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2300 tcg_temp_free_i32(r_asi);
2301 }
2302 break;
2303 }
1a2fb1c0
BS		 2304}
2305
22e70060 2306static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
14776ab5 2307 int insn, MemOp memop)
1a2fb1c0 2308{
f0913be0 2309 DisasASI da = get_asi(dc, insn, memop);
1a2fb1c0 2310
7ec1e5ea
RH		 2311 switch (da.type) {
2312 case GET_ASI_EXCP:
2313 break;
e4dc0052 2314 case GET_ASI_DTWINX: /* Reserved for stda. */
3390537b 2315#ifndef TARGET_SPARC64
e4dc0052
RH		 2316 gen_exception(dc, TT_ILL_INSN);
2317 break;
3390537b
AT		 2318#else
2319 if (!(dc->def->features & CPU_FEATURE_HYPV)) {
2320 /* Pre OpenSPARC CPUs don't have these */
2321 gen_exception(dc, TT_ILL_INSN);
2322 return;
2323 }
2324 /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
2325 * are ST_BLKINIT_ ASIs */
3390537b 2326#endif
fc0cd867 2327 /* fall through */
f0913be0
RH		 2328 case GET_ASI_DIRECT:
2329 gen_address_mask(dc, addr);
2330 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
2331 break;
34810610
RH		 2332#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
2333 case GET_ASI_BCOPY:
2334 /* Copy 32 bytes from the address in SRC to ADDR. */
2335 /* ??? The original qemu code suggests 4-byte alignment, dropping
2336 the low bits, but the only place I can see this used is in the
2337 Linux kernel with 32 byte alignment, which would make more sense
2338 as a cacheline-style operation. */
2339 {
2340 TCGv saddr = tcg_temp_new();
2341 TCGv daddr = tcg_temp_new();
2342 TCGv four = tcg_const_tl(4);
2343 TCGv_i32 tmp = tcg_temp_new_i32();
2344 int i;
2345
2346 tcg_gen_andi_tl(saddr, src, -4);
2347 tcg_gen_andi_tl(daddr, addr, -4);
2348 for (i = 0; i < 32; i += 4) {
2349 /* Since the loads and stores are paired, allow the
2350 copy to happen in the host endianness. */
2351 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
2352 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
2353 tcg_gen_add_tl(saddr, saddr, four);
2354 tcg_gen_add_tl(daddr, daddr, four);
2355 }
2356
2357 tcg_temp_free(saddr);
2358 tcg_temp_free(daddr);
2359 tcg_temp_free(four);
2360 tcg_temp_free_i32(tmp);
2361 }
2362 break;
2363#endif
7ec1e5ea
RH		 2364 default:
2365 {
2366 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2367 TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE);
7ec1e5ea
RH		 2368
2369 save_state(dc);
22e70060 2370#ifdef TARGET_SPARC64
6850811e 2371 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop);
22e70060 2372#else
7ec1e5ea
RH		 2373 {
2374 TCGv_i64 t64 = tcg_temp_new_i64();
2375 tcg_gen_extu_tl_i64(t64, src);
6850811e 2376 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
7ec1e5ea
RH		 2377 tcg_temp_free_i64(t64);
2378 }
22e70060 2379#endif
6850811e 2380 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2381 tcg_temp_free_i32(r_asi);
2382
2383 /* A write to a TLB register may alter page maps. End the TB. */
2384 dc->npc = DYNAMIC_PC;
2385 }
2386 break;
2387 }
1a2fb1c0
BS		 2388}
2389
22e70060
RH		 2390static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2391 TCGv addr, int insn)
1a2fb1c0 2392{
f0913be0 2393 DisasASI da = get_asi(dc, insn, MO_TEUL);
22e70060 2394
7ec1e5ea
RH		 2395 switch (da.type) {
2396 case GET_ASI_EXCP:
2397 break;
4fb554bc
RH		 2398 case GET_ASI_DIRECT:
2399 gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
2400 break;
7ec1e5ea 2401 default:
4fb554bc
RH		 2402 /* ??? Should be DAE_invalid_asi. */
2403 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2404 break;
2405 }
1a2fb1c0
BS		 2406}
2407
5a7267b6 2408static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060
RH		 2409 int insn, int rd)
2410{
f0913be0 2411 DisasASI da = get_asi(dc, insn, MO_TEUL);
5a7267b6 2412 TCGv oldv;
22e70060 2413
7268adeb
RH		 2414 switch (da.type) {
2415 case GET_ASI_EXCP:
7ec1e5ea 2416 return;
7268adeb 2417 case GET_ASI_DIRECT:
7268adeb 2418 oldv = tcg_temp_new();
5a7267b6
RH		 2419 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2420 da.mem_idx, da.memop);
7268adeb 2421 gen_store_gpr(dc, rd, oldv);
7268adeb 2422 tcg_temp_free(oldv);
7268adeb
RH		 2423 break;
2424 default:
2425 /* ??? Should be DAE_invalid_asi. */
2426 gen_exception(dc, TT_DATA_ACCESS);
2427 break;
7ec1e5ea 2428 }
22e70060
RH		 2429}
2430
2431static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2432{
f0913be0 2433 DisasASI da = get_asi(dc, insn, MO_UB);
22e70060 2434
7ec1e5ea
RH		 2435 switch (da.type) {
2436 case GET_ASI_EXCP:
2437 break;
fbb4bbb6
RH		 2438 case GET_ASI_DIRECT:
2439 gen_ldstub(dc, dst, addr, da.mem_idx);
2440 break;
7ec1e5ea 2441 default:
3db010c3
RH		 2442 /* ??? In theory, this should be raise DAE_invalid_asi.
2443 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
af00be49 2444 if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
3db010c3
RH		 2445 gen_helper_exit_atomic(cpu_env);
2446 } else {
2447 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2448 TCGv_i32 r_mop = tcg_const_i32(MO_UB);
2449 TCGv_i64 s64, t64;
2450
2451 save_state(dc);
2452 t64 = tcg_temp_new_i64();
2453 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2454
2455 s64 = tcg_const_i64(0xff);
2456 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop);
2457 tcg_temp_free_i64(s64);
2458 tcg_temp_free_i32(r_mop);
2459 tcg_temp_free_i32(r_asi);
2460
2461 tcg_gen_trunc_i64_tl(dst, t64);
2462 tcg_temp_free_i64(t64);
2463
2464 /* End the TB. */
2465 dc->npc = DYNAMIC_PC;
2466 }
7ec1e5ea
RH		 2467 break;
2468 }
22e70060
RH		 2469}
2470#endif
2471
2472#ifdef TARGET_SPARC64
2473static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2474 int insn, int size, int rd)
1a2fb1c0 2475{
f0913be0 2476 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2477 TCGv_i32 d32;
cb21b4da 2478 TCGv_i64 d64;
1a2fb1c0 2479
7ec1e5ea
RH		 2480 switch (da.type) {
2481 case GET_ASI_EXCP:
2482 break;
7705091c
RH		 2483
2484 case GET_ASI_DIRECT:
2485 gen_address_mask(dc, addr);
2486 switch (size) {
2487 case 4:
2488 d32 = gen_dest_fpr_F(dc);
2489 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
2490 gen_store_fpr_F(dc, rd, d32);
2491 break;
2492 case 8:
cb21b4da
RH		 2493 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2494 da.memop | MO_ALIGN_4);
7705091c
RH		 2495 break;
2496 case 16:
cb21b4da
RH		 2497 d64 = tcg_temp_new_i64();
2498 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
7705091c 2499 tcg_gen_addi_tl(addr, addr, 8);
cb21b4da
RH		 2500 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2501 da.memop | MO_ALIGN_4);
2502 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2503 tcg_temp_free_i64(d64);
7705091c
RH		 2504 break;
2505 default:
2506 g_assert_not_reached();
2507 }
2508 break;
2509
ca5ce572
RH		 2510 case GET_ASI_BLOCK:
2511 /* Valid for lddfa on aligned registers only. */
2512 if (size == 8 && (rd & 7) == 0) {
14776ab5 2513 MemOp memop;
ca5ce572
RH		 2514 TCGv eight;
2515 int i;
2516
ca5ce572
RH		 2517 gen_address_mask(dc, addr);
2518
80883227
RH		 2519 /* The first operation checks required alignment. */
2520 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2521 eight = tcg_const_tl(8);
2522 for (i = 0; ; ++i) {
2523 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2524 da.mem_idx, memop);
ca5ce572
RH		 2525 if (i == 7) {
2526 break;
2527 }
2528 tcg_gen_add_tl(addr, addr, eight);
80883227 2529 memop = da.memop;
ca5ce572
RH		 2530 }
2531 tcg_temp_free(eight);
2532 } else {
2533 gen_exception(dc, TT_ILL_INSN);
2534 }
2535 break;
2536
2537 case GET_ASI_SHORT:
2538 /* Valid for lddfa only. */
2539 if (size == 8) {
2540 gen_address_mask(dc, addr);
2541 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2542 } else {
2543 gen_exception(dc, TT_ILL_INSN);
2544 }
2545 break;
2546
7ec1e5ea
RH		 2547 default:
2548 {
2549 TCGv_i32 r_asi = tcg_const_i32(da.asi);
f2fe396f 2550 TCGv_i32 r_mop = tcg_const_i32(da.memop);
7ec1e5ea
RH		 2551
2552 save_state(dc);
f2fe396f
RH		 2553 /* According to the table in the UA2011 manual, the only
2554 other asis that are valid for ldfa/lddfa/ldqfa are
2555 the NO_FAULT asis. We still need a helper for these,
2556 but we can just use the integer asi helper for them. */
2557 switch (size) {
2558 case 4:
cb21b4da
RH		 2559 d64 = tcg_temp_new_i64();
2560 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
2561 d32 = gen_dest_fpr_F(dc);
2562 tcg_gen_extrl_i64_i32(d32, d64);
2563 tcg_temp_free_i64(d64);
2564 gen_store_fpr_F(dc, rd, d32);
f2fe396f
RH		 2565 break;
2566 case 8:
2567 gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop);
2568 break;
2569 case 16:
cb21b4da
RH		 2570 d64 = tcg_temp_new_i64();
2571 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
f2fe396f
RH		 2572 tcg_gen_addi_tl(addr, addr, 8);
2573 gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop);
cb21b4da
RH		 2574 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2575 tcg_temp_free_i64(d64);
f2fe396f
RH		 2576 break;
2577 default:
2578 g_assert_not_reached();
2579 }
2580 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2581 tcg_temp_free_i32(r_asi);
2582 }
2583 break;
2584 }
1a2fb1c0
BS		 2585}
2586
22e70060
RH		 2587static void gen_stf_asi(DisasContext *dc, TCGv addr,
2588 int insn, int size, int rd)
1a2fb1c0 2589{
f0913be0 2590 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2591 TCGv_i32 d32;
1a2fb1c0 2592
7ec1e5ea
RH		 2593 switch (da.type) {
2594 case GET_ASI_EXCP:
2595 break;
7705091c
RH		 2596
2597 case GET_ASI_DIRECT:
2598 gen_address_mask(dc, addr);
2599 switch (size) {
2600 case 4:
2601 d32 = gen_load_fpr_F(dc, rd);
2602 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
2603 break;
2604 case 8:
cb21b4da
RH		 2605 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2606 da.memop | MO_ALIGN_4);
7705091c
RH		 2607 break;
2608 case 16:
cb21b4da
RH		 2609 /* Only 4-byte alignment required. However, it is legal for the
2610 cpu to signal the alignment fault, and the OS trap handler is
2611 required to fix it up. Requiring 16-byte alignment here avoids
2612 having to probe the second page before performing the first
2613 write. */
f939ffe5
RH		 2614 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2615 da.memop | MO_ALIGN_16);
7705091c
RH		 2616 tcg_gen_addi_tl(addr, addr, 8);
2617 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2618 break;
2619 default:
2620 g_assert_not_reached();
2621 }
2622 break;
2623
ca5ce572
RH		 2624 case GET_ASI_BLOCK:
2625 /* Valid for stdfa on aligned registers only. */
2626 if (size == 8 && (rd & 7) == 0) {
14776ab5 2627 MemOp memop;
ca5ce572
RH		 2628 TCGv eight;
2629 int i;
2630
ca5ce572
RH		 2631 gen_address_mask(dc, addr);
2632
80883227
RH		 2633 /* The first operation checks required alignment. */
2634 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2635 eight = tcg_const_tl(8);
2636 for (i = 0; ; ++i) {
2637 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2638 da.mem_idx, memop);
ca5ce572
RH		 2639 if (i == 7) {
2640 break;
2641 }
2642 tcg_gen_add_tl(addr, addr, eight);
80883227 2643 memop = da.memop;
ca5ce572
RH		 2644 }
2645 tcg_temp_free(eight);
2646 } else {
2647 gen_exception(dc, TT_ILL_INSN);
2648 }
2649 break;
2650
2651 case GET_ASI_SHORT:
2652 /* Valid for stdfa only. */
2653 if (size == 8) {
2654 gen_address_mask(dc, addr);
2655 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2656 } else {
2657 gen_exception(dc, TT_ILL_INSN);
2658 }
2659 break;
2660
7ec1e5ea 2661 default:
f2fe396f
RH		 2662 /* According to the table in the UA2011 manual, the only
2663 other asis that are valid for ldfa/lddfa/ldqfa are
2664 the PST* asis, which aren't currently handled. */
2665 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2666 break;
2667 }
1a2fb1c0
BS		 2668}
2669
e4dc0052 2670static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2671{
f0913be0 2672 DisasASI da = get_asi(dc, insn, MO_TEQ);
e4dc0052
RH		 2673 TCGv_i64 hi = gen_dest_gpr(dc, rd);
2674 TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
1a2fb1c0 2675
7ec1e5ea
RH		 2676 switch (da.type) {
2677 case GET_ASI_EXCP:
e4dc0052
RH		 2678 return;
2679
2680 case GET_ASI_DTWINX:
e4dc0052 2681 gen_address_mask(dc, addr);
80883227 2682 tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2683 tcg_gen_addi_tl(addr, addr, 8);
2684 tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
7ec1e5ea 2685 break;
e4dc0052
RH		 2686
2687 case GET_ASI_DIRECT:
2688 {
2689 TCGv_i64 tmp = tcg_temp_new_i64();
2690
2691 gen_address_mask(dc, addr);
2692 tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
2693
2694 /* Note that LE ldda acts as if each 32-bit register
2695 result is byte swapped. Having just performed one
2696 64-bit bswap, we need now to swap the writebacks. */
2697 if ((da.memop & MO_BSWAP) == MO_TE) {
2698 tcg_gen_extr32_i64(lo, hi, tmp);
2699 } else {
2700 tcg_gen_extr32_i64(hi, lo, tmp);
2701 }
2702 tcg_temp_free_i64(tmp);
2703 }
2704 break;
2705
7ec1e5ea 2706 default:
918d9a2c
RH		 2707 /* ??? In theory we've handled all of the ASIs that are valid
2708 for ldda, and this should raise DAE_invalid_asi. However,
2709 real hardware allows others. This can be seen with e.g.
2710 FreeBSD 10.3 wrt ASI_IC_TAG. */
7ec1e5ea
RH		 2711 {
2712 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2713 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2714 TCGv_i64 tmp = tcg_temp_new_i64();
7ec1e5ea
RH		 2715
2716 save_state(dc);
918d9a2c 2717 gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop);
7ec1e5ea 2718 tcg_temp_free_i32(r_asi);
918d9a2c 2719 tcg_temp_free_i32(r_mop);
3f4288eb 2720
918d9a2c
RH		 2721 /* See above. */
2722 if ((da.memop & MO_BSWAP) == MO_TE) {
2723 tcg_gen_extr32_i64(lo, hi, tmp);
2724 } else {
2725 tcg_gen_extr32_i64(hi, lo, tmp);
2726 }
2727 tcg_temp_free_i64(tmp);
7ec1e5ea
RH		 2728 }
2729 break;
2730 }
e4dc0052
RH		 2731
2732 gen_store_gpr(dc, rd, hi);
2733 gen_store_gpr(dc, rd + 1, lo);
0425bee5
BS		 2734}
2735
22e70060
RH		 2736static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2737 int insn, int rd)
0425bee5 2738{
f0913be0 2739 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2740 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2741
7ec1e5ea
RH		 2742 switch (da.type) {
2743 case GET_ASI_EXCP:
2744 break;
e4dc0052
RH		 2745
2746 case GET_ASI_DTWINX:
e4dc0052 2747 gen_address_mask(dc, addr);
80883227 2748 tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2749 tcg_gen_addi_tl(addr, addr, 8);
2750 tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
2751 break;
2752
2753 case GET_ASI_DIRECT:
2754 {
2755 TCGv_i64 t64 = tcg_temp_new_i64();
2756
2757 /* Note that LE stda acts as if each 32-bit register result is
2758 byte swapped. We will perform one 64-bit LE store, so now
2759 we must swap the order of the construction. */
2760 if ((da.memop & MO_BSWAP) == MO_TE) {
2761 tcg_gen_concat32_i64(t64, lo, hi);
2762 } else {
2763 tcg_gen_concat32_i64(t64, hi, lo);
2764 }
2765 gen_address_mask(dc, addr);
2766 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2767 tcg_temp_free_i64(t64);
2768 }
2769 break;
2770
7ec1e5ea 2771 default:
918d9a2c
RH		 2772 /* ??? In theory we've handled all of the ASIs that are valid
2773 for stda, and this should raise DAE_invalid_asi. */
7ec1e5ea
RH		 2774 {
2775 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2776 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2777 TCGv_i64 t64 = tcg_temp_new_i64();
7ec1e5ea 2778
918d9a2c
RH		 2779 /* See above. */
2780 if ((da.memop & MO_BSWAP) == MO_TE) {
2781 tcg_gen_concat32_i64(t64, lo, hi);
2782 } else {
2783 tcg_gen_concat32_i64(t64, hi, lo);
2784 }
7ec1e5ea 2785
918d9a2c 2786 save_state(dc);
6850811e
RH		 2787 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2788 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2789 tcg_temp_free_i32(r_asi);
2790 tcg_temp_free_i64(t64);
2791 }
2792 break;
2793 }
1a2fb1c0
BS		 2794}
2795
7268adeb 2796static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060 2797 int insn, int rd)
1a2fb1c0 2798{
f0913be0 2799 DisasASI da = get_asi(dc, insn, MO_TEQ);
5a7267b6 2800 TCGv oldv;
1a2fb1c0 2801
7268adeb
RH		 2802 switch (da.type) {
2803 case GET_ASI_EXCP:
7ec1e5ea 2804 return;
7268adeb
RH		 2805 case GET_ASI_DIRECT:
2806 oldv = tcg_temp_new();
5a7267b6
RH		 2807 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2808 da.mem_idx, da.memop);
7268adeb
RH		 2809 gen_store_gpr(dc, rd, oldv);
2810 tcg_temp_free(oldv);
7268adeb
RH		 2811 break;
2812 default:
2813 /* ??? Should be DAE_invalid_asi. */
2814 gen_exception(dc, TT_DATA_ACCESS);
2815 break;
2816 }
1a2fb1c0
BS		 2817}
2818
2819#elif !defined(CONFIG_USER_ONLY)
e4dc0052 2820static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2821{
d2dc4069
RH		 2822 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2823 whereby "rd + 1" elicits "error: array subscript is above array".
2824 Since we have already asserted that rd is even, the semantics
2825 are unchanged. */
7ec1e5ea 2826 TCGv lo = gen_dest_gpr(dc, rd | 1);
e4dc0052 2827 TCGv hi = gen_dest_gpr(dc, rd);
7ec1e5ea 2828 TCGv_i64 t64 = tcg_temp_new_i64();
f0913be0 2829 DisasASI da = get_asi(dc, insn, MO_TEQ);
7ec1e5ea
RH		 2830
2831 switch (da.type) {
2832 case GET_ASI_EXCP:
2833 tcg_temp_free_i64(t64);
2834 return;
e4dc0052
RH		 2835 case GET_ASI_DIRECT:
2836 gen_address_mask(dc, addr);
2837 tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
2838 break;
7ec1e5ea
RH		 2839 default:
2840 {
2841 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2842 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2843
2844 save_state(dc);
6850811e
RH		 2845 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2846 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2847 tcg_temp_free_i32(r_asi);
2848 }
2849 break;
2850 }
c7785e16 2851
7ec1e5ea 2852 tcg_gen_extr_i64_i32(lo, hi, t64);
1ec789ab 2853 tcg_temp_free_i64(t64);
7ec1e5ea 2854 gen_store_gpr(dc, rd | 1, lo);
c7785e16 2855 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2856}
2857
22e70060
RH		 2858static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2859 int insn, int rd)
0425bee5 2860{
f0913be0 2861 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2862 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2863 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2864
1ec789ab 2865 tcg_gen_concat_tl_i64(t64, lo, hi);
7ec1e5ea
RH		 2866
2867 switch (da.type) {
2868 case GET_ASI_EXCP:
2869 break;
e4dc0052
RH		 2870 case GET_ASI_DIRECT:
2871 gen_address_mask(dc, addr);
2872 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2873 break;
34810610
RH		 2874 case GET_ASI_BFILL:
2875 /* Store 32 bytes of T64 to ADDR. */
2876 /* ??? The original qemu code suggests 8-byte alignment, dropping
2877 the low bits, but the only place I can see this used is in the
2878 Linux kernel with 32 byte alignment, which would make more sense
2879 as a cacheline-style operation. */
2880 {
2881 TCGv d_addr = tcg_temp_new();
2882 TCGv eight = tcg_const_tl(8);
2883 int i;
2884
2885 tcg_gen_andi_tl(d_addr, addr, -8);
2886 for (i = 0; i < 32; i += 8) {
2887 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
2888 tcg_gen_add_tl(d_addr, d_addr, eight);
2889 }
2890
2891 tcg_temp_free(d_addr);
2892 tcg_temp_free(eight);
2893 }
2894 break;
7ec1e5ea
RH		 2895 default:
2896 {
2897 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2898 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2899
2900 save_state(dc);
6850811e
RH		 2901 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2902 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2903 tcg_temp_free_i32(r_asi);
2904 }
2905 break;
2906 }
2907
1ec789ab 2908 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2909}
2910#endif
2911
9d1d4e34 2912static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2913{
9d1d4e34
RH		 2914 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2915 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2916}
2917
9d1d4e34 2918static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2919{
a49d9390 2920 if (IS_IMM) { /* immediate */
42a8aa83 2921 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2922 TCGv t = get_temp_tl(dc);
2923 tcg_gen_movi_tl(t, simm);
2924 return t;
2925 } else { /* register */
42a8aa83 2926 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2927 return gen_load_gpr(dc, rs2);
a49d9390 2928 }
a49d9390
BS		 2929}
2930
8194f35a 2931#ifdef TARGET_SPARC64
7e480893
RH		 2932static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2933{
2934 TCGv_i32 c32, zero, dst, s1, s2;
2935
2936 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2937 or fold the comparison down to 32 bits and use movcond_i32. Choose
2938 the later. */
2939 c32 = tcg_temp_new_i32();
2940 if (cmp->is_bool) {
ecc7b3aa 2941 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2942 } else {
2943 TCGv_i64 c64 = tcg_temp_new_i64();
2944 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2945 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2946 tcg_temp_free_i64(c64);
2947 }
2948
2949 s1 = gen_load_fpr_F(dc, rs);
2950 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2951 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2952 zero = tcg_const_i32(0);
2953
2954 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2955
2956 tcg_temp_free_i32(c32);
2957 tcg_temp_free_i32(zero);
2958 gen_store_fpr_F(dc, rd, dst);
2959}
2960
2961static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2962{
3886b8a3 2963 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2964 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2965 gen_load_fpr_D(dc, rs),
2966 gen_load_fpr_D(dc, rd));
2967 gen_store_fpr_D(dc, rd, dst);
2968}
2969
2970static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2971{
2972 int qd = QFPREG(rd);
2973 int qs = QFPREG(rs);
2974
2975 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2976 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2977 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2978 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2979
f9c816c0 2980 gen_update_fprs_dirty(dc, qd);
7e480893
RH		 2981}
2982
a2035e83 2983#ifndef CONFIG_USER_ONLY
1bcea73e 2984static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
8194f35a 2985{
b551ec04 2986 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2987
2988 /* load env->tl into r_tl */
b551ec04 2989 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2990
2991 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2992 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2993
2994 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2995 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2996 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2997
2998 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2999 {
3000 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
3001 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
3002 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 3003 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 3004 }
8194f35a 3005
b551ec04 3006 tcg_temp_free_i32(r_tl);
8194f35a 3007}
a2035e83 3008#endif
6c073553
RH		 3009
3010static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
3011 int width, bool cc, bool left)
3012{
3013 TCGv lo1, lo2, t1, t2;
3014 uint64_t amask, tabl, tabr;
3015 int shift, imask, omask;
3016
3017 if (cc) {
3018 tcg_gen_mov_tl(cpu_cc_src, s1);
3019 tcg_gen_mov_tl(cpu_cc_src2, s2);
3020 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
3021 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3022 dc->cc_op = CC_OP_SUB;
3023 }
3024
3025 /* Theory of operation: there are two tables, left and right (not to
3026 be confused with the left and right versions of the opcode). These
3027 are indexed by the low 3 bits of the inputs. To make things "easy",
3028 these tables are loaded into two constants, TABL and TABR below.
3029 The operation index = (input & imask) << shift calculates the index
3030 into the constant, while val = (table >> index) & omask calculates
3031 the value we're looking for. */
3032 switch (width) {
3033 case 8:
3034 imask = 0x7;
3035 shift = 3;
3036 omask = 0xff;
3037 if (left) {
3038 tabl = 0x80c0e0f0f8fcfeffULL;
3039 tabr = 0xff7f3f1f0f070301ULL;
3040 } else {
3041 tabl = 0x0103070f1f3f7fffULL;
3042 tabr = 0xfffefcf8f0e0c080ULL;
3043 }
3044 break;
3045 case 16:
3046 imask = 0x6;
3047 shift = 1;
3048 omask = 0xf;
3049 if (left) {
3050 tabl = 0x8cef;
3051 tabr = 0xf731;
3052 } else {
3053 tabl = 0x137f;
3054 tabr = 0xfec8;
3055 }
3056 break;
3057 case 32:
3058 imask = 0x4;
3059 shift = 0;
3060 omask = 0x3;
3061 if (left) {
3062 tabl = (2 << 2) | 3;
3063 tabr = (3 << 2) | 1;
3064 } else {
3065 tabl = (1 << 2) | 3;
3066 tabr = (3 << 2) | 2;
3067 }
3068 break;
3069 default:
3070 abort();
3071 }
3072
3073 lo1 = tcg_temp_new();
3074 lo2 = tcg_temp_new();
3075 tcg_gen_andi_tl(lo1, s1, imask);
3076 tcg_gen_andi_tl(lo2, s2, imask);
3077 tcg_gen_shli_tl(lo1, lo1, shift);
3078 tcg_gen_shli_tl(lo2, lo2, shift);
3079
3080 t1 = tcg_const_tl(tabl);
3081 t2 = tcg_const_tl(tabr);
3082 tcg_gen_shr_tl(lo1, t1, lo1);
3083 tcg_gen_shr_tl(lo2, t2, lo2);
3084 tcg_gen_andi_tl(dst, lo1, omask);
3085 tcg_gen_andi_tl(lo2, lo2, omask);
3086
3087 amask = -8;
3088 if (AM_CHECK(dc)) {
3089 amask &= 0xffffffffULL;
3090 }
3091 tcg_gen_andi_tl(s1, s1, amask);
3092 tcg_gen_andi_tl(s2, s2, amask);
3093
3094 /* We want to compute
3095 dst = (s1 == s2 ? lo1 : lo1 & lo2).
3096 We've already done dst = lo1, so this reduces to
3097 dst &= (s1 == s2 ? -1 : lo2)
3098 Which we perform by
3099 lo2 |= -(s1 == s2)
3100 dst &= lo2
3101 */
3102 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
3103 tcg_gen_neg_tl(t1, t1);
3104 tcg_gen_or_tl(lo2, lo2, t1);
3105 tcg_gen_and_tl(dst, dst, lo2);
3106
3107 tcg_temp_free(lo1);
3108 tcg_temp_free(lo2);
3109 tcg_temp_free(t1);
3110 tcg_temp_free(t2);
3111}
add545ab
RH		 3112
3113static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
3114{
3115 TCGv tmp = tcg_temp_new();
3116
3117 tcg_gen_add_tl(tmp, s1, s2);
3118 tcg_gen_andi_tl(dst, tmp, -8);
3119 if (left) {
3120 tcg_gen_neg_tl(tmp, tmp);
3121 }
3122 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
3123
3124 tcg_temp_free(tmp);
3125}
50c796f9
RH		 3126
3127static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
3128{
3129 TCGv t1, t2, shift;
3130
3131 t1 = tcg_temp_new();
3132 t2 = tcg_temp_new();
3133 shift = tcg_temp_new();
3134
3135 tcg_gen_andi_tl(shift, gsr, 7);
3136 tcg_gen_shli_tl(shift, shift, 3);
3137 tcg_gen_shl_tl(t1, s1, shift);
3138
3139 /* A shift of 64 does not produce 0 in TCG. Divide this into a
3140 shift of (up to 63) followed by a constant shift of 1. */
3141 tcg_gen_xori_tl(shift, shift, 63);
3142 tcg_gen_shr_tl(t2, s2, shift);
3143 tcg_gen_shri_tl(t2, t2, 1);
3144
3145 tcg_gen_or_tl(dst, t1, t2);
3146
3147 tcg_temp_free(t1);
3148 tcg_temp_free(t2);
3149 tcg_temp_free(shift);
3150}
8194f35a
IK		 3151#endif
3152
64a88d5d 3153#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 3154 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3155 goto illegal_insn;
3156#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 3157 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3158 goto nfpu_insn;
3159
0bee699e 3160/* before an instruction, dc->pc must be static */
0184e266 3161static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 3162{
0184e266 3163 unsigned int opc, rs1, rs2, rd;
a4273524 3164 TCGv cpu_src1, cpu_src2;
208ae657 3165 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 3166 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 3167 target_long simm;
7a3f1944 3168
cf495bcf 3169 opc = GET_FIELD(insn, 0, 1);
cf495bcf 3170 rd = GET_FIELD(insn, 2, 6);
6ae20372 3171
cf495bcf 3172 switch (opc) {
0f8a249a
BS		 3173 case 0: /* branches/sethi */
3174 {
3175 unsigned int xop = GET_FIELD(insn, 7, 9);
3176 int32_t target;
3177 switch (xop) {
3475187d 3178#ifdef TARGET_SPARC64
0f8a249a
BS		 3179 case 0x1: /* V9 BPcc */
3180 {
3181 int cc;
3182
3183 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 3184 target = sign_extend(target, 19);
0f8a249a
BS		 3185 target <<= 2;
3186 cc = GET_FIELD_SP(insn, 20, 21);
3187 if (cc == 0)
d4a288ef 3188 do_branch(dc, target, insn, 0);
0f8a249a 3189 else if (cc == 2)
d4a288ef 3190 do_branch(dc, target, insn, 1);
0f8a249a
BS		 3191 else
3192 goto illegal_insn;
3193 goto jmp_insn;
3194 }
3195 case 0x3: /* V9 BPr */
3196 {
3197 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 3198 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 3199 target = sign_extend(target, 16);
3200 target <<= 2;
9d1d4e34 3201 cpu_src1 = get_src1(dc, insn);
d4a288ef 3202 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 3203 goto jmp_insn;
3204 }
3205 case 0x5: /* V9 FBPcc */
3206 {
3207 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 3208 if (gen_trap_ifnofpu(dc)) {
a80dde08 3209 goto jmp_insn;
5b12f1e8 3210 }
0f8a249a
BS		 3211 target = GET_FIELD_SP(insn, 0, 18);
3212 target = sign_extend(target, 19);
3213 target <<= 2;
d4a288ef 3214 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 3215 goto jmp_insn;
3216 }
a4d17f19 3217#else
0f8a249a
BS		 3218 case 0x7: /* CBN+x */
3219 {
3220 goto ncp_insn;
3221 }
3222#endif
3223 case 0x2: /* BN+x */
3224 {
3225 target = GET_FIELD(insn, 10, 31);
3226 target = sign_extend(target, 22);
3227 target <<= 2;
d4a288ef 3228 do_branch(dc, target, insn, 0);
0f8a249a
BS		 3229 goto jmp_insn;
3230 }
3231 case 0x6: /* FBN+x */
3232 {
5b12f1e8 3233 if (gen_trap_ifnofpu(dc)) {
a80dde08 3234 goto jmp_insn;
5b12f1e8 3235 }
0f8a249a
BS		 3236 target = GET_FIELD(insn, 10, 31);
3237 target = sign_extend(target, 22);
3238 target <<= 2;
d4a288ef 3239 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 3240 goto jmp_insn;
3241 }
3242 case 0x4: /* SETHI */
97ea2859
RH		 3243 /* Special-case %g0 because that's the canonical nop. */
3244 if (rd) {
0f8a249a 3245 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 3246 TCGv t = gen_dest_gpr(dc, rd);
3247 tcg_gen_movi_tl(t, value << 10);
3248 gen_store_gpr(dc, rd, t);
0f8a249a 3249 }
0f8a249a
BS		 3250 break;
3251 case 0x0: /* UNIMPL */
3252 default:
3475187d 3253 goto illegal_insn;
0f8a249a
BS		 3254 }
3255 break;
3256 }
3257 break;
dc1a6971
BS		 3258 case 1: /*CALL*/
3259 {
0f8a249a 3260 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 3261 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 3262
97ea2859
RH		 3263 tcg_gen_movi_tl(o7, dc->pc);
3264 gen_store_gpr(dc, 15, o7);
0f8a249a 3265 target += dc->pc;
13a6dd00 3266 gen_mov_pc_npc(dc);
22036a49
AT		 3267#ifdef TARGET_SPARC64
3268 if (unlikely(AM_CHECK(dc))) {
3269 target &= 0xffffffffULL;
3270 }
3271#endif
0f8a249a
BS		 3272 dc->npc = target;
3273 }
3274 goto jmp_insn;
3275 case 2: /* FPU & Logical Operations */
3276 {
3277 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 3278 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 3279 TCGv cpu_tmp0;
5793f2a4 3280
0f8a249a 3281 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 3282 int cond = GET_FIELD(insn, 3, 6);
3283 TCGv_i32 trap;
42a268c2
RH		 3284 TCGLabel *l1 = NULL;
3285 int mask;
3475187d 3286
bd49ed41
RH		 3287 if (cond == 0) {
3288 /* Trap never. */
3289 break;
cf495bcf 3290 }
b04d9890 3291
bd49ed41 3292 save_state(dc);
b04d9890 3293
bd49ed41
RH		 3294 if (cond != 8) {
3295 /* Conditional trap. */
3a49e759 3296 DisasCompare cmp;
3475187d 3297#ifdef TARGET_SPARC64
0f8a249a
BS		 3298 /* V9 icc/xcc */
3299 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 3300 if (cc == 0) {
3301 gen_compare(&cmp, 0, cond, dc);
3302 } else if (cc == 2) {
3303 gen_compare(&cmp, 1, cond, dc);
3304 } else {
0f8a249a 3305 goto illegal_insn;
3a49e759 3306 }
3475187d 3307#else
3a49e759 3308 gen_compare(&cmp, 0, cond, dc);
3475187d 3309#endif
b158a785 3310 l1 = gen_new_label();
3a49e759
RH		 3311 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
3312 cmp.c1, cmp.c2, l1);
3313 free_compare(&cmp);
bd49ed41 3314 }
b158a785 3315
bd49ed41
RH		 3316 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3317 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3318
3319 /* Don't use the normal temporaries, as they may well have
3320 gone out of scope with the branch above. While we're
3321 doing that we might as well pre-truncate to 32-bit. */
3322 trap = tcg_temp_new_i32();
3323
3324 rs1 = GET_FIELD_SP(insn, 14, 18);
3325 if (IS_IMM) {
5c65df36 3326 rs2 = GET_FIELD_SP(insn, 0, 7);
bd49ed41
RH		 3327 if (rs1 == 0) {
3328 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
3329 /* Signal that the trap value is fully constant. */
3330 mask = 0;
3331 } else {
97ea2859 3332 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 3333 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3334 tcg_gen_addi_i32(trap, trap, rs2);
3335 }
3336 } else {
97ea2859 3337 TCGv t1, t2;
bd49ed41 3338 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 3339 t1 = gen_load_gpr(dc, rs1);
3340 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 3341 tcg_gen_add_tl(t1, t1, t2);
3342 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3343 }
3344 if (mask != 0) {
3345 tcg_gen_andi_i32(trap, trap, mask);
3346 tcg_gen_addi_i32(trap, trap, TT_TRAP);
3347 }
3348
3349 gen_helper_raise_exception(cpu_env, trap);
3350 tcg_temp_free_i32(trap);
b158a785 3351
fe1755cb
RH		 3352 if (cond == 8) {
3353 /* An unconditional trap ends the TB. */
af00be49 3354 dc->base.is_jmp = DISAS_NORETURN;
fe1755cb
RH		 3355 goto jmp_insn;
3356 } else {
3357 /* A conditional trap falls through to the next insn. */
b158a785 3358 gen_set_label(l1);
fe1755cb 3359 break;
cf495bcf
FB		 3360 }
3361 } else if (xop == 0x28) {
3362 rs1 = GET_FIELD(insn, 13, 17);
3363 switch(rs1) {
3364 case 0: /* rdy */
65fe7b09
BS		 3365#ifndef TARGET_SPARC64
3366 case 0x01 ... 0x0e: /* undefined in the SPARCv8
3367 manual, rdy on the microSPARC
3368 II */
3369 case 0x0f: /* stbar in the SPARCv8 manual,
3370 rdy on the microSPARC II */
3371 case 0x10 ... 0x1f: /* implementation-dependent in the
3372 SPARCv8 manual, rdy on the
3373 microSPARC II */
4a2ba232
FC		 3374 /* Read Asr17 */
3375 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 3376 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 3377 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 3378 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
3379 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 3380 break;
3381 }
65fe7b09 3382#endif
97ea2859 3383 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 3384 break;
3475187d 3385#ifdef TARGET_SPARC64
0f8a249a 3386 case 0x2: /* V9 rdccr */
20132b96 3387 update_psr(dc);
063c3675 3388 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 3389 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3390 break;
0f8a249a 3391 case 0x3: /* V9 rdasi */
a6d567e5 3392 tcg_gen_movi_tl(cpu_dst, dc->asi);
97ea2859 3393 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3394 break;
0f8a249a 3395 case 0x4: /* V9 rdtick */
ccd4a219 3396 {
a7812ae4 3397 TCGv_ptr r_tickptr;
c9a46442 3398 TCGv_i32 r_const;
ccd4a219 3399
a7812ae4 3400 r_tickptr = tcg_temp_new_ptr();
c9a46442 3401 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3402 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3403 offsetof(CPUSPARCState, tick));
46bb0137
MCA		 3404 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3405 gen_io_start();
3406 }
c9a46442
MCA		 3407 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3408 r_const);
a7812ae4 3409 tcg_temp_free_ptr(r_tickptr);
c9a46442 3410 tcg_temp_free_i32(r_const);
97ea2859 3411 gen_store_gpr(dc, rd, cpu_dst);
46bb0137
MCA		 3412 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3413 gen_io_end();
3414 }
ccd4a219 3415 }
3475187d 3416 break;
0f8a249a 3417 case 0x5: /* V9 rdpc */
2ea815ca 3418 {
97ea2859 3419 TCGv t = gen_dest_gpr(dc, rd);
22036a49 3420 if (unlikely(AM_CHECK(dc))) {
97ea2859 3421 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 3422 } else {
97ea2859 3423 tcg_gen_movi_tl(t, dc->pc);
22036a49 3424 }
97ea2859 3425 gen_store_gpr(dc, rd, t);
2ea815ca 3426 }
0f8a249a
BS		 3427 break;
3428 case 0x6: /* V9 rdfprs */
255e1fcb 3429 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 3430 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3431 break;
65fe7b09
BS		 3432 case 0xf: /* V9 membar */
3433 break; /* no effect */
0f8a249a 3434 case 0x13: /* Graphics Status */
5b12f1e8 3435 if (gen_trap_ifnofpu(dc)) {
725cb90b 3436 goto jmp_insn;
5b12f1e8 3437 }
97ea2859 3438 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 3439 break;
9d926598 3440 case 0x16: /* Softint */
e86ceb0d
RH		 3441 tcg_gen_ld32s_tl(cpu_dst, cpu_env,
3442 offsetof(CPUSPARCState, softint));
97ea2859 3443 gen_store_gpr(dc, rd, cpu_dst);
9d926598 3444 break;
0f8a249a 3445 case 0x17: /* Tick compare */
97ea2859 3446 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 3447 break;
0f8a249a 3448 case 0x18: /* System tick */
ccd4a219 3449 {
a7812ae4 3450 TCGv_ptr r_tickptr;
c9a46442 3451 TCGv_i32 r_const;
ccd4a219 3452
a7812ae4 3453 r_tickptr = tcg_temp_new_ptr();
c9a46442 3454 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3455 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3456 offsetof(CPUSPARCState, stick));
46bb0137
MCA		 3457 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3458 gen_io_start();
3459 }
c9a46442
MCA		 3460 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3461 r_const);
a7812ae4 3462 tcg_temp_free_ptr(r_tickptr);
c9a46442 3463 tcg_temp_free_i32(r_const);
97ea2859 3464 gen_store_gpr(dc, rd, cpu_dst);
46bb0137
MCA		 3465 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3466 gen_io_end();
3467 }
ccd4a219 3468 }
83469015 3469 break;
0f8a249a 3470 case 0x19: /* System tick compare */
97ea2859 3471 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 3472 break;
b8e31b3c
AT		 3473 case 0x1a: /* UltraSPARC-T1 Strand status */
3474 /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
3475 * this ASR as impl. dep
3476 */
3477 CHECK_IU_FEATURE(dc, HYPV);
3478 {
3479 TCGv t = gen_dest_gpr(dc, rd);
3480 tcg_gen_movi_tl(t, 1UL);
3481 gen_store_gpr(dc, rd, t);
3482 }
3483 break;
0f8a249a
BS		 3484 case 0x10: /* Performance Control */
3485 case 0x11: /* Performance Instrumentation Counter */
3486 case 0x12: /* Dispatch Control */
3487 case 0x14: /* Softint set, WO */
3488 case 0x15: /* Softint clear, WO */
3475187d
FB		 3489#endif
3490 default:
cf495bcf
FB		 3491 goto illegal_insn;
3492 }
e8af50a3 3493#if !defined(CONFIG_USER_ONLY)
e9ebed4d 3494 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 3495#ifndef TARGET_SPARC64
20132b96 3496 if (!supervisor(dc)) {
0f8a249a 3497 goto priv_insn;
20132b96
RH		 3498 }
3499 update_psr(dc);
063c3675 3500 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 3501#else
fb79ceb9 3502 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3503 if (!hypervisor(dc))
3504 goto priv_insn;
3505 rs1 = GET_FIELD(insn, 13, 17);
3506 switch (rs1) {
3507 case 0: // hpstate
f7f17ef7
AT		 3508 tcg_gen_ld_i64(cpu_dst, cpu_env,
3509 offsetof(CPUSPARCState, hpstate));
e9ebed4d
BS		 3510 break;
3511 case 1: // htstate
3512 // gen_op_rdhtstate();
3513 break;
3514 case 3: // hintp
255e1fcb 3515 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 3516 break;
3517 case 5: // htba
255e1fcb 3518 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 3519 break;
3520 case 6: // hver
255e1fcb 3521 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 3522 break;
3523 case 31: // hstick_cmpr
255e1fcb 3524 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 3525 break;
3526 default:
3527 goto illegal_insn;
3528 }
3529#endif
97ea2859 3530 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 3531 break;
3475187d 3532 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 3533 if (!supervisor(dc)) {
0f8a249a 3534 goto priv_insn;
de9e9d9f
RH		 3535 }
3536 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 3537#ifdef TARGET_SPARC64
3538 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3539 switch (rs1) {
3540 case 0: // tpc
375ee38b 3541 {
a7812ae4 3542 TCGv_ptr r_tsptr;
375ee38b 3543
a7812ae4 3544 r_tsptr = tcg_temp_new_ptr();
8194f35a 3545 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 3546 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3547 offsetof(trap_state, tpc));
a7812ae4 3548 tcg_temp_free_ptr(r_tsptr);
375ee38b 3549 }
0f8a249a
BS		 3550 break;
3551 case 1: // tnpc
375ee38b 3552 {
a7812ae4 3553 TCGv_ptr r_tsptr;
375ee38b 3554
a7812ae4 3555 r_tsptr = tcg_temp_new_ptr();
8194f35a 3556 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3557 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3558 offsetof(trap_state, tnpc));
a7812ae4 3559 tcg_temp_free_ptr(r_tsptr);
375ee38b 3560 }
0f8a249a
BS		 3561 break;
3562 case 2: // tstate
375ee38b 3563 {
a7812ae4 3564 TCGv_ptr r_tsptr;
375ee38b 3565
a7812ae4 3566 r_tsptr = tcg_temp_new_ptr();
8194f35a 3567 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3568 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3569 offsetof(trap_state, tstate));
a7812ae4 3570 tcg_temp_free_ptr(r_tsptr);
375ee38b 3571 }
0f8a249a
BS		 3572 break;
3573 case 3: // tt
375ee38b 3574 {
45778f99 3575 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 3576
8194f35a 3577 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 3578 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
3579 offsetof(trap_state, tt));
a7812ae4 3580 tcg_temp_free_ptr(r_tsptr);
375ee38b 3581 }
0f8a249a
BS		 3582 break;
3583 case 4: // tick
ccd4a219 3584 {
a7812ae4 3585 TCGv_ptr r_tickptr;
c9a46442 3586 TCGv_i32 r_const;
ccd4a219 3587
a7812ae4 3588 r_tickptr = tcg_temp_new_ptr();
c9a46442 3589 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3590 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3591 offsetof(CPUSPARCState, tick));
46bb0137
MCA		 3592 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3593 gen_io_start();
3594 }
c9a46442
MCA		 3595 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
3596 r_tickptr, r_const);
a7812ae4 3597 tcg_temp_free_ptr(r_tickptr);
c9a46442 3598 tcg_temp_free_i32(r_const);
46bb0137
MCA		 3599 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
3600 gen_io_end();
3601 }
ccd4a219 3602 }
0f8a249a
BS		 3603 break;
3604 case 5: // tba
255e1fcb 3605 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 3606 break;
3607 case 6: // pstate
45778f99
RH		 3608 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3609 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 3610 break;
3611 case 7: // tl
45778f99
RH		 3612 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3613 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3614 break;
3615 case 8: // pil
45778f99
RH		 3616 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3617 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3618 break;
3619 case 9: // cwp
063c3675 3620 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 3621 break;
3622 case 10: // cansave
45778f99
RH		 3623 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3624 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3625 break;
3626 case 11: // canrestore
45778f99
RH		 3627 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3628 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3629 break;
3630 case 12: // cleanwin
45778f99
RH		 3631 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3632 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3633 break;
3634 case 13: // otherwin
45778f99
RH		 3635 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3636 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3637 break;
3638 case 14: // wstate
45778f99
RH		 3639 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3640 offsetof(CPUSPARCState, wstate));
0f8a249a 3641 break;
e9ebed4d 3642 case 16: // UA2005 gl
fb79ceb9 3643 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 3644 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3645 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3646 break;
3647 case 26: // UA2005 strand status
fb79ceb9 3648 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3649 if (!hypervisor(dc))
3650 goto priv_insn;
527067d8 3651 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 3652 break;
0f8a249a 3653 case 31: // ver
255e1fcb 3654 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 3655 break;
3656 case 15: // fq
3657 default:
3658 goto illegal_insn;
3659 }
3475187d 3660#else
255e1fcb 3661 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 3662#endif
97ea2859 3663 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 3664 break;
aa04c9d9
GM		 3665#endif
3666#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
3475187d
FB		 3667 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
3668#ifdef TARGET_SPARC64
063c3675 3669 gen_helper_flushw(cpu_env);
3475187d 3670#else
0f8a249a
BS		 3671 if (!supervisor(dc))
3672 goto priv_insn;
97ea2859 3673 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 3674#endif
e8af50a3
FB		 3675 break;
3676#endif
0f8a249a 3677 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 3678 if (gen_trap_ifnofpu(dc)) {
a80dde08 3679 goto jmp_insn;
5b12f1e8 3680 }
0f8a249a 3681 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 3682 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3683 rs2 = GET_FIELD(insn, 27, 31);
3684 xop = GET_FIELD(insn, 18, 26);
02c79d78 3685
0f8a249a 3686 switch (xop) {
dc1a6971 3687 case 0x1: /* fmovs */
208ae657
RH		 3688 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3689 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 3690 break;
3691 case 0x5: /* fnegs */
61f17f6e 3692 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 3693 break;
3694 case 0x9: /* fabss */
61f17f6e 3695 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 3696 break;
3697 case 0x29: /* fsqrts */
3698 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3699 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 3700 break;
3701 case 0x2a: /* fsqrtd */
3702 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3703 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 3704 break;
3705 case 0x2b: /* fsqrtq */
3706 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3707 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 3708 break;
3709 case 0x41: /* fadds */
61f17f6e 3710 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 3711 break;
3712 case 0x42: /* faddd */
61f17f6e 3713 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 3714 break;
3715 case 0x43: /* faddq */
3716 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3717 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 3718 break;
3719 case 0x45: /* fsubs */
61f17f6e 3720 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 3721 break;
3722 case 0x46: /* fsubd */
61f17f6e 3723 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3724 break;
3725 case 0x47: /* fsubq */
3726 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3727 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3728 break;
3729 case 0x49: /* fmuls */
3730 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3731 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3732 break;
3733 case 0x4a: /* fmuld */
3734 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3735 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3736 break;
3737 case 0x4b: /* fmulq */
3738 CHECK_FPU_FEATURE(dc, FLOAT128);
3739 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3740 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3741 break;
3742 case 0x4d: /* fdivs */
61f17f6e 3743 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3744 break;
3745 case 0x4e: /* fdivd */
61f17f6e 3746 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3747 break;
3748 case 0x4f: /* fdivq */
3749 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3750 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3751 break;
3752 case 0x69: /* fsmuld */
3753 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3754 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3755 break;
3756 case 0x6e: /* fdmulq */
3757 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3758 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3759 break;
3760 case 0xc4: /* fitos */
61f17f6e 3761 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3762 break;
3763 case 0xc6: /* fdtos */
61f17f6e 3764 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3765 break;
3766 case 0xc7: /* fqtos */
3767 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3768 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3769 break;
3770 case 0xc8: /* fitod */
61f17f6e 3771 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3772 break;
3773 case 0xc9: /* fstod */
61f17f6e 3774 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3775 break;
3776 case 0xcb: /* fqtod */
3777 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3778 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3779 break;
3780 case 0xcc: /* fitoq */
3781 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3782 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3783 break;
3784 case 0xcd: /* fstoq */
3785 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3786 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3787 break;
3788 case 0xce: /* fdtoq */
3789 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3790 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3791 break;
3792 case 0xd1: /* fstoi */
61f17f6e 3793 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3794 break;
3795 case 0xd2: /* fdtoi */
61f17f6e 3796 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3797 break;
3798 case 0xd3: /* fqtoi */
3799 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3800 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3801 break;
3475187d 3802#ifdef TARGET_SPARC64
dc1a6971 3803 case 0x2: /* V9 fmovd */
96eda024
RH		 3804 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3805 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3806 break;
3807 case 0x3: /* V9 fmovq */
3808 CHECK_FPU_FEATURE(dc, FLOAT128);
f9c816c0 3809 gen_move_Q(dc, rd, rs2);
dc1a6971
BS		 3810 break;
3811 case 0x6: /* V9 fnegd */
61f17f6e 3812 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3813 break;
3814 case 0x7: /* V9 fnegq */
3815 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3816 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3817 break;
3818 case 0xa: /* V9 fabsd */
61f17f6e 3819 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3820 break;
3821 case 0xb: /* V9 fabsq */
3822 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3823 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3824 break;
3825 case 0x81: /* V9 fstox */
61f17f6e 3826 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3827 break;
3828 case 0x82: /* V9 fdtox */
61f17f6e 3829 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3830 break;
3831 case 0x83: /* V9 fqtox */
3832 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3833 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3834 break;
3835 case 0x84: /* V9 fxtos */
61f17f6e 3836 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3837 break;
3838 case 0x88: /* V9 fxtod */
61f17f6e 3839 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3840 break;
3841 case 0x8c: /* V9 fxtoq */
3842 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3843 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3844 break;
0f8a249a 3845#endif
dc1a6971
BS		 3846 default:
3847 goto illegal_insn;
0f8a249a
BS		 3848 }
3849 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3850#ifdef TARGET_SPARC64
0f8a249a 3851 int cond;
3475187d 3852#endif
5b12f1e8 3853 if (gen_trap_ifnofpu(dc)) {
a80dde08 3854 goto jmp_insn;
5b12f1e8 3855 }
0f8a249a 3856 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3857 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3858 rs2 = GET_FIELD(insn, 27, 31);
3859 xop = GET_FIELD(insn, 18, 26);
dcf24905 3860
690995a6
RH		 3861#ifdef TARGET_SPARC64
3862#define FMOVR(sz) \
3863 do { \
3864 DisasCompare cmp; \
e7c8afb9 3865 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3866 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3867 gen_compare_reg(&cmp, cond, cpu_src1); \
3868 gen_fmov##sz(dc, &cmp, rd, rs2); \
3869 free_compare(&cmp); \
3870 } while (0)
3871
3872 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3873 FMOVR(s);
0f8a249a
BS		 3874 break;
3875 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3876 FMOVR(d);
0f8a249a
BS		 3877 break;
3878 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3879 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3880 FMOVR(q);
1f587329 3881 break;
0f8a249a 3882 }
690995a6 3883#undef FMOVR
0f8a249a
BS		 3884#endif
3885 switch (xop) {
3475187d 3886#ifdef TARGET_SPARC64
7e480893
RH		 3887#define FMOVCC(fcc, sz) \
3888 do { \
3889 DisasCompare cmp; \
714547bb 3890 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3891 gen_fcompare(&cmp, fcc, cond); \
3892 gen_fmov##sz(dc, &cmp, rd, rs2); \
3893 free_compare(&cmp); \
3894 } while (0)
3895
0f8a249a 3896 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3897 FMOVCC(0, s);
0f8a249a
BS		 3898 break;
3899 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3900 FMOVCC(0, d);
0f8a249a
BS		 3901 break;
3902 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3903 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3904 FMOVCC(0, q);
1f587329 3905 break;
0f8a249a 3906 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3907 FMOVCC(1, s);
0f8a249a
BS		 3908 break;
3909 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3910 FMOVCC(1, d);
0f8a249a
BS		 3911 break;
3912 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3913 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3914 FMOVCC(1, q);
1f587329 3915 break;
0f8a249a 3916 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3917 FMOVCC(2, s);
0f8a249a
BS		 3918 break;
3919 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3920 FMOVCC(2, d);
0f8a249a
BS		 3921 break;
3922 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3923 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3924 FMOVCC(2, q);
1f587329 3925 break;
0f8a249a 3926 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3927 FMOVCC(3, s);
0f8a249a
BS		 3928 break;
3929 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3930 FMOVCC(3, d);
0f8a249a
BS		 3931 break;
3932 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3933 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3934 FMOVCC(3, q);
1f587329 3935 break;
7e480893
RH		 3936#undef FMOVCC
3937#define FMOVCC(xcc, sz) \
3938 do { \
3939 DisasCompare cmp; \
714547bb 3940 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3941 gen_compare(&cmp, xcc, cond, dc); \
3942 gen_fmov##sz(dc, &cmp, rd, rs2); \
3943 free_compare(&cmp); \
3944 } while (0)
19f329ad 3945
0f8a249a 3946 case 0x101: /* V9 fmovscc %icc */
7e480893 3947 FMOVCC(0, s);
0f8a249a
BS		 3948 break;
3949 case 0x102: /* V9 fmovdcc %icc */
7e480893 3950 FMOVCC(0, d);
b7d69dc2 3951 break;
0f8a249a 3952 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3953 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3954 FMOVCC(0, q);
1f587329 3955 break;
0f8a249a 3956 case 0x181: /* V9 fmovscc %xcc */
7e480893 3957 FMOVCC(1, s);
0f8a249a
BS		 3958 break;
3959 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3960 FMOVCC(1, d);
0f8a249a
BS		 3961 break;
3962 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3963 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3964 FMOVCC(1, q);
1f587329 3965 break;
7e480893 3966#undef FMOVCC
1f587329
BS		 3967#endif
3968 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3969 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3970 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3971 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3972 break;
1f587329 3973 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3974 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3975 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3976 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3977 break;
1f587329 3978 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3979 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3980 gen_op_load_fpr_QT0(QFPREG(rs1));
3981 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3982 gen_op_fcmpq(rd & 3);
1f587329 3983 break;
0f8a249a 3984 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3985 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3986 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3987 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3988 break;
3989 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3990 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3991 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3992 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3993 break;
1f587329 3994 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3995 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3996 gen_op_load_fpr_QT0(QFPREG(rs1));
3997 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3998 gen_op_fcmpeq(rd & 3);
1f587329 3999 break;
0f8a249a
BS		 4000 default:
4001 goto illegal_insn;
4002 }
0f8a249a 4003 } else if (xop == 0x2) {
97ea2859 4004 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 4005 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 4006 if (rs1 == 0) {
97ea2859 4007 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 4008 if (IS_IMM) { /* immediate */
67526b20 4009 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 4010 tcg_gen_movi_tl(dst, simm);
4011 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4012 } else { /* register */
4013 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 4014 if (rs2 == 0) {
4015 tcg_gen_movi_tl(dst, 0);
4016 gen_store_gpr(dc, rd, dst);
4017 } else {
4018 cpu_src2 = gen_load_gpr(dc, rs2);
4019 gen_store_gpr(dc, rd, cpu_src2);
4020 }
0f8a249a 4021 }
0f8a249a 4022 } else {
9d1d4e34 4023 cpu_src1 = get_src1(dc, insn);
0f8a249a 4024 if (IS_IMM) { /* immediate */
67526b20 4025 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 4026 tcg_gen_ori_tl(dst, cpu_src1, simm);
4027 gen_store_gpr(dc, rd, dst);
0f8a249a 4028 } else { /* register */
0f8a249a 4029 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 4030 if (rs2 == 0) {
4031 /* mov shortcut: or x, %g0, y -> mov x, y */
4032 gen_store_gpr(dc, rd, cpu_src1);
4033 } else {
4034 cpu_src2 = gen_load_gpr(dc, rs2);
4035 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
4036 gen_store_gpr(dc, rd, dst);
4037 }
0f8a249a 4038 }
0f8a249a 4039 }
83469015 4040#ifdef TARGET_SPARC64
0f8a249a 4041 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 4042 cpu_src1 = get_src1(dc, insn);
0f8a249a 4043 if (IS_IMM) { /* immediate */
67526b20 4044 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4045 if (insn & (1 << 12)) {
67526b20 4046 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4047 } else {
67526b20 4048 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 4049 }
0f8a249a 4050 } else { /* register */
83469015 4051 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4052 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4053 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4054 if (insn & (1 << 12)) {
6ae20372 4055 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 4056 } else {
6ae20372 4057 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 4058 }
01b1fa6d 4059 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 4060 }
97ea2859 4061 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4062 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 4063 cpu_src1 = get_src1(dc, insn);
0f8a249a 4064 if (IS_IMM) { /* immediate */
67526b20 4065 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4066 if (insn & (1 << 12)) {
67526b20 4067 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4068 } else {
6ae20372 4069 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 4070 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4071 }
0f8a249a 4072 } else { /* register */
83469015 4073 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4074 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4075 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4076 if (insn & (1 << 12)) {
6ae20372
BS		 4077 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4078 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4079 } else {
6ae20372
BS		 4080 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4081 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
4082 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4083 }
83469015 4084 }
97ea2859 4085 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4086 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 4087 cpu_src1 = get_src1(dc, insn);
0f8a249a 4088 if (IS_IMM) { /* immediate */
67526b20 4089 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4090 if (insn & (1 << 12)) {
67526b20 4091 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4092 } else {
97ea2859 4093 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 4094 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4095 }
0f8a249a 4096 } else { /* register */
83469015 4097 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4098 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4099 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4100 if (insn & (1 << 12)) {
6ae20372
BS		 4101 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4102 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4103 } else {
6ae20372 4104 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 4105 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 4106 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4107 }
83469015 4108 }
97ea2859 4109 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 4110#endif
fcc72045 4111 } else if (xop < 0x36) {
cf495bcf 4112 if (xop < 0x20) {
9d1d4e34
RH		 4113 cpu_src1 = get_src1(dc, insn);
4114 cpu_src2 = get_src2(dc, insn);
cf495bcf 4115 switch (xop & ~0x10) {
b89e94af 4116 case 0x0: /* add */
97ea2859
RH		 4117 if (xop & 0x10) {
4118 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
4119 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4120 dc->cc_op = CC_OP_ADD;
41d72852 4121 } else {
97ea2859 4122 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4123 }
cf495bcf 4124 break;
b89e94af 4125 case 0x1: /* and */
97ea2859 4126 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4127 if (xop & 0x10) {
38482a77
BS		 4128 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4129 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4130 dc->cc_op = CC_OP_LOGIC;
41d72852 4131 }
cf495bcf 4132 break;
b89e94af 4133 case 0x2: /* or */
97ea2859 4134 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4135 if (xop & 0x10) {
38482a77
BS		 4136 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4137 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4138 dc->cc_op = CC_OP_LOGIC;
8393617c 4139 }
0f8a249a 4140 break;
b89e94af 4141 case 0x3: /* xor */
97ea2859 4142 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4143 if (xop & 0x10) {
38482a77
BS		 4144 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4145 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4146 dc->cc_op = CC_OP_LOGIC;
8393617c 4147 }
cf495bcf 4148 break;
b89e94af 4149 case 0x4: /* sub */
97ea2859
RH		 4150 if (xop & 0x10) {
4151 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
4152 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
4153 dc->cc_op = CC_OP_SUB;
41d72852 4154 } else {
97ea2859 4155 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4156 }
cf495bcf 4157 break;
b89e94af 4158 case 0x5: /* andn */
97ea2859 4159 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4160 if (xop & 0x10) {
38482a77
BS		 4161 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4162 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4163 dc->cc_op = CC_OP_LOGIC;
8393617c 4164 }
cf495bcf 4165 break;
b89e94af 4166 case 0x6: /* orn */
97ea2859 4167 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4168 if (xop & 0x10) {
38482a77
BS		 4169 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4170 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4171 dc->cc_op = CC_OP_LOGIC;
8393617c 4172 }
cf495bcf 4173 break;
b89e94af 4174 case 0x7: /* xorn */
97ea2859 4175 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4176 if (xop & 0x10) {
38482a77
BS		 4177 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4178 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4179 dc->cc_op = CC_OP_LOGIC;
8393617c 4180 }
cf495bcf 4181 break;
b89e94af 4182 case 0x8: /* addx, V9 addc */
70c48285
RH		 4183 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4184 (xop & 0x10));
cf495bcf 4185 break;
ded3ab80 4186#ifdef TARGET_SPARC64
0f8a249a 4187 case 0x9: /* V9 mulx */
97ea2859 4188 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 4189 break;
4190#endif
b89e94af 4191 case 0xa: /* umul */
64a88d5d 4192 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4193 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4194 if (xop & 0x10) {
38482a77
BS		 4195 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4196 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4197 dc->cc_op = CC_OP_LOGIC;
8393617c 4198 }
cf495bcf 4199 break;
b89e94af 4200 case 0xb: /* smul */
64a88d5d 4201 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4202 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4203 if (xop & 0x10) {
38482a77
BS		 4204 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4205 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4206 dc->cc_op = CC_OP_LOGIC;
8393617c 4207 }
cf495bcf 4208 break;
b89e94af 4209 case 0xc: /* subx, V9 subc */
70c48285
RH		 4210 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4211 (xop & 0x10));
cf495bcf 4212 break;
ded3ab80 4213#ifdef TARGET_SPARC64
0f8a249a 4214 case 0xd: /* V9 udivx */
c28ae41e 4215 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 4216 break;
4217#endif
b89e94af 4218 case 0xe: /* udiv */
64a88d5d 4219 CHECK_IU_FEATURE(dc, DIV);
8393617c 4220 if (xop & 0x10) {
7a5e4488
BS		 4221 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
4222 cpu_src2);
6c78ea32 4223 dc->cc_op = CC_OP_DIV;
0fcec41e 4224 } else {
7a5e4488
BS		 4225 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
4226 cpu_src2);
8393617c 4227 }
cf495bcf 4228 break;
b89e94af 4229 case 0xf: /* sdiv */
64a88d5d 4230 CHECK_IU_FEATURE(dc, DIV);
8393617c 4231 if (xop & 0x10) {
7a5e4488
BS		 4232 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
4233 cpu_src2);
6c78ea32 4234 dc->cc_op = CC_OP_DIV;
0fcec41e 4235 } else {
7a5e4488
BS		 4236 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
4237 cpu_src2);
8393617c 4238 }
cf495bcf
FB		 4239 break;
4240 default:
4241 goto illegal_insn;
4242 }
97ea2859 4243 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4244 } else {
9d1d4e34
RH		 4245 cpu_src1 = get_src1(dc, insn);
4246 cpu_src2 = get_src2(dc, insn);
cf495bcf 4247 switch (xop) {
0f8a249a 4248 case 0x20: /* taddcc */
a2ea4aa9 4249 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4250 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4251 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
4252 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 4253 break;
4254 case 0x21: /* tsubcc */
a2ea4aa9 4255 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4256 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4257 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
4258 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 4259 break;
4260 case 0x22: /* taddcctv */
a2ea4aa9
RH		 4261 gen_helper_taddcctv(cpu_dst, cpu_env,
4262 cpu_src1, cpu_src2);
97ea2859 4263 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4264 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 4265 break;
4266 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 4267 gen_helper_tsubcctv(cpu_dst, cpu_env,
4268 cpu_src1, cpu_src2);
97ea2859 4269 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4270 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 4271 break;
cf495bcf 4272 case 0x24: /* mulscc */
20132b96 4273 update_psr(dc);
6ae20372 4274 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4275 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 4276 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4277 dc->cc_op = CC_OP_ADD;
cf495bcf 4278 break;
83469015 4279#ifndef TARGET_SPARC64
0f8a249a 4280 case 0x25: /* sll */
e35298cd 4281 if (IS_IMM) { /* immediate */
67526b20
BS		 4282 simm = GET_FIELDs(insn, 20, 31);
4283 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4284 } else { /* register */
de9e9d9f 4285 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4286 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4287 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
4288 }
97ea2859 4289 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4290 break;
83469015 4291 case 0x26: /* srl */
e35298cd 4292 if (IS_IMM) { /* immediate */
67526b20
BS		 4293 simm = GET_FIELDs(insn, 20, 31);
4294 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4295 } else { /* register */
de9e9d9f 4296 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4297 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4298 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
4299 }
97ea2859 4300 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4301 break;
83469015 4302 case 0x27: /* sra */
e35298cd 4303 if (IS_IMM) { /* immediate */
67526b20
BS		 4304 simm = GET_FIELDs(insn, 20, 31);
4305 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4306 } else { /* register */
de9e9d9f 4307 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4308 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4309 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
4310 }
97ea2859 4311 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4312 break;
83469015 4313#endif
cf495bcf
FB		 4314 case 0x30:
4315 {
de9e9d9f 4316 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 4317 switch(rd) {
3475187d 4318 case 0: /* wry */
5068cbd9
BS		 4319 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4320 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 4321 break;
65fe7b09
BS		 4322#ifndef TARGET_SPARC64
4323 case 0x01 ... 0x0f: /* undefined in the
4324 SPARCv8 manual, nop
4325 on the microSPARC
4326 II */
4327 case 0x10 ... 0x1f: /* implementation-dependent
4328 in the SPARCv8
4329 manual, nop on the
4330 microSPARC II */
d1c36ba7
RH		 4331 if ((rd == 0x13) && (dc->def->features &
4332 CPU_FEATURE_POWERDOWN)) {
4333 /* LEON3 power-down */
1cf892ca 4334 save_state(dc);
d1c36ba7
RH		 4335 gen_helper_power_down(cpu_env);
4336 }
65fe7b09
BS		 4337 break;
4338#else
0f8a249a 4339 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 4340 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4341 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 4342 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4343 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 4344 break;
4345 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 4346 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4347 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
a6d567e5
RH		 4348 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4349 offsetof(CPUSPARCState, asi));
4350 /* End TB to notice changed ASI. */
4351 save_state(dc);
4352 gen_op_next_insn();
07ea28b4 4353 tcg_gen_exit_tb(NULL, 0);
af00be49 4354 dc->base.is_jmp = DISAS_NORETURN;
0f8a249a
BS		 4355 break;
4356 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 4357 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4358 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
f9c816c0 4359 dc->fprs_dirty = 0;
66442b07 4360 save_state(dc);
3299908c 4361 gen_op_next_insn();
07ea28b4 4362 tcg_gen_exit_tb(NULL, 0);
af00be49 4363 dc->base.is_jmp = DISAS_NORETURN;
0f8a249a
BS		 4364 break;
4365 case 0xf: /* V9 sir, nop if user */
3475187d 4366#if !defined(CONFIG_USER_ONLY)
6ad6135d 4367 if (supervisor(dc)) {
1a2fb1c0 4368 ; // XXX
6ad6135d 4369 }
3475187d 4370#endif
0f8a249a
BS		 4371 break;
4372 case 0x13: /* Graphics Status */
5b12f1e8 4373 if (gen_trap_ifnofpu(dc)) {
725cb90b 4374 goto jmp_insn;
5b12f1e8 4375 }
255e1fcb 4376 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 4377 break;
9d926598
BS		 4378 case 0x14: /* Softint set */
4379 if (!supervisor(dc))
4380 goto illegal_insn;
aeff993c
RH		 4381 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4382 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4383 break;
4384 case 0x15: /* Softint clear */
4385 if (!supervisor(dc))
4386 goto illegal_insn;
aeff993c
RH		 4387 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4388 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4389 break;
4390 case 0x16: /* Softint write */
4391 if (!supervisor(dc))
4392 goto illegal_insn;
aeff993c
RH		 4393 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4394 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 4395 break;
0f8a249a 4396 case 0x17: /* Tick compare */
83469015 4397#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4398 if (!supervisor(dc))
4399 goto illegal_insn;
83469015 4400#endif
ccd4a219 4401 {
a7812ae4 4402 TCGv_ptr r_tickptr;
ccd4a219 4403
255e1fcb 4404 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 4405 cpu_src2);
a7812ae4 4406 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4407 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4408 offsetof(CPUSPARCState, tick));
46bb0137
MCA		 4409 if (tb_cflags(dc->base.tb) &
4410 CF_USE_ICOUNT) {
4411 gen_io_start();
4412 }
a7812ae4
PB		 4413 gen_helper_tick_set_limit(r_tickptr,
4414 cpu_tick_cmpr);
4415 tcg_temp_free_ptr(r_tickptr);
46bb0137
MCA		 4416 /* End TB to handle timer interrupt */
4417 dc->base.is_jmp = DISAS_EXIT;
ccd4a219 4418 }
0f8a249a
BS		 4419 break;
4420 case 0x18: /* System tick */
83469015 4421#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4422 if (!supervisor(dc))
4423 goto illegal_insn;
83469015 4424#endif
ccd4a219 4425 {
a7812ae4 4426 TCGv_ptr r_tickptr;
ccd4a219 4427
7b04bd5c 4428 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 4429 cpu_src2);
a7812ae4 4430 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4431 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4432 offsetof(CPUSPARCState, stick));
46bb0137
MCA		 4433 if (tb_cflags(dc->base.tb) &
4434 CF_USE_ICOUNT) {
4435 gen_io_start();
4436 }
a7812ae4 4437 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 4438 cpu_tmp0);
a7812ae4 4439 tcg_temp_free_ptr(r_tickptr);
46bb0137
MCA		 4440 /* End TB to handle timer interrupt */
4441 dc->base.is_jmp = DISAS_EXIT;
ccd4a219 4442 }
0f8a249a
BS		 4443 break;
4444 case 0x19: /* System tick compare */
83469015 4445#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4446 if (!supervisor(dc))
4447 goto illegal_insn;
3475187d 4448#endif
ccd4a219 4449 {
a7812ae4 4450 TCGv_ptr r_tickptr;
ccd4a219 4451
255e1fcb 4452 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 4453 cpu_src2);
a7812ae4 4454 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4455 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4456 offsetof(CPUSPARCState, stick));
46bb0137
MCA		 4457 if (tb_cflags(dc->base.tb) &
4458 CF_USE_ICOUNT) {
4459 gen_io_start();
4460 }
a7812ae4
PB		 4461 gen_helper_tick_set_limit(r_tickptr,
4462 cpu_stick_cmpr);
4463 tcg_temp_free_ptr(r_tickptr);
46bb0137
MCA		 4464 /* End TB to handle timer interrupt */
4465 dc->base.is_jmp = DISAS_EXIT;
ccd4a219 4466 }
0f8a249a 4467 break;
83469015 4468
0f8a249a 4469 case 0x10: /* Performance Control */
77f193da
BS		 4470 case 0x11: /* Performance Instrumentation
4471 Counter */
0f8a249a 4472 case 0x12: /* Dispatch Control */
83469015 4473#endif
3475187d 4474 default:
cf495bcf
FB		 4475 goto illegal_insn;
4476 }
4477 }
4478 break;
e8af50a3 4479#if !defined(CONFIG_USER_ONLY)
af7bf89b 4480 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 4481 {
0f8a249a
BS		 4482 if (!supervisor(dc))
4483 goto priv_insn;
3475187d 4484#ifdef TARGET_SPARC64
0f8a249a
BS		 4485 switch (rd) {
4486 case 0:
063c3675 4487 gen_helper_saved(cpu_env);
0f8a249a
BS		 4488 break;
4489 case 1:
063c3675 4490 gen_helper_restored(cpu_env);
0f8a249a 4491 break;
e9ebed4d
BS		 4492 case 2: /* UA2005 allclean */
4493 case 3: /* UA2005 otherw */
4494 case 4: /* UA2005 normalw */
4495 case 5: /* UA2005 invalw */
4496 // XXX
0f8a249a 4497 default:
3475187d
FB		 4498 goto illegal_insn;
4499 }
4500#else
de9e9d9f 4501 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 4502 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4503 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 4504 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4505 dc->cc_op = CC_OP_FLAGS;
66442b07 4506 save_state(dc);
9e61bde5 4507 gen_op_next_insn();
07ea28b4 4508 tcg_gen_exit_tb(NULL, 0);
af00be49 4509 dc->base.is_jmp = DISAS_NORETURN;
3475187d 4510#endif
e8af50a3
FB		 4511 }
4512 break;
af7bf89b 4513 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 4514 {
0f8a249a
BS		 4515 if (!supervisor(dc))
4516 goto priv_insn;
de9e9d9f 4517 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4518 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 4519#ifdef TARGET_SPARC64
0f8a249a
BS		 4520 switch (rd) {
4521 case 0: // tpc
375ee38b 4522 {
a7812ae4 4523 TCGv_ptr r_tsptr;
375ee38b 4524
a7812ae4 4525 r_tsptr = tcg_temp_new_ptr();
8194f35a 4526 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4527 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4528 offsetof(trap_state, tpc));
a7812ae4 4529 tcg_temp_free_ptr(r_tsptr);
375ee38b 4530 }
0f8a249a
BS		 4531 break;
4532 case 1: // tnpc
375ee38b 4533 {
a7812ae4 4534 TCGv_ptr r_tsptr;
375ee38b 4535
a7812ae4 4536 r_tsptr = tcg_temp_new_ptr();
8194f35a 4537 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4538 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4539 offsetof(trap_state, tnpc));
a7812ae4 4540 tcg_temp_free_ptr(r_tsptr);
375ee38b 4541 }
0f8a249a
BS		 4542 break;
4543 case 2: // tstate
375ee38b 4544 {
a7812ae4 4545 TCGv_ptr r_tsptr;
375ee38b 4546
a7812ae4 4547 r_tsptr = tcg_temp_new_ptr();
8194f35a 4548 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4549 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 4550 offsetof(trap_state,
4551 tstate));
a7812ae4 4552 tcg_temp_free_ptr(r_tsptr);
375ee38b 4553 }
0f8a249a
BS		 4554 break;
4555 case 3: // tt
375ee38b 4556 {
a7812ae4 4557 TCGv_ptr r_tsptr;
375ee38b 4558
a7812ae4 4559 r_tsptr = tcg_temp_new_ptr();
8194f35a 4560 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 4561 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
4562 offsetof(trap_state, tt));
a7812ae4 4563 tcg_temp_free_ptr(r_tsptr);
375ee38b 4564 }
0f8a249a
BS		 4565 break;
4566 case 4: // tick
ccd4a219 4567 {
a7812ae4 4568 TCGv_ptr r_tickptr;
ccd4a219 4569
a7812ae4 4570 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4571 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4572 offsetof(CPUSPARCState, tick));
46bb0137
MCA		 4573 if (tb_cflags(dc->base.tb) &
4574 CF_USE_ICOUNT) {
4575 gen_io_start();
4576 }
a7812ae4
PB		 4577 gen_helper_tick_set_count(r_tickptr,
4578 cpu_tmp0);
4579 tcg_temp_free_ptr(r_tickptr);
46bb0137
MCA		 4580 /* End TB to handle timer interrupt */
4581 dc->base.is_jmp = DISAS_EXIT;
ccd4a219 4582 }
0f8a249a
BS		 4583 break;
4584 case 5: // tba
255e1fcb 4585 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 4586 break;
4587 case 6: // pstate
6234ac09 4588 save_state(dc);
46bb0137
MCA		 4589 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
4590 gen_io_start();
4591 }
6234ac09 4592 gen_helper_wrpstate(cpu_env, cpu_tmp0);
46bb0137
MCA		 4593 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
4594 gen_io_end();
4595 }
6234ac09 4596 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4597 break;
4598 case 7: // tl
6234ac09 4599 save_state(dc);
7b9e066b 4600 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 4601 offsetof(CPUSPARCState, tl));
4602 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4603 break;
4604 case 8: // pil
46bb0137
MCA		 4605 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
4606 gen_io_start();
4607 }
063c3675 4608 gen_helper_wrpil(cpu_env, cpu_tmp0);
46bb0137
MCA		 4609 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
4610 gen_io_end();
4611 }
0f8a249a
BS		 4612 break;
4613 case 9: // cwp
063c3675 4614 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 4615 break;
4616 case 10: // cansave
7b9e066b
RH		 4617 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4618 offsetof(CPUSPARCState,
4619 cansave));
0f8a249a
BS		 4620 break;
4621 case 11: // canrestore
7b9e066b
RH		 4622 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4623 offsetof(CPUSPARCState,
4624 canrestore));
0f8a249a
BS		 4625 break;
4626 case 12: // cleanwin
7b9e066b
RH		 4627 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4628 offsetof(CPUSPARCState,
4629 cleanwin));
0f8a249a
BS		 4630 break;
4631 case 13: // otherwin
7b9e066b
RH		 4632 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4633 offsetof(CPUSPARCState,
4634 otherwin));
0f8a249a
BS		 4635 break;
4636 case 14: // wstate
7b9e066b
RH		 4637 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4638 offsetof(CPUSPARCState,
4639 wstate));
0f8a249a 4640 break;
e9ebed4d 4641 case 16: // UA2005 gl
fb79ceb9 4642 CHECK_IU_FEATURE(dc, GL);
cbc3a6a4 4643 gen_helper_wrgl(cpu_env, cpu_tmp0);
e9ebed4d
BS		 4644 break;
4645 case 26: // UA2005 strand status
fb79ceb9 4646 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4647 if (!hypervisor(dc))
4648 goto priv_insn;
527067d8 4649 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 4650 break;
0f8a249a
BS		 4651 default:
4652 goto illegal_insn;
4653 }
3475187d 4654#else
7b9e066b
RH		 4655 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
4656 if (dc->def->nwindows != 32) {
4657 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 4658 (1 << dc->def->nwindows) - 1);
7b9e066b 4659 }
3475187d 4660#endif
e8af50a3
FB		 4661 }
4662 break;
e9ebed4d 4663 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 4664 {
e9ebed4d 4665#ifndef TARGET_SPARC64
0f8a249a
BS		 4666 if (!supervisor(dc))
4667 goto priv_insn;
255e1fcb 4668 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 4669#else
fb79ceb9 4670 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4671 if (!hypervisor(dc))
4672 goto priv_insn;
de9e9d9f 4673 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4674 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 4675 switch (rd) {
4676 case 0: // hpstate
f7f17ef7
AT		 4677 tcg_gen_st_i64(cpu_tmp0, cpu_env,
4678 offsetof(CPUSPARCState,
4679 hpstate));
66442b07 4680 save_state(dc);
e9ebed4d 4681 gen_op_next_insn();
07ea28b4 4682 tcg_gen_exit_tb(NULL, 0);
af00be49 4683 dc->base.is_jmp = DISAS_NORETURN;
e9ebed4d
BS		 4684 break;
4685 case 1: // htstate
4686 // XXX gen_op_wrhtstate();
4687 break;
4688 case 3: // hintp
255e1fcb 4689 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 4690 break;
4691 case 5: // htba
255e1fcb 4692 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 4693 break;
4694 case 31: // hstick_cmpr
ccd4a219 4695 {
a7812ae4 4696 TCGv_ptr r_tickptr;
ccd4a219 4697
255e1fcb 4698 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 4699 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4700 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4701 offsetof(CPUSPARCState, hstick));
46bb0137
MCA		 4702 if (tb_cflags(dc->base.tb) &
4703 CF_USE_ICOUNT) {
4704 gen_io_start();
4705 }
a7812ae4
PB		 4706 gen_helper_tick_set_limit(r_tickptr,
4707 cpu_hstick_cmpr);
4708 tcg_temp_free_ptr(r_tickptr);
46bb0137
MCA		 4709 if (tb_cflags(dc->base.tb) &
4710 CF_USE_ICOUNT) {
4711 gen_io_end();
4712 }
4713 /* End TB to handle timer interrupt */
4714 dc->base.is_jmp = DISAS_EXIT;
ccd4a219 4715 }
e9ebed4d
BS		 4716 break;
4717 case 6: // hver readonly
4718 default:
4719 goto illegal_insn;
4720 }
4721#endif
e8af50a3
FB		 4722 }
4723 break;
4724#endif
3475187d 4725#ifdef TARGET_SPARC64
0f8a249a
BS		 4726 case 0x2c: /* V9 movcc */
4727 {
4728 int cc = GET_FIELD_SP(insn, 11, 12);
4729 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 4730 DisasCompare cmp;
97ea2859 4731 TCGv dst;
00f219bf 4732
0f8a249a 4733 if (insn & (1 << 18)) {
f52879b4
RH		 4734 if (cc == 0) {
4735 gen_compare(&cmp, 0, cond, dc);
4736 } else if (cc == 2) {
4737 gen_compare(&cmp, 1, cond, dc);
4738 } else {
0f8a249a 4739 goto illegal_insn;
f52879b4 4740 }
0f8a249a 4741 } else {
f52879b4 4742 gen_fcompare(&cmp, cc, cond);
0f8a249a 4743 }
00f219bf 4744
f52879b4
RH		 4745 /* The get_src2 above loaded the normal 13-bit
4746 immediate field, not the 11-bit field we have
4747 in movcc. But it did handle the reg case. */
4748 if (IS_IMM) {
67526b20 4749 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 4750 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 4751 }
f52879b4 4752
97ea2859
RH		 4753 dst = gen_load_gpr(dc, rd);
4754 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 4755 cmp.c1, cmp.c2,
97ea2859 4756 cpu_src2, dst);
f52879b4 4757 free_compare(&cmp);
97ea2859 4758 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4759 break;
4760 }
4761 case 0x2d: /* V9 sdivx */
c28ae41e 4762 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 4763 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 4764 break;
4765 case 0x2e: /* V9 popc */
08da3180 4766 tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
97ea2859
RH		 4767 gen_store_gpr(dc, rd, cpu_dst);
4768 break;
0f8a249a
BS		 4769 case 0x2f: /* V9 movr */
4770 {
4771 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 4772 DisasCompare cmp;
97ea2859 4773 TCGv dst;
00f219bf 4774
c33f80f5 4775 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4776
c33f80f5
RH		 4777 /* The get_src2 above loaded the normal 13-bit
4778 immediate field, not the 10-bit field we have
4779 in movr. But it did handle the reg case. */
4780 if (IS_IMM) {
67526b20 4781 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4782 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4783 }
c33f80f5 4784
97ea2859
RH		 4785 dst = gen_load_gpr(dc, rd);
4786 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4787 cmp.c1, cmp.c2,
97ea2859 4788 cpu_src2, dst);
c33f80f5 4789 free_compare(&cmp);
97ea2859 4790 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4791 break;
4792 }
4793#endif
4794 default:
4795 goto illegal_insn;
4796 }
4797 }
3299908c
BS		 4798 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4799#ifdef TARGET_SPARC64
4800 int opf = GET_FIELD_SP(insn, 5, 13);
4801 rs1 = GET_FIELD(insn, 13, 17);
4802 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4803 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4804 goto jmp_insn;
5b12f1e8 4805 }
3299908c
BS		 4806
4807 switch (opf) {
e9ebed4d 4808 case 0x000: /* VIS I edge8cc */
6c073553 4809 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4810 cpu_src1 = gen_load_gpr(dc, rs1);
4811 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4812 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4813 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4814 break;
e9ebed4d 4815 case 0x001: /* VIS II edge8n */
6c073553 4816 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4817 cpu_src1 = gen_load_gpr(dc, rs1);
4818 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4819 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4820 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4821 break;
e9ebed4d 4822 case 0x002: /* VIS I edge8lcc */
6c073553 4823 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4824 cpu_src1 = gen_load_gpr(dc, rs1);
4825 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4826 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4827 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4828 break;
e9ebed4d 4829 case 0x003: /* VIS II edge8ln */
6c073553 4830 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4831 cpu_src1 = gen_load_gpr(dc, rs1);
4832 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4833 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4834 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4835 break;
e9ebed4d 4836 case 0x004: /* VIS I edge16cc */
6c073553 4837 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4838 cpu_src1 = gen_load_gpr(dc, rs1);
4839 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4840 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4841 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4842 break;
e9ebed4d 4843 case 0x005: /* VIS II edge16n */
6c073553 4844 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4845 cpu_src1 = gen_load_gpr(dc, rs1);
4846 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4847 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4848 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4849 break;
e9ebed4d 4850 case 0x006: /* VIS I edge16lcc */
6c073553 4851 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4852 cpu_src1 = gen_load_gpr(dc, rs1);
4853 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4854 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4855 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4856 break;
e9ebed4d 4857 case 0x007: /* VIS II edge16ln */
6c073553 4858 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4859 cpu_src1 = gen_load_gpr(dc, rs1);
4860 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4861 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4862 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4863 break;
e9ebed4d 4864 case 0x008: /* VIS I edge32cc */
6c073553 4865 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4866 cpu_src1 = gen_load_gpr(dc, rs1);
4867 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4868 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4869 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4870 break;
e9ebed4d 4871 case 0x009: /* VIS II edge32n */
6c073553 4872 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4873 cpu_src1 = gen_load_gpr(dc, rs1);
4874 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4875 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4876 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4877 break;
e9ebed4d 4878 case 0x00a: /* VIS I edge32lcc */
6c073553 4879 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4880 cpu_src1 = gen_load_gpr(dc, rs1);
4881 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4882 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4883 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4884 break;
e9ebed4d 4885 case 0x00b: /* VIS II edge32ln */
6c073553 4886 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4887 cpu_src1 = gen_load_gpr(dc, rs1);
4888 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4889 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4890 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4891 break;
e9ebed4d 4892 case 0x010: /* VIS I array8 */
64a88d5d 4893 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4894 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4895 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4896 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4897 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4898 break;
4899 case 0x012: /* VIS I array16 */
64a88d5d 4900 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4901 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4902 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4903 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4904 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4905 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4906 break;
4907 case 0x014: /* VIS I array32 */
64a88d5d 4908 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4909 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4910 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4911 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4912 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4913 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4914 break;
3299908c 4915 case 0x018: /* VIS I alignaddr */
64a88d5d 4916 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4917 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4918 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4919 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4920 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4921 break;
4922 case 0x01a: /* VIS I alignaddrl */
add545ab 4923 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4924 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4925 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4926 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4927 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4928 break;
4929 case 0x019: /* VIS II bmask */
793a137a 4930 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4931 cpu_src1 = gen_load_gpr(dc, rs1);
4932 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4933 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4934 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4935 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4936 break;
e9ebed4d 4937 case 0x020: /* VIS I fcmple16 */
64a88d5d 4938 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4939 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4940 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4941 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4942 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4943 break;
4944 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4945 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4946 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4947 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4948 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4949 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4950 break;
e9ebed4d 4951 case 0x024: /* VIS I fcmple32 */
64a88d5d 4952 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4953 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4954 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4955 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4956 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4957 break;
4958 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4959 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4960 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4961 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4962 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4963 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4964 break;
4965 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4966 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4967 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4968 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4969 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4970 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4971 break;
4972 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4973 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4974 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4975 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4976 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4977 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4978 break;
4979 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4980 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4981 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4982 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4983 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4984 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4985 break;
4986 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4987 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4988 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4989 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4990 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4991 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4992 break;
4993 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4994 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4995 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4996 break;
4997 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4998 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4999 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 5000 break;
5001 case 0x035: /* VIS I fmul8x16al */
64a88d5d 5002 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5003 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 5004 break;
5005 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 5006 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5007 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 5008 break;
5009 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 5010 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5011 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 5012 break;
5013 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 5014 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5015 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 5016 break;
5017 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 5018 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5019 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 5020 break;
5021 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 5022 CHECK_FPU_FEATURE(dc, VIS1);
5023 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
5024 break;
e9ebed4d 5025 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 5026 CHECK_FPU_FEATURE(dc, VIS1);
5027 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 5028 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 5029 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
5030 gen_store_fpr_F(dc, rd, cpu_dst_32);
5031 break;
e9ebed4d 5032 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 5033 CHECK_FPU_FEATURE(dc, VIS1);
5034 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 5035 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 5036 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
5037 gen_store_fpr_F(dc, rd, cpu_dst_32);
5038 break;
f888300b
RH		 5039 case 0x03e: /* VIS I pdist */
5040 CHECK_FPU_FEATURE(dc, VIS1);
5041 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
5042 break;
3299908c 5043 case 0x048: /* VIS I faligndata */
64a88d5d 5044 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 5045 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 5046 break;
e9ebed4d 5047 case 0x04b: /* VIS I fpmerge */
64a88d5d 5048 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5049 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 5050 break;
5051 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 5052 CHECK_FPU_FEATURE(dc, VIS2);
5053 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
5054 break;
e9ebed4d 5055 case 0x04d: /* VIS I fexpand */
64a88d5d 5056 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5057 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 5058 break;
5059 case 0x050: /* VIS I fpadd16 */
64a88d5d 5060 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5061 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 5062 break;
5063 case 0x051: /* VIS I fpadd16s */
64a88d5d 5064 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5065 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 5066 break;
5067 case 0x052: /* VIS I fpadd32 */
64a88d5d 5068 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5069 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 5070 break;
5071 case 0x053: /* VIS I fpadd32s */
64a88d5d 5072 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5073 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 5074 break;
5075 case 0x054: /* VIS I fpsub16 */
64a88d5d 5076 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5077 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 5078 break;
5079 case 0x055: /* VIS I fpsub16s */
64a88d5d 5080 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5081 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 5082 break;
5083 case 0x056: /* VIS I fpsub32 */
64a88d5d 5084 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5085 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 5086 break;
5087 case 0x057: /* VIS I fpsub32s */
64a88d5d 5088 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5089 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 5090 break;
3299908c 5091 case 0x060: /* VIS I fzero */
64a88d5d 5092 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5093 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5094 tcg_gen_movi_i64(cpu_dst_64, 0);
5095 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5096 break;
5097 case 0x061: /* VIS I fzeros */
64a88d5d 5098 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5099 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5100 tcg_gen_movi_i32(cpu_dst_32, 0);
5101 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5102 break;
e9ebed4d 5103 case 0x062: /* VIS I fnor */
64a88d5d 5104 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5105 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 5106 break;
5107 case 0x063: /* VIS I fnors */
64a88d5d 5108 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5109 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 5110 break;
5111 case 0x064: /* VIS I fandnot2 */
64a88d5d 5112 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5113 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 5114 break;
5115 case 0x065: /* VIS I fandnot2s */
64a88d5d 5116 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5117 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 5118 break;
5119 case 0x066: /* VIS I fnot2 */
64a88d5d 5120 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5121 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 5122 break;
5123 case 0x067: /* VIS I fnot2s */
64a88d5d 5124 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5125 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 5126 break;
5127 case 0x068: /* VIS I fandnot1 */
64a88d5d 5128 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5129 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 5130 break;
5131 case 0x069: /* VIS I fandnot1s */
64a88d5d 5132 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5133 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 5134 break;
5135 case 0x06a: /* VIS I fnot1 */
64a88d5d 5136 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5137 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 5138 break;
5139 case 0x06b: /* VIS I fnot1s */
64a88d5d 5140 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5141 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 5142 break;
5143 case 0x06c: /* VIS I fxor */
64a88d5d 5144 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5145 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 5146 break;
5147 case 0x06d: /* VIS I fxors */
64a88d5d 5148 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5149 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 5150 break;
5151 case 0x06e: /* VIS I fnand */
64a88d5d 5152 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5153 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 5154 break;
5155 case 0x06f: /* VIS I fnands */
64a88d5d 5156 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5157 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 5158 break;
5159 case 0x070: /* VIS I fand */
64a88d5d 5160 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5161 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 5162 break;
5163 case 0x071: /* VIS I fands */
64a88d5d 5164 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5165 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 5166 break;
5167 case 0x072: /* VIS I fxnor */
64a88d5d 5168 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5169 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 5170 break;
5171 case 0x073: /* VIS I fxnors */
64a88d5d 5172 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5173 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 5174 break;
3299908c 5175 case 0x074: /* VIS I fsrc1 */
64a88d5d 5176 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5177 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5178 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5179 break;
5180 case 0x075: /* VIS I fsrc1s */
64a88d5d 5181 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5182 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5183 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5184 break;
e9ebed4d 5185 case 0x076: /* VIS I fornot2 */
64a88d5d 5186 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5187 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 5188 break;
5189 case 0x077: /* VIS I fornot2s */
64a88d5d 5190 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5191 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 5192 break;
3299908c 5193 case 0x078: /* VIS I fsrc2 */
64a88d5d 5194 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5195 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5196 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5197 break;
5198 case 0x079: /* VIS I fsrc2s */
64a88d5d 5199 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5200 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5201 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5202 break;
e9ebed4d 5203 case 0x07a: /* VIS I fornot1 */
64a88d5d 5204 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5205 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 5206 break;
5207 case 0x07b: /* VIS I fornot1s */
64a88d5d 5208 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5209 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 5210 break;
5211 case 0x07c: /* VIS I for */
64a88d5d 5212 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5213 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 5214 break;
5215 case 0x07d: /* VIS I fors */
64a88d5d 5216 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5217 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 5218 break;
3299908c 5219 case 0x07e: /* VIS I fone */
64a88d5d 5220 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5221 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5222 tcg_gen_movi_i64(cpu_dst_64, -1);
5223 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5224 break;
5225 case 0x07f: /* VIS I fones */
64a88d5d 5226 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5227 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5228 tcg_gen_movi_i32(cpu_dst_32, -1);
5229 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5230 break;
e9ebed4d
BS		 5231 case 0x080: /* VIS I shutdown */
5232 case 0x081: /* VIS II siam */
5233 // XXX
5234 goto illegal_insn;
3299908c
BS		 5235 default:
5236 goto illegal_insn;
5237 }
5238#else
0f8a249a 5239 goto ncp_insn;
3299908c
BS		 5240#endif
5241 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 5242#ifdef TARGET_SPARC64
0f8a249a 5243 goto illegal_insn;
fcc72045 5244#else
0f8a249a 5245 goto ncp_insn;
fcc72045 5246#endif
3475187d 5247#ifdef TARGET_SPARC64
0f8a249a 5248 } else if (xop == 0x39) { /* V9 return */
66442b07 5249 save_state(dc);
9d1d4e34 5250 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5251 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5252 if (IS_IMM) { /* immediate */
67526b20 5253 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5254 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5255 } else { /* register */
3475187d 5256 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5257 if (rs2) {
97ea2859 5258 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5259 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5260 } else {
7b04bd5c 5261 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5262 }
3475187d 5263 }
063c3675 5264 gen_helper_restore(cpu_env);
13a6dd00 5265 gen_mov_pc_npc(dc);
35e94905 5266 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5267 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5268 dc->npc = DYNAMIC_PC;
5269 goto jmp_insn;
3475187d 5270#endif
0f8a249a 5271 } else {
9d1d4e34 5272 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5273 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5274 if (IS_IMM) { /* immediate */
67526b20 5275 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5276 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5277 } else { /* register */
e80cfcfc 5278 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5279 if (rs2) {
97ea2859 5280 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5281 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5282 } else {
7b04bd5c 5283 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5284 }
cf495bcf 5285 }
0f8a249a
BS		 5286 switch (xop) {
5287 case 0x38: /* jmpl */
5288 {
35e94905 5289 TCGv t = gen_dest_gpr(dc, rd);
97ea2859
RH		 5290 tcg_gen_movi_tl(t, dc->pc);
5291 gen_store_gpr(dc, rd, t);
35e94905 5292
13a6dd00 5293 gen_mov_pc_npc(dc);
35e94905 5294 gen_check_align(cpu_tmp0, 3);
7b04bd5c
RH		 5295 gen_address_mask(dc, cpu_tmp0);
5296 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5297 dc->npc = DYNAMIC_PC;
5298 }
5299 goto jmp_insn;
3475187d 5300#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 5301 case 0x39: /* rett, V9 return */
5302 {
5303 if (!supervisor(dc))
5304 goto priv_insn;
13a6dd00 5305 gen_mov_pc_npc(dc);
35e94905 5306 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5307 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 5308 dc->npc = DYNAMIC_PC;
063c3675 5309 gen_helper_rett(cpu_env);
0f8a249a
BS		 5310 }
5311 goto jmp_insn;
5312#endif
5313 case 0x3b: /* flush */
5578ceab 5314 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 5315 goto unimp_flush;
dcfd14b3 5316 /* nop */
0f8a249a
BS		 5317 break;
5318 case 0x3c: /* save */
063c3675 5319 gen_helper_save(cpu_env);
7b04bd5c 5320 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 5321 break;
5322 case 0x3d: /* restore */
063c3675 5323 gen_helper_restore(cpu_env);
7b04bd5c 5324 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 5325 break;
3475187d 5326#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 5327 case 0x3e: /* V9 done/retry */
5328 {
5329 switch (rd) {
5330 case 0:
5331 if (!supervisor(dc))
5332 goto priv_insn;
5333 dc->npc = DYNAMIC_PC;
5334 dc->pc = DYNAMIC_PC;
46bb0137
MCA		 5335 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
5336 gen_io_start();
5337 }
063c3675 5338 gen_helper_done(cpu_env);
46bb0137
MCA		 5339 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
5340 gen_io_end();
5341 }
0f8a249a
BS		 5342 goto jmp_insn;
5343 case 1:
5344 if (!supervisor(dc))
5345 goto priv_insn;
5346 dc->npc = DYNAMIC_PC;
5347 dc->pc = DYNAMIC_PC;
46bb0137
MCA		 5348 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
5349 gen_io_start();
5350 }
063c3675 5351 gen_helper_retry(cpu_env);
46bb0137
MCA		 5352 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
5353 gen_io_end();
5354 }
0f8a249a
BS		 5355 goto jmp_insn;
5356 default:
5357 goto illegal_insn;
5358 }
5359 }
5360 break;
5361#endif
5362 default:
5363 goto illegal_insn;
5364 }
cf495bcf 5365 }
0f8a249a
BS		 5366 break;
5367 }
5368 break;
5369 case 3: /* load/store instructions */
5370 {
5371 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 5372 /* ??? gen_address_mask prevents us from using a source
5373 register directly. Always generate a temporary. */
5374 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 5375
5e6ed439
RH		 5376 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5377 if (xop == 0x3c || xop == 0x3e) {
5378 /* V9 casa/casxa : no offset */
71817e48 5379 } else if (IS_IMM) { /* immediate */
67526b20 5380 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 5381 if (simm != 0) {
5382 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5383 }
0f8a249a
BS		 5384 } else { /* register */
5385 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5386 if (rs2 != 0) {
5e6ed439 5387 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 5388 }
0f8a249a 5389 }
2f2ecb83
BS		 5390 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5391 (xop > 0x17 && xop <= 0x1d ) ||
5392 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 5393 TCGv cpu_val = gen_dest_gpr(dc, rd);
5394
0f8a249a 5395 switch (xop) {
b89e94af 5396 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 5397 gen_address_mask(dc, cpu_addr);
6ae20372 5398 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5399 break;
b89e94af 5400 case 0x1: /* ldub, load unsigned byte */
2cade6a3 5401 gen_address_mask(dc, cpu_addr);
6ae20372 5402 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5403 break;
b89e94af 5404 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 5405 gen_address_mask(dc, cpu_addr);
6ae20372 5406 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5407 break;
b89e94af 5408 case 0x3: /* ldd, load double word */
0f8a249a 5409 if (rd & 1)
d4218d99 5410 goto illegal_insn;
1a2fb1c0 5411 else {
abcc7191 5412 TCGv_i64 t64;
2ea815ca 5413
2cade6a3 5414 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 5415 t64 = tcg_temp_new_i64();
5416 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 5417 tcg_gen_trunc_i64_tl(cpu_val, t64);
5418 tcg_gen_ext32u_tl(cpu_val, cpu_val);
5419 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 5420 tcg_gen_shri_i64(t64, t64, 32);
5421 tcg_gen_trunc_i64_tl(cpu_val, t64);
5422 tcg_temp_free_i64(t64);
de9e9d9f 5423 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 5424 }
0f8a249a 5425 break;
b89e94af 5426 case 0x9: /* ldsb, load signed byte */
2cade6a3 5427 gen_address_mask(dc, cpu_addr);
6ae20372 5428 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5429 break;
b89e94af 5430 case 0xa: /* ldsh, load signed halfword */
2cade6a3 5431 gen_address_mask(dc, cpu_addr);
6ae20372 5432 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5433 break;
fbb4bbb6
RH		 5434 case 0xd: /* ldstub */
5435 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5436 break;
de9e9d9f
RH		 5437 case 0x0f:
5438 /* swap, swap register with memory. Also atomically */
4fb554bc
RH		 5439 CHECK_IU_FEATURE(dc, SWAP);
5440 cpu_src1 = gen_load_gpr(dc, rd);
5441 gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5442 dc->mem_idx, MO_TEUL);
0f8a249a 5443 break;
3475187d 5444#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5445 case 0x10: /* lda, V9 lduwa, load word alternate */
1d65b0f5 5446 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
0f8a249a 5447 break;
b89e94af 5448 case 0x11: /* lduba, load unsigned byte alternate */
1d65b0f5 5449 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
0f8a249a 5450 break;
b89e94af 5451 case 0x12: /* lduha, load unsigned halfword alternate */
1d65b0f5 5452 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
0f8a249a 5453 break;
b89e94af 5454 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 5455 if (rd & 1) {
d4218d99 5456 goto illegal_insn;
7ec1e5ea 5457 }
e4dc0052 5458 gen_ldda_asi(dc, cpu_addr, insn, rd);
db166940 5459 goto skip_move;
b89e94af 5460 case 0x19: /* ldsba, load signed byte alternate */
1d65b0f5 5461 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
0f8a249a 5462 break;
b89e94af 5463 case 0x1a: /* ldsha, load signed halfword alternate */
1d65b0f5 5464 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
0f8a249a
BS		 5465 break;
5466 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 5467 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 5468 break;
b89e94af 5469 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 5470 atomically */
64a88d5d 5471 CHECK_IU_FEATURE(dc, SWAP);
06828032 5472 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 5473 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 5474 break;
3475187d
FB		 5475
5476#ifndef TARGET_SPARC64
0f8a249a
BS		 5477 case 0x30: /* ldc */
5478 case 0x31: /* ldcsr */
5479 case 0x33: /* lddc */
5480 goto ncp_insn;
3475187d
FB		 5481#endif
5482#endif
5483#ifdef TARGET_SPARC64
0f8a249a 5484 case 0x08: /* V9 ldsw */
2cade6a3 5485 gen_address_mask(dc, cpu_addr);
6ae20372 5486 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5487 break;
5488 case 0x0b: /* V9 ldx */
2cade6a3 5489 gen_address_mask(dc, cpu_addr);
6ae20372 5490 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5491 break;
5492 case 0x18: /* V9 ldswa */
1d65b0f5 5493 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
0f8a249a
BS		 5494 break;
5495 case 0x1b: /* V9 ldxa */
1d65b0f5 5496 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a
BS		 5497 break;
5498 case 0x2d: /* V9 prefetch, no effect */
5499 goto skip_move;
5500 case 0x30: /* V9 ldfa */
5b12f1e8 5501 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5502 goto jmp_insn;
5503 }
22e70060 5504 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
f9c816c0 5505 gen_update_fprs_dirty(dc, rd);
81ad8ba2 5506 goto skip_move;
0f8a249a 5507 case 0x33: /* V9 lddfa */
5b12f1e8 5508 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5509 goto jmp_insn;
5510 }
22e70060 5511 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
f9c816c0 5512 gen_update_fprs_dirty(dc, DFPREG(rd));
81ad8ba2 5513 goto skip_move;
0f8a249a
BS		 5514 case 0x3d: /* V9 prefetcha, no effect */
5515 goto skip_move;
5516 case 0x32: /* V9 ldqfa */
64a88d5d 5517 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5518 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5519 goto jmp_insn;
5520 }
22e70060 5521 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
f9c816c0 5522 gen_update_fprs_dirty(dc, QFPREG(rd));
1f587329 5523 goto skip_move;
0f8a249a
BS		 5524#endif
5525 default:
5526 goto illegal_insn;
5527 }
97ea2859 5528 gen_store_gpr(dc, rd, cpu_val);
db166940 5529#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 5530 skip_move: ;
3475187d 5531#endif
0f8a249a 5532 } else if (xop >= 0x20 && xop < 0x24) {
5b12f1e8 5533 if (gen_trap_ifnofpu(dc)) {
a80dde08 5534 goto jmp_insn;
5b12f1e8 5535 }
0f8a249a 5536 switch (xop) {
b89e94af 5537 case 0x20: /* ldf, load fpreg */
2cade6a3 5538 gen_address_mask(dc, cpu_addr);
ba5f5179 5539 cpu_dst_32 = gen_dest_fpr_F(dc);
cb21b4da
RH		 5540 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5541 dc->mem_idx, MO_TEUL);
208ae657 5542 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 5543 break;
3a3b925d
BS		 5544 case 0x21: /* ldfsr, V9 ldxfsr */
5545#ifdef TARGET_SPARC64
2cade6a3 5546 gen_address_mask(dc, cpu_addr);
3a3b925d 5547 if (rd == 1) {
abcc7191 5548 TCGv_i64 t64 = tcg_temp_new_i64();
cb21b4da
RH		 5549 tcg_gen_qemu_ld_i64(t64, cpu_addr,
5550 dc->mem_idx, MO_TEQ);
7385aed2 5551 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
abcc7191 5552 tcg_temp_free_i64(t64);
f8641947 5553 break;
fe987e23 5554 }
f8641947 5555#endif
de9e9d9f 5556 cpu_dst_32 = get_temp_i32(dc);
cb21b4da
RH		 5557 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5558 dc->mem_idx, MO_TEUL);
7385aed2 5559 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
0f8a249a 5560 break;
b89e94af 5561 case 0x22: /* ldqf, load quad fpreg */
f939ffe5
RH		 5562 CHECK_FPU_FEATURE(dc, FLOAT128);
5563 gen_address_mask(dc, cpu_addr);
5564 cpu_src1_64 = tcg_temp_new_i64();
cb21b4da
RH		 5565 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5566 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5567 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5568 cpu_src2_64 = tcg_temp_new_i64();
cb21b4da
RH		 5569 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
5570 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5571 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
5572 tcg_temp_free_i64(cpu_src1_64);
5573 tcg_temp_free_i64(cpu_src2_64);
1f587329 5574 break;
b89e94af 5575 case 0x23: /* lddf, load double fpreg */
03fb8cfc 5576 gen_address_mask(dc, cpu_addr);
3886b8a3 5577 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
cb21b4da
RH		 5578 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
5579 MO_TEQ | MO_ALIGN_4);
03fb8cfc 5580 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 5581 break;
5582 default:
5583 goto illegal_insn;
5584 }
dc1a6971 5585 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 5586 xop == 0xe || xop == 0x1e) {
81634eea
RH		 5587 TCGv cpu_val = gen_load_gpr(dc, rd);
5588
0f8a249a 5589 switch (xop) {
b89e94af 5590 case 0x4: /* st, store word */
2cade6a3 5591 gen_address_mask(dc, cpu_addr);
6ae20372 5592 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5593 break;
b89e94af 5594 case 0x5: /* stb, store byte */
2cade6a3 5595 gen_address_mask(dc, cpu_addr);
6ae20372 5596 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5597 break;
b89e94af 5598 case 0x6: /* sth, store halfword */
2cade6a3 5599 gen_address_mask(dc, cpu_addr);
6ae20372 5600 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5601 break;
b89e94af 5602 case 0x7: /* std, store double word */
0f8a249a 5603 if (rd & 1)
d4218d99 5604 goto illegal_insn;
1a2fb1c0 5605 else {
abcc7191 5606 TCGv_i64 t64;
81634eea 5607 TCGv lo;
1a2fb1c0 5608
2cade6a3 5609 gen_address_mask(dc, cpu_addr);
81634eea 5610 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5611 t64 = tcg_temp_new_i64();
5612 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
5613 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
5614 tcg_temp_free_i64(t64);
7fa76c0b 5615 }
0f8a249a 5616 break;
3475187d 5617#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5618 case 0x14: /* sta, V9 stwa, store word alternate */
1d65b0f5 5619 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
d39c0b99 5620 break;
b89e94af 5621 case 0x15: /* stba, store byte alternate */
1d65b0f5 5622 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
d39c0b99 5623 break;
b89e94af 5624 case 0x16: /* stha, store halfword alternate */
1d65b0f5 5625 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
d39c0b99 5626 break;
b89e94af 5627 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5628 if (rd & 1) {
0f8a249a 5629 goto illegal_insn;
1a2fb1c0 5630 }
7ec1e5ea 5631 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5632 break;
e80cfcfc 5633#endif
3475187d 5634#ifdef TARGET_SPARC64
0f8a249a 5635 case 0x0e: /* V9 stx */
2cade6a3 5636 gen_address_mask(dc, cpu_addr);
6ae20372 5637 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5638 break;
5639 case 0x1e: /* V9 stxa */
1d65b0f5 5640 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a 5641 break;
3475187d 5642#endif
0f8a249a
BS		 5643 default:
5644 goto illegal_insn;
5645 }
5646 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5647 if (gen_trap_ifnofpu(dc)) {
a80dde08 5648 goto jmp_insn;
5b12f1e8 5649 }
0f8a249a 5650 switch (xop) {
b89e94af 5651 case 0x24: /* stf, store fpreg */
cb21b4da
RH		 5652 gen_address_mask(dc, cpu_addr);
5653 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5654 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
5655 dc->mem_idx, MO_TEUL);
0f8a249a
BS		 5656 break;
5657 case 0x25: /* stfsr, V9 stxfsr */
f8641947 5658 {
3a3b925d 5659#ifdef TARGET_SPARC64
f8641947
RH		 5660 gen_address_mask(dc, cpu_addr);
5661 if (rd == 1) {
ba2397d1 5662 tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947
RH		 5663 break;
5664 }
3a3b925d 5665#endif
ba2397d1 5666 tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947 5667 }
0f8a249a 5668 break;
1f587329
BS		 5669 case 0x26:
5670#ifdef TARGET_SPARC64
1f587329 5671 /* V9 stqf, store quad fpreg */
f939ffe5
RH		 5672 CHECK_FPU_FEATURE(dc, FLOAT128);
5673 gen_address_mask(dc, cpu_addr);
5674 /* ??? While stqf only requires 4-byte alignment, it is
5675 legal for the cpu to signal the unaligned exception.
5676 The OS trap handler is then required to fix it up.
5677 For qemu, this avoids having to probe the second page
5678 before performing the first write. */
5679 cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5680 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5681 dc->mem_idx, MO_TEQ | MO_ALIGN_16);
5682 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5683 cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5684 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5685 dc->mem_idx, MO_TEQ);
1f587329 5686 break;
1f587329
BS		 5687#else /* !TARGET_SPARC64 */
5688 /* stdfq, store floating point queue */
5689#if defined(CONFIG_USER_ONLY)
5690 goto illegal_insn;
5691#else
0f8a249a
BS		 5692 if (!supervisor(dc))
5693 goto priv_insn;
5b12f1e8 5694 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5695 goto jmp_insn;
5b12f1e8 5696 }
0f8a249a 5697 goto nfq_insn;
1f587329 5698#endif
0f8a249a 5699#endif
b89e94af 5700 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5701 gen_address_mask(dc, cpu_addr);
5702 cpu_src1_64 = gen_load_fpr_D(dc, rd);
cb21b4da
RH		 5703 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5704 MO_TEQ | MO_ALIGN_4);
0f8a249a
BS		 5705 break;
5706 default:
5707 goto illegal_insn;
5708 }
5709 } else if (xop > 0x33 && xop < 0x3f) {
5710 switch (xop) {
a4d17f19 5711#ifdef TARGET_SPARC64
0f8a249a 5712 case 0x34: /* V9 stfa */
5b12f1e8 5713 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5714 goto jmp_insn;
5715 }
22e70060 5716 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5717 break;
1f587329 5718 case 0x36: /* V9 stqfa */
2ea815ca 5719 {
2ea815ca 5720 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5721 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5722 goto jmp_insn;
5723 }
22e70060 5724 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5725 }
1f587329 5726 break;
0f8a249a 5727 case 0x37: /* V9 stdfa */
5b12f1e8 5728 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5729 goto jmp_insn;
5730 }
22e70060 5731 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5732 break;
0f8a249a 5733 case 0x3e: /* V9 casxa */
a4273524
RH		 5734 rs2 = GET_FIELD(insn, 27, 31);
5735 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5736 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5737 break;
a4d17f19 5738#else
0f8a249a
BS		 5739 case 0x34: /* stc */
5740 case 0x35: /* stcsr */
5741 case 0x36: /* stdcq */
5742 case 0x37: /* stdc */
5743 goto ncp_insn;
16c358e9
SH		 5744#endif
5745#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5746 case 0x3c: /* V9 or LEON3 casa */
5747#ifndef TARGET_SPARC64
5748 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5749#endif
5750 rs2 = GET_FIELD(insn, 27, 31);
5751 cpu_src2 = gen_load_gpr(dc, rs2);
5752 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5753 break;
0f8a249a
BS		 5754#endif
5755 default:
5756 goto illegal_insn;
5757 }
a4273524 5758 } else {
0f8a249a 5759 goto illegal_insn;
a4273524 5760 }
0f8a249a
BS		 5761 }
5762 break;
cf495bcf
FB		 5763 }
5764 /* default case for non jump instructions */
72cbca10 5765 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5766 dc->pc = DYNAMIC_PC;
5767 gen_op_next_insn();
72cbca10
FB		 5768 } else if (dc->npc == JUMP_PC) {
5769 /* we can do a static jump */
6ae20372 5770 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
af00be49 5771 dc->base.is_jmp = DISAS_NORETURN;
72cbca10 5772 } else {
0f8a249a
BS		 5773 dc->pc = dc->npc;
5774 dc->npc = dc->npc + 4;
cf495bcf 5775 }
e80cfcfc 5776 jmp_insn:
42a8aa83 5777 goto egress;
cf495bcf 5778 illegal_insn:
4fbe0067 5779 gen_exception(dc, TT_ILL_INSN);
42a8aa83 5780 goto egress;
64a88d5d 5781 unimp_flush:
4fbe0067 5782 gen_exception(dc, TT_UNIMP_FLUSH);
42a8aa83 5783 goto egress;
e80cfcfc 5784#if !defined(CONFIG_USER_ONLY)
e8af50a3 5785 priv_insn:
4fbe0067 5786 gen_exception(dc, TT_PRIV_INSN);
42a8aa83 5787 goto egress;
64a88d5d 5788#endif
e80cfcfc 5789 nfpu_insn:
4fbe0067 5790 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
42a8aa83 5791 goto egress;
64a88d5d 5792#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5793 nfq_insn:
4fbe0067 5794 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
42a8aa83 5795 goto egress;
9143e598 5796#endif
fcc72045
BS		 5797#ifndef TARGET_SPARC64
5798 ncp_insn:
4fbe0067 5799 gen_exception(dc, TT_NCP_INSN);
42a8aa83 5800 goto egress;
fcc72045 5801#endif
42a8aa83 5802 egress:
30038fd8
RH		 5803 if (dc->n_t32 != 0) {
5804 int i;
5805 for (i = dc->n_t32 - 1; i >= 0; --i) {
5806 tcg_temp_free_i32(dc->t32[i]);
5807 }
5808 dc->n_t32 = 0;
5809 }
88023616
RH		 5810 if (dc->n_ttl != 0) {
5811 int i;
5812 for (i = dc->n_ttl - 1; i >= 0; --i) {
5813 tcg_temp_free(dc->ttl[i]);
5814 }
5815 dc->n_ttl = 0;
5816 }
7a3f1944
FB		 5817}
5818
6e61bc94 5819static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7a3f1944 5820{
6e61bc94 5821 DisasContext *dc = container_of(dcbase, DisasContext, base);
9c489ea6 5822 CPUSPARCState *env = cs->env_ptr;
6e61bc94 5823 int bound;
af00be49
EC		 5824
5825 dc->pc = dc->base.pc_first;
6e61bc94 5826 dc->npc = (target_ulong)dc->base.tb->cs_base;
8393617c 5827 dc->cc_op = CC_OP_DYNAMIC;
6e61bc94 5828 dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
576e1c4c 5829 dc->def = &env->def;
6e61bc94
EC		 5830 dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
5831 dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
c9b459aa 5832#ifndef CONFIG_USER_ONLY
6e61bc94 5833 dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
c9b459aa 5834#endif
a6d567e5 5835#ifdef TARGET_SPARC64
f9c816c0 5836 dc->fprs_dirty = 0;
6e61bc94 5837 dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
c9b459aa 5838#ifndef CONFIG_USER_ONLY
6e61bc94 5839 dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
c9b459aa 5840#endif
a6d567e5 5841#endif
6e61bc94
EC		 5842 /*
5843 * if we reach a page boundary, we stop generation so that the
5844 * PC of a TT_TFAULT exception is always in the right page
5845 */
5846 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
5847 dc->base.max_insns = MIN(dc->base.max_insns, bound);
5848}
cf495bcf 5849
6e61bc94
EC		 5850static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
5851{
5852}
190ce7fb 5853
6e61bc94
EC		 5854static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
5855{
5856 DisasContext *dc = container_of(dcbase, DisasContext, base);
667b8e29 5857
6e61bc94
EC		 5858 if (dc->npc & JUMP_PC) {
5859 assert(dc->jump_pc[1] == dc->pc + 4);
5860 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5861 } else {
5862 tcg_gen_insn_start(dc->pc, dc->npc);
5863 }
5864}
b933066a 5865
6e61bc94
EC		 5866static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
5867 const CPUBreakpoint *bp)
5868{
5869 DisasContext *dc = container_of(dcbase, DisasContext, base);
667b8e29 5870
6e61bc94
EC		 5871 if (dc->pc != dc->base.pc_first) {
5872 save_state(dc);
5873 }
5874 gen_helper_debug(cpu_env);
07ea28b4 5875 tcg_gen_exit_tb(NULL, 0);
6e61bc94
EC		 5876 dc->base.is_jmp = DISAS_NORETURN;
5877 /* update pc_next so that the current instruction is included in tb->size */
5878 dc->base.pc_next += 4;
5879 return true;
5880}
b09b2fd3 5881
6e61bc94
EC		 5882static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
5883{
5884 DisasContext *dc = container_of(dcbase, DisasContext, base);
5885 CPUSPARCState *env = cs->env_ptr;
5886 unsigned int insn;
0f8a249a 5887
b89b9001 5888 insn = translator_ldl(env, dc->pc);
6e61bc94
EC		 5889 dc->base.pc_next += 4;
5890 disas_sparc_insn(dc, insn);
e80cfcfc 5891
6e61bc94
EC		 5892 if (dc->base.is_jmp == DISAS_NORETURN) {
5893 return;
5894 }
5895 if (dc->pc != dc->base.pc_next) {
5896 dc->base.is_jmp = DISAS_TOO_MANY;
b09b2fd3 5897 }
6e61bc94
EC		 5898}
5899
5900static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
5901{
5902 DisasContext *dc = container_of(dcbase, DisasContext, base);
5903
46bb0137
MCA		 5904 switch (dc->base.is_jmp) {
5905 case DISAS_NEXT:
5906 case DISAS_TOO_MANY:
5fafdf24 5907 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5908 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5909 /* static PC and NPC: we can use direct chaining */
2f5680ee 5910 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5911 } else {
b09b2fd3 5912 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5913 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5914 }
934da7ee 5915 save_npc(dc);
07ea28b4 5916 tcg_gen_exit_tb(NULL, 0);
72cbca10 5917 }
46bb0137
MCA		 5918 break;
5919
5920 case DISAS_NORETURN:
5921 break;
5922
5923 case DISAS_EXIT:
5924 /* Exit TB */
5925 save_state(dc);
5926 tcg_gen_exit_tb(NULL, 0);
5927 break;
5928
5929 default:
5930 g_assert_not_reached();
72cbca10 5931 }
6e61bc94
EC		 5932}
5933
5934static void sparc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
5935{
5936 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
5937 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
5938}
5939
5940static const TranslatorOps sparc_tr_ops = {
5941 .init_disas_context = sparc_tr_init_disas_context,
5942 .tb_start = sparc_tr_tb_start,
5943 .insn_start = sparc_tr_insn_start,
5944 .breakpoint_check = sparc_tr_breakpoint_check,
5945 .translate_insn = sparc_tr_translate_insn,
5946 .tb_stop = sparc_tr_tb_stop,
5947 .disas_log = sparc_tr_disas_log,
5948};
5949
8b86d6d2 5950void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
6e61bc94
EC		 5951{
5952 DisasContext dc = {};
5953
8b86d6d2 5954 translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns);
7a3f1944
FB		 5955}
5956
55c3ceef 5957void sparc_tcg_init(void)
e80cfcfc 5958{
d2dc4069 5959 static const char gregnames[32][4] = {
0ea63844 5960 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5961 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5962 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5963 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5964 };
0ea63844 5965 static const char fregnames[32][4] = {
30038fd8
RH		 5966 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5967 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5968 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5969 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5970 };
aaed909a 5971
0ea63844 5972 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5973#ifdef TARGET_SPARC64
0ea63844 5974 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5975 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
255e1fcb 5976#else
0ea63844
RH		 5977 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5978#endif
5979 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5980 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5981 };
5982
5983 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5984#ifdef TARGET_SPARC64
5985 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5986 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5987 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5988 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5989 "hstick_cmpr" },
5990 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5991 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5992 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5993 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5994 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5995#endif
0ea63844
RH		 5996 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5997 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5998 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5999 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
6000 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
6001 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
6002 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
6003 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 6004#ifndef CONFIG_USER_ONLY
0ea63844 6005 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 6006#endif
0ea63844
RH		 6007 };
6008
6009 unsigned int i;
6010
0ea63844
RH		 6011 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
6012 offsetof(CPUSPARCState, regwptr),
6013 "regwptr");
6014
6015 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
6016 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
6017 }
6018
6019 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
6020 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
6021 }
6022
f764718d 6023 cpu_regs[0] = NULL;
0ea63844 6024 for (i = 1; i < 8; ++i) {
d2dc4069
RH		 6025 cpu_regs[i] = tcg_global_mem_new(cpu_env,
6026 offsetof(CPUSPARCState, gregs[i]),
6027 gregnames[i]);
6028 }
6029
6030 for (i = 8; i < 32; ++i) {
6031 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
6032 (i - 8) * sizeof(target_ulong),
6033 gregnames[i]);
0ea63844
RH		 6034 }
6035
6036 for (i = 0; i < TARGET_DPREGS; i++) {
6037 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
6038 offsetof(CPUSPARCState, fpr[i]),
6039 fregnames[i]);
1a2fb1c0 6040 }
658138bc 6041}
d2856f1a 6042
bad729e2
RH		 6043void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
6044 target_ulong *data)
d2856f1a 6045{
bad729e2
RH		 6046 target_ulong pc = data[0];
6047 target_ulong npc = data[1];
6048
6049 env->pc = pc;
6c42444f 6050 if (npc == DYNAMIC_PC) {
d2856f1a 6051 /* dynamic NPC: already stored */
6c42444f 6052 } else if (npc & JUMP_PC) {
d7da2a10
BS		 6053 /* jump PC: use 'cond' and the jump targets of the translation */
6054 if (env->cond) {
6c42444f 6055 env->npc = npc & ~3;
d7da2a10 6056 } else {
6c42444f 6057 env->npc = pc + 4;
d7da2a10 6058 }
d2856f1a
AJ		 6059 } else {
6060 env->npc = npc;
6061 }
6062}
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