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tools/envcrc: add --binary option to export embedded env
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887e2ec9 1/*
5132106a 2 * (C) Copyright 2006-2009
887e2ec9
SR
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
865f0f97 7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9
SR
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
13628884
SR
26#include <libfdt.h>
27#include <fdt_support.h>
4fb25a3d 28#include <ppc4xx.h>
b05e8bf5 29#include <asm/gpio.h>
887e2ec9 30#include <asm/processor.h>
5a5958b7 31#include <asm/io.h>
83a49c8d 32#include <asm/bitops.h>
887e2ec9
SR
33
34DECLARE_GLOBAL_DATA_PTR;
35
6d0f6bcf 36extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
887e2ec9 37
5132106a
SR
38extern void __ft_board_setup(void *blob, bd_t *bd);
39ulong flash_get_size(ulong base, int banknum);
1b3c360c 40
887e2ec9
SR
41int board_early_init_f(void)
42{
a78bc443
SR
43 u32 sdr0_cust0;
44 u32 sdr0_pfc1, sdr0_pfc2;
45 u32 reg;
887e2ec9
SR
46
47 mtdcr(ebccfga, xbcfg);
48 mtdcr(ebccfgd, 0xb8400000);
49
83a49c8d 50 /*
887e2ec9 51 * Setup the interrupt controller polarities, triggers, etc.
83a49c8d 52 */
887e2ec9
SR
53 mtdcr(uic0sr, 0xffffffff); /* clear all */
54 mtdcr(uic0er, 0x00000000); /* disable all */
55 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
56 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
57 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
58 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
59 mtdcr(uic0sr, 0xffffffff); /* clear all */
60
61 mtdcr(uic1sr, 0xffffffff); /* clear all */
62 mtdcr(uic1er, 0x00000000); /* disable all */
63 mtdcr(uic1cr, 0x00000000); /* all non-critical */
64 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
65 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
66 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
67 mtdcr(uic1sr, 0xffffffff); /* clear all */
68
69 mtdcr(uic2sr, 0xffffffff); /* clear all */
70 mtdcr(uic2er, 0x00000000); /* disable all */
71 mtdcr(uic2cr, 0x00000000); /* all non-critical */
72 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
73 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
74 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
75 mtdcr(uic2sr, 0xffffffff); /* clear all */
76
77 /* 50MHz tmrclk */
6d0f6bcf 78 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
887e2ec9
SR
79
80 /* clear write protects */
6d0f6bcf 81 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
887e2ec9
SR
82
83 /* enable Ethernet */
6d0f6bcf 84 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
887e2ec9
SR
85
86 /* enable USB device */
6d0f6bcf 87 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
887e2ec9 88
b738654d 89 /* select Ethernet (and optionally IIC1) pins */
887e2ec9 90 mfsdr(SDR0_PFC1, sdr0_pfc1);
83a49c8d
MF
91 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
92 SDR0_PFC1_SELECT_CONFIG_4;
b738654d
MN
93#ifdef CONFIG_I2C_MULTI_BUS
94 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
95#endif
eab10073
SF
96 /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
97 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
98 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
99 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
100
887e2ec9 101 mfsdr(SDR0_PFC2, sdr0_pfc2);
83a49c8d
MF
102 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
103 SDR0_PFC2_SELECT_CONFIG_4;
887e2ec9
SR
104 mtsdr(SDR0_PFC2, sdr0_pfc2);
105 mtsdr(SDR0_PFC1, sdr0_pfc1);
106
107 /* PCI arbiter enabled */
108 mfsdr(sdr_pci0, reg);
109 mtsdr(sdr_pci0, 0x80000000 | reg);
110
111 /* setup NAND FLASH */
112 mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72 113 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
887e2ec9
SR
114 SDR0_CUST0_NDFC_ENABLE |
115 SDR0_CUST0_NDFC_BW_8_BIT |
116 SDR0_CUST0_NDFC_ARE_MASK |
6d0f6bcf 117 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
511d0c72 118 mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9
SR
119
120 return 0;
121}
122
887e2ec9
SR
123int misc_init_r(void)
124{
125 uint pbcr;
126 int size_val = 0;
a78bc443 127 u32 reg;
854bc8da 128#ifdef CONFIG_440EPX
887e2ec9
SR
129 unsigned long usb2d0cr = 0;
130 unsigned long usb2phy0cr, usb2h0cr = 0;
131 unsigned long sdr0_pfc1;
132 char *act = getenv("usbact");
854bc8da 133#endif
887e2ec9 134
83a49c8d 135 /* Re-do flash sizing to get full correct info */
1b3c360c
SR
136
137 /* adjust flash start and offset */
138 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
139 gd->bd->bi_flashoffset = 0;
140
887e2ec9
SR
141#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
142 mtdcr(ebccfga, pb3cr);
143#else
144 mtdcr(ebccfga, pb0cr);
145#endif
146 pbcr = mfdcr(ebccfgd);
865f0f97 147 size_val = ffs(gd->bd->bi_flashsize) - 21;
887e2ec9
SR
148 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
149#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
150 mtdcr(ebccfga, pb3cr);
151#else
152 mtdcr(ebccfga, pb0cr);
153#endif
154 mtdcr(ebccfgd, pbcr);
155
1b3c360c
SR
156 /*
157 * Re-check to get correct base address
158 */
159 flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9 160
5a1aceb0 161#ifdef CONFIG_ENV_IS_IN_FLASH
887e2ec9
SR
162 /* Monitor protection ON by default */
163 (void)flash_protect(FLAG_PROTECT_SET,
6d0f6bcf 164 -CONFIG_SYS_MONITOR_LEN,
887e2ec9
SR
165 0xffffffff,
166 &flash_info[0]);
167
168 /* Env protection ON by default */
169 (void)flash_protect(FLAG_PROTECT_SET,
0e8d1586
JCPV
170 CONFIG_ENV_ADDR_REDUND,
171 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
887e2ec9
SR
172 &flash_info[0]);
173#endif
174
175 /*
176 * USB suff...
177 */
854bc8da 178#ifdef CONFIG_440EPX
83a49c8d 179 if (act == NULL || strcmp(act, "hostdev") == 0) {
887e2ec9 180 /* SDR Setting */
511d0c72 181 mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 182 mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD
183 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
184 mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR
185
186 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 187 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 188 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 189 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
887e2ec9 190 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 191 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 192 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 193 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 194 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 195 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9 196
83a49c8d
MF
197 /*
198 * An 8-bit/60MHz interface is the only possible alternative
199 * when connecting the Device to the PHY
200 */
511d0c72 201 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 202 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
887e2ec9 203
83a49c8d
MF
204 /*
205 * To enable the USB 2.0 Device function
206 * through the UTMI interface
207 */
511d0c72 208 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 209 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
887e2ec9 210
511d0c72 211 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 212 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
887e2ec9 213
511d0c72 214 mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 215 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD
216 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
217 mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR
218
219 /*clear resets*/
220 udelay (1000);
221 mtsdr(SDR0_SRST1, 0x00000000);
222 udelay (1000);
223 mtsdr(SDR0_SRST0, 0x00000000);
224
225 printf("USB: Host(int phy) Device(ext phy)\n");
226
227 } else if (strcmp(act, "dev") == 0) {
228 /*-------------------PATCH-------------------------------*/
229 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
230
231 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 232 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
887e2ec9 233 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 234 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 235 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 236 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 237 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 238 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9
SR
239 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
240
241 udelay (1000);
242 mtsdr(SDR0_SRST1, 0x672c6000);
243
244 udelay (1000);
245 mtsdr(SDR0_SRST0, 0x00000080);
246
247 udelay (1000);
248 mtsdr(SDR0_SRST1, 0x60206000);
249
250 *(unsigned int *)(0xe0000350) = 0x00000001;
251
252 udelay (1000);
253 mtsdr(SDR0_SRST1, 0x60306000);
254 /*-------------------PATCH-------------------------------*/
255
256 /* SDR Setting */
511d0c72 257 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9 258 mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833 259 mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR
260 mfsdr(SDR0_PFC1, sdr0_pfc1);
261
262 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 263 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 264 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 265 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
887e2ec9 266 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 267 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
887e2ec9 268 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 269 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
887e2ec9 270 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 271 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
887e2ec9
SR
272
273 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 274 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
887e2ec9
SR
275
276 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 277 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
887e2ec9
SR
278
279 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 280 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
887e2ec9 281
511d0c72
WD
282 mtsdr(SDR0_USB2H0CR, usb2h0cr);
283 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833 284 mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR
285 mtsdr(SDR0_PFC1, sdr0_pfc1);
286
83a49c8d 287 /* clear resets */
887e2ec9
SR
288 udelay (1000);
289 mtsdr(SDR0_SRST1, 0x00000000);
290 udelay (1000);
291 mtsdr(SDR0_SRST0, 0x00000000);
292
293 printf("USB: Device(int phy)\n");
294 }
854bc8da 295#endif /* CONFIG_440EPX */
887e2ec9 296
8ce16f55
JO
297 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
298 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
299 mtsdr(SDR0_SRST1, reg);
300
a78bc443
SR
301 /*
302 * Clear PLB4A0_ACR[WRP]
303 * This fix will make the MAL burst disabling patch for the Linux
304 * EMAC driver obsolete.
305 */
306 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
307 mtdcr(plb4_acr, reg);
308
887e2ec9
SR
309 return 0;
310}
311
312int checkboard(void)
313{
314 char *s = getenv("serial#");
e0b9ea8c
SR
315 u8 rev;
316 u8 val;
887e2ec9 317
854bc8da 318#ifdef CONFIG_440EPX
887e2ec9 319 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da
SR
320#else
321 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
322#endif
e0b9ea8c 323
6d0f6bcf
JCPV
324 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
325 val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
e0b9ea8c
SR
326 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
327
887e2ec9
SR
328 if (s != NULL) {
329 puts(", serial# ");
330 puts(s);
331 }
332 putc('\n');
333
334 return (0);
335}
336
1f84021a
MF
337#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
338/*
339 * Assign interrupts to PCI devices.
340 */
341void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
342{
d1631fe1 343 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
1f84021a
MF
344}
345#endif
346
83a49c8d
MF
347/*
348 * pci_pre_init
887e2ec9 349 *
83a49c8d
MF
350 * This routine is called just prior to registering the hose and gives
351 * the board the opportunity to check things. Returning a value of zero
352 * indicates that things are bad & PCI initialization should be aborted.
887e2ec9 353 *
83a49c8d
MF
354 * Different boards may wish to customize the pci controller structure
355 * (add regions, override default access routines, etc) or perform
356 * certain pre-initialization actions.
357 */
466fff1a 358#if defined(CONFIG_PCI)
887e2ec9
SR
359int pci_pre_init(struct pci_controller *hose)
360{
361 unsigned long addr;
887e2ec9 362
83a49c8d
MF
363 /*
364 * Set priority for all PLB3 devices to 0.
365 * Set PLB3 arbiter to fair mode.
366 */
887e2ec9
SR
367 mfsdr(sdr_amp1, addr);
368 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
369 addr = mfdcr(plb3_acr);
370 mtdcr(plb3_acr, addr | 0x80000000);
371
83a49c8d
MF
372 /*
373 * Set priority for all PLB4 devices to 0.
374 */
887e2ec9
SR
375 mfsdr(sdr_amp0, addr);
376 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
377 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
378 mtdcr(plb4_acr, addr);
379
83a49c8d
MF
380 /*
381 * Set Nebula PLB4 arbiter to fair mode.
382 */
887e2ec9
SR
383 /* Segment0 */
384 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
385 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
386 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
387 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
388 mtdcr(plb0_acr, addr);
389
390 /* Segment1 */
391 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
392 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
393 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
394 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
395 mtdcr(plb1_acr, addr);
396
1f84021a
MF
397#ifdef CONFIG_PCI_PNP
398 hose->fixup_irq = sequoia_pci_fixup_irq;
399#endif
887e2ec9
SR
400 return 1;
401}
466fff1a 402#endif /* defined(CONFIG_PCI) */
887e2ec9 403
83a49c8d
MF
404/*
405 * pci_target_init
887e2ec9 406 *
83a49c8d
MF
407 * The bootstrap configuration provides default settings for the pci
408 * inbound map (PIM). But the bootstrap config choices are limited and
409 * may not be sufficient for a given board.
410 */
6d0f6bcf 411#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
887e2ec9
SR
412void pci_target_init(struct pci_controller *hose)
413{
83a49c8d 414 /*
887e2ec9 415 * Set up Direct MMIO registers
83a49c8d
MF
416 */
417 /*
418 * PowerPC440EPX PCI Master configuration.
419 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
420 * PLB address 0xA0000000-0xDFFFFFFF
421 * ==> PCI address 0xA0000000-0xDFFFFFFF
422 * Use byte reversed out routines to handle endianess.
423 * Make this region non-prefetchable.
424 */
425 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
426 /* - disabled b4 setting */
6d0f6bcf
JCPV
427 out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
428 out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
887e2ec9 429 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
83a49c8d
MF
430 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
431 /* and enable region */
887e2ec9 432
83a49c8d
MF
433 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
434 /* - disabled b4 setting */
6d0f6bcf
JCPV
435 out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
436 out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
887e2ec9 437 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
83a49c8d
MF
438 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
439 /* and enable region */
887e2ec9
SR
440
441 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
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MF
442 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
443 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
444 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
887e2ec9 445
83a49c8d 446 /*
887e2ec9 447 * Set up Configuration registers
83a49c8d 448 */
887e2ec9
SR
449
450 /* Program the board's subsystem id/vendor id */
451 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
6d0f6bcf
JCPV
452 CONFIG_SYS_PCI_SUBSYS_VENDORID);
453 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
887e2ec9
SR
454
455 /* Configure command register as bus master */
456 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
457
458 /* 240nS PCI clock */
459 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
460
461 /* No error reporting */
462 pci_write_config_word(0, PCI_ERREN, 0);
463
464 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
465
466}
6d0f6bcf 467#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
887e2ec9 468
6d0f6bcf 469#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
887e2ec9
SR
470void pci_master_init(struct pci_controller *hose)
471{
472 unsigned short temp_short;
473
83a49c8d
MF
474 /*
475 * Write the PowerPC440 EP PCI Configuration regs.
476 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
477 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
478 */
887e2ec9
SR
479 pci_read_config_word(0, PCI_COMMAND, &temp_short);
480 pci_write_config_word(0, PCI_COMMAND,
481 temp_short | PCI_COMMAND_MASTER |
482 PCI_COMMAND_MEMORY);
483}
6d0f6bcf 484#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
887e2ec9 485
83a49c8d
MF
486/*
487 * is_pci_host
887e2ec9 488 *
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MF
489 * This routine is called to determine if a pci scan should be
490 * performed. With various hardware environments (especially cPCI and
491 * PPMC) it's insufficient to depend on the state of the arbiter enable
492 * bit in the strap register, or generic host/adapter assumptions.
887e2ec9 493 *
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MF
494 * Rather than hard-code a bad assumption in the general 440 code, the
495 * 440 pci code requires the board to decide at runtime.
887e2ec9 496 *
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MF
497 * Return 0 for adapter mode, non-zero for host (monarch) mode.
498 */
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SR
499#if defined(CONFIG_PCI)
500int is_pci_host(struct pci_controller *hose)
501{
502 /* Cactus is always configured as host. */
503 return (1);
504}
83a49c8d
MF
505#endif /* defined(CONFIG_PCI) */
506
a11e0696
IL
507#if defined(CONFIG_POST)
508/*
509 * Returns 1 if keys pressed to start the power-on long-running tests
510 * Called from board_init_f().
511 */
512int post_hotkeys_pressed(void)
513{
514 return 0; /* No hotkeys supported */
515}
516#endif /* CONFIG_POST */
5132106a
SR
517
518#if defined(CONFIG_NAND_U_BOOT)
519/*
520 * On NAND-booting sequoia, we need to patch the chips select numbers
521 * in the dtb (CS0 - NAND, CS3 - NOR)
522 */
523void ft_board_setup(void *blob, bd_t *bd)
524{
525 int rc;
526 int len;
527 int nodeoffset;
528 struct fdt_property *prop;
529 u32 *reg;
530 char path[32];
531
532 /* First do common fdt setup */
533 __ft_board_setup(blob, bd);
534
535 /* And now configure NOR chip select to 3 instead of 0 */
536 strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
537 nodeoffset = fdt_path_offset(blob, path);
538 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
539 if (prop == NULL) {
540 printf("Unable to update NOR chip select for NAND booting\n");
541 return;
542 }
543 reg = (u32 *)&prop->data[0];
544 reg[0] = 3;
545 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
546 if (rc) {
547 printf("Unable to update property NOR mappings, err=%s\n",
548 fdt_strerror(rc));
549 return;
550 }
551
552 /* And now configure NAND chip select to 0 instead of 3 */
553 strcpy(path, "/plb/opb/ebc/ndfc@3,0");
554 nodeoffset = fdt_path_offset(blob, path);
555 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
556 if (prop == NULL) {
557 printf("Unable to update NDFC chip select for NAND booting\n");
558 return;
559 }
560 reg = (u32 *)&prop->data[0];
561 reg[0] = 0;
562 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
563 if (rc) {
564 printf("Unable to update property NDFC mappings, err=%s\n",
565 fdt_strerror(rc));
566 return;
567 }
568}
569#endif /* CONFIG_NAND_U_BOOT */