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887e2ec9 1/*
5132106a 2 * (C) Copyright 2006-2009
887e2ec9
SR
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
865f0f97 7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9
SR
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
13628884
SR
26#include <libfdt.h>
27#include <fdt_support.h>
4fb25a3d 28#include <ppc4xx.h>
b05e8bf5 29#include <asm/gpio.h>
887e2ec9 30#include <asm/processor.h>
5a5958b7 31#include <asm/io.h>
83a49c8d 32#include <asm/bitops.h>
887e2ec9
SR
33
34DECLARE_GLOBAL_DATA_PTR;
35
d873133f 36#if !defined(CONFIG_SYS_NO_FLASH)
6d0f6bcf 37extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
d873133f 38#endif
887e2ec9 39
5132106a
SR
40extern void __ft_board_setup(void *blob, bd_t *bd);
41ulong flash_get_size(ulong base, int banknum);
1b3c360c 42
887e2ec9
SR
43int board_early_init_f(void)
44{
a78bc443
SR
45 u32 sdr0_cust0;
46 u32 sdr0_pfc1, sdr0_pfc2;
47 u32 reg;
887e2ec9 48
d1c3b275
SR
49 mtdcr(EBC0_CFGADDR, EBC0_CFG);
50 mtdcr(EBC0_CFGDATA, 0xb8400000);
887e2ec9 51
83a49c8d 52 /*
887e2ec9 53 * Setup the interrupt controller polarities, triggers, etc.
83a49c8d 54 */
887e2ec9
SR
55 mtdcr(uic0sr, 0xffffffff); /* clear all */
56 mtdcr(uic0er, 0x00000000); /* disable all */
57 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
58 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
59 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
60 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
61 mtdcr(uic0sr, 0xffffffff); /* clear all */
62
63 mtdcr(uic1sr, 0xffffffff); /* clear all */
64 mtdcr(uic1er, 0x00000000); /* disable all */
65 mtdcr(uic1cr, 0x00000000); /* all non-critical */
66 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
67 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
68 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
69 mtdcr(uic1sr, 0xffffffff); /* clear all */
70
71 mtdcr(uic2sr, 0xffffffff); /* clear all */
72 mtdcr(uic2er, 0x00000000); /* disable all */
73 mtdcr(uic2cr, 0x00000000); /* all non-critical */
74 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
75 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
76 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
77 mtdcr(uic2sr, 0xffffffff); /* clear all */
78
79 /* 50MHz tmrclk */
6d0f6bcf 80 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
887e2ec9
SR
81
82 /* clear write protects */
6d0f6bcf 83 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
887e2ec9
SR
84
85 /* enable Ethernet */
6d0f6bcf 86 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
887e2ec9
SR
87
88 /* enable USB device */
6d0f6bcf 89 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
887e2ec9 90
b738654d 91 /* select Ethernet (and optionally IIC1) pins */
887e2ec9 92 mfsdr(SDR0_PFC1, sdr0_pfc1);
83a49c8d
MF
93 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
94 SDR0_PFC1_SELECT_CONFIG_4;
b738654d
MN
95#ifdef CONFIG_I2C_MULTI_BUS
96 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
97#endif
eab10073
SF
98 /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
99 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
100 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
101 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
102
887e2ec9 103 mfsdr(SDR0_PFC2, sdr0_pfc2);
83a49c8d
MF
104 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
105 SDR0_PFC2_SELECT_CONFIG_4;
887e2ec9
SR
106 mtsdr(SDR0_PFC2, sdr0_pfc2);
107 mtsdr(SDR0_PFC1, sdr0_pfc1);
108
109 /* PCI arbiter enabled */
d1c3b275
SR
110 mfsdr(SDR0_PCI0, reg);
111 mtsdr(SDR0_PCI0, 0x80000000 | reg);
887e2ec9
SR
112
113 /* setup NAND FLASH */
114 mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72 115 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
887e2ec9
SR
116 SDR0_CUST0_NDFC_ENABLE |
117 SDR0_CUST0_NDFC_BW_8_BIT |
118 SDR0_CUST0_NDFC_ARE_MASK |
6d0f6bcf 119 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
511d0c72 120 mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9
SR
121
122 return 0;
123}
124
887e2ec9
SR
125int misc_init_r(void)
126{
d873133f 127#if !defined(CONFIG_SYS_NO_FLASH)
887e2ec9
SR
128 uint pbcr;
129 int size_val = 0;
d873133f 130#endif
854bc8da 131#ifdef CONFIG_440EPX
887e2ec9
SR
132 unsigned long usb2d0cr = 0;
133 unsigned long usb2phy0cr, usb2h0cr = 0;
134 unsigned long sdr0_pfc1;
135 char *act = getenv("usbact");
854bc8da 136#endif
d873133f 137 u32 reg;
887e2ec9 138
d873133f 139#if !defined(CONFIG_SYS_NO_FLASH)
83a49c8d 140 /* Re-do flash sizing to get full correct info */
1b3c360c
SR
141
142 /* adjust flash start and offset */
143 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
144 gd->bd->bi_flashoffset = 0;
145
887e2ec9 146#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
d1c3b275 147 mtdcr(EBC0_CFGADDR, PB3CR);
887e2ec9 148#else
d1c3b275 149 mtdcr(EBC0_CFGADDR, PB0CR);
887e2ec9 150#endif
d1c3b275 151 pbcr = mfdcr(EBC0_CFGDATA);
865f0f97 152 size_val = ffs(gd->bd->bi_flashsize) - 21;
887e2ec9
SR
153 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
154#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
d1c3b275 155 mtdcr(EBC0_CFGADDR, PB3CR);
887e2ec9 156#else
d1c3b275 157 mtdcr(EBC0_CFGADDR, PB0CR);
887e2ec9 158#endif
d1c3b275 159 mtdcr(EBC0_CFGDATA, pbcr);
887e2ec9 160
1b3c360c
SR
161 /*
162 * Re-check to get correct base address
163 */
164 flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9 165
5a1aceb0 166#ifdef CONFIG_ENV_IS_IN_FLASH
887e2ec9
SR
167 /* Monitor protection ON by default */
168 (void)flash_protect(FLAG_PROTECT_SET,
6d0f6bcf 169 -CONFIG_SYS_MONITOR_LEN,
887e2ec9
SR
170 0xffffffff,
171 &flash_info[0]);
172
173 /* Env protection ON by default */
174 (void)flash_protect(FLAG_PROTECT_SET,
0e8d1586
JCPV
175 CONFIG_ENV_ADDR_REDUND,
176 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
887e2ec9
SR
177 &flash_info[0]);
178#endif
d873133f 179#endif /* CONFIG_SYS_NO_FLASH */
887e2ec9
SR
180
181 /*
182 * USB suff...
183 */
854bc8da 184#ifdef CONFIG_440EPX
83a49c8d 185 if (act == NULL || strcmp(act, "hostdev") == 0) {
887e2ec9 186 /* SDR Setting */
511d0c72 187 mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 188 mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD
189 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
190 mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR
191
192 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 193 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 194 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 195 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
887e2ec9 196 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 197 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 198 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 199 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 200 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 201 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9 202
83a49c8d
MF
203 /*
204 * An 8-bit/60MHz interface is the only possible alternative
205 * when connecting the Device to the PHY
206 */
511d0c72 207 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 208 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
887e2ec9 209
83a49c8d
MF
210 /*
211 * To enable the USB 2.0 Device function
212 * through the UTMI interface
213 */
511d0c72 214 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 215 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
887e2ec9 216
511d0c72 217 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 218 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
887e2ec9 219
511d0c72 220 mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 221 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD
222 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
223 mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR
224
225 /*clear resets*/
226 udelay (1000);
227 mtsdr(SDR0_SRST1, 0x00000000);
228 udelay (1000);
229 mtsdr(SDR0_SRST0, 0x00000000);
230
231 printf("USB: Host(int phy) Device(ext phy)\n");
232
233 } else if (strcmp(act, "dev") == 0) {
234 /*-------------------PATCH-------------------------------*/
235 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
236
237 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 238 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
887e2ec9 239 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 240 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 241 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 242 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 243 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 244 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9
SR
245 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
246
247 udelay (1000);
248 mtsdr(SDR0_SRST1, 0x672c6000);
249
250 udelay (1000);
251 mtsdr(SDR0_SRST0, 0x00000080);
252
253 udelay (1000);
254 mtsdr(SDR0_SRST1, 0x60206000);
255
256 *(unsigned int *)(0xe0000350) = 0x00000001;
257
258 udelay (1000);
259 mtsdr(SDR0_SRST1, 0x60306000);
260 /*-------------------PATCH-------------------------------*/
261
262 /* SDR Setting */
511d0c72 263 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9 264 mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833 265 mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR
266 mfsdr(SDR0_PFC1, sdr0_pfc1);
267
268 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 269 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 270 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 271 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
887e2ec9 272 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 273 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
887e2ec9 274 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 275 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
887e2ec9 276 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 277 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
887e2ec9
SR
278
279 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 280 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
887e2ec9
SR
281
282 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 283 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
887e2ec9
SR
284
285 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 286 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
887e2ec9 287
511d0c72
WD
288 mtsdr(SDR0_USB2H0CR, usb2h0cr);
289 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833 290 mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR
291 mtsdr(SDR0_PFC1, sdr0_pfc1);
292
83a49c8d 293 /* clear resets */
887e2ec9
SR
294 udelay (1000);
295 mtsdr(SDR0_SRST1, 0x00000000);
296 udelay (1000);
297 mtsdr(SDR0_SRST0, 0x00000000);
298
299 printf("USB: Device(int phy)\n");
300 }
854bc8da 301#endif /* CONFIG_440EPX */
887e2ec9 302
8ce16f55
JO
303 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
304 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
305 mtsdr(SDR0_SRST1, reg);
306
a78bc443
SR
307 /*
308 * Clear PLB4A0_ACR[WRP]
309 * This fix will make the MAL burst disabling patch for the Linux
310 * EMAC driver obsolete.
311 */
d1c3b275
SR
312 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
313 mtdcr(PLB4_ACR, reg);
a78bc443 314
887e2ec9
SR
315 return 0;
316}
317
318int checkboard(void)
319{
320 char *s = getenv("serial#");
e0b9ea8c
SR
321 u8 rev;
322 u8 val;
887e2ec9 323
854bc8da 324#ifdef CONFIG_440EPX
887e2ec9 325 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da
SR
326#else
327 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
328#endif
e0b9ea8c 329
6d0f6bcf
JCPV
330 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
331 val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
e0b9ea8c
SR
332 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
333
887e2ec9
SR
334 if (s != NULL) {
335 puts(", serial# ");
336 puts(s);
337 }
338 putc('\n');
339
340 return (0);
341}
342
1f84021a
MF
343#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
344/*
345 * Assign interrupts to PCI devices.
346 */
347void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
348{
d1631fe1 349 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
1f84021a
MF
350}
351#endif
352
83a49c8d
MF
353/*
354 * pci_pre_init
887e2ec9 355 *
83a49c8d
MF
356 * This routine is called just prior to registering the hose and gives
357 * the board the opportunity to check things. Returning a value of zero
358 * indicates that things are bad & PCI initialization should be aborted.
887e2ec9 359 *
83a49c8d
MF
360 * Different boards may wish to customize the pci controller structure
361 * (add regions, override default access routines, etc) or perform
362 * certain pre-initialization actions.
363 */
466fff1a 364#if defined(CONFIG_PCI)
887e2ec9
SR
365int pci_pre_init(struct pci_controller *hose)
366{
367 unsigned long addr;
887e2ec9 368
83a49c8d
MF
369 /*
370 * Set priority for all PLB3 devices to 0.
371 * Set PLB3 arbiter to fair mode.
372 */
d1c3b275
SR
373 mfsdr(SD0_AMP1, addr);
374 mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
375 addr = mfdcr(PLB3_ACR);
376 mtdcr(PLB3_ACR, addr | 0x80000000);
887e2ec9 377
83a49c8d
MF
378 /*
379 * Set priority for all PLB4 devices to 0.
380 */
d1c3b275
SR
381 mfsdr(SD0_AMP0, addr);
382 mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
383 addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
384 mtdcr(PLB4_ACR, addr);
887e2ec9 385
83a49c8d
MF
386 /*
387 * Set Nebula PLB4 arbiter to fair mode.
388 */
887e2ec9 389 /* Segment0 */
d1c3b275
SR
390 addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
391 addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
392 addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
393 addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
394 mtdcr(PLB0_ACR, addr);
887e2ec9
SR
395
396 /* Segment1 */
d1c3b275
SR
397 addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
398 addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
399 addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
400 addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
401 mtdcr(PLB1_ACR, addr);
887e2ec9 402
1f84021a
MF
403#ifdef CONFIG_PCI_PNP
404 hose->fixup_irq = sequoia_pci_fixup_irq;
405#endif
887e2ec9
SR
406 return 1;
407}
466fff1a 408#endif /* defined(CONFIG_PCI) */
887e2ec9 409
83a49c8d
MF
410/*
411 * pci_target_init
887e2ec9 412 *
83a49c8d
MF
413 * The bootstrap configuration provides default settings for the pci
414 * inbound map (PIM). But the bootstrap config choices are limited and
415 * may not be sufficient for a given board.
416 */
6d0f6bcf 417#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
887e2ec9
SR
418void pci_target_init(struct pci_controller *hose)
419{
83a49c8d 420 /*
887e2ec9 421 * Set up Direct MMIO registers
83a49c8d
MF
422 */
423 /*
424 * PowerPC440EPX PCI Master configuration.
425 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
426 * PLB address 0xA0000000-0xDFFFFFFF
427 * ==> PCI address 0xA0000000-0xDFFFFFFF
428 * Use byte reversed out routines to handle endianess.
429 * Make this region non-prefetchable.
430 */
431 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
432 /* - disabled b4 setting */
6d0f6bcf
JCPV
433 out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
434 out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
887e2ec9 435 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
83a49c8d
MF
436 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
437 /* and enable region */
887e2ec9 438
83a49c8d
MF
439 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
440 /* - disabled b4 setting */
6d0f6bcf
JCPV
441 out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
442 out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
887e2ec9 443 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
83a49c8d
MF
444 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
445 /* and enable region */
887e2ec9
SR
446
447 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
83a49c8d
MF
448 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
449 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
450 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
887e2ec9 451
83a49c8d 452 /*
887e2ec9 453 * Set up Configuration registers
83a49c8d 454 */
887e2ec9
SR
455
456 /* Program the board's subsystem id/vendor id */
457 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
6d0f6bcf
JCPV
458 CONFIG_SYS_PCI_SUBSYS_VENDORID);
459 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
887e2ec9
SR
460
461 /* Configure command register as bus master */
462 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
463
464 /* 240nS PCI clock */
465 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
466
467 /* No error reporting */
468 pci_write_config_word(0, PCI_ERREN, 0);
469
470 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
471
472}
6d0f6bcf 473#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
887e2ec9 474
6d0f6bcf 475#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
887e2ec9
SR
476void pci_master_init(struct pci_controller *hose)
477{
478 unsigned short temp_short;
479
83a49c8d
MF
480 /*
481 * Write the PowerPC440 EP PCI Configuration regs.
482 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
483 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
484 */
887e2ec9
SR
485 pci_read_config_word(0, PCI_COMMAND, &temp_short);
486 pci_write_config_word(0, PCI_COMMAND,
487 temp_short | PCI_COMMAND_MASTER |
488 PCI_COMMAND_MEMORY);
489}
6d0f6bcf 490#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
887e2ec9 491
83a49c8d
MF
492/*
493 * is_pci_host
887e2ec9 494 *
83a49c8d
MF
495 * This routine is called to determine if a pci scan should be
496 * performed. With various hardware environments (especially cPCI and
497 * PPMC) it's insufficient to depend on the state of the arbiter enable
498 * bit in the strap register, or generic host/adapter assumptions.
887e2ec9 499 *
83a49c8d
MF
500 * Rather than hard-code a bad assumption in the general 440 code, the
501 * 440 pci code requires the board to decide at runtime.
887e2ec9 502 *
83a49c8d
MF
503 * Return 0 for adapter mode, non-zero for host (monarch) mode.
504 */
887e2ec9
SR
505#if defined(CONFIG_PCI)
506int is_pci_host(struct pci_controller *hose)
507{
508 /* Cactus is always configured as host. */
509 return (1);
510}
83a49c8d
MF
511#endif /* defined(CONFIG_PCI) */
512
a11e0696
IL
513#if defined(CONFIG_POST)
514/*
515 * Returns 1 if keys pressed to start the power-on long-running tests
516 * Called from board_init_f().
517 */
518int post_hotkeys_pressed(void)
519{
520 return 0; /* No hotkeys supported */
521}
522#endif /* CONFIG_POST */
5132106a 523
d873133f 524#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
5132106a
SR
525/*
526 * On NAND-booting sequoia, we need to patch the chips select numbers
527 * in the dtb (CS0 - NAND, CS3 - NOR)
528 */
529void ft_board_setup(void *blob, bd_t *bd)
530{
531 int rc;
532 int len;
533 int nodeoffset;
534 struct fdt_property *prop;
535 u32 *reg;
536 char path[32];
537
538 /* First do common fdt setup */
539 __ft_board_setup(blob, bd);
540
541 /* And now configure NOR chip select to 3 instead of 0 */
542 strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
543 nodeoffset = fdt_path_offset(blob, path);
544 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
545 if (prop == NULL) {
546 printf("Unable to update NOR chip select for NAND booting\n");
547 return;
548 }
549 reg = (u32 *)&prop->data[0];
550 reg[0] = 3;
551 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
552 if (rc) {
553 printf("Unable to update property NOR mappings, err=%s\n",
554 fdt_strerror(rc));
555 return;
556 }
557
558 /* And now configure NAND chip select to 0 instead of 3 */
559 strcpy(path, "/plb/opb/ebc/ndfc@3,0");
560 nodeoffset = fdt_path_offset(blob, path);
561 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
562 if (prop == NULL) {
563 printf("Unable to update NDFC chip select for NAND booting\n");
564 return;
565 }
566 reg = (u32 *)&prop->data[0];
567 reg[0] = 0;
568 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
569 if (rc) {
570 printf("Unable to update property NDFC mappings, err=%s\n",
571 fdt_strerror(rc));
572 return;
573 }
574}
575#endif /* CONFIG_NAND_U_BOOT */