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de941241 SG |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Sukumar Ghorai <s-ghorai@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation's version 2 of | |
12 | * the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <common.h> | |
93bfd616 | 27 | #include <malloc.h> |
de941241 SG |
28 | #include <mmc.h> |
29 | #include <part.h> | |
30 | #include <i2c.h> | |
31 | #include <twl4030.h> | |
14fa2dd0 | 32 | #include <twl6030.h> |
cb199102 | 33 | #include <palmas.h> |
de941241 SG |
34 | #include <asm/io.h> |
35 | #include <asm/arch/mmc_host_def.h> | |
3b68939f RQ |
36 | #if !defined(CONFIG_SOC_KEYSTONE) |
37 | #include <asm/gpio.h> | |
96e0e7b3 | 38 | #include <asm/arch/sys_proto.h> |
3b68939f | 39 | #endif |
a9d6a7e2 M |
40 | #include <dm.h> |
41 | ||
42 | DECLARE_GLOBAL_DATA_PTR; | |
de941241 | 43 | |
ab769f22 PA |
44 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
45 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ | |
46 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) | |
47 | #define OMAP_HSMMC_USE_GPIO | |
48 | #else | |
49 | #undef OMAP_HSMMC_USE_GPIO | |
50 | #endif | |
51 | ||
25c719e2 GI |
52 | /* common definitions for all OMAPs */ |
53 | #define SYSCTL_SRC (1 << 25) | |
54 | #define SYSCTL_SRD (1 << 26) | |
55 | ||
cc22b0c0 NK |
56 | struct omap_hsmmc_data { |
57 | struct hsmmc *base_addr; | |
93bfd616 | 58 | struct mmc_config cfg; |
ab769f22 | 59 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 M |
60 | #ifdef CONFIG_DM_MMC |
61 | struct gpio_desc cd_gpio; /* Change Detect GPIO */ | |
62 | struct gpio_desc wp_gpio; /* Write Protect GPIO */ | |
63 | bool cd_inverted; | |
64 | #else | |
e874d5b0 | 65 | int cd_gpio; |
e3913f56 | 66 | int wp_gpio; |
ab769f22 | 67 | #endif |
a9d6a7e2 | 68 | #endif |
cc22b0c0 NK |
69 | }; |
70 | ||
eb9a28f6 NM |
71 | /* If we fail after 1 second wait, something is really bad */ |
72 | #define MAX_RETRY_MS 1000 | |
73 | ||
933efe64 S |
74 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
75 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
76 | unsigned int siz); | |
14fa2dd0 | 77 | |
a9d6a7e2 | 78 | #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC) |
e874d5b0 NK |
79 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
80 | { | |
5915a2ad | 81 | int ret; |
e874d5b0 | 82 | |
5915a2ad SG |
83 | #ifndef CONFIG_DM_GPIO |
84 | if (!gpio_is_valid(gpio)) | |
e874d5b0 | 85 | return -1; |
5915a2ad SG |
86 | #endif |
87 | ret = gpio_request(gpio, label); | |
88 | if (ret) | |
89 | return ret; | |
e874d5b0 | 90 | |
5915a2ad SG |
91 | ret = gpio_direction_input(gpio); |
92 | if (ret) | |
93 | return ret; | |
e874d5b0 NK |
94 | |
95 | return gpio; | |
96 | } | |
e874d5b0 NK |
97 | #endif |
98 | ||
750121c3 | 99 | static unsigned char mmc_board_init(struct mmc *mmc) |
de941241 | 100 | { |
de941241 SG |
101 | #if defined(CONFIG_OMAP34XX) |
102 | t2_t *t2_base = (t2_t *)T2_BASE; | |
103 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
b1e725f2 | 104 | u32 pbias_lite; |
de941241 | 105 | |
b1e725f2 GI |
106 | pbias_lite = readl(&t2_base->pbias_lite); |
107 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); | |
5bfdd1fc AA |
108 | #ifdef CONFIG_TARGET_OMAP3_CAIRO |
109 | /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ | |
110 | pbias_lite &= ~PBIASLITEVMODE0; | |
111 | #endif | |
b1e725f2 | 112 | writel(pbias_lite, &t2_base->pbias_lite); |
aac5450e | 113 | |
b1e725f2 | 114 | writel(pbias_lite | PBIASLITEPWRDNZ1 | |
de941241 SG |
115 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
116 | &t2_base->pbias_lite); | |
117 | ||
118 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, | |
119 | &t2_base->devconf0); | |
120 | ||
121 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, | |
122 | &t2_base->devconf1); | |
123 | ||
bbbc1ae9 | 124 | /* Change from default of 52MHz to 26MHz if necessary */ |
93bfd616 | 125 | if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz)) |
bbbc1ae9 JS |
126 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
127 | &t2_base->ctl_prog_io1); | |
128 | ||
de941241 SG |
129 | writel(readl(&prcm_base->fclken1_core) | |
130 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
131 | &prcm_base->fclken1_core); | |
132 | ||
133 | writel(readl(&prcm_base->iclken1_core) | | |
134 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
135 | &prcm_base->iclken1_core); | |
136 | #endif | |
137 | ||
b4b06006 | 138 | #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) |
14fa2dd0 | 139 | /* PBIAS config needed for MMC1 only */ |
bcce53d0 | 140 | if (mmc->block_dev.devnum == 0) |
b4b06006 | 141 | vmmc_pbias_config(LDO_VOLT_3V0); |
dd23e59d | 142 | #endif |
de941241 SG |
143 | |
144 | return 0; | |
145 | } | |
146 | ||
933efe64 | 147 | void mmc_init_stream(struct hsmmc *mmc_base) |
de941241 | 148 | { |
eb9a28f6 | 149 | ulong start; |
de941241 SG |
150 | |
151 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); | |
152 | ||
153 | writel(MMC_CMD0, &mmc_base->cmd); | |
eb9a28f6 NM |
154 | start = get_timer(0); |
155 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
156 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
157 | printf("%s: timedout waiting for cc!\n", __func__); | |
158 | return; | |
159 | } | |
160 | } | |
de941241 SG |
161 | writel(CC_MASK, &mmc_base->stat) |
162 | ; | |
163 | writel(MMC_CMD0, &mmc_base->cmd) | |
164 | ; | |
eb9a28f6 NM |
165 | start = get_timer(0); |
166 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
167 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
168 | printf("%s: timedout waiting for cc2!\n", __func__); | |
169 | return; | |
170 | } | |
171 | } | |
de941241 SG |
172 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
173 | } | |
174 | ||
ab769f22 | 175 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
de941241 | 176 | { |
cc22b0c0 | 177 | struct hsmmc *mmc_base; |
de941241 SG |
178 | unsigned int reg_val; |
179 | unsigned int dsor; | |
eb9a28f6 | 180 | ulong start; |
de941241 | 181 | |
cc22b0c0 | 182 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
14fa2dd0 | 183 | mmc_board_init(mmc); |
de941241 SG |
184 | |
185 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, | |
186 | &mmc_base->sysconfig); | |
eb9a28f6 NM |
187 | start = get_timer(0); |
188 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { | |
189 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
190 | printf("%s: timedout waiting for cc2!\n", __func__); | |
915ffa52 | 191 | return -ETIMEDOUT; |
eb9a28f6 NM |
192 | } |
193 | } | |
de941241 | 194 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
eb9a28f6 NM |
195 | start = get_timer(0); |
196 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { | |
197 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
198 | printf("%s: timedout waiting for softresetall!\n", | |
199 | __func__); | |
915ffa52 | 200 | return -ETIMEDOUT; |
eb9a28f6 NM |
201 | } |
202 | } | |
de941241 SG |
203 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
204 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, | |
205 | &mmc_base->capa); | |
206 | ||
207 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; | |
208 | ||
209 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | | |
210 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | | |
211 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); | |
212 | ||
213 | dsor = 240; | |
214 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
215 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
216 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
217 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
eb9a28f6 NM |
218 | start = get_timer(0); |
219 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
220 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
221 | printf("%s: timedout waiting for ics!\n", __func__); | |
915ffa52 | 222 | return -ETIMEDOUT; |
eb9a28f6 NM |
223 | } |
224 | } | |
de941241 SG |
225 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
226 | ||
227 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); | |
228 | ||
229 | writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | | |
230 | IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, | |
231 | &mmc_base->ie); | |
232 | ||
233 | mmc_init_stream(mmc_base); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
25c719e2 GI |
238 | /* |
239 | * MMC controller internal finite state machine reset | |
240 | * | |
241 | * Used to reset command or data internal state machines, using respectively | |
242 | * SRC or SRD bit of SYSCTL register | |
243 | */ | |
244 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) | |
245 | { | |
246 | ulong start; | |
247 | ||
248 | mmc_reg_out(&mmc_base->sysctl, bit, bit); | |
249 | ||
61a6cc27 OT |
250 | /* |
251 | * CMD(DAT) lines reset procedures are slightly different | |
252 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). | |
253 | * According to OMAP3 TRM: | |
254 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it | |
255 | * returns to 0x0. | |
256 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset | |
257 | * procedure steps must be as follows: | |
258 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in | |
259 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). | |
260 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. | |
261 | * 3. Wait until the SRC (SRD) bit returns to 0x0 | |
262 | * (reset procedure is completed). | |
263 | */ | |
264 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ | |
dce55b93 | 265 | defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) |
61a6cc27 OT |
266 | if (!(readl(&mmc_base->sysctl) & bit)) { |
267 | start = get_timer(0); | |
268 | while (!(readl(&mmc_base->sysctl) & bit)) { | |
269 | if (get_timer(0) - start > MAX_RETRY_MS) | |
270 | return; | |
271 | } | |
272 | } | |
273 | #endif | |
25c719e2 GI |
274 | start = get_timer(0); |
275 | while ((readl(&mmc_base->sysctl) & bit) != 0) { | |
276 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
277 | printf("%s: timedout waiting for sysctl %x to clear\n", | |
278 | __func__, bit); | |
279 | return; | |
280 | } | |
281 | } | |
282 | } | |
de941241 | 283 | |
ab769f22 | 284 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
de941241 SG |
285 | struct mmc_data *data) |
286 | { | |
cc22b0c0 | 287 | struct hsmmc *mmc_base; |
de941241 | 288 | unsigned int flags, mmc_stat; |
eb9a28f6 | 289 | ulong start; |
de941241 | 290 | |
cc22b0c0 | 291 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
eb9a28f6 | 292 | start = get_timer(0); |
a7778f8f | 293 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
eb9a28f6 | 294 | if (get_timer(0) - start > MAX_RETRY_MS) { |
a7778f8f TR |
295 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
296 | __func__); | |
915ffa52 | 297 | return -ETIMEDOUT; |
eb9a28f6 NM |
298 | } |
299 | } | |
de941241 | 300 | writel(0xFFFFFFFF, &mmc_base->stat); |
eb9a28f6 NM |
301 | start = get_timer(0); |
302 | while (readl(&mmc_base->stat)) { | |
303 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
15ceb1de GI |
304 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
305 | __func__, readl(&mmc_base->stat)); | |
915ffa52 | 306 | return -ETIMEDOUT; |
eb9a28f6 NM |
307 | } |
308 | } | |
de941241 SG |
309 | /* |
310 | * CMDREG | |
311 | * CMDIDX[13:8] : Command index | |
312 | * DATAPRNT[5] : Data Present Select | |
313 | * ENCMDIDX[4] : Command Index Check Enable | |
314 | * ENCMDCRC[3] : Command CRC Check Enable | |
315 | * RSPTYP[1:0] | |
316 | * 00 = No Response | |
317 | * 01 = Length 136 | |
318 | * 10 = Length 48 | |
319 | * 11 = Length 48 Check busy after response | |
320 | */ | |
321 | /* Delay added before checking the status of frq change | |
322 | * retry not supported by mmc.c(core file) | |
323 | */ | |
324 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) | |
325 | udelay(50000); /* wait 50 ms */ | |
326 | ||
327 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
328 | flags = 0; | |
329 | else if (cmd->resp_type & MMC_RSP_136) | |
330 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; | |
331 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
332 | flags = RSP_TYPE_LGHT48B; | |
333 | else | |
334 | flags = RSP_TYPE_LGHT48; | |
335 | ||
336 | /* enable default flags */ | |
337 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | | |
338 | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); | |
339 | ||
340 | if (cmd->resp_type & MMC_RSP_CRC) | |
341 | flags |= CCCE_CHECK; | |
342 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
343 | flags |= CICE_CHECK; | |
344 | ||
345 | if (data) { | |
346 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || | |
347 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { | |
348 | flags |= (MSBS_MULTIBLK | BCE_ENABLE); | |
349 | data->blocksize = 512; | |
350 | writel(data->blocksize | (data->blocks << 16), | |
351 | &mmc_base->blk); | |
352 | } else | |
353 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); | |
354 | ||
355 | if (data->flags & MMC_DATA_READ) | |
356 | flags |= (DP_DATA | DDIR_READ); | |
357 | else | |
358 | flags |= (DP_DATA | DDIR_WRITE); | |
359 | } | |
360 | ||
361 | writel(cmd->cmdarg, &mmc_base->arg); | |
152ba363 | 362 | udelay(20); /* To fix "No status update" error on eMMC */ |
de941241 SG |
363 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
364 | ||
eb9a28f6 | 365 | start = get_timer(0); |
de941241 SG |
366 | do { |
367 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
368 | if (get_timer(0) - start > MAX_RETRY_MS) { |
369 | printf("%s : timeout: No status update\n", __func__); | |
915ffa52 | 370 | return -ETIMEDOUT; |
eb9a28f6 NM |
371 | } |
372 | } while (!mmc_stat); | |
de941241 | 373 | |
25c719e2 GI |
374 | if ((mmc_stat & IE_CTO) != 0) { |
375 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
915ffa52 | 376 | return -ETIMEDOUT; |
25c719e2 | 377 | } else if ((mmc_stat & ERRI_MASK) != 0) |
de941241 SG |
378 | return -1; |
379 | ||
380 | if (mmc_stat & CC_MASK) { | |
381 | writel(CC_MASK, &mmc_base->stat); | |
382 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
383 | if (cmd->resp_type & MMC_RSP_136) { | |
384 | /* response type 2 */ | |
385 | cmd->response[3] = readl(&mmc_base->rsp10); | |
386 | cmd->response[2] = readl(&mmc_base->rsp32); | |
387 | cmd->response[1] = readl(&mmc_base->rsp54); | |
388 | cmd->response[0] = readl(&mmc_base->rsp76); | |
389 | } else | |
390 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
391 | cmd->response[0] = readl(&mmc_base->rsp10); | |
392 | } | |
393 | } | |
394 | ||
395 | if (data && (data->flags & MMC_DATA_READ)) { | |
396 | mmc_read_data(mmc_base, data->dest, | |
397 | data->blocksize * data->blocks); | |
398 | } else if (data && (data->flags & MMC_DATA_WRITE)) { | |
399 | mmc_write_data(mmc_base, data->src, | |
400 | data->blocksize * data->blocks); | |
401 | } | |
402 | return 0; | |
403 | } | |
404 | ||
933efe64 | 405 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
de941241 SG |
406 | { |
407 | unsigned int *output_buf = (unsigned int *)buf; | |
408 | unsigned int mmc_stat; | |
409 | unsigned int count; | |
410 | ||
411 | /* | |
412 | * Start Polled Read | |
413 | */ | |
414 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
415 | count /= 4; | |
416 | ||
417 | while (size) { | |
eb9a28f6 | 418 | ulong start = get_timer(0); |
de941241 SG |
419 | do { |
420 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
421 | if (get_timer(0) - start > MAX_RETRY_MS) { |
422 | printf("%s: timedout waiting for status!\n", | |
423 | __func__); | |
915ffa52 | 424 | return -ETIMEDOUT; |
eb9a28f6 | 425 | } |
de941241 SG |
426 | } while (mmc_stat == 0); |
427 | ||
25c719e2 GI |
428 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
429 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
430 | ||
de941241 SG |
431 | if ((mmc_stat & ERRI_MASK) != 0) |
432 | return 1; | |
433 | ||
434 | if (mmc_stat & BRR_MASK) { | |
435 | unsigned int k; | |
436 | ||
437 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
438 | &mmc_base->stat); | |
439 | for (k = 0; k < count; k++) { | |
440 | *output_buf = readl(&mmc_base->data); | |
441 | output_buf++; | |
442 | } | |
443 | size -= (count*4); | |
444 | } | |
445 | ||
446 | if (mmc_stat & BWR_MASK) | |
447 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
448 | &mmc_base->stat); | |
449 | ||
450 | if (mmc_stat & TC_MASK) { | |
451 | writel(readl(&mmc_base->stat) | TC_MASK, | |
452 | &mmc_base->stat); | |
453 | break; | |
454 | } | |
455 | } | |
456 | return 0; | |
457 | } | |
458 | ||
933efe64 S |
459 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
460 | unsigned int size) | |
de941241 SG |
461 | { |
462 | unsigned int *input_buf = (unsigned int *)buf; | |
463 | unsigned int mmc_stat; | |
464 | unsigned int count; | |
465 | ||
466 | /* | |
152ba363 | 467 | * Start Polled Write |
de941241 SG |
468 | */ |
469 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
470 | count /= 4; | |
471 | ||
472 | while (size) { | |
eb9a28f6 | 473 | ulong start = get_timer(0); |
de941241 SG |
474 | do { |
475 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
476 | if (get_timer(0) - start > MAX_RETRY_MS) { |
477 | printf("%s: timedout waiting for status!\n", | |
478 | __func__); | |
915ffa52 | 479 | return -ETIMEDOUT; |
eb9a28f6 | 480 | } |
de941241 SG |
481 | } while (mmc_stat == 0); |
482 | ||
25c719e2 GI |
483 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
484 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
485 | ||
de941241 SG |
486 | if ((mmc_stat & ERRI_MASK) != 0) |
487 | return 1; | |
488 | ||
489 | if (mmc_stat & BWR_MASK) { | |
490 | unsigned int k; | |
491 | ||
492 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
493 | &mmc_base->stat); | |
494 | for (k = 0; k < count; k++) { | |
495 | writel(*input_buf, &mmc_base->data); | |
496 | input_buf++; | |
497 | } | |
498 | size -= (count*4); | |
499 | } | |
500 | ||
501 | if (mmc_stat & BRR_MASK) | |
502 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
503 | &mmc_base->stat); | |
504 | ||
505 | if (mmc_stat & TC_MASK) { | |
506 | writel(readl(&mmc_base->stat) | TC_MASK, | |
507 | &mmc_base->stat); | |
508 | break; | |
509 | } | |
510 | } | |
511 | return 0; | |
512 | } | |
513 | ||
07b0b9c0 | 514 | static int omap_hsmmc_set_ios(struct mmc *mmc) |
de941241 | 515 | { |
cc22b0c0 | 516 | struct hsmmc *mmc_base; |
de941241 | 517 | unsigned int dsor = 0; |
eb9a28f6 | 518 | ulong start; |
de941241 | 519 | |
cc22b0c0 | 520 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
de941241 SG |
521 | /* configue bus width */ |
522 | switch (mmc->bus_width) { | |
523 | case 8: | |
524 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, | |
525 | &mmc_base->con); | |
526 | break; | |
527 | ||
528 | case 4: | |
529 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
530 | &mmc_base->con); | |
531 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, | |
532 | &mmc_base->hctl); | |
533 | break; | |
534 | ||
535 | case 1: | |
536 | default: | |
537 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
538 | &mmc_base->con); | |
539 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, | |
540 | &mmc_base->hctl); | |
541 | break; | |
542 | } | |
543 | ||
544 | /* configure clock with 96Mhz system clock. | |
545 | */ | |
546 | if (mmc->clock != 0) { | |
547 | dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); | |
548 | if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) | |
549 | dsor++; | |
550 | } | |
551 | ||
552 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
553 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
554 | ||
555 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
556 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
557 | ||
eb9a28f6 NM |
558 | start = get_timer(0); |
559 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
560 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
561 | printf("%s: timedout waiting for ics!\n", __func__); | |
07b0b9c0 | 562 | return -ETIMEDOUT; |
eb9a28f6 NM |
563 | } |
564 | } | |
de941241 | 565 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
07b0b9c0 JC |
566 | |
567 | return 0; | |
de941241 SG |
568 | } |
569 | ||
ab769f22 | 570 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 M |
571 | #ifdef CONFIG_DM_MMC |
572 | static int omap_hsmmc_getcd(struct mmc *mmc) | |
573 | { | |
574 | struct omap_hsmmc_data *priv = mmc->priv; | |
575 | int value; | |
576 | ||
577 | value = dm_gpio_get_value(&priv->cd_gpio); | |
578 | /* if no CD return as 1 */ | |
579 | if (value < 0) | |
580 | return 1; | |
581 | ||
582 | if (priv->cd_inverted) | |
583 | return !value; | |
584 | return value; | |
585 | } | |
586 | ||
587 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
588 | { | |
589 | struct omap_hsmmc_data *priv = mmc->priv; | |
590 | int value; | |
591 | ||
592 | value = dm_gpio_get_value(&priv->wp_gpio); | |
593 | /* if no WP return as 0 */ | |
594 | if (value < 0) | |
595 | return 0; | |
596 | return value; | |
597 | } | |
598 | #else | |
ab769f22 PA |
599 | static int omap_hsmmc_getcd(struct mmc *mmc) |
600 | { | |
601 | struct omap_hsmmc_data *priv_data = mmc->priv; | |
602 | int cd_gpio; | |
603 | ||
604 | /* if no CD return as 1 */ | |
605 | cd_gpio = priv_data->cd_gpio; | |
606 | if (cd_gpio < 0) | |
607 | return 1; | |
608 | ||
0b03a931 IG |
609 | /* NOTE: assumes card detect signal is active-low */ |
610 | return !gpio_get_value(cd_gpio); | |
ab769f22 PA |
611 | } |
612 | ||
613 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
614 | { | |
615 | struct omap_hsmmc_data *priv_data = mmc->priv; | |
616 | int wp_gpio; | |
617 | ||
618 | /* if no WP return as 0 */ | |
619 | wp_gpio = priv_data->wp_gpio; | |
620 | if (wp_gpio < 0) | |
621 | return 0; | |
622 | ||
0b03a931 | 623 | /* NOTE: assumes write protect signal is active-high */ |
ab769f22 PA |
624 | return gpio_get_value(wp_gpio); |
625 | } | |
626 | #endif | |
a9d6a7e2 | 627 | #endif |
ab769f22 PA |
628 | |
629 | static const struct mmc_ops omap_hsmmc_ops = { | |
630 | .send_cmd = omap_hsmmc_send_cmd, | |
631 | .set_ios = omap_hsmmc_set_ios, | |
632 | .init = omap_hsmmc_init_setup, | |
633 | #ifdef OMAP_HSMMC_USE_GPIO | |
634 | .getcd = omap_hsmmc_getcd, | |
635 | .getwp = omap_hsmmc_getwp, | |
636 | #endif | |
637 | }; | |
638 | ||
a9d6a7e2 | 639 | #ifndef CONFIG_DM_MMC |
e3913f56 NK |
640 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
641 | int wp_gpio) | |
de941241 | 642 | { |
93bfd616 PA |
643 | struct mmc *mmc; |
644 | struct omap_hsmmc_data *priv_data; | |
645 | struct mmc_config *cfg; | |
646 | uint host_caps_val; | |
647 | ||
648 | priv_data = malloc(sizeof(*priv_data)); | |
649 | if (priv_data == NULL) | |
650 | return -1; | |
de941241 | 651 | |
5a20397b | 652 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
de941241 SG |
653 | |
654 | switch (dev_index) { | |
655 | case 0: | |
cc22b0c0 | 656 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 | 657 | break; |
1037d585 | 658 | #ifdef OMAP_HSMMC2_BASE |
de941241 | 659 | case 1: |
cc22b0c0 | 660 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
152ba363 | 661 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
3891a54f | 662 | defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ |
3b68939f RQ |
663 | defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ |
664 | defined(CONFIG_HSMMC2_8BIT) | |
152ba363 LP |
665 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ |
666 | host_caps_val |= MMC_MODE_8BIT; | |
667 | #endif | |
de941241 | 668 | break; |
1037d585 TR |
669 | #endif |
670 | #ifdef OMAP_HSMMC3_BASE | |
de941241 | 671 | case 2: |
cc22b0c0 | 672 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
3891a54f | 673 | #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) |
152ba363 LP |
674 | /* Enable 8-bit interface for eMMC on DRA7XX */ |
675 | host_caps_val |= MMC_MODE_8BIT; | |
676 | #endif | |
de941241 | 677 | break; |
1037d585 | 678 | #endif |
de941241 | 679 | default: |
cc22b0c0 | 680 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 SG |
681 | return 1; |
682 | } | |
ab769f22 PA |
683 | #ifdef OMAP_HSMMC_USE_GPIO |
684 | /* on error gpio values are set to -1, which is what we want */ | |
e874d5b0 | 685 | priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
e3913f56 | 686 | priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); |
ab769f22 | 687 | #endif |
173ddc5b | 688 | |
93bfd616 | 689 | cfg = &priv_data->cfg; |
de941241 | 690 | |
93bfd616 PA |
691 | cfg->name = "OMAP SD/MMC"; |
692 | cfg->ops = &omap_hsmmc_ops; | |
693 | ||
694 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
695 | cfg->host_caps = host_caps_val & ~host_caps_mask; | |
696 | ||
697 | cfg->f_min = 400000; | |
bbbc1ae9 JS |
698 | |
699 | if (f_max != 0) | |
93bfd616 | 700 | cfg->f_max = f_max; |
bbbc1ae9 | 701 | else { |
93bfd616 PA |
702 | if (cfg->host_caps & MMC_MODE_HS) { |
703 | if (cfg->host_caps & MMC_MODE_HS_52MHz) | |
704 | cfg->f_max = 52000000; | |
bbbc1ae9 | 705 | else |
93bfd616 | 706 | cfg->f_max = 26000000; |
bbbc1ae9 | 707 | } else |
93bfd616 | 708 | cfg->f_max = 20000000; |
bbbc1ae9 | 709 | } |
de941241 | 710 | |
93bfd616 | 711 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
8feafcc4 | 712 | |
4ca9244d JR |
713 | #if defined(CONFIG_OMAP34XX) |
714 | /* | |
715 | * Silicon revs 2.1 and older do not support multiblock transfers. | |
716 | */ | |
717 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) | |
93bfd616 | 718 | cfg->b_max = 1; |
4ca9244d | 719 | #endif |
93bfd616 PA |
720 | mmc = mmc_create(cfg, priv_data); |
721 | if (mmc == NULL) | |
722 | return -1; | |
de941241 SG |
723 | |
724 | return 0; | |
725 | } | |
a9d6a7e2 M |
726 | #else |
727 | static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) | |
728 | { | |
729 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
730 | const void *fdt = gd->fdt_blob; | |
731 | int node = dev->of_offset; | |
732 | struct mmc_config *cfg; | |
733 | int val; | |
734 | ||
4bc5e19e M |
735 | priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *), |
736 | MAP_NOCACHE); | |
a9d6a7e2 M |
737 | cfg = &priv->cfg; |
738 | ||
739 | cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; | |
740 | val = fdtdec_get_int(fdt, node, "bus-width", -1); | |
741 | if (val < 0) { | |
742 | printf("error: bus-width property missing\n"); | |
743 | return -ENOENT; | |
744 | } | |
745 | ||
746 | switch (val) { | |
747 | case 0x8: | |
748 | cfg->host_caps |= MMC_MODE_8BIT; | |
749 | case 0x4: | |
750 | cfg->host_caps |= MMC_MODE_4BIT; | |
751 | break; | |
752 | default: | |
753 | printf("error: invalid bus-width property\n"); | |
754 | return -ENOENT; | |
755 | } | |
756 | ||
757 | cfg->f_min = 400000; | |
758 | cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); | |
759 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
760 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; | |
761 | ||
4de2de51 | 762 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 | 763 | priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); |
4de2de51 | 764 | #endif |
a9d6a7e2 M |
765 | |
766 | return 0; | |
767 | } | |
768 | ||
769 | static int omap_hsmmc_probe(struct udevice *dev) | |
770 | { | |
771 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
772 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
773 | struct mmc_config *cfg; | |
774 | struct mmc *mmc; | |
775 | ||
776 | cfg = &priv->cfg; | |
777 | cfg->name = "OMAP SD/MMC"; | |
778 | cfg->ops = &omap_hsmmc_ops; | |
779 | ||
780 | mmc = mmc_create(cfg, priv); | |
781 | if (mmc == NULL) | |
782 | return -1; | |
783 | ||
5cc6a245 M |
784 | #ifdef OMAP_HSMMC_USE_GPIO |
785 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); | |
786 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); | |
787 | #endif | |
788 | ||
cffe5d86 | 789 | mmc->dev = dev; |
a9d6a7e2 M |
790 | upriv->mmc = mmc; |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static const struct udevice_id omap_hsmmc_ids[] = { | |
796 | { .compatible = "ti,omap3-hsmmc" }, | |
797 | { .compatible = "ti,omap4-hsmmc" }, | |
798 | { .compatible = "ti,am33xx-hsmmc" }, | |
799 | { } | |
800 | }; | |
801 | ||
802 | U_BOOT_DRIVER(omap_hsmmc) = { | |
803 | .name = "omap_hsmmc", | |
804 | .id = UCLASS_MMC, | |
805 | .of_match = omap_hsmmc_ids, | |
806 | .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, | |
807 | .probe = omap_hsmmc_probe, | |
808 | .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), | |
809 | }; | |
810 | #endif |