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Commit | Line | Data |
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3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
792a09eb | 11 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
3e326ece MK |
12 | * |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
1a459660 | 20 | * SPDX-License-Identifier: GPL-2.0+ |
3e326ece MK |
21 | */ |
22 | /* | |
23 | * IMPORTANT NOTES | |
fc43be47 | 24 | * 1 - Read doc/README.generic_usb_ohci |
3e326ece | 25 | * 2 - this driver is intended for use with USB Mass Storage Devices |
4dae14ce | 26 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
fc43be47 | 27 | * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
3e326ece MK |
28 | * to activate workaround for bug #41 or this driver will NOT work! |
29 | */ | |
30 | ||
31 | #include <common.h> | |
fc43be47 | 32 | #include <asm/byteorder.h> |
58b4048f HG |
33 | #include <dm.h> |
34 | #include <errno.h> | |
fc43be47 MK |
35 | |
36 | #if defined(CONFIG_PCI_OHCI) | |
4dae14ce | 37 | # include <pci.h> |
477434c6 SP |
38 | #if !defined(CONFIG_PCI_OHCI_DEVNO) |
39 | #define CONFIG_PCI_OHCI_DEVNO 0 | |
40 | #endif | |
ddf83a2f | 41 | #endif |
3e326ece MK |
42 | |
43 | #include <malloc.h> | |
44 | #include <usb.h> | |
2731b9a8 JCPV |
45 | |
46 | #include "ohci.h" | |
3e326ece | 47 | |
e8da58f2 WD |
48 | #ifdef CONFIG_AT91RM9200 |
49 | #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ | |
50 | #endif | |
51 | ||
f2168440 | 52 | #if defined(CONFIG_CPU_ARM920T) || \ |
ac67804f | 53 | defined(CONFIG_S3C24X0) || \ |
ae3b770e | 54 | defined(CONFIG_440EP) || \ |
4dae14ce | 55 | defined(CONFIG_PCI_OHCI) || \ |
2596f5b9 | 56 | defined(CONFIG_MPC5200) || \ |
6d0f6bcf | 57 | defined(CONFIG_SYS_OHCI_USE_NPS) |
24e37645 MK |
58 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
59 | #endif | |
60 | ||
3e326ece | 61 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
62 | #undef DEBUG |
63 | #undef SHOW_INFO | |
64 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
65 | |
66 | /* For initializing controller (mask in an HCFS mode too) */ | |
67 | #define OHCI_CONTROL_INIT \ | |
68 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
69 | ||
4dae14ce ZW |
70 | #ifdef CONFIG_PCI_OHCI |
71 | static struct pci_device_id ohci_pci_ids[] = { | |
72 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
97213f32 | 73 | {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ |
3afac79e | 74 | {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ |
4dae14ce ZW |
75 | /* Please add supported PCI OHCI controller ids here */ |
76 | {0, 0} | |
77 | }; | |
78 | #endif | |
79 | ||
e90fb6af YT |
80 | #ifdef CONFIG_PCI_EHCI_DEVNO |
81 | static struct pci_device_id ehci_pci_ids[] = { | |
82 | {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ | |
83 | /* Please add supported PCI EHCI controller ids here */ | |
84 | {0, 0} | |
85 | }; | |
86 | #endif | |
87 | ||
3e326ece MK |
88 | #ifdef DEBUG |
89 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
90 | #else | |
6f5794a6 | 91 | #define dbg(format, arg...) do {} while (0) |
3e326ece MK |
92 | #endif /* DEBUG */ |
93 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
3e326ece MK |
94 | #ifdef SHOW_INFO |
95 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
96 | #else | |
6f5794a6 | 97 | #define info(format, arg...) do {} while (0) |
3e326ece MK |
98 | #endif |
99 | ||
6d0f6bcf | 100 | #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER |
fc43be47 MK |
101 | # define m16_swap(x) cpu_to_be16(x) |
102 | # define m32_swap(x) cpu_to_be32(x) | |
ae3b770e | 103 | #else |
fc43be47 MK |
104 | # define m16_swap(x) cpu_to_le16(x) |
105 | # define m32_swap(x) cpu_to_le32(x) | |
6d0f6bcf | 106 | #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ |
3e326ece | 107 | |
8d005ef8 HG |
108 | #ifdef CONFIG_DM_USB |
109 | /* | |
110 | * We really should do proper cache flushing everywhere, but for now we only | |
111 | * do it for new (driver-model) usb code to avoid regressions. | |
112 | */ | |
113 | #define flush_dcache_buffer(addr, size) \ | |
114 | flush_dcache_range((unsigned long)(addr), \ | |
115 | ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) | |
116 | #define invalidate_dcache_buffer(addr, size) \ | |
117 | invalidate_dcache_range((unsigned long)(addr), \ | |
118 | ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) | |
119 | #else | |
120 | #define flush_dcache_buffer(addr, size) | |
121 | #define invalidate_dcache_buffer(addr, size) | |
122 | #endif | |
123 | ||
124 | /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */ | |
125 | #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16) | |
126 | #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16) | |
127 | #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32) | |
128 | #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256) | |
129 | #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16) | |
130 | #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16) | |
131 | #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) | |
132 | #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) | |
133 | ||
8f761f02 HG |
134 | #ifdef CONFIG_DM_USB |
135 | /* | |
136 | * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep | |
137 | * them around when building for older boards not yet converted to the dm | |
138 | * just in case (to avoid regressions), for dm this turns them into nops. | |
139 | */ | |
140 | #define ohci_mdelay(x) | |
141 | #else | |
142 | #define ohci_mdelay(x) mdelay(x) | |
143 | #endif | |
144 | ||
58b4048f | 145 | #ifndef CONFIG_DM_USB |
3e326ece MK |
146 | /* global ohci_t */ |
147 | static ohci_t gohci; | |
148 | /* this must be aligned to a 256 byte boundary */ | |
149 | struct ohci_hcca ghcca[1]; | |
58b4048f | 150 | #endif |
3e326ece | 151 | |
6651c140 HG |
152 | /* mapping of the OHCI CC status to error codes */ |
153 | static int cc_to_error[16] = { | |
154 | /* No Error */ 0, | |
155 | /* CRC Error */ USB_ST_CRC_ERR, | |
156 | /* Bit Stuff */ USB_ST_BIT_ERR, | |
157 | /* Data Togg */ USB_ST_CRC_ERR, | |
158 | /* Stall */ USB_ST_STALLED, | |
159 | /* DevNotResp */ -1, | |
160 | /* PIDCheck */ USB_ST_BIT_ERR, | |
161 | /* UnExpPID */ USB_ST_BIT_ERR, | |
162 | /* DataOver */ USB_ST_BUF_ERR, | |
163 | /* DataUnder */ USB_ST_BUF_ERR, | |
164 | /* reservd */ -1, | |
165 | /* reservd */ -1, | |
166 | /* BufferOver */ USB_ST_BUF_ERR, | |
167 | /* BuffUnder */ USB_ST_BUF_ERR, | |
168 | /* Not Access */ -1, | |
169 | /* Not Access */ -1 | |
170 | }; | |
171 | ||
172 | static const char *cc_to_string[16] = { | |
173 | "No Error", | |
174 | "CRC: Last data packet from endpoint contained a CRC error.", | |
175 | "BITSTUFFING: Last data packet from endpoint contained a bit " \ | |
176 | "stuffing violation", | |
177 | "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ | |
178 | "that did not match the expected value.", | |
179 | "STALL: TD was moved to the Done Queue because the endpoint returned" \ | |
180 | " a STALL PID", | |
181 | "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ | |
182 | "not provide a handshake (OUT)", | |
183 | "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ | |
184 | "(IN) or handshake (OUT)", | |
185 | "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ | |
186 | "value is not defined.", | |
187 | "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ | |
188 | "either the size of the maximum data packet allowed\n" \ | |
189 | "from the endpoint (found in MaximumPacketSize field\n" \ | |
190 | "of ED) or the remaining buffer size.", | |
191 | "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ | |
192 | "and that amount was not sufficient to fill the\n" \ | |
193 | "specified buffer", | |
194 | "reserved1", | |
195 | "reserved2", | |
196 | "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ | |
197 | "than it could be written to system memory", | |
198 | "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ | |
199 | "system memory fast enough to keep up with data USB " \ | |
200 | "data rate.", | |
201 | "NOT ACCESSED: This code is set by software before the TD is placed" \ | |
202 | "on a list to be processed by the HC.(1)", | |
203 | "NOT ACCESSED: This code is set by software before the TD is placed" \ | |
204 | "on a list to be processed by the HC.(2)", | |
205 | }; | |
206 | ||
6f5794a6 | 207 | static inline u32 roothub_a(struct ohci *hc) |
a5496a18 | 208 | { return ohci_readl(&hc->regs->roothub.a); } |
6f5794a6 | 209 | static inline u32 roothub_b(struct ohci *hc) |
a5496a18 | 210 | { return ohci_readl(&hc->regs->roothub.b); } |
6f5794a6 | 211 | static inline u32 roothub_status(struct ohci *hc) |
a5496a18 | 212 | { return ohci_readl(&hc->regs->roothub.status); } |
6f5794a6 | 213 | static inline u32 roothub_portstatus(struct ohci *hc, int i) |
a5496a18 | 214 | { return ohci_readl(&hc->regs->roothub.portstatus[i]); } |
3e326ece | 215 | |
3e326ece | 216 | /* forward declaration */ |
c5613df5 HG |
217 | static int hc_interrupt(ohci_t *ohci); |
218 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, | |
219 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
220 | struct devrequest *setup, urb_priv_t *urb, |
221 | int interval); | |
6651c140 HG |
222 | static int ep_link(ohci_t * ohci, ed_t * ed); |
223 | static int ep_unlink(ohci_t * ohci, ed_t * ed); | |
224 | static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, | |
225 | unsigned long pipe, int interval, int load); | |
226 | ||
227 | /*-------------------------------------------------------------------------*/ | |
228 | ||
229 | /* TDs ... */ | |
230 | static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev) | |
231 | { | |
232 | int i; | |
233 | struct td *td; | |
234 | ||
235 | td = NULL; | |
236 | for (i = 0; i < NUM_TD; i++) | |
237 | { | |
238 | if (ohci_dev->tds[i].usb_dev == NULL) | |
239 | { | |
240 | td = &ohci_dev->tds[i]; | |
241 | td->usb_dev = usb_dev; | |
242 | break; | |
243 | } | |
244 | } | |
245 | ||
246 | return td; | |
247 | } | |
248 | ||
249 | static inline void ed_free(struct ed *ed) | |
250 | { | |
251 | ed->usb_dev = NULL; | |
252 | } | |
3e326ece MK |
253 | |
254 | /*-------------------------------------------------------------------------* | |
255 | * URB support functions | |
256 | *-------------------------------------------------------------------------*/ | |
257 | ||
258 | /* free HCD-private data associated with this URB */ | |
259 | ||
6f5794a6 | 260 | static void urb_free_priv(urb_priv_t *urb) |
3e326ece MK |
261 | { |
262 | int i; | |
263 | int last; | |
6f5794a6 | 264 | struct td *td; |
3e326ece MK |
265 | |
266 | last = urb->length - 1; | |
267 | if (last >= 0) { | |
268 | for (i = 0; i <= last; i++) { | |
269 | td = urb->td[i]; | |
270 | if (td) { | |
271 | td->usb_dev = NULL; | |
272 | urb->td[i] = NULL; | |
273 | } | |
274 | } | |
275 | } | |
4dae14ce | 276 | free(urb); |
3e326ece MK |
277 | } |
278 | ||
279 | /*-------------------------------------------------------------------------*/ | |
280 | ||
281 | #ifdef DEBUG | |
c5613df5 | 282 | static int sohci_get_current_frame_number(ohci_t *ohci); |
3e326ece MK |
283 | |
284 | /* debug| print the main components of an URB | |
285 | * small: 0) header + data packets 1) just header */ | |
286 | ||
c5613df5 | 287 | static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, |
6f5794a6 RB |
288 | unsigned long pipe, void *buffer, int transfer_len, |
289 | struct devrequest *setup, char *str, int small) | |
3e326ece | 290 | { |
6f5794a6 | 291 | dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", |
3e326ece | 292 | str, |
c5613df5 | 293 | sohci_get_current_frame_number(ohci), |
6f5794a6 RB |
294 | usb_pipedevice(pipe), |
295 | usb_pipeendpoint(pipe), | |
296 | usb_pipeout(pipe)? 'O': 'I', | |
297 | usb_pipetype(pipe) < 2 ? \ | |
298 | (usb_pipeint(pipe)? "INTR": "ISOC"): \ | |
299 | (usb_pipecontrol(pipe)? "CTRL": "BULK"), | |
4dae14ce | 300 | (purb ? purb->actual_length : 0), |
3e326ece MK |
301 | transfer_len, dev->status); |
302 | #ifdef OHCI_VERBOSE_DEBUG | |
303 | if (!small) { | |
304 | int i, len; | |
305 | ||
6f5794a6 RB |
306 | if (usb_pipecontrol(pipe)) { |
307 | printf(__FILE__ ": cmd(8):"); | |
3e326ece | 308 | for (i = 0; i < 8 ; i++) |
6f5794a6 RB |
309 | printf(" %02x", ((__u8 *) setup) [i]); |
310 | printf("\n"); | |
3e326ece MK |
311 | } |
312 | if (transfer_len > 0 && buffer) { | |
6f5794a6 | 313 | printf(__FILE__ ": data(%d/%d):", |
4dae14ce | 314 | (purb ? purb->actual_length : 0), |
3e326ece | 315 | transfer_len); |
6f5794a6 | 316 | len = usb_pipeout(pipe)? transfer_len: |
4dae14ce | 317 | (purb ? purb->actual_length : 0); |
3e326ece | 318 | for (i = 0; i < 16 && i < len; i++) |
6f5794a6 RB |
319 | printf(" %02x", ((__u8 *) buffer) [i]); |
320 | printf("%s\n", i < len? "...": ""); | |
3e326ece MK |
321 | } |
322 | } | |
323 | #endif | |
324 | } | |
325 | ||
6f5794a6 RB |
326 | /* just for debugging; prints non-empty branches of the int ed tree |
327 | * inclusive iso eds */ | |
328 | void ep_print_int_eds(ohci_t *ohci, char *str) | |
329 | { | |
3e326ece | 330 | int i, j; |
6f5794a6 RB |
331 | __u32 *ed_p; |
332 | for (i = 0; i < 32; i++) { | |
3e326ece MK |
333 | j = 5; |
334 | ed_p = &(ohci->hcca->int_table [i]); | |
335 | if (*ed_p == 0) | |
336 | continue; | |
8d005ef8 | 337 | invalidate_dcache_ed(ed_p); |
6f5794a6 | 338 | printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); |
3e326ece MK |
339 | while (*ed_p != 0 && j--) { |
340 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
8d005ef8 | 341 | invalidate_dcache_ed(ed); |
6f5794a6 | 342 | printf(" ed: %4x;", ed->hwINFO); |
3e326ece MK |
343 | ed_p = &ed->hwNextED; |
344 | } | |
6f5794a6 | 345 | printf("\n"); |
3e326ece MK |
346 | } |
347 | } | |
348 | ||
6f5794a6 | 349 | static void ohci_dump_intr_mask(char *label, __u32 mask) |
3e326ece | 350 | { |
6f5794a6 | 351 | dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
3e326ece MK |
352 | label, |
353 | mask, | |
354 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
355 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
356 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
357 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
358 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
359 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
360 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
361 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
362 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
363 | ); | |
364 | } | |
365 | ||
6f5794a6 | 366 | static void maybe_print_eds(char *label, __u32 value) |
3e326ece MK |
367 | { |
368 | ed_t *edp = (ed_t *)value; | |
369 | ||
370 | if (value) { | |
6f5794a6 | 371 | dbg("%s %08x", label, value); |
8d005ef8 | 372 | invalidate_dcache_ed(edp); |
6f5794a6 RB |
373 | dbg("%08x", edp->hwINFO); |
374 | dbg("%08x", edp->hwTailP); | |
375 | dbg("%08x", edp->hwHeadP); | |
376 | dbg("%08x", edp->hwNextED); | |
3e326ece MK |
377 | } |
378 | } | |
379 | ||
6f5794a6 | 380 | static char *hcfs2string(int state) |
3e326ece MK |
381 | { |
382 | switch (state) { | |
6f5794a6 RB |
383 | case OHCI_USB_RESET: return "reset"; |
384 | case OHCI_USB_RESUME: return "resume"; | |
385 | case OHCI_USB_OPER: return "operational"; | |
386 | case OHCI_USB_SUSPEND: return "suspend"; | |
3e326ece MK |
387 | } |
388 | return "?"; | |
389 | } | |
390 | ||
391 | /* dump control and status registers */ | |
6f5794a6 | 392 | static void ohci_dump_status(ohci_t *controller) |
3e326ece MK |
393 | { |
394 | struct ohci_regs *regs = controller->regs; | |
395 | __u32 temp; | |
396 | ||
a5496a18 | 397 | temp = ohci_readl(®s->revision) & 0xff; |
3e326ece | 398 | if (temp != 0x10) |
6f5794a6 | 399 | dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
3e326ece | 400 | |
a5496a18 | 401 | temp = ohci_readl(®s->control); |
6f5794a6 | 402 | dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, |
3e326ece MK |
403 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", |
404 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
405 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
6f5794a6 | 406 | hcfs2string(temp & OHCI_CTRL_HCFS), |
3e326ece MK |
407 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", |
408 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
409 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
410 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
411 | temp & OHCI_CTRL_CBSR | |
412 | ); | |
413 | ||
a5496a18 | 414 | temp = ohci_readl(®s->cmdstatus); |
6f5794a6 | 415 | dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, |
3e326ece MK |
416 | (temp & OHCI_SOC) >> 16, |
417 | (temp & OHCI_OCR) ? " OCR" : "", | |
418 | (temp & OHCI_BLF) ? " BLF" : "", | |
419 | (temp & OHCI_CLF) ? " CLF" : "", | |
420 | (temp & OHCI_HCR) ? " HCR" : "" | |
421 | ); | |
422 | ||
a5496a18 BB |
423 | ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); |
424 | ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); | |
3e326ece | 425 | |
a5496a18 BB |
426 | maybe_print_eds("ed_periodcurrent", |
427 | ohci_readl(®s->ed_periodcurrent)); | |
3e326ece | 428 | |
a5496a18 BB |
429 | maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); |
430 | maybe_print_eds("ed_controlcurrent", | |
431 | ohci_readl(®s->ed_controlcurrent)); | |
3e326ece | 432 | |
a5496a18 BB |
433 | maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); |
434 | maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); | |
3e326ece | 435 | |
a5496a18 | 436 | maybe_print_eds("donehead", ohci_readl(®s->donehead)); |
3e326ece MK |
437 | } |
438 | ||
6f5794a6 | 439 | static void ohci_dump_roothub(ohci_t *controller, int verbose) |
3e326ece MK |
440 | { |
441 | __u32 temp, ndp, i; | |
442 | ||
6f5794a6 | 443 | temp = roothub_a(controller); |
3e326ece MK |
444 | ndp = (temp & RH_A_NDP); |
445 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
446 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
447 | #endif |
448 | if (verbose) { | |
6f5794a6 | 449 | dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
3e326ece MK |
450 | ((temp & RH_A_POTPGT) >> 24) & 0xff, |
451 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
452 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
453 | (temp & RH_A_DT) ? " DT" : "", | |
454 | (temp & RH_A_NPS) ? " NPS" : "", | |
455 | (temp & RH_A_PSM) ? " PSM" : "", | |
456 | ndp | |
457 | ); | |
6f5794a6 RB |
458 | temp = roothub_b(controller); |
459 | dbg("roothub.b: %08x PPCM=%04x DR=%04x", | |
3e326ece MK |
460 | temp, |
461 | (temp & RH_B_PPCM) >> 16, | |
462 | (temp & RH_B_DR) | |
463 | ); | |
6f5794a6 RB |
464 | temp = roothub_status(controller); |
465 | dbg("roothub.status: %08x%s%s%s%s%s%s", | |
3e326ece MK |
466 | temp, |
467 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
468 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
469 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
470 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
471 | (temp & RH_HS_OCI) ? " OCI" : "", | |
472 | (temp & RH_HS_LPS) ? " LPS" : "" | |
473 | ); | |
474 | } | |
475 | ||
476 | for (i = 0; i < ndp; i++) { | |
6f5794a6 RB |
477 | temp = roothub_portstatus(controller, i); |
478 | dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
3e326ece MK |
479 | i, |
480 | temp, | |
481 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
482 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
483 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
484 | (temp & RH_PS_PESC) ? " PESC" : "", | |
485 | (temp & RH_PS_CSC) ? " CSC" : "", | |
486 | ||
487 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
488 | (temp & RH_PS_PPS) ? " PPS" : "", | |
489 | (temp & RH_PS_PRS) ? " PRS" : "", | |
490 | (temp & RH_PS_POCI) ? " POCI" : "", | |
491 | (temp & RH_PS_PSS) ? " PSS" : "", | |
492 | ||
493 | (temp & RH_PS_PES) ? " PES" : "", | |
494 | (temp & RH_PS_CCS) ? " CCS" : "" | |
495 | ); | |
496 | } | |
497 | } | |
498 | ||
6f5794a6 | 499 | static void ohci_dump(ohci_t *controller, int verbose) |
3e326ece | 500 | { |
6f5794a6 | 501 | dbg("OHCI controller usb-%s state", controller->slot_name); |
3e326ece MK |
502 | |
503 | /* dumps some of the state we know about */ | |
6f5794a6 | 504 | ohci_dump_status(controller); |
3e326ece | 505 | if (verbose) |
6f5794a6 | 506 | ep_print_int_eds(controller, "hcca"); |
8d005ef8 | 507 | invalidate_dcache_hcca(controller->hcca); |
6f5794a6 RB |
508 | dbg("hcca frame #%04x", controller->hcca->frame_no); |
509 | ohci_dump_roothub(controller, 1); | |
2596f5b9 | 510 | } |
3e326ece MK |
511 | #endif /* DEBUG */ |
512 | ||
513 | /*-------------------------------------------------------------------------* | |
514 | * Interface functions (URB) | |
515 | *-------------------------------------------------------------------------*/ | |
516 | ||
517 | /* get a transfer request */ | |
518 | ||
19d95d57 HG |
519 | int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, |
520 | struct devrequest *setup) | |
3e326ece | 521 | { |
6f5794a6 | 522 | ed_t *ed; |
4dae14ce | 523 | urb_priv_t *purb_priv = urb; |
3e326ece | 524 | int i, size = 0; |
4dae14ce ZW |
525 | struct usb_device *dev = urb->dev; |
526 | unsigned long pipe = urb->pipe; | |
527 | void *buffer = urb->transfer_buffer; | |
528 | int transfer_len = urb->transfer_buffer_length; | |
529 | int interval = urb->interval; | |
3e326ece | 530 | |
3e326ece MK |
531 | /* when controller's hung, permit only roothub cleanup attempts |
532 | * such as powering down ports */ | |
533 | if (ohci->disabled) { | |
534 | err("sohci_submit_job: EPIPE"); | |
535 | return -1; | |
536 | } | |
ae79f606 | 537 | |
6f5794a6 RB |
538 | /* we're about to begin a new transaction here so mark the |
539 | * URB unfinished */ | |
4dae14ce | 540 | urb->finished = 0; |
3e326ece MK |
541 | |
542 | /* every endpoint has a ed, locate and fill it */ | |
19d95d57 | 543 | ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); |
6f5794a6 | 544 | if (!ed) { |
3e326ece MK |
545 | err("sohci_submit_job: ENOMEM"); |
546 | return -1; | |
547 | } | |
548 | ||
549 | /* for the private part of the URB we need the number of TDs (size) */ | |
6f5794a6 RB |
550 | switch (usb_pipetype(pipe)) { |
551 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
552 | size = (transfer_len - 1) / 4096 + 1; | |
553 | break; | |
554 | case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
555 | size = (transfer_len == 0)? 2: | |
556 | (transfer_len - 1) / 4096 + 3; | |
557 | break; | |
558 | case PIPE_INTERRUPT: /* 1 TD */ | |
559 | size = 1; | |
560 | break; | |
3e326ece MK |
561 | } |
562 | ||
4dae14ce ZW |
563 | ed->purb = urb; |
564 | ||
3e326ece MK |
565 | if (size >= (N_URB_TD - 1)) { |
566 | err("need %d TDs, only have %d", size, N_URB_TD); | |
567 | return -1; | |
568 | } | |
3e326ece MK |
569 | purb_priv->pipe = pipe; |
570 | ||
571 | /* fill the private part of the URB */ | |
572 | purb_priv->length = size; | |
573 | purb_priv->ed = ed; | |
574 | purb_priv->actual_length = 0; | |
575 | ||
576 | /* allocate the TDs */ | |
577 | /* note that td[0] was allocated in ep_add_ed */ | |
578 | for (i = 0; i < size; i++) { | |
3c5497d8 | 579 | purb_priv->td[i] = td_alloc(ohci_dev, dev); |
3e326ece MK |
580 | if (!purb_priv->td[i]) { |
581 | purb_priv->length = i; | |
6f5794a6 | 582 | urb_free_priv(purb_priv); |
3e326ece MK |
583 | err("sohci_submit_job: ENOMEM"); |
584 | return -1; | |
585 | } | |
586 | } | |
587 | ||
588 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
6f5794a6 | 589 | urb_free_priv(purb_priv); |
3e326ece MK |
590 | err("sohci_submit_job: EINVAL"); |
591 | return -1; | |
592 | } | |
593 | ||
594 | /* link the ed into a chain if is not already */ | |
595 | if (ed->state != ED_OPER) | |
6f5794a6 | 596 | ep_link(ohci, ed); |
3e326ece MK |
597 | |
598 | /* fill the TDs and link it to the ed */ | |
c5613df5 | 599 | td_submit_job(ohci, dev, pipe, buffer, transfer_len, |
6f5794a6 | 600 | setup, purb_priv, interval); |
3e326ece MK |
601 | |
602 | return 0; | |
603 | } | |
604 | ||
605 | /*-------------------------------------------------------------------------*/ | |
606 | ||
607 | #ifdef DEBUG | |
608 | /* tell us the current USB frame number */ | |
c5613df5 | 609 | static int sohci_get_current_frame_number(ohci_t *ohci) |
3e326ece | 610 | { |
8d005ef8 | 611 | invalidate_dcache_hcca(ohci->hcca); |
6f5794a6 | 612 | return m16_swap(ohci->hcca->frame_no); |
3e326ece MK |
613 | } |
614 | #endif | |
615 | ||
4dae14ce ZW |
616 | /*-------------------------------------------------------------------------* |
617 | * ED handling functions | |
618 | *-------------------------------------------------------------------------*/ | |
619 | ||
620 | /* search for the right branch to insert an interrupt ed into the int tree | |
621 | * do some load ballancing; | |
622 | * returns the branch and | |
623 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
624 | ||
6f5794a6 | 625 | static int ep_int_ballance(ohci_t *ohci, int interval, int load) |
4dae14ce ZW |
626 | { |
627 | int i, branch = 0; | |
628 | ||
629 | /* search for the least loaded interrupt endpoint | |
630 | * branch of all 32 branches | |
631 | */ | |
632 | for (i = 0; i < 32; i++) | |
633 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
634 | branch = i; | |
635 | ||
636 | branch = branch % interval; | |
637 | for (i = branch; i < 32; i += interval) | |
638 | ohci->ohci_int_load [i] += load; | |
639 | ||
640 | return branch; | |
641 | } | |
642 | ||
643 | /*-------------------------------------------------------------------------*/ | |
644 | ||
645 | /* 2^int( ld (inter)) */ | |
646 | ||
6f5794a6 | 647 | static int ep_2_n_interval(int inter) |
4dae14ce ZW |
648 | { |
649 | int i; | |
6f5794a6 | 650 | for (i = 0; ((inter >> i) > 1) && (i < 5); i++); |
4dae14ce ZW |
651 | return 1 << i; |
652 | } | |
653 | ||
654 | /*-------------------------------------------------------------------------*/ | |
655 | ||
656 | /* the int tree is a binary tree | |
6f5794a6 RB |
657 | * in order to process it sequentially the indexes of the branches have to |
658 | * be mapped the mapping reverses the bits of a word of num_bits length */ | |
659 | static int ep_rev(int num_bits, int word) | |
4dae14ce ZW |
660 | { |
661 | int i, wout = 0; | |
662 | ||
663 | for (i = 0; i < num_bits; i++) | |
664 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
665 | return wout; | |
666 | } | |
667 | ||
3e326ece MK |
668 | /*-------------------------------------------------------------------------* |
669 | * ED handling functions | |
670 | *-------------------------------------------------------------------------*/ | |
671 | ||
672 | /* link an ed into one of the HC chains */ | |
673 | ||
6f5794a6 | 674 | static int ep_link(ohci_t *ohci, ed_t *edi) |
3e326ece MK |
675 | { |
676 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
677 | int int_branch; |
678 | int i; | |
679 | int inter; | |
680 | int interval; | |
681 | int load; | |
6f5794a6 | 682 | __u32 *ed_p; |
3e326ece MK |
683 | |
684 | ed->state = ED_OPER; | |
4dae14ce | 685 | ed->int_interval = 0; |
3e326ece MK |
686 | |
687 | switch (ed->type) { | |
688 | case PIPE_CONTROL: | |
689 | ed->hwNextED = 0; | |
8d005ef8 | 690 | flush_dcache_ed(ed); |
6f5794a6 | 691 | if (ohci->ed_controltail == NULL) |
a5496a18 | 692 | ohci_writel(ed, &ohci->regs->ed_controlhead); |
6f5794a6 RB |
693 | else |
694 | ohci->ed_controltail->hwNextED = | |
695 | m32_swap((unsigned long)ed); | |
696 | ||
3e326ece MK |
697 | ed->ed_prev = ohci->ed_controltail; |
698 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
699 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
700 | ohci->hc_control |= OHCI_CTRL_CLE; | |
a5496a18 | 701 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
702 | } |
703 | ohci->ed_controltail = edi; | |
704 | break; | |
705 | ||
706 | case PIPE_BULK: | |
707 | ed->hwNextED = 0; | |
8d005ef8 | 708 | flush_dcache_ed(ed); |
6f5794a6 | 709 | if (ohci->ed_bulktail == NULL) |
a5496a18 | 710 | ohci_writel(ed, &ohci->regs->ed_bulkhead); |
6f5794a6 RB |
711 | else |
712 | ohci->ed_bulktail->hwNextED = | |
713 | m32_swap((unsigned long)ed); | |
714 | ||
3e326ece MK |
715 | ed->ed_prev = ohci->ed_bulktail; |
716 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
717 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
718 | ohci->hc_control |= OHCI_CTRL_BLE; | |
a5496a18 | 719 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
720 | } |
721 | ohci->ed_bulktail = edi; | |
722 | break; | |
4dae14ce ZW |
723 | |
724 | case PIPE_INTERRUPT: | |
725 | load = ed->int_load; | |
6f5794a6 | 726 | interval = ep_2_n_interval(ed->int_period); |
4dae14ce | 727 | ed->int_interval = interval; |
6f5794a6 | 728 | int_branch = ep_int_ballance(ohci, interval, load); |
4dae14ce ZW |
729 | ed->int_branch = int_branch; |
730 | ||
6f5794a6 | 731 | for (i = 0; i < ep_rev(6, interval); i += inter) { |
4dae14ce | 732 | inter = 1; |
6f5794a6 RB |
733 | for (ed_p = &(ohci->hcca->int_table[\ |
734 | ep_rev(5, i) + int_branch]); | |
735 | (*ed_p != 0) && | |
736 | (((ed_t *)ed_p)->int_interval >= interval); | |
4dae14ce | 737 | ed_p = &(((ed_t *)ed_p)->hwNextED)) |
6f5794a6 RB |
738 | inter = ep_rev(6, |
739 | ((ed_t *)ed_p)->int_interval); | |
4dae14ce | 740 | ed->hwNextED = *ed_p; |
8d005ef8 | 741 | flush_dcache_ed(ed); |
4a8527ef | 742 | *ed_p = m32_swap((unsigned long)ed); |
8d005ef8 | 743 | flush_dcache_hcca(ohci->hcca); |
4dae14ce ZW |
744 | } |
745 | break; | |
3e326ece MK |
746 | } |
747 | return 0; | |
748 | } | |
749 | ||
750 | /*-------------------------------------------------------------------------*/ | |
751 | ||
4dae14ce | 752 | /* scan the periodic table to find and unlink this ED */ |
6f5794a6 RB |
753 | static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, |
754 | unsigned index, unsigned period) | |
4dae14ce | 755 | { |
8d005ef8 HG |
756 | __maybe_unused unsigned long aligned_ed_p; |
757 | ||
4dae14ce ZW |
758 | for (; index < NUM_INTS; index += period) { |
759 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
760 | ||
761 | /* ED might have been unlinked through another path */ | |
762 | while (*ed_p != 0) { | |
6f5794a6 RB |
763 | if (((struct ed *) |
764 | m32_swap((unsigned long)ed_p)) == ed) { | |
4dae14ce | 765 | *ed_p = ed->hwNextED; |
8d005ef8 HG |
766 | #ifdef CONFIG_DM_USB |
767 | aligned_ed_p = (unsigned long)ed_p; | |
768 | aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1); | |
769 | flush_dcache_range(aligned_ed_p, | |
770 | aligned_ed_p + ARCH_DMA_MINALIGN); | |
771 | #endif | |
4dae14ce ZW |
772 | break; |
773 | } | |
6f5794a6 RB |
774 | ed_p = &(((struct ed *) |
775 | m32_swap((unsigned long)ed_p))->hwNextED); | |
4dae14ce ZW |
776 | } |
777 | } | |
778 | } | |
779 | ||
3e326ece MK |
780 | /* unlink an ed from one of the HC chains. |
781 | * just the link to the ed is unlinked. | |
782 | * the link from the ed still points to another operational ed or 0 | |
783 | * so the HC can eventually finish the processing of the unlinked ed */ | |
784 | ||
6f5794a6 | 785 | static int ep_unlink(ohci_t *ohci, ed_t *edi) |
3e326ece | 786 | { |
53e336e9 | 787 | volatile ed_t *ed = edi; |
4dae14ce | 788 | int i; |
53e336e9 | 789 | |
6f5794a6 | 790 | ed->hwINFO |= m32_swap(OHCI_ED_SKIP); |
8d005ef8 | 791 | flush_dcache_ed(ed); |
3e326ece MK |
792 | |
793 | switch (ed->type) { | |
794 | case PIPE_CONTROL: | |
795 | if (ed->ed_prev == NULL) { | |
796 | if (!ed->hwNextED) { | |
797 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
a5496a18 BB |
798 | ohci_writel(ohci->hc_control, |
799 | &ohci->regs->control); | |
3e326ece | 800 | } |
a5496a18 | 801 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 802 | &ohci->regs->ed_controlhead); |
3e326ece MK |
803 | } else { |
804 | ed->ed_prev->hwNextED = ed->hwNextED; | |
8d005ef8 | 805 | flush_dcache_ed(ed->ed_prev); |
3e326ece MK |
806 | } |
807 | if (ohci->ed_controltail == ed) { | |
808 | ohci->ed_controltail = ed->ed_prev; | |
809 | } else { | |
6f5794a6 RB |
810 | ((ed_t *)m32_swap( |
811 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
812 | } |
813 | break; | |
814 | ||
815 | case PIPE_BULK: | |
816 | if (ed->ed_prev == NULL) { | |
817 | if (!ed->hwNextED) { | |
818 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
a5496a18 BB |
819 | ohci_writel(ohci->hc_control, |
820 | &ohci->regs->control); | |
3e326ece | 821 | } |
a5496a18 | 822 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 823 | &ohci->regs->ed_bulkhead); |
3e326ece MK |
824 | } else { |
825 | ed->ed_prev->hwNextED = ed->hwNextED; | |
8d005ef8 | 826 | flush_dcache_ed(ed->ed_prev); |
3e326ece MK |
827 | } |
828 | if (ohci->ed_bulktail == ed) { | |
829 | ohci->ed_bulktail = ed->ed_prev; | |
830 | } else { | |
6f5794a6 RB |
831 | ((ed_t *)m32_swap( |
832 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
833 | } |
834 | break; | |
4dae14ce ZW |
835 | |
836 | case PIPE_INTERRUPT: | |
6f5794a6 | 837 | periodic_unlink(ohci, ed, 0, 1); |
4dae14ce ZW |
838 | for (i = ed->int_branch; i < 32; i += ed->int_interval) |
839 | ohci->ohci_int_load[i] -= ed->int_load; | |
840 | break; | |
3e326ece MK |
841 | } |
842 | ed->state = ED_UNLINK; | |
843 | return 0; | |
844 | } | |
845 | ||
3e326ece MK |
846 | /*-------------------------------------------------------------------------*/ |
847 | ||
ddf83a2f MK |
848 | /* add/reinit an endpoint; this should be done once at the |
849 | * usb_set_configuration command, but the USB stack is a little bit | |
850 | * stateless so we do it at every transaction if the state of the ed | |
851 | * is ED_NEW then a dummy td is added and the state is changed to | |
852 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
853 | * info fields are setted anyway even though most of them should not | |
854 | * change | |
855 | */ | |
19d95d57 HG |
856 | static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, |
857 | unsigned long pipe, int interval, int load) | |
3e326ece MK |
858 | { |
859 | td_t *td; | |
860 | ed_t *ed_ret; | |
861 | volatile ed_t *ed; | |
862 | ||
19d95d57 | 863 | ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | |
6f5794a6 | 864 | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; |
3e326ece MK |
865 | |
866 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
867 | err("ep_add_ed: pending delete"); | |
868 | /* pending delete request */ | |
869 | return NULL; | |
870 | } | |
871 | ||
872 | if (ed->state == ED_NEW) { | |
3e326ece | 873 | /* dummy td; end of td list for ed */ |
3c5497d8 | 874 | td = td_alloc(ohci_dev, usb_dev); |
6f5794a6 | 875 | ed->hwTailP = m32_swap((unsigned long)td); |
3e326ece MK |
876 | ed->hwHeadP = ed->hwTailP; |
877 | ed->state = ED_UNLINK; | |
6f5794a6 | 878 | ed->type = usb_pipetype(pipe); |
19d95d57 | 879 | ohci_dev->ed_cnt++; |
3e326ece MK |
880 | } |
881 | ||
6f5794a6 RB |
882 | ed->hwINFO = m32_swap(usb_pipedevice(pipe) |
883 | | usb_pipeendpoint(pipe) << 7 | |
884 | | (usb_pipeisoc(pipe)? 0x8000: 0) | |
885 | | (usb_pipecontrol(pipe)? 0: \ | |
886 | (usb_pipeout(pipe)? 0x800: 0x1000)) | |
c60795f4 | 887 | | (usb_dev->speed == USB_SPEED_LOW) << 13 |
6f5794a6 | 888 | | usb_maxpacket(usb_dev, pipe) << 16); |
3e326ece | 889 | |
4dae14ce ZW |
890 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
891 | ed->int_period = interval; | |
892 | ed->int_load = load; | |
893 | } | |
894 | ||
8d005ef8 HG |
895 | flush_dcache_ed(ed); |
896 | ||
3e326ece MK |
897 | return ed_ret; |
898 | } | |
899 | ||
900 | /*-------------------------------------------------------------------------* | |
901 | * TD handling functions | |
902 | *-------------------------------------------------------------------------*/ | |
903 | ||
904 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
905 | ||
6f5794a6 | 906 | static void td_fill(ohci_t *ohci, unsigned int info, |
3e326ece MK |
907 | void *data, int len, |
908 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
909 | { | |
910 | volatile td_t *td, *td_pt; | |
911 | #ifdef OHCI_FILL_TRACE | |
912 | int i; | |
913 | #endif | |
914 | ||
915 | if (index > urb_priv->length) { | |
916 | err("index > length"); | |
917 | return; | |
918 | } | |
919 | /* use this td as the next dummy */ | |
920 | td_pt = urb_priv->td [index]; | |
921 | td_pt->hwNextTD = 0; | |
8d005ef8 | 922 | flush_dcache_td(td_pt); |
3e326ece MK |
923 | |
924 | /* fill the old dummy TD */ | |
6f5794a6 RB |
925 | td = urb_priv->td [index] = |
926 | (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); | |
3e326ece MK |
927 | |
928 | td->ed = urb_priv->ed; | |
929 | td->next_dl_td = NULL; | |
930 | td->index = index; | |
931 | td->data = (__u32)data; | |
932 | #ifdef OHCI_FILL_TRACE | |
48867208 | 933 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
3e326ece | 934 | for (i = 0; i < len; i++) |
6f5794a6 | 935 | printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); |
3e326ece MK |
936 | printf("\n"); |
937 | } | |
938 | #endif | |
939 | if (!len) | |
940 | data = 0; | |
941 | ||
6f5794a6 RB |
942 | td->hwINFO = m32_swap(info); |
943 | td->hwCBP = m32_swap((unsigned long)data); | |
3e326ece | 944 | if (data) |
6f5794a6 | 945 | td->hwBE = m32_swap((unsigned long)(data + len - 1)); |
3e326ece MK |
946 | else |
947 | td->hwBE = 0; | |
6f5794a6 RB |
948 | |
949 | td->hwNextTD = m32_swap((unsigned long)td_pt); | |
8d005ef8 | 950 | flush_dcache_td(td); |
3e326ece MK |
951 | |
952 | /* append to queue */ | |
953 | td->ed->hwTailP = td->hwNextTD; | |
8d005ef8 | 954 | flush_dcache_ed(td->ed); |
3e326ece MK |
955 | } |
956 | ||
957 | /*-------------------------------------------------------------------------*/ | |
958 | ||
959 | /* prepare all TDs of a transfer */ | |
960 | ||
c5613df5 HG |
961 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, |
962 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
963 | struct devrequest *setup, urb_priv_t *urb, |
964 | int interval) | |
3e326ece | 965 | { |
3e326ece MK |
966 | int data_len = transfer_len; |
967 | void *data; | |
968 | int cnt = 0; | |
969 | __u32 info = 0; | |
970 | unsigned int toggle = 0; | |
971 | ||
8d005ef8 HG |
972 | flush_dcache_buffer(buffer, data_len); |
973 | ||
6f5794a6 RB |
974 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle |
975 | * bits for reseting */ | |
976 | if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { | |
3e326ece MK |
977 | toggle = TD_T_TOGGLE; |
978 | } else { | |
979 | toggle = TD_T_DATA0; | |
6f5794a6 RB |
980 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
981 | usb_pipeout(pipe), 1); | |
3e326ece MK |
982 | } |
983 | urb->td_cnt = 0; | |
984 | if (data_len) | |
985 | data = buffer; | |
986 | else | |
987 | data = 0; | |
988 | ||
6f5794a6 | 989 | switch (usb_pipetype(pipe)) { |
3e326ece | 990 | case PIPE_BULK: |
6f5794a6 | 991 | info = usb_pipeout(pipe)? |
3e326ece | 992 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; |
6f5794a6 RB |
993 | while (data_len > 4096) { |
994 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), | |
995 | data, 4096, dev, cnt, urb); | |
3e326ece MK |
996 | data += 4096; data_len -= 4096; cnt++; |
997 | } | |
6f5794a6 | 998 | info = usb_pipeout(pipe)? |
3e326ece | 999 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; |
6f5794a6 RB |
1000 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, |
1001 | data_len, dev, cnt, urb); | |
3e326ece MK |
1002 | cnt++; |
1003 | ||
6f5794a6 RB |
1004 | if (!ohci->sleeping) { |
1005 | /* start bulk list */ | |
a5496a18 | 1006 | ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); |
6f5794a6 | 1007 | } |
3e326ece MK |
1008 | break; |
1009 | ||
1010 | case PIPE_CONTROL: | |
6f5794a6 | 1011 | /* Setup phase */ |
3e326ece | 1012 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; |
8d005ef8 | 1013 | flush_dcache_buffer(setup, 8); |
6f5794a6 RB |
1014 | td_fill(ohci, info, setup, 8, dev, cnt++, urb); |
1015 | ||
1016 | /* Optional Data phase */ | |
3e326ece | 1017 | if (data_len > 0) { |
6f5794a6 RB |
1018 | info = usb_pipeout(pipe)? |
1019 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : | |
1020 | TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
3e326ece | 1021 | /* NOTE: mishandles transfers >8K, some >4K */ |
6f5794a6 RB |
1022 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
1023 | } | |
1024 | ||
1025 | /* Status phase */ | |
cae01cb2 | 1026 | info = (usb_pipeout(pipe) || data_len == 0) ? |
6f5794a6 RB |
1027 | TD_CC | TD_DP_IN | TD_T_DATA1: |
1028 | TD_CC | TD_DP_OUT | TD_T_DATA1; | |
1029 | td_fill(ohci, info, data, 0, dev, cnt++, urb); | |
1030 | ||
1031 | if (!ohci->sleeping) { | |
1032 | /* start Control list */ | |
a5496a18 | 1033 | ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); |
3e326ece | 1034 | } |
3e326ece | 1035 | break; |
4dae14ce ZW |
1036 | |
1037 | case PIPE_INTERRUPT: | |
6f5794a6 | 1038 | info = usb_pipeout(urb->pipe)? |
4dae14ce ZW |
1039 | TD_CC | TD_DP_OUT | toggle: |
1040 | TD_CC | TD_R | TD_DP_IN | toggle; | |
6f5794a6 | 1041 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
4dae14ce | 1042 | break; |
3e326ece MK |
1043 | } |
1044 | if (urb->length != cnt) | |
1045 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
1046 | } | |
1047 | ||
1048 | /*-------------------------------------------------------------------------* | |
1049 | * Done List handling functions | |
1050 | *-------------------------------------------------------------------------*/ | |
1051 | ||
3e326ece MK |
1052 | /* calculate the transfer length and update the urb */ |
1053 | ||
6f5794a6 | 1054 | static void dl_transfer_length(td_t *td) |
3e326ece | 1055 | { |
6bc52ef3 | 1056 | __u32 tdBE, tdCBP; |
4dae14ce | 1057 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece | 1058 | |
6f5794a6 RB |
1059 | tdBE = m32_swap(td->hwBE); |
1060 | tdCBP = m32_swap(td->hwCBP); | |
3e326ece | 1061 | |
48867208 | 1062 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
3e326ece MK |
1063 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
1064 | if (tdBE != 0) { | |
1065 | if (td->hwCBP == 0) | |
1066 | lurb_priv->actual_length += tdBE - td->data + 1; | |
1067 | else | |
1068 | lurb_priv->actual_length += tdCBP - td->data; | |
1069 | } | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | /*-------------------------------------------------------------------------*/ | |
6f5794a6 RB |
1074 | static void check_status(td_t *td_list) |
1075 | { | |
1076 | urb_priv_t *lurb_priv = td_list->ed->purb; | |
1077 | int urb_len = lurb_priv->length; | |
1078 | __u32 *phwHeadP = &td_list->ed->hwHeadP; | |
1079 | int cc; | |
1080 | ||
1081 | cc = TD_CC_GET(m32_swap(td_list->hwINFO)); | |
1082 | if (cc) { | |
1083 | err(" USB-error: %s (%x)", cc_to_string[cc], cc); | |
1084 | ||
8d005ef8 | 1085 | invalidate_dcache_ed(td_list->ed); |
6f5794a6 RB |
1086 | if (*phwHeadP & m32_swap(0x1)) { |
1087 | if (lurb_priv && | |
1088 | ((td_list->index + 1) < urb_len)) { | |
1089 | *phwHeadP = | |
1090 | (lurb_priv->td[urb_len - 1]->hwNextTD &\ | |
1091 | m32_swap(0xfffffff0)) | | |
1092 | (*phwHeadP & m32_swap(0x2)); | |
1093 | ||
1094 | lurb_priv->td_cnt += urb_len - | |
1095 | td_list->index - 1; | |
1096 | } else | |
1097 | *phwHeadP &= m32_swap(0xfffffff2); | |
8d005ef8 | 1098 | flush_dcache_ed(td_list->ed); |
6f5794a6 RB |
1099 | } |
1100 | #ifdef CONFIG_MPC5200 | |
1101 | td_list->hwNextTD = 0; | |
8d005ef8 | 1102 | flush_dcache_td(td_list); |
6f5794a6 RB |
1103 | #endif |
1104 | } | |
1105 | } | |
3e326ece MK |
1106 | |
1107 | /* replies to the request have to be on a FIFO basis so | |
1108 | * we reverse the reversed done-list */ | |
6f5794a6 | 1109 | static td_t *dl_reverse_done_list(ohci_t *ohci) |
3e326ece MK |
1110 | { |
1111 | __u32 td_list_hc; | |
1112 | td_t *td_rev = NULL; | |
1113 | td_t *td_list = NULL; | |
3e326ece | 1114 | |
8d005ef8 | 1115 | invalidate_dcache_hcca(ohci->hcca); |
6f5794a6 | 1116 | td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; |
3e326ece | 1117 | ohci->hcca->done_head = 0; |
8d005ef8 | 1118 | flush_dcache_hcca(ohci->hcca); |
3e326ece MK |
1119 | |
1120 | while (td_list_hc) { | |
1121 | td_list = (td_t *)td_list_hc; | |
8d005ef8 | 1122 | invalidate_dcache_td(td_list); |
6f5794a6 | 1123 | check_status(td_list); |
3e326ece MK |
1124 | td_list->next_dl_td = td_rev; |
1125 | td_rev = td_list; | |
6f5794a6 | 1126 | td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; |
3e326ece MK |
1127 | } |
1128 | return td_list; | |
1129 | } | |
1130 | ||
6f5794a6 | 1131 | /*-------------------------------------------------------------------------*/ |
3e326ece MK |
1132 | /*-------------------------------------------------------------------------*/ |
1133 | ||
6f5794a6 RB |
1134 | static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) |
1135 | { | |
1136 | if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) | |
47976d2c | 1137 | urb->finished = 1; |
6f5794a6 RB |
1138 | else |
1139 | dbg("finish_urb: strange.., ED state %x, \n", status); | |
1140 | } | |
1141 | ||
1142 | /* | |
1143 | * Used to take back a TD from the host controller. This would normally be | |
1144 | * called from within dl_done_list, however it may be called directly if the | |
1145 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1146 | * two frames). This bug has been observed on ZF Micro systems. | |
1147 | */ | |
1148 | static int takeback_td(ohci_t *ohci, td_t *td_list) | |
3e326ece | 1149 | { |
3e326ece | 1150 | ed_t *ed; |
6f5794a6 | 1151 | int cc; |
3e326ece MK |
1152 | int stat = 0; |
1153 | /* urb_t *urb; */ | |
1154 | urb_priv_t *lurb_priv; | |
1155 | __u32 tdINFO, edHeadP, edTailP; | |
1156 | ||
8d005ef8 | 1157 | invalidate_dcache_td(td_list); |
6f5794a6 | 1158 | tdINFO = m32_swap(td_list->hwINFO); |
3e326ece | 1159 | |
6f5794a6 RB |
1160 | ed = td_list->ed; |
1161 | lurb_priv = ed->purb; | |
3e326ece | 1162 | |
6f5794a6 | 1163 | dl_transfer_length(td_list); |
3e326ece | 1164 | |
6f5794a6 | 1165 | lurb_priv->td_cnt++; |
3e326ece | 1166 | |
6f5794a6 RB |
1167 | /* error code of transfer */ |
1168 | cc = TD_CC_GET(tdINFO); | |
1169 | if (cc) { | |
1170 | err("USB-error: %s (%x)", cc_to_string[cc], cc); | |
1171 | stat = cc_to_error[cc]; | |
1172 | } | |
ae79f606 | 1173 | |
6f5794a6 RB |
1174 | /* see if this done list makes for all TD's of current URB, |
1175 | * and mark the URB finished if so */ | |
1176 | if (lurb_priv->td_cnt == lurb_priv->length) | |
1177 | finish_urb(ohci, lurb_priv, ed->state); | |
1178 | ||
1179 | dbg("dl_done_list: processing TD %x, len %x\n", | |
1180 | lurb_priv->td_cnt, lurb_priv->length); | |
1181 | ||
48867208 | 1182 | if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { |
8d005ef8 | 1183 | invalidate_dcache_ed(ed); |
6f5794a6 RB |
1184 | edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; |
1185 | edTailP = m32_swap(ed->hwTailP); | |
1186 | ||
1187 | /* unlink eds if they are not busy */ | |
1188 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1189 | ep_unlink(ohci, ed); | |
1190 | } | |
1191 | return stat; | |
1192 | } | |
3e326ece | 1193 | |
6f5794a6 RB |
1194 | static int dl_done_list(ohci_t *ohci) |
1195 | { | |
1196 | int stat = 0; | |
1197 | td_t *td_list = dl_reverse_done_list(ohci); | |
1198 | ||
1199 | while (td_list) { | |
1200 | td_t *td_next = td_list->next_dl_td; | |
1201 | stat = takeback_td(ohci, td_list); | |
1202 | td_list = td_next; | |
3e326ece MK |
1203 | } |
1204 | return stat; | |
1205 | } | |
1206 | ||
1207 | /*-------------------------------------------------------------------------* | |
1208 | * Virtual Root Hub | |
1209 | *-------------------------------------------------------------------------*/ | |
1210 | ||
eb838e7d | 1211 | #include <usbroothubdes.h> |
3e326ece MK |
1212 | |
1213 | /* Hub class-specific descriptor is constructed dynamically */ | |
1214 | ||
3e326ece MK |
1215 | /*-------------------------------------------------------------------------*/ |
1216 | ||
1217 | #define OK(x) len = (x); break | |
1218 | #ifdef DEBUG | |
a5496a18 | 1219 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ |
c5613df5 | 1220 | &ohci->regs->roothub.status); } |
6f5794a6 | 1221 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ |
c5613df5 | 1222 | (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } |
3e326ece | 1223 | #else |
c5613df5 | 1224 | #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) |
a5496a18 | 1225 | #define WR_RH_PORTSTAT(x) ohci_writel((x), \ |
c5613df5 | 1226 | &ohci->regs->roothub.portstatus[wIndex-1]) |
3e326ece | 1227 | #endif |
c5613df5 HG |
1228 | #define RD_RH_STAT roothub_status(ohci) |
1229 | #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) | |
3e326ece MK |
1230 | |
1231 | /* request to virtual root hub */ | |
1232 | ||
1233 | int rh_check_port_status(ohci_t *controller) | |
1234 | { | |
1235 | __u32 temp, ndp, i; | |
1236 | int res; | |
1237 | ||
1238 | res = -1; | |
6f5794a6 | 1239 | temp = roothub_a(controller); |
3e326ece MK |
1240 | ndp = (temp & RH_A_NDP); |
1241 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1242 | ndp = (ndp == 2) ? 1:0; | |
1243 | #endif | |
1244 | for (i = 0; i < ndp; i++) { | |
6f5794a6 | 1245 | temp = roothub_portstatus(controller, i); |
3e326ece MK |
1246 | /* check for a device disconnect */ |
1247 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1248 | (RH_PS_PESC | RH_PS_CSC)) && | |
1249 | ((temp & RH_PS_CCS) == 0)) { | |
1250 | res = i; | |
1251 | break; | |
1252 | } | |
1253 | } | |
1254 | return res; | |
1255 | } | |
1256 | ||
c5613df5 HG |
1257 | static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, |
1258 | unsigned long pipe, void *buffer, int transfer_len, | |
1259 | struct devrequest *cmd) | |
3e326ece | 1260 | { |
6f5794a6 | 1261 | void *data = buffer; |
3e326ece MK |
1262 | int leni = transfer_len; |
1263 | int len = 0; | |
1264 | int stat = 0; | |
3e326ece MK |
1265 | __u16 bmRType_bReq; |
1266 | __u16 wValue; | |
1267 | __u16 wIndex; | |
1268 | __u16 wLength; | |
f1273f11 | 1269 | ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); |
5f6aa03f | 1270 | |
3e326ece | 1271 | #ifdef DEBUG |
c5613df5 | 1272 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1273 | cmd, "SUB(rh)", usb_pipein(pipe)); |
3e326ece | 1274 | #else |
8f761f02 | 1275 | ohci_mdelay(1); |
3e326ece | 1276 | #endif |
48867208 | 1277 | if (usb_pipeint(pipe)) { |
3e326ece MK |
1278 | info("Root-Hub submit IRQ: NOT implemented"); |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
6f5794a6 RB |
1283 | wValue = le16_to_cpu(cmd->value); |
1284 | wIndex = le16_to_cpu(cmd->index); | |
1285 | wLength = le16_to_cpu(cmd->length); | |
3e326ece MK |
1286 | |
1287 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1288 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1289 | ||
1290 | switch (bmRType_bReq) { | |
1291 | /* Request Destination: | |
1292 | without flags: Device, | |
1293 | RH_INTERFACE: interface, | |
1294 | RH_ENDPOINT: endpoint, | |
1295 | RH_CLASS means HUB here, | |
1296 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1297 | */ | |
1298 | ||
1299 | case RH_GET_STATUS: | |
f1273f11 | 1300 | *(u16 *)databuf = cpu_to_le16(1); |
6f5794a6 | 1301 | OK(2); |
3e326ece | 1302 | case RH_GET_STATUS | RH_INTERFACE: |
f1273f11 | 1303 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1304 | OK(2); |
3e326ece | 1305 | case RH_GET_STATUS | RH_ENDPOINT: |
f1273f11 | 1306 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1307 | OK(2); |
3e326ece | 1308 | case RH_GET_STATUS | RH_CLASS: |
f1273f11 | 1309 | *(u32 *)databuf = cpu_to_le32( |
3e326ece | 1310 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); |
6f5794a6 | 1311 | OK(4); |
3e326ece | 1312 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
f1273f11 | 1313 | *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); |
6f5794a6 | 1314 | OK(4); |
3e326ece MK |
1315 | |
1316 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1317 | switch (wValue) { | |
6f5794a6 RB |
1318 | case (RH_ENDPOINT_STALL): |
1319 | OK(0); | |
3e326ece MK |
1320 | } |
1321 | break; | |
1322 | ||
1323 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1324 | switch (wValue) { | |
6f5794a6 RB |
1325 | case RH_C_HUB_LOCAL_POWER: |
1326 | OK(0); | |
1327 | case (RH_C_HUB_OVER_CURRENT): | |
1328 | WR_RH_STAT(RH_HS_OCIC); | |
1329 | OK(0); | |
3e326ece MK |
1330 | } |
1331 | break; | |
1332 | ||
1333 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1334 | switch (wValue) { | |
6f5794a6 RB |
1335 | case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); |
1336 | case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); | |
1337 | case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); | |
1338 | case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); | |
1339 | case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); | |
1340 | case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); | |
1341 | case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); | |
1342 | case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); | |
3e326ece MK |
1343 | } |
1344 | break; | |
1345 | ||
1346 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1347 | switch (wValue) { | |
6f5794a6 RB |
1348 | case (RH_PORT_SUSPEND): |
1349 | WR_RH_PORTSTAT(RH_PS_PSS); OK(0); | |
1350 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1351 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1352 | WR_RH_PORTSTAT(RH_PS_PRS); | |
1353 | OK(0); | |
1354 | case (RH_PORT_POWER): | |
1355 | WR_RH_PORTSTAT(RH_PS_PPS); | |
6f5794a6 RB |
1356 | OK(0); |
1357 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1358 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1359 | WR_RH_PORTSTAT(RH_PS_PES); | |
1360 | OK(0); | |
3e326ece MK |
1361 | } |
1362 | break; | |
1363 | ||
6f5794a6 | 1364 | case RH_SET_ADDRESS: |
c5613df5 | 1365 | ohci->rh.devnum = wValue; |
6f5794a6 | 1366 | OK(0); |
3e326ece MK |
1367 | |
1368 | case RH_GET_DESCRIPTOR: | |
1369 | switch ((wValue & 0xff00) >> 8) { | |
6f5794a6 RB |
1370 | case (0x01): /* device descriptor */ |
1371 | len = min_t(unsigned int, | |
1372 | leni, | |
1373 | min_t(unsigned int, | |
1374 | sizeof(root_hub_dev_des), | |
1375 | wLength)); | |
f1273f11 | 1376 | databuf = root_hub_dev_des; OK(len); |
6f5794a6 RB |
1377 | case (0x02): /* configuration descriptor */ |
1378 | len = min_t(unsigned int, | |
1379 | leni, | |
1380 | min_t(unsigned int, | |
1381 | sizeof(root_hub_config_des), | |
1382 | wLength)); | |
f1273f11 | 1383 | databuf = root_hub_config_des; OK(len); |
6f5794a6 RB |
1384 | case (0x03): /* string descriptors */ |
1385 | if (wValue == 0x0300) { | |
3e326ece | 1386 | len = min_t(unsigned int, |
6f5794a6 RB |
1387 | leni, |
1388 | min_t(unsigned int, | |
1389 | sizeof(root_hub_str_index0), | |
1390 | wLength)); | |
f1273f11 | 1391 | databuf = root_hub_str_index0; |
6f5794a6 | 1392 | OK(len); |
3e326ece | 1393 | } |
6f5794a6 RB |
1394 | if (wValue == 0x0301) { |
1395 | len = min_t(unsigned int, | |
1396 | leni, | |
1397 | min_t(unsigned int, | |
1398 | sizeof(root_hub_str_index1), | |
1399 | wLength)); | |
f1273f11 | 1400 | databuf = root_hub_str_index1; |
6f5794a6 RB |
1401 | OK(len); |
1402 | } | |
1403 | default: | |
1404 | stat = USB_ST_STALLED; | |
3e326ece MK |
1405 | } |
1406 | break; | |
1407 | ||
1408 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1409 | { | |
c5613df5 | 1410 | __u32 temp = roothub_a(ohci); |
3e326ece | 1411 | |
f1273f11 TK |
1412 | databuf[0] = 9; /* min length; */ |
1413 | databuf[1] = 0x29; | |
1414 | databuf[2] = temp & RH_A_NDP; | |
3e326ece | 1415 | #ifdef CONFIG_AT91C_PQFP_UHPBUG |
f1273f11 | 1416 | databuf[2] = (databuf[2] == 2) ? 1 : 0; |
3e326ece | 1417 | #endif |
f1273f11 | 1418 | databuf[3] = 0; |
3e326ece | 1419 | if (temp & RH_A_PSM) /* per-port power switching? */ |
f1273f11 | 1420 | databuf[3] |= 0x1; |
3e326ece | 1421 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ |
f1273f11 | 1422 | databuf[3] |= 0x10; |
6f5794a6 | 1423 | else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ |
f1273f11 | 1424 | databuf[3] |= 0x8; |
3e326ece | 1425 | |
f1273f11 TK |
1426 | databuf[4] = 0; |
1427 | databuf[5] = (temp & RH_A_POTPGT) >> 24; | |
1428 | databuf[6] = 0; | |
c5613df5 | 1429 | temp = roothub_b(ohci); |
f1273f11 TK |
1430 | databuf[7] = temp & RH_B_DR; |
1431 | if (databuf[2] < 7) { | |
1432 | databuf[8] = 0xff; | |
3e326ece | 1433 | } else { |
f1273f11 TK |
1434 | databuf[0] += 2; |
1435 | databuf[8] = (temp & RH_B_DR) >> 8; | |
1436 | databuf[10] = databuf[9] = 0xff; | |
3e326ece MK |
1437 | } |
1438 | ||
1439 | len = min_t(unsigned int, leni, | |
f1273f11 | 1440 | min_t(unsigned int, databuf[0], wLength)); |
6f5794a6 | 1441 | OK(len); |
3e326ece MK |
1442 | } |
1443 | ||
5f6aa03f | 1444 | case RH_GET_CONFIGURATION: |
f1273f11 | 1445 | databuf[0] = 0x01; |
5f6aa03f | 1446 | OK(1); |
3e326ece | 1447 | |
5f6aa03f MV |
1448 | case RH_SET_CONFIGURATION: |
1449 | WR_RH_STAT(0x10000); | |
1450 | OK(0); | |
3e326ece MK |
1451 | |
1452 | default: | |
6f5794a6 | 1453 | dbg("unsupported root hub command"); |
3e326ece MK |
1454 | stat = USB_ST_STALLED; |
1455 | } | |
1456 | ||
1457 | #ifdef DEBUG | |
c5613df5 | 1458 | ohci_dump_roothub(ohci, 1); |
3e326ece | 1459 | #else |
8f761f02 | 1460 | ohci_mdelay(1); |
3e326ece MK |
1461 | #endif |
1462 | ||
1463 | len = min_t(int, len, leni); | |
f1273f11 TK |
1464 | if (data != databuf) |
1465 | memcpy(data, databuf, len); | |
3e326ece MK |
1466 | dev->act_len = len; |
1467 | dev->status = stat; | |
1468 | ||
1469 | #ifdef DEBUG | |
c5613df5 | 1470 | pkt_print(ohci, NULL, dev, pipe, buffer, |
6f5794a6 | 1471 | transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
3e326ece | 1472 | #else |
8f761f02 | 1473 | ohci_mdelay(1); |
3e326ece MK |
1474 | #endif |
1475 | ||
1476 | return stat; | |
1477 | } | |
1478 | ||
1479 | /*-------------------------------------------------------------------------*/ | |
1480 | ||
44dbc330 HG |
1481 | static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr) |
1482 | { | |
1483 | int i; | |
1484 | ||
1485 | if (!intr) | |
1486 | return &ohci->ohci_dev; | |
1487 | ||
1488 | /* First see if we already have an ohci_dev for this dev. */ | |
1489 | for (i = 0; i < NUM_INT_DEVS; i++) { | |
1490 | if (ohci->int_dev[i].devnum == devnum) | |
1491 | return &ohci->int_dev[i]; | |
1492 | } | |
1493 | ||
1494 | /* If not then find a free one. */ | |
1495 | for (i = 0; i < NUM_INT_DEVS; i++) { | |
1496 | if (ohci->int_dev[i].devnum == -1) { | |
1497 | ohci->int_dev[i].devnum = devnum; | |
1498 | return &ohci->int_dev[i]; | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | printf("ohci: Error out of ohci_devs for interrupt endpoints\n"); | |
1503 | return NULL; | |
1504 | } | |
1505 | ||
3e326ece MK |
1506 | /* common code for handling submit messages - used for all but root hub */ |
1507 | /* accesses. */ | |
c5613df5 HG |
1508 | static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, |
1509 | unsigned long pipe, void *buffer, int transfer_len, | |
1510 | struct devrequest *setup, int interval) | |
3e326ece MK |
1511 | { |
1512 | int stat = 0; | |
1513 | int maxsize = usb_maxpacket(dev, pipe); | |
1514 | int timeout; | |
4dae14ce | 1515 | urb_priv_t *urb; |
44dbc330 | 1516 | ohci_dev_t *ohci_dev; |
4dae14ce ZW |
1517 | |
1518 | urb = malloc(sizeof(urb_priv_t)); | |
1519 | memset(urb, 0, sizeof(urb_priv_t)); | |
1520 | ||
1521 | urb->dev = dev; | |
1522 | urb->pipe = pipe; | |
1523 | urb->transfer_buffer = buffer; | |
1524 | urb->transfer_buffer_length = transfer_len; | |
1525 | urb->interval = interval; | |
3e326ece | 1526 | |
3e326ece | 1527 | #ifdef DEBUG |
4dae14ce | 1528 | urb->actual_length = 0; |
c5613df5 | 1529 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1530 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1531 | #else |
8f761f02 | 1532 | ohci_mdelay(1); |
3e326ece MK |
1533 | #endif |
1534 | if (!maxsize) { | |
1535 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1536 | pipe); | |
1537 | return -1; | |
1538 | } | |
1539 | ||
44dbc330 HG |
1540 | ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe)); |
1541 | if (!ohci_dev) | |
1542 | return -ENOMEM; | |
1543 | ||
1544 | if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) { | |
3e326ece MK |
1545 | err("sohci_submit_job failed"); |
1546 | return -1; | |
1547 | } | |
1548 | ||
ae3b770e | 1549 | #if 0 |
5b84dd67 | 1550 | mdelay(10); |
c5613df5 | 1551 | /* ohci_dump_status(ohci); */ |
ae3b770e | 1552 | #endif |
3e326ece | 1553 | |
96820a35 | 1554 | timeout = USB_TIMEOUT_MS(pipe); |
3e326ece MK |
1555 | |
1556 | /* wait for it to complete */ | |
1557 | for (;;) { | |
1558 | /* check whether the controller is done */ | |
c5613df5 | 1559 | stat = hc_interrupt(ohci); |
3e326ece MK |
1560 | if (stat < 0) { |
1561 | stat = USB_ST_CRC_ERR; | |
1562 | break; | |
1563 | } | |
ddf83a2f | 1564 | |
ddf83a2f MK |
1565 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1566 | * handle only one URB at a time, we cannot assume the | |
1567 | * transaction finished on the first successful return from | |
1568 | * hc_interrupt().. unless the flag for current URB is set, | |
1569 | * meaning that all TD's to/from device got actually | |
1570 | * transferred and processed. If the current URB is not | |
1571 | * finished we need to re-iterate this loop so as | |
1572 | * hc_interrupt() gets called again as there needs to be some | |
1573 | * more TD's to process still */ | |
4dae14ce | 1574 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1575 | /* 0xff is returned for an SF-interrupt */ |
1576 | break; | |
1577 | } | |
ddf83a2f | 1578 | |
3e326ece | 1579 | if (--timeout) { |
5b84dd67 | 1580 | mdelay(1); |
4dae14ce | 1581 | if (!urb->finished) |
6f5794a6 | 1582 | dbg("*"); |
4dae14ce | 1583 | |
3e326ece | 1584 | } else { |
fa5b9baa HG |
1585 | if (!usb_pipeint(pipe)) |
1586 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1587 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1588 | urb->finished = 1; |
3e326ece MK |
1589 | stat = USB_ST_CRC_ERR; |
1590 | break; | |
1591 | } | |
1592 | } | |
3e326ece MK |
1593 | |
1594 | dev->status = stat; | |
522c9564 | 1595 | dev->act_len = urb->actual_length; |
3e326ece | 1596 | |
8d005ef8 HG |
1597 | if (usb_pipein(pipe) && dev->status == 0 && dev->act_len) |
1598 | invalidate_dcache_buffer(buffer, dev->act_len); | |
1599 | ||
3e326ece | 1600 | #ifdef DEBUG |
c5613df5 | 1601 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1602 | setup, "RET(ctlr)", usb_pipein(pipe)); |
3e326ece | 1603 | #else |
8f761f02 | 1604 | ohci_mdelay(1); |
3e326ece | 1605 | #endif |
47976d2c | 1606 | urb_free_priv(urb); |
3e326ece MK |
1607 | return 0; |
1608 | } | |
1609 | ||
58b4048f | 1610 | #ifndef CONFIG_DM_USB |
3e326ece MK |
1611 | /* submit routines called from usb.c */ |
1612 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1613 | int transfer_len) | |
1614 | { | |
1615 | info("submit_bulk_msg"); | |
c5613df5 HG |
1616 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, |
1617 | NULL, 0); | |
1618 | } | |
1619 | ||
1620 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1621 | int transfer_len, int interval) | |
1622 | { | |
1623 | info("submit_int_msg"); | |
1624 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, | |
1625 | interval); | |
3e326ece | 1626 | } |
58b4048f | 1627 | #endif |
3e326ece | 1628 | |
c5613df5 HG |
1629 | static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, |
1630 | unsigned long pipe, void *buffer, int transfer_len, | |
1631 | struct devrequest *setup) | |
3e326ece MK |
1632 | { |
1633 | int maxsize = usb_maxpacket(dev, pipe); | |
1634 | ||
1635 | info("submit_control_msg"); | |
1636 | #ifdef DEBUG | |
c5613df5 | 1637 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1638 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1639 | #else |
8f761f02 | 1640 | ohci_mdelay(1); |
3e326ece MK |
1641 | #endif |
1642 | if (!maxsize) { | |
1643 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1644 | pipe); | |
1645 | return -1; | |
1646 | } | |
c5613df5 HG |
1647 | if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { |
1648 | ohci->rh.dev = dev; | |
3e326ece | 1649 | /* root hub - redirect */ |
c5613df5 HG |
1650 | return ohci_submit_rh_msg(ohci, dev, pipe, buffer, |
1651 | transfer_len, setup); | |
3e326ece MK |
1652 | } |
1653 | ||
c5613df5 HG |
1654 | return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, |
1655 | setup, 0); | |
3e326ece MK |
1656 | } |
1657 | ||
1658 | /*-------------------------------------------------------------------------* | |
1659 | * HC functions | |
1660 | *-------------------------------------------------------------------------*/ | |
1661 | ||
1662 | /* reset the HC and BUS */ | |
1663 | ||
6f5794a6 | 1664 | static int hc_reset(ohci_t *ohci) |
3e326ece | 1665 | { |
e90fb6af YT |
1666 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1667 | pci_dev_t pdev; | |
1668 | #endif | |
3e326ece MK |
1669 | int timeout = 30; |
1670 | int smm_timeout = 50; /* 0,5 sec */ | |
1671 | ||
1672 | dbg("%s\n", __FUNCTION__); | |
1673 | ||
e90fb6af YT |
1674 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1675 | /* | |
1676 | * Some multi-function controllers (e.g. ISP1562) allow root hub | |
1677 | * resetting via EHCI registers only. | |
1678 | */ | |
1679 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); | |
1680 | if (pdev != -1) { | |
1681 | u32 base; | |
1682 | int timeout = 1000; | |
1683 | ||
1684 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
a5496a18 BB |
1685 | base += EHCI_USBCMD_OFF; |
1686 | ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); | |
e90fb6af | 1687 | |
a5496a18 | 1688 | while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { |
e90fb6af YT |
1689 | if (timeout-- <= 0) { |
1690 | printf("USB RootHub reset timed out!"); | |
1691 | break; | |
1692 | } | |
1693 | udelay(1); | |
1694 | } | |
1695 | } else | |
1696 | printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); | |
1697 | #endif | |
a5496a18 BB |
1698 | if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1699 | /* SMM owns the HC, request ownership */ | |
1700 | ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); | |
3e326ece | 1701 | info("USB HC TakeOver from SMM"); |
a5496a18 | 1702 | while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
5b84dd67 | 1703 | mdelay(10); |
3e326ece MK |
1704 | if (--smm_timeout == 0) { |
1705 | err("USB HC TakeOver failed!"); | |
1706 | return -1; | |
1707 | } | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | /* Disable HC interrupts */ | |
a5496a18 | 1712 | ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3e326ece MK |
1713 | |
1714 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1715 | ohci->slot_name, | |
a5496a18 | 1716 | ohci_readl(&ohci->regs->control)); |
3e326ece MK |
1717 | |
1718 | /* Reset USB (needed by some controllers) */ | |
53e336e9 | 1719 | ohci->hc_control = 0; |
a5496a18 | 1720 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1721 | |
1722 | /* HC Reset requires max 10 us delay */ | |
a5496a18 BB |
1723 | ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); |
1724 | while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
3e326ece MK |
1725 | if (--timeout == 0) { |
1726 | err("USB HC reset timed out!"); | |
1727 | return -1; | |
1728 | } | |
6f5794a6 | 1729 | udelay(1); |
3e326ece MK |
1730 | } |
1731 | return 0; | |
1732 | } | |
1733 | ||
1734 | /*-------------------------------------------------------------------------*/ | |
1735 | ||
1736 | /* Start an OHCI controller, set the BUS operational | |
1737 | * enable interrupts | |
1738 | * connect the virtual root hub */ | |
1739 | ||
6f5794a6 | 1740 | static int hc_start(ohci_t *ohci) |
3e326ece MK |
1741 | { |
1742 | __u32 mask; | |
1743 | unsigned int fminterval; | |
44dbc330 | 1744 | int i; |
3e326ece MK |
1745 | |
1746 | ohci->disabled = 1; | |
44dbc330 HG |
1747 | for (i = 0; i < NUM_INT_DEVS; i++) |
1748 | ohci->int_dev[i].devnum = -1; | |
3e326ece MK |
1749 | |
1750 | /* Tell the controller where the control and bulk lists are | |
1751 | * The lists are empty now. */ | |
1752 | ||
a5496a18 BB |
1753 | ohci_writel(0, &ohci->regs->ed_controlhead); |
1754 | ohci_writel(0, &ohci->regs->ed_bulkhead); | |
3e326ece | 1755 | |
a5496a18 BB |
1756 | ohci_writel((__u32)ohci->hcca, |
1757 | &ohci->regs->hcca); /* reset clears this */ | |
3e326ece MK |
1758 | |
1759 | fminterval = 0x2edf; | |
a5496a18 | 1760 | ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); |
3e326ece | 1761 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
a5496a18 BB |
1762 | ohci_writel(fminterval, &ohci->regs->fminterval); |
1763 | ohci_writel(0x628, &ohci->regs->lsthresh); | |
3e326ece MK |
1764 | |
1765 | /* start controller operations */ | |
1766 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1767 | ohci->disabled = 0; | |
a5496a18 | 1768 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1769 | |
1770 | /* disable all interrupts */ | |
1771 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1772 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1773 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
a5496a18 | 1774 | ohci_writel(mask, &ohci->regs->intrdisable); |
3e326ece MK |
1775 | /* clear all interrupts */ |
1776 | mask &= ~OHCI_INTR_MIE; | |
a5496a18 | 1777 | ohci_writel(mask, &ohci->regs->intrstatus); |
3e326ece MK |
1778 | /* Choose the interrupts we care about now - but w/o MIE */ |
1779 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
a5496a18 | 1780 | ohci_writel(mask, &ohci->regs->intrenable); |
3e326ece MK |
1781 | |
1782 | #ifdef OHCI_USE_NPS | |
1783 | /* required for AMD-756 and some Mac platforms */ | |
a5496a18 | 1784 | ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, |
3e326ece | 1785 | &ohci->regs->roothub.a); |
a5496a18 | 1786 | ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); |
3e326ece MK |
1787 | #endif /* OHCI_USE_NPS */ |
1788 | ||
3e326ece MK |
1789 | /* connect the virtual root hub */ |
1790 | ohci->rh.devnum = 0; | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
1795 | /*-------------------------------------------------------------------------*/ | |
1796 | ||
1797 | /* an interrupt happens */ | |
1798 | ||
c5613df5 | 1799 | static int hc_interrupt(ohci_t *ohci) |
3e326ece | 1800 | { |
3e326ece MK |
1801 | struct ohci_regs *regs = ohci->regs; |
1802 | int ints; | |
1803 | int stat = -1; | |
1804 | ||
8d005ef8 HG |
1805 | invalidate_dcache_hcca(ohci->hcca); |
1806 | ||
ddf83a2f | 1807 | if ((ohci->hcca->done_head != 0) && |
6f5794a6 | 1808 | !(m32_swap(ohci->hcca->done_head) & 0x01)) { |
ddf83a2f | 1809 | ints = OHCI_INTR_WDH; |
6f5794a6 | 1810 | } else { |
a5496a18 | 1811 | ints = ohci_readl(®s->intrstatus); |
6f5794a6 RB |
1812 | if (ints == ~(u32)0) { |
1813 | ohci->disabled++; | |
1814 | err("%s device removed!", ohci->slot_name); | |
1815 | return -1; | |
1816 | } else { | |
a5496a18 | 1817 | ints &= ohci_readl(®s->intrenable); |
6f5794a6 RB |
1818 | if (ints == 0) { |
1819 | dbg("hc_interrupt: returning..\n"); | |
1820 | return 0xff; | |
1821 | } | |
1822 | } | |
ddf83a2f | 1823 | } |
ae79f606 | 1824 | |
6f5794a6 RB |
1825 | /* dbg("Interrupt: %x frame: %x", ints, |
1826 | le16_to_cpu(ohci->hcca->frame_no)); */ | |
3e326ece | 1827 | |
6f5794a6 | 1828 | if (ints & OHCI_INTR_RHSC) |
ddf83a2f | 1829 | stat = 0xff; |
3e326ece MK |
1830 | |
1831 | if (ints & OHCI_INTR_UE) { | |
1832 | ohci->disabled++; | |
6f5794a6 | 1833 | err("OHCI Unrecoverable Error, controller usb-%s disabled", |
3e326ece MK |
1834 | ohci->slot_name); |
1835 | /* e.g. due to PCI Master/Target Abort */ | |
1836 | ||
1837 | #ifdef DEBUG | |
6f5794a6 | 1838 | ohci_dump(ohci, 1); |
3e326ece | 1839 | #else |
8f761f02 | 1840 | ohci_mdelay(1); |
3e326ece MK |
1841 | #endif |
1842 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1843 | /* Make some non-interrupt context restart the controller. */ | |
1844 | /* Count and limit the retries though; either hardware or */ | |
1845 | /* software errors can go forever... */ | |
6f5794a6 | 1846 | hc_reset(ohci); |
3e326ece MK |
1847 | return -1; |
1848 | } | |
1849 | ||
1850 | if (ints & OHCI_INTR_WDH) { | |
8f761f02 | 1851 | ohci_mdelay(1); |
a5496a18 BB |
1852 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
1853 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
c5613df5 | 1854 | stat = dl_done_list(ohci); |
a5496a18 BB |
1855 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
1856 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
3e326ece MK |
1857 | } |
1858 | ||
1859 | if (ints & OHCI_INTR_SO) { | |
1860 | dbg("USB Schedule overrun\n"); | |
a5496a18 | 1861 | ohci_writel(OHCI_INTR_SO, ®s->intrenable); |
3e326ece MK |
1862 | stat = -1; |
1863 | } | |
1864 | ||
1865 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1866 | if (ints & OHCI_INTR_SF) { | |
6f5794a6 | 1867 | unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; |
5b84dd67 | 1868 | mdelay(1); |
a5496a18 | 1869 | ohci_writel(OHCI_INTR_SF, ®s->intrdisable); |
3e326ece | 1870 | if (ohci->ed_rm_list[frame] != NULL) |
a5496a18 | 1871 | ohci_writel(OHCI_INTR_SF, ®s->intrenable); |
3e326ece MK |
1872 | stat = 0xff; |
1873 | } | |
1874 | ||
a5496a18 | 1875 | ohci_writel(ints, ®s->intrstatus); |
3e326ece MK |
1876 | return stat; |
1877 | } | |
1878 | ||
1879 | /*-------------------------------------------------------------------------*/ | |
1880 | ||
58b4048f HG |
1881 | #ifndef CONFIG_DM_USB |
1882 | ||
3e326ece MK |
1883 | /*-------------------------------------------------------------------------*/ |
1884 | ||
1885 | /* De-allocate all resources.. */ | |
1886 | ||
6f5794a6 | 1887 | static void hc_release_ohci(ohci_t *ohci) |
3e326ece | 1888 | { |
6f5794a6 | 1889 | dbg("USB HC release ohci usb-%s", ohci->slot_name); |
3e326ece MK |
1890 | |
1891 | if (!ohci->disabled) | |
6f5794a6 | 1892 | hc_reset(ohci); |
3e326ece MK |
1893 | } |
1894 | ||
1895 | /*-------------------------------------------------------------------------*/ | |
1896 | ||
1897 | /* | |
1898 | * low level initalisation routine, called from usb.c | |
1899 | */ | |
1900 | static char ohci_inited = 0; | |
1901 | ||
06d513ec | 1902 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
3e326ece | 1903 | { |
4dae14ce ZW |
1904 | #ifdef CONFIG_PCI_OHCI |
1905 | pci_dev_t pdev; | |
1906 | #endif | |
24e37645 | 1907 | |
6d0f6bcf | 1908 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1909 | /* cpu dependant init */ |
6f5794a6 | 1910 | if (usb_cpu_init()) |
3e326ece | 1911 | return -1; |
24e37645 | 1912 | #endif |
3e326ece | 1913 | |
6d0f6bcf | 1914 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1915 | /* board dependant init */ |
16297cfb | 1916 | if (board_usb_init(index, USB_INIT_HOST)) |
24e37645 MK |
1917 | return -1; |
1918 | #endif | |
6f5794a6 | 1919 | memset(&gohci, 0, sizeof(ohci_t)); |
3e326ece MK |
1920 | |
1921 | /* align the storage */ | |
1922 | if ((__u32)&ghcca[0] & 0xff) { | |
1923 | err("HCCA not aligned!!"); | |
1924 | return -1; | |
1925 | } | |
26548bb2 HG |
1926 | gohci.hcca = &ghcca[0]; |
1927 | info("aligned ghcca %p", gohci.hcca); | |
1928 | memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); | |
3e326ece MK |
1929 | |
1930 | gohci.disabled = 1; | |
1931 | gohci.sleeping = 0; | |
1932 | gohci.irq = -1; | |
4dae14ce | 1933 | #ifdef CONFIG_PCI_OHCI |
477434c6 | 1934 | pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); |
4dae14ce ZW |
1935 | |
1936 | if (pdev != -1) { | |
1937 | u16 vid, did; | |
1938 | u32 base; | |
1939 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
1940 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
1941 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
1942 | vid, did, (pdev >> 16) & 0xff, | |
1943 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
1944 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
1945 | printf("OHCI regs address 0x%08x\n", base); | |
1946 | gohci.regs = (struct ohci_regs *)base; | |
1947 | } else | |
1948 | return -1; | |
1949 | #else | |
6d0f6bcf | 1950 | gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; |
4dae14ce | 1951 | #endif |
3e326ece MK |
1952 | |
1953 | gohci.flags = 0; | |
6d0f6bcf | 1954 | gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; |
3e326ece MK |
1955 | |
1956 | if (hc_reset (&gohci) < 0) { | |
1957 | hc_release_ohci (&gohci); | |
1958 | err ("can't reset usb-%s", gohci.slot_name); | |
6d0f6bcf | 1959 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1960 | /* board dependant cleanup */ |
16297cfb | 1961 | board_usb_cleanup(index, USB_INIT_HOST); |
24e37645 MK |
1962 | #endif |
1963 | ||
6d0f6bcf | 1964 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1965 | /* cpu dependant cleanup */ |
ddf83a2f | 1966 | usb_cpu_init_fail(); |
24e37645 | 1967 | #endif |
3e326ece MK |
1968 | return -1; |
1969 | } | |
1970 | ||
6f5794a6 RB |
1971 | if (hc_start(&gohci) < 0) { |
1972 | err("can't start usb-%s", gohci.slot_name); | |
1973 | hc_release_ohci(&gohci); | |
3e326ece | 1974 | /* Initialization failed */ |
6d0f6bcf | 1975 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 MK |
1976 | /* board dependant cleanup */ |
1977 | usb_board_stop(); | |
1978 | #endif | |
1979 | ||
6d0f6bcf | 1980 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 MK |
1981 | /* cpu dependant cleanup */ |
1982 | usb_cpu_stop(); | |
1983 | #endif | |
3e326ece MK |
1984 | return -1; |
1985 | } | |
1986 | ||
1987 | #ifdef DEBUG | |
6f5794a6 | 1988 | ohci_dump(&gohci, 1); |
3e326ece | 1989 | #else |
8f761f02 | 1990 | ohci_mdelay(1); |
3e326ece MK |
1991 | #endif |
1992 | ohci_inited = 1; | |
1993 | return 0; | |
1994 | } | |
1995 | ||
c7e3b2b5 | 1996 | int usb_lowlevel_stop(int index) |
3e326ece MK |
1997 | { |
1998 | /* this gets called really early - before the controller has */ | |
1999 | /* even been initialized! */ | |
2000 | if (!ohci_inited) | |
2001 | return 0; | |
2002 | /* TODO release any interrupts, etc. */ | |
2003 | /* call hc_release_ohci() here ? */ | |
6f5794a6 | 2004 | hc_reset(&gohci); |
3e326ece | 2005 | |
6d0f6bcf | 2006 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
3e326ece | 2007 | /* board dependant cleanup */ |
6f5794a6 | 2008 | if (usb_board_stop()) |
3e326ece | 2009 | return -1; |
24e37645 MK |
2010 | #endif |
2011 | ||
6d0f6bcf | 2012 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 2013 | /* cpu dependant cleanup */ |
6f5794a6 | 2014 | if (usb_cpu_stop()) |
24e37645 MK |
2015 | return -1; |
2016 | #endif | |
eba1f2fc RB |
2017 | /* This driver is no longer initialised. It needs a new low-level |
2018 | * init (board/cpu) before it can be used again. */ | |
2019 | ohci_inited = 0; | |
3e326ece MK |
2020 | return 0; |
2021 | } | |
c5613df5 HG |
2022 | |
2023 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, | |
2024 | void *buffer, int transfer_len, struct devrequest *setup) | |
2025 | { | |
2026 | return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, | |
2027 | transfer_len, setup); | |
2028 | } | |
58b4048f HG |
2029 | #endif |
2030 | ||
2031 | #ifdef CONFIG_DM_USB | |
2032 | static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev, | |
2033 | unsigned long pipe, void *buffer, int length, | |
2034 | struct devrequest *setup) | |
2035 | { | |
2036 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2037 | ||
2038 | return _ohci_submit_control_msg(ohci, udev, pipe, buffer, | |
2039 | length, setup); | |
2040 | } | |
2041 | ||
2042 | static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, | |
2043 | unsigned long pipe, void *buffer, int length) | |
2044 | { | |
2045 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2046 | ||
2047 | return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0); | |
2048 | } | |
2049 | ||
2050 | static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev, | |
2051 | unsigned long pipe, void *buffer, int length, | |
2052 | int interval) | |
2053 | { | |
2054 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2055 | ||
2056 | return submit_common_msg(ohci, udev, pipe, buffer, length, | |
2057 | NULL, interval); | |
2058 | } | |
2059 | ||
2060 | int ohci_register(struct udevice *dev, struct ohci_regs *regs) | |
2061 | { | |
2062 | struct usb_bus_priv *priv = dev_get_uclass_priv(dev); | |
2063 | ohci_t *ohci = dev_get_priv(dev); | |
2064 | u32 reg; | |
2065 | ||
2066 | priv->desc_before_addr = true; | |
2067 | ||
2068 | ohci->regs = regs; | |
2069 | ohci->hcca = memalign(256, sizeof(struct ohci_hcca)); | |
2070 | if (!ohci->hcca) | |
2071 | return -ENOMEM; | |
2072 | memset(ohci->hcca, 0, sizeof(struct ohci_hcca)); | |
2073 | ||
2074 | if (hc_reset(ohci) < 0) | |
2075 | return -EIO; | |
2076 | ||
2077 | if (hc_start(ohci) < 0) | |
2078 | return -EIO; | |
2079 | ||
2080 | reg = ohci_readl(®s->revision); | |
2081 | printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf); | |
2082 | ||
2083 | return 0; | |
2084 | } | |
2085 | ||
2086 | int ohci_deregister(struct udevice *dev) | |
2087 | { | |
2088 | ohci_t *ohci = dev_get_priv(dev); | |
2089 | ||
2090 | if (hc_reset(ohci) < 0) | |
2091 | return -EIO; | |
2092 | ||
2093 | free(ohci->hcca); | |
2094 | ||
2095 | return 0; | |
2096 | } | |
2097 | ||
2098 | struct dm_usb_ops ohci_usb_ops = { | |
2099 | .control = ohci_submit_control_msg, | |
2100 | .bulk = ohci_submit_bulk_msg, | |
2101 | .interrupt = ohci_submit_int_msg, | |
2102 | }; | |
2103 | ||
2104 | #endif |