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b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
b99bd4ef
NC		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC		 6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC		 8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
ec2655a6 13 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC		 14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC		 19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC		 23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
b99bd4ef 25
42a68e18 26#include "as.h"
5287ad62 27#include <limits.h>
037e8744 28#include <stdarg.h>
c19d1205 29#define NO_RELOC 0
3882b010 30#include "safe-ctype.h"
b99bd4ef
NC		 31#include "subsegs.h"
32#include "obstack.h"
3da1d841 33#include "libiberty.h"
f263249b
RE		 34#include "opcode/arm.h"
35
b99bd4ef
NC		 36#ifdef OBJ_ELF
37#include "elf/arm.h"
a394c00f 38#include "dw2gencfi.h"
b99bd4ef
NC		 39#endif
40
f0927246
NC		 41#include "dwarf2dbg.h"
42
7ed4c4c5
NC		 43#ifdef OBJ_ELF
44/* Must be at least the size of the largest unwind opcode (currently two). */
45#define ARM_OPCODE_CHUNK_SIZE 8
46
47/* This structure holds the unwinding state. */
48
49static struct
50{
c19d1205
ZW		 51 symbolS * proc_start;
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
7ed4c4c5 55 /* The segment containing the function. */
c19d1205
ZW		 56 segT saved_seg;
57 subsegT saved_subseg;
7ed4c4c5
NC		 58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
c19d1205
ZW		 60 int opcode_count;
61 int opcode_alloc;
7ed4c4c5 62 /* The number of bytes pushed to the stack. */
c19d1205 63 offsetT frame_size;
7ed4c4c5
NC		 64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
c19d1205 67 offsetT pending_offset;
7ed4c4c5 68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW		 69 hold the reg+offset to use when restoring sp from a frame pointer. */
70 offsetT fp_offset;
71 int fp_reg;
7ed4c4c5 72 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 73 unsigned fp_used:1;
7ed4c4c5 74 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 75 unsigned sp_restored:1;
7ed4c4c5
NC		 76} unwind;
77
18a20338
CL		 78/* Whether --fdpic was given. */
79static int arm_fdpic;
80
8b1ad454
NC		 81#endif /* OBJ_ELF */
82
4962c51a
MS		 83/* Results from operand parsing worker functions. */
84
85typedef enum
86{
87 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90} parse_operand_result;
91
33a392fb
PB		 92enum arm_float_abi
93{
94 ARM_FLOAT_ABI_HARD,
95 ARM_FLOAT_ABI_SOFTFP,
96 ARM_FLOAT_ABI_SOFT
97};
98
c19d1205 99/* Types of processor to assemble for. */
b99bd4ef 100#ifndef CPU_DEFAULT
8a59fff3 101/* The code that was here used to select a default CPU depending on compiler
fa94de6b 102 pre-defines which were only present when doing native builds, thus
8a59fff3
MGD		 103 changing gas' default behaviour depending upon the build host.
104
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
b99bd4ef
NC		 107#endif
108
109#ifndef FPU_DEFAULT
c820d418
MM		 110# ifdef TE_LINUX
111# define FPU_DEFAULT FPU_ARCH_FPA
112# elif defined (TE_NetBSD)
113# ifdef OBJ_ELF
114# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115# else
116 /* Legacy a.out format. */
117# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118# endif
4e7fd91e
PB		 119# elif defined (TE_VXWORKS)
120# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM		 121# else
122 /* For backwards compatibility, default to FPA. */
123# define FPU_DEFAULT FPU_ARCH_FPA
124# endif
125#endif /* ifndef FPU_DEFAULT */
b99bd4ef 126
c19d1205 127#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 128
4d354d8b
TP		 129/* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
e74cfd16 132static arm_feature_set cpu_variant;
4d354d8b
TP		 133/* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
e74cfd16
PB		 135static arm_feature_set arm_arch_used;
136static arm_feature_set thumb_arch_used;
b99bd4ef 137
b99bd4ef 138/* Flags stored in private area of BFD structure. */
c19d1205
ZW		 139static int uses_apcs_26 = FALSE;
140static int atpcs = FALSE;
b34976b6
AM		 141static int support_interwork = FALSE;
142static int uses_apcs_float = FALSE;
c19d1205 143static int pic_code = FALSE;
845b51d6 144static int fix_v4bx = FALSE;
278df34e
NS		 145/* Warn on using deprecated features. */
146static int warn_on_deprecated = TRUE;
147
2e6976a8
DG		 148/* Understand CodeComposer Studio assembly syntax. */
149bfd_boolean codecomposer_syntax = FALSE;
03b1477f
RE		 150
151/* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
153 assembly flags. */
4d354d8b
TP		 154
155/* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157static const arm_feature_set *legacy_cpu = NULL;
158static const arm_feature_set *legacy_fpu = NULL;
159
160/* CPU, extension and FPU feature bits selected by -mcpu. */
161static const arm_feature_set *mcpu_cpu_opt = NULL;
162static arm_feature_set *mcpu_ext_opt = NULL;
163static const arm_feature_set *mcpu_fpu_opt = NULL;
164
165/* CPU, extension and FPU feature bits selected by -march. */
166static const arm_feature_set *march_cpu_opt = NULL;
167static arm_feature_set *march_ext_opt = NULL;
168static const arm_feature_set *march_fpu_opt = NULL;
169
170/* Feature bits selected by -mfpu. */
171static const arm_feature_set *mfpu_opt = NULL;
e74cfd16
PB		 172
173/* Constants for known architecture features. */
174static const arm_feature_set fpu_default = FPU_DEFAULT;
f85d59c3 175static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
e74cfd16 176static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
f85d59c3
KT		 177static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
178static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
e74cfd16
PB		 179static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
180static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
69c9e028 181#ifdef OBJ_ELF
e74cfd16 182static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
69c9e028 183#endif
e74cfd16
PB		 184static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
185
186#ifdef CPU_DEFAULT
187static const arm_feature_set cpu_default = CPU_DEFAULT;
188#endif
189
823d2571 190static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
4070243b 191static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
823d2571
TG		 192static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
193static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
194static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
195static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
196static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
197static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
e74cfd16 198static const arm_feature_set arm_ext_v4t_5 =
823d2571
TG		 199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
200static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
201static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
202static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
203static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
204static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
205static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
206static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
55e8aae7
SP		 207/* Only for compatability of hint instructions. */
208static const arm_feature_set arm_ext_v6k_v6t2 =
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
823d2571
TG		 210static const arm_feature_set arm_ext_v6_notm =
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
212static const arm_feature_set arm_ext_v6_dsp =
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
214static const arm_feature_set arm_ext_barrier =
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
216static const arm_feature_set arm_ext_msr =
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
218static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
219static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
220static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
221static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
69c9e028 222#ifdef OBJ_ELF
e7d39ed3 223static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
69c9e028 224#endif
823d2571 225static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
7e806470 226static const arm_feature_set arm_ext_m =
173205ca 227 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
16a1fa25 228 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
823d2571
TG		 229static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
230static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
231static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
232static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
233static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
ddfded2f 234static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
4ed7ed8d 235static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
16a1fa25
TP		 236static const arm_feature_set arm_ext_v8m_main =
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
e12437dc
AV		 238static const arm_feature_set arm_ext_v8_1m_main =
239ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
16a1fa25
TP		 240/* Instructions in ARMv8-M only found in M profile architectures. */
241static const arm_feature_set arm_ext_v8m_m_only =
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
ff8646ee
TP		 243static const arm_feature_set arm_ext_v6t2_v8m =
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
4ed7ed8d
TP		 245/* Instructions shared between ARMv8-A and ARMv8-M. */
246static const arm_feature_set arm_ext_atomics =
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
69c9e028 248#ifdef OBJ_ELF
15afaa63
TP		 249/* DSP instructions Tag_DSP_extension refers to. */
250static const arm_feature_set arm_ext_dsp =
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
69c9e028 252#endif
4d1464f2
MW		 253static const arm_feature_set arm_ext_ras =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
b8ec4e87
JW		 255/* FP16 instructions. */
256static const arm_feature_set arm_ext_fp16 =
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
01f48020
TC		 258static const arm_feature_set arm_ext_fp16_fml =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
dec41383
JW		 260static const arm_feature_set arm_ext_v8_2 =
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
49e8a725
SN		 262static const arm_feature_set arm_ext_v8_3 =
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
7fadb25d
SD		 264static const arm_feature_set arm_ext_sb =
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
dad0c3bf
SD		 266static const arm_feature_set arm_ext_predres =
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
e74cfd16
PB		 268
269static const arm_feature_set arm_arch_any = ARM_ANY;
49fa50ef 270#ifdef OBJ_ELF
2c6b98ea 271static const arm_feature_set fpu_any = FPU_ANY;
49fa50ef 272#endif
f85d59c3 273static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
e74cfd16
PB		 274static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
275static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
276
2d447fca 277static const arm_feature_set arm_cext_iwmmxt2 =
823d2571 278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
e74cfd16 279static const arm_feature_set arm_cext_iwmmxt =
823d2571 280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
e74cfd16 281static const arm_feature_set arm_cext_xscale =
823d2571 282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
e74cfd16 283static const arm_feature_set arm_cext_maverick =
823d2571
TG		 284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
285static const arm_feature_set fpu_fpa_ext_v1 =
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
287static const arm_feature_set fpu_fpa_ext_v2 =
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
e74cfd16 289static const arm_feature_set fpu_vfp_ext_v1xd =
823d2571
TG		 290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
291static const arm_feature_set fpu_vfp_ext_v1 =
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
293static const arm_feature_set fpu_vfp_ext_v2 =
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
295static const arm_feature_set fpu_vfp_ext_v3xd =
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
297static const arm_feature_set fpu_vfp_ext_v3 =
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
b1cc4aeb 299static const arm_feature_set fpu_vfp_ext_d32 =
823d2571
TG		 300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
301static const arm_feature_set fpu_neon_ext_v1 =
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
5287ad62 303static const arm_feature_set fpu_vfp_v3_or_neon_ext =
823d2571 304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
a7ad558c
AV		 305static const arm_feature_set mve_ext =
306 ARM_FEATURE_COPROC (FPU_MVE);
307static const arm_feature_set mve_fp_ext =
308 ARM_FEATURE_COPROC (FPU_MVE_FP);
69c9e028 309#ifdef OBJ_ELF
823d2571
TG		 310static const arm_feature_set fpu_vfp_fp16 =
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
312static const arm_feature_set fpu_neon_ext_fma =
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
69c9e028 314#endif
823d2571
TG		 315static const arm_feature_set fpu_vfp_ext_fma =
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
bca38921 317static const arm_feature_set fpu_vfp_ext_armv8 =
823d2571 318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
a715796b 319static const arm_feature_set fpu_vfp_ext_armv8xd =
823d2571 320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
bca38921 321static const arm_feature_set fpu_neon_ext_armv8 =
823d2571 322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
bca38921 323static const arm_feature_set fpu_crypto_ext_armv8 =
823d2571 324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
dd5181d5 325static const arm_feature_set crc_ext_armv8 =
823d2571 326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
d6b4b13e 327static const arm_feature_set fpu_neon_ext_v8_1 =
643afb90 328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
c604a79a
JW		 329static const arm_feature_set fpu_neon_ext_dotprod =
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
e74cfd16 331
33a392fb 332static int mfloat_abi_opt = -1;
4d354d8b
TP		 333/* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
334 directive. */
335static arm_feature_set selected_arch = ARM_ARCH_NONE;
336/* Extension feature bits selected by the last -mcpu/-march or .arch_extension
337 directive. */
338static arm_feature_set selected_ext = ARM_ARCH_NONE;
339/* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
341 directive. */
e74cfd16 342static arm_feature_set selected_cpu = ARM_ARCH_NONE;
4d354d8b
TP		 343/* FPU feature bits selected by the last -mfpu or .fpu directive. */
344static arm_feature_set selected_fpu = FPU_NONE;
345/* Feature bits selected by the last .object_arch directive. */
346static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
ee065d83 347/* Must be long enough to hold any of the names in arm_cpus. */
ef8e6722 348static char selected_cpu_name[20];
8d67f500 349
aacf0b33
KT		 350extern FLONUM_TYPE generic_floating_point_number;
351
8d67f500
NC		 352/* Return if no cpu was selected on command-line. */
353static bfd_boolean
354no_cpu_selected (void)
355{
823d2571 356 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
8d67f500
NC		 357}
358
7cc69913 359#ifdef OBJ_ELF
deeaaff8
DJ		 360# ifdef EABI_DEFAULT
361static int meabi_flags = EABI_DEFAULT;
362# else
d507cf36 363static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 364# endif
e1da3f5b 365
ee3c0378
AS		 366static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
367
e1da3f5b 368bfd_boolean
5f4273c7 369arm_is_eabi (void)
e1da3f5b
PB		 370{
371 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
372}
7cc69913 373#endif
b99bd4ef 374
b99bd4ef 375#ifdef OBJ_ELF
c19d1205 376/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC		 377symbolS * GOT_symbol;
378#endif
379
b99bd4ef
NC		 380/* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
383 instructions. */
384static int thumb_mode = 0;
8dc2430f
NC		 385/* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388#define MODE_RECORDED (1 << 4)
b99bd4ef 389
e07e6e58
NC		 390/* Specifies the intrinsic IT insn behavior mode. */
391enum implicit_it_mode
392{
393 IMPLICIT_IT_MODE_NEVER = 0x00,
394 IMPLICIT_IT_MODE_ARM = 0x01,
395 IMPLICIT_IT_MODE_THUMB = 0x02,
396 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
397};
398static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
399
c19d1205
ZW		 400/* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
402
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
407 there.)
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
410 machine code.
411
412 Important differences from the old Thumb mode:
413
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
422
423static bfd_boolean unified_syntax = FALSE;
b99bd4ef 424
bacebabc
RM		 425/* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
477330fc
RM		 427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429const char arm_symbol_chars[] = "#[]{}";
bacebabc 430
5287ad62
JB		 431enum neon_el_type
432{
dcbf9037 433 NT_invtype,
5287ad62
JB		 434 NT_untyped,
435 NT_integer,
436 NT_float,
437 NT_poly,
438 NT_signed,
dcbf9037 439 NT_unsigned
5287ad62
JB		 440};
441
442struct neon_type_el
443{
444 enum neon_el_type type;
445 unsigned size;
446};
447
448#define NEON_MAX_TYPE_ELS 4
449
450struct neon_type
451{
452 struct neon_type_el el[NEON_MAX_TYPE_ELS];
453 unsigned elems;
454};
455
5ee91343 456enum pred_instruction_type
e07e6e58 457{
5ee91343
AV		 458 OUTSIDE_PRED_INSN,
459 INSIDE_VPT_INSN,
e07e6e58
NC		 460 INSIDE_IT_INSN,
461 INSIDE_IT_LAST_INSN,
462 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
477330fc 463 if inside, should be the last one. */
e07e6e58 464 NEUTRAL_IT_INSN, /* This could be either inside or outside,
477330fc 465 i.e. BKPT and NOP. */
5ee91343
AV		 466 IT_INSN, /* The IT insn has been parsed. */
467 VPT_INSN, /* The VPT/VPST insn has been parsed. */
35c228db 468 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
5ee91343 469 a predication code. */
35c228db 470 MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */
e07e6e58
NC		 471};
472
ad6cec43
MGD		 473/* The maximum number of operands we need. */
474#define ARM_IT_MAX_OPERANDS 6
e2b0ab59 475#define ARM_IT_MAX_RELOCS 3
ad6cec43 476
b99bd4ef
NC		 477struct arm_it
478{
c19d1205 479 const char * error;
b99bd4ef 480 unsigned long instruction;
c19d1205
ZW		 481 int size;
482 int size_req;
483 int cond;
037e8744
JB		 484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
486 appropriate. */
487 int uncond_value;
5287ad62 488 struct neon_type vectype;
88714cb8
DG		 489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
491 int is_neon;
0110f2b8
PB		 492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
494 unsigned long relax;
b99bd4ef
NC		 495 struct
496 {
497 bfd_reloc_code_real_type type;
c19d1205
ZW		 498 expressionS exp;
499 int pc_rel;
e2b0ab59 500 } relocs[ARM_IT_MAX_RELOCS];
b99bd4ef 501
5ee91343 502 enum pred_instruction_type pred_insn_type;
e07e6e58 503
c19d1205
ZW		 504 struct
505 {
506 unsigned reg;
ca3f61f7 507 signed int imm;
dcbf9037 508 struct neon_type_el vectype;
ca3f61f7
NC		 509 unsigned present : 1; /* Operand present. */
510 unsigned isreg : 1; /* Operand was a register. */
f5f10c66
AV		 511 unsigned immisreg : 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
57785aa2
AV		 513 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
514 0) not scalar,
515 1) Neon scalar,
516 2) MVE scalar. */
5287ad62 517 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 518 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB		 519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 522 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5ee91343 523 unsigned isquad : 1; /* Operand is SIMD quad register. */
037e8744 524 unsigned issingle : 1; /* Operand is VFP single-precision register. */
1b883319 525 unsigned iszr : 1; /* Operand is ZR register. */
ca3f61f7
NC		 526 unsigned hasreloc : 1; /* Operand has relocation suffix. */
527 unsigned writeback : 1; /* Operand has trailing ! */
528 unsigned preind : 1; /* Preindexed address. */
529 unsigned postind : 1; /* Postindexed address. */
530 unsigned negative : 1; /* Index register was negated. */
531 unsigned shifted : 1; /* Shift applied to operation. */
532 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
ad6cec43 533 } operands[ARM_IT_MAX_OPERANDS];
b99bd4ef
NC		 534};
535
c19d1205 536static struct arm_it inst;
b99bd4ef
NC		 537
538#define NUM_FLOAT_VALS 8
539
05d2d07e 540const char * fp_const[] =
b99bd4ef
NC		 541{
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
543};
544
b99bd4ef
NC		 545LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
546
547#define FAIL (-1)
548#define SUCCESS (0)
549
550#define SUFF_S 1
551#define SUFF_D 2
552#define SUFF_E 3
553#define SUFF_P 4
554
c19d1205
ZW		 555#define CP_T_X 0x00008000
556#define CP_T_Y 0x00400000
b99bd4ef 557
c19d1205
ZW		 558#define CONDS_BIT 0x00100000
559#define LOAD_BIT 0x00100000
b99bd4ef
NC		 560
561#define DOUBLE_LOAD_FLAG 0x00000001
562
563struct asm_cond
564{
d3ce72d0 565 const char * template_name;
c921be7d 566 unsigned long value;
b99bd4ef
NC		 567};
568
c19d1205 569#define COND_ALWAYS 0xE
b99bd4ef 570
b99bd4ef
NC		 571struct asm_psr
572{
d3ce72d0 573 const char * template_name;
c921be7d 574 unsigned long field;
b99bd4ef
NC		 575};
576
62b3e311
PB		 577struct asm_barrier_opt
578{
e797f7e0
MGD		 579 const char * template_name;
580 unsigned long value;
581 const arm_feature_set arch;
62b3e311
PB		 582};
583
2d2255b5 584/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC		 585#define SPSR_BIT (1 << 22)
586
c19d1205
ZW		 587/* The individual PSR flag bits. */
588#define PSR_c (1 << 16)
589#define PSR_x (1 << 17)
590#define PSR_s (1 << 18)
591#define PSR_f (1 << 19)
b99bd4ef 592
c19d1205 593struct reloc_entry
bfae80f2 594{
0198d5e6 595 const char * name;
c921be7d 596 bfd_reloc_code_real_type reloc;
bfae80f2
RE		 597};
598
5287ad62 599enum vfp_reg_pos
bfae80f2 600{
5287ad62
JB		 601 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
602 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE		 603};
604
605enum vfp_ldstm_type
606{
607 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
608};
609
dcbf9037
JB		 610/* Bits for DEFINED field in neon_typed_alias. */
611#define NTA_HASTYPE 1
612#define NTA_HASINDEX 2
613
614struct neon_typed_alias
615{
c921be7d
NC		 616 unsigned char defined;
617 unsigned char index;
618 struct neon_type_el eltype;
dcbf9037
JB		 619};
620
c19d1205 621/* ARM register categories. This includes coprocessor numbers and various
5aa75429
TP		 622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
c19d1205 624enum arm_reg_type
bfae80f2 625{
c19d1205
ZW		 626 REG_TYPE_RN,
627 REG_TYPE_CP,
628 REG_TYPE_CN,
629 REG_TYPE_FN,
630 REG_TYPE_VFS,
631 REG_TYPE_VFD,
5287ad62 632 REG_TYPE_NQ,
037e8744 633 REG_TYPE_VFSD,
5287ad62 634 REG_TYPE_NDQ,
dec41383 635 REG_TYPE_NSD,
037e8744 636 REG_TYPE_NSDQ,
c19d1205
ZW		 637 REG_TYPE_VFC,
638 REG_TYPE_MVF,
639 REG_TYPE_MVD,
640 REG_TYPE_MVFX,
641 REG_TYPE_MVDX,
642 REG_TYPE_MVAX,
5ee91343 643 REG_TYPE_MQ,
c19d1205
ZW		 644 REG_TYPE_DSPSC,
645 REG_TYPE_MMXWR,
646 REG_TYPE_MMXWC,
647 REG_TYPE_MMXWCG,
648 REG_TYPE_XSCALE,
5ee91343 649 REG_TYPE_RNB,
1b883319 650 REG_TYPE_ZR
bfae80f2
RE		 651};
652
dcbf9037
JB		 653/* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE		 657struct reg_entry
658{
c921be7d 659 const char * name;
90ec0d68 660 unsigned int number;
c921be7d
NC		 661 unsigned char type;
662 unsigned char builtin;
663 struct neon_typed_alias * neon;
6c43fab6
RE		 664};
665
c19d1205 666/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 667const char * const reg_expected_msgs[] =
c19d1205 668{
5aa75429
TP		 669 [REG_TYPE_RN] = N_("ARM register expected"),
670 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN] = N_("co-processor register expected"),
672 [REG_TYPE_FN] = N_("FPA register expected"),
673 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
680 " expected"),
681 [REG_TYPE_VFC] = N_("VFP system register expected"),
682 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
5ee91343 692 [REG_TYPE_MQ] = N_("MVE vector register expected"),
5aa75429 693 [REG_TYPE_RNB] = N_("")
6c43fab6
RE		 694};
695
c19d1205 696/* Some well known registers that we refer to directly elsewhere. */
bd340a04 697#define REG_R12 12
c19d1205
ZW		 698#define REG_SP 13
699#define REG_LR 14
700#define REG_PC 15
404ff6b5 701
b99bd4ef
NC		 702/* ARM instructions take 4bytes in the object file, Thumb instructions
703 take 2: */
c19d1205 704#define INSN_SIZE 4
b99bd4ef
NC		 705
706struct asm_opcode
707{
708 /* Basic string to match. */
d3ce72d0 709 const char * template_name;
c19d1205
ZW		 710
711 /* Parameters to instruction. */
5be8be5d 712 unsigned int operands[8];
c19d1205
ZW		 713
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag : 4;
b99bd4ef
NC		 716
717 /* Basic instruction code. */
a302e574 718 unsigned int avalue;
b99bd4ef 719
c19d1205
ZW		 720 /* Thumb-format instruction code. */
721 unsigned int tvalue;
b99bd4ef 722
90e4755a 723 /* Which architecture variant provides this instruction. */
c921be7d
NC		 724 const arm_feature_set * avariant;
725 const arm_feature_set * tvariant;
c19d1205
ZW		 726
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode) (void);
b99bd4ef 729
c19d1205
ZW		 730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode) (void);
5ee91343
AV		 732
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred : 1;
b99bd4ef
NC		 735};
736
a737bd4d
NC		 737/* Defines for various bits that we will want to toggle. */
738#define INST_IMMEDIATE 0x02000000
739#define OFFSET_REG 0x02000000
c19d1205 740#define HWOFFSET_IMM 0x00400000
a737bd4d
NC		 741#define SHIFT_BY_REG 0x00000010
742#define PRE_INDEX 0x01000000
743#define INDEX_UP 0x00800000
744#define WRITE_BACK 0x00200000
745#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 746#define CPSI_MMOD 0x00020000
90e4755a 747
a737bd4d
NC		 748#define LITERAL_MASK 0xf000f000
749#define OPCODE_MASK 0xfe1fffff
750#define V4_STR_BIT 0x00000020
8335d6aa 751#define VLDR_VMOV_SAME 0x0040f000
90e4755a 752
efd81785
PB		 753#define T2_SUBS_PC_LR 0xf3de8f00
754
a737bd4d 755#define DATA_OP_SHIFT 21
bada4342 756#define SBIT_SHIFT 20
90e4755a 757
ef8d22e6
PB		 758#define T2_OPCODE_MASK 0xfe1fffff
759#define T2_DATA_OP_SHIFT 21
bada4342 760#define T2_SBIT_SHIFT 20
ef8d22e6 761
6530b175
NC		 762#define A_COND_MASK 0xf0000000
763#define A_PUSH_POP_OP_MASK 0x0fff0000
764
765/* Opcodes for pushing/poping registers to/from the stack. */
766#define A1_OPCODE_PUSH 0x092d0000
767#define A2_OPCODE_PUSH 0x052d0004
768#define A2_OPCODE_POP 0x049d0004
769
a737bd4d
NC		 770/* Codes to distinguish the arithmetic instructions. */
771#define OPCODE_AND 0
772#define OPCODE_EOR 1
773#define OPCODE_SUB 2
774#define OPCODE_RSB 3
775#define OPCODE_ADD 4
776#define OPCODE_ADC 5
777#define OPCODE_SBC 6
778#define OPCODE_RSC 7
779#define OPCODE_TST 8
780#define OPCODE_TEQ 9
781#define OPCODE_CMP 10
782#define OPCODE_CMN 11
783#define OPCODE_ORR 12
784#define OPCODE_MOV 13
785#define OPCODE_BIC 14
786#define OPCODE_MVN 15
90e4755a 787
ef8d22e6
PB		 788#define T2_OPCODE_AND 0
789#define T2_OPCODE_BIC 1
790#define T2_OPCODE_ORR 2
791#define T2_OPCODE_ORN 3
792#define T2_OPCODE_EOR 4
793#define T2_OPCODE_ADD 8
794#define T2_OPCODE_ADC 10
795#define T2_OPCODE_SBC 11
796#define T2_OPCODE_SUB 13
797#define T2_OPCODE_RSB 14
798
a737bd4d
NC		 799#define T_OPCODE_MUL 0x4340
800#define T_OPCODE_TST 0x4200
801#define T_OPCODE_CMN 0x42c0
802#define T_OPCODE_NEG 0x4240
803#define T_OPCODE_MVN 0x43c0
90e4755a 804
a737bd4d
NC		 805#define T_OPCODE_ADD_R3 0x1800
806#define T_OPCODE_SUB_R3 0x1a00
807#define T_OPCODE_ADD_HI 0x4400
808#define T_OPCODE_ADD_ST 0xb000
809#define T_OPCODE_SUB_ST 0xb080
810#define T_OPCODE_ADD_SP 0xa800
811#define T_OPCODE_ADD_PC 0xa000
812#define T_OPCODE_ADD_I8 0x3000
813#define T_OPCODE_SUB_I8 0x3800
814#define T_OPCODE_ADD_I3 0x1c00
815#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 816
a737bd4d
NC		 817#define T_OPCODE_ASR_R 0x4100
818#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW		 819#define T_OPCODE_LSR_R 0x40c0
820#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC		 821#define T_OPCODE_ASR_I 0x1000
822#define T_OPCODE_LSL_I 0x0000
823#define T_OPCODE_LSR_I 0x0800
b99bd4ef 824
a737bd4d
NC		 825#define T_OPCODE_MOV_I8 0x2000
826#define T_OPCODE_CMP_I8 0x2800
827#define T_OPCODE_CMP_LR 0x4280
828#define T_OPCODE_MOV_HR 0x4600
829#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 830
a737bd4d
NC		 831#define T_OPCODE_LDR_PC 0x4800
832#define T_OPCODE_LDR_SP 0x9800
833#define T_OPCODE_STR_SP 0x9000
834#define T_OPCODE_LDR_IW 0x6800
835#define T_OPCODE_STR_IW 0x6000
836#define T_OPCODE_LDR_IH 0x8800
837#define T_OPCODE_STR_IH 0x8000
838#define T_OPCODE_LDR_IB 0x7800
839#define T_OPCODE_STR_IB 0x7000
840#define T_OPCODE_LDR_RW 0x5800
841#define T_OPCODE_STR_RW 0x5000
842#define T_OPCODE_LDR_RH 0x5a00
843#define T_OPCODE_STR_RH 0x5200
844#define T_OPCODE_LDR_RB 0x5c00
845#define T_OPCODE_STR_RB 0x5400
c9b604bd 846
a737bd4d
NC		 847#define T_OPCODE_PUSH 0xb400
848#define T_OPCODE_POP 0xbc00
b99bd4ef 849
2fc8bdac 850#define T_OPCODE_BRANCH 0xe000
b99bd4ef 851
a737bd4d 852#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 853#define THUMB_PP_PC_LR 0x0100
c19d1205 854#define THUMB_LOAD_BIT 0x0800
53365c0d 855#define THUMB2_LOAD_BIT 0x00100000
c19d1205 856
5ee91343 857#define BAD_SYNTAX _("syntax error")
c19d1205 858#define BAD_ARGS _("bad arguments to instruction")
fdfde340 859#define BAD_SP _("r13 not allowed here")
c19d1205 860#define BAD_PC _("r15 not allowed here")
a302e574
AV		 861#define BAD_ODD _("Odd register not allowed here")
862#define BAD_EVEN _("Even register not allowed here")
c19d1205
ZW		 863#define BAD_COND _("instruction cannot be conditional")
864#define BAD_OVERLAP _("registers may not be the same")
865#define BAD_HIREG _("lo register required")
866#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
35c228db 867#define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
dfa9f0d5 868#define BAD_BRANCH _("branch must be last instruction in IT block")
e12437dc 869#define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
dfa9f0d5 870#define BAD_NOT_IT _("instruction not allowed in IT block")
5ee91343 871#define BAD_NOT_VPT _("instruction missing MVE vector predication code")
037e8744 872#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58 873#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
5ee91343
AV		 874#define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
e07e6e58 876#define BAD_IT_COND _("incorrect condition in IT block")
5ee91343 877#define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
e07e6e58 878#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 879#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG		 880#define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882#define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
9db2f6b4
RL		 884#define BAD_RANGE _("branch out of range")
885#define BAD_FP16 _("selected processor does not support fp16 instruction")
dd5181d5 886#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
a9f02af8 887#define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
5ee91343
AV		 888#define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
889 "block")
890#define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
891 "block")
892#define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
893 " operand")
894#define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
895 " operand")
a302e574 896#define BAD_SIMD_TYPE _("bad type in SIMD instruction")
886e1c73
AV		 897#define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900#define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
35c228db 902#define BAD_EL_TYPE _("bad element type for instruction")
1b883319 903#define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
c19d1205 904
c921be7d
NC		 905static struct hash_control * arm_ops_hsh;
906static struct hash_control * arm_cond_hsh;
5ee91343 907static struct hash_control * arm_vcond_hsh;
c921be7d
NC		 908static struct hash_control * arm_shift_hsh;
909static struct hash_control * arm_psr_hsh;
910static struct hash_control * arm_v7m_psr_hsh;
911static struct hash_control * arm_reg_hsh;
912static struct hash_control * arm_reloc_hsh;
913static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 914
b99bd4ef
NC		 915/* Stuff needed to resolve the label ambiguity
916 As:
917 ...
918 label: <insn>
919 may differ from:
920 ...
921 label:
5f4273c7 922 <insn> */
b99bd4ef
NC		 923
924symbolS * last_label_seen;
b34976b6 925static int label_is_thumb_function_name = FALSE;
e07e6e58 926
3d0c9500
NC		 927/* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
a737bd4d 929
c19d1205 930#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 931typedef struct literal_pool
b99bd4ef 932{
c921be7d
NC		 933 expressionS literals [MAX_LITERAL_POOL_SIZE];
934 unsigned int next_free_entry;
935 unsigned int id;
936 symbolS * symbol;
937 segT section;
938 subsegT sub_section;
a8040cf2
NC		 939#ifdef OBJ_ELF
940 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
941#endif
c921be7d 942 struct literal_pool * next;
8335d6aa 943 unsigned int alignment;
3d0c9500 944} literal_pool;
b99bd4ef 945
3d0c9500
NC		 946/* Pointer to a linked list of literal pools. */
947literal_pool * list_of_pools = NULL;
e27ec89e 948
2e6976a8
DG		 949typedef enum asmfunc_states
950{
951 OUTSIDE_ASMFUNC,
952 WAITING_ASMFUNC_NAME,
953 WAITING_ENDASMFUNC
954} asmfunc_states;
955
956static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
957
e07e6e58 958#ifdef OBJ_ELF
5ee91343 959# define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
e07e6e58 960#else
5ee91343 961static struct current_pred now_pred;
e07e6e58
NC		 962#endif
963
964static inline int
5ee91343 965now_pred_compatible (int cond)
e07e6e58 966{
5ee91343 967 return (cond & ~1) == (now_pred.cc & ~1);
e07e6e58
NC		 968}
969
970static inline int
971conditional_insn (void)
972{
973 return inst.cond != COND_ALWAYS;
974}
975
5ee91343 976static int in_pred_block (void);
e07e6e58 977
5ee91343 978static int handle_pred_state (void);
e07e6e58
NC		 979
980static void force_automatic_it_block_close (void);
981
c921be7d
NC		 982static void it_fsm_post_encode (void);
983
5ee91343 984#define set_pred_insn_type(type) \
e07e6e58
NC		 985 do \
986 { \
5ee91343
AV		 987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
477330fc 989 return; \
e07e6e58
NC		 990 } \
991 while (0)
992
5ee91343 993#define set_pred_insn_type_nonvoid(type, failret) \
c921be7d
NC		 994 do \
995 { \
5ee91343
AV		 996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
477330fc 998 return failret; \
c921be7d
NC		 999 } \
1000 while(0)
1001
5ee91343 1002#define set_pred_insn_type_last() \
e07e6e58
NC		 1003 do \
1004 { \
1005 if (inst.cond == COND_ALWAYS) \
5ee91343 1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
e07e6e58 1007 else \
5ee91343 1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
e07e6e58
NC		 1009 } \
1010 while (0)
1011
e39c1607
SD		 1012/* Toggle value[pos]. */
1013#define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1014
c19d1205 1015/* Pure syntax. */
b99bd4ef 1016
c19d1205
ZW		 1017/* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
2e6976a8 1019char arm_comment_chars[] = "@";
3d0c9500 1020
c19d1205
ZW		 1021/* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024/* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027/* Also note that comments like this one will always work. */
1028const char line_comment_chars[] = "#";
3d0c9500 1029
2e6976a8 1030char arm_line_separator_chars[] = ";";
b99bd4ef 1031
c19d1205
ZW		 1032/* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034const char EXP_CHARS[] = "eE";
3d0c9500 1035
c19d1205
ZW		 1036/* Chars that mean this number is a floating point constant. */
1037/* As in 0f12.456 */
1038/* or 0d1.2345e12 */
b99bd4ef 1039
5312fe52 1040const char FLT_CHARS[] = "rRsSfFdDxXeEpPHh";
3d0c9500 1041
c19d1205
ZW		 1042/* Prefix characters that indicate the start of an immediate
1043 value. */
1044#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 1045
c19d1205
ZW		 1046/* Separator character handling. */
1047
1048#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1049
5312fe52
BW		 1050enum fp_16bit_format
1051{
1052 ARM_FP16_FORMAT_IEEE = 0x1,
1053 ARM_FP16_FORMAT_ALTERNATIVE = 0x2,
1054 ARM_FP16_FORMAT_DEFAULT = 0x3
1055};
1056
1057static enum fp_16bit_format fp16_format = ARM_FP16_FORMAT_DEFAULT;
1058
1059
c19d1205
ZW		 1060static inline int
1061skip_past_char (char ** str, char c)
1062{
8ab8155f
NC		 1063 /* PR gas/14987: Allow for whitespace before the expected character. */
1064 skip_whitespace (*str);
427d0db6 1065
c19d1205
ZW		 1066 if (**str == c)
1067 {
1068 (*str)++;
1069 return SUCCESS;
3d0c9500 1070 }
c19d1205
ZW		 1071 else
1072 return FAIL;
1073}
c921be7d 1074
c19d1205 1075#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 1076
c19d1205
ZW		 1077/* Arithmetic expressions (possibly involving symbols). */
1078
1079/* Return TRUE if anything in the expression is a bignum. */
1080
0198d5e6 1081static bfd_boolean
c19d1205
ZW		 1082walk_no_bignums (symbolS * sp)
1083{
1084 if (symbol_get_value_expression (sp)->X_op == O_big)
0198d5e6 1085 return TRUE;
c19d1205
ZW		 1086
1087 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 1088 {
c19d1205
ZW		 1089 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1090 || (symbol_get_value_expression (sp)->X_op_symbol
1091 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC		 1092 }
1093
0198d5e6 1094 return FALSE;
3d0c9500
NC		 1095}
1096
0198d5e6 1097static bfd_boolean in_my_get_expression = FALSE;
c19d1205
ZW		 1098
1099/* Third argument to my_get_expression. */
1100#define GE_NO_PREFIX 0
1101#define GE_IMM_PREFIX 1
1102#define GE_OPT_PREFIX 2
5287ad62
JB		 1103/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1104 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1105#define GE_OPT_PREFIX_BIG 3
a737bd4d 1106
b99bd4ef 1107static int
c19d1205 1108my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 1109{
c19d1205 1110 char * save_in;
b99bd4ef 1111
c19d1205
ZW		 1112 /* In unified syntax, all prefixes are optional. */
1113 if (unified_syntax)
5287ad62 1114 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
477330fc 1115 : GE_OPT_PREFIX;
b99bd4ef 1116
c19d1205 1117 switch (prefix_mode)
b99bd4ef 1118 {
c19d1205
ZW		 1119 case GE_NO_PREFIX: break;
1120 case GE_IMM_PREFIX:
1121 if (!is_immediate_prefix (**str))
1122 {
1123 inst.error = _("immediate expression requires a # prefix");
1124 return FAIL;
1125 }
1126 (*str)++;
1127 break;
1128 case GE_OPT_PREFIX:
5287ad62 1129 case GE_OPT_PREFIX_BIG:
c19d1205
ZW		 1130 if (is_immediate_prefix (**str))
1131 (*str)++;
1132 break;
0198d5e6
TC		 1133 default:
1134 abort ();
c19d1205 1135 }
b99bd4ef 1136
c19d1205 1137 memset (ep, 0, sizeof (expressionS));
b99bd4ef 1138
c19d1205
ZW		 1139 save_in = input_line_pointer;
1140 input_line_pointer = *str;
0198d5e6 1141 in_my_get_expression = TRUE;
2ac93be7 1142 expression (ep);
0198d5e6 1143 in_my_get_expression = FALSE;
c19d1205 1144
f86adc07 1145 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 1146 {
f86adc07 1147 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW		 1148 *str = input_line_pointer;
1149 input_line_pointer = save_in;
1150 if (inst.error == NULL)
f86adc07
NS		 1151 inst.error = (ep->X_op == O_absent
1152 ? _("missing expression") :_("bad expression"));
c19d1205
ZW		 1153 return 1;
1154 }
b99bd4ef 1155
c19d1205
ZW		 1156 /* Get rid of any bignums now, so that we don't generate an error for which
1157 we can't establish a line number later on. Big numbers are never valid
1158 in instructions, which is where this routine is always called. */
5287ad62
JB		 1159 if (prefix_mode != GE_OPT_PREFIX_BIG
1160 && (ep->X_op == O_big
477330fc 1161 || (ep->X_add_symbol
5287ad62 1162 && (walk_no_bignums (ep->X_add_symbol)
477330fc 1163 || (ep->X_op_symbol
5287ad62 1164 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW		 1165 {
1166 inst.error = _("invalid constant");
1167 *str = input_line_pointer;
1168 input_line_pointer = save_in;
1169 return 1;
1170 }
b99bd4ef 1171
c19d1205
ZW		 1172 *str = input_line_pointer;
1173 input_line_pointer = save_in;
0198d5e6 1174 return SUCCESS;
b99bd4ef
NC		 1175}
1176
c19d1205
ZW		 1177/* Turn a string in input_line_pointer into a floating point constant
1178 of type TYPE, and store the appropriate bytes in *LITP. The number
1179 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1180 returned, or NULL on OK.
b99bd4ef 1181
c19d1205
ZW		 1182 Note that fp constants aren't represent in the normal way on the ARM.
1183 In big endian mode, things are as expected. However, in little endian
1184 mode fp constants are big-endian word-wise, and little-endian byte-wise
1185 within the words. For example, (double) 1.1 in big endian mode is
1186 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1187 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 1188
c19d1205 1189 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 1190
6d4af3c2 1191const char *
c19d1205
ZW		 1192md_atof (int type, char * litP, int * sizeP)
1193{
1194 int prec;
1195 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1196 char *t;
1197 int i;
b99bd4ef 1198
c19d1205
ZW		 1199 switch (type)
1200 {
5312fe52
BW		 1201 case 'H':
1202 case 'h':
1203 prec = 1;
1204 break;
1205
c19d1205
ZW		 1206 case 'f':
1207 case 'F':
1208 case 's':
1209 case 'S':
1210 prec = 2;
1211 break;
b99bd4ef 1212
c19d1205
ZW		 1213 case 'd':
1214 case 'D':
1215 case 'r':
1216 case 'R':
1217 prec = 4;
1218 break;
b99bd4ef 1219
c19d1205
ZW		 1220 case 'x':
1221 case 'X':
499ac353 1222 prec = 5;
c19d1205 1223 break;
b99bd4ef 1224
c19d1205
ZW		 1225 case 'p':
1226 case 'P':
499ac353 1227 prec = 5;
c19d1205 1228 break;
a737bd4d 1229
c19d1205
ZW		 1230 default:
1231 *sizeP = 0;
499ac353 1232 return _("Unrecognized or unsupported floating point constant");
c19d1205 1233 }
b99bd4ef 1234
c19d1205
ZW		 1235 t = atof_ieee (input_line_pointer, type, words);
1236 if (t)
1237 input_line_pointer = t;
499ac353 1238 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1239
72c03e30
BW		 1240 if (target_big_endian || prec == 1)
1241 for (i = 0; i < prec; i++)
1242 {
1243 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1244 litP += sizeof (LITTLENUM_TYPE);
1245 }
1246 else if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1247 for (i = prec - 1; i >= 0; i--)
1248 {
1249 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1250 litP += sizeof (LITTLENUM_TYPE);
1251 }
c19d1205 1252 else
72c03e30
BW		 1253 /* For a 4 byte float the order of elements in `words' is 1 0.
1254 For an 8 byte float the order is 1 0 3 2. */
1255 for (i = 0; i < prec; i += 2)
1256 {
1257 md_number_to_chars (litP, (valueT) words[i + 1],
1258 sizeof (LITTLENUM_TYPE));
1259 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1260 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1261 litP += 2 * sizeof (LITTLENUM_TYPE);
1262 }
b99bd4ef 1263
499ac353 1264 return NULL;
c19d1205 1265}
b99bd4ef 1266
c19d1205
ZW		 1267/* We handle all bad expressions here, so that we can report the faulty
1268 instruction in the error message. */
0198d5e6 1269
c19d1205 1270void
91d6fa6a 1271md_operand (expressionS * exp)
c19d1205
ZW		 1272{
1273 if (in_my_get_expression)
91d6fa6a 1274 exp->X_op = O_illegal;
b99bd4ef
NC		 1275}
1276
c19d1205 1277/* Immediate values. */
b99bd4ef 1278
0198d5e6 1279#ifdef OBJ_ELF
c19d1205
ZW		 1280/* Generic immediate-value read function for use in directives.
1281 Accepts anything that 'expression' can fold to a constant.
1282 *val receives the number. */
0198d5e6 1283
c19d1205
ZW		 1284static int
1285immediate_for_directive (int *val)
b99bd4ef 1286{
c19d1205
ZW		 1287 expressionS exp;
1288 exp.X_op = O_illegal;
b99bd4ef 1289
c19d1205
ZW		 1290 if (is_immediate_prefix (*input_line_pointer))
1291 {
1292 input_line_pointer++;
1293 expression (&exp);
1294 }
b99bd4ef 1295
c19d1205
ZW		 1296 if (exp.X_op != O_constant)
1297 {
1298 as_bad (_("expected #constant"));
1299 ignore_rest_of_line ();
1300 return FAIL;
1301 }
1302 *val = exp.X_add_number;
1303 return SUCCESS;
b99bd4ef 1304}
c19d1205 1305#endif
b99bd4ef 1306
c19d1205 1307/* Register parsing. */
b99bd4ef 1308
c19d1205
ZW		 1309/* Generic register parser. CCP points to what should be the
1310 beginning of a register name. If it is indeed a valid register
1311 name, advance CCP over it and return the reg_entry structure;
1312 otherwise return NULL. Does not issue diagnostics. */
1313
1314static struct reg_entry *
1315arm_reg_parse_multi (char **ccp)
b99bd4ef 1316{
c19d1205
ZW		 1317 char *start = *ccp;
1318 char *p;
1319 struct reg_entry *reg;
b99bd4ef 1320
477330fc
RM		 1321 skip_whitespace (start);
1322
c19d1205
ZW		 1323#ifdef REGISTER_PREFIX
1324 if (*start != REGISTER_PREFIX)
01cfc07f 1325 return NULL;
c19d1205
ZW		 1326 start++;
1327#endif
1328#ifdef OPTIONAL_REGISTER_PREFIX
1329 if (*start == OPTIONAL_REGISTER_PREFIX)
1330 start++;
1331#endif
b99bd4ef 1332
c19d1205
ZW		 1333 p = start;
1334 if (!ISALPHA (*p) || !is_name_beginner (*p))
1335 return NULL;
b99bd4ef 1336
c19d1205
ZW		 1337 do
1338 p++;
1339 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1340
1341 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1342
1343 if (!reg)
1344 return NULL;
1345
1346 *ccp = p;
1347 return reg;
b99bd4ef
NC		 1348}
1349
1350static int
dcbf9037 1351arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
477330fc 1352 enum arm_reg_type type)
b99bd4ef 1353{
c19d1205
ZW		 1354 /* Alternative syntaxes are accepted for a few register classes. */
1355 switch (type)
1356 {
1357 case REG_TYPE_MVF:
1358 case REG_TYPE_MVD:
1359 case REG_TYPE_MVFX:
1360 case REG_TYPE_MVDX:
1361 /* Generic coprocessor register names are allowed for these. */
79134647 1362 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW		 1363 return reg->number;
1364 break;
69b97547 1365
c19d1205
ZW		 1366 case REG_TYPE_CP:
1367 /* For backward compatibility, a bare number is valid here. */
1368 {
1369 unsigned long processor = strtoul (start, ccp, 10);
1370 if (*ccp != start && processor <= 15)
1371 return processor;
1372 }
1a0670f3 1373 /* Fall through. */
6057a28f 1374
c19d1205
ZW		 1375 case REG_TYPE_MMXWC:
1376 /* WC includes WCG. ??? I'm not sure this is true for all
1377 instructions that take WC registers. */
79134647 1378 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1379 return reg->number;
6057a28f 1380 break;
c19d1205 1381
6057a28f 1382 default:
c19d1205 1383 break;
6057a28f
NC		 1384 }
1385
dcbf9037
JB		 1386 return FAIL;
1387}
1388
1389/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1390 return value is the register number or FAIL. */
1391
1392static int
1393arm_reg_parse (char **ccp, enum arm_reg_type type)
1394{
1395 char *start = *ccp;
1396 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1397 int ret;
1398
1399 /* Do not allow a scalar (reg+index) to parse as a register. */
1400 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1401 return FAIL;
1402
1403 if (reg && reg->type == type)
1404 return reg->number;
1405
1406 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1407 return ret;
1408
c19d1205
ZW		 1409 *ccp = start;
1410 return FAIL;
1411}
69b97547 1412
dcbf9037
JB		 1413/* Parse a Neon type specifier. *STR should point at the leading '.'
1414 character. Does no verification at this stage that the type fits the opcode
1415 properly. E.g.,
1416
1417 .i32.i32.s16
1418 .s32.f32
1419 .u16
1420
1421 Can all be legally parsed by this function.
1422
1423 Fills in neon_type struct pointer with parsed information, and updates STR
1424 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1425 type, FAIL if not. */
1426
1427static int
1428parse_neon_type (struct neon_type *type, char **str)
1429{
1430 char *ptr = *str;
1431
1432 if (type)
1433 type->elems = 0;
1434
1435 while (type->elems < NEON_MAX_TYPE_ELS)
1436 {
1437 enum neon_el_type thistype = NT_untyped;
1438 unsigned thissize = -1u;
1439
1440 if (*ptr != '.')
1441 break;
1442
1443 ptr++;
1444
1445 /* Just a size without an explicit type. */
1446 if (ISDIGIT (*ptr))
1447 goto parsesize;
1448
1449 switch (TOLOWER (*ptr))
1450 {
1451 case 'i': thistype = NT_integer; break;
1452 case 'f': thistype = NT_float; break;
1453 case 'p': thistype = NT_poly; break;
1454 case 's': thistype = NT_signed; break;
1455 case 'u': thistype = NT_unsigned; break;
477330fc
RM		 1456 case 'd':
1457 thistype = NT_float;
1458 thissize = 64;
1459 ptr++;
1460 goto done;
dcbf9037
JB		 1461 default:
1462 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1463 return FAIL;
1464 }
1465
1466 ptr++;
1467
1468 /* .f is an abbreviation for .f32. */
1469 if (thistype == NT_float && !ISDIGIT (*ptr))
1470 thissize = 32;
1471 else
1472 {
1473 parsesize:
1474 thissize = strtoul (ptr, &ptr, 10);
1475
1476 if (thissize != 8 && thissize != 16 && thissize != 32
477330fc
RM		 1477 && thissize != 64)
1478 {
1479 as_bad (_("bad size %d in type specifier"), thissize);
dcbf9037
JB		 1480 return FAIL;
1481 }
1482 }
1483
037e8744 1484 done:
dcbf9037 1485 if (type)
477330fc
RM		 1486 {
1487 type->el[type->elems].type = thistype;
dcbf9037
JB		 1488 type->el[type->elems].size = thissize;
1489 type->elems++;
1490 }
1491 }
1492
1493 /* Empty/missing type is not a successful parse. */
1494 if (type->elems == 0)
1495 return FAIL;
1496
1497 *str = ptr;
1498
1499 return SUCCESS;
1500}
1501
1502/* Errors may be set multiple times during parsing or bit encoding
1503 (particularly in the Neon bits), but usually the earliest error which is set
1504 will be the most meaningful. Avoid overwriting it with later (cascading)
1505 errors by calling this function. */
1506
1507static void
1508first_error (const char *err)
1509{
1510 if (!inst.error)
1511 inst.error = err;
1512}
1513
1514/* Parse a single type, e.g. ".s32", leading period included. */
1515static int
1516parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1517{
1518 char *str = *ccp;
1519 struct neon_type optype;
1520
1521 if (*str == '.')
1522 {
1523 if (parse_neon_type (&optype, &str) == SUCCESS)
477330fc
RM		 1524 {
1525 if (optype.elems == 1)
1526 *vectype = optype.el[0];
1527 else
1528 {
1529 first_error (_("only one type should be specified for operand"));
1530 return FAIL;
1531 }
1532 }
dcbf9037 1533 else
477330fc
RM		 1534 {
1535 first_error (_("vector type expected"));
1536 return FAIL;
1537 }
dcbf9037
JB		 1538 }
1539 else
1540 return FAIL;
5f4273c7 1541
dcbf9037 1542 *ccp = str;
5f4273c7 1543
dcbf9037
JB		 1544 return SUCCESS;
1545}
1546
1547/* Special meanings for indices (which have a range of 0-7), which will fit into
1548 a 4-bit integer. */
1549
1550#define NEON_ALL_LANES 15
1551#define NEON_INTERLEAVE_LANES 14
1552
5ee91343
AV		 1553/* Record a use of the given feature. */
1554static void
1555record_feature_use (const arm_feature_set *feature)
1556{
1557 if (thumb_mode)
1558 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1559 else
1560 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1561}
1562
1563/* If the given feature available in the selected CPU, mark it as used.
1564 Returns TRUE iff feature is available. */
1565static bfd_boolean
1566mark_feature_used (const arm_feature_set *feature)
1567{
886e1c73
AV		 1568
1569 /* Do not support the use of MVE only instructions when in auto-detection or
1570 -march=all. */
1571 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1572 && ARM_CPU_IS_ANY (cpu_variant))
1573 {
1574 first_error (BAD_MVE_AUTO);
1575 return FALSE;
1576 }
5ee91343
AV		 1577 /* Ensure the option is valid on the current architecture. */
1578 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1579 return FALSE;
1580
1581 /* Add the appropriate architecture feature for the barrier option used.
1582 */
1583 record_feature_use (feature);
1584
1585 return TRUE;
1586}
1587
dcbf9037
JB		 1588/* Parse either a register or a scalar, with an optional type. Return the
1589 register number, and optionally fill in the actual type of the register
1590 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1591 type/index information in *TYPEINFO. */
1592
1593static int
1594parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
477330fc
RM		 1595 enum arm_reg_type *rtype,
1596 struct neon_typed_alias *typeinfo)
dcbf9037
JB		 1597{
1598 char *str = *ccp;
1599 struct reg_entry *reg = arm_reg_parse_multi (&str);
1600 struct neon_typed_alias atype;
1601 struct neon_type_el parsetype;
1602
1603 atype.defined = 0;
1604 atype.index = -1;
1605 atype.eltype.type = NT_invtype;
1606 atype.eltype.size = -1;
1607
1608 /* Try alternate syntax for some types of register. Note these are mutually
1609 exclusive with the Neon syntax extensions. */
1610 if (reg == NULL)
1611 {
1612 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1613 if (altreg != FAIL)
477330fc 1614 *ccp = str;
dcbf9037 1615 if (typeinfo)
477330fc 1616 *typeinfo = atype;
dcbf9037
JB		 1617 return altreg;
1618 }
1619
037e8744
JB		 1620 /* Undo polymorphism when a set of register types may be accepted. */
1621 if ((type == REG_TYPE_NDQ
1622 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1623 || (type == REG_TYPE_VFSD
477330fc 1624 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
037e8744 1625 || (type == REG_TYPE_NSDQ
477330fc
RM		 1626 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1627 || reg->type == REG_TYPE_NQ))
dec41383
JW		 1628 || (type == REG_TYPE_NSD
1629 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
f512f76f
NC		 1630 || (type == REG_TYPE_MMXWC
1631 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1632 type = (enum arm_reg_type) reg->type;
dcbf9037 1633
5ee91343
AV		 1634 if (type == REG_TYPE_MQ)
1635 {
1636 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1637 return FAIL;
1638
1639 if (!reg || reg->type != REG_TYPE_NQ)
1640 return FAIL;
1641
1642 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1643 {
1644 first_error (_("expected MVE register [q0..q7]"));
1645 return FAIL;
1646 }
1647 type = REG_TYPE_NQ;
1648 }
1649 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1650 && (type == REG_TYPE_NQ))
1651 return FAIL;
1652
1653
dcbf9037
JB		 1654 if (type != reg->type)
1655 return FAIL;
1656
1657 if (reg->neon)
1658 atype = *reg->neon;
5f4273c7 1659
dcbf9037
JB		 1660 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1661 {
1662 if ((atype.defined & NTA_HASTYPE) != 0)
477330fc
RM		 1663 {
1664 first_error (_("can't redefine type for operand"));
1665 return FAIL;
1666 }
dcbf9037
JB		 1667 atype.defined |= NTA_HASTYPE;
1668 atype.eltype = parsetype;
1669 }
5f4273c7 1670
dcbf9037
JB		 1671 if (skip_past_char (&str, '[') == SUCCESS)
1672 {
dec41383
JW		 1673 if (type != REG_TYPE_VFD
1674 && !(type == REG_TYPE_VFS
57785aa2
AV		 1675 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1676 && !(type == REG_TYPE_NQ
1677 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
477330fc 1678 {
57785aa2
AV		 1679 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1680 first_error (_("only D and Q registers may be indexed"));
1681 else
1682 first_error (_("only D registers may be indexed"));
477330fc
RM		 1683 return FAIL;
1684 }
5f4273c7 1685
dcbf9037 1686 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 1687 {
1688 first_error (_("can't change index for operand"));
1689 return FAIL;
1690 }
dcbf9037
JB		 1691
1692 atype.defined |= NTA_HASINDEX;
1693
1694 if (skip_past_char (&str, ']') == SUCCESS)
477330fc 1695 atype.index = NEON_ALL_LANES;
dcbf9037 1696 else
477330fc
RM		 1697 {
1698 expressionS exp;
dcbf9037 1699
477330fc 1700 my_get_expression (&exp, &str, GE_NO_PREFIX);
dcbf9037 1701
477330fc
RM		 1702 if (exp.X_op != O_constant)
1703 {
1704 first_error (_("constant expression required"));
1705 return FAIL;
1706 }
dcbf9037 1707
477330fc
RM		 1708 if (skip_past_char (&str, ']') == FAIL)
1709 return FAIL;
dcbf9037 1710
477330fc
RM		 1711 atype.index = exp.X_add_number;
1712 }
dcbf9037 1713 }
5f4273c7 1714
dcbf9037
JB		 1715 if (typeinfo)
1716 *typeinfo = atype;
5f4273c7 1717
dcbf9037
JB		 1718 if (rtype)
1719 *rtype = type;
5f4273c7 1720
dcbf9037 1721 *ccp = str;
5f4273c7 1722
dcbf9037
JB		 1723 return reg->number;
1724}
1725
efd6b359 1726/* Like arm_reg_parse, but also allow the following extra features:
dcbf9037
JB		 1727 - If RTYPE is non-zero, return the (possibly restricted) type of the
1728 register (e.g. Neon double or quad reg when either has been requested).
1729 - If this is a Neon vector type with additional type information, fill
1730 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1731 This function will fault on encountering a scalar. */
dcbf9037
JB		 1732
1733static int
1734arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
477330fc 1735 enum arm_reg_type *rtype, struct neon_type_el *vectype)
dcbf9037
JB		 1736{
1737 struct neon_typed_alias atype;
1738 char *str = *ccp;
1739 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1740
1741 if (reg == FAIL)
1742 return FAIL;
1743
0855e32b
NS		 1744 /* Do not allow regname(... to parse as a register. */
1745 if (*str == '(')
1746 return FAIL;
1747
dcbf9037
JB		 1748 /* Do not allow a scalar (reg+index) to parse as a register. */
1749 if ((atype.defined & NTA_HASINDEX) != 0)
1750 {
1751 first_error (_("register operand expected, but got scalar"));
1752 return FAIL;
1753 }
1754
1755 if (vectype)
1756 *vectype = atype.eltype;
1757
1758 *ccp = str;
1759
1760 return reg;
1761}
1762
1763#define NEON_SCALAR_REG(X) ((X) >> 4)
1764#define NEON_SCALAR_INDEX(X) ((X) & 15)
1765
5287ad62
JB		 1766/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1767 have enough information to be able to do a good job bounds-checking. So, we
1768 just do easy checks here, and do further checks later. */
1769
1770static int
57785aa2
AV		 1771parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1772 arm_reg_type reg_type)
5287ad62 1773{
dcbf9037 1774 int reg;
5287ad62 1775 char *str = *ccp;
dcbf9037 1776 struct neon_typed_alias atype;
57785aa2 1777 unsigned reg_size;
5f4273c7 1778
dec41383 1779 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
5f4273c7 1780
57785aa2
AV		 1781 switch (reg_type)
1782 {
1783 case REG_TYPE_VFS:
1784 reg_size = 32;
1785 break;
1786 case REG_TYPE_VFD:
1787 reg_size = 64;
1788 break;
1789 case REG_TYPE_MQ:
1790 reg_size = 128;
1791 break;
1792 default:
1793 gas_assert (0);
1794 return FAIL;
1795 }
1796
dcbf9037 1797 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1798 return FAIL;
5f4273c7 1799
57785aa2 1800 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
5287ad62 1801 {
dcbf9037 1802 first_error (_("scalar must have an index"));
5287ad62
JB		 1803 return FAIL;
1804 }
57785aa2 1805 else if (atype.index >= reg_size / elsize)
5287ad62 1806 {
dcbf9037 1807 first_error (_("scalar index out of range"));
5287ad62
JB		 1808 return FAIL;
1809 }
5f4273c7 1810
dcbf9037
JB		 1811 if (type)
1812 *type = atype.eltype;
5f4273c7 1813
5287ad62 1814 *ccp = str;
5f4273c7 1815
dcbf9037 1816 return reg * 16 + atype.index;
5287ad62
JB		 1817}
1818
4b5a202f
AV		 1819/* Types of registers in a list. */
1820
1821enum reg_list_els
1822{
1823 REGLIST_RN,
1824 REGLIST_CLRM,
1825 REGLIST_VFP_S,
efd6b359 1826 REGLIST_VFP_S_VPR,
4b5a202f 1827 REGLIST_VFP_D,
efd6b359 1828 REGLIST_VFP_D_VPR,
4b5a202f
AV		 1829 REGLIST_NEON_D
1830};
1831
c19d1205 1832/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1833
c19d1205 1834static long
4b5a202f 1835parse_reg_list (char ** strp, enum reg_list_els etype)
c19d1205 1836{
4b5a202f
AV		 1837 char *str = *strp;
1838 long range = 0;
1839 int another_range;
1840
1841 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
a737bd4d 1842
c19d1205
ZW		 1843 /* We come back here if we get ranges concatenated by '+' or '|'. */
1844 do
6057a28f 1845 {
477330fc
RM		 1846 skip_whitespace (str);
1847
c19d1205 1848 another_range = 0;
a737bd4d 1849
c19d1205
ZW		 1850 if (*str == '{')
1851 {
1852 int in_range = 0;
1853 int cur_reg = -1;
a737bd4d 1854
c19d1205
ZW		 1855 str++;
1856 do
1857 {
1858 int reg;
4b5a202f
AV		 1859 const char apsr_str[] = "apsr";
1860 int apsr_str_len = strlen (apsr_str);
6057a28f 1861
4b5a202f
AV		 1862 reg = arm_reg_parse (&str, REGLIST_RN);
1863 if (etype == REGLIST_CLRM)
c19d1205 1864 {
4b5a202f
AV		 1865 if (reg == REG_SP || reg == REG_PC)
1866 reg = FAIL;
1867 else if (reg == FAIL
1868 && !strncasecmp (str, apsr_str, apsr_str_len)
1869 && !ISALPHA (*(str + apsr_str_len)))
1870 {
1871 reg = 15;
1872 str += apsr_str_len;
1873 }
1874
1875 if (reg == FAIL)
1876 {
1877 first_error (_("r0-r12, lr or APSR expected"));
1878 return FAIL;
1879 }
1880 }
1881 else /* etype == REGLIST_RN. */
1882 {
1883 if (reg == FAIL)
1884 {
1885 first_error (_(reg_expected_msgs[REGLIST_RN]));
1886 return FAIL;
1887 }
c19d1205 1888 }
a737bd4d 1889
c19d1205
ZW		 1890 if (in_range)
1891 {
1892 int i;
a737bd4d 1893
c19d1205
ZW		 1894 if (reg <= cur_reg)
1895 {
dcbf9037 1896 first_error (_("bad range in register list"));
c19d1205
ZW		 1897 return FAIL;
1898 }
40a18ebd 1899
c19d1205
ZW		 1900 for (i = cur_reg + 1; i < reg; i++)
1901 {
1902 if (range & (1 << i))
1903 as_tsktsk
1904 (_("Warning: duplicated register (r%d) in register list"),
1905 i);
1906 else
1907 range |= 1 << i;
1908 }
1909 in_range = 0;
1910 }
a737bd4d 1911
c19d1205
ZW		 1912 if (range & (1 << reg))
1913 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1914 reg);
1915 else if (reg <= cur_reg)
1916 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1917
c19d1205
ZW		 1918 range |= 1 << reg;
1919 cur_reg = reg;
1920 }
1921 while (skip_past_comma (&str) != FAIL
1922 || (in_range = 1, *str++ == '-'));
1923 str--;
a737bd4d 1924
d996d970 1925 if (skip_past_char (&str, '}') == FAIL)
c19d1205 1926 {
dcbf9037 1927 first_error (_("missing `}'"));
c19d1205
ZW		 1928 return FAIL;
1929 }
1930 }
4b5a202f 1931 else if (etype == REGLIST_RN)
c19d1205 1932 {
91d6fa6a 1933 expressionS exp;
40a18ebd 1934
91d6fa6a 1935 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 1936 return FAIL;
40a18ebd 1937
91d6fa6a 1938 if (exp.X_op == O_constant)
c19d1205 1939 {
91d6fa6a
NC		 1940 if (exp.X_add_number
1941 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW		 1942 {
1943 inst.error = _("invalid register mask");
1944 return FAIL;
1945 }
a737bd4d 1946
91d6fa6a 1947 if ((range & exp.X_add_number) != 0)
c19d1205 1948 {
91d6fa6a 1949 int regno = range & exp.X_add_number;
a737bd4d 1950
c19d1205
ZW		 1951 regno &= -regno;
1952 regno = (1 << regno) - 1;
1953 as_tsktsk
1954 (_("Warning: duplicated register (r%d) in register list"),
1955 regno);
1956 }
a737bd4d 1957
91d6fa6a 1958 range |= exp.X_add_number;
c19d1205
ZW		 1959 }
1960 else
1961 {
e2b0ab59 1962 if (inst.relocs[0].type != 0)
c19d1205
ZW		 1963 {
1964 inst.error = _("expression too complex");
1965 return FAIL;
1966 }
a737bd4d 1967
e2b0ab59
AV		 1968 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
1969 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
1970 inst.relocs[0].pc_rel = 0;
c19d1205
ZW		 1971 }
1972 }
a737bd4d 1973
c19d1205
ZW		 1974 if (*str == '|' || *str == '+')
1975 {
1976 str++;
1977 another_range = 1;
1978 }
a737bd4d 1979 }
c19d1205 1980 while (another_range);
a737bd4d 1981
c19d1205
ZW		 1982 *strp = str;
1983 return range;
a737bd4d
NC		 1984}
1985
c19d1205
ZW		 1986/* Parse a VFP register list. If the string is invalid return FAIL.
1987 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB		 1988 register. Parses registers of type ETYPE.
1989 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1990 - Q registers can be used to specify pairs of D registers
1991 - { } can be omitted from around a singleton register list
477330fc
RM		 1992 FIXME: This is not implemented, as it would require backtracking in
1993 some cases, e.g.:
1994 vtbl.8 d3,d4,d5
1995 This could be done (the meaning isn't really ambiguous), but doesn't
1996 fit in well with the current parsing framework.
dcbf9037
JB		 1997 - 32 D registers may be used (also true for VFPv3).
1998 FIXME: Types are ignored in these register lists, which is probably a
1999 bug. */
6057a28f 2000
c19d1205 2001static int
efd6b359
AV		 2002parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
2003 bfd_boolean *partial_match)
6057a28f 2004{
037e8744 2005 char *str = *ccp;
c19d1205
ZW		 2006 int base_reg;
2007 int new_base;
21d799b5 2008 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 2009 int max_regs = 0;
c19d1205
ZW		 2010 int count = 0;
2011 int warned = 0;
2012 unsigned long mask = 0;
a737bd4d 2013 int i;
efd6b359
AV		 2014 bfd_boolean vpr_seen = FALSE;
2015 bfd_boolean expect_vpr =
2016 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
6057a28f 2017
477330fc 2018 if (skip_past_char (&str, '{') == FAIL)
5287ad62
JB		 2019 {
2020 inst.error = _("expecting {");
2021 return FAIL;
2022 }
6057a28f 2023
5287ad62 2024 switch (etype)
c19d1205 2025 {
5287ad62 2026 case REGLIST_VFP_S:
efd6b359 2027 case REGLIST_VFP_S_VPR:
c19d1205
ZW		 2028 regtype = REG_TYPE_VFS;
2029 max_regs = 32;
5287ad62 2030 break;
5f4273c7 2031
5287ad62 2032 case REGLIST_VFP_D:
efd6b359 2033 case REGLIST_VFP_D_VPR:
5287ad62 2034 regtype = REG_TYPE_VFD;
b7fc2769 2035 break;
5f4273c7 2036
b7fc2769
JB		 2037 case REGLIST_NEON_D:
2038 regtype = REG_TYPE_NDQ;
2039 break;
4b5a202f
AV		 2040
2041 default:
2042 gas_assert (0);
b7fc2769
JB		 2043 }
2044
efd6b359 2045 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
b7fc2769 2046 {
b1cc4aeb
PB		 2047 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2048 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 2049 {
2050 max_regs = 32;
2051 if (thumb_mode)
2052 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2053 fpu_vfp_ext_d32);
2054 else
2055 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2056 fpu_vfp_ext_d32);
2057 }
5287ad62 2058 else
477330fc 2059 max_regs = 16;
c19d1205 2060 }
6057a28f 2061
c19d1205 2062 base_reg = max_regs;
efd6b359 2063 *partial_match = FALSE;
a737bd4d 2064
c19d1205
ZW		 2065 do
2066 {
5287ad62 2067 int setmask = 1, addregs = 1;
efd6b359
AV		 2068 const char vpr_str[] = "vpr";
2069 int vpr_str_len = strlen (vpr_str);
dcbf9037 2070
037e8744 2071 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 2072
efd6b359
AV		 2073 if (expect_vpr)
2074 {
2075 if (new_base == FAIL
2076 && !strncasecmp (str, vpr_str, vpr_str_len)
2077 && !ISALPHA (*(str + vpr_str_len))
2078 && !vpr_seen)
2079 {
2080 vpr_seen = TRUE;
2081 str += vpr_str_len;
2082 if (count == 0)
2083 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2084 }
2085 else if (vpr_seen)
2086 {
2087 first_error (_("VPR expected last"));
2088 return FAIL;
2089 }
2090 else if (new_base == FAIL)
2091 {
2092 if (regtype == REG_TYPE_VFS)
2093 first_error (_("VFP single precision register or VPR "
2094 "expected"));
2095 else /* regtype == REG_TYPE_VFD. */
2096 first_error (_("VFP/Neon double precision register or VPR "
2097 "expected"));
2098 return FAIL;
2099 }
2100 }
2101 else if (new_base == FAIL)
a737bd4d 2102 {
dcbf9037 2103 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW		 2104 return FAIL;
2105 }
5f4273c7 2106
efd6b359
AV		 2107 *partial_match = TRUE;
2108 if (vpr_seen)
2109 continue;
2110
b7fc2769 2111 if (new_base >= max_regs)
477330fc
RM		 2112 {
2113 first_error (_("register out of range in list"));
2114 return FAIL;
2115 }
5f4273c7 2116
5287ad62
JB		 2117 /* Note: a value of 2 * n is returned for the register Q<n>. */
2118 if (regtype == REG_TYPE_NQ)
477330fc
RM		 2119 {
2120 setmask = 3;
2121 addregs = 2;
2122 }
5287ad62 2123
c19d1205
ZW		 2124 if (new_base < base_reg)
2125 base_reg = new_base;
a737bd4d 2126
5287ad62 2127 if (mask & (setmask << new_base))
c19d1205 2128 {
dcbf9037 2129 first_error (_("invalid register list"));
c19d1205 2130 return FAIL;
a737bd4d 2131 }
a737bd4d 2132
efd6b359 2133 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
c19d1205
ZW		 2134 {
2135 as_tsktsk (_("register list not in ascending order"));
2136 warned = 1;
2137 }
0bbf2aa4 2138
5287ad62
JB		 2139 mask |= setmask << new_base;
2140 count += addregs;
0bbf2aa4 2141
037e8744 2142 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW		 2143 {
2144 int high_range;
0bbf2aa4 2145
037e8744 2146 str++;
0bbf2aa4 2147
037e8744 2148 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
477330fc 2149 == FAIL)
c19d1205
ZW		 2150 {
2151 inst.error = gettext (reg_expected_msgs[regtype]);
2152 return FAIL;
2153 }
0bbf2aa4 2154
477330fc
RM		 2155 if (high_range >= max_regs)
2156 {
2157 first_error (_("register out of range in list"));
2158 return FAIL;
2159 }
b7fc2769 2160
477330fc
RM		 2161 if (regtype == REG_TYPE_NQ)
2162 high_range = high_range + 1;
5287ad62 2163
c19d1205
ZW		 2164 if (high_range <= new_base)
2165 {
2166 inst.error = _("register range not in ascending order");
2167 return FAIL;
2168 }
0bbf2aa4 2169
5287ad62 2170 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 2171 {
5287ad62 2172 if (mask & (setmask << new_base))
0bbf2aa4 2173 {
c19d1205
ZW		 2174 inst.error = _("invalid register list");
2175 return FAIL;
0bbf2aa4 2176 }
c19d1205 2177
5287ad62
JB		 2178 mask |= setmask << new_base;
2179 count += addregs;
0bbf2aa4 2180 }
0bbf2aa4 2181 }
0bbf2aa4 2182 }
037e8744 2183 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 2184
037e8744 2185 str++;
0bbf2aa4 2186
c19d1205 2187 /* Sanity check -- should have raised a parse error above. */
efd6b359 2188 if ((!vpr_seen && count == 0) || count > max_regs)
c19d1205
ZW		 2189 abort ();
2190
2191 *pbase = base_reg;
2192
efd6b359
AV		 2193 if (expect_vpr && !vpr_seen)
2194 {
2195 first_error (_("VPR expected last"));
2196 return FAIL;
2197 }
2198
c19d1205
ZW		 2199 /* Final test -- the registers must be consecutive. */
2200 mask >>= base_reg;
2201 for (i = 0; i < count; i++)
2202 {
2203 if ((mask & (1u << i)) == 0)
2204 {
2205 inst.error = _("non-contiguous register range");
2206 return FAIL;
2207 }
2208 }
2209
037e8744
JB		 2210 *ccp = str;
2211
c19d1205 2212 return count;
b99bd4ef
NC		 2213}
2214
dcbf9037
JB		 2215/* True if two alias types are the same. */
2216
c921be7d 2217static bfd_boolean
dcbf9037
JB		 2218neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2219{
2220 if (!a && !b)
c921be7d 2221 return TRUE;
5f4273c7 2222
dcbf9037 2223 if (!a || !b)
c921be7d 2224 return FALSE;
dcbf9037
JB		 2225
2226 if (a->defined != b->defined)
c921be7d 2227 return FALSE;
5f4273c7 2228
dcbf9037
JB		 2229 if ((a->defined & NTA_HASTYPE) != 0
2230 && (a->eltype.type != b->eltype.type
477330fc 2231 || a->eltype.size != b->eltype.size))
c921be7d 2232 return FALSE;
dcbf9037
JB		 2233
2234 if ((a->defined & NTA_HASINDEX) != 0
2235 && (a->index != b->index))
c921be7d 2236 return FALSE;
5f4273c7 2237
c921be7d 2238 return TRUE;
dcbf9037
JB		 2239}
2240
5287ad62
JB		 2241/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2242 The base register is put in *PBASE.
dcbf9037 2243 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB		 2244 the return value.
2245 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB		 2246 Bits [6:5] encode the list length (minus one).
2247 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 2248
5287ad62 2249#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 2250#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB		 2251#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2252
2253static int
dcbf9037 2254parse_neon_el_struct_list (char **str, unsigned *pbase,
35c228db 2255 int mve,
477330fc 2256 struct neon_type_el *eltype)
5287ad62
JB		 2257{
2258 char *ptr = *str;
2259 int base_reg = -1;
2260 int reg_incr = -1;
2261 int count = 0;
2262 int lane = -1;
2263 int leading_brace = 0;
2264 enum arm_reg_type rtype = REG_TYPE_NDQ;
35c228db
AV		 2265 const char *const incr_error = mve ? _("register stride must be 1") :
2266 _("register stride must be 1 or 2");
20203fb9 2267 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 2268 struct neon_typed_alias firsttype;
f85d59c3
KT		 2269 firsttype.defined = 0;
2270 firsttype.eltype.type = NT_invtype;
2271 firsttype.eltype.size = -1;
2272 firsttype.index = -1;
5f4273c7 2273
5287ad62
JB		 2274 if (skip_past_char (&ptr, '{') == SUCCESS)
2275 leading_brace = 1;
5f4273c7 2276
5287ad62
JB		 2277 do
2278 {
dcbf9037 2279 struct neon_typed_alias atype;
35c228db
AV		 2280 if (mve)
2281 rtype = REG_TYPE_MQ;
dcbf9037
JB		 2282 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2283
5287ad62 2284 if (getreg == FAIL)
477330fc
RM		 2285 {
2286 first_error (_(reg_expected_msgs[rtype]));
2287 return FAIL;
2288 }
5f4273c7 2289
5287ad62 2290 if (base_reg == -1)
477330fc
RM		 2291 {
2292 base_reg = getreg;
2293 if (rtype == REG_TYPE_NQ)
2294 {
2295 reg_incr = 1;
2296 }
2297 firsttype = atype;
2298 }
5287ad62 2299 else if (reg_incr == -1)
477330fc
RM		 2300 {
2301 reg_incr = getreg - base_reg;
2302 if (reg_incr < 1 || reg_incr > 2)
2303 {
2304 first_error (_(incr_error));
2305 return FAIL;
2306 }
2307 }
5287ad62 2308 else if (getreg != base_reg + reg_incr * count)
477330fc
RM		 2309 {
2310 first_error (_(incr_error));
2311 return FAIL;
2312 }
dcbf9037 2313
c921be7d 2314 if (! neon_alias_types_same (&atype, &firsttype))
477330fc
RM		 2315 {
2316 first_error (_(type_error));
2317 return FAIL;
2318 }
5f4273c7 2319
5287ad62 2320 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
477330fc 2321 modes. */
5287ad62 2322 if (ptr[0] == '-')
477330fc
RM		 2323 {
2324 struct neon_typed_alias htype;
2325 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2326 if (lane == -1)
2327 lane = NEON_INTERLEAVE_LANES;
2328 else if (lane != NEON_INTERLEAVE_LANES)
2329 {
2330 first_error (_(type_error));
2331 return FAIL;
2332 }
2333 if (reg_incr == -1)
2334 reg_incr = 1;
2335 else if (reg_incr != 1)
2336 {
2337 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2338 return FAIL;
2339 }
2340 ptr++;
2341 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2342 if (hireg == FAIL)
2343 {
2344 first_error (_(reg_expected_msgs[rtype]));
2345 return FAIL;
2346 }
2347 if (! neon_alias_types_same (&htype, &firsttype))
2348 {
2349 first_error (_(type_error));
2350 return FAIL;
2351 }
2352 count += hireg + dregs - getreg;
2353 continue;
2354 }
5f4273c7 2355
5287ad62
JB		 2356 /* If we're using Q registers, we can't use [] or [n] syntax. */
2357 if (rtype == REG_TYPE_NQ)
477330fc
RM		 2358 {
2359 count += 2;
2360 continue;
2361 }
5f4273c7 2362
dcbf9037 2363 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 2364 {
2365 if (lane == -1)
2366 lane = atype.index;
2367 else if (lane != atype.index)
2368 {
2369 first_error (_(type_error));
2370 return FAIL;
2371 }
2372 }
5287ad62 2373 else if (lane == -1)
477330fc 2374 lane = NEON_INTERLEAVE_LANES;
5287ad62 2375 else if (lane != NEON_INTERLEAVE_LANES)
477330fc
RM		 2376 {
2377 first_error (_(type_error));
2378 return FAIL;
2379 }
5287ad62
JB		 2380 count++;
2381 }
2382 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 2383
5287ad62
JB		 2384 /* No lane set by [x]. We must be interleaving structures. */
2385 if (lane == -1)
2386 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2387
5287ad62 2388 /* Sanity check. */
35c228db 2389 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
5287ad62
JB		 2390 || (count > 1 && reg_incr == -1))
2391 {
dcbf9037 2392 first_error (_("error parsing element/structure list"));
5287ad62
JB		 2393 return FAIL;
2394 }
2395
2396 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2397 {
dcbf9037 2398 first_error (_("expected }"));
5287ad62
JB		 2399 return FAIL;
2400 }
5f4273c7 2401
5287ad62
JB		 2402 if (reg_incr == -1)
2403 reg_incr = 1;
2404
dcbf9037
JB		 2405 if (eltype)
2406 *eltype = firsttype.eltype;
2407
5287ad62
JB		 2408 *pbase = base_reg;
2409 *str = ptr;
5f4273c7 2410
5287ad62
JB		 2411 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2412}
2413
c19d1205
ZW		 2414/* Parse an explicit relocation suffix on an expression. This is
2415 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2416 arm_reloc_hsh contains no entries, so this function can only
2417 succeed if there is no () after the word. Returns -1 on error,
2418 BFD_RELOC_UNUSED if there wasn't any suffix. */
3da1d841 2419
c19d1205
ZW		 2420static int
2421parse_reloc (char **str)
b99bd4ef 2422{
c19d1205
ZW		 2423 struct reloc_entry *r;
2424 char *p, *q;
b99bd4ef 2425
c19d1205
ZW		 2426 if (**str != '(')
2427 return BFD_RELOC_UNUSED;
b99bd4ef 2428
c19d1205
ZW		 2429 p = *str + 1;
2430 q = p;
2431
2432 while (*q && *q != ')' && *q != ',')
2433 q++;
2434 if (*q != ')')
2435 return -1;
2436
21d799b5
NC		 2437 if ((r = (struct reloc_entry *)
2438 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW		 2439 return -1;
2440
2441 *str = q + 1;
2442 return r->reloc;
b99bd4ef
NC		 2443}
2444
c19d1205
ZW		 2445/* Directives: register aliases. */
2446
dcbf9037 2447static struct reg_entry *
90ec0d68 2448insert_reg_alias (char *str, unsigned number, int type)
b99bd4ef 2449{
d3ce72d0 2450 struct reg_entry *new_reg;
c19d1205 2451 const char *name;
b99bd4ef 2452
d3ce72d0 2453 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2454 {
d3ce72d0 2455 if (new_reg->builtin)
c19d1205 2456 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2457
c19d1205
ZW		 2458 /* Only warn about a redefinition if it's not defined as the
2459 same register. */
d3ce72d0 2460 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2461 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2462
d929913e 2463 return NULL;
c19d1205 2464 }
b99bd4ef 2465
c19d1205 2466 name = xstrdup (str);
325801bd 2467 new_reg = XNEW (struct reg_entry);
b99bd4ef 2468
d3ce72d0
NC		 2469 new_reg->name = name;
2470 new_reg->number = number;
2471 new_reg->type = type;
2472 new_reg->builtin = FALSE;
2473 new_reg->neon = NULL;
b99bd4ef 2474
d3ce72d0 2475 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2476 abort ();
5f4273c7 2477
d3ce72d0 2478 return new_reg;
dcbf9037
JB		 2479}
2480
2481static void
2482insert_neon_reg_alias (char *str, int number, int type,
477330fc 2483 struct neon_typed_alias *atype)
dcbf9037
JB		 2484{
2485 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2486
dcbf9037
JB		 2487 if (!reg)
2488 {
2489 first_error (_("attempt to redefine typed alias"));
2490 return;
2491 }
5f4273c7 2492
dcbf9037
JB		 2493 if (atype)
2494 {
325801bd 2495 reg->neon = XNEW (struct neon_typed_alias);
dcbf9037
JB		 2496 *reg->neon = *atype;
2497 }
c19d1205 2498}
b99bd4ef 2499
c19d1205 2500/* Look for the .req directive. This is of the form:
b99bd4ef 2501
c19d1205 2502 new_register_name .req existing_register_name
b99bd4ef 2503
c19d1205 2504 If we find one, or if it looks sufficiently like one that we want to
d929913e 2505 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2506
d929913e 2507static bfd_boolean
c19d1205
ZW		 2508create_register_alias (char * newname, char *p)
2509{
2510 struct reg_entry *old;
2511 char *oldname, *nbuf;
2512 size_t nlen;
b99bd4ef 2513
c19d1205
ZW		 2514 /* The input scrubber ensures that whitespace after the mnemonic is
2515 collapsed to single spaces. */
2516 oldname = p;
2517 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2518 return FALSE;
b99bd4ef 2519
c19d1205
ZW		 2520 oldname += 6;
2521 if (*oldname == '\0')
d929913e 2522 return FALSE;
b99bd4ef 2523
21d799b5 2524 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2525 if (!old)
b99bd4ef 2526 {
c19d1205 2527 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2528 return TRUE;
b99bd4ef
NC		 2529 }
2530
c19d1205
ZW		 2531 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2532 the desired alias name, and p points to its end. If not, then
2533 the desired alias name is in the global original_case_string. */
2534#ifdef TC_CASE_SENSITIVE
2535 nlen = p - newname;
2536#else
2537 newname = original_case_string;
2538 nlen = strlen (newname);
2539#endif
b99bd4ef 2540
29a2809e 2541 nbuf = xmemdup0 (newname, nlen);
b99bd4ef 2542
c19d1205
ZW		 2543 /* Create aliases under the new name as stated; an all-lowercase
2544 version of the new name; and an all-uppercase version of the new
2545 name. */
d929913e
NC		 2546 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2547 {
2548 for (p = nbuf; *p; p++)
2549 *p = TOUPPER (*p);
c19d1205 2550
d929913e
NC		 2551 if (strncmp (nbuf, newname, nlen))
2552 {
2553 /* If this attempt to create an additional alias fails, do not bother
2554 trying to create the all-lower case alias. We will fail and issue
2555 a second, duplicate error message. This situation arises when the
2556 programmer does something like:
2557 foo .req r0
2558 Foo .req r1
2559 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2560 the artificial FOO alias because it has already been created by the
d929913e
NC		 2561 first .req. */
2562 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
e1fa0163
NC		 2563 {
2564 free (nbuf);
2565 return TRUE;
2566 }
d929913e 2567 }
c19d1205 2568
d929913e
NC		 2569 for (p = nbuf; *p; p++)
2570 *p = TOLOWER (*p);
c19d1205 2571
d929913e
NC		 2572 if (strncmp (nbuf, newname, nlen))
2573 insert_reg_alias (nbuf, old->number, old->type);
2574 }
c19d1205 2575
e1fa0163 2576 free (nbuf);
d929913e 2577 return TRUE;
b99bd4ef
NC		 2578}
2579
dcbf9037
JB		 2580/* Create a Neon typed/indexed register alias using directives, e.g.:
2581 X .dn d5.s32[1]
2582 Y .qn 6.s16
2583 Z .dn d7
2584 T .dn Z[0]
2585 These typed registers can be used instead of the types specified after the
2586 Neon mnemonic, so long as all operands given have types. Types can also be
2587 specified directly, e.g.:
5f4273c7 2588 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2589
c921be7d 2590static bfd_boolean
dcbf9037
JB		 2591create_neon_reg_alias (char *newname, char *p)
2592{
2593 enum arm_reg_type basetype;
2594 struct reg_entry *basereg;
2595 struct reg_entry mybasereg;
2596 struct neon_type ntype;
2597 struct neon_typed_alias typeinfo;
12d6b0b7 2598 char *namebuf, *nameend ATTRIBUTE_UNUSED;
dcbf9037 2599 int namelen;
5f4273c7 2600
dcbf9037
JB		 2601 typeinfo.defined = 0;
2602 typeinfo.eltype.type = NT_invtype;
2603 typeinfo.eltype.size = -1;
2604 typeinfo.index = -1;
5f4273c7 2605
dcbf9037 2606 nameend = p;
5f4273c7 2607
dcbf9037
JB		 2608 if (strncmp (p, " .dn ", 5) == 0)
2609 basetype = REG_TYPE_VFD;
2610 else if (strncmp (p, " .qn ", 5) == 0)
2611 basetype = REG_TYPE_NQ;
2612 else
c921be7d 2613 return FALSE;
5f4273c7 2614
dcbf9037 2615 p += 5;
5f4273c7 2616
dcbf9037 2617 if (*p == '\0')
c921be7d 2618 return FALSE;
5f4273c7 2619
dcbf9037
JB		 2620 basereg = arm_reg_parse_multi (&p);
2621
2622 if (basereg && basereg->type != basetype)
2623 {
2624 as_bad (_("bad type for register"));
c921be7d 2625 return FALSE;
dcbf9037
JB		 2626 }
2627
2628 if (basereg == NULL)
2629 {
2630 expressionS exp;
2631 /* Try parsing as an integer. */
2632 my_get_expression (&exp, &p, GE_NO_PREFIX);
2633 if (exp.X_op != O_constant)
477330fc
RM		 2634 {
2635 as_bad (_("expression must be constant"));
2636 return FALSE;
2637 }
dcbf9037
JB		 2638 basereg = &mybasereg;
2639 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
477330fc 2640 : exp.X_add_number;
dcbf9037
JB		 2641 basereg->neon = 0;
2642 }
2643
2644 if (basereg->neon)
2645 typeinfo = *basereg->neon;
2646
2647 if (parse_neon_type (&ntype, &p) == SUCCESS)
2648 {
2649 /* We got a type. */
2650 if (typeinfo.defined & NTA_HASTYPE)
477330fc
RM		 2651 {
2652 as_bad (_("can't redefine the type of a register alias"));
2653 return FALSE;
2654 }
5f4273c7 2655
dcbf9037
JB		 2656 typeinfo.defined |= NTA_HASTYPE;
2657 if (ntype.elems != 1)
477330fc
RM		 2658 {
2659 as_bad (_("you must specify a single type only"));
2660 return FALSE;
2661 }
dcbf9037
JB		 2662 typeinfo.eltype = ntype.el[0];
2663 }
5f4273c7 2664
dcbf9037
JB		 2665 if (skip_past_char (&p, '[') == SUCCESS)
2666 {
2667 expressionS exp;
2668 /* We got a scalar index. */
5f4273c7 2669
dcbf9037 2670 if (typeinfo.defined & NTA_HASINDEX)
477330fc
RM		 2671 {
2672 as_bad (_("can't redefine the index of a scalar alias"));
2673 return FALSE;
2674 }
5f4273c7 2675
dcbf9037 2676 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2677
dcbf9037 2678 if (exp.X_op != O_constant)
477330fc
RM		 2679 {
2680 as_bad (_("scalar index must be constant"));
2681 return FALSE;
2682 }
5f4273c7 2683
dcbf9037
JB		 2684 typeinfo.defined |= NTA_HASINDEX;
2685 typeinfo.index = exp.X_add_number;
5f4273c7 2686
dcbf9037 2687 if (skip_past_char (&p, ']') == FAIL)
477330fc
RM		 2688 {
2689 as_bad (_("expecting ]"));
2690 return FALSE;
2691 }
dcbf9037
JB		 2692 }
2693
15735687
NS		 2694 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2695 the desired alias name, and p points to its end. If not, then
2696 the desired alias name is in the global original_case_string. */
2697#ifdef TC_CASE_SENSITIVE
dcbf9037 2698 namelen = nameend - newname;
15735687
NS		 2699#else
2700 newname = original_case_string;
2701 namelen = strlen (newname);
2702#endif
2703
29a2809e 2704 namebuf = xmemdup0 (newname, namelen);
5f4273c7 2705
dcbf9037 2706 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2707 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2708
dcbf9037
JB		 2709 /* Insert name in all uppercase. */
2710 for (p = namebuf; *p; p++)
2711 *p = TOUPPER (*p);
5f4273c7 2712
dcbf9037
JB		 2713 if (strncmp (namebuf, newname, namelen))
2714 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2715 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2716
dcbf9037
JB		 2717 /* Insert name in all lowercase. */
2718 for (p = namebuf; *p; p++)
2719 *p = TOLOWER (*p);
5f4273c7 2720
dcbf9037
JB		 2721 if (strncmp (namebuf, newname, namelen))
2722 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2723 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2724
e1fa0163 2725 free (namebuf);
c921be7d 2726 return TRUE;
dcbf9037
JB		 2727}
2728
c19d1205
ZW		 2729/* Should never be called, as .req goes between the alias and the
2730 register name, not at the beginning of the line. */
c921be7d 2731
b99bd4ef 2732static void
c19d1205 2733s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2734{
c19d1205
ZW		 2735 as_bad (_("invalid syntax for .req directive"));
2736}
b99bd4ef 2737
dcbf9037
JB		 2738static void
2739s_dn (int a ATTRIBUTE_UNUSED)
2740{
2741 as_bad (_("invalid syntax for .dn directive"));
2742}
2743
2744static void
2745s_qn (int a ATTRIBUTE_UNUSED)
2746{
2747 as_bad (_("invalid syntax for .qn directive"));
2748}
2749
c19d1205
ZW		 2750/* The .unreq directive deletes an alias which was previously defined
2751 by .req. For example:
b99bd4ef 2752
c19d1205
ZW		 2753 my_alias .req r11
2754 .unreq my_alias */
b99bd4ef
NC		 2755
2756static void
c19d1205 2757s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2758{
c19d1205
ZW		 2759 char * name;
2760 char saved_char;
b99bd4ef 2761
c19d1205
ZW		 2762 name = input_line_pointer;
2763
2764 while (*input_line_pointer != 0
2765 && *input_line_pointer != ' '
2766 && *input_line_pointer != '\n')
2767 ++input_line_pointer;
2768
2769 saved_char = *input_line_pointer;
2770 *input_line_pointer = 0;
2771
2772 if (!*name)
2773 as_bad (_("invalid syntax for .unreq directive"));
2774 else
2775 {
21d799b5 2776 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
477330fc 2777 name);
c19d1205
ZW		 2778
2779 if (!reg)
2780 as_bad (_("unknown register alias '%s'"), name);
2781 else if (reg->builtin)
a1727c1a 2782 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
c19d1205
ZW		 2783 name);
2784 else
2785 {
d929913e
NC		 2786 char * p;
2787 char * nbuf;
2788
db0bc284 2789 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2790 free ((char *) reg->name);
477330fc
RM		 2791 if (reg->neon)
2792 free (reg->neon);
c19d1205 2793 free (reg);
d929913e
NC		 2794
2795 /* Also locate the all upper case and all lower case versions.
2796 Do not complain if we cannot find one or the other as it
2797 was probably deleted above. */
5f4273c7 2798
d929913e
NC		 2799 nbuf = strdup (name);
2800 for (p = nbuf; *p; p++)
2801 *p = TOUPPER (*p);
21d799b5 2802 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2803 if (reg)
2804 {
db0bc284 2805 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2806 free ((char *) reg->name);
2807 if (reg->neon)
2808 free (reg->neon);
2809 free (reg);
2810 }
2811
2812 for (p = nbuf; *p; p++)
2813 *p = TOLOWER (*p);
21d799b5 2814 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2815 if (reg)
2816 {
db0bc284 2817 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2818 free ((char *) reg->name);
2819 if (reg->neon)
2820 free (reg->neon);
2821 free (reg);
2822 }
2823
2824 free (nbuf);
c19d1205
ZW		 2825 }
2826 }
b99bd4ef 2827
c19d1205 2828 *input_line_pointer = saved_char;
b99bd4ef
NC		 2829 demand_empty_rest_of_line ();
2830}
2831
c19d1205
ZW		 2832/* Directives: Instruction set selection. */
2833
2834#ifdef OBJ_ELF
2835/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2836 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2837 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2838 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2839
cd000bff
DJ		 2840/* Create a new mapping symbol for the transition to STATE. */
2841
2842static void
2843make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2844{
a737bd4d 2845 symbolS * symbolP;
c19d1205
ZW		 2846 const char * symname;
2847 int type;
b99bd4ef 2848
c19d1205 2849 switch (state)
b99bd4ef 2850 {
c19d1205
ZW		 2851 case MAP_DATA:
2852 symname = "$d";
2853 type = BSF_NO_FLAGS;
2854 break;
2855 case MAP_ARM:
2856 symname = "$a";
2857 type = BSF_NO_FLAGS;
2858 break;
2859 case MAP_THUMB:
2860 symname = "$t";
2861 type = BSF_NO_FLAGS;
2862 break;
c19d1205
ZW		 2863 default:
2864 abort ();
2865 }
2866
cd000bff 2867 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW		 2868 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2869
2870 switch (state)
2871 {
2872 case MAP_ARM:
2873 THUMB_SET_FUNC (symbolP, 0);
2874 ARM_SET_THUMB (symbolP, 0);
2875 ARM_SET_INTERWORK (symbolP, support_interwork);
2876 break;
2877
2878 case MAP_THUMB:
2879 THUMB_SET_FUNC (symbolP, 1);
2880 ARM_SET_THUMB (symbolP, 1);
2881 ARM_SET_INTERWORK (symbolP, support_interwork);
2882 break;
2883
2884 case MAP_DATA:
2885 default:
cd000bff
DJ		 2886 break;
2887 }
2888
2889 /* Save the mapping symbols for future reference. Also check that
2890 we do not place two mapping symbols at the same offset within a
2891 frag. We'll handle overlap between frags in
2de7820f
JZ		 2892 check_mapping_symbols.
2893
2894 If .fill or other data filling directive generates zero sized data,
2895 the mapping symbol for the following code will have the same value
2896 as the one generated for the data filling directive. In this case,
2897 we replace the old symbol with the new one at the same address. */
cd000bff
DJ		 2898 if (value == 0)
2899 {
2de7820f
JZ		 2900 if (frag->tc_frag_data.first_map != NULL)
2901 {
2902 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2903 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2904 }
cd000bff
DJ		 2905 frag->tc_frag_data.first_map = symbolP;
2906 }
2907 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ		 2908 {
2909 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ		 2910 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2911 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2912 }
cd000bff
DJ		 2913 frag->tc_frag_data.last_map = symbolP;
2914}
2915
2916/* We must sometimes convert a region marked as code to data during
2917 code alignment, if an odd number of bytes have to be padded. The
2918 code mapping symbol is pushed to an aligned address. */
2919
2920static void
2921insert_data_mapping_symbol (enum mstate state,
2922 valueT value, fragS *frag, offsetT bytes)
2923{
2924 /* If there was already a mapping symbol, remove it. */
2925 if (frag->tc_frag_data.last_map != NULL
2926 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2927 {
2928 symbolS *symp = frag->tc_frag_data.last_map;
2929
2930 if (value == 0)
2931 {
2932 know (frag->tc_frag_data.first_map == symp);
2933 frag->tc_frag_data.first_map = NULL;
2934 }
2935 frag->tc_frag_data.last_map = NULL;
2936 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 2937 }
cd000bff
DJ		 2938
2939 make_mapping_symbol (MAP_DATA, value, frag);
2940 make_mapping_symbol (state, value + bytes, frag);
2941}
2942
2943static void mapping_state_2 (enum mstate state, int max_chars);
2944
2945/* Set the mapping state to STATE. Only call this when about to
2946 emit some STATE bytes to the file. */
2947
4e9aaefb 2948#define TRANSITION(from, to) (mapstate == (from) && state == (to))
cd000bff
DJ		 2949void
2950mapping_state (enum mstate state)
2951{
940b5ce0
DJ		 2952 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2953
cd000bff
DJ		 2954 if (mapstate == state)
2955 /* The mapping symbol has already been emitted.
2956 There is nothing else to do. */
2957 return;
49c62a33
NC		 2958
2959 if (state == MAP_ARM || state == MAP_THUMB)
2960 /* PR gas/12931
2961 All ARM instructions require 4-byte alignment.
2962 (Almost) all Thumb instructions require 2-byte alignment.
2963
2964 When emitting instructions into any section, mark the section
2965 appropriately.
2966
2967 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2968 but themselves require 2-byte alignment; this applies to some
33eaf5de 2969 PC- relative forms. However, these cases will involve implicit
49c62a33
NC		 2970 literal pool generation or an explicit .align >=2, both of
2971 which will cause the section to me marked with sufficient
2972 alignment. Thus, we don't handle those cases here. */
2973 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2974
2975 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
4e9aaefb 2976 /* This case will be evaluated later. */
cd000bff 2977 return;
cd000bff
DJ		 2978
2979 mapping_state_2 (state, 0);
cd000bff
DJ		 2980}
2981
2982/* Same as mapping_state, but MAX_CHARS bytes have already been
2983 allocated. Put the mapping symbol that far back. */
2984
2985static void
2986mapping_state_2 (enum mstate state, int max_chars)
2987{
940b5ce0
DJ		 2988 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2989
2990 if (!SEG_NORMAL (now_seg))
2991 return;
2992
cd000bff
DJ		 2993 if (mapstate == state)
2994 /* The mapping symbol has already been emitted.
2995 There is nothing else to do. */
2996 return;
2997
4e9aaefb
SA		 2998 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2999 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
3000 {
3001 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
3002 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
3003
3004 if (add_symbol)
3005 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
3006 }
3007
cd000bff
DJ		 3008 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
3009 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205 3010}
4e9aaefb 3011#undef TRANSITION
c19d1205 3012#else
d3106081
NS		 3013#define mapping_state(x) ((void)0)
3014#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW		 3015#endif
3016
3017/* Find the real, Thumb encoded start of a Thumb function. */
3018
4343666d 3019#ifdef OBJ_COFF
c19d1205
ZW		 3020static symbolS *
3021find_real_start (symbolS * symbolP)
3022{
3023 char * real_start;
3024 const char * name = S_GET_NAME (symbolP);
3025 symbolS * new_target;
3026
3027 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3028#define STUB_NAME ".real_start_of"
3029
3030 if (name == NULL)
3031 abort ();
3032
37f6032b
ZW		 3033 /* The compiler may generate BL instructions to local labels because
3034 it needs to perform a branch to a far away location. These labels
3035 do not have a corresponding ".real_start_of" label. We check
3036 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3037 the ".real_start_of" convention for nonlocal branches. */
3038 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW		 3039 return symbolP;
3040
e1fa0163 3041 real_start = concat (STUB_NAME, name, NULL);
c19d1205 3042 new_target = symbol_find (real_start);
e1fa0163 3043 free (real_start);
c19d1205
ZW		 3044
3045 if (new_target == NULL)
3046 {
bd3ba5d1 3047 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW		 3048 new_target = symbolP;
3049 }
3050
c19d1205
ZW		 3051 return new_target;
3052}
4343666d 3053#endif
c19d1205
ZW		 3054
3055static void
3056opcode_select (int width)
3057{
3058 switch (width)
3059 {
3060 case 16:
3061 if (! thumb_mode)
3062 {
e74cfd16 3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW		 3064 as_bad (_("selected processor does not support THUMB opcodes"));
3065
3066 thumb_mode = 1;
3067 /* No need to force the alignment, since we will have been
3068 coming from ARM mode, which is word-aligned. */
3069 record_alignment (now_seg, 1);
3070 }
c19d1205
ZW		 3071 break;
3072
3073 case 32:
3074 if (thumb_mode)
3075 {
e74cfd16 3076 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW		 3077 as_bad (_("selected processor does not support ARM opcodes"));
3078
3079 thumb_mode = 0;
3080
3081 if (!need_pass_2)
3082 frag_align (2, 0, 0);
3083
3084 record_alignment (now_seg, 1);
3085 }
c19d1205
ZW		 3086 break;
3087
3088 default:
3089 as_bad (_("invalid instruction size selected (%d)"), width);
3090 }
3091}
3092
3093static void
3094s_arm (int ignore ATTRIBUTE_UNUSED)
3095{
3096 opcode_select (32);
3097 demand_empty_rest_of_line ();
3098}
3099
3100static void
3101s_thumb (int ignore ATTRIBUTE_UNUSED)
3102{
3103 opcode_select (16);
3104 demand_empty_rest_of_line ();
3105}
3106
3107static void
3108s_code (int unused ATTRIBUTE_UNUSED)
3109{
3110 int temp;
3111
3112 temp = get_absolute_expression ();
3113 switch (temp)
3114 {
3115 case 16:
3116 case 32:
3117 opcode_select (temp);
3118 break;
3119
3120 default:
3121 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3122 }
3123}
3124
3125static void
3126s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3127{
3128 /* If we are not already in thumb mode go into it, EVEN if
3129 the target processor does not support thumb instructions.
3130 This is used by gcc/config/arm/lib1funcs.asm for example
3131 to compile interworking support functions even if the
3132 target processor should not support interworking. */
3133 if (! thumb_mode)
3134 {
3135 thumb_mode = 2;
3136 record_alignment (now_seg, 1);
3137 }
3138
3139 demand_empty_rest_of_line ();
3140}
3141
3142static void
3143s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3144{
3145 s_thumb (0);
3146
3147 /* The following label is the name/address of the start of a Thumb function.
3148 We need to know this for the interworking support. */
3149 label_is_thumb_function_name = TRUE;
3150}
3151
3152/* Perform a .set directive, but also mark the alias as
3153 being a thumb function. */
3154
3155static void
3156s_thumb_set (int equiv)
3157{
3158 /* XXX the following is a duplicate of the code for s_set() in read.c
3159 We cannot just call that code as we need to get at the symbol that
3160 is created. */
3161 char * name;
3162 char delim;
3163 char * end_name;
3164 symbolS * symbolP;
3165
3166 /* Especial apologies for the random logic:
3167 This just grew, and could be parsed much more simply!
3168 Dean - in haste. */
d02603dc 3169 delim = get_symbol_name (& name);
c19d1205 3170 end_name = input_line_pointer;
d02603dc 3171 (void) restore_line_pointer (delim);
c19d1205
ZW		 3172
3173 if (*input_line_pointer != ',')
3174 {
3175 *end_name = 0;
3176 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC		 3177 *end_name = delim;
3178 ignore_rest_of_line ();
3179 return;
3180 }
3181
3182 input_line_pointer++;
3183 *end_name = 0;
3184
3185 if (name[0] == '.' && name[1] == '\0')
3186 {
3187 /* XXX - this should not happen to .thumb_set. */
3188 abort ();
3189 }
3190
3191 if ((symbolP = symbol_find (name)) == NULL
3192 && (symbolP = md_undefined_symbol (name)) == NULL)
3193 {
3194#ifndef NO_LISTING
3195 /* When doing symbol listings, play games with dummy fragments living
3196 outside the normal fragment chain to record the file and line info
c19d1205 3197 for this symbol. */
b99bd4ef
NC		 3198 if (listing & LISTING_SYMBOLS)
3199 {
3200 extern struct list_info_struct * listing_tail;
21d799b5 3201 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC		 3202
3203 memset (dummy_frag, 0, sizeof (fragS));
3204 dummy_frag->fr_type = rs_fill;
3205 dummy_frag->line = listing_tail;
3206 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3207 dummy_frag->fr_symbol = symbolP;
3208 }
3209 else
3210#endif
3211 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3212
3213#ifdef OBJ_COFF
3214 /* "set" symbols are local unless otherwise specified. */
3215 SF_SET_LOCAL (symbolP);
3216#endif /* OBJ_COFF */
3217 } /* Make a new symbol. */
3218
3219 symbol_table_insert (symbolP);
3220
3221 * end_name = delim;
3222
3223 if (equiv
3224 && S_IS_DEFINED (symbolP)
3225 && S_GET_SEGMENT (symbolP) != reg_section)
3226 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3227
3228 pseudo_set (symbolP);
3229
3230 demand_empty_rest_of_line ();
3231
c19d1205 3232 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC		 3233
3234 THUMB_SET_FUNC (symbolP, 1);
3235 ARM_SET_THUMB (symbolP, 1);
3236#if defined OBJ_ELF || defined OBJ_COFF
3237 ARM_SET_INTERWORK (symbolP, support_interwork);
3238#endif
3239}
3240
c19d1205 3241/* Directives: Mode selection. */
b99bd4ef 3242
c19d1205
ZW		 3243/* .syntax [unified|divided] - choose the new unified syntax
3244 (same for Arm and Thumb encoding, modulo slight differences in what
3245 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 3246static void
c19d1205 3247s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 3248{
c19d1205
ZW		 3249 char *name, delim;
3250
d02603dc 3251 delim = get_symbol_name (& name);
c19d1205
ZW		 3252
3253 if (!strcasecmp (name, "unified"))
3254 unified_syntax = TRUE;
3255 else if (!strcasecmp (name, "divided"))
3256 unified_syntax = FALSE;
3257 else
3258 {
3259 as_bad (_("unrecognized syntax mode \"%s\""), name);
3260 return;
3261 }
d02603dc 3262 (void) restore_line_pointer (delim);
b99bd4ef
NC		 3263 demand_empty_rest_of_line ();
3264}
3265
c19d1205
ZW		 3266/* Directives: sectioning and alignment. */
3267
c19d1205
ZW		 3268static void
3269s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 3270{
c19d1205
ZW		 3271 /* We don't support putting frags in the BSS segment, we fake it by
3272 marking in_bss, then looking at s_skip for clues. */
3273 subseg_set (bss_section, 0);
3274 demand_empty_rest_of_line ();
cd000bff
DJ		 3275
3276#ifdef md_elf_section_change_hook
3277 md_elf_section_change_hook ();
3278#endif
c19d1205 3279}
b99bd4ef 3280
c19d1205
ZW		 3281static void
3282s_even (int ignore ATTRIBUTE_UNUSED)
3283{
3284 /* Never make frag if expect extra pass. */
3285 if (!need_pass_2)
3286 frag_align (1, 0, 0);
b99bd4ef 3287
c19d1205 3288 record_alignment (now_seg, 1);
b99bd4ef 3289
c19d1205 3290 demand_empty_rest_of_line ();
b99bd4ef
NC		 3291}
3292
2e6976a8
DG		 3293/* Directives: CodeComposer Studio. */
3294
3295/* .ref (for CodeComposer Studio syntax only). */
3296static void
3297s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3298{
3299 if (codecomposer_syntax)
3300 ignore_rest_of_line ();
3301 else
3302 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3303}
3304
3305/* If name is not NULL, then it is used for marking the beginning of a
2b0f3761 3306 function, whereas if it is NULL then it means the function end. */
2e6976a8
DG		 3307static void
3308asmfunc_debug (const char * name)
3309{
3310 static const char * last_name = NULL;
3311
3312 if (name != NULL)
3313 {
3314 gas_assert (last_name == NULL);
3315 last_name = name;
3316
3317 if (debug_type == DEBUG_STABS)
3318 stabs_generate_asm_func (name, name);
3319 }
3320 else
3321 {
3322 gas_assert (last_name != NULL);
3323
3324 if (debug_type == DEBUG_STABS)
3325 stabs_generate_asm_endfunc (last_name, last_name);
3326
3327 last_name = NULL;
3328 }
3329}
3330
3331static void
3332s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3333{
3334 if (codecomposer_syntax)
3335 {
3336 switch (asmfunc_state)
3337 {
3338 case OUTSIDE_ASMFUNC:
3339 asmfunc_state = WAITING_ASMFUNC_NAME;
3340 break;
3341
3342 case WAITING_ASMFUNC_NAME:
3343 as_bad (_(".asmfunc repeated."));
3344 break;
3345
3346 case WAITING_ENDASMFUNC:
3347 as_bad (_(".asmfunc without function."));
3348 break;
3349 }
3350 demand_empty_rest_of_line ();
3351 }
3352 else
3353 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3354}
3355
3356static void
3357s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3358{
3359 if (codecomposer_syntax)
3360 {
3361 switch (asmfunc_state)
3362 {
3363 case OUTSIDE_ASMFUNC:
3364 as_bad (_(".endasmfunc without a .asmfunc."));
3365 break;
3366
3367 case WAITING_ASMFUNC_NAME:
3368 as_bad (_(".endasmfunc without function."));
3369 break;
3370
3371 case WAITING_ENDASMFUNC:
3372 asmfunc_state = OUTSIDE_ASMFUNC;
3373 asmfunc_debug (NULL);
3374 break;
3375 }
3376 demand_empty_rest_of_line ();
3377 }
3378 else
3379 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3380}
3381
3382static void
3383s_ccs_def (int name)
3384{
3385 if (codecomposer_syntax)
3386 s_globl (name);
3387 else
3388 as_bad (_(".def pseudo-op only available with -mccs flag."));
3389}
3390
c19d1205 3391/* Directives: Literal pools. */
a737bd4d 3392
c19d1205
ZW		 3393static literal_pool *
3394find_literal_pool (void)
a737bd4d 3395{
c19d1205 3396 literal_pool * pool;
a737bd4d 3397
c19d1205 3398 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 3399 {
c19d1205
ZW		 3400 if (pool->section == now_seg
3401 && pool->sub_section == now_subseg)
3402 break;
a737bd4d
NC		 3403 }
3404
c19d1205 3405 return pool;
a737bd4d
NC		 3406}
3407
c19d1205
ZW		 3408static literal_pool *
3409find_or_make_literal_pool (void)
a737bd4d 3410{
c19d1205
ZW		 3411 /* Next literal pool ID number. */
3412 static unsigned int latest_pool_num = 1;
3413 literal_pool * pool;
a737bd4d 3414
c19d1205 3415 pool = find_literal_pool ();
a737bd4d 3416
c19d1205 3417 if (pool == NULL)
a737bd4d 3418 {
c19d1205 3419 /* Create a new pool. */
325801bd 3420 pool = XNEW (literal_pool);
c19d1205
ZW		 3421 if (! pool)
3422 return NULL;
a737bd4d 3423
c19d1205
ZW		 3424 pool->next_free_entry = 0;
3425 pool->section = now_seg;
3426 pool->sub_section = now_subseg;
3427 pool->next = list_of_pools;
3428 pool->symbol = NULL;
8335d6aa 3429 pool->alignment = 2;
c19d1205
ZW		 3430
3431 /* Add it to the list. */
3432 list_of_pools = pool;
a737bd4d 3433 }
a737bd4d 3434
c19d1205
ZW		 3435 /* New pools, and emptied pools, will have a NULL symbol. */
3436 if (pool->symbol == NULL)
a737bd4d 3437 {
c19d1205
ZW		 3438 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3439 (valueT) 0, &zero_address_frag);
3440 pool->id = latest_pool_num ++;
a737bd4d
NC		 3441 }
3442
c19d1205
ZW		 3443 /* Done. */
3444 return pool;
a737bd4d
NC		 3445}
3446
c19d1205 3447/* Add the literal in the global 'inst'
5f4273c7 3448 structure to the relevant literal pool. */
b99bd4ef
NC		 3449
3450static int
8335d6aa 3451add_to_lit_pool (unsigned int nbytes)
b99bd4ef 3452{
8335d6aa
JW		 3453#define PADDING_SLOT 0x1
3454#define LIT_ENTRY_SIZE_MASK 0xFF
c19d1205 3455 literal_pool * pool;
8335d6aa
JW		 3456 unsigned int entry, pool_size = 0;
3457 bfd_boolean padding_slot_p = FALSE;
e56c722b 3458 unsigned imm1 = 0;
8335d6aa
JW		 3459 unsigned imm2 = 0;
3460
3461 if (nbytes == 8)
3462 {
3463 imm1 = inst.operands[1].imm;
3464 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
e2b0ab59 3465 : inst.relocs[0].exp.X_unsigned ? 0
2569ceb0 3466 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
8335d6aa
JW		 3467 if (target_big_endian)
3468 {
3469 imm1 = imm2;
3470 imm2 = inst.operands[1].imm;
3471 }
3472 }
b99bd4ef 3473
c19d1205
ZW		 3474 pool = find_or_make_literal_pool ();
3475
3476 /* Check if this literal value is already in the pool. */
3477 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3478 {
8335d6aa
JW		 3479 if (nbytes == 4)
3480 {
e2b0ab59
AV		 3481 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3482 && (inst.relocs[0].exp.X_op == O_constant)
8335d6aa 3483 && (pool->literals[entry].X_add_number
e2b0ab59 3484 == inst.relocs[0].exp.X_add_number)
8335d6aa
JW		 3485 && (pool->literals[entry].X_md == nbytes)
3486 && (pool->literals[entry].X_unsigned
e2b0ab59 3487 == inst.relocs[0].exp.X_unsigned))
8335d6aa
JW		 3488 break;
3489
e2b0ab59
AV		 3490 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3491 && (inst.relocs[0].exp.X_op == O_symbol)
8335d6aa 3492 && (pool->literals[entry].X_add_number
e2b0ab59 3493 == inst.relocs[0].exp.X_add_number)
8335d6aa 3494 && (pool->literals[entry].X_add_symbol
e2b0ab59 3495 == inst.relocs[0].exp.X_add_symbol)
8335d6aa 3496 && (pool->literals[entry].X_op_symbol
e2b0ab59 3497 == inst.relocs[0].exp.X_op_symbol)
8335d6aa
JW		 3498 && (pool->literals[entry].X_md == nbytes))
3499 break;
3500 }
3501 else if ((nbytes == 8)
3502 && !(pool_size & 0x7)
3503 && ((entry + 1) != pool->next_free_entry)
3504 && (pool->literals[entry].X_op == O_constant)
19f2f6a9 3505 && (pool->literals[entry].X_add_number == (offsetT) imm1)
8335d6aa 3506 && (pool->literals[entry].X_unsigned
e2b0ab59 3507 == inst.relocs[0].exp.X_unsigned)
8335d6aa 3508 && (pool->literals[entry + 1].X_op == O_constant)
19f2f6a9 3509 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
8335d6aa 3510 && (pool->literals[entry + 1].X_unsigned
e2b0ab59 3511 == inst.relocs[0].exp.X_unsigned))
c19d1205
ZW		 3512 break;
3513
8335d6aa
JW		 3514 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3515 if (padding_slot_p && (nbytes == 4))
c19d1205 3516 break;
8335d6aa
JW		 3517
3518 pool_size += 4;
b99bd4ef
NC		 3519 }
3520
c19d1205
ZW		 3521 /* Do we need to create a new entry? */
3522 if (entry == pool->next_free_entry)
3523 {
3524 if (entry >= MAX_LITERAL_POOL_SIZE)
3525 {
3526 inst.error = _("literal pool overflow");
3527 return FAIL;
3528 }
3529
8335d6aa
JW		 3530 if (nbytes == 8)
3531 {
3532 /* For 8-byte entries, we align to an 8-byte boundary,
3533 and split it into two 4-byte entries, because on 32-bit
3534 host, 8-byte constants are treated as big num, thus
3535 saved in "generic_bignum" which will be overwritten
3536 by later assignments.
3537
3538 We also need to make sure there is enough space for
3539 the split.
3540
3541 We also check to make sure the literal operand is a
3542 constant number. */
e2b0ab59
AV		 3543 if (!(inst.relocs[0].exp.X_op == O_constant
3544 || inst.relocs[0].exp.X_op == O_big))
8335d6aa
JW		 3545 {
3546 inst.error = _("invalid type for literal pool");
3547 return FAIL;
3548 }
3549 else if (pool_size & 0x7)
3550 {
3551 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3552 {
3553 inst.error = _("literal pool overflow");
3554 return FAIL;
3555 }
3556
e2b0ab59 3557 pool->literals[entry] = inst.relocs[0].exp;
a6684f0d 3558 pool->literals[entry].X_op = O_constant;
8335d6aa
JW		 3559 pool->literals[entry].X_add_number = 0;
3560 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3561 pool->next_free_entry += 1;
3562 pool_size += 4;
3563 }
3564 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3565 {
3566 inst.error = _("literal pool overflow");
3567 return FAIL;
3568 }
3569
e2b0ab59 3570 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3571 pool->literals[entry].X_op = O_constant;
3572 pool->literals[entry].X_add_number = imm1;
e2b0ab59 3573 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa 3574 pool->literals[entry++].X_md = 4;
e2b0ab59 3575 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3576 pool->literals[entry].X_op = O_constant;
3577 pool->literals[entry].X_add_number = imm2;
e2b0ab59 3578 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa
JW		 3579 pool->literals[entry].X_md = 4;
3580 pool->alignment = 3;
3581 pool->next_free_entry += 1;
3582 }
3583 else
3584 {
e2b0ab59 3585 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3586 pool->literals[entry].X_md = 4;
3587 }
3588
a8040cf2
NC		 3589#ifdef OBJ_ELF
3590 /* PR ld/12974: Record the location of the first source line to reference
3591 this entry in the literal pool. If it turns out during linking that the
3592 symbol does not exist we will be able to give an accurate line number for
3593 the (first use of the) missing reference. */
3594 if (debug_type == DEBUG_DWARF2)
3595 dwarf2_where (pool->locs + entry);
3596#endif
c19d1205
ZW		 3597 pool->next_free_entry += 1;
3598 }
8335d6aa
JW		 3599 else if (padding_slot_p)
3600 {
e2b0ab59 3601 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3602 pool->literals[entry].X_md = nbytes;
3603 }
b99bd4ef 3604
e2b0ab59
AV		 3605 inst.relocs[0].exp.X_op = O_symbol;
3606 inst.relocs[0].exp.X_add_number = pool_size;
3607 inst.relocs[0].exp.X_add_symbol = pool->symbol;
b99bd4ef 3608
c19d1205 3609 return SUCCESS;
b99bd4ef
NC		 3610}
3611
2e6976a8 3612bfd_boolean
2e57ce7b 3613tc_start_label_without_colon (void)
2e6976a8
DG		 3614{
3615 bfd_boolean ret = TRUE;
3616
3617 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3618 {
2e57ce7b 3619 const char *label = input_line_pointer;
2e6976a8
DG		 3620
3621 while (!is_end_of_line[(int) label[-1]])
3622 --label;
3623
3624 if (*label == '.')
3625 {
3626 as_bad (_("Invalid label '%s'"), label);
3627 ret = FALSE;
3628 }
3629
3630 asmfunc_debug (label);
3631
3632 asmfunc_state = WAITING_ENDASMFUNC;
3633 }
3634
3635 return ret;
3636}
3637
c19d1205 3638/* Can't use symbol_new here, so have to create a symbol and then at
33eaf5de 3639 a later date assign it a value. That's what these functions do. */
e16bb312 3640
c19d1205
ZW		 3641static void
3642symbol_locate (symbolS * symbolP,
3643 const char * name, /* It is copied, the caller can modify. */
3644 segT segment, /* Segment identifier (SEG_<something>). */
3645 valueT valu, /* Symbol value. */
3646 fragS * frag) /* Associated fragment. */
3647{
e57e6ddc 3648 size_t name_length;
c19d1205 3649 char * preserved_copy_of_name;
e16bb312 3650
c19d1205
ZW		 3651 name_length = strlen (name) + 1; /* +1 for \0. */
3652 obstack_grow (&notes, name, name_length);
21d799b5 3653 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3654
c19d1205
ZW		 3655#ifdef tc_canonicalize_symbol_name
3656 preserved_copy_of_name =
3657 tc_canonicalize_symbol_name (preserved_copy_of_name);
3658#endif
b99bd4ef 3659
c19d1205 3660 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3661
c19d1205
ZW		 3662 S_SET_SEGMENT (symbolP, segment);
3663 S_SET_VALUE (symbolP, valu);
3664 symbol_clear_list_pointers (symbolP);
b99bd4ef 3665
c19d1205 3666 symbol_set_frag (symbolP, frag);
b99bd4ef 3667
c19d1205
ZW		 3668 /* Link to end of symbol chain. */
3669 {
3670 extern int symbol_table_frozen;
b99bd4ef 3671
c19d1205
ZW		 3672 if (symbol_table_frozen)
3673 abort ();
3674 }
b99bd4ef 3675
c19d1205 3676 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3677
c19d1205 3678 obj_symbol_new_hook (symbolP);
b99bd4ef 3679
c19d1205
ZW		 3680#ifdef tc_symbol_new_hook
3681 tc_symbol_new_hook (symbolP);
3682#endif
3683
3684#ifdef DEBUG_SYMS
3685 verify_symbol_chain (symbol_rootP, symbol_lastP);
3686#endif /* DEBUG_SYMS */
b99bd4ef
NC		 3687}
3688
c19d1205
ZW		 3689static void
3690s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3691{
c19d1205
ZW		 3692 unsigned int entry;
3693 literal_pool * pool;
3694 char sym_name[20];
b99bd4ef 3695
c19d1205
ZW		 3696 pool = find_literal_pool ();
3697 if (pool == NULL
3698 || pool->symbol == NULL
3699 || pool->next_free_entry == 0)
3700 return;
b99bd4ef 3701
c19d1205
ZW		 3702 /* Align pool as you have word accesses.
3703 Only make a frag if we have to. */
3704 if (!need_pass_2)
8335d6aa 3705 frag_align (pool->alignment, 0, 0);
b99bd4ef 3706
c19d1205 3707 record_alignment (now_seg, 2);
b99bd4ef 3708
aaca88ef 3709#ifdef OBJ_ELF
47fc6e36
WN		 3710 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3711 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
aaca88ef 3712#endif
c19d1205 3713 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3714
c19d1205
ZW		 3715 symbol_locate (pool->symbol, sym_name, now_seg,
3716 (valueT) frag_now_fix (), frag_now);
3717 symbol_table_insert (pool->symbol);
b99bd4ef 3718
c19d1205 3719 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3720
c19d1205
ZW		 3721#if defined OBJ_COFF || defined OBJ_ELF
3722 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3723#endif
6c43fab6 3724
c19d1205 3725 for (entry = 0; entry < pool->next_free_entry; entry ++)
a8040cf2
NC		 3726 {
3727#ifdef OBJ_ELF
3728 if (debug_type == DEBUG_DWARF2)
3729 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3730#endif
3731 /* First output the expression in the instruction to the pool. */
8335d6aa
JW		 3732 emit_expr (&(pool->literals[entry]),
3733 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
a8040cf2 3734 }
b99bd4ef 3735
c19d1205
ZW		 3736 /* Mark the pool as empty. */
3737 pool->next_free_entry = 0;
3738 pool->symbol = NULL;
b99bd4ef
NC		 3739}
3740
c19d1205
ZW		 3741#ifdef OBJ_ELF
3742/* Forward declarations for functions below, in the MD interface
3743 section. */
3744static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3745static valueT create_unwind_entry (int);
3746static void start_unwind_section (const segT, int);
3747static void add_unwind_opcode (valueT, int);
3748static void flush_pending_unwind (void);
b99bd4ef 3749
c19d1205 3750/* Directives: Data. */
b99bd4ef 3751
c19d1205
ZW		 3752static void
3753s_arm_elf_cons (int nbytes)
3754{
3755 expressionS exp;
b99bd4ef 3756
c19d1205
ZW		 3757#ifdef md_flush_pending_output
3758 md_flush_pending_output ();
3759#endif
b99bd4ef 3760
c19d1205 3761 if (is_it_end_of_statement ())
b99bd4ef 3762 {
c19d1205
ZW		 3763 demand_empty_rest_of_line ();
3764 return;
b99bd4ef
NC		 3765 }
3766
c19d1205
ZW		 3767#ifdef md_cons_align
3768 md_cons_align (nbytes);
3769#endif
b99bd4ef 3770
c19d1205
ZW		 3771 mapping_state (MAP_DATA);
3772 do
b99bd4ef 3773 {
c19d1205
ZW		 3774 int reloc;
3775 char *base = input_line_pointer;
b99bd4ef 3776
c19d1205 3777 expression (& exp);
b99bd4ef 3778
c19d1205
ZW		 3779 if (exp.X_op != O_symbol)
3780 emit_expr (&exp, (unsigned int) nbytes);
3781 else
3782 {
3783 char *before_reloc = input_line_pointer;
3784 reloc = parse_reloc (&input_line_pointer);
3785 if (reloc == -1)
3786 {
3787 as_bad (_("unrecognized relocation suffix"));
3788 ignore_rest_of_line ();
3789 return;
3790 }
3791 else if (reloc == BFD_RELOC_UNUSED)
3792 emit_expr (&exp, (unsigned int) nbytes);
3793 else
3794 {
21d799b5 3795 reloc_howto_type *howto = (reloc_howto_type *)
477330fc
RM		 3796 bfd_reloc_type_lookup (stdoutput,
3797 (bfd_reloc_code_real_type) reloc);
c19d1205 3798 int size = bfd_get_reloc_size (howto);
b99bd4ef 3799
2fc8bdac
ZW		 3800 if (reloc == BFD_RELOC_ARM_PLT32)
3801 {
3802 as_bad (_("(plt) is only valid on branch targets"));
3803 reloc = BFD_RELOC_UNUSED;
3804 size = 0;
3805 }
3806
c19d1205 3807 if (size > nbytes)
992a06ee
AM		 3808 as_bad (ngettext ("%s relocations do not fit in %d byte",
3809 "%s relocations do not fit in %d bytes",
3810 nbytes),
c19d1205
ZW		 3811 howto->name, nbytes);
3812 else
3813 {
3814 /* We've parsed an expression stopping at O_symbol.
3815 But there may be more expression left now that we
3816 have parsed the relocation marker. Parse it again.
3817 XXX Surely there is a cleaner way to do this. */
3818 char *p = input_line_pointer;
3819 int offset;
325801bd 3820 char *save_buf = XNEWVEC (char, input_line_pointer - base);
e1fa0163 3821
c19d1205
ZW		 3822 memcpy (save_buf, base, input_line_pointer - base);
3823 memmove (base + (input_line_pointer - before_reloc),
3824 base, before_reloc - base);
3825
3826 input_line_pointer = base + (input_line_pointer-before_reloc);
3827 expression (&exp);
3828 memcpy (base, save_buf, p - base);
3829
3830 offset = nbytes - size;
4b1a927e
AM		 3831 p = frag_more (nbytes);
3832 memset (p, 0, nbytes);
c19d1205 3833 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3834 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
e1fa0163 3835 free (save_buf);
c19d1205
ZW		 3836 }
3837 }
3838 }
b99bd4ef 3839 }
c19d1205 3840 while (*input_line_pointer++ == ',');
b99bd4ef 3841
c19d1205
ZW		 3842 /* Put terminator back into stream. */
3843 input_line_pointer --;
3844 demand_empty_rest_of_line ();
b99bd4ef
NC		 3845}
3846
c921be7d
NC		 3847/* Emit an expression containing a 32-bit thumb instruction.
3848 Implementation based on put_thumb32_insn. */
3849
3850static void
3851emit_thumb32_expr (expressionS * exp)
3852{
3853 expressionS exp_high = *exp;
3854
3855 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3856 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3857 exp->X_add_number &= 0xffff;
3858 emit_expr (exp, (unsigned int) THUMB_SIZE);
3859}
3860
3861/* Guess the instruction size based on the opcode. */
3862
3863static int
3864thumb_insn_size (int opcode)
3865{
3866 if ((unsigned int) opcode < 0xe800u)
3867 return 2;
3868 else if ((unsigned int) opcode >= 0xe8000000u)
3869 return 4;
3870 else
3871 return 0;
3872}
3873
3874static bfd_boolean
3875emit_insn (expressionS *exp, int nbytes)
3876{
3877 int size = 0;
3878
3879 if (exp->X_op == O_constant)
3880 {
3881 size = nbytes;
3882
3883 if (size == 0)
3884 size = thumb_insn_size (exp->X_add_number);
3885
3886 if (size != 0)
3887 {
3888 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3889 {
3890 as_bad (_(".inst.n operand too big. "\
3891 "Use .inst.w instead"));
3892 size = 0;
3893 }
3894 else
3895 {
5ee91343
AV		 3896 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
3897 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
c921be7d 3898 else
5ee91343 3899 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
c921be7d
NC		 3900
3901 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3902 emit_thumb32_expr (exp);
3903 else
3904 emit_expr (exp, (unsigned int) size);
3905
3906 it_fsm_post_encode ();
3907 }
3908 }
3909 else
3910 as_bad (_("cannot determine Thumb instruction size. " \
3911 "Use .inst.n/.inst.w instead"));
3912 }
3913 else
3914 as_bad (_("constant expression required"));
3915
3916 return (size != 0);
3917}
3918
3919/* Like s_arm_elf_cons but do not use md_cons_align and
3920 set the mapping state to MAP_ARM/MAP_THUMB. */
3921
3922static void
3923s_arm_elf_inst (int nbytes)
3924{
3925 if (is_it_end_of_statement ())
3926 {
3927 demand_empty_rest_of_line ();
3928 return;
3929 }
3930
3931 /* Calling mapping_state () here will not change ARM/THUMB,
3932 but will ensure not to be in DATA state. */
3933
3934 if (thumb_mode)
3935 mapping_state (MAP_THUMB);
3936 else
3937 {
3938 if (nbytes != 0)
3939 {
3940 as_bad (_("width suffixes are invalid in ARM mode"));
3941 ignore_rest_of_line ();
3942 return;
3943 }
3944
3945 nbytes = 4;
3946
3947 mapping_state (MAP_ARM);
3948 }
3949
3950 do
3951 {
3952 expressionS exp;
3953
3954 expression (& exp);
3955
3956 if (! emit_insn (& exp, nbytes))
3957 {
3958 ignore_rest_of_line ();
3959 return;
3960 }
3961 }
3962 while (*input_line_pointer++ == ',');
3963
3964 /* Put terminator back into stream. */
3965 input_line_pointer --;
3966 demand_empty_rest_of_line ();
3967}
b99bd4ef 3968
c19d1205 3969/* Parse a .rel31 directive. */
b99bd4ef 3970
c19d1205
ZW		 3971static void
3972s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3973{
3974 expressionS exp;
3975 char *p;
3976 valueT highbit;
b99bd4ef 3977
c19d1205
ZW		 3978 highbit = 0;
3979 if (*input_line_pointer == '1')
3980 highbit = 0x80000000;
3981 else if (*input_line_pointer != '0')
3982 as_bad (_("expected 0 or 1"));
b99bd4ef 3983
c19d1205
ZW		 3984 input_line_pointer++;
3985 if (*input_line_pointer != ',')
3986 as_bad (_("missing comma"));
3987 input_line_pointer++;
b99bd4ef 3988
c19d1205
ZW		 3989#ifdef md_flush_pending_output
3990 md_flush_pending_output ();
3991#endif
b99bd4ef 3992
c19d1205
ZW		 3993#ifdef md_cons_align
3994 md_cons_align (4);
3995#endif
b99bd4ef 3996
c19d1205 3997 mapping_state (MAP_DATA);
b99bd4ef 3998
c19d1205 3999 expression (&exp);
b99bd4ef 4000
c19d1205
ZW		 4001 p = frag_more (4);
4002 md_number_to_chars (p, highbit, 4);
4003 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
4004 BFD_RELOC_ARM_PREL31);
b99bd4ef 4005
c19d1205 4006 demand_empty_rest_of_line ();
b99bd4ef
NC		 4007}
4008
c19d1205 4009/* Directives: AEABI stack-unwind tables. */
b99bd4ef 4010
c19d1205 4011/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 4012
c19d1205
ZW		 4013static void
4014s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4015{
4016 demand_empty_rest_of_line ();
921e5f0a
PB		 4017 if (unwind.proc_start)
4018 {
c921be7d 4019 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB		 4020 return;
4021 }
4022
c19d1205
ZW		 4023 /* Mark the start of the function. */
4024 unwind.proc_start = expr_build_dot ();
b99bd4ef 4025
c19d1205
ZW		 4026 /* Reset the rest of the unwind info. */
4027 unwind.opcode_count = 0;
4028 unwind.table_entry = NULL;
4029 unwind.personality_routine = NULL;
4030 unwind.personality_index = -1;
4031 unwind.frame_size = 0;
4032 unwind.fp_offset = 0;
fdfde340 4033 unwind.fp_reg = REG_SP;
c19d1205
ZW		 4034 unwind.fp_used = 0;
4035 unwind.sp_restored = 0;
4036}
b99bd4ef 4037
b99bd4ef 4038
c19d1205
ZW		 4039/* Parse a handlerdata directive. Creates the exception handling table entry
4040 for the function. */
b99bd4ef 4041
c19d1205
ZW		 4042static void
4043s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4044{
4045 demand_empty_rest_of_line ();
921e5f0a 4046 if (!unwind.proc_start)
c921be7d 4047 as_bad (MISSING_FNSTART);
921e5f0a 4048
c19d1205 4049 if (unwind.table_entry)
6decc662 4050 as_bad (_("duplicate .handlerdata directive"));
f02232aa 4051
c19d1205
ZW		 4052 create_unwind_entry (1);
4053}
a737bd4d 4054
c19d1205 4055/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 4056
c19d1205
ZW		 4057static void
4058s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4059{
4060 long where;
4061 char *ptr;
4062 valueT val;
940b5ce0 4063 unsigned int marked_pr_dependency;
f02232aa 4064
c19d1205 4065 demand_empty_rest_of_line ();
f02232aa 4066
921e5f0a
PB		 4067 if (!unwind.proc_start)
4068 {
c921be7d 4069 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB		 4070 return;
4071 }
4072
c19d1205
ZW		 4073 /* Add eh table entry. */
4074 if (unwind.table_entry == NULL)
4075 val = create_unwind_entry (0);
4076 else
4077 val = 0;
f02232aa 4078
c19d1205
ZW		 4079 /* Add index table entry. This is two words. */
4080 start_unwind_section (unwind.saved_seg, 1);
4081 frag_align (2, 0, 0);
4082 record_alignment (now_seg, 2);
b99bd4ef 4083
c19d1205 4084 ptr = frag_more (8);
5011093d 4085 memset (ptr, 0, 8);
c19d1205 4086 where = frag_now_fix () - 8;
f02232aa 4087
c19d1205
ZW		 4088 /* Self relative offset of the function start. */
4089 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4090 BFD_RELOC_ARM_PREL31);
f02232aa 4091
c19d1205
ZW		 4092 /* Indicate dependency on EHABI-defined personality routines to the
4093 linker, if it hasn't been done already. */
940b5ce0
DJ		 4094 marked_pr_dependency
4095 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW		 4096 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4097 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4098 {
5f4273c7
NC		 4099 static const char *const name[] =
4100 {
4101 "__aeabi_unwind_cpp_pr0",
4102 "__aeabi_unwind_cpp_pr1",
4103 "__aeabi_unwind_cpp_pr2"
4104 };
c19d1205
ZW		 4105 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4106 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 4107 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 4108 |= 1 << unwind.personality_index;
c19d1205 4109 }
f02232aa 4110
c19d1205
ZW		 4111 if (val)
4112 /* Inline exception table entry. */
4113 md_number_to_chars (ptr + 4, val, 4);
4114 else
4115 /* Self relative offset of the table entry. */
4116 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4117 BFD_RELOC_ARM_PREL31);
f02232aa 4118
c19d1205
ZW		 4119 /* Restore the original section. */
4120 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB		 4121
4122 unwind.proc_start = NULL;
c19d1205 4123}
f02232aa 4124
f02232aa 4125
c19d1205 4126/* Parse an unwind_cantunwind directive. */
b99bd4ef 4127
c19d1205
ZW		 4128static void
4129s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4130{
4131 demand_empty_rest_of_line ();
921e5f0a 4132 if (!unwind.proc_start)
c921be7d 4133 as_bad (MISSING_FNSTART);
921e5f0a 4134
c19d1205
ZW		 4135 if (unwind.personality_routine || unwind.personality_index != -1)
4136 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 4137
c19d1205
ZW		 4138 unwind.personality_index = -2;
4139}
b99bd4ef 4140
b99bd4ef 4141
c19d1205 4142/* Parse a personalityindex directive. */
b99bd4ef 4143
c19d1205
ZW		 4144static void
4145s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4146{
4147 expressionS exp;
b99bd4ef 4148
921e5f0a 4149 if (!unwind.proc_start)
c921be7d 4150 as_bad (MISSING_FNSTART);
921e5f0a 4151
c19d1205
ZW		 4152 if (unwind.personality_routine || unwind.personality_index != -1)
4153 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 4154
c19d1205 4155 expression (&exp);
b99bd4ef 4156
c19d1205
ZW		 4157 if (exp.X_op != O_constant
4158 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 4159 {
c19d1205
ZW		 4160 as_bad (_("bad personality routine number"));
4161 ignore_rest_of_line ();
4162 return;
b99bd4ef
NC		 4163 }
4164
c19d1205 4165 unwind.personality_index = exp.X_add_number;
b99bd4ef 4166
c19d1205
ZW		 4167 demand_empty_rest_of_line ();
4168}
e16bb312 4169
e16bb312 4170
c19d1205 4171/* Parse a personality directive. */
e16bb312 4172
c19d1205
ZW		 4173static void
4174s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4175{
4176 char *name, *p, c;
a737bd4d 4177
921e5f0a 4178 if (!unwind.proc_start)
c921be7d 4179 as_bad (MISSING_FNSTART);
921e5f0a 4180
c19d1205
ZW		 4181 if (unwind.personality_routine || unwind.personality_index != -1)
4182 as_bad (_("duplicate .personality directive"));
a737bd4d 4183
d02603dc 4184 c = get_symbol_name (& name);
c19d1205 4185 p = input_line_pointer;
d02603dc
NC		 4186 if (c == '"')
4187 ++ input_line_pointer;
c19d1205
ZW		 4188 unwind.personality_routine = symbol_find_or_make (name);
4189 *p = c;
4190 demand_empty_rest_of_line ();
4191}
e16bb312 4192
e16bb312 4193
c19d1205 4194/* Parse a directive saving core registers. */
e16bb312 4195
c19d1205
ZW		 4196static void
4197s_arm_unwind_save_core (void)
e16bb312 4198{
c19d1205
ZW		 4199 valueT op;
4200 long range;
4201 int n;
e16bb312 4202
4b5a202f 4203 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
c19d1205 4204 if (range == FAIL)
e16bb312 4205 {
c19d1205
ZW		 4206 as_bad (_("expected register list"));
4207 ignore_rest_of_line ();
4208 return;
4209 }
e16bb312 4210
c19d1205 4211 demand_empty_rest_of_line ();
e16bb312 4212
c19d1205
ZW		 4213 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4214 into .unwind_save {..., sp...}. We aren't bothered about the value of
4215 ip because it is clobbered by calls. */
4216 if (unwind.sp_restored && unwind.fp_reg == 12
4217 && (range & 0x3000) == 0x1000)
4218 {
4219 unwind.opcode_count--;
4220 unwind.sp_restored = 0;
4221 range = (range | 0x2000) & ~0x1000;
4222 unwind.pending_offset = 0;
4223 }
e16bb312 4224
01ae4198
DJ		 4225 /* Pop r4-r15. */
4226 if (range & 0xfff0)
c19d1205 4227 {
01ae4198
DJ		 4228 /* See if we can use the short opcodes. These pop a block of up to 8
4229 registers starting with r4, plus maybe r14. */
4230 for (n = 0; n < 8; n++)
4231 {
4232 /* Break at the first non-saved register. */
4233 if ((range & (1 << (n + 4))) == 0)
4234 break;
4235 }
4236 /* See if there are any other bits set. */
4237 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4238 {
4239 /* Use the long form. */
4240 op = 0x8000 | ((range >> 4) & 0xfff);
4241 add_unwind_opcode (op, 2);
4242 }
0dd132b6 4243 else
01ae4198
DJ		 4244 {
4245 /* Use the short form. */
4246 if (range & 0x4000)
4247 op = 0xa8; /* Pop r14. */
4248 else
4249 op = 0xa0; /* Do not pop r14. */
4250 op |= (n - 1);
4251 add_unwind_opcode (op, 1);
4252 }
c19d1205 4253 }
0dd132b6 4254
c19d1205
ZW		 4255 /* Pop r0-r3. */
4256 if (range & 0xf)
4257 {
4258 op = 0xb100 | (range & 0xf);
4259 add_unwind_opcode (op, 2);
0dd132b6
NC		 4260 }
4261
c19d1205
ZW		 4262 /* Record the number of bytes pushed. */
4263 for (n = 0; n < 16; n++)
4264 {
4265 if (range & (1 << n))
4266 unwind.frame_size += 4;
4267 }
0dd132b6
NC		 4268}
4269
c19d1205
ZW		 4270
4271/* Parse a directive saving FPA registers. */
b99bd4ef
NC		 4272
4273static void
c19d1205 4274s_arm_unwind_save_fpa (int reg)
b99bd4ef 4275{
c19d1205
ZW		 4276 expressionS exp;
4277 int num_regs;
4278 valueT op;
b99bd4ef 4279
c19d1205
ZW		 4280 /* Get Number of registers to transfer. */
4281 if (skip_past_comma (&input_line_pointer) != FAIL)
4282 expression (&exp);
4283 else
4284 exp.X_op = O_illegal;
b99bd4ef 4285
c19d1205 4286 if (exp.X_op != O_constant)
b99bd4ef 4287 {
c19d1205
ZW		 4288 as_bad (_("expected , <constant>"));
4289 ignore_rest_of_line ();
b99bd4ef
NC		 4290 return;
4291 }
4292
c19d1205
ZW		 4293 num_regs = exp.X_add_number;
4294
4295 if (num_regs < 1 || num_regs > 4)
b99bd4ef 4296 {
c19d1205
ZW		 4297 as_bad (_("number of registers must be in the range [1:4]"));
4298 ignore_rest_of_line ();
b99bd4ef
NC		 4299 return;
4300 }
4301
c19d1205 4302 demand_empty_rest_of_line ();
b99bd4ef 4303
c19d1205
ZW		 4304 if (reg == 4)
4305 {
4306 /* Short form. */
4307 op = 0xb4 | (num_regs - 1);
4308 add_unwind_opcode (op, 1);
4309 }
b99bd4ef
NC		 4310 else
4311 {
c19d1205
ZW		 4312 /* Long form. */
4313 op = 0xc800 | (reg << 4) | (num_regs - 1);
4314 add_unwind_opcode (op, 2);
b99bd4ef 4315 }
c19d1205 4316 unwind.frame_size += num_regs * 12;
b99bd4ef
NC		 4317}
4318
c19d1205 4319
fa073d69
MS		 4320/* Parse a directive saving VFP registers for ARMv6 and above. */
4321
4322static void
4323s_arm_unwind_save_vfp_armv6 (void)
4324{
4325 int count;
4326 unsigned int start;
4327 valueT op;
4328 int num_vfpv3_regs = 0;
4329 int num_regs_below_16;
efd6b359 4330 bfd_boolean partial_match;
fa073d69 4331
efd6b359
AV		 4332 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4333 &partial_match);
fa073d69
MS		 4334 if (count == FAIL)
4335 {
4336 as_bad (_("expected register list"));
4337 ignore_rest_of_line ();
4338 return;
4339 }
4340
4341 demand_empty_rest_of_line ();
4342
4343 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4344 than FSTMX/FLDMX-style ones). */
4345
4346 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4347 if (start >= 16)
4348 num_vfpv3_regs = count;
4349 else if (start + count > 16)
4350 num_vfpv3_regs = start + count - 16;
4351
4352 if (num_vfpv3_regs > 0)
4353 {
4354 int start_offset = start > 16 ? start - 16 : 0;
4355 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4356 add_unwind_opcode (op, 2);
4357 }
4358
4359 /* Generate opcode for registers numbered in the range 0 .. 15. */
4360 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 4361 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS		 4362 if (num_regs_below_16 > 0)
4363 {
4364 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4365 add_unwind_opcode (op, 2);
4366 }
4367
4368 unwind.frame_size += count * 8;
4369}
4370
4371
4372/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC		 4373
4374static void
c19d1205 4375s_arm_unwind_save_vfp (void)
b99bd4ef 4376{
c19d1205 4377 int count;
ca3f61f7 4378 unsigned int reg;
c19d1205 4379 valueT op;
efd6b359 4380 bfd_boolean partial_match;
b99bd4ef 4381
efd6b359
AV		 4382 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D,
4383 &partial_match);
c19d1205 4384 if (count == FAIL)
b99bd4ef 4385 {
c19d1205
ZW		 4386 as_bad (_("expected register list"));
4387 ignore_rest_of_line ();
b99bd4ef
NC		 4388 return;
4389 }
4390
c19d1205 4391 demand_empty_rest_of_line ();
b99bd4ef 4392
c19d1205 4393 if (reg == 8)
b99bd4ef 4394 {
c19d1205
ZW		 4395 /* Short form. */
4396 op = 0xb8 | (count - 1);
4397 add_unwind_opcode (op, 1);
b99bd4ef 4398 }
c19d1205 4399 else
b99bd4ef 4400 {
c19d1205
ZW		 4401 /* Long form. */
4402 op = 0xb300 | (reg << 4) | (count - 1);
4403 add_unwind_opcode (op, 2);
b99bd4ef 4404 }
c19d1205
ZW		 4405 unwind.frame_size += count * 8 + 4;
4406}
b99bd4ef 4407
b99bd4ef 4408
c19d1205
ZW		 4409/* Parse a directive saving iWMMXt data registers. */
4410
4411static void
4412s_arm_unwind_save_mmxwr (void)
4413{
4414 int reg;
4415 int hi_reg;
4416 int i;
4417 unsigned mask = 0;
4418 valueT op;
b99bd4ef 4419
c19d1205
ZW		 4420 if (*input_line_pointer == '{')
4421 input_line_pointer++;
b99bd4ef 4422
c19d1205 4423 do
b99bd4ef 4424 {
dcbf9037 4425 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 4426
c19d1205 4427 if (reg == FAIL)
b99bd4ef 4428 {
9b7132d3 4429 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 4430 goto error;
b99bd4ef
NC		 4431 }
4432
c19d1205
ZW		 4433 if (mask >> reg)
4434 as_tsktsk (_("register list not in ascending order"));
4435 mask |= 1 << reg;
b99bd4ef 4436
c19d1205
ZW		 4437 if (*input_line_pointer == '-')
4438 {
4439 input_line_pointer++;
dcbf9037 4440 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW		 4441 if (hi_reg == FAIL)
4442 {
9b7132d3 4443 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW		 4444 goto error;
4445 }
4446 else if (reg >= hi_reg)
4447 {
4448 as_bad (_("bad register range"));
4449 goto error;
4450 }
4451 for (; reg < hi_reg; reg++)
4452 mask |= 1 << reg;
4453 }
4454 }
4455 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4456
d996d970 4457 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4458
c19d1205 4459 demand_empty_rest_of_line ();
b99bd4ef 4460
708587a4 4461 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4462 the list. */
4463 flush_pending_unwind ();
b99bd4ef 4464
c19d1205 4465 for (i = 0; i < 16; i++)
b99bd4ef 4466 {
c19d1205
ZW		 4467 if (mask & (1 << i))
4468 unwind.frame_size += 8;
b99bd4ef
NC		 4469 }
4470
c19d1205
ZW		 4471 /* Attempt to combine with a previous opcode. We do this because gcc
4472 likes to output separate unwind directives for a single block of
4473 registers. */
4474 if (unwind.opcode_count > 0)
b99bd4ef 4475 {
c19d1205
ZW		 4476 i = unwind.opcodes[unwind.opcode_count - 1];
4477 if ((i & 0xf8) == 0xc0)
4478 {
4479 i &= 7;
4480 /* Only merge if the blocks are contiguous. */
4481 if (i < 6)
4482 {
4483 if ((mask & 0xfe00) == (1 << 9))
4484 {
4485 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4486 unwind.opcode_count--;
4487 }
4488 }
4489 else if (i == 6 && unwind.opcode_count >= 2)
4490 {
4491 i = unwind.opcodes[unwind.opcode_count - 2];
4492 reg = i >> 4;
4493 i &= 0xf;
b99bd4ef 4494
c19d1205
ZW		 4495 op = 0xffff << (reg - 1);
4496 if (reg > 0
87a1fd79 4497 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW		 4498 {
4499 op = (1 << (reg + i + 1)) - 1;
4500 op &= ~((1 << reg) - 1);
4501 mask |= op;
4502 unwind.opcode_count -= 2;
4503 }
4504 }
4505 }
b99bd4ef
NC		 4506 }
4507
c19d1205
ZW		 4508 hi_reg = 15;
4509 /* We want to generate opcodes in the order the registers have been
4510 saved, ie. descending order. */
4511 for (reg = 15; reg >= -1; reg--)
b99bd4ef 4512 {
c19d1205
ZW		 4513 /* Save registers in blocks. */
4514 if (reg < 0
4515 || !(mask & (1 << reg)))
4516 {
4517 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 4518 preceding block. */
c19d1205
ZW		 4519 if (reg != hi_reg)
4520 {
4521 if (reg == 9)
4522 {
4523 /* Short form. */
4524 op = 0xc0 | (hi_reg - 10);
4525 add_unwind_opcode (op, 1);
4526 }
4527 else
4528 {
4529 /* Long form. */
4530 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4531 add_unwind_opcode (op, 2);
4532 }
4533 }
4534 hi_reg = reg - 1;
4535 }
b99bd4ef
NC		 4536 }
4537
c19d1205
ZW		 4538 return;
4539error:
4540 ignore_rest_of_line ();
b99bd4ef
NC		 4541}
4542
4543static void
c19d1205 4544s_arm_unwind_save_mmxwcg (void)
b99bd4ef 4545{
c19d1205
ZW		 4546 int reg;
4547 int hi_reg;
4548 unsigned mask = 0;
4549 valueT op;
b99bd4ef 4550
c19d1205
ZW		 4551 if (*input_line_pointer == '{')
4552 input_line_pointer++;
b99bd4ef 4553
477330fc
RM		 4554 skip_whitespace (input_line_pointer);
4555
c19d1205 4556 do
b99bd4ef 4557 {
dcbf9037 4558 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 4559
c19d1205
ZW		 4560 if (reg == FAIL)
4561 {
9b7132d3 4562 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4563 goto error;
4564 }
b99bd4ef 4565
c19d1205
ZW		 4566 reg -= 8;
4567 if (mask >> reg)
4568 as_tsktsk (_("register list not in ascending order"));
4569 mask |= 1 << reg;
b99bd4ef 4570
c19d1205
ZW		 4571 if (*input_line_pointer == '-')
4572 {
4573 input_line_pointer++;
dcbf9037 4574 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW		 4575 if (hi_reg == FAIL)
4576 {
9b7132d3 4577 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4578 goto error;
4579 }
4580 else if (reg >= hi_reg)
4581 {
4582 as_bad (_("bad register range"));
4583 goto error;
4584 }
4585 for (; reg < hi_reg; reg++)
4586 mask |= 1 << reg;
4587 }
b99bd4ef 4588 }
c19d1205 4589 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4590
d996d970 4591 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4592
c19d1205
ZW		 4593 demand_empty_rest_of_line ();
4594
708587a4 4595 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4596 the list. */
4597 flush_pending_unwind ();
b99bd4ef 4598
c19d1205 4599 for (reg = 0; reg < 16; reg++)
b99bd4ef 4600 {
c19d1205
ZW		 4601 if (mask & (1 << reg))
4602 unwind.frame_size += 4;
b99bd4ef 4603 }
c19d1205
ZW		 4604 op = 0xc700 | mask;
4605 add_unwind_opcode (op, 2);
4606 return;
4607error:
4608 ignore_rest_of_line ();
b99bd4ef
NC		 4609}
4610
c19d1205 4611
fa073d69
MS		 4612/* Parse an unwind_save directive.
4613 If the argument is non-zero, this is a .vsave directive. */
c19d1205 4614
b99bd4ef 4615static void
fa073d69 4616s_arm_unwind_save (int arch_v6)
b99bd4ef 4617{
c19d1205
ZW		 4618 char *peek;
4619 struct reg_entry *reg;
4620 bfd_boolean had_brace = FALSE;
b99bd4ef 4621
921e5f0a 4622 if (!unwind.proc_start)
c921be7d 4623 as_bad (MISSING_FNSTART);
921e5f0a 4624
c19d1205
ZW		 4625 /* Figure out what sort of save we have. */
4626 peek = input_line_pointer;
b99bd4ef 4627
c19d1205 4628 if (*peek == '{')
b99bd4ef 4629 {
c19d1205
ZW		 4630 had_brace = TRUE;
4631 peek++;
b99bd4ef
NC		 4632 }
4633
c19d1205 4634 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4635
c19d1205 4636 if (!reg)
b99bd4ef 4637 {
c19d1205
ZW		 4638 as_bad (_("register expected"));
4639 ignore_rest_of_line ();
b99bd4ef
NC		 4640 return;
4641 }
4642
c19d1205 4643 switch (reg->type)
b99bd4ef 4644 {
c19d1205
ZW		 4645 case REG_TYPE_FN:
4646 if (had_brace)
4647 {
4648 as_bad (_("FPA .unwind_save does not take a register list"));
4649 ignore_rest_of_line ();
4650 return;
4651 }
93ac2687 4652 input_line_pointer = peek;
c19d1205 4653 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4654 return;
c19d1205 4655
1f5afe1c
NC		 4656 case REG_TYPE_RN:
4657 s_arm_unwind_save_core ();
4658 return;
4659
fa073d69
MS		 4660 case REG_TYPE_VFD:
4661 if (arch_v6)
477330fc 4662 s_arm_unwind_save_vfp_armv6 ();
fa073d69 4663 else
477330fc 4664 s_arm_unwind_save_vfp ();
fa073d69 4665 return;
1f5afe1c
NC		 4666
4667 case REG_TYPE_MMXWR:
4668 s_arm_unwind_save_mmxwr ();
4669 return;
4670
4671 case REG_TYPE_MMXWCG:
4672 s_arm_unwind_save_mmxwcg ();
4673 return;
c19d1205
ZW		 4674
4675 default:
4676 as_bad (_(".unwind_save does not support this kind of register"));
4677 ignore_rest_of_line ();
b99bd4ef 4678 }
c19d1205 4679}
b99bd4ef 4680
b99bd4ef 4681
c19d1205
ZW		 4682/* Parse an unwind_movsp directive. */
4683
4684static void
4685s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4686{
4687 int reg;
4688 valueT op;
4fa3602b 4689 int offset;
c19d1205 4690
921e5f0a 4691 if (!unwind.proc_start)
c921be7d 4692 as_bad (MISSING_FNSTART);
921e5f0a 4693
dcbf9037 4694 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4695 if (reg == FAIL)
b99bd4ef 4696 {
9b7132d3 4697 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4698 ignore_rest_of_line ();
b99bd4ef
NC		 4699 return;
4700 }
4fa3602b
PB		 4701
4702 /* Optional constant. */
4703 if (skip_past_comma (&input_line_pointer) != FAIL)
4704 {
4705 if (immediate_for_directive (&offset) == FAIL)
4706 return;
4707 }
4708 else
4709 offset = 0;
4710
c19d1205 4711 demand_empty_rest_of_line ();
b99bd4ef 4712
c19d1205 4713 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4714 {
c19d1205 4715 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC		 4716 return;
4717 }
4718
c19d1205
ZW		 4719 if (unwind.fp_reg != REG_SP)
4720 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4721
c19d1205
ZW		 4722 /* Generate opcode to restore the value. */
4723 op = 0x90 | reg;
4724 add_unwind_opcode (op, 1);
4725
4726 /* Record the information for later. */
4727 unwind.fp_reg = reg;
4fa3602b 4728 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4729 unwind.sp_restored = 1;
b05fe5cf
ZW		 4730}
4731
c19d1205
ZW		 4732/* Parse an unwind_pad directive. */
4733
b05fe5cf 4734static void
c19d1205 4735s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4736{
c19d1205 4737 int offset;
b05fe5cf 4738
921e5f0a 4739 if (!unwind.proc_start)
c921be7d 4740 as_bad (MISSING_FNSTART);
921e5f0a 4741
c19d1205
ZW		 4742 if (immediate_for_directive (&offset) == FAIL)
4743 return;
b99bd4ef 4744
c19d1205
ZW		 4745 if (offset & 3)
4746 {
4747 as_bad (_("stack increment must be multiple of 4"));
4748 ignore_rest_of_line ();
4749 return;
4750 }
b99bd4ef 4751
c19d1205
ZW		 4752 /* Don't generate any opcodes, just record the details for later. */
4753 unwind.frame_size += offset;
4754 unwind.pending_offset += offset;
4755
4756 demand_empty_rest_of_line ();
4757}
4758
4759/* Parse an unwind_setfp directive. */
4760
4761static void
4762s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4763{
c19d1205
ZW		 4764 int sp_reg;
4765 int fp_reg;
4766 int offset;
4767
921e5f0a 4768 if (!unwind.proc_start)
c921be7d 4769 as_bad (MISSING_FNSTART);
921e5f0a 4770
dcbf9037 4771 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW		 4772 if (skip_past_comma (&input_line_pointer) == FAIL)
4773 sp_reg = FAIL;
4774 else
dcbf9037 4775 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4776
c19d1205
ZW		 4777 if (fp_reg == FAIL || sp_reg == FAIL)
4778 {
4779 as_bad (_("expected <reg>, <reg>"));
4780 ignore_rest_of_line ();
4781 return;
4782 }
b99bd4ef 4783
c19d1205
ZW		 4784 /* Optional constant. */
4785 if (skip_past_comma (&input_line_pointer) != FAIL)
4786 {
4787 if (immediate_for_directive (&offset) == FAIL)
4788 return;
4789 }
4790 else
4791 offset = 0;
a737bd4d 4792
c19d1205 4793 demand_empty_rest_of_line ();
a737bd4d 4794
fdfde340 4795 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4796 {
c19d1205
ZW		 4797 as_bad (_("register must be either sp or set by a previous"
4798 "unwind_movsp directive"));
4799 return;
a737bd4d
NC		 4800 }
4801
c19d1205
ZW		 4802 /* Don't generate any opcodes, just record the information for later. */
4803 unwind.fp_reg = fp_reg;
4804 unwind.fp_used = 1;
fdfde340 4805 if (sp_reg == REG_SP)
c19d1205
ZW		 4806 unwind.fp_offset = unwind.frame_size - offset;
4807 else
4808 unwind.fp_offset -= offset;
a737bd4d
NC		 4809}
4810
c19d1205
ZW		 4811/* Parse an unwind_raw directive. */
4812
4813static void
4814s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4815{
c19d1205 4816 expressionS exp;
708587a4 4817 /* This is an arbitrary limit. */
c19d1205
ZW		 4818 unsigned char op[16];
4819 int count;
a737bd4d 4820
921e5f0a 4821 if (!unwind.proc_start)
c921be7d 4822 as_bad (MISSING_FNSTART);
921e5f0a 4823
c19d1205
ZW		 4824 expression (&exp);
4825 if (exp.X_op == O_constant
4826 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4827 {
c19d1205
ZW		 4828 unwind.frame_size += exp.X_add_number;
4829 expression (&exp);
4830 }
4831 else
4832 exp.X_op = O_illegal;
a737bd4d 4833
c19d1205
ZW		 4834 if (exp.X_op != O_constant)
4835 {
4836 as_bad (_("expected <offset>, <opcode>"));
4837 ignore_rest_of_line ();
4838 return;
4839 }
a737bd4d 4840
c19d1205 4841 count = 0;
a737bd4d 4842
c19d1205
ZW		 4843 /* Parse the opcode. */
4844 for (;;)
4845 {
4846 if (count >= 16)
4847 {
4848 as_bad (_("unwind opcode too long"));
4849 ignore_rest_of_line ();
a737bd4d 4850 }
c19d1205 4851 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4852 {
c19d1205
ZW		 4853 as_bad (_("invalid unwind opcode"));
4854 ignore_rest_of_line ();
4855 return;
a737bd4d 4856 }
c19d1205 4857 op[count++] = exp.X_add_number;
a737bd4d 4858
c19d1205
ZW		 4859 /* Parse the next byte. */
4860 if (skip_past_comma (&input_line_pointer) == FAIL)
4861 break;
a737bd4d 4862
c19d1205
ZW		 4863 expression (&exp);
4864 }
b99bd4ef 4865
c19d1205
ZW		 4866 /* Add the opcode bytes in reverse order. */
4867 while (count--)
4868 add_unwind_opcode (op[count], 1);
b99bd4ef 4869
c19d1205 4870 demand_empty_rest_of_line ();
b99bd4ef 4871}
ee065d83
PB		 4872
4873
4874/* Parse a .eabi_attribute directive. */
4875
4876static void
4877s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4878{
0420f52b 4879 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
ee3c0378 4880
3076e594 4881 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
ee3c0378 4882 attributes_set_explicitly[tag] = 1;
ee065d83
PB		 4883}
4884
0855e32b
NS		 4885/* Emit a tls fix for the symbol. */
4886
4887static void
4888s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4889{
4890 char *p;
4891 expressionS exp;
4892#ifdef md_flush_pending_output
4893 md_flush_pending_output ();
4894#endif
4895
4896#ifdef md_cons_align
4897 md_cons_align (4);
4898#endif
4899
4900 /* Since we're just labelling the code, there's no need to define a
4901 mapping symbol. */
4902 expression (&exp);
4903 p = obstack_next_free (&frchain_now->frch_obstack);
4904 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4905 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4906 : BFD_RELOC_ARM_TLS_DESCSEQ);
4907}
cdf9ccec 4908#endif /* OBJ_ELF */
0855e32b 4909
ee065d83 4910static void s_arm_arch (int);
7a1d4c38 4911static void s_arm_object_arch (int);
ee065d83
PB		 4912static void s_arm_cpu (int);
4913static void s_arm_fpu (int);
69133863 4914static void s_arm_arch_extension (int);
b99bd4ef 4915
f0927246
NC		 4916#ifdef TE_PE
4917
4918static void
5f4273c7 4919pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC		 4920{
4921 expressionS exp;
4922
4923 do
4924 {
4925 expression (&exp);
4926 if (exp.X_op == O_symbol)
4927 exp.X_op = O_secrel;
4928
4929 emit_expr (&exp, 4);
4930 }
4931 while (*input_line_pointer++ == ',');
4932
4933 input_line_pointer--;
4934 demand_empty_rest_of_line ();
4935}
4936#endif /* TE_PE */
4937
5312fe52
BW		 4938int
4939arm_is_largest_exponent_ok (int precision)
4940{
4941 /* precision == 1 ensures that this will only return
4942 true for 16 bit floats. */
4943 return (precision == 1) && (fp16_format == ARM_FP16_FORMAT_ALTERNATIVE);
4944}
4945
4946static void
4947set_fp16_format (int dummy ATTRIBUTE_UNUSED)
4948{
4949 char saved_char;
4950 char* name;
4951 enum fp_16bit_format new_format;
4952
4953 new_format = ARM_FP16_FORMAT_DEFAULT;
4954
4955 name = input_line_pointer;
4956 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
4957 input_line_pointer++;
4958
4959 saved_char = *input_line_pointer;
4960 *input_line_pointer = 0;
4961
4962 if (strcasecmp (name, "ieee") == 0)
4963 new_format = ARM_FP16_FORMAT_IEEE;
4964 else if (strcasecmp (name, "alternative") == 0)
4965 new_format = ARM_FP16_FORMAT_ALTERNATIVE;
4966 else
4967 {
4968 as_bad (_("unrecognised float16 format \"%s\""), name);
4969 goto cleanup;
4970 }
4971
4972 /* Only set fp16_format if it is still the default (aka not already
4973 been set yet). */
4974 if (fp16_format == ARM_FP16_FORMAT_DEFAULT)
4975 fp16_format = new_format;
4976 else
4977 {
4978 if (new_format != fp16_format)
4979 as_warn (_("float16 format cannot be set more than once, ignoring."));
4980 }
4981
4982cleanup:
4983 *input_line_pointer = saved_char;
4984 ignore_rest_of_line ();
4985}
4986
c19d1205
ZW		 4987/* This table describes all the machine specific pseudo-ops the assembler
4988 has to support. The fields are:
4989 pseudo-op name without dot
4990 function to call to execute this pseudo-op
4991 Integer arg to pass to the function. */
b99bd4ef 4992
c19d1205 4993const pseudo_typeS md_pseudo_table[] =
b99bd4ef 4994{
c19d1205
ZW		 4995 /* Never called because '.req' does not start a line. */
4996 { "req", s_req, 0 },
dcbf9037
JB		 4997 /* Following two are likewise never called. */
4998 { "dn", s_dn, 0 },
4999 { "qn", s_qn, 0 },
c19d1205
ZW		 5000 { "unreq", s_unreq, 0 },
5001 { "bss", s_bss, 0 },
db2ed2e0 5002 { "align", s_align_ptwo, 2 },
c19d1205
ZW		 5003 { "arm", s_arm, 0 },
5004 { "thumb", s_thumb, 0 },
5005 { "code", s_code, 0 },
5006 { "force_thumb", s_force_thumb, 0 },
5007 { "thumb_func", s_thumb_func, 0 },
5008 { "thumb_set", s_thumb_set, 0 },
5009 { "even", s_even, 0 },
5010 { "ltorg", s_ltorg, 0 },
5011 { "pool", s_ltorg, 0 },
5012 { "syntax", s_syntax, 0 },
8463be01
PB		 5013 { "cpu", s_arm_cpu, 0 },
5014 { "arch", s_arm_arch, 0 },
7a1d4c38 5015 { "object_arch", s_arm_object_arch, 0 },
8463be01 5016 { "fpu", s_arm_fpu, 0 },
69133863 5017 { "arch_extension", s_arm_arch_extension, 0 },
c19d1205 5018#ifdef OBJ_ELF
c921be7d
NC		 5019 { "word", s_arm_elf_cons, 4 },
5020 { "long", s_arm_elf_cons, 4 },
5021 { "inst.n", s_arm_elf_inst, 2 },
5022 { "inst.w", s_arm_elf_inst, 4 },
5023 { "inst", s_arm_elf_inst, 0 },
5024 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW		 5025 { "fnstart", s_arm_unwind_fnstart, 0 },
5026 { "fnend", s_arm_unwind_fnend, 0 },
5027 { "cantunwind", s_arm_unwind_cantunwind, 0 },
5028 { "personality", s_arm_unwind_personality, 0 },
5029 { "personalityindex", s_arm_unwind_personalityindex, 0 },
5030 { "handlerdata", s_arm_unwind_handlerdata, 0 },
5031 { "save", s_arm_unwind_save, 0 },
fa073d69 5032 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW		 5033 { "movsp", s_arm_unwind_movsp, 0 },
5034 { "pad", s_arm_unwind_pad, 0 },
5035 { "setfp", s_arm_unwind_setfp, 0 },
5036 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 5037 { "eabi_attribute", s_arm_eabi_attribute, 0 },
0855e32b 5038 { "tlsdescseq", s_arm_tls_descseq, 0 },
c19d1205
ZW		 5039#else
5040 { "word", cons, 4},
f0927246
NC		 5041
5042 /* These are used for dwarf. */
5043 {"2byte", cons, 2},
5044 {"4byte", cons, 4},
5045 {"8byte", cons, 8},
5046 /* These are used for dwarf2. */
68d20676 5047 { "file", dwarf2_directive_file, 0 },
f0927246
NC		 5048 { "loc", dwarf2_directive_loc, 0 },
5049 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW		 5050#endif
5051 { "extend", float_cons, 'x' },
5052 { "ldouble", float_cons, 'x' },
5053 { "packed", float_cons, 'p' },
f0927246
NC		 5054#ifdef TE_PE
5055 {"secrel32", pe_directive_secrel, 0},
5056#endif
2e6976a8
DG		 5057
5058 /* These are for compatibility with CodeComposer Studio. */
5059 {"ref", s_ccs_ref, 0},
5060 {"def", s_ccs_def, 0},
5061 {"asmfunc", s_ccs_asmfunc, 0},
5062 {"endasmfunc", s_ccs_endasmfunc, 0},
5063
5312fe52
BW		 5064 {"float16", float_cons, 'h' },
5065 {"float16_format", set_fp16_format, 0 },
5066
c19d1205
ZW		 5067 { 0, 0, 0 }
5068};
5312fe52 5069
c19d1205 5070/* Parser functions used exclusively in instruction operands. */
b99bd4ef 5071
c19d1205
ZW		 5072/* Generic immediate-value read function for use in insn parsing.
5073 STR points to the beginning of the immediate (the leading #);
5074 VAL receives the value; if the value is outside [MIN, MAX]
5075 issue an error. PREFIX_OPT is true if the immediate prefix is
5076 optional. */
b99bd4ef 5077
c19d1205
ZW		 5078static int
5079parse_immediate (char **str, int *val, int min, int max,
5080 bfd_boolean prefix_opt)
5081{
5082 expressionS exp;
0198d5e6 5083
c19d1205
ZW		 5084 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5085 if (exp.X_op != O_constant)
b99bd4ef 5086 {
c19d1205
ZW		 5087 inst.error = _("constant expression required");
5088 return FAIL;
5089 }
b99bd4ef 5090
c19d1205
ZW		 5091 if (exp.X_add_number < min || exp.X_add_number > max)
5092 {
5093 inst.error = _("immediate value out of range");
5094 return FAIL;
5095 }
b99bd4ef 5096
c19d1205
ZW		 5097 *val = exp.X_add_number;
5098 return SUCCESS;
5099}
b99bd4ef 5100
5287ad62 5101/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 5102 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB		 5103 instructions. Puts the result directly in inst.operands[i]. */
5104
5105static int
8335d6aa
JW		 5106parse_big_immediate (char **str, int i, expressionS *in_exp,
5107 bfd_boolean allow_symbol_p)
5287ad62
JB		 5108{
5109 expressionS exp;
8335d6aa 5110 expressionS *exp_p = in_exp ? in_exp : &exp;
5287ad62
JB		 5111 char *ptr = *str;
5112
8335d6aa 5113 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5287ad62 5114
8335d6aa 5115 if (exp_p->X_op == O_constant)
036dc3f7 5116 {
8335d6aa 5117 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
036dc3f7
PB		 5118 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5119 O_constant. We have to be careful not to break compilation for
5120 32-bit X_add_number, though. */
8335d6aa 5121 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
036dc3f7 5122 {
8335d6aa
JW		 5123 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5124 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5125 & 0xffffffff);
036dc3f7
PB		 5126 inst.operands[i].regisimm = 1;
5127 }
5128 }
8335d6aa
JW		 5129 else if (exp_p->X_op == O_big
5130 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5287ad62
JB		 5131 {
5132 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
95b75c01 5133
5287ad62 5134 /* Bignums have their least significant bits in
477330fc
RM		 5135 generic_bignum[0]. Make sure we put 32 bits in imm and
5136 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 5137 gas_assert (parts != 0);
95b75c01
NC		 5138
5139 /* Make sure that the number is not too big.
5140 PR 11972: Bignums can now be sign-extended to the
5141 size of a .octa so check that the out of range bits
5142 are all zero or all one. */
8335d6aa 5143 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
95b75c01
NC		 5144 {
5145 LITTLENUM_TYPE m = -1;
5146
5147 if (generic_bignum[parts * 2] != 0
5148 && generic_bignum[parts * 2] != m)
5149 return FAIL;
5150
8335d6aa 5151 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
95b75c01
NC		 5152 if (generic_bignum[j] != generic_bignum[j-1])
5153 return FAIL;
5154 }
5155
5287ad62
JB		 5156 inst.operands[i].imm = 0;
5157 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 5158 inst.operands[i].imm |= generic_bignum[idx]
5159 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 5160 inst.operands[i].reg = 0;
5161 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 5162 inst.operands[i].reg |= generic_bignum[idx]
5163 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 5164 inst.operands[i].regisimm = 1;
5165 }
8335d6aa 5166 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5287ad62 5167 return FAIL;
5f4273c7 5168
5287ad62
JB		 5169 *str = ptr;
5170
5171 return SUCCESS;
5172}
5173
c19d1205
ZW		 5174/* Returns the pseudo-register number of an FPA immediate constant,
5175 or FAIL if there isn't a valid constant here. */
b99bd4ef 5176
c19d1205
ZW		 5177static int
5178parse_fpa_immediate (char ** str)
5179{
5180 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5181 char * save_in;
5182 expressionS exp;
5183 int i;
5184 int j;
b99bd4ef 5185
c19d1205
ZW		 5186 /* First try and match exact strings, this is to guarantee
5187 that some formats will work even for cross assembly. */
b99bd4ef 5188
c19d1205
ZW		 5189 for (i = 0; fp_const[i]; i++)
5190 {
5191 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 5192 {
c19d1205 5193 char *start = *str;
b99bd4ef 5194
c19d1205
ZW		 5195 *str += strlen (fp_const[i]);
5196 if (is_end_of_line[(unsigned char) **str])
5197 return i + 8;
5198 *str = start;
5199 }
5200 }
b99bd4ef 5201
c19d1205
ZW		 5202 /* Just because we didn't get a match doesn't mean that the constant
5203 isn't valid, just that it is in a format that we don't
5204 automatically recognize. Try parsing it with the standard
5205 expression routines. */
b99bd4ef 5206
c19d1205 5207 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 5208
c19d1205
ZW		 5209 /* Look for a raw floating point number. */
5210 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5211 && is_end_of_line[(unsigned char) *save_in])
5212 {
5213 for (i = 0; i < NUM_FLOAT_VALS; i++)
5214 {
5215 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 5216 {
c19d1205
ZW		 5217 if (words[j] != fp_values[i][j])
5218 break;
b99bd4ef
NC		 5219 }
5220
c19d1205 5221 if (j == MAX_LITTLENUMS)
b99bd4ef 5222 {
c19d1205
ZW		 5223 *str = save_in;
5224 return i + 8;
b99bd4ef
NC		 5225 }
5226 }
5227 }
b99bd4ef 5228
c19d1205
ZW		 5229 /* Try and parse a more complex expression, this will probably fail
5230 unless the code uses a floating point prefix (eg "0f"). */
5231 save_in = input_line_pointer;
5232 input_line_pointer = *str;
5233 if (expression (&exp) == absolute_section
5234 && exp.X_op == O_big
5235 && exp.X_add_number < 0)
5236 {
5237 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5238 Ditto for 15. */
ba592044
AM		 5239#define X_PRECISION 5
5240#define E_PRECISION 15L
5241 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
c19d1205
ZW		 5242 {
5243 for (i = 0; i < NUM_FLOAT_VALS; i++)
5244 {
5245 for (j = 0; j < MAX_LITTLENUMS; j++)
5246 {
5247 if (words[j] != fp_values[i][j])
5248 break;
5249 }
b99bd4ef 5250
c19d1205
ZW		 5251 if (j == MAX_LITTLENUMS)
5252 {
5253 *str = input_line_pointer;
5254 input_line_pointer = save_in;
5255 return i + 8;
5256 }
5257 }
5258 }
b99bd4ef
NC		 5259 }
5260
c19d1205
ZW		 5261 *str = input_line_pointer;
5262 input_line_pointer = save_in;
5263 inst.error = _("invalid FPA immediate expression");
5264 return FAIL;
b99bd4ef
NC		 5265}
5266
136da414
JB		 5267/* Returns 1 if a number has "quarter-precision" float format
5268 0baBbbbbbc defgh000 00000000 00000000. */
5269
5270static int
5271is_quarter_float (unsigned imm)
5272{
5273 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5274 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5275}
5276
aacf0b33
KT		 5277
5278/* Detect the presence of a floating point or integer zero constant,
5279 i.e. #0.0 or #0. */
5280
5281static bfd_boolean
5282parse_ifimm_zero (char **in)
5283{
5284 int error_code;
5285
5286 if (!is_immediate_prefix (**in))
3c6452ae
TP		 5287 {
5288 /* In unified syntax, all prefixes are optional. */
5289 if (!unified_syntax)
5290 return FALSE;
5291 }
5292 else
5293 ++*in;
0900a05b
JW		 5294
5295 /* Accept #0x0 as a synonym for #0. */
5296 if (strncmp (*in, "0x", 2) == 0)
5297 {
5298 int val;
5299 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5300 return FALSE;
5301 return TRUE;
5302 }
5303
aacf0b33
KT		 5304 error_code = atof_generic (in, ".", EXP_CHARS,
5305 &generic_floating_point_number);
5306
5307 if (!error_code
5308 && generic_floating_point_number.sign == '+'
5309 && (generic_floating_point_number.low
5310 > generic_floating_point_number.leader))
5311 return TRUE;
5312
5313 return FALSE;
5314}
5315
136da414
JB		 5316/* Parse an 8-bit "quarter-precision" floating point number of the form:
5317 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB		 5318 The zero and minus-zero cases need special handling, since they can't be
5319 encoded in the "quarter-precision" float format, but can nonetheless be
5320 loaded as integer constants. */
136da414
JB		 5321
5322static unsigned
5323parse_qfloat_immediate (char **ccp, int *immed)
5324{
5325 char *str = *ccp;
c96612cc 5326 char *fpnum;
136da414 5327 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 5328 int found_fpchar = 0;
5f4273c7 5329
136da414 5330 skip_past_char (&str, '#');
5f4273c7 5331
c96612cc
JB		 5332 /* We must not accidentally parse an integer as a floating-point number. Make
5333 sure that the value we parse is not an integer by checking for special
5334 characters '.' or 'e'.
5335 FIXME: This is a horrible hack, but doing better is tricky because type
5336 information isn't in a very usable state at parse time. */
5337 fpnum = str;
5338 skip_whitespace (fpnum);
5339
5340 if (strncmp (fpnum, "0x", 2) == 0)
5341 return FAIL;
5342 else
5343 {
5344 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
477330fc
RM		 5345 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5346 {
5347 found_fpchar = 1;
5348 break;
5349 }
c96612cc
JB		 5350
5351 if (!found_fpchar)
477330fc 5352 return FAIL;
c96612cc 5353 }
5f4273c7 5354
136da414
JB		 5355 if ((str = atof_ieee (str, 's', words)) != NULL)
5356 {
5357 unsigned fpword = 0;
5358 int i;
5f4273c7 5359
136da414
JB		 5360 /* Our FP word must be 32 bits (single-precision FP). */
5361 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
477330fc
RM		 5362 {
5363 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5364 fpword |= words[i];
5365 }
5f4273c7 5366
c96612cc 5367 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
477330fc 5368 *immed = fpword;
136da414 5369 else
477330fc 5370 return FAIL;
136da414
JB		 5371
5372 *ccp = str;
5f4273c7 5373
136da414
JB		 5374 return SUCCESS;
5375 }
5f4273c7 5376
136da414
JB		 5377 return FAIL;
5378}
5379
c19d1205
ZW		 5380/* Shift operands. */
5381enum shift_kind
b99bd4ef 5382{
f5f10c66 5383 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
c19d1205 5384};
b99bd4ef 5385
c19d1205
ZW		 5386struct asm_shift_name
5387{
5388 const char *name;
5389 enum shift_kind kind;
5390};
b99bd4ef 5391
c19d1205
ZW		 5392/* Third argument to parse_shift. */
5393enum parse_shift_mode
5394{
5395 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5396 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5397 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5398 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5399 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
f5f10c66 5400 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
c19d1205 5401};
b99bd4ef 5402
c19d1205
ZW		 5403/* Parse a <shift> specifier on an ARM data processing instruction.
5404 This has three forms:
b99bd4ef 5405
c19d1205
ZW		 5406 (LSL|LSR|ASL|ASR|ROR) Rs
5407 (LSL|LSR|ASL|ASR|ROR) #imm
5408 RRX
b99bd4ef 5409
c19d1205
ZW		 5410 Note that ASL is assimilated to LSL in the instruction encoding, and
5411 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 5412
c19d1205
ZW		 5413static int
5414parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 5415{
c19d1205
ZW		 5416 const struct asm_shift_name *shift_name;
5417 enum shift_kind shift;
5418 char *s = *str;
5419 char *p = s;
5420 int reg;
b99bd4ef 5421
c19d1205
ZW		 5422 for (p = *str; ISALPHA (*p); p++)
5423 ;
b99bd4ef 5424
c19d1205 5425 if (p == *str)
b99bd4ef 5426 {
c19d1205
ZW		 5427 inst.error = _("shift expression expected");
5428 return FAIL;
b99bd4ef
NC		 5429 }
5430
21d799b5 5431 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
477330fc 5432 p - *str);
c19d1205
ZW		 5433
5434 if (shift_name == NULL)
b99bd4ef 5435 {
c19d1205
ZW		 5436 inst.error = _("shift expression expected");
5437 return FAIL;
b99bd4ef
NC		 5438 }
5439
c19d1205 5440 shift = shift_name->kind;
b99bd4ef 5441
c19d1205
ZW		 5442 switch (mode)
5443 {
5444 case NO_SHIFT_RESTRICT:
f5f10c66
AV		 5445 case SHIFT_IMMEDIATE:
5446 if (shift == SHIFT_UXTW)
5447 {
5448 inst.error = _("'UXTW' not allowed here");
5449 return FAIL;
5450 }
5451 break;
b99bd4ef 5452
c19d1205
ZW		 5453 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5454 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5455 {
5456 inst.error = _("'LSL' or 'ASR' required");
5457 return FAIL;
5458 }
5459 break;
b99bd4ef 5460
c19d1205
ZW		 5461 case SHIFT_LSL_IMMEDIATE:
5462 if (shift != SHIFT_LSL)
5463 {
5464 inst.error = _("'LSL' required");
5465 return FAIL;
5466 }
5467 break;
b99bd4ef 5468
c19d1205
ZW		 5469 case SHIFT_ASR_IMMEDIATE:
5470 if (shift != SHIFT_ASR)
5471 {
5472 inst.error = _("'ASR' required");
5473 return FAIL;
5474 }
5475 break;
f5f10c66
AV		 5476 case SHIFT_UXTW_IMMEDIATE:
5477 if (shift != SHIFT_UXTW)
5478 {
5479 inst.error = _("'UXTW' required");
5480 return FAIL;
5481 }
5482 break;
b99bd4ef 5483
c19d1205
ZW		 5484 default: abort ();
5485 }
b99bd4ef 5486
c19d1205
ZW		 5487 if (shift != SHIFT_RRX)
5488 {
5489 /* Whitespace can appear here if the next thing is a bare digit. */
5490 skip_whitespace (p);
b99bd4ef 5491
c19d1205 5492 if (mode == NO_SHIFT_RESTRICT
dcbf9037 5493 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5494 {
5495 inst.operands[i].imm = reg;
5496 inst.operands[i].immisreg = 1;
5497 }
e2b0ab59 5498 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
c19d1205
ZW		 5499 return FAIL;
5500 }
5501 inst.operands[i].shift_kind = shift;
5502 inst.operands[i].shifted = 1;
5503 *str = p;
5504 return SUCCESS;
b99bd4ef
NC		 5505}
5506
c19d1205 5507/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 5508
c19d1205
ZW		 5509 #<immediate>
5510 #<immediate>, <rotate>
5511 <Rm>
5512 <Rm>, <shift>
b99bd4ef 5513
c19d1205
ZW		 5514 where <shift> is defined by parse_shift above, and <rotate> is a
5515 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 5516 is deferred to md_apply_fix. */
b99bd4ef 5517
c19d1205
ZW		 5518static int
5519parse_shifter_operand (char **str, int i)
5520{
5521 int value;
91d6fa6a 5522 expressionS exp;
b99bd4ef 5523
dcbf9037 5524 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5525 {
5526 inst.operands[i].reg = value;
5527 inst.operands[i].isreg = 1;
b99bd4ef 5528
c19d1205 5529 /* parse_shift will override this if appropriate */
e2b0ab59
AV		 5530 inst.relocs[0].exp.X_op = O_constant;
5531 inst.relocs[0].exp.X_add_number = 0;
b99bd4ef 5532
c19d1205
ZW		 5533 if (skip_past_comma (str) == FAIL)
5534 return SUCCESS;
b99bd4ef 5535
c19d1205
ZW		 5536 /* Shift operation on register. */
5537 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC		 5538 }
5539
e2b0ab59 5540 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
c19d1205 5541 return FAIL;
b99bd4ef 5542
c19d1205 5543 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 5544 {
c19d1205 5545 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 5546 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 5547 return FAIL;
b99bd4ef 5548
e2b0ab59 5549 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
c19d1205
ZW		 5550 {
5551 inst.error = _("constant expression expected");
5552 return FAIL;
5553 }
b99bd4ef 5554
91d6fa6a 5555 value = exp.X_add_number;
c19d1205
ZW		 5556 if (value < 0 || value > 30 || value % 2 != 0)
5557 {
5558 inst.error = _("invalid rotation");
5559 return FAIL;
5560 }
e2b0ab59
AV		 5561 if (inst.relocs[0].exp.X_add_number < 0
5562 || inst.relocs[0].exp.X_add_number > 255)
c19d1205
ZW		 5563 {
5564 inst.error = _("invalid constant");
5565 return FAIL;
5566 }
09d92015 5567
a415b1cd 5568 /* Encode as specified. */
e2b0ab59 5569 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
a415b1cd 5570 return SUCCESS;
09d92015
MM		 5571 }
5572
e2b0ab59
AV		 5573 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5574 inst.relocs[0].pc_rel = 0;
c19d1205 5575 return SUCCESS;
09d92015
MM		 5576}
5577
4962c51a
MS		 5578/* Group relocation information. Each entry in the table contains the
5579 textual name of the relocation as may appear in assembler source
5580 and must end with a colon.
5581 Along with this textual name are the relocation codes to be used if
5582 the corresponding instruction is an ALU instruction (ADD or SUB only),
5583 an LDR, an LDRS, or an LDC. */
5584
5585struct group_reloc_table_entry
5586{
5587 const char *name;
5588 int alu_code;
5589 int ldr_code;
5590 int ldrs_code;
5591 int ldc_code;
5592};
5593
5594typedef enum
5595{
5596 /* Varieties of non-ALU group relocation. */
5597
5598 GROUP_LDR,
5599 GROUP_LDRS,
35c228db
AV		 5600 GROUP_LDC,
5601 GROUP_MVE
4962c51a
MS		 5602} group_reloc_type;
5603
5604static struct group_reloc_table_entry group_reloc_table[] =
5605 { /* Program counter relative: */
5606 { "pc_g0_nc",
5607 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5608 0, /* LDR */
5609 0, /* LDRS */
5610 0 }, /* LDC */
5611 { "pc_g0",
5612 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5613 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5614 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5615 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5616 { "pc_g1_nc",
5617 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5618 0, /* LDR */
5619 0, /* LDRS */
5620 0 }, /* LDC */
5621 { "pc_g1",
5622 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5623 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5624 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5625 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5626 { "pc_g2",
5627 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5628 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5629 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5630 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5631 /* Section base relative */
5632 { "sb_g0_nc",
5633 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5634 0, /* LDR */
5635 0, /* LDRS */
5636 0 }, /* LDC */
5637 { "sb_g0",
5638 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5639 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5640 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5641 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5642 { "sb_g1_nc",
5643 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5644 0, /* LDR */
5645 0, /* LDRS */
5646 0 }, /* LDC */
5647 { "sb_g1",
5648 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5649 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5650 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5651 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5652 { "sb_g2",
5653 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5654 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5655 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
72d98d16
MG		 5656 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5657 /* Absolute thumb alu relocations. */
5658 { "lower0_7",
5659 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5660 0, /* LDR. */
5661 0, /* LDRS. */
5662 0 }, /* LDC. */
5663 { "lower8_15",
5664 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5665 0, /* LDR. */
5666 0, /* LDRS. */
5667 0 }, /* LDC. */
5668 { "upper0_7",
5669 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5670 0, /* LDR. */
5671 0, /* LDRS. */
5672 0 }, /* LDC. */
5673 { "upper8_15",
5674 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5675 0, /* LDR. */
5676 0, /* LDRS. */
5677 0 } }; /* LDC. */
4962c51a
MS		 5678
5679/* Given the address of a pointer pointing to the textual name of a group
5680 relocation as may appear in assembler source, attempt to find its details
5681 in group_reloc_table. The pointer will be updated to the character after
5682 the trailing colon. On failure, FAIL will be returned; SUCCESS
5683 otherwise. On success, *entry will be updated to point at the relevant
5684 group_reloc_table entry. */
5685
5686static int
5687find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5688{
5689 unsigned int i;
5690 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5691 {
5692 int length = strlen (group_reloc_table[i].name);
5693
5f4273c7
NC		 5694 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5695 && (*str)[length] == ':')
477330fc
RM		 5696 {
5697 *out = &group_reloc_table[i];
5698 *str += (length + 1);
5699 return SUCCESS;
5700 }
4962c51a
MS		 5701 }
5702
5703 return FAIL;
5704}
5705
5706/* Parse a <shifter_operand> for an ARM data processing instruction
5707 (as for parse_shifter_operand) where group relocations are allowed:
5708
5709 #<immediate>
5710 #<immediate>, <rotate>
5711 #:<group_reloc>:<expression>
5712 <Rm>
5713 <Rm>, <shift>
5714
5715 where <group_reloc> is one of the strings defined in group_reloc_table.
5716 The hashes are optional.
5717
5718 Everything else is as for parse_shifter_operand. */
5719
5720static parse_operand_result
5721parse_shifter_operand_group_reloc (char **str, int i)
5722{
5723 /* Determine if we have the sequence of characters #: or just :
5724 coming next. If we do, then we check for a group relocation.
5725 If we don't, punt the whole lot to parse_shifter_operand. */
5726
5727 if (((*str)[0] == '#' && (*str)[1] == ':')
5728 || (*str)[0] == ':')
5729 {
5730 struct group_reloc_table_entry *entry;
5731
5732 if ((*str)[0] == '#')
477330fc 5733 (*str) += 2;
4962c51a 5734 else
477330fc 5735 (*str)++;
4962c51a
MS		 5736
5737 /* Try to parse a group relocation. Anything else is an error. */
5738 if (find_group_reloc_table_entry (str, &entry) == FAIL)
477330fc
RM		 5739 {
5740 inst.error = _("unknown group relocation");
5741 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5742 }
4962c51a
MS		 5743
5744 /* We now have the group relocation table entry corresponding to
477330fc 5745 the name in the assembler source. Next, we parse the expression. */
e2b0ab59 5746 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
477330fc 5747 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4962c51a
MS		 5748
5749 /* Record the relocation type (always the ALU variant here). */
e2b0ab59
AV		 5750 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5751 gas_assert (inst.relocs[0].type != 0);
4962c51a
MS		 5752
5753 return PARSE_OPERAND_SUCCESS;
5754 }
5755 else
5756 return parse_shifter_operand (str, i) == SUCCESS
477330fc 5757 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4962c51a
MS		 5758
5759 /* Never reached. */
5760}
5761
8e560766
MGD		 5762/* Parse a Neon alignment expression. Information is written to
5763 inst.operands[i]. We assume the initial ':' has been skipped.
fa94de6b 5764
8e560766
MGD		 5765 align .imm = align << 8, .immisalign=1, .preind=0 */
5766static parse_operand_result
5767parse_neon_alignment (char **str, int i)
5768{
5769 char *p = *str;
5770 expressionS exp;
5771
5772 my_get_expression (&exp, &p, GE_NO_PREFIX);
5773
5774 if (exp.X_op != O_constant)
5775 {
5776 inst.error = _("alignment must be constant");
5777 return PARSE_OPERAND_FAIL;
5778 }
5779
5780 inst.operands[i].imm = exp.X_add_number << 8;
5781 inst.operands[i].immisalign = 1;
5782 /* Alignments are not pre-indexes. */
5783 inst.operands[i].preind = 0;
5784
5785 *str = p;
5786 return PARSE_OPERAND_SUCCESS;
5787}
5788
c19d1205 5789/* Parse all forms of an ARM address expression. Information is written
e2b0ab59 5790 to inst.operands[i] and/or inst.relocs[0].
09d92015 5791
c19d1205 5792 Preindexed addressing (.preind=1):
09d92015 5793
e2b0ab59 5794 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
c19d1205
ZW		 5795 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5796 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5797 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5798
c19d1205 5799 These three may have a trailing ! which causes .writeback to be set also.
09d92015 5800
c19d1205 5801 Postindexed addressing (.postind=1, .writeback=1):
09d92015 5802
e2b0ab59 5803 [Rn], #offset .reg=Rn .relocs[0].exp=offset
c19d1205
ZW		 5804 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5805 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5806 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5807
c19d1205 5808 Unindexed addressing (.preind=0, .postind=0):
09d92015 5809
c19d1205 5810 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5811
c19d1205 5812 Other:
09d92015 5813
c19d1205 5814 [Rn]{!} shorthand for [Rn,#0]{!}
e2b0ab59
AV		 5815 =immediate .isreg=0 .relocs[0].exp=immediate
5816 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
09d92015 5817
c19d1205 5818 It is the caller's responsibility to check for addressing modes not
e2b0ab59 5819 supported by the instruction, and to set inst.relocs[0].type. */
c19d1205 5820
4962c51a
MS		 5821static parse_operand_result
5822parse_address_main (char **str, int i, int group_relocations,
477330fc 5823 group_reloc_type group_type)
09d92015 5824{
c19d1205
ZW		 5825 char *p = *str;
5826 int reg;
09d92015 5827
c19d1205 5828 if (skip_past_char (&p, '[') == FAIL)
09d92015 5829 {
c19d1205
ZW		 5830 if (skip_past_char (&p, '=') == FAIL)
5831 {
974da60d 5832 /* Bare address - translate to PC-relative offset. */
e2b0ab59 5833 inst.relocs[0].pc_rel = 1;
c19d1205
ZW		 5834 inst.operands[i].reg = REG_PC;
5835 inst.operands[i].isreg = 1;
5836 inst.operands[i].preind = 1;
09d92015 5837
e2b0ab59 5838 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
8335d6aa
JW		 5839 return PARSE_OPERAND_FAIL;
5840 }
e2b0ab59 5841 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
8335d6aa 5842 /*allow_symbol_p=*/TRUE))
4962c51a 5843 return PARSE_OPERAND_FAIL;
09d92015 5844
c19d1205 5845 *str = p;
4962c51a 5846 return PARSE_OPERAND_SUCCESS;
09d92015
MM		 5847 }
5848
8ab8155f
NC		 5849 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5850 skip_whitespace (p);
5851
f5f10c66
AV		 5852 if (group_type == GROUP_MVE)
5853 {
5854 enum arm_reg_type rtype = REG_TYPE_MQ;
5855 struct neon_type_el et;
5856 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5857 {
5858 inst.operands[i].isquad = 1;
5859 }
5860 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5861 {
5862 inst.error = BAD_ADDR_MODE;
5863 return PARSE_OPERAND_FAIL;
5864 }
5865 }
5866 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5867 {
35c228db
AV		 5868 if (group_type == GROUP_MVE)
5869 inst.error = BAD_ADDR_MODE;
5870 else
5871 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5872 return PARSE_OPERAND_FAIL;
09d92015 5873 }
c19d1205
ZW		 5874 inst.operands[i].reg = reg;
5875 inst.operands[i].isreg = 1;
09d92015 5876
c19d1205 5877 if (skip_past_comma (&p) == SUCCESS)
09d92015 5878 {
c19d1205 5879 inst.operands[i].preind = 1;
09d92015 5880
c19d1205
ZW		 5881 if (*p == '+') p++;
5882 else if (*p == '-') p++, inst.operands[i].negative = 1;
5883
f5f10c66
AV		 5884 enum arm_reg_type rtype = REG_TYPE_MQ;
5885 struct neon_type_el et;
5886 if (group_type == GROUP_MVE
5887 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5888 {
5889 inst.operands[i].immisreg = 2;
5890 inst.operands[i].imm = reg;
5891
5892 if (skip_past_comma (&p) == SUCCESS)
5893 {
5894 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
5895 {
5896 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5897 inst.relocs[0].exp.X_add_number = 0;
5898 }
5899 else
5900 return PARSE_OPERAND_FAIL;
5901 }
5902 }
5903 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 5904 {
c19d1205
ZW		 5905 inst.operands[i].imm = reg;
5906 inst.operands[i].immisreg = 1;
5907
5908 if (skip_past_comma (&p) == SUCCESS)
5909 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5910 return PARSE_OPERAND_FAIL;
c19d1205 5911 }
5287ad62 5912 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD		 5913 {
5914 /* FIXME: '@' should be used here, but it's filtered out by generic
5915 code before we get to see it here. This may be subject to
5916 change. */
5917 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5918
8e560766
MGD		 5919 if (result != PARSE_OPERAND_SUCCESS)
5920 return result;
5921 }
c19d1205
ZW		 5922 else
5923 {
5924 if (inst.operands[i].negative)
5925 {
5926 inst.operands[i].negative = 0;
5927 p--;
5928 }
4962c51a 5929
5f4273c7
NC		 5930 if (group_relocations
5931 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS		 5932 {
5933 struct group_reloc_table_entry *entry;
5934
477330fc
RM		 5935 /* Skip over the #: or : sequence. */
5936 if (*p == '#')
5937 p += 2;
5938 else
5939 p++;
4962c51a
MS		 5940
5941 /* Try to parse a group relocation. Anything else is an
477330fc 5942 error. */
4962c51a
MS		 5943 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5944 {
5945 inst.error = _("unknown group relocation");
5946 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5947 }
5948
5949 /* We now have the group relocation table entry corresponding to
5950 the name in the assembler source. Next, we parse the
477330fc 5951 expression. */
e2b0ab59 5952 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
4962c51a
MS		 5953 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5954
5955 /* Record the relocation type. */
477330fc
RM		 5956 switch (group_type)
5957 {
5958 case GROUP_LDR:
e2b0ab59
AV		 5959 inst.relocs[0].type
5960 = (bfd_reloc_code_real_type) entry->ldr_code;
477330fc 5961 break;
4962c51a 5962
477330fc 5963 case GROUP_LDRS:
e2b0ab59
AV		 5964 inst.relocs[0].type
5965 = (bfd_reloc_code_real_type) entry->ldrs_code;
477330fc 5966 break;
4962c51a 5967
477330fc 5968 case GROUP_LDC:
e2b0ab59
AV		 5969 inst.relocs[0].type
5970 = (bfd_reloc_code_real_type) entry->ldc_code;
477330fc 5971 break;
4962c51a 5972
477330fc
RM		 5973 default:
5974 gas_assert (0);
5975 }
4962c51a 5976
e2b0ab59 5977 if (inst.relocs[0].type == 0)
4962c51a
MS		 5978 {
5979 inst.error = _("this group relocation is not allowed on this instruction");
5980 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5981 }
477330fc
RM		 5982 }
5983 else
26d97720
NS		 5984 {
5985 char *q = p;
0198d5e6 5986
e2b0ab59 5987 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
26d97720
NS		 5988 return PARSE_OPERAND_FAIL;
5989 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV		 5990 if (inst.relocs[0].exp.X_op == O_constant
5991 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS		 5992 {
5993 skip_whitespace (q);
5994 if (*q == '#')
5995 {
5996 q++;
5997 skip_whitespace (q);
5998 }
5999 if (*q == '-')
6000 inst.operands[i].negative = 1;
6001 }
6002 }
09d92015
MM		 6003 }
6004 }
8e560766
MGD		 6005 else if (skip_past_char (&p, ':') == SUCCESS)
6006 {
6007 /* FIXME: '@' should be used here, but it's filtered out by generic code
6008 before we get to see it here. This may be subject to change. */
6009 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 6010
8e560766
MGD		 6011 if (result != PARSE_OPERAND_SUCCESS)
6012 return result;
6013 }
09d92015 6014
c19d1205 6015 if (skip_past_char (&p, ']') == FAIL)
09d92015 6016 {
c19d1205 6017 inst.error = _("']' expected");
4962c51a 6018 return PARSE_OPERAND_FAIL;
09d92015
MM		 6019 }
6020
c19d1205
ZW		 6021 if (skip_past_char (&p, '!') == SUCCESS)
6022 inst.operands[i].writeback = 1;
09d92015 6023
c19d1205 6024 else if (skip_past_comma (&p) == SUCCESS)
09d92015 6025 {
c19d1205
ZW		 6026 if (skip_past_char (&p, '{') == SUCCESS)
6027 {
6028 /* [Rn], {expr} - unindexed, with option */
6029 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 6030 0, 255, TRUE) == FAIL)
4962c51a 6031 return PARSE_OPERAND_FAIL;
09d92015 6032
c19d1205
ZW		 6033 if (skip_past_char (&p, '}') == FAIL)
6034 {
6035 inst.error = _("'}' expected at end of 'option' field");
4962c51a 6036 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6037 }
6038 if (inst.operands[i].preind)
6039 {
6040 inst.error = _("cannot combine index with option");
4962c51a 6041 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6042 }
6043 *str = p;
4962c51a 6044 return PARSE_OPERAND_SUCCESS;
09d92015 6045 }
c19d1205
ZW		 6046 else
6047 {
6048 inst.operands[i].postind = 1;
6049 inst.operands[i].writeback = 1;
09d92015 6050
c19d1205
ZW		 6051 if (inst.operands[i].preind)
6052 {
6053 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 6054 return PARSE_OPERAND_FAIL;
c19d1205 6055 }
09d92015 6056
c19d1205
ZW		 6057 if (*p == '+') p++;
6058 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 6059
f5f10c66
AV		 6060 enum arm_reg_type rtype = REG_TYPE_MQ;
6061 struct neon_type_el et;
6062 if (group_type == GROUP_MVE
6063 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6064 {
6065 inst.operands[i].immisreg = 2;
6066 inst.operands[i].imm = reg;
6067 }
6068 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 6069 {
477330fc
RM		 6070 /* We might be using the immediate for alignment already. If we
6071 are, OR the register number into the low-order bits. */
6072 if (inst.operands[i].immisalign)
6073 inst.operands[i].imm |= reg;
6074 else
6075 inst.operands[i].imm = reg;
c19d1205 6076 inst.operands[i].immisreg = 1;
a737bd4d 6077
c19d1205
ZW		 6078 if (skip_past_comma (&p) == SUCCESS)
6079 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 6080 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6081 }
6082 else
6083 {
26d97720 6084 char *q = p;
0198d5e6 6085
c19d1205
ZW		 6086 if (inst.operands[i].negative)
6087 {
6088 inst.operands[i].negative = 0;
6089 p--;
6090 }
e2b0ab59 6091 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
4962c51a 6092 return PARSE_OPERAND_FAIL;
26d97720 6093 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV		 6094 if (inst.relocs[0].exp.X_op == O_constant
6095 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS		 6096 {
6097 skip_whitespace (q);
6098 if (*q == '#')
6099 {
6100 q++;
6101 skip_whitespace (q);
6102 }
6103 if (*q == '-')
6104 inst.operands[i].negative = 1;
6105 }
c19d1205
ZW		 6106 }
6107 }
a737bd4d
NC		 6108 }
6109
c19d1205
ZW		 6110 /* If at this point neither .preind nor .postind is set, we have a
6111 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6112 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6113 {
6114 inst.operands[i].preind = 1;
e2b0ab59
AV		 6115 inst.relocs[0].exp.X_op = O_constant;
6116 inst.relocs[0].exp.X_add_number = 0;
c19d1205
ZW		 6117 }
6118 *str = p;
4962c51a
MS		 6119 return PARSE_OPERAND_SUCCESS;
6120}
6121
6122static int
6123parse_address (char **str, int i)
6124{
21d799b5 6125 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
477330fc 6126 ? SUCCESS : FAIL;
4962c51a
MS		 6127}
6128
6129static parse_operand_result
6130parse_address_group_reloc (char **str, int i, group_reloc_type type)
6131{
6132 return parse_address_main (str, i, 1, type);
a737bd4d
NC		 6133}
6134
b6895b4f
PB		 6135/* Parse an operand for a MOVW or MOVT instruction. */
6136static int
6137parse_half (char **str)
6138{
6139 char * p;
5f4273c7 6140
b6895b4f
PB		 6141 p = *str;
6142 skip_past_char (&p, '#');
5f4273c7 6143 if (strncasecmp (p, ":lower16:", 9) == 0)
e2b0ab59 6144 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
b6895b4f 6145 else if (strncasecmp (p, ":upper16:", 9) == 0)
e2b0ab59 6146 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
b6895b4f 6147
e2b0ab59 6148 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
b6895b4f
PB		 6149 {
6150 p += 9;
5f4273c7 6151 skip_whitespace (p);
b6895b4f
PB		 6152 }
6153
e2b0ab59 6154 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
b6895b4f
PB		 6155 return FAIL;
6156
e2b0ab59 6157 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 6158 {
e2b0ab59 6159 if (inst.relocs[0].exp.X_op != O_constant)
b6895b4f
PB		 6160 {
6161 inst.error = _("constant expression expected");
6162 return FAIL;
6163 }
e2b0ab59
AV		 6164 if (inst.relocs[0].exp.X_add_number < 0
6165 || inst.relocs[0].exp.X_add_number > 0xffff)
b6895b4f
PB		 6166 {
6167 inst.error = _("immediate value out of range");
6168 return FAIL;
6169 }
6170 }
6171 *str = p;
6172 return SUCCESS;
6173}
6174
c19d1205 6175/* Miscellaneous. */
a737bd4d 6176
c19d1205
ZW		 6177/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6178 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6179static int
d2cd1205 6180parse_psr (char **str, bfd_boolean lhs)
09d92015 6181{
c19d1205
ZW		 6182 char *p;
6183 unsigned long psr_field;
62b3e311
PB		 6184 const struct asm_psr *psr;
6185 char *start;
d2cd1205 6186 bfd_boolean is_apsr = FALSE;
ac7f631b 6187 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
09d92015 6188
a4482bb6
NC		 6189 /* PR gas/12698: If the user has specified -march=all then m_profile will
6190 be TRUE, but we want to ignore it in this case as we are building for any
6191 CPU type, including non-m variants. */
823d2571 6192 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
a4482bb6
NC		 6193 m_profile = FALSE;
6194
c19d1205
ZW		 6195 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6196 feature for ease of use and backwards compatibility. */
6197 p = *str;
62b3e311 6198 if (strncasecmp (p, "SPSR", 4) == 0)
d2cd1205
JB		 6199 {
6200 if (m_profile)
6201 goto unsupported_psr;
fa94de6b 6202
d2cd1205
JB		 6203 psr_field = SPSR_BIT;
6204 }
6205 else if (strncasecmp (p, "CPSR", 4) == 0)
6206 {
6207 if (m_profile)
6208 goto unsupported_psr;
6209
6210 psr_field = 0;
6211 }
6212 else if (strncasecmp (p, "APSR", 4) == 0)
6213 {
6214 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6215 and ARMv7-R architecture CPUs. */
6216 is_apsr = TRUE;
6217 psr_field = 0;
6218 }
6219 else if (m_profile)
62b3e311
PB		 6220 {
6221 start = p;
6222 do
6223 p++;
6224 while (ISALNUM (*p) || *p == '_');
6225
d2cd1205
JB		 6226 if (strncasecmp (start, "iapsr", 5) == 0
6227 || strncasecmp (start, "eapsr", 5) == 0
6228 || strncasecmp (start, "xpsr", 4) == 0
6229 || strncasecmp (start, "psr", 3) == 0)
6230 p = start + strcspn (start, "rR") + 1;
6231
21d799b5 6232 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
477330fc 6233 p - start);
d2cd1205 6234
62b3e311
PB		 6235 if (!psr)
6236 return FAIL;
09d92015 6237
d2cd1205
JB		 6238 /* If APSR is being written, a bitfield may be specified. Note that
6239 APSR itself is handled above. */
6240 if (psr->field <= 3)
6241 {
6242 psr_field = psr->field;
6243 is_apsr = TRUE;
6244 goto check_suffix;
6245 }
6246
62b3e311 6247 *str = p;
d2cd1205
JB		 6248 /* M-profile MSR instructions have the mask field set to "10", except
6249 *PSR variants which modify APSR, which may use a different mask (and
6250 have been handled already). Do that by setting the PSR_f field
6251 here. */
6252 return psr->field | (lhs ? PSR_f : 0);
62b3e311 6253 }
d2cd1205
JB		 6254 else
6255 goto unsupported_psr;
09d92015 6256
62b3e311 6257 p += 4;
d2cd1205 6258check_suffix:
c19d1205
ZW		 6259 if (*p == '_')
6260 {
6261 /* A suffix follows. */
c19d1205
ZW		 6262 p++;
6263 start = p;
a737bd4d 6264
c19d1205
ZW		 6265 do
6266 p++;
6267 while (ISALNUM (*p) || *p == '_');
a737bd4d 6268
d2cd1205
JB		 6269 if (is_apsr)
6270 {
6271 /* APSR uses a notation for bits, rather than fields. */
6272 unsigned int nzcvq_bits = 0;
6273 unsigned int g_bit = 0;
6274 char *bit;
fa94de6b 6275
d2cd1205
JB		 6276 for (bit = start; bit != p; bit++)
6277 {
6278 switch (TOLOWER (*bit))
477330fc 6279 {
d2cd1205
JB		 6280 case 'n':
6281 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6282 break;
6283
6284 case 'z':
6285 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6286 break;
6287
6288 case 'c':
6289 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6290 break;
6291
6292 case 'v':
6293 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6294 break;
fa94de6b 6295
d2cd1205
JB		 6296 case 'q':
6297 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6298 break;
fa94de6b 6299
d2cd1205
JB		 6300 case 'g':
6301 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6302 break;
fa94de6b 6303
d2cd1205
JB		 6304 default:
6305 inst.error = _("unexpected bit specified after APSR");
6306 return FAIL;
6307 }
6308 }
fa94de6b 6309
d2cd1205
JB		 6310 if (nzcvq_bits == 0x1f)
6311 psr_field |= PSR_f;
fa94de6b 6312
d2cd1205
JB		 6313 if (g_bit == 0x1)
6314 {
6315 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
477330fc 6316 {
d2cd1205
JB		 6317 inst.error = _("selected processor does not "
6318 "support DSP extension");
6319 return FAIL;
6320 }
6321
6322 psr_field |= PSR_s;
6323 }
fa94de6b 6324
d2cd1205
JB		 6325 if ((nzcvq_bits & 0x20) != 0
6326 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6327 || (g_bit & 0x2) != 0)
6328 {
6329 inst.error = _("bad bitmask specified after APSR");
6330 return FAIL;
6331 }
6332 }
6333 else
477330fc 6334 {
d2cd1205 6335 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
477330fc 6336 p - start);
d2cd1205 6337 if (!psr)
477330fc 6338 goto error;
a737bd4d 6339
d2cd1205
JB		 6340 psr_field |= psr->field;
6341 }
a737bd4d 6342 }
c19d1205 6343 else
a737bd4d 6344 {
c19d1205
ZW		 6345 if (ISALNUM (*p))
6346 goto error; /* Garbage after "[CS]PSR". */
6347
d2cd1205 6348 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
477330fc 6349 is deprecated, but allow it anyway. */
d2cd1205
JB		 6350 if (is_apsr && lhs)
6351 {
6352 psr_field |= PSR_f;
6353 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6354 "deprecated"));
6355 }
6356 else if (!m_profile)
6357 /* These bits are never right for M-profile devices: don't set them
6358 (only code paths which read/write APSR reach here). */
6359 psr_field |= (PSR_c | PSR_f);
a737bd4d 6360 }
c19d1205
ZW		 6361 *str = p;
6362 return psr_field;
a737bd4d 6363
d2cd1205
JB		 6364 unsupported_psr:
6365 inst.error = _("selected processor does not support requested special "
6366 "purpose register");
6367 return FAIL;
6368
c19d1205
ZW		 6369 error:
6370 inst.error = _("flag for {c}psr instruction expected");
6371 return FAIL;
a737bd4d
NC		 6372}
6373
32c36c3c
AV		 6374static int
6375parse_sys_vldr_vstr (char **str)
6376{
6377 unsigned i;
6378 int val = FAIL;
6379 struct {
6380 const char *name;
6381 int regl;
6382 int regh;
6383 } sysregs[] = {
6384 {"FPSCR", 0x1, 0x0},
6385 {"FPSCR_nzcvqc", 0x2, 0x0},
6386 {"VPR", 0x4, 0x1},
6387 {"P0", 0x5, 0x1},
6388 {"FPCXTNS", 0x6, 0x1},
6389 {"FPCXTS", 0x7, 0x1}
6390 };
6391 char *op_end = strchr (*str, ',');
6392 size_t op_strlen = op_end - *str;
6393
6394 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6395 {
6396 if (!strncmp (*str, sysregs[i].name, op_strlen))
6397 {
6398 val = sysregs[i].regl | (sysregs[i].regh << 3);
6399 *str = op_end;
6400 break;
6401 }
6402 }
6403
6404 return val;
6405}
6406
c19d1205
ZW		 6407/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6408 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 6409
c19d1205
ZW		 6410static int
6411parse_cps_flags (char **str)
a737bd4d 6412{
c19d1205
ZW		 6413 int val = 0;
6414 int saw_a_flag = 0;
6415 char *s = *str;
a737bd4d 6416
c19d1205
ZW		 6417 for (;;)
6418 switch (*s++)
6419 {
6420 case '\0': case ',':
6421 goto done;
a737bd4d 6422
c19d1205
ZW		 6423 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6424 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6425 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 6426
c19d1205
ZW		 6427 default:
6428 inst.error = _("unrecognized CPS flag");
6429 return FAIL;
6430 }
a737bd4d 6431
c19d1205
ZW		 6432 done:
6433 if (saw_a_flag == 0)
a737bd4d 6434 {
c19d1205
ZW		 6435 inst.error = _("missing CPS flags");
6436 return FAIL;
a737bd4d 6437 }
a737bd4d 6438
c19d1205
ZW		 6439 *str = s - 1;
6440 return val;
a737bd4d
NC		 6441}
6442
c19d1205
ZW		 6443/* Parse an endian specifier ("BE" or "LE", case insensitive);
6444 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC		 6445
6446static int
c19d1205 6447parse_endian_specifier (char **str)
a737bd4d 6448{
c19d1205
ZW		 6449 int little_endian;
6450 char *s = *str;
a737bd4d 6451
c19d1205
ZW		 6452 if (strncasecmp (s, "BE", 2))
6453 little_endian = 0;
6454 else if (strncasecmp (s, "LE", 2))
6455 little_endian = 1;
6456 else
a737bd4d 6457 {
c19d1205 6458 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6459 return FAIL;
6460 }
6461
c19d1205 6462 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 6463 {
c19d1205 6464 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6465 return FAIL;
6466 }
6467
c19d1205
ZW		 6468 *str = s + 2;
6469 return little_endian;
6470}
a737bd4d 6471
c19d1205
ZW		 6472/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6473 value suitable for poking into the rotate field of an sxt or sxta
6474 instruction, or FAIL on error. */
6475
6476static int
6477parse_ror (char **str)
6478{
6479 int rot;
6480 char *s = *str;
6481
6482 if (strncasecmp (s, "ROR", 3) == 0)
6483 s += 3;
6484 else
a737bd4d 6485 {
c19d1205 6486 inst.error = _("missing rotation field after comma");
a737bd4d
NC		 6487 return FAIL;
6488 }
c19d1205
ZW		 6489
6490 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6491 return FAIL;
6492
6493 switch (rot)
a737bd4d 6494 {
c19d1205
ZW		 6495 case 0: *str = s; return 0x0;
6496 case 8: *str = s; return 0x1;
6497 case 16: *str = s; return 0x2;
6498 case 24: *str = s; return 0x3;
6499
6500 default:
6501 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC		 6502 return FAIL;
6503 }
c19d1205 6504}
a737bd4d 6505
c19d1205
ZW		 6506/* Parse a conditional code (from conds[] below). The value returned is in the
6507 range 0 .. 14, or FAIL. */
6508static int
6509parse_cond (char **str)
6510{
c462b453 6511 char *q;
c19d1205 6512 const struct asm_cond *c;
c462b453
PB		 6513 int n;
6514 /* Condition codes are always 2 characters, so matching up to
6515 3 characters is sufficient. */
6516 char cond[3];
a737bd4d 6517
c462b453
PB		 6518 q = *str;
6519 n = 0;
6520 while (ISALPHA (*q) && n < 3)
6521 {
e07e6e58 6522 cond[n] = TOLOWER (*q);
c462b453
PB		 6523 q++;
6524 n++;
6525 }
a737bd4d 6526
21d799b5 6527 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 6528 if (!c)
a737bd4d 6529 {
c19d1205 6530 inst.error = _("condition required");
a737bd4d
NC		 6531 return FAIL;
6532 }
6533
c19d1205
ZW		 6534 *str = q;
6535 return c->value;
6536}
6537
62b3e311
PB		 6538/* Parse an option for a barrier instruction. Returns the encoding for the
6539 option, or FAIL. */
6540static int
6541parse_barrier (char **str)
6542{
6543 char *p, *q;
6544 const struct asm_barrier_opt *o;
6545
6546 p = q = *str;
6547 while (ISALPHA (*q))
6548 q++;
6549
21d799b5 6550 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
477330fc 6551 q - p);
62b3e311
PB		 6552 if (!o)
6553 return FAIL;
6554
e797f7e0
MGD		 6555 if (!mark_feature_used (&o->arch))
6556 return FAIL;
6557
62b3e311
PB		 6558 *str = q;
6559 return o->value;
6560}
6561
92e90b6e
PB		 6562/* Parse the operands of a table branch instruction. Similar to a memory
6563 operand. */
6564static int
6565parse_tb (char **str)
6566{
6567 char * p = *str;
6568 int reg;
6569
6570 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB		 6571 {
6572 inst.error = _("'[' expected");
6573 return FAIL;
6574 }
92e90b6e 6575
dcbf9037 6576 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6577 {
6578 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6579 return FAIL;
6580 }
6581 inst.operands[0].reg = reg;
6582
6583 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB		 6584 {
6585 inst.error = _("',' expected");
6586 return FAIL;
6587 }
5f4273c7 6588
dcbf9037 6589 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6590 {
6591 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6592 return FAIL;
6593 }
6594 inst.operands[0].imm = reg;
6595
6596 if (skip_past_comma (&p) == SUCCESS)
6597 {
6598 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6599 return FAIL;
e2b0ab59 6600 if (inst.relocs[0].exp.X_add_number != 1)
92e90b6e
PB		 6601 {
6602 inst.error = _("invalid shift");
6603 return FAIL;
6604 }
6605 inst.operands[0].shifted = 1;
6606 }
6607
6608 if (skip_past_char (&p, ']') == FAIL)
6609 {
6610 inst.error = _("']' expected");
6611 return FAIL;
6612 }
6613 *str = p;
6614 return SUCCESS;
6615}
6616
5287ad62
JB		 6617/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6618 information on the types the operands can take and how they are encoded.
037e8744
JB		 6619 Up to four operands may be read; this function handles setting the
6620 ".present" field for each read operand itself.
5287ad62
JB		 6621 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6622 else returns FAIL. */
6623
6624static int
6625parse_neon_mov (char **str, int *which_operand)
6626{
6627 int i = *which_operand, val;
6628 enum arm_reg_type rtype;
6629 char *ptr = *str;
dcbf9037 6630 struct neon_type_el optype;
5f4273c7 6631
57785aa2
AV		 6632 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6633 {
6634 /* Cases 17 or 19. */
6635 inst.operands[i].reg = val;
6636 inst.operands[i].isvec = 1;
6637 inst.operands[i].isscalar = 2;
6638 inst.operands[i].vectype = optype;
6639 inst.operands[i++].present = 1;
6640
6641 if (skip_past_comma (&ptr) == FAIL)
6642 goto wanted_comma;
6643
6644 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6645 {
6646 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6647 inst.operands[i].reg = val;
6648 inst.operands[i].isreg = 1;
6649 inst.operands[i].present = 1;
6650 }
6651 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6652 {
6653 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6654 inst.operands[i].reg = val;
6655 inst.operands[i].isvec = 1;
6656 inst.operands[i].isscalar = 2;
6657 inst.operands[i].vectype = optype;
6658 inst.operands[i++].present = 1;
6659
6660 if (skip_past_comma (&ptr) == FAIL)
6661 goto wanted_comma;
6662
6663 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6664 goto wanted_arm;
6665
6666 inst.operands[i].reg = val;
6667 inst.operands[i].isreg = 1;
6668 inst.operands[i++].present = 1;
6669
6670 if (skip_past_comma (&ptr) == FAIL)
6671 goto wanted_comma;
6672
6673 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6674 goto wanted_arm;
6675
6676 inst.operands[i].reg = val;
6677 inst.operands[i].isreg = 1;
6678 inst.operands[i].present = 1;
6679 }
6680 else
6681 {
6682 first_error (_("expected ARM or MVE vector register"));
6683 return FAIL;
6684 }
6685 }
6686 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
5287ad62
JB		 6687 {
6688 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6689 inst.operands[i].reg = val;
6690 inst.operands[i].isscalar = 1;
dcbf9037 6691 inst.operands[i].vectype = optype;
5287ad62
JB		 6692 inst.operands[i++].present = 1;
6693
6694 if (skip_past_comma (&ptr) == FAIL)
477330fc 6695 goto wanted_comma;
5f4273c7 6696
dcbf9037 6697 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
477330fc 6698 goto wanted_arm;
5f4273c7 6699
5287ad62
JB		 6700 inst.operands[i].reg = val;
6701 inst.operands[i].isreg = 1;
6702 inst.operands[i].present = 1;
6703 }
57785aa2
AV		 6704 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6705 != FAIL)
6706 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6707 != FAIL))
5287ad62
JB		 6708 {
6709 /* Cases 0, 1, 2, 3, 5 (D only). */
6710 if (skip_past_comma (&ptr) == FAIL)
477330fc 6711 goto wanted_comma;
5f4273c7 6712
5287ad62
JB		 6713 inst.operands[i].reg = val;
6714 inst.operands[i].isreg = 1;
6715 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB		 6716 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6717 inst.operands[i].isvec = 1;
dcbf9037 6718 inst.operands[i].vectype = optype;
5287ad62
JB		 6719 inst.operands[i++].present = 1;
6720
dcbf9037 6721 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6722 {
6723 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6724 Case 13: VMOV <Sd>, <Rm> */
6725 inst.operands[i].reg = val;
6726 inst.operands[i].isreg = 1;
6727 inst.operands[i].present = 1;
6728
6729 if (rtype == REG_TYPE_NQ)
6730 {
6731 first_error (_("can't use Neon quad register here"));
6732 return FAIL;
6733 }
6734 else if (rtype != REG_TYPE_VFS)
6735 {
6736 i++;
6737 if (skip_past_comma (&ptr) == FAIL)
6738 goto wanted_comma;
6739 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6740 goto wanted_arm;
6741 inst.operands[i].reg = val;
6742 inst.operands[i].isreg = 1;
6743 inst.operands[i].present = 1;
6744 }
6745 }
c4a23bf8
SP		 6746 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6747 &optype)) != FAIL)
6748 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype,
6749 &optype)) != FAIL))
477330fc
RM		 6750 {
6751 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6752 Case 1: VMOV<c><q> <Dd>, <Dm>
6753 Case 8: VMOV.F32 <Sd>, <Sm>
6754 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6755
6756 inst.operands[i].reg = val;
6757 inst.operands[i].isreg = 1;
6758 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6759 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6760 inst.operands[i].isvec = 1;
6761 inst.operands[i].vectype = optype;
6762 inst.operands[i].present = 1;
6763
6764 if (skip_past_comma (&ptr) == SUCCESS)
6765 {
6766 /* Case 15. */
6767 i++;
6768
6769 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6770 goto wanted_arm;
6771
6772 inst.operands[i].reg = val;
6773 inst.operands[i].isreg = 1;
6774 inst.operands[i++].present = 1;
6775
6776 if (skip_past_comma (&ptr) == FAIL)
6777 goto wanted_comma;
6778
6779 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6780 goto wanted_arm;
6781
6782 inst.operands[i].reg = val;
6783 inst.operands[i].isreg = 1;
6784 inst.operands[i].present = 1;
6785 }
6786 }
4641781c 6787 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
477330fc
RM		 6788 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6789 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6790 Case 10: VMOV.F32 <Sd>, #<imm>
6791 Case 11: VMOV.F64 <Dd>, #<imm> */
6792 inst.operands[i].immisfloat = 1;
8335d6aa
JW		 6793 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6794 == SUCCESS)
477330fc
RM		 6795 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6796 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6797 ;
5287ad62 6798 else
477330fc
RM		 6799 {
6800 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6801 return FAIL;
6802 }
5287ad62 6803 }
dcbf9037 6804 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62 6805 {
57785aa2 6806 /* Cases 6, 7, 16, 18. */
5287ad62
JB		 6807 inst.operands[i].reg = val;
6808 inst.operands[i].isreg = 1;
6809 inst.operands[i++].present = 1;
5f4273c7 6810
5287ad62 6811 if (skip_past_comma (&ptr) == FAIL)
477330fc 6812 goto wanted_comma;
5f4273c7 6813
57785aa2
AV		 6814 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6815 {
6816 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6817 inst.operands[i].reg = val;
6818 inst.operands[i].isscalar = 2;
6819 inst.operands[i].present = 1;
6820 inst.operands[i].vectype = optype;
6821 }
6822 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
477330fc
RM		 6823 {
6824 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6825 inst.operands[i].reg = val;
6826 inst.operands[i].isscalar = 1;
6827 inst.operands[i].present = 1;
6828 inst.operands[i].vectype = optype;
6829 }
dcbf9037 6830 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc 6831 {
477330fc
RM		 6832 inst.operands[i].reg = val;
6833 inst.operands[i].isreg = 1;
6834 inst.operands[i++].present = 1;
6835
6836 if (skip_past_comma (&ptr) == FAIL)
6837 goto wanted_comma;
6838
6839 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
57785aa2 6840 != FAIL)
477330fc 6841 {
57785aa2 6842 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
477330fc 6843
477330fc
RM		 6844 inst.operands[i].reg = val;
6845 inst.operands[i].isreg = 1;
6846 inst.operands[i].isvec = 1;
57785aa2 6847 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
477330fc
RM		 6848 inst.operands[i].vectype = optype;
6849 inst.operands[i].present = 1;
57785aa2
AV		 6850
6851 if (rtype == REG_TYPE_VFS)
6852 {
6853 /* Case 14. */
6854 i++;
6855 if (skip_past_comma (&ptr) == FAIL)
6856 goto wanted_comma;
6857 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6858 &optype)) == FAIL)
6859 {
6860 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6861 return FAIL;
6862 }
6863 inst.operands[i].reg = val;
6864 inst.operands[i].isreg = 1;
6865 inst.operands[i].isvec = 1;
6866 inst.operands[i].issingle = 1;
6867 inst.operands[i].vectype = optype;
6868 inst.operands[i].present = 1;
6869 }
6870 }
6871 else
6872 {
6873 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6874 != FAIL)
6875 {
6876 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6877 inst.operands[i].reg = val;
6878 inst.operands[i].isvec = 1;
6879 inst.operands[i].isscalar = 2;
6880 inst.operands[i].vectype = optype;
6881 inst.operands[i++].present = 1;
6882
6883 if (skip_past_comma (&ptr) == FAIL)
6884 goto wanted_comma;
6885
6886 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6887 == FAIL)
6888 {
6889 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6890 return FAIL;
6891 }
6892 inst.operands[i].reg = val;
6893 inst.operands[i].isvec = 1;
6894 inst.operands[i].isscalar = 2;
6895 inst.operands[i].vectype = optype;
6896 inst.operands[i].present = 1;
6897 }
6898 else
6899 {
6900 first_error (_("VFP single, double or MVE vector register"
6901 " expected"));
6902 return FAIL;
6903 }
477330fc
RM		 6904 }
6905 }
037e8744 6906 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
477330fc
RM		 6907 != FAIL)
6908 {
6909 /* Case 13. */
6910 inst.operands[i].reg = val;
6911 inst.operands[i].isreg = 1;
6912 inst.operands[i].isvec = 1;
6913 inst.operands[i].issingle = 1;
6914 inst.operands[i].vectype = optype;
6915 inst.operands[i].present = 1;
6916 }
5287ad62
JB		 6917 }
6918 else
6919 {
dcbf9037 6920 first_error (_("parse error"));
5287ad62
JB		 6921 return FAIL;
6922 }
6923
6924 /* Successfully parsed the operands. Update args. */
6925 *which_operand = i;
6926 *str = ptr;
6927 return SUCCESS;
6928
5f4273c7 6929 wanted_comma:
dcbf9037 6930 first_error (_("expected comma"));
5287ad62 6931 return FAIL;
5f4273c7
NC		 6932
6933 wanted_arm:
dcbf9037 6934 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 6935 return FAIL;
5287ad62
JB		 6936}
6937
5be8be5d
DG		 6938/* Use this macro when the operand constraints are different
6939 for ARM and THUMB (e.g. ldrd). */
6940#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6941 ((arm_operand) | ((thumb_operand) << 16))
6942
c19d1205
ZW		 6943/* Matcher codes for parse_operands. */
6944enum operand_parse_code
6945{
6946 OP_stop, /* end of line */
6947
6948 OP_RR, /* ARM register */
6949 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 6950 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 6951 OP_RRnpcb, /* ARM register, not r15, in square brackets */
fa94de6b 6952 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
55881a11 6953 optional trailing ! */
c19d1205
ZW		 6954 OP_RRw, /* ARM register, not r15, optional trailing ! */
6955 OP_RCP, /* Coprocessor number */
6956 OP_RCN, /* Coprocessor register */
6957 OP_RF, /* FPA register */
6958 OP_RVS, /* VFP single precision register */
5287ad62
JB		 6959 OP_RVD, /* VFP double precision register (0..15) */
6960 OP_RND, /* Neon double precision register (0..31) */
5ee91343
AV		 6961 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
6962 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
6963 */
5287ad62 6964 OP_RNQ, /* Neon quad precision register */
5ee91343 6965 OP_RNQMQ, /* Neon quad or MVE vector register. */
037e8744 6966 OP_RVSD, /* VFP single or double precision register */
1b883319 6967 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
dd9634d9 6968 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
dec41383 6969 OP_RNSD, /* Neon single or double precision register */
5287ad62 6970 OP_RNDQ, /* Neon double or quad precision register */
5ee91343 6971 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
7df54120 6972 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
037e8744 6973 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 6974 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW		 6975 OP_RVC, /* VFP control register */
6976 OP_RMF, /* Maverick F register */
6977 OP_RMD, /* Maverick D register */
6978 OP_RMFX, /* Maverick FX register */
6979 OP_RMDX, /* Maverick DX register */
6980 OP_RMAX, /* Maverick AX register */
6981 OP_RMDS, /* Maverick DSPSC register */
6982 OP_RIWR, /* iWMMXt wR register */
6983 OP_RIWC, /* iWMMXt wC register */
6984 OP_RIWG, /* iWMMXt wCG register */
6985 OP_RXA, /* XScale accumulator register */
6986
5ee91343
AV		 6987 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
6988 */
6989 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
6990 GPR (no SP/SP) */
a302e574 6991 OP_RMQ, /* MVE vector register. */
1b883319 6992 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
35d1cfc2 6993 OP_RMQRR, /* MVE vector or ARM register. */
a302e574 6994
60f993ce
AV		 6995 /* New operands for Armv8.1-M Mainline. */
6996 OP_LR, /* ARM LR register */
a302e574
AV		 6997 OP_RRe, /* ARM register, only even numbered. */
6998 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
60f993ce 6999 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
e39c1607 7000 OP_RR_ZR, /* ARM register or ZR but no PC */
60f993ce 7001
c19d1205 7002 OP_REGLST, /* ARM register list */
4b5a202f 7003 OP_CLRMLST, /* CLRM register list */
c19d1205
ZW		 7004 OP_VRSLST, /* VFP single-precision register list */
7005 OP_VRDLST, /* VFP double-precision register list */
037e8744 7006 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB		 7007 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
7008 OP_NSTRLST, /* Neon element/structure list */
efd6b359 7009 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
35c228db
AV		 7010 OP_MSTRLST2, /* MVE vector list with two elements. */
7011 OP_MSTRLST4, /* MVE vector list with four elements. */
5287ad62 7012
5287ad62 7013 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 7014 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
aacf0b33 7015 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
1b883319
AV		 7016 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
7017 zero. */
5287ad62 7018 OP_RR_RNSC, /* ARM reg or Neon scalar. */
dec41383 7019 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
037e8744 7020 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
886e1c73
AV		 7021 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7022 */
a8465a06
AV		 7023 OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7024 scalar, or ARM register. */
5287ad62 7025 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
42b16635
AV		 7026 OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */
7027 OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7028 register. */
5d281bf0 7029 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
5287ad62
JB		 7030 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
7031 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 7032 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
f601a00c
AV		 7033 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7034 OP_RNDQMQ_Ibig,
5287ad62 7035 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5150f0d8
AV		 7036 OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or
7037 ARM register. */
2d447fca 7038 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
32c36c3c 7039 OP_VLDR, /* VLDR operand. */
5287ad62
JB		 7040
7041 OP_I0, /* immediate zero */
c19d1205
ZW		 7042 OP_I7, /* immediate value 0 .. 7 */
7043 OP_I15, /* 0 .. 15 */
7044 OP_I16, /* 1 .. 16 */
5287ad62 7045 OP_I16z, /* 0 .. 16 */
c19d1205
ZW		 7046 OP_I31, /* 0 .. 31 */
7047 OP_I31w, /* 0 .. 31, optional trailing ! */
7048 OP_I32, /* 1 .. 32 */
5287ad62 7049 OP_I32z, /* 0 .. 32 */
08132bdd 7050 OP_I48_I64, /* 48 or 64 */
5287ad62 7051 OP_I63, /* 0 .. 63 */
c19d1205 7052 OP_I63s, /* -64 .. 63 */
5287ad62
JB		 7053 OP_I64, /* 1 .. 64 */
7054 OP_I64z, /* 0 .. 64 */
c19d1205 7055 OP_I255, /* 0 .. 255 */
c19d1205
ZW		 7056
7057 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
7058 OP_I7b, /* 0 .. 7 */
7059 OP_I15b, /* 0 .. 15 */
7060 OP_I31b, /* 0 .. 31 */
7061
7062 OP_SH, /* shifter operand */
4962c51a 7063 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 7064 OP_ADDR, /* Memory address expression (any mode) */
35c228db 7065 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
4962c51a
MS		 7066 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
7067 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
7068 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW		 7069 OP_EXP, /* arbitrary expression */
7070 OP_EXPi, /* same, with optional immediate prefix */
7071 OP_EXPr, /* same, with optional relocation suffix */
e2b0ab59 7072 OP_EXPs, /* same, with optional non-first operand relocation suffix */
b6895b4f 7073 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c28eeff2
SN		 7074 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
7075 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
c19d1205
ZW		 7076
7077 OP_CPSF, /* CPS flags */
7078 OP_ENDI, /* Endianness specifier */
d2cd1205
JB		 7079 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7080 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
c19d1205 7081 OP_COND, /* conditional code */
92e90b6e 7082 OP_TB, /* Table branch. */
c19d1205 7083
037e8744
JB		 7084 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7085
c19d1205 7086 OP_RRnpc_I0, /* ARM register or literal 0 */
33eaf5de 7087 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
c19d1205
ZW		 7088 OP_RR_EXi, /* ARM register or expression with imm prefix */
7089 OP_RF_IF, /* FPA register or immediate */
7090 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 7091 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW		 7092
7093 /* Optional operands. */
7094 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7095 OP_oI31b, /* 0 .. 31 */
5287ad62 7096 OP_oI32b, /* 1 .. 32 */
5f1af56b 7097 OP_oI32z, /* 0 .. 32 */
c19d1205
ZW		 7098 OP_oIffffb, /* 0 .. 65535 */
7099 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7100
7101 OP_oRR, /* ARM register */
60f993ce 7102 OP_oLR, /* ARM LR register */
c19d1205 7103 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 7104 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 7105 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB		 7106 OP_oRND, /* Optional Neon double precision register */
7107 OP_oRNQ, /* Optional Neon quad precision register */
5ee91343 7108 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
5287ad62 7109 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 7110 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5ee91343
AV		 7111 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7112 register. */
c19d1205
ZW		 7113 OP_oSHll, /* LSL immediate */
7114 OP_oSHar, /* ASR immediate */
7115 OP_oSHllar, /* LSL or ASR immediate */
7116 OP_oROR, /* ROR 0/8/16/24 */
52e7f43d 7117 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
c19d1205 7118
1b883319
AV		 7119 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7120
5be8be5d
DG		 7121 /* Some pre-defined mixed (ARM/THUMB) operands. */
7122 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7123 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7124 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7125
c19d1205
ZW		 7126 OP_FIRST_OPTIONAL = OP_oI7b
7127};
a737bd4d 7128
c19d1205
ZW		 7129/* Generic instruction operand parser. This does no encoding and no
7130 semantic validation; it merely squirrels values away in the inst
7131 structure. Returns SUCCESS or FAIL depending on whether the
7132 specified grammar matched. */
7133static int
5be8be5d 7134parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 7135{
5be8be5d 7136 unsigned const int *upat = pattern;
c19d1205
ZW		 7137 char *backtrack_pos = 0;
7138 const char *backtrack_error = 0;
99aad254 7139 int i, val = 0, backtrack_index = 0;
5287ad62 7140 enum arm_reg_type rtype;
4962c51a 7141 parse_operand_result result;
5be8be5d 7142 unsigned int op_parse_code;
efd6b359 7143 bfd_boolean partial_match;
c19d1205 7144
e07e6e58
NC		 7145#define po_char_or_fail(chr) \
7146 do \
7147 { \
7148 if (skip_past_char (&str, chr) == FAIL) \
477330fc 7149 goto bad_args; \
e07e6e58
NC		 7150 } \
7151 while (0)
c19d1205 7152
e07e6e58
NC		 7153#define po_reg_or_fail(regtype) \
7154 do \
dcbf9037 7155 { \
e07e6e58 7156 val = arm_typed_reg_parse (& str, regtype, & rtype, \
477330fc 7157 & inst.operands[i].vectype); \
e07e6e58 7158 if (val == FAIL) \
477330fc
RM		 7159 { \
7160 first_error (_(reg_expected_msgs[regtype])); \
7161 goto failure; \
7162 } \
e07e6e58
NC		 7163 inst.operands[i].reg = val; \
7164 inst.operands[i].isreg = 1; \
7165 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7166 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7167 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc
RM		 7168 || rtype == REG_TYPE_VFD \
7169 || rtype == REG_TYPE_NQ); \
1b883319 7170 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
dcbf9037 7171 } \
e07e6e58
NC		 7172 while (0)
7173
7174#define po_reg_or_goto(regtype, label) \
7175 do \
7176 { \
7177 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7178 & inst.operands[i].vectype); \
7179 if (val == FAIL) \
7180 goto label; \
dcbf9037 7181 \
e07e6e58
NC		 7182 inst.operands[i].reg = val; \
7183 inst.operands[i].isreg = 1; \
7184 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7185 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7186 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc 7187 || rtype == REG_TYPE_VFD \
e07e6e58 7188 || rtype == REG_TYPE_NQ); \
1b883319 7189 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
e07e6e58
NC		 7190 } \
7191 while (0)
7192
7193#define po_imm_or_fail(min, max, popt) \
7194 do \
7195 { \
7196 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7197 goto failure; \
7198 inst.operands[i].imm = val; \
7199 } \
7200 while (0)
7201
08132bdd
SP		 7202#define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7203 do \
7204 { \
7205 expressionS exp; \
7206 my_get_expression (&exp, &str, popt); \
7207 if (exp.X_op != O_constant) \
7208 { \
7209 inst.error = _("constant expression required"); \
7210 goto failure; \
7211 } \
7212 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7213 { \
7214 inst.error = _("immediate value 48 or 64 expected"); \
7215 goto failure; \
7216 } \
7217 inst.operands[i].imm = exp.X_add_number; \
7218 } \
7219 while (0)
7220
57785aa2 7221#define po_scalar_or_goto(elsz, label, reg_type) \
e07e6e58
NC		 7222 do \
7223 { \
57785aa2
AV		 7224 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7225 reg_type); \
e07e6e58
NC		 7226 if (val == FAIL) \
7227 goto label; \
7228 inst.operands[i].reg = val; \
7229 inst.operands[i].isscalar = 1; \
7230 } \
7231 while (0)
7232
7233#define po_misc_or_fail(expr) \
7234 do \
7235 { \
7236 if (expr) \
7237 goto failure; \
7238 } \
7239 while (0)
7240
7241#define po_misc_or_fail_no_backtrack(expr) \
7242 do \
7243 { \
7244 result = expr; \
7245 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7246 backtrack_pos = 0; \
7247 if (result != PARSE_OPERAND_SUCCESS) \
7248 goto failure; \
7249 } \
7250 while (0)
4962c51a 7251
52e7f43d
RE		 7252#define po_barrier_or_imm(str) \
7253 do \
7254 { \
7255 val = parse_barrier (&str); \
ccb84d65
JB		 7256 if (val == FAIL && ! ISALPHA (*str)) \
7257 goto immediate; \
7258 if (val == FAIL \
7259 /* ISB can only take SY as an option. */ \
7260 || ((inst.instruction & 0xf0) == 0x60 \
7261 && val != 0xf)) \
52e7f43d 7262 { \
ccb84d65
JB		 7263 inst.error = _("invalid barrier type"); \
7264 backtrack_pos = 0; \
7265 goto failure; \
52e7f43d
RE		 7266 } \
7267 } \
7268 while (0)
7269
c19d1205
ZW		 7270 skip_whitespace (str);
7271
7272 for (i = 0; upat[i] != OP_stop; i++)
7273 {
5be8be5d
DG		 7274 op_parse_code = upat[i];
7275 if (op_parse_code >= 1<<16)
7276 op_parse_code = thumb ? (op_parse_code >> 16)
7277 : (op_parse_code & ((1<<16)-1));
7278
7279 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW		 7280 {
7281 /* Remember where we are in case we need to backtrack. */
c19d1205
ZW		 7282 backtrack_pos = str;
7283 backtrack_error = inst.error;
7284 backtrack_index = i;
7285 }
7286
b6702015 7287 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW		 7288 po_char_or_fail (',');
7289
5be8be5d 7290 switch (op_parse_code)
c19d1205
ZW		 7291 {
7292 /* Registers */
7293 case OP_oRRnpc:
5be8be5d 7294 case OP_oRRnpcsp:
c19d1205 7295 case OP_RRnpc:
5be8be5d 7296 case OP_RRnpcsp:
c19d1205 7297 case OP_oRR:
a302e574
AV		 7298 case OP_RRe:
7299 case OP_RRo:
60f993ce
AV		 7300 case OP_LR:
7301 case OP_oLR:
c19d1205
ZW		 7302 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7303 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7304 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7305 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7306 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7307 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
477330fc 7308 case OP_oRND:
5ee91343
AV		 7309 case OP_RNDMQR:
7310 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7311 break;
7312 try_rndmq:
7313 case OP_RNDMQ:
7314 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7315 break;
7316 try_rnd:
5287ad62 7317 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB		 7318 case OP_RVC:
7319 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7320 break;
7321 /* Also accept generic coprocessor regs for unknown registers. */
7322 coproc_reg:
ba6cd17f
SD		 7323 po_reg_or_goto (REG_TYPE_CN, vpr_po);
7324 break;
7325 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7326 existing register with a value of 0, this seems like the
7327 best way to parse P0. */
7328 vpr_po:
7329 if (strncasecmp (str, "P0", 2) == 0)
7330 {
7331 str += 2;
7332 inst.operands[i].isreg = 1;
7333 inst.operands[i].reg = 13;
7334 }
7335 else
7336 goto failure;
cd2cf30b 7337 break;
c19d1205
ZW		 7338 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7339 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7340 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7341 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7342 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7343 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7344 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7345 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7346 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7347 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
477330fc 7348 case OP_oRNQ:
5ee91343
AV		 7349 case OP_RNQMQ:
7350 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7351 break;
7352 try_nq:
5287ad62 7353 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
dec41383 7354 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7df54120
AV		 7355 case OP_RNDQMQR:
7356 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7357 break;
7358 try_rndqmq:
5ee91343
AV		 7359 case OP_oRNDQMQ:
7360 case OP_RNDQMQ:
7361 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7362 break;
7363 try_rndq:
477330fc 7364 case OP_oRNDQ:
5287ad62 7365 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
dd9634d9
AV		 7366 case OP_RVSDMQ:
7367 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7368 break;
7369 try_rvsd:
477330fc 7370 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
1b883319
AV		 7371 case OP_RVSD_COND:
7372 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7373 break;
477330fc
RM		 7374 case OP_oRNSDQ:
7375 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5ee91343
AV		 7376 case OP_RNSDQMQR:
7377 po_reg_or_goto (REG_TYPE_RN, try_mq);
7378 break;
7379 try_mq:
7380 case OP_oRNSDQMQ:
7381 case OP_RNSDQMQ:
7382 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7383 break;
7384 try_nsdq2:
7385 po_reg_or_fail (REG_TYPE_NSDQ);
7386 inst.error = 0;
7387 break;
35d1cfc2
AV		 7388 case OP_RMQRR:
7389 po_reg_or_goto (REG_TYPE_RN, try_rmq);
7390 break;
7391 try_rmq:
a302e574
AV		 7392 case OP_RMQ:
7393 po_reg_or_fail (REG_TYPE_MQ);
7394 break;
477330fc
RM		 7395 /* Neon scalar. Using an element size of 8 means that some invalid
7396 scalars are accepted here, so deal with those in later code. */
57785aa2 7397 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
477330fc
RM		 7398
7399 case OP_RNDQ_I0:
7400 {
7401 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7402 break;
7403 try_imm0:
7404 po_imm_or_fail (0, 0, TRUE);
7405 }
7406 break;
7407
7408 case OP_RVSD_I0:
7409 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7410 break;
7411
1b883319
AV		 7412 case OP_RSVDMQ_FI0:
7413 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7414 break;
7415 try_rsvd_fi0:
aacf0b33
KT		 7416 case OP_RSVD_FI0:
7417 {
7418 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7419 break;
7420 try_ifimm0:
7421 if (parse_ifimm_zero (&str))
7422 inst.operands[i].imm = 0;
7423 else
7424 {
7425 inst.error
7426 = _("only floating point zero is allowed as immediate value");
7427 goto failure;
7428 }
7429 }
7430 break;
7431
477330fc
RM		 7432 case OP_RR_RNSC:
7433 {
57785aa2 7434 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
477330fc
RM		 7435 break;
7436 try_rr:
7437 po_reg_or_fail (REG_TYPE_RN);
7438 }
7439 break;
7440
a8465a06
AV		 7441 case OP_RNSDQ_RNSC_MQ_RR:
7442 po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7443 break;
7444 try_rnsdq_rnsc_mq:
886e1c73
AV		 7445 case OP_RNSDQ_RNSC_MQ:
7446 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7447 break;
7448 try_rnsdq_rnsc:
477330fc
RM		 7449 case OP_RNSDQ_RNSC:
7450 {
57785aa2
AV		 7451 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7452 inst.error = 0;
477330fc
RM		 7453 break;
7454 try_nsdq:
7455 po_reg_or_fail (REG_TYPE_NSDQ);
57785aa2 7456 inst.error = 0;
477330fc
RM		 7457 }
7458 break;
7459
dec41383
JW		 7460 case OP_RNSD_RNSC:
7461 {
57785aa2 7462 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
dec41383
JW		 7463 break;
7464 try_s_scalar:
57785aa2 7465 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
dec41383
JW		 7466 break;
7467 try_nsd:
7468 po_reg_or_fail (REG_TYPE_NSD);
7469 }
7470 break;
7471
42b16635
AV		 7472 case OP_RNDQMQ_RNSC_RR:
7473 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
7474 break;
7475 try_rndq_rnsc_rr:
7476 case OP_RNDQ_RNSC_RR:
7477 po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
7478 break;
5d281bf0
AV		 7479 case OP_RNDQMQ_RNSC:
7480 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7481 break;
7482 try_rndq_rnsc:
477330fc
RM		 7483 case OP_RNDQ_RNSC:
7484 {
57785aa2 7485 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
477330fc
RM		 7486 break;
7487 try_ndq:
7488 po_reg_or_fail (REG_TYPE_NDQ);
7489 }
7490 break;
7491
7492 case OP_RND_RNSC:
7493 {
57785aa2 7494 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
477330fc
RM		 7495 break;
7496 try_vfd:
7497 po_reg_or_fail (REG_TYPE_VFD);
7498 }
7499 break;
7500
7501 case OP_VMOV:
7502 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7503 not careful then bad things might happen. */
7504 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7505 break;
7506
f601a00c
AV		 7507 case OP_RNDQMQ_Ibig:
7508 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7509 break;
7510 try_rndq_ibig:
477330fc
RM		 7511 case OP_RNDQ_Ibig:
7512 {
7513 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7514 break;
7515 try_immbig:
7516 /* There's a possibility of getting a 64-bit immediate here, so
7517 we need special handling. */
8335d6aa
JW		 7518 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7519 == FAIL)
477330fc
RM		 7520 {
7521 inst.error = _("immediate value is out of range");
7522 goto failure;
7523 }
7524 }
7525 break;
7526
5150f0d8
AV		 7527 case OP_RNDQMQ_I63b_RR:
7528 po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr);
7529 break;
7530 try_rndq_i63b_rr:
7531 po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b);
7532 break;
7533 try_rndq_i63b:
477330fc
RM		 7534 case OP_RNDQ_I63b:
7535 {
7536 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7537 break;
7538 try_shimm:
7539 po_imm_or_fail (0, 63, TRUE);
7540 }
7541 break;
c19d1205
ZW		 7542
7543 case OP_RRnpcb:
7544 po_char_or_fail ('[');
7545 po_reg_or_fail (REG_TYPE_RN);
7546 po_char_or_fail (']');
7547 break;
a737bd4d 7548
55881a11 7549 case OP_RRnpctw:
c19d1205 7550 case OP_RRw:
b6702015 7551 case OP_oRRw:
c19d1205
ZW		 7552 po_reg_or_fail (REG_TYPE_RN);
7553 if (skip_past_char (&str, '!') == SUCCESS)
7554 inst.operands[i].writeback = 1;
7555 break;
7556
7557 /* Immediates */
7558 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7559 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7560 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
477330fc 7561 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW		 7562 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7563 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
477330fc 7564 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
08132bdd 7565 case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, FALSE); break;
c19d1205 7566 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
477330fc
RM		 7567 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7568 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7569 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 7570 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW		 7571
7572 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7573 case OP_oI7b:
7574 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7575 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7576 case OP_oI31b:
7577 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
477330fc
RM		 7578 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7579 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
c19d1205
ZW		 7580 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7581
7582 /* Immediate variants */
7583 case OP_oI255c:
7584 po_char_or_fail ('{');
7585 po_imm_or_fail (0, 255, TRUE);
7586 po_char_or_fail ('}');
7587 break;
7588
7589 case OP_I31w:
7590 /* The expression parser chokes on a trailing !, so we have
7591 to find it first and zap it. */
7592 {
7593 char *s = str;
7594 while (*s && *s != ',')
7595 s++;
7596 if (s[-1] == '!')
7597 {
7598 s[-1] = '\0';
7599 inst.operands[i].writeback = 1;
7600 }
7601 po_imm_or_fail (0, 31, TRUE);
7602 if (str == s - 1)
7603 str = s;
7604 }
7605 break;
7606
7607 /* Expressions */
7608 case OP_EXPi: EXPi:
e2b0ab59 7609 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW		 7610 GE_OPT_PREFIX));
7611 break;
7612
7613 case OP_EXP:
e2b0ab59 7614 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW		 7615 GE_NO_PREFIX));
7616 break;
7617
7618 case OP_EXPr: EXPr:
e2b0ab59 7619 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205 7620 GE_NO_PREFIX));
e2b0ab59 7621 if (inst.relocs[0].exp.X_op == O_symbol)
a737bd4d 7622 {
c19d1205
ZW		 7623 val = parse_reloc (&str);
7624 if (val == -1)
7625 {
7626 inst.error = _("unrecognized relocation suffix");
7627 goto failure;
7628 }
7629 else if (val != BFD_RELOC_UNUSED)
7630 {
7631 inst.operands[i].imm = val;
7632 inst.operands[i].hasreloc = 1;
7633 }
a737bd4d 7634 }
c19d1205 7635 break;
a737bd4d 7636
e2b0ab59
AV		 7637 case OP_EXPs:
7638 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7639 GE_NO_PREFIX));
7640 if (inst.relocs[i].exp.X_op == O_symbol)
7641 {
7642 inst.operands[i].hasreloc = 1;
7643 }
7644 else if (inst.relocs[i].exp.X_op == O_constant)
7645 {
7646 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7647 inst.operands[i].hasreloc = 0;
7648 }
7649 break;
7650
b6895b4f
PB		 7651 /* Operand for MOVW or MOVT. */
7652 case OP_HALF:
7653 po_misc_or_fail (parse_half (&str));
7654 break;
7655
e07e6e58 7656 /* Register or expression. */
c19d1205
ZW		 7657 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7658 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 7659
e07e6e58 7660 /* Register or immediate. */
c19d1205
ZW		 7661 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7662 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 7663
23d00a41
SD		 7664 case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break;
7665 I32: po_imm_or_fail (1, 32, FALSE); break;
7666
c19d1205
ZW		 7667 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7668 IF:
7669 if (!is_immediate_prefix (*str))
7670 goto bad_args;
7671 str++;
7672 val = parse_fpa_immediate (&str);
7673 if (val == FAIL)
7674 goto failure;
7675 /* FPA immediates are encoded as registers 8-15.
7676 parse_fpa_immediate has already applied the offset. */
7677 inst.operands[i].reg = val;
7678 inst.operands[i].isreg = 1;
7679 break;
09d92015 7680
2d447fca
JM		 7681 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7682 I32z: po_imm_or_fail (0, 32, FALSE); break;
7683
e07e6e58 7684 /* Two kinds of register. */
c19d1205
ZW		 7685 case OP_RIWR_RIWC:
7686 {
7687 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM		 7688 if (!rege
7689 || (rege->type != REG_TYPE_MMXWR
7690 && rege->type != REG_TYPE_MMXWC
7691 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW		 7692 {
7693 inst.error = _("iWMMXt data or control register expected");
7694 goto failure;
7695 }
7696 inst.operands[i].reg = rege->number;
7697 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7698 }
7699 break;
09d92015 7700
41adaa5c
JM		 7701 case OP_RIWC_RIWG:
7702 {
7703 struct reg_entry *rege = arm_reg_parse_multi (&str);
7704 if (!rege
7705 || (rege->type != REG_TYPE_MMXWC
7706 && rege->type != REG_TYPE_MMXWCG))
7707 {
7708 inst.error = _("iWMMXt control register expected");
7709 goto failure;
7710 }
7711 inst.operands[i].reg = rege->number;
7712 inst.operands[i].isreg = 1;
7713 }
7714 break;
7715
c19d1205
ZW		 7716 /* Misc */
7717 case OP_CPSF: val = parse_cps_flags (&str); break;
7718 case OP_ENDI: val = parse_endian_specifier (&str); break;
7719 case OP_oROR: val = parse_ror (&str); break;
1b883319 7720 try_cond:
c19d1205 7721 case OP_COND: val = parse_cond (&str); break;
52e7f43d
RE		 7722 case OP_oBARRIER_I15:
7723 po_barrier_or_imm (str); break;
7724 immediate:
7725 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
477330fc 7726 goto failure;
52e7f43d 7727 break;
c19d1205 7728
fa94de6b 7729 case OP_wPSR:
d2cd1205 7730 case OP_rPSR:
90ec0d68
MGD		 7731 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7732 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7733 {
7734 inst.error = _("Banked registers are not available with this "
7735 "architecture.");
7736 goto failure;
7737 }
7738 break;
d2cd1205
JB		 7739 try_psr:
7740 val = parse_psr (&str, op_parse_code == OP_wPSR);
7741 break;
037e8744 7742
32c36c3c
AV		 7743 case OP_VLDR:
7744 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7745 break;
7746 try_sysreg:
7747 val = parse_sys_vldr_vstr (&str);
7748 break;
7749
477330fc
RM		 7750 case OP_APSR_RR:
7751 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7752 break;
7753 try_apsr:
7754 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7755 instruction). */
7756 if (strncasecmp (str, "APSR_", 5) == 0)
7757 {
7758 unsigned found = 0;
7759 str += 5;
7760 while (found < 15)
7761 switch (*str++)
7762 {
7763 case 'c': found = (found & 1) ? 16 : found | 1; break;
7764 case 'n': found = (found & 2) ? 16 : found | 2; break;
7765 case 'z': found = (found & 4) ? 16 : found | 4; break;
7766 case 'v': found = (found & 8) ? 16 : found | 8; break;
7767 default: found = 16;
7768 }
7769 if (found != 15)
7770 goto failure;
7771 inst.operands[i].isvec = 1;
f7c21dc7
NC		 7772 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7773 inst.operands[i].reg = REG_PC;
477330fc
RM		 7774 }
7775 else
7776 goto failure;
7777 break;
037e8744 7778
92e90b6e
PB		 7779 case OP_TB:
7780 po_misc_or_fail (parse_tb (&str));
7781 break;
7782
e07e6e58 7783 /* Register lists. */
c19d1205 7784 case OP_REGLST:
4b5a202f 7785 val = parse_reg_list (&str, REGLIST_RN);
c19d1205
ZW		 7786 if (*str == '^')
7787 {
5e0d7f77 7788 inst.operands[i].writeback = 1;
c19d1205
ZW		 7789 str++;
7790 }
7791 break;
09d92015 7792
4b5a202f
AV		 7793 case OP_CLRMLST:
7794 val = parse_reg_list (&str, REGLIST_CLRM);
7795 break;
7796
c19d1205 7797 case OP_VRSLST:
efd6b359
AV		 7798 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7799 &partial_match);
c19d1205 7800 break;
09d92015 7801
c19d1205 7802 case OP_VRDLST:
efd6b359
AV		 7803 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7804 &partial_match);
c19d1205 7805 break;
a737bd4d 7806
477330fc
RM		 7807 case OP_VRSDLST:
7808 /* Allow Q registers too. */
7809 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7810 REGLIST_NEON_D, &partial_match);
477330fc
RM		 7811 if (val == FAIL)
7812 {
7813 inst.error = NULL;
7814 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359
AV		 7815 REGLIST_VFP_S, &partial_match);
7816 inst.operands[i].issingle = 1;
7817 }
7818 break;
7819
7820 case OP_VRSDVLST:
7821 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7822 REGLIST_VFP_D_VPR, &partial_match);
7823 if (val == FAIL && !partial_match)
7824 {
7825 inst.error = NULL;
7826 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7827 REGLIST_VFP_S_VPR, &partial_match);
477330fc
RM		 7828 inst.operands[i].issingle = 1;
7829 }
7830 break;
7831
7832 case OP_NRDLST:
7833 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7834 REGLIST_NEON_D, &partial_match);
477330fc 7835 break;
5287ad62 7836
35c228db
AV		 7837 case OP_MSTRLST4:
7838 case OP_MSTRLST2:
7839 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7840 1, &inst.operands[i].vectype);
7841 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7842 goto failure;
7843 break;
5287ad62 7844 case OP_NSTRLST:
477330fc 7845 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
35c228db 7846 0, &inst.operands[i].vectype);
477330fc 7847 break;
5287ad62 7848
c19d1205 7849 /* Addressing modes */
35c228db
AV		 7850 case OP_ADDRMVE:
7851 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7852 break;
7853
c19d1205
ZW		 7854 case OP_ADDR:
7855 po_misc_or_fail (parse_address (&str, i));
7856 break;
09d92015 7857
4962c51a
MS		 7858 case OP_ADDRGLDR:
7859 po_misc_or_fail_no_backtrack (
477330fc 7860 parse_address_group_reloc (&str, i, GROUP_LDR));
4962c51a
MS		 7861 break;
7862
7863 case OP_ADDRGLDRS:
7864 po_misc_or_fail_no_backtrack (
477330fc 7865 parse_address_group_reloc (&str, i, GROUP_LDRS));
4962c51a
MS		 7866 break;
7867
7868 case OP_ADDRGLDC:
7869 po_misc_or_fail_no_backtrack (
477330fc 7870 parse_address_group_reloc (&str, i, GROUP_LDC));
4962c51a
MS		 7871 break;
7872
c19d1205
ZW		 7873 case OP_SH:
7874 po_misc_or_fail (parse_shifter_operand (&str, i));
7875 break;
09d92015 7876
4962c51a
MS		 7877 case OP_SHG:
7878 po_misc_or_fail_no_backtrack (
477330fc 7879 parse_shifter_operand_group_reloc (&str, i));
4962c51a
MS		 7880 break;
7881
c19d1205
ZW		 7882 case OP_oSHll:
7883 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7884 break;
09d92015 7885
c19d1205
ZW		 7886 case OP_oSHar:
7887 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7888 break;
09d92015 7889
c19d1205
ZW		 7890 case OP_oSHllar:
7891 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7892 break;
09d92015 7893
1b883319
AV		 7894 case OP_RMQRZ:
7895 case OP_oRMQRZ:
7896 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
7897 break;
e39c1607
SD		 7898
7899 case OP_RR_ZR:
1b883319
AV		 7900 try_rr_zr:
7901 po_reg_or_goto (REG_TYPE_RN, ZR);
7902 break;
7903 ZR:
7904 po_reg_or_fail (REG_TYPE_ZR);
7905 break;
7906
c19d1205 7907 default:
5be8be5d 7908 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 7909 }
09d92015 7910
c19d1205
ZW		 7911 /* Various value-based sanity checks and shared operations. We
7912 do not signal immediate failures for the register constraints;
7913 this allows a syntax error to take precedence. */
5be8be5d 7914 switch (op_parse_code)
c19d1205
ZW		 7915 {
7916 case OP_oRRnpc:
7917 case OP_RRnpc:
7918 case OP_RRnpcb:
7919 case OP_RRw:
b6702015 7920 case OP_oRRw:
c19d1205
ZW		 7921 case OP_RRnpc_I0:
7922 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7923 inst.error = BAD_PC;
7924 break;
09d92015 7925
5be8be5d
DG		 7926 case OP_oRRnpcsp:
7927 case OP_RRnpcsp:
23d00a41 7928 case OP_RRnpcsp_I32:
5be8be5d
DG		 7929 if (inst.operands[i].isreg)
7930 {
7931 if (inst.operands[i].reg == REG_PC)
7932 inst.error = BAD_PC;
5c8ed6a4
JW		 7933 else if (inst.operands[i].reg == REG_SP
7934 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7935 relaxed since ARMv8-A. */
7936 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
7937 {
7938 gas_assert (thumb);
7939 inst.error = BAD_SP;
7940 }
5be8be5d
DG		 7941 }
7942 break;
7943
55881a11 7944 case OP_RRnpctw:
fa94de6b
RM		 7945 if (inst.operands[i].isreg
7946 && inst.operands[i].reg == REG_PC
55881a11
MGD		 7947 && (inst.operands[i].writeback || thumb))
7948 inst.error = BAD_PC;
7949 break;
7950
1b883319 7951 case OP_RVSD_COND:
32c36c3c
AV		 7952 case OP_VLDR:
7953 if (inst.operands[i].isreg)
7954 break;
7955 /* fall through. */
1b883319 7956
c19d1205
ZW		 7957 case OP_CPSF:
7958 case OP_ENDI:
7959 case OP_oROR:
d2cd1205
JB		 7960 case OP_wPSR:
7961 case OP_rPSR:
c19d1205 7962 case OP_COND:
52e7f43d 7963 case OP_oBARRIER_I15:
c19d1205 7964 case OP_REGLST:
4b5a202f 7965 case OP_CLRMLST:
c19d1205
ZW		 7966 case OP_VRSLST:
7967 case OP_VRDLST:
477330fc 7968 case OP_VRSDLST:
efd6b359 7969 case OP_VRSDVLST:
477330fc
RM		 7970 case OP_NRDLST:
7971 case OP_NSTRLST:
35c228db
AV		 7972 case OP_MSTRLST2:
7973 case OP_MSTRLST4:
c19d1205
ZW		 7974 if (val == FAIL)
7975 goto failure;
7976 inst.operands[i].imm = val;
7977 break;
a737bd4d 7978
60f993ce
AV		 7979 case OP_LR:
7980 case OP_oLR:
7981 if (inst.operands[i].reg != REG_LR)
7982 inst.error = _("operand must be LR register");
7983 break;
7984
1b883319
AV		 7985 case OP_RMQRZ:
7986 case OP_oRMQRZ:
e39c1607 7987 case OP_RR_ZR:
1b883319
AV		 7988 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
7989 inst.error = BAD_PC;
7990 break;
7991
a302e574
AV		 7992 case OP_RRe:
7993 if (inst.operands[i].isreg
7994 && (inst.operands[i].reg & 0x00000001) != 0)
7995 inst.error = BAD_ODD;
7996 break;
7997
7998 case OP_RRo:
7999 if (inst.operands[i].isreg)
8000 {
8001 if ((inst.operands[i].reg & 0x00000001) != 1)
8002 inst.error = BAD_EVEN;
8003 else if (inst.operands[i].reg == REG_SP)
8004 as_tsktsk (MVE_BAD_SP);
8005 else if (inst.operands[i].reg == REG_PC)
8006 inst.error = BAD_PC;
8007 }
8008 break;
8009
c19d1205
ZW		 8010 default:
8011 break;
8012 }
09d92015 8013
c19d1205
ZW		 8014 /* If we get here, this operand was successfully parsed. */
8015 inst.operands[i].present = 1;
8016 continue;
09d92015 8017
c19d1205 8018 bad_args:
09d92015 8019 inst.error = BAD_ARGS;
c19d1205
ZW		 8020
8021 failure:
8022 if (!backtrack_pos)
d252fdde
PB		 8023 {
8024 /* The parse routine should already have set inst.error, but set a
5f4273c7 8025 default here just in case. */
d252fdde 8026 if (!inst.error)
5ee91343 8027 inst.error = BAD_SYNTAX;
d252fdde
PB		 8028 return FAIL;
8029 }
c19d1205
ZW		 8030
8031 /* Do not backtrack over a trailing optional argument that
8032 absorbed some text. We will only fail again, with the
8033 'garbage following instruction' error message, which is
8034 probably less helpful than the current one. */
8035 if (backtrack_index == i && backtrack_pos != str
8036 && upat[i+1] == OP_stop)
d252fdde
PB		 8037 {
8038 if (!inst.error)
5ee91343 8039 inst.error = BAD_SYNTAX;
d252fdde
PB		 8040 return FAIL;
8041 }
c19d1205
ZW		 8042
8043 /* Try again, skipping the optional argument at backtrack_pos. */
8044 str = backtrack_pos;
8045 inst.error = backtrack_error;
8046 inst.operands[backtrack_index].present = 0;
8047 i = backtrack_index;
8048 backtrack_pos = 0;
09d92015 8049 }
09d92015 8050
c19d1205
ZW		 8051 /* Check that we have parsed all the arguments. */
8052 if (*str != '\0' && !inst.error)
8053 inst.error = _("garbage following instruction");
09d92015 8054
c19d1205 8055 return inst.error ? FAIL : SUCCESS;
09d92015
MM		 8056}
8057
c19d1205
ZW		 8058#undef po_char_or_fail
8059#undef po_reg_or_fail
8060#undef po_reg_or_goto
8061#undef po_imm_or_fail
5287ad62 8062#undef po_scalar_or_fail
52e7f43d 8063#undef po_barrier_or_imm
e07e6e58 8064
c19d1205 8065/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC		 8066#define constraint(expr, err) \
8067 do \
c19d1205 8068 { \
e07e6e58
NC		 8069 if (expr) \
8070 { \
8071 inst.error = err; \
8072 return; \
8073 } \
c19d1205 8074 } \
e07e6e58 8075 while (0)
c19d1205 8076
fdfde340
JM		 8077/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8078 instructions are unpredictable if these registers are used. This
5c8ed6a4
JW		 8079 is the BadReg predicate in ARM's Thumb-2 documentation.
8080
8081 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8082 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8083#define reject_bad_reg(reg) \
8084 do \
8085 if (reg == REG_PC) \
8086 { \
8087 inst.error = BAD_PC; \
8088 return; \
8089 } \
8090 else if (reg == REG_SP \
8091 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8092 { \
8093 inst.error = BAD_SP; \
8094 return; \
8095 } \
fdfde340
JM		 8096 while (0)
8097
94206790
MM		 8098/* If REG is R13 (the stack pointer), warn that its use is
8099 deprecated. */
8100#define warn_deprecated_sp(reg) \
8101 do \
8102 if (warn_on_deprecated && reg == REG_SP) \
5c3696f8 8103 as_tsktsk (_("use of r13 is deprecated")); \
94206790
MM		 8104 while (0)
8105
c19d1205
ZW		 8106/* Functions for operand encoding. ARM, then Thumb. */
8107
d840c081 8108#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
c19d1205 8109
9db2f6b4
RL		 8110/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8111
8112 The only binary encoding difference is the Coprocessor number. Coprocessor
8113 9 is used for half-precision calculations or conversions. The format of the
2b0f3761 8114 instruction is the same as the equivalent Coprocessor 10 instruction that
9db2f6b4
RL		 8115 exists for Single-Precision operation. */
8116
8117static void
8118do_scalar_fp16_v82_encode (void)
8119{
5ee91343 8120 if (inst.cond < COND_ALWAYS)
9db2f6b4
RL		 8121 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8122 " the behaviour is UNPREDICTABLE"));
8123 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
8124 _(BAD_FP16));
8125
8126 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8127 mark_feature_used (&arm_ext_fp16);
8128}
8129
c19d1205
ZW		 8130/* If VAL can be encoded in the immediate field of an ARM instruction,
8131 return the encoded form. Otherwise, return FAIL. */
8132
8133static unsigned int
8134encode_arm_immediate (unsigned int val)
09d92015 8135{
c19d1205
ZW		 8136 unsigned int a, i;
8137
4f1d6205
L		 8138 if (val <= 0xff)
8139 return val;
8140
8141 for (i = 2; i < 32; i += 2)
c19d1205
ZW		 8142 if ((a = rotate_left (val, i)) <= 0xff)
8143 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8144
8145 return FAIL;
09d92015
MM		 8146}
8147
c19d1205
ZW		 8148/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8149 return the encoded form. Otherwise, return FAIL. */
8150static unsigned int
8151encode_thumb32_immediate (unsigned int val)
09d92015 8152{
c19d1205 8153 unsigned int a, i;
09d92015 8154
9c3c69f2 8155 if (val <= 0xff)
c19d1205 8156 return val;
a737bd4d 8157
9c3c69f2 8158 for (i = 1; i <= 24; i++)
09d92015 8159 {
9c3c69f2
PB		 8160 a = val >> i;
8161 if ((val & ~(0xff << i)) == 0)
8162 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 8163 }
a737bd4d 8164
c19d1205
ZW		 8165 a = val & 0xff;
8166 if (val == ((a << 16) | a))
8167 return 0x100 | a;
8168 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8169 return 0x300 | a;
09d92015 8170
c19d1205
ZW		 8171 a = val & 0xff00;
8172 if (val == ((a << 16) | a))
8173 return 0x200 | (a >> 8);
a737bd4d 8174
c19d1205 8175 return FAIL;
09d92015 8176}
5287ad62 8177/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM		 8178
8179static void
5287ad62
JB		 8180encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8181{
8182 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8183 && reg > 15)
8184 {
b1cc4aeb 8185 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 8186 {
8187 if (thumb_mode)
8188 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8189 fpu_vfp_ext_d32);
8190 else
8191 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8192 fpu_vfp_ext_d32);
8193 }
5287ad62 8194 else
477330fc
RM		 8195 {
8196 first_error (_("D register out of range for selected VFP version"));
8197 return;
8198 }
5287ad62
JB		 8199 }
8200
c19d1205 8201 switch (pos)
09d92015 8202 {
c19d1205
ZW		 8203 case VFP_REG_Sd:
8204 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8205 break;
8206
8207 case VFP_REG_Sn:
8208 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8209 break;
8210
8211 case VFP_REG_Sm:
8212 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8213 break;
8214
5287ad62
JB		 8215 case VFP_REG_Dd:
8216 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8217 break;
5f4273c7 8218
5287ad62
JB		 8219 case VFP_REG_Dn:
8220 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8221 break;
5f4273c7 8222
5287ad62
JB		 8223 case VFP_REG_Dm:
8224 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8225 break;
8226
c19d1205
ZW		 8227 default:
8228 abort ();
09d92015 8229 }
09d92015
MM		 8230}
8231
c19d1205 8232/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 8233 if any, is handled by md_apply_fix. */
09d92015 8234static void
c19d1205 8235encode_arm_shift (int i)
09d92015 8236{
008a97ef
RL		 8237 /* register-shifted register. */
8238 if (inst.operands[i].immisreg)
8239 {
bf355b69
MR		 8240 int op_index;
8241 for (op_index = 0; op_index <= i; ++op_index)
008a97ef 8242 {
5689c942
RL		 8243 /* Check the operand only when it's presented. In pre-UAL syntax,
8244 if the destination register is the same as the first operand, two
8245 register form of the instruction can be used. */
bf355b69
MR		 8246 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8247 && inst.operands[op_index].reg == REG_PC)
008a97ef
RL		 8248 as_warn (UNPRED_REG ("r15"));
8249 }
8250
8251 if (inst.operands[i].imm == REG_PC)
8252 as_warn (UNPRED_REG ("r15"));
8253 }
8254
c19d1205
ZW		 8255 if (inst.operands[i].shift_kind == SHIFT_RRX)
8256 inst.instruction |= SHIFT_ROR << 5;
8257 else
09d92015 8258 {
c19d1205
ZW		 8259 inst.instruction |= inst.operands[i].shift_kind << 5;
8260 if (inst.operands[i].immisreg)
8261 {
8262 inst.instruction |= SHIFT_BY_REG;
8263 inst.instruction |= inst.operands[i].imm << 8;
8264 }
8265 else
e2b0ab59 8266 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 8267 }
c19d1205 8268}
09d92015 8269
c19d1205
ZW		 8270static void
8271encode_arm_shifter_operand (int i)
8272{
8273 if (inst.operands[i].isreg)
09d92015 8274 {
c19d1205
ZW		 8275 inst.instruction |= inst.operands[i].reg;
8276 encode_arm_shift (i);
09d92015 8277 }
c19d1205 8278 else
a415b1cd
JB		 8279 {
8280 inst.instruction |= INST_IMMEDIATE;
e2b0ab59 8281 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
a415b1cd
JB		 8282 inst.instruction |= inst.operands[i].imm;
8283 }
09d92015
MM		 8284}
8285
c19d1205 8286/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 8287static void
c19d1205 8288encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 8289{
2b2f5df9
NC		 8290 /* PR 14260:
8291 Generate an error if the operand is not a register. */
8292 constraint (!inst.operands[i].isreg,
8293 _("Instruction does not support =N addresses"));
8294
c19d1205 8295 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 8296
c19d1205 8297 if (inst.operands[i].preind)
09d92015 8298 {
c19d1205
ZW		 8299 if (is_t)
8300 {
8301 inst.error = _("instruction does not accept preindexed addressing");
8302 return;
8303 }
8304 inst.instruction |= PRE_INDEX;
8305 if (inst.operands[i].writeback)
8306 inst.instruction |= WRITE_BACK;
09d92015 8307
c19d1205
ZW		 8308 }
8309 else if (inst.operands[i].postind)
8310 {
9c2799c2 8311 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 8312 if (is_t)
8313 inst.instruction |= WRITE_BACK;
8314 }
8315 else /* unindexed - only for coprocessor */
09d92015 8316 {
c19d1205 8317 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM		 8318 return;
8319 }
8320
c19d1205
ZW		 8321 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8322 && (((inst.instruction & 0x000f0000) >> 16)
8323 == ((inst.instruction & 0x0000f000) >> 12)))
8324 as_warn ((inst.instruction & LOAD_BIT)
8325 ? _("destination register same as write-back base")
8326 : _("source register same as write-back base"));
09d92015
MM		 8327}
8328
c19d1205
ZW		 8329/* inst.operands[i] was set up by parse_address. Encode it into an
8330 ARM-format mode 2 load or store instruction. If is_t is true,
8331 reject forms that cannot be used with a T instruction (i.e. not
8332 post-indexed). */
a737bd4d 8333static void
c19d1205 8334encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 8335{
5be8be5d
DG		 8336 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8337
c19d1205 8338 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8339
c19d1205 8340 if (inst.operands[i].immisreg)
09d92015 8341 {
5be8be5d
DG		 8342 constraint ((inst.operands[i].imm == REG_PC
8343 || (is_pc && inst.operands[i].writeback)),
8344 BAD_PC_ADDRESSING);
c19d1205
ZW		 8345 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8346 inst.instruction |= inst.operands[i].imm;
8347 if (!inst.operands[i].negative)
8348 inst.instruction |= INDEX_UP;
8349 if (inst.operands[i].shifted)
8350 {
8351 if (inst.operands[i].shift_kind == SHIFT_RRX)
8352 inst.instruction |= SHIFT_ROR << 5;
8353 else
8354 {
8355 inst.instruction |= inst.operands[i].shift_kind << 5;
e2b0ab59 8356 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
c19d1205
ZW		 8357 }
8358 }
09d92015 8359 }
e2b0ab59 8360 else /* immediate offset in inst.relocs[0] */
09d92015 8361 {
e2b0ab59 8362 if (is_pc && !inst.relocs[0].pc_rel)
5be8be5d
DG		 8363 {
8364 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
23a10334
JZ		 8365
8366 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8367 cannot use PC in addressing.
8368 PC cannot be used in writeback addressing, either. */
8369 constraint ((is_t || inst.operands[i].writeback),
5be8be5d 8370 BAD_PC_ADDRESSING);
23a10334 8371
dc5ec521 8372 /* Use of PC in str is deprecated for ARMv7. */
23a10334
JZ		 8373 if (warn_on_deprecated
8374 && !is_load
8375 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
5c3696f8 8376 as_tsktsk (_("use of PC in this instruction is deprecated"));
5be8be5d
DG		 8377 }
8378
e2b0ab59 8379 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS		 8380 {
8381 /* Prefer + for zero encoded value. */
8382 if (!inst.operands[i].negative)
8383 inst.instruction |= INDEX_UP;
e2b0ab59 8384 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
26d97720 8385 }
09d92015 8386 }
09d92015
MM		 8387}
8388
c19d1205
ZW		 8389/* inst.operands[i] was set up by parse_address. Encode it into an
8390 ARM-format mode 3 load or store instruction. Reject forms that
8391 cannot be used with such instructions. If is_t is true, reject
8392 forms that cannot be used with a T instruction (i.e. not
8393 post-indexed). */
8394static void
8395encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 8396{
c19d1205 8397 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 8398 {
c19d1205
ZW		 8399 inst.error = _("instruction does not accept scaled register index");
8400 return;
09d92015 8401 }
a737bd4d 8402
c19d1205 8403 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8404
c19d1205
ZW		 8405 if (inst.operands[i].immisreg)
8406 {
5be8be5d 8407 constraint ((inst.operands[i].imm == REG_PC
eb9f3f00 8408 || (is_t && inst.operands[i].reg == REG_PC)),
5be8be5d 8409 BAD_PC_ADDRESSING);
eb9f3f00
JB		 8410 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8411 BAD_PC_WRITEBACK);
c19d1205
ZW		 8412 inst.instruction |= inst.operands[i].imm;
8413 if (!inst.operands[i].negative)
8414 inst.instruction |= INDEX_UP;
8415 }
e2b0ab59 8416 else /* immediate offset in inst.relocs[0] */
c19d1205 8417 {
e2b0ab59 8418 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
5be8be5d
DG		 8419 && inst.operands[i].writeback),
8420 BAD_PC_WRITEBACK);
c19d1205 8421 inst.instruction |= HWOFFSET_IMM;
e2b0ab59 8422 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS		 8423 {
8424 /* Prefer + for zero encoded value. */
8425 if (!inst.operands[i].negative)
8426 inst.instruction |= INDEX_UP;
8427
e2b0ab59 8428 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
26d97720 8429 }
c19d1205 8430 }
a737bd4d
NC		 8431}
8432
8335d6aa
JW		 8433/* Write immediate bits [7:0] to the following locations:
8434
8435 |28/24|23 19|18 16|15 4|3 0|
8436 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8437
8438 This function is used by VMOV/VMVN/VORR/VBIC. */
8439
8440static void
8441neon_write_immbits (unsigned immbits)
8442{
8443 inst.instruction |= immbits & 0xf;
8444 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8445 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8446}
8447
8448/* Invert low-order SIZE bits of XHI:XLO. */
8449
8450static void
8451neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8452{
8453 unsigned immlo = xlo ? *xlo : 0;
8454 unsigned immhi = xhi ? *xhi : 0;
8455
8456 switch (size)
8457 {
8458 case 8:
8459 immlo = (~immlo) & 0xff;
8460 break;
8461
8462 case 16:
8463 immlo = (~immlo) & 0xffff;
8464 break;
8465
8466 case 64:
8467 immhi = (~immhi) & 0xffffffff;
8468 /* fall through. */
8469
8470 case 32:
8471 immlo = (~immlo) & 0xffffffff;
8472 break;
8473
8474 default:
8475 abort ();
8476 }
8477
8478 if (xlo)
8479 *xlo = immlo;
8480
8481 if (xhi)
8482 *xhi = immhi;
8483}
8484
8485/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8486 A, B, C, D. */
09d92015 8487
c19d1205 8488static int
8335d6aa 8489neon_bits_same_in_bytes (unsigned imm)
09d92015 8490{
8335d6aa
JW		 8491 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8492 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8493 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8494 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8495}
a737bd4d 8496
8335d6aa 8497/* For immediate of above form, return 0bABCD. */
09d92015 8498
8335d6aa
JW		 8499static unsigned
8500neon_squash_bits (unsigned imm)
8501{
8502 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8503 | ((imm & 0x01000000) >> 21);
8504}
8505
8506/* Compress quarter-float representation to 0b...000 abcdefgh. */
8507
8508static unsigned
8509neon_qfloat_bits (unsigned imm)
8510{
8511 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8512}
8513
8514/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8515 the instruction. *OP is passed as the initial value of the op field, and
8516 may be set to a different value depending on the constant (i.e.
8517 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8518 MVN). If the immediate looks like a repeated pattern then also
8519 try smaller element sizes. */
8520
8521static int
8522neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8523 unsigned *immbits, int *op, int size,
8524 enum neon_el_type type)
8525{
8526 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8527 float. */
8528 if (type == NT_float && !float_p)
8529 return FAIL;
8530
8531 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
09d92015 8532 {
8335d6aa
JW		 8533 if (size != 32 || *op == 1)
8534 return FAIL;
8535 *immbits = neon_qfloat_bits (immlo);
8536 return 0xf;
8537 }
8538
8539 if (size == 64)
8540 {
8541 if (neon_bits_same_in_bytes (immhi)
8542 && neon_bits_same_in_bytes (immlo))
c19d1205 8543 {
8335d6aa
JW		 8544 if (*op == 1)
8545 return FAIL;
8546 *immbits = (neon_squash_bits (immhi) << 4)
8547 | neon_squash_bits (immlo);
8548 *op = 1;
8549 return 0xe;
c19d1205 8550 }
a737bd4d 8551
8335d6aa
JW		 8552 if (immhi != immlo)
8553 return FAIL;
8554 }
a737bd4d 8555
8335d6aa 8556 if (size >= 32)
09d92015 8557 {
8335d6aa 8558 if (immlo == (immlo & 0x000000ff))
c19d1205 8559 {
8335d6aa
JW		 8560 *immbits = immlo;
8561 return 0x0;
c19d1205 8562 }
8335d6aa 8563 else if (immlo == (immlo & 0x0000ff00))
c19d1205 8564 {
8335d6aa
JW		 8565 *immbits = immlo >> 8;
8566 return 0x2;
c19d1205 8567 }
8335d6aa
JW		 8568 else if (immlo == (immlo & 0x00ff0000))
8569 {
8570 *immbits = immlo >> 16;
8571 return 0x4;
8572 }
8573 else if (immlo == (immlo & 0xff000000))
8574 {
8575 *immbits = immlo >> 24;
8576 return 0x6;
8577 }
8578 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8579 {
8580 *immbits = (immlo >> 8) & 0xff;
8581 return 0xc;
8582 }
8583 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8584 {
8585 *immbits = (immlo >> 16) & 0xff;
8586 return 0xd;
8587 }
8588
8589 if ((immlo & 0xffff) != (immlo >> 16))
8590 return FAIL;
8591 immlo &= 0xffff;
09d92015 8592 }
a737bd4d 8593
8335d6aa 8594 if (size >= 16)
4962c51a 8595 {
8335d6aa
JW		 8596 if (immlo == (immlo & 0x000000ff))
8597 {
8598 *immbits = immlo;
8599 return 0x8;
8600 }
8601 else if (immlo == (immlo & 0x0000ff00))
8602 {
8603 *immbits = immlo >> 8;
8604 return 0xa;
8605 }
8606
8607 if ((immlo & 0xff) != (immlo >> 8))
8608 return FAIL;
8609 immlo &= 0xff;
4962c51a
MS		 8610 }
8611
8335d6aa
JW		 8612 if (immlo == (immlo & 0x000000ff))
8613 {
8614 /* Don't allow MVN with 8-bit immediate. */
8615 if (*op == 1)
8616 return FAIL;
8617 *immbits = immlo;
8618 return 0xe;
8619 }
26d97720 8620
8335d6aa 8621 return FAIL;
c19d1205 8622}
a737bd4d 8623
5fc177c8 8624#if defined BFD_HOST_64_BIT
ba592044
AM		 8625/* Returns TRUE if double precision value V may be cast
8626 to single precision without loss of accuracy. */
8627
8628static bfd_boolean
5fc177c8 8629is_double_a_single (bfd_int64_t v)
ba592044 8630{
5fc177c8 8631 int exp = (int)((v >> 52) & 0x7FF);
8fe3f3d6 8632 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM		 8633
8634 return (exp == 0 || exp == 0x7FF
8635 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8636 && (mantissa & 0x1FFFFFFFl) == 0;
8637}
8638
3739860c 8639/* Returns a double precision value casted to single precision
ba592044
AM		 8640 (ignoring the least significant bits in exponent and mantissa). */
8641
8642static int
5fc177c8 8643double_to_single (bfd_int64_t v)
ba592044
AM		 8644{
8645 int sign = (int) ((v >> 63) & 1l);
5fc177c8 8646 int exp = (int) ((v >> 52) & 0x7FF);
8fe3f3d6 8647 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM		 8648
8649 if (exp == 0x7FF)
8650 exp = 0xFF;
8651 else
8652 {
8653 exp = exp - 1023 + 127;
8654 if (exp >= 0xFF)
8655 {
8656 /* Infinity. */
8657 exp = 0x7F;
8658 mantissa = 0;
8659 }
8660 else if (exp < 0)
8661 {
8662 /* No denormalized numbers. */
8663 exp = 0;
8664 mantissa = 0;
8665 }
8666 }
8667 mantissa >>= 29;
8668 return (sign << 31) | (exp << 23) | mantissa;
8669}
5fc177c8 8670#endif /* BFD_HOST_64_BIT */
ba592044 8671
8335d6aa
JW		 8672enum lit_type
8673{
8674 CONST_THUMB,
8675 CONST_ARM,
8676 CONST_VEC
8677};
8678
ba592044
AM		 8679static void do_vfp_nsyn_opcode (const char *);
8680
e2b0ab59 8681/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
c19d1205
ZW		 8682 Determine whether it can be performed with a move instruction; if
8683 it can, convert inst.instruction to that move instruction and
c921be7d
NC		 8684 return TRUE; if it can't, convert inst.instruction to a literal-pool
8685 load and return FALSE. If this is not a valid thing to do in the
8686 current context, set inst.error and return TRUE.
a737bd4d 8687
c19d1205
ZW		 8688 inst.operands[i] describes the destination register. */
8689
c921be7d 8690static bfd_boolean
8335d6aa 8691move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
c19d1205 8692{
53365c0d 8693 unsigned long tbit;
8335d6aa
JW		 8694 bfd_boolean thumb_p = (t == CONST_THUMB);
8695 bfd_boolean arm_p = (t == CONST_ARM);
53365c0d
PB		 8696
8697 if (thumb_p)
8698 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8699 else
8700 tbit = LOAD_BIT;
8701
8702 if ((inst.instruction & tbit) == 0)
09d92015 8703 {
c19d1205 8704 inst.error = _("invalid pseudo operation");
c921be7d 8705 return TRUE;
09d92015 8706 }
ba592044 8707
e2b0ab59
AV		 8708 if (inst.relocs[0].exp.X_op != O_constant
8709 && inst.relocs[0].exp.X_op != O_symbol
8710 && inst.relocs[0].exp.X_op != O_big)
09d92015
MM		 8711 {
8712 inst.error = _("constant expression expected");
c921be7d 8713 return TRUE;
09d92015 8714 }
ba592044 8715
e2b0ab59
AV		 8716 if (inst.relocs[0].exp.X_op == O_constant
8717 || inst.relocs[0].exp.X_op == O_big)
8335d6aa 8718 {
5fc177c8
NC		 8719#if defined BFD_HOST_64_BIT
8720 bfd_int64_t v;
8721#else
ba592044 8722 offsetT v;
5fc177c8 8723#endif
e2b0ab59 8724 if (inst.relocs[0].exp.X_op == O_big)
8335d6aa 8725 {
ba592044
AM		 8726 LITTLENUM_TYPE w[X_PRECISION];
8727 LITTLENUM_TYPE * l;
8728
e2b0ab59 8729 if (inst.relocs[0].exp.X_add_number == -1)
8335d6aa 8730 {
ba592044
AM		 8731 gen_to_words (w, X_PRECISION, E_PRECISION);
8732 l = w;
8733 /* FIXME: Should we check words w[2..5] ? */
8335d6aa 8734 }
ba592044
AM		 8735 else
8736 l = generic_bignum;
3739860c 8737
5fc177c8
NC		 8738#if defined BFD_HOST_64_BIT
8739 v =
8740 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8741 << LITTLENUM_NUMBER_OF_BITS)
8742 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8743 << LITTLENUM_NUMBER_OF_BITS)
8744 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8745 << LITTLENUM_NUMBER_OF_BITS)
8746 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8747#else
ba592044
AM		 8748 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8749 | (l[0] & LITTLENUM_MASK);
5fc177c8 8750#endif
8335d6aa 8751 }
ba592044 8752 else
e2b0ab59 8753 v = inst.relocs[0].exp.X_add_number;
ba592044
AM		 8754
8755 if (!inst.operands[i].issingle)
8335d6aa 8756 {
12569877 8757 if (thumb_p)
8335d6aa 8758 {
53445554
TP		 8759 /* LDR should not use lead in a flag-setting instruction being
8760 chosen so we do not check whether movs can be used. */
12569877 8761
53445554 8762 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
ff8646ee 8763 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
53445554
TP		 8764 && inst.operands[i].reg != 13
8765 && inst.operands[i].reg != 15)
12569877 8766 {
fc289b0a
TP		 8767 /* Check if on thumb2 it can be done with a mov.w, mvn or
8768 movw instruction. */
12569877
AM		 8769 unsigned int newimm;
8770 bfd_boolean isNegated;
8771
8772 newimm = encode_thumb32_immediate (v);
8773 if (newimm != (unsigned int) FAIL)
8774 isNegated = FALSE;
8775 else
8776 {
582cfe03 8777 newimm = encode_thumb32_immediate (~v);
12569877
AM		 8778 if (newimm != (unsigned int) FAIL)
8779 isNegated = TRUE;
8780 }
8781
fc289b0a
TP		 8782 /* The number can be loaded with a mov.w or mvn
8783 instruction. */
ff8646ee
TP		 8784 if (newimm != (unsigned int) FAIL
8785 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
12569877 8786 {
fc289b0a 8787 inst.instruction = (0xf04f0000 /* MOV.W. */
582cfe03 8788 | (inst.operands[i].reg << 8));
fc289b0a 8789 /* Change to MOVN. */
582cfe03 8790 inst.instruction |= (isNegated ? 0x200000 : 0);
12569877
AM		 8791 inst.instruction |= (newimm & 0x800) << 15;
8792 inst.instruction |= (newimm & 0x700) << 4;
8793 inst.instruction |= (newimm & 0x0ff);
8794 return TRUE;
8795 }
fc289b0a 8796 /* The number can be loaded with a movw instruction. */
ff8646ee
TP		 8797 else if ((v & ~0xFFFF) == 0
8798 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
3739860c 8799 {
582cfe03 8800 int imm = v & 0xFFFF;
12569877 8801
582cfe03 8802 inst.instruction = 0xf2400000; /* MOVW. */
12569877
AM		 8803 inst.instruction |= (inst.operands[i].reg << 8);
8804 inst.instruction |= (imm & 0xf000) << 4;
8805 inst.instruction |= (imm & 0x0800) << 15;
8806 inst.instruction |= (imm & 0x0700) << 4;
8807 inst.instruction |= (imm & 0x00ff);
8fe9a076
AV		 8808 /* In case this replacement is being done on Armv8-M
8809 Baseline we need to make sure to disable the
8810 instruction size check, as otherwise GAS will reject
8811 the use of this T32 instruction. */
8812 inst.size_req = 0;
12569877
AM		 8813 return TRUE;
8814 }
8815 }
8335d6aa 8816 }
12569877 8817 else if (arm_p)
ba592044
AM		 8818 {
8819 int value = encode_arm_immediate (v);
12569877 8820
ba592044
AM		 8821 if (value != FAIL)
8822 {
8823 /* This can be done with a mov instruction. */
8824 inst.instruction &= LITERAL_MASK;
8825 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8826 inst.instruction |= value & 0xfff;
8827 return TRUE;
8828 }
8335d6aa 8829
ba592044
AM		 8830 value = encode_arm_immediate (~ v);
8831 if (value != FAIL)
8832 {
8833 /* This can be done with a mvn instruction. */
8834 inst.instruction &= LITERAL_MASK;
8835 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8836 inst.instruction |= value & 0xfff;
8837 return TRUE;
8838 }
8839 }
934c2632 8840 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8335d6aa 8841 {
ba592044
AM		 8842 int op = 0;
8843 unsigned immbits = 0;
8844 unsigned immlo = inst.operands[1].imm;
8845 unsigned immhi = inst.operands[1].regisimm
8846 ? inst.operands[1].reg
e2b0ab59 8847 : inst.relocs[0].exp.X_unsigned
ba592044
AM		 8848 ? 0
8849 : ((bfd_int64_t)((int) immlo)) >> 32;
8850 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8851 &op, 64, NT_invtype);
8852
8853 if (cmode == FAIL)
8854 {
8855 neon_invert_size (&immlo, &immhi, 64);
8856 op = !op;
8857 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8858 &op, 64, NT_invtype);
8859 }
8860
8861 if (cmode != FAIL)
8862 {
8863 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8864 | (1 << 23)
8865 | (cmode << 8)
8866 | (op << 5)
8867 | (1 << 4);
8868
8869 /* Fill other bits in vmov encoding for both thumb and arm. */
8870 if (thumb_mode)
eff0bc54 8871 inst.instruction |= (0x7U << 29) | (0xF << 24);
ba592044 8872 else
eff0bc54 8873 inst.instruction |= (0xFU << 28) | (0x1 << 25);
ba592044
AM		 8874 neon_write_immbits (immbits);
8875 return TRUE;
8876 }
8335d6aa
JW		 8877 }
8878 }
8335d6aa 8879
ba592044
AM		 8880 if (t == CONST_VEC)
8881 {
8882 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8883 if (inst.operands[i].issingle
8884 && is_quarter_float (inst.operands[1].imm)
8885 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8335d6aa 8886 {
ba592044
AM		 8887 inst.operands[1].imm =
8888 neon_qfloat_bits (v);
8889 do_vfp_nsyn_opcode ("fconsts");
8890 return TRUE;
8335d6aa 8891 }
5fc177c8
NC		 8892
8893 /* If our host does not support a 64-bit type then we cannot perform
8894 the following optimization. This mean that there will be a
8895 discrepancy between the output produced by an assembler built for
8896 a 32-bit-only host and the output produced from a 64-bit host, but
8897 this cannot be helped. */
8898#if defined BFD_HOST_64_BIT
ba592044
AM		 8899 else if (!inst.operands[1].issingle
8900 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8335d6aa 8901 {
ba592044
AM		 8902 if (is_double_a_single (v)
8903 && is_quarter_float (double_to_single (v)))
8904 {
8905 inst.operands[1].imm =
8906 neon_qfloat_bits (double_to_single (v));
8907 do_vfp_nsyn_opcode ("fconstd");
8908 return TRUE;
8909 }
8335d6aa 8910 }
5fc177c8 8911#endif
8335d6aa
JW		 8912 }
8913 }
8914
8915 if (add_to_lit_pool ((!inst.operands[i].isvec
8916 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8917 return TRUE;
8918
8919 inst.operands[1].reg = REG_PC;
8920 inst.operands[1].isreg = 1;
8921 inst.operands[1].preind = 1;
e2b0ab59
AV		 8922 inst.relocs[0].pc_rel = 1;
8923 inst.relocs[0].type = (thumb_p
8335d6aa
JW		 8924 ? BFD_RELOC_ARM_THUMB_OFFSET
8925 : (mode_3
8926 ? BFD_RELOC_ARM_HWLITERAL
8927 : BFD_RELOC_ARM_LITERAL));
8928 return FALSE;
8929}
8930
8931/* inst.operands[i] was set up by parse_address. Encode it into an
8932 ARM-format instruction. Reject all forms which cannot be encoded
8933 into a coprocessor load/store instruction. If wb_ok is false,
8934 reject use of writeback; if unind_ok is false, reject use of
8935 unindexed addressing. If reloc_override is not 0, use it instead
8936 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8937 (in which case it is preserved). */
8938
8939static int
8940encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8941{
8942 if (!inst.operands[i].isreg)
8943 {
99b2a2dd
NC		 8944 /* PR 18256 */
8945 if (! inst.operands[0].isvec)
8946 {
8947 inst.error = _("invalid co-processor operand");
8948 return FAIL;
8949 }
8335d6aa
JW		 8950 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8951 return SUCCESS;
8952 }
8953
8954 inst.instruction |= inst.operands[i].reg << 16;
8955
8956 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8957
8958 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8959 {
8960 gas_assert (!inst.operands[i].writeback);
8961 if (!unind_ok)
8962 {
8963 inst.error = _("instruction does not support unindexed addressing");
8964 return FAIL;
8965 }
8966 inst.instruction |= inst.operands[i].imm;
8967 inst.instruction |= INDEX_UP;
8968 return SUCCESS;
8969 }
8970
8971 if (inst.operands[i].preind)
8972 inst.instruction |= PRE_INDEX;
8973
8974 if (inst.operands[i].writeback)
09d92015 8975 {
8335d6aa 8976 if (inst.operands[i].reg == REG_PC)
c19d1205 8977 {
8335d6aa
JW		 8978 inst.error = _("pc may not be used with write-back");
8979 return FAIL;
c19d1205 8980 }
8335d6aa 8981 if (!wb_ok)
c19d1205 8982 {
8335d6aa
JW		 8983 inst.error = _("instruction does not support writeback");
8984 return FAIL;
c19d1205 8985 }
8335d6aa 8986 inst.instruction |= WRITE_BACK;
09d92015
MM		 8987 }
8988
8335d6aa 8989 if (reloc_override)
e2b0ab59
AV		 8990 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
8991 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
8992 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
8993 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
c19d1205 8994 {
8335d6aa 8995 if (thumb_mode)
e2b0ab59 8996 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8335d6aa 8997 else
e2b0ab59 8998 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
c19d1205 8999 }
8335d6aa
JW		 9000
9001 /* Prefer + for zero encoded value. */
9002 if (!inst.operands[i].negative)
9003 inst.instruction |= INDEX_UP;
9004
9005 return SUCCESS;
09d92015
MM		 9006}
9007
5f4273c7 9008/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW		 9009 First some generics; their names are taken from the conventional
9010 bit positions for register arguments in ARM format instructions. */
09d92015 9011
a737bd4d 9012static void
c19d1205 9013do_noargs (void)
09d92015 9014{
c19d1205 9015}
a737bd4d 9016
c19d1205
ZW		 9017static void
9018do_rd (void)
9019{
9020 inst.instruction |= inst.operands[0].reg << 12;
9021}
a737bd4d 9022
16a1fa25
TP		 9023static void
9024do_rn (void)
9025{
9026 inst.instruction |= inst.operands[0].reg << 16;
9027}
9028
c19d1205
ZW		 9029static void
9030do_rd_rm (void)
9031{
9032 inst.instruction |= inst.operands[0].reg << 12;
9033 inst.instruction |= inst.operands[1].reg;
9034}
09d92015 9035
9eb6c0f1
MGD		 9036static void
9037do_rm_rn (void)
9038{
9039 inst.instruction |= inst.operands[0].reg;
9040 inst.instruction |= inst.operands[1].reg << 16;
9041}
9042
c19d1205
ZW		 9043static void
9044do_rd_rn (void)
9045{
9046 inst.instruction |= inst.operands[0].reg << 12;
9047 inst.instruction |= inst.operands[1].reg << 16;
9048}
a737bd4d 9049
c19d1205
ZW		 9050static void
9051do_rn_rd (void)
9052{
9053 inst.instruction |= inst.operands[0].reg << 16;
9054 inst.instruction |= inst.operands[1].reg << 12;
9055}
09d92015 9056
4ed7ed8d
TP		 9057static void
9058do_tt (void)
9059{
9060 inst.instruction |= inst.operands[0].reg << 8;
9061 inst.instruction |= inst.operands[1].reg << 16;
9062}
9063
59d09be6
MGD		 9064static bfd_boolean
9065check_obsolete (const arm_feature_set *feature, const char *msg)
9066{
9067 if (ARM_CPU_IS_ANY (cpu_variant))
9068 {
5c3696f8 9069 as_tsktsk ("%s", msg);
59d09be6
MGD		 9070 return TRUE;
9071 }
9072 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
9073 {
9074 as_bad ("%s", msg);
9075 return TRUE;
9076 }
9077
9078 return FALSE;
9079}
9080
c19d1205
ZW		 9081static void
9082do_rd_rm_rn (void)
9083{
9a64e435 9084 unsigned Rn = inst.operands[2].reg;
708587a4 9085 /* Enforce restrictions on SWP instruction. */
9a64e435 9086 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG		 9087 {
9088 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9089 _("Rn must not overlap other operands"));
9090
59d09be6
MGD		 9091 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9092 */
9093 if (!check_obsolete (&arm_ext_v8,
9094 _("swp{b} use is obsoleted for ARMv8 and later"))
9095 && warn_on_deprecated
9096 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
5c3696f8 9097 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
56adecf4 9098 }
59d09be6 9099
c19d1205
ZW		 9100 inst.instruction |= inst.operands[0].reg << 12;
9101 inst.instruction |= inst.operands[1].reg;
9a64e435 9102 inst.instruction |= Rn << 16;
c19d1205 9103}
09d92015 9104
c19d1205
ZW		 9105static void
9106do_rd_rn_rm (void)
9107{
9108 inst.instruction |= inst.operands[0].reg << 12;
9109 inst.instruction |= inst.operands[1].reg << 16;
9110 inst.instruction |= inst.operands[2].reg;
9111}
a737bd4d 9112
c19d1205
ZW		 9113static void
9114do_rm_rd_rn (void)
9115{
5be8be5d 9116 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
e2b0ab59
AV		 9117 constraint (((inst.relocs[0].exp.X_op != O_constant
9118 && inst.relocs[0].exp.X_op != O_illegal)
9119 || inst.relocs[0].exp.X_add_number != 0),
5be8be5d 9120 BAD_ADDR_MODE);
c19d1205
ZW		 9121 inst.instruction |= inst.operands[0].reg;
9122 inst.instruction |= inst.operands[1].reg << 12;
9123 inst.instruction |= inst.operands[2].reg << 16;
9124}
09d92015 9125
c19d1205
ZW		 9126static void
9127do_imm0 (void)
9128{
9129 inst.instruction |= inst.operands[0].imm;
9130}
09d92015 9131
c19d1205
ZW		 9132static void
9133do_rd_cpaddr (void)
9134{
9135 inst.instruction |= inst.operands[0].reg << 12;
9136 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 9137}
a737bd4d 9138
c19d1205
ZW		 9139/* ARM instructions, in alphabetical order by function name (except
9140 that wrapper functions appear immediately after the function they
9141 wrap). */
09d92015 9142
c19d1205
ZW		 9143/* This is a pseudo-op of the form "adr rd, label" to be converted
9144 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM		 9145
9146static void
c19d1205 9147do_adr (void)
09d92015 9148{
c19d1205 9149 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9150
c19d1205
ZW		 9151 /* Frag hacking will turn this into a sub instruction if the offset turns
9152 out to be negative. */
e2b0ab59
AV		 9153 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9154 inst.relocs[0].pc_rel = 1;
9155 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9156
fc6141f0 9157 if (support_interwork
e2b0ab59
AV		 9158 && inst.relocs[0].exp.X_op == O_symbol
9159 && inst.relocs[0].exp.X_add_symbol != NULL
9160 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9161 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9162 inst.relocs[0].exp.X_add_number |= 1;
c19d1205 9163}
b99bd4ef 9164
c19d1205
ZW		 9165/* This is a pseudo-op of the form "adrl rd, label" to be converted
9166 into a relative address of the form:
9167 add rd, pc, #low(label-.-8)"
9168 add rd, rd, #high(label-.-8)" */
b99bd4ef 9169
c19d1205
ZW		 9170static void
9171do_adrl (void)
9172{
9173 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9174
c19d1205
ZW		 9175 /* Frag hacking will turn this into a sub instruction if the offset turns
9176 out to be negative. */
e2b0ab59
AV		 9177 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9178 inst.relocs[0].pc_rel = 1;
c19d1205 9179 inst.size = INSN_SIZE * 2;
e2b0ab59 9180 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9181
fc6141f0 9182 if (support_interwork
e2b0ab59
AV		 9183 && inst.relocs[0].exp.X_op == O_symbol
9184 && inst.relocs[0].exp.X_add_symbol != NULL
9185 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9186 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9187 inst.relocs[0].exp.X_add_number |= 1;
b99bd4ef
NC		 9188}
9189
b99bd4ef 9190static void
c19d1205 9191do_arit (void)
b99bd4ef 9192{
e2b0ab59
AV		 9193 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9194 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 9195 THUMB1_RELOC_ONLY);
c19d1205
ZW		 9196 if (!inst.operands[1].present)
9197 inst.operands[1].reg = inst.operands[0].reg;
9198 inst.instruction |= inst.operands[0].reg << 12;
9199 inst.instruction |= inst.operands[1].reg << 16;
9200 encode_arm_shifter_operand (2);
9201}
b99bd4ef 9202
62b3e311
PB		 9203static void
9204do_barrier (void)
9205{
9206 if (inst.operands[0].present)
ccb84d65 9207 inst.instruction |= inst.operands[0].imm;
62b3e311
PB		 9208 else
9209 inst.instruction |= 0xf;
9210}
9211
c19d1205
ZW		 9212static void
9213do_bfc (void)
9214{
9215 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9216 constraint (msb > 32, _("bit-field extends past end of register"));
9217 /* The instruction encoding stores the LSB and MSB,
9218 not the LSB and width. */
9219 inst.instruction |= inst.operands[0].reg << 12;
9220 inst.instruction |= inst.operands[1].imm << 7;
9221 inst.instruction |= (msb - 1) << 16;
9222}
b99bd4ef 9223
c19d1205
ZW		 9224static void
9225do_bfi (void)
9226{
9227 unsigned int msb;
b99bd4ef 9228
c19d1205
ZW		 9229 /* #0 in second position is alternative syntax for bfc, which is
9230 the same instruction but with REG_PC in the Rm field. */
9231 if (!inst.operands[1].isreg)
9232 inst.operands[1].reg = REG_PC;
b99bd4ef 9233
c19d1205
ZW		 9234 msb = inst.operands[2].imm + inst.operands[3].imm;
9235 constraint (msb > 32, _("bit-field extends past end of register"));
9236 /* The instruction encoding stores the LSB and MSB,
9237 not the LSB and width. */
9238 inst.instruction |= inst.operands[0].reg << 12;
9239 inst.instruction |= inst.operands[1].reg;
9240 inst.instruction |= inst.operands[2].imm << 7;
9241 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC		 9242}
9243
b99bd4ef 9244static void
c19d1205 9245do_bfx (void)
b99bd4ef 9246{
c19d1205
ZW		 9247 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9248 _("bit-field extends past end of register"));
9249 inst.instruction |= inst.operands[0].reg << 12;
9250 inst.instruction |= inst.operands[1].reg;
9251 inst.instruction |= inst.operands[2].imm << 7;
9252 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9253}
09d92015 9254
c19d1205
ZW		 9255/* ARM V5 breakpoint instruction (argument parse)
9256 BKPT <16 bit unsigned immediate>
9257 Instruction is not conditional.
9258 The bit pattern given in insns[] has the COND_ALWAYS condition,
9259 and it is an error if the caller tried to override that. */
b99bd4ef 9260
c19d1205
ZW		 9261static void
9262do_bkpt (void)
9263{
9264 /* Top 12 of 16 bits to bits 19:8. */
9265 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 9266
c19d1205
ZW		 9267 /* Bottom 4 of 16 bits to bits 3:0. */
9268 inst.instruction |= inst.operands[0].imm & 0xf;
9269}
09d92015 9270
c19d1205
ZW		 9271static void
9272encode_branch (int default_reloc)
9273{
9274 if (inst.operands[0].hasreloc)
9275 {
0855e32b
NS		 9276 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9277 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9278 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
e2b0ab59 9279 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
0855e32b
NS		 9280 ? BFD_RELOC_ARM_PLT32
9281 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
c19d1205 9282 }
b99bd4ef 9283 else
e2b0ab59
AV		 9284 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9285 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC		 9286}
9287
b99bd4ef 9288static void
c19d1205 9289do_branch (void)
b99bd4ef 9290{
39b41c9c
PB		 9291#ifdef OBJ_ELF
9292 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9293 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9294 else
9295#endif
9296 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9297}
9298
9299static void
9300do_bl (void)
9301{
9302#ifdef OBJ_ELF
9303 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9304 {
9305 if (inst.cond == COND_ALWAYS)
9306 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9307 else
9308 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9309 }
9310 else
9311#endif
9312 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 9313}
b99bd4ef 9314
c19d1205
ZW		 9315/* ARM V5 branch-link-exchange instruction (argument parse)
9316 BLX <target_addr> ie BLX(1)
9317 BLX{<condition>} <Rm> ie BLX(2)
9318 Unfortunately, there are two different opcodes for this mnemonic.
9319 So, the insns[].value is not used, and the code here zaps values
9320 into inst.instruction.
9321 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 9322
c19d1205
ZW		 9323static void
9324do_blx (void)
9325{
9326 if (inst.operands[0].isreg)
b99bd4ef 9327 {
c19d1205
ZW		 9328 /* Arg is a register; the opcode provided by insns[] is correct.
9329 It is not illegal to do "blx pc", just useless. */
9330 if (inst.operands[0].reg == REG_PC)
9331 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 9332
c19d1205
ZW		 9333 inst.instruction |= inst.operands[0].reg;
9334 }
9335 else
b99bd4ef 9336 {
c19d1205 9337 /* Arg is an address; this instruction cannot be executed
267bf995
RR		 9338 conditionally, and the opcode must be adjusted.
9339 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9340 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 9341 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 9342 inst.instruction = 0xfa000000;
267bf995 9343 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 9344 }
c19d1205
ZW		 9345}
9346
9347static void
9348do_bx (void)
9349{
845b51d6
PB		 9350 bfd_boolean want_reloc;
9351
c19d1205
ZW		 9352 if (inst.operands[0].reg == REG_PC)
9353 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 9354
c19d1205 9355 inst.instruction |= inst.operands[0].reg;
845b51d6
PB		 9356 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9357 it is for ARMv4t or earlier. */
9358 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
4d354d8b
TP		 9359 if (!ARM_FEATURE_ZERO (selected_object_arch)
9360 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
845b51d6
PB		 9361 want_reloc = TRUE;
9362
5ad34203 9363#ifdef OBJ_ELF
845b51d6 9364 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 9365#endif
584206db 9366 want_reloc = FALSE;
845b51d6
PB		 9367
9368 if (want_reloc)
e2b0ab59 9369 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
09d92015
MM		 9370}
9371
c19d1205
ZW		 9372
9373/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC		 9374
9375static void
c19d1205 9376do_bxj (void)
a737bd4d 9377{
c19d1205
ZW		 9378 if (inst.operands[0].reg == REG_PC)
9379 as_tsktsk (_("use of r15 in bxj is not really useful"));
9380
9381 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC		 9382}
9383
c19d1205
ZW		 9384/* Co-processor data operation:
9385 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9386 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9387static void
9388do_cdp (void)
9389{
9390 inst.instruction |= inst.operands[0].reg << 8;
9391 inst.instruction |= inst.operands[1].imm << 20;
9392 inst.instruction |= inst.operands[2].reg << 12;
9393 inst.instruction |= inst.operands[3].reg << 16;
9394 inst.instruction |= inst.operands[4].reg;
9395 inst.instruction |= inst.operands[5].imm << 5;
9396}
a737bd4d
NC		 9397
9398static void
c19d1205 9399do_cmp (void)
a737bd4d 9400{
c19d1205
ZW		 9401 inst.instruction |= inst.operands[0].reg << 16;
9402 encode_arm_shifter_operand (1);
a737bd4d
NC		 9403}
9404
c19d1205
ZW		 9405/* Transfer between coprocessor and ARM registers.
9406 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9407 MRC2
9408 MCR{cond}
9409 MCR2
9410
9411 No special properties. */
09d92015 9412
dcbd0d71
MGD		 9413struct deprecated_coproc_regs_s
9414{
9415 unsigned cp;
9416 int opc1;
9417 unsigned crn;
9418 unsigned crm;
9419 int opc2;
9420 arm_feature_set deprecated;
9421 arm_feature_set obsoleted;
9422 const char *dep_msg;
9423 const char *obs_msg;
9424};
9425
9426#define DEPR_ACCESS_V8 \
9427 N_("This coprocessor register access is deprecated in ARMv8")
9428
9429/* Table of all deprecated coprocessor registers. */
9430static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9431{
9432 {15, 0, 7, 10, 5, /* CP15DMB. */
823d2571 9433 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9434 DEPR_ACCESS_V8, NULL},
9435 {15, 0, 7, 10, 4, /* CP15DSB. */
823d2571 9436 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9437 DEPR_ACCESS_V8, NULL},
9438 {15, 0, 7, 5, 4, /* CP15ISB. */
823d2571 9439 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9440 DEPR_ACCESS_V8, NULL},
9441 {14, 6, 1, 0, 0, /* TEEHBR. */
823d2571 9442 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9443 DEPR_ACCESS_V8, NULL},
9444 {14, 6, 0, 0, 0, /* TEECR. */
823d2571 9445 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9446 DEPR_ACCESS_V8, NULL},
9447};
9448
9449#undef DEPR_ACCESS_V8
9450
9451static const size_t deprecated_coproc_reg_count =
9452 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9453
09d92015 9454static void
c19d1205 9455do_co_reg (void)
09d92015 9456{
fdfde340 9457 unsigned Rd;
dcbd0d71 9458 size_t i;
fdfde340
JM		 9459
9460 Rd = inst.operands[2].reg;
9461 if (thumb_mode)
9462 {
9463 if (inst.instruction == 0xee000010
9464 || inst.instruction == 0xfe000010)
9465 /* MCR, MCR2 */
9466 reject_bad_reg (Rd);
5c8ed6a4 9467 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
fdfde340
JM		 9468 /* MRC, MRC2 */
9469 constraint (Rd == REG_SP, BAD_SP);
9470 }
9471 else
9472 {
9473 /* MCR */
9474 if (inst.instruction == 0xe000010)
9475 constraint (Rd == REG_PC, BAD_PC);
9476 }
9477
dcbd0d71
MGD		 9478 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9479 {
9480 const struct deprecated_coproc_regs_s *r =
9481 deprecated_coproc_regs + i;
9482
9483 if (inst.operands[0].reg == r->cp
9484 && inst.operands[1].imm == r->opc1
9485 && inst.operands[3].reg == r->crn
9486 && inst.operands[4].reg == r->crm
9487 && inst.operands[5].imm == r->opc2)
9488 {
b10bf8c5 9489 if (! ARM_CPU_IS_ANY (cpu_variant)
477330fc 9490 && warn_on_deprecated
dcbd0d71 9491 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
5c3696f8 9492 as_tsktsk ("%s", r->dep_msg);
dcbd0d71
MGD		 9493 }
9494 }
fdfde340 9495
c19d1205
ZW		 9496 inst.instruction |= inst.operands[0].reg << 8;
9497 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 9498 inst.instruction |= Rd << 12;
c19d1205
ZW		 9499 inst.instruction |= inst.operands[3].reg << 16;
9500 inst.instruction |= inst.operands[4].reg;
9501 inst.instruction |= inst.operands[5].imm << 5;
9502}
09d92015 9503
c19d1205
ZW		 9504/* Transfer between coprocessor register and pair of ARM registers.
9505 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9506 MCRR2
9507 MRRC{cond}
9508 MRRC2
b99bd4ef 9509
c19d1205 9510 Two XScale instructions are special cases of these:
09d92015 9511
c19d1205
ZW		 9512 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9513 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 9514
5f4273c7 9515 Result unpredictable if Rd or Rn is R15. */
a737bd4d 9516
c19d1205
ZW		 9517static void
9518do_co_reg2c (void)
9519{
fdfde340
JM		 9520 unsigned Rd, Rn;
9521
9522 Rd = inst.operands[2].reg;
9523 Rn = inst.operands[3].reg;
9524
9525 if (thumb_mode)
9526 {
9527 reject_bad_reg (Rd);
9528 reject_bad_reg (Rn);
9529 }
9530 else
9531 {
9532 constraint (Rd == REG_PC, BAD_PC);
9533 constraint (Rn == REG_PC, BAD_PC);
9534 }
9535
873f10f0
TC		 9536 /* Only check the MRRC{2} variants. */
9537 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9538 {
9539 /* If Rd == Rn, error that the operation is
9540 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9541 constraint (Rd == Rn, BAD_OVERLAP);
9542 }
9543
c19d1205
ZW		 9544 inst.instruction |= inst.operands[0].reg << 8;
9545 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM		 9546 inst.instruction |= Rd << 12;
9547 inst.instruction |= Rn << 16;
c19d1205 9548 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC		 9549}
9550
c19d1205
ZW		 9551static void
9552do_cpsi (void)
9553{
9554 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB		 9555 if (inst.operands[1].present)
9556 {
9557 inst.instruction |= CPSI_MMOD;
9558 inst.instruction |= inst.operands[1].imm;
9559 }
c19d1205 9560}
b99bd4ef 9561
62b3e311
PB		 9562static void
9563do_dbg (void)
9564{
9565 inst.instruction |= inst.operands[0].imm;
9566}
9567
eea54501
MGD		 9568static void
9569do_div (void)
9570{
9571 unsigned Rd, Rn, Rm;
9572
9573 Rd = inst.operands[0].reg;
9574 Rn = (inst.operands[1].present
9575 ? inst.operands[1].reg : Rd);
9576 Rm = inst.operands[2].reg;
9577
9578 constraint ((Rd == REG_PC), BAD_PC);
9579 constraint ((Rn == REG_PC), BAD_PC);
9580 constraint ((Rm == REG_PC), BAD_PC);
9581
9582 inst.instruction |= Rd << 16;
9583 inst.instruction |= Rn << 0;
9584 inst.instruction |= Rm << 8;
9585}
9586
b99bd4ef 9587static void
c19d1205 9588do_it (void)
b99bd4ef 9589{
c19d1205 9590 /* There is no IT instruction in ARM mode. We
e07e6e58
NC		 9591 process it to do the validation as if in
9592 thumb mode, just in case the code gets
9593 assembled for thumb using the unified syntax. */
9594
c19d1205 9595 inst.size = 0;
e07e6e58
NC		 9596 if (unified_syntax)
9597 {
5ee91343
AV		 9598 set_pred_insn_type (IT_INSN);
9599 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9600 now_pred.cc = inst.operands[0].imm;
e07e6e58 9601 }
09d92015 9602}
b99bd4ef 9603
6530b175
NC		 9604/* If there is only one register in the register list,
9605 then return its register number. Otherwise return -1. */
9606static int
9607only_one_reg_in_list (int range)
9608{
9609 int i = ffs (range) - 1;
9610 return (i > 15 || range != (1 << i)) ? -1 : i;
9611}
9612
09d92015 9613static void
6530b175 9614encode_ldmstm(int from_push_pop_mnem)
ea6ef066 9615{
c19d1205
ZW		 9616 int base_reg = inst.operands[0].reg;
9617 int range = inst.operands[1].imm;
6530b175 9618 int one_reg;
ea6ef066 9619
c19d1205
ZW		 9620 inst.instruction |= base_reg << 16;
9621 inst.instruction |= range;
ea6ef066 9622
c19d1205
ZW		 9623 if (inst.operands[1].writeback)
9624 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 9625
c19d1205 9626 if (inst.operands[0].writeback)
ea6ef066 9627 {
c19d1205
ZW		 9628 inst.instruction |= WRITE_BACK;
9629 /* Check for unpredictable uses of writeback. */
9630 if (inst.instruction & LOAD_BIT)
09d92015 9631 {
c19d1205
ZW		 9632 /* Not allowed in LDM type 2. */
9633 if ((inst.instruction & LDM_TYPE_2_OR_3)
9634 && ((range & (1 << REG_PC)) == 0))
9635 as_warn (_("writeback of base register is UNPREDICTABLE"));
9636 /* Only allowed if base reg not in list for other types. */
9637 else if (range & (1 << base_reg))
9638 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9639 }
9640 else /* STM. */
9641 {
9642 /* Not allowed for type 2. */
9643 if (inst.instruction & LDM_TYPE_2_OR_3)
9644 as_warn (_("writeback of base register is UNPREDICTABLE"));
9645 /* Only allowed if base reg not in list, or first in list. */
9646 else if ((range & (1 << base_reg))
9647 && (range & ((1 << base_reg) - 1)))
9648 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 9649 }
ea6ef066 9650 }
6530b175
NC		 9651
9652 /* If PUSH/POP has only one register, then use the A2 encoding. */
9653 one_reg = only_one_reg_in_list (range);
9654 if (from_push_pop_mnem && one_reg >= 0)
9655 {
9656 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9657
4f588891
NC		 9658 if (is_push && one_reg == 13 /* SP */)
9659 /* PR 22483: The A2 encoding cannot be used when
9660 pushing the stack pointer as this is UNPREDICTABLE. */
9661 return;
9662
6530b175
NC		 9663 inst.instruction &= A_COND_MASK;
9664 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9665 inst.instruction |= one_reg << 12;
9666 }
9667}
9668
9669static void
9670do_ldmstm (void)
9671{
9672 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
a737bd4d
NC		 9673}
9674
c19d1205
ZW		 9675/* ARMv5TE load-consecutive (argument parse)
9676 Mode is like LDRH.
9677
9678 LDRccD R, mode
9679 STRccD R, mode. */
9680
a737bd4d 9681static void
c19d1205 9682do_ldrd (void)
a737bd4d 9683{
c19d1205 9684 constraint (inst.operands[0].reg % 2 != 0,
c56791bb 9685 _("first transfer register must be even"));
c19d1205
ZW		 9686 constraint (inst.operands[1].present
9687 && inst.operands[1].reg != inst.operands[0].reg + 1,
c56791bb 9688 _("can only transfer two consecutive registers"));
c19d1205
ZW		 9689 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9690 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 9691
c19d1205
ZW		 9692 if (!inst.operands[1].present)
9693 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 9694
c56791bb
RE		 9695 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9696 register and the first register written; we have to diagnose
9697 overlap between the base and the second register written here. */
ea6ef066 9698
c56791bb
RE		 9699 if (inst.operands[2].reg == inst.operands[1].reg
9700 && (inst.operands[2].writeback || inst.operands[2].postind))
9701 as_warn (_("base register written back, and overlaps "
9702 "second transfer register"));
b05fe5cf 9703
c56791bb
RE		 9704 if (!(inst.instruction & V4_STR_BIT))
9705 {
c19d1205 9706 /* For an index-register load, the index register must not overlap the
c56791bb
RE		 9707 destination (even if not write-back). */
9708 if (inst.operands[2].immisreg
9709 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9710 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9711 as_warn (_("index register overlaps transfer register"));
b05fe5cf 9712 }
c19d1205
ZW		 9713 inst.instruction |= inst.operands[0].reg << 12;
9714 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW		 9715}
9716
9717static void
c19d1205 9718do_ldrex (void)
b05fe5cf 9719{
c19d1205
ZW		 9720 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9721 || inst.operands[1].postind || inst.operands[1].writeback
9722 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC		 9723 || inst.operands[1].negative
9724 /* This can arise if the programmer has written
9725 strex rN, rM, foo
9726 or if they have mistakenly used a register name as the last
9727 operand, eg:
9728 strex rN, rM, rX
9729 It is very difficult to distinguish between these two cases
9730 because "rX" might actually be a label. ie the register
9731 name has been occluded by a symbol of the same name. So we
9732 just generate a general 'bad addressing mode' type error
9733 message and leave it up to the programmer to discover the
9734 true cause and fix their mistake. */
9735 || (inst.operands[1].reg == REG_PC),
9736 BAD_ADDR_MODE);
b05fe5cf 9737
e2b0ab59
AV		 9738 constraint (inst.relocs[0].exp.X_op != O_constant
9739 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9740 _("offset must be zero in ARM encoding"));
b05fe5cf 9741
5be8be5d
DG		 9742 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9743
c19d1205
ZW		 9744 inst.instruction |= inst.operands[0].reg << 12;
9745 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 9746 inst.relocs[0].type = BFD_RELOC_UNUSED;
b05fe5cf
ZW		 9747}
9748
9749static void
c19d1205 9750do_ldrexd (void)
b05fe5cf 9751{
c19d1205
ZW		 9752 constraint (inst.operands[0].reg % 2 != 0,
9753 _("even register required"));
9754 constraint (inst.operands[1].present
9755 && inst.operands[1].reg != inst.operands[0].reg + 1,
9756 _("can only load two consecutive registers"));
9757 /* If op 1 were present and equal to PC, this function wouldn't
9758 have been called in the first place. */
9759 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 9760
c19d1205
ZW		 9761 inst.instruction |= inst.operands[0].reg << 12;
9762 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW		 9763}
9764
1be5fd2e
NC		 9765/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9766 which is not a multiple of four is UNPREDICTABLE. */
9767static void
9768check_ldr_r15_aligned (void)
9769{
9770 constraint (!(inst.operands[1].immisreg)
9771 && (inst.operands[0].reg == REG_PC
9772 && inst.operands[1].reg == REG_PC
e2b0ab59 9773 && (inst.relocs[0].exp.X_add_number & 0x3)),
de194d85 9774 _("ldr to register 15 must be 4-byte aligned"));
1be5fd2e
NC		 9775}
9776
b05fe5cf 9777static void
c19d1205 9778do_ldst (void)
b05fe5cf 9779{
c19d1205
ZW		 9780 inst.instruction |= inst.operands[0].reg << 12;
9781 if (!inst.operands[1].isreg)
8335d6aa 9782 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
b05fe5cf 9783 return;
c19d1205 9784 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
1be5fd2e 9785 check_ldr_r15_aligned ();
b05fe5cf
ZW		 9786}
9787
9788static void
c19d1205 9789do_ldstt (void)
b05fe5cf 9790{
c19d1205
ZW		 9791 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9792 reject [Rn,...]. */
9793 if (inst.operands[1].preind)
b05fe5cf 9794 {
e2b0ab59
AV		 9795 constraint (inst.relocs[0].exp.X_op != O_constant
9796 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9797 _("this instruction requires a post-indexed address"));
b05fe5cf 9798
c19d1205
ZW		 9799 inst.operands[1].preind = 0;
9800 inst.operands[1].postind = 1;
9801 inst.operands[1].writeback = 1;
b05fe5cf 9802 }
c19d1205
ZW		 9803 inst.instruction |= inst.operands[0].reg << 12;
9804 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9805}
b05fe5cf 9806
c19d1205 9807/* Halfword and signed-byte load/store operations. */
b05fe5cf 9808
c19d1205
ZW		 9809static void
9810do_ldstv4 (void)
9811{
ff4a8d2b 9812 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW		 9813 inst.instruction |= inst.operands[0].reg << 12;
9814 if (!inst.operands[1].isreg)
8335d6aa 9815 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
b05fe5cf 9816 return;
c19d1205 9817 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW		 9818}
9819
9820static void
c19d1205 9821do_ldsttv4 (void)
b05fe5cf 9822{
c19d1205
ZW		 9823 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9824 reject [Rn,...]. */
9825 if (inst.operands[1].preind)
b05fe5cf 9826 {
e2b0ab59
AV		 9827 constraint (inst.relocs[0].exp.X_op != O_constant
9828 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9829 _("this instruction requires a post-indexed address"));
b05fe5cf 9830
c19d1205
ZW		 9831 inst.operands[1].preind = 0;
9832 inst.operands[1].postind = 1;
9833 inst.operands[1].writeback = 1;
b05fe5cf 9834 }
c19d1205
ZW		 9835 inst.instruction |= inst.operands[0].reg << 12;
9836 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9837}
b05fe5cf 9838
c19d1205
ZW		 9839/* Co-processor register load/store.
9840 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9841static void
9842do_lstc (void)
9843{
9844 inst.instruction |= inst.operands[0].reg << 8;
9845 inst.instruction |= inst.operands[1].reg << 12;
9846 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW		 9847}
9848
b05fe5cf 9849static void
c19d1205 9850do_mlas (void)
b05fe5cf 9851{
8fb9d7b9 9852 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 9853 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 9854 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 9855 && !(inst.instruction & 0x00400000))
8fb9d7b9 9856 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 9857
c19d1205
ZW		 9858 inst.instruction |= inst.operands[0].reg << 16;
9859 inst.instruction |= inst.operands[1].reg;
9860 inst.instruction |= inst.operands[2].reg << 8;
9861 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 9862}
b05fe5cf 9863
c19d1205
ZW		 9864static void
9865do_mov (void)
9866{
e2b0ab59
AV		 9867 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9868 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 9869 THUMB1_RELOC_ONLY);
c19d1205
ZW		 9870 inst.instruction |= inst.operands[0].reg << 12;
9871 encode_arm_shifter_operand (1);
9872}
b05fe5cf 9873
c19d1205
ZW		 9874/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9875static void
9876do_mov16 (void)
9877{
b6895b4f
PB		 9878 bfd_vma imm;
9879 bfd_boolean top;
9880
9881 top = (inst.instruction & 0x00400000) != 0;
e2b0ab59 9882 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
33eaf5de 9883 _(":lower16: not allowed in this instruction"));
e2b0ab59 9884 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
33eaf5de 9885 _(":upper16: not allowed in this instruction"));
c19d1205 9886 inst.instruction |= inst.operands[0].reg << 12;
e2b0ab59 9887 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 9888 {
e2b0ab59 9889 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB		 9890 /* The value is in two pieces: 0:11, 16:19. */
9891 inst.instruction |= (imm & 0x00000fff);
9892 inst.instruction |= (imm & 0x0000f000) << 4;
9893 }
b05fe5cf 9894}
b99bd4ef 9895
037e8744
JB		 9896static int
9897do_vfp_nsyn_mrs (void)
9898{
9899 if (inst.operands[0].isvec)
9900 {
9901 if (inst.operands[1].reg != 1)
477330fc 9902 first_error (_("operand 1 must be FPSCR"));
037e8744
JB		 9903 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9904 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9905 do_vfp_nsyn_opcode ("fmstat");
9906 }
9907 else if (inst.operands[1].isvec)
9908 do_vfp_nsyn_opcode ("fmrx");
9909 else
9910 return FAIL;
5f4273c7 9911
037e8744
JB		 9912 return SUCCESS;
9913}
9914
9915static int
9916do_vfp_nsyn_msr (void)
9917{
9918 if (inst.operands[0].isvec)
9919 do_vfp_nsyn_opcode ("fmxr");
9920 else
9921 return FAIL;
9922
9923 return SUCCESS;
9924}
9925
f7c21dc7
NC		 9926static void
9927do_vmrs (void)
9928{
9929 unsigned Rt = inst.operands[0].reg;
fa94de6b 9930
16d02dc9 9931 if (thumb_mode && Rt == REG_SP)
f7c21dc7
NC		 9932 {
9933 inst.error = BAD_SP;
9934 return;
9935 }
9936
ba6cd17f
SD		 9937 switch (inst.operands[1].reg)
9938 {
9939 /* MVFR2 is only valid for Armv8-A. */
9940 case 5:
9941 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9942 _(BAD_FPU));
9943 break;
9944
9945 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9946 case 1: /* fpscr. */
9947 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
9948 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
9949 _(BAD_FPU));
9950 break;
9951
9952 case 14: /* fpcxt_ns. */
9953 case 15: /* fpcxt_s. */
9954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
9955 _("selected processor does not support instruction"));
9956 break;
9957
9958 case 2: /* fpscr_nzcvqc. */
9959 case 12: /* vpr. */
9960 case 13: /* p0. */
9961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
9962 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
9963 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
9964 _("selected processor does not support instruction"));
9965 if (inst.operands[0].reg != 2
9966 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
9967 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9968 break;
9969
9970 default:
9971 break;
9972 }
40c7d507 9973
f7c21dc7 9974 /* APSR_ sets isvec. All other refs to PC are illegal. */
16d02dc9 9975 if (!inst.operands[0].isvec && Rt == REG_PC)
f7c21dc7
NC		 9976 {
9977 inst.error = BAD_PC;
9978 return;
9979 }
9980
16d02dc9
JB		 9981 /* If we get through parsing the register name, we just insert the number
9982 generated into the instruction without further validation. */
9983 inst.instruction |= (inst.operands[1].reg << 16);
f7c21dc7
NC		 9984 inst.instruction |= (Rt << 12);
9985}
9986
9987static void
9988do_vmsr (void)
9989{
9990 unsigned Rt = inst.operands[1].reg;
fa94de6b 9991
f7c21dc7
NC		 9992 if (thumb_mode)
9993 reject_bad_reg (Rt);
9994 else if (Rt == REG_PC)
9995 {
9996 inst.error = BAD_PC;
9997 return;
9998 }
9999
ba6cd17f
SD		 10000 switch (inst.operands[0].reg)
10001 {
10002 /* MVFR2 is only valid for Armv8-A. */
10003 case 5:
10004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10005 _(BAD_FPU));
10006 break;
10007
10008 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10009 case 1: /* fpcr. */
10010 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10011 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10012 _(BAD_FPU));
10013 break;
10014
10015 case 14: /* fpcxt_ns. */
10016 case 15: /* fpcxt_s. */
10017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10018 _("selected processor does not support instruction"));
10019 break;
10020
10021 case 2: /* fpscr_nzcvqc. */
10022 case 12: /* vpr. */
10023 case 13: /* p0. */
10024 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10025 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10026 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10027 _("selected processor does not support instruction"));
10028 if (inst.operands[0].reg != 2
10029 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10030 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10031 break;
10032
10033 default:
10034 break;
10035 }
40c7d507 10036
16d02dc9
JB		 10037 /* If we get through parsing the register name, we just insert the number
10038 generated into the instruction without further validation. */
10039 inst.instruction |= (inst.operands[0].reg << 16);
f7c21dc7
NC		 10040 inst.instruction |= (Rt << 12);
10041}
10042
b99bd4ef 10043static void
c19d1205 10044do_mrs (void)
b99bd4ef 10045{
90ec0d68
MGD		 10046 unsigned br;
10047
037e8744
JB		 10048 if (do_vfp_nsyn_mrs () == SUCCESS)
10049 return;
10050
ff4a8d2b 10051 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205 10052 inst.instruction |= inst.operands[0].reg << 12;
90ec0d68
MGD		 10053
10054 if (inst.operands[1].isreg)
10055 {
10056 br = inst.operands[1].reg;
806ab1c0 10057 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
90ec0d68
MGD		 10058 as_bad (_("bad register for mrs"));
10059 }
10060 else
10061 {
10062 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10063 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
10064 != (PSR_c|PSR_f),
d2cd1205 10065 _("'APSR', 'CPSR' or 'SPSR' expected"));
90ec0d68
MGD		 10066 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
10067 }
10068
10069 inst.instruction |= br;
c19d1205 10070}
b99bd4ef 10071
c19d1205
ZW		 10072/* Two possible forms:
10073 "{C|S}PSR_<field>, Rm",
10074 "{C|S}PSR_f, #expression". */
b99bd4ef 10075
c19d1205
ZW		 10076static void
10077do_msr (void)
10078{
037e8744
JB		 10079 if (do_vfp_nsyn_msr () == SUCCESS)
10080 return;
10081
c19d1205
ZW		 10082 inst.instruction |= inst.operands[0].imm;
10083 if (inst.operands[1].isreg)
10084 inst.instruction |= inst.operands[1].reg;
10085 else
b99bd4ef 10086 {
c19d1205 10087 inst.instruction |= INST_IMMEDIATE;
e2b0ab59
AV		 10088 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
10089 inst.relocs[0].pc_rel = 0;
b99bd4ef 10090 }
b99bd4ef
NC		 10091}
10092
c19d1205
ZW		 10093static void
10094do_mul (void)
a737bd4d 10095{
ff4a8d2b
NC		 10096 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
10097
c19d1205
ZW		 10098 if (!inst.operands[2].present)
10099 inst.operands[2].reg = inst.operands[0].reg;
10100 inst.instruction |= inst.operands[0].reg << 16;
10101 inst.instruction |= inst.operands[1].reg;
10102 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 10103
8fb9d7b9
MS		 10104 if (inst.operands[0].reg == inst.operands[1].reg
10105 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
10106 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC		 10107}
10108
c19d1205
ZW		 10109/* Long Multiply Parser
10110 UMULL RdLo, RdHi, Rm, Rs
10111 SMULL RdLo, RdHi, Rm, Rs
10112 UMLAL RdLo, RdHi, Rm, Rs
10113 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC		 10114
10115static void
c19d1205 10116do_mull (void)
b99bd4ef 10117{
c19d1205
ZW		 10118 inst.instruction |= inst.operands[0].reg << 12;
10119 inst.instruction |= inst.operands[1].reg << 16;
10120 inst.instruction |= inst.operands[2].reg;
10121 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 10122
682b27ad
PB		 10123 /* rdhi and rdlo must be different. */
10124 if (inst.operands[0].reg == inst.operands[1].reg)
10125 as_tsktsk (_("rdhi and rdlo must be different"));
10126
10127 /* rdhi, rdlo and rm must all be different before armv6. */
10128 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 10129 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 10130 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW		 10131 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10132}
b99bd4ef 10133
c19d1205
ZW		 10134static void
10135do_nop (void)
10136{
e7495e45
NS		 10137 if (inst.operands[0].present
10138 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW		 10139 {
10140 /* Architectural NOP hints are CPSR sets with no bits selected. */
10141 inst.instruction &= 0xf0000000;
e7495e45
NS		 10142 inst.instruction |= 0x0320f000;
10143 if (inst.operands[0].present)
10144 inst.instruction |= inst.operands[0].imm;
c19d1205 10145 }
b99bd4ef
NC		 10146}
10147
c19d1205
ZW		 10148/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10149 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10150 Condition defaults to COND_ALWAYS.
10151 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC		 10152
10153static void
c19d1205 10154do_pkhbt (void)
b99bd4ef 10155{
c19d1205
ZW		 10156 inst.instruction |= inst.operands[0].reg << 12;
10157 inst.instruction |= inst.operands[1].reg << 16;
10158 inst.instruction |= inst.operands[2].reg;
10159 if (inst.operands[3].present)
10160 encode_arm_shift (3);
10161}
b99bd4ef 10162
c19d1205 10163/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 10164
c19d1205
ZW		 10165static void
10166do_pkhtb (void)
10167{
10168 if (!inst.operands[3].present)
b99bd4ef 10169 {
c19d1205
ZW		 10170 /* If the shift specifier is omitted, turn the instruction
10171 into pkhbt rd, rm, rn. */
10172 inst.instruction &= 0xfff00010;
10173 inst.instruction |= inst.operands[0].reg << 12;
10174 inst.instruction |= inst.operands[1].reg;
10175 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 10176 }
10177 else
10178 {
c19d1205
ZW		 10179 inst.instruction |= inst.operands[0].reg << 12;
10180 inst.instruction |= inst.operands[1].reg << 16;
10181 inst.instruction |= inst.operands[2].reg;
10182 encode_arm_shift (3);
b99bd4ef
NC		 10183 }
10184}
10185
c19d1205 10186/* ARMv5TE: Preload-Cache
60e5ef9f 10187 MP Extensions: Preload for write
c19d1205 10188
60e5ef9f 10189 PLD(W) <addr_mode>
c19d1205
ZW		 10190
10191 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC		 10192
10193static void
c19d1205 10194do_pld (void)
b99bd4ef 10195{
c19d1205
ZW		 10196 constraint (!inst.operands[0].isreg,
10197 _("'[' expected after PLD mnemonic"));
10198 constraint (inst.operands[0].postind,
10199 _("post-indexed expression used in preload instruction"));
10200 constraint (inst.operands[0].writeback,
10201 _("writeback used in preload instruction"));
10202 constraint (!inst.operands[0].preind,
10203 _("unindexed addressing used in preload instruction"));
c19d1205
ZW		 10204 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10205}
b99bd4ef 10206
62b3e311
PB		 10207/* ARMv7: PLI <addr_mode> */
10208static void
10209do_pli (void)
10210{
10211 constraint (!inst.operands[0].isreg,
10212 _("'[' expected after PLI mnemonic"));
10213 constraint (inst.operands[0].postind,
10214 _("post-indexed expression used in preload instruction"));
10215 constraint (inst.operands[0].writeback,
10216 _("writeback used in preload instruction"));
10217 constraint (!inst.operands[0].preind,
10218 _("unindexed addressing used in preload instruction"));
10219 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10220 inst.instruction &= ~PRE_INDEX;
10221}
10222
c19d1205
ZW		 10223static void
10224do_push_pop (void)
10225{
5e0d7f77
MP		 10226 constraint (inst.operands[0].writeback,
10227 _("push/pop do not support {reglist}^"));
c19d1205
ZW		 10228 inst.operands[1] = inst.operands[0];
10229 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10230 inst.operands[0].isreg = 1;
10231 inst.operands[0].writeback = 1;
10232 inst.operands[0].reg = REG_SP;
6530b175 10233 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
c19d1205 10234}
b99bd4ef 10235
c19d1205
ZW		 10236/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10237 word at the specified address and the following word
10238 respectively.
10239 Unconditionally executed.
10240 Error if Rn is R15. */
b99bd4ef 10241
c19d1205
ZW		 10242static void
10243do_rfe (void)
10244{
10245 inst.instruction |= inst.operands[0].reg << 16;
10246 if (inst.operands[0].writeback)
10247 inst.instruction |= WRITE_BACK;
10248}
b99bd4ef 10249
c19d1205 10250/* ARM V6 ssat (argument parse). */
b99bd4ef 10251
c19d1205
ZW		 10252static void
10253do_ssat (void)
10254{
10255 inst.instruction |= inst.operands[0].reg << 12;
10256 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10257 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10258
c19d1205
ZW		 10259 if (inst.operands[3].present)
10260 encode_arm_shift (3);
b99bd4ef
NC		 10261}
10262
c19d1205 10263/* ARM V6 usat (argument parse). */
b99bd4ef
NC		 10264
10265static void
c19d1205 10266do_usat (void)
b99bd4ef 10267{
c19d1205
ZW		 10268 inst.instruction |= inst.operands[0].reg << 12;
10269 inst.instruction |= inst.operands[1].imm << 16;
10270 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10271
c19d1205
ZW		 10272 if (inst.operands[3].present)
10273 encode_arm_shift (3);
b99bd4ef
NC		 10274}
10275
c19d1205 10276/* ARM V6 ssat16 (argument parse). */
09d92015
MM		 10277
10278static void
c19d1205 10279do_ssat16 (void)
09d92015 10280{
c19d1205
ZW		 10281 inst.instruction |= inst.operands[0].reg << 12;
10282 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10283 inst.instruction |= inst.operands[2].reg;
09d92015
MM		 10284}
10285
c19d1205
ZW		 10286static void
10287do_usat16 (void)
a737bd4d 10288{
c19d1205
ZW		 10289 inst.instruction |= inst.operands[0].reg << 12;
10290 inst.instruction |= inst.operands[1].imm << 16;
10291 inst.instruction |= inst.operands[2].reg;
10292}
a737bd4d 10293
c19d1205
ZW		 10294/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10295 preserving the other bits.
a737bd4d 10296
c19d1205
ZW		 10297 setend <endian_specifier>, where <endian_specifier> is either
10298 BE or LE. */
a737bd4d 10299
c19d1205
ZW		 10300static void
10301do_setend (void)
10302{
12e37cbc
MGD		 10303 if (warn_on_deprecated
10304 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 10305 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 10306
c19d1205
ZW		 10307 if (inst.operands[0].imm)
10308 inst.instruction |= 0x200;
a737bd4d
NC		 10309}
10310
10311static void
c19d1205 10312do_shift (void)
a737bd4d 10313{
c19d1205
ZW		 10314 unsigned int Rm = (inst.operands[1].present
10315 ? inst.operands[1].reg
10316 : inst.operands[0].reg);
a737bd4d 10317
c19d1205
ZW		 10318 inst.instruction |= inst.operands[0].reg << 12;
10319 inst.instruction |= Rm;
10320 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 10321 {
c19d1205
ZW		 10322 inst.instruction |= inst.operands[2].reg << 8;
10323 inst.instruction |= SHIFT_BY_REG;
94342ec3
NC		 10324 /* PR 12854: Error on extraneous shifts. */
10325 constraint (inst.operands[2].shifted,
10326 _("extraneous shift as part of operand to shift insn"));
a737bd4d
NC		 10327 }
10328 else
e2b0ab59 10329 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC		 10330}
10331
09d92015 10332static void
3eb17e6b 10333do_smc (void)
09d92015 10334{
ba85f98c
BW		 10335 unsigned int value = inst.relocs[0].exp.X_add_number;
10336 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
10337
e2b0ab59
AV		 10338 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10339 inst.relocs[0].pc_rel = 0;
09d92015
MM		 10340}
10341
90ec0d68
MGD		 10342static void
10343do_hvc (void)
10344{
e2b0ab59
AV		 10345 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10346 inst.relocs[0].pc_rel = 0;
90ec0d68
MGD		 10347}
10348
09d92015 10349static void
c19d1205 10350do_swi (void)
09d92015 10351{
e2b0ab59
AV		 10352 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10353 inst.relocs[0].pc_rel = 0;
09d92015
MM		 10354}
10355
ddfded2f
MW		 10356static void
10357do_setpan (void)
10358{
10359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10360 _("selected processor does not support SETPAN instruction"));
10361
10362 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10363}
10364
10365static void
10366do_t_setpan (void)
10367{
10368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10369 _("selected processor does not support SETPAN instruction"));
10370
10371 inst.instruction |= (inst.operands[0].imm << 3);
10372}
10373
c19d1205
ZW		 10374/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10375 SMLAxy{cond} Rd,Rm,Rs,Rn
10376 SMLAWy{cond} Rd,Rm,Rs,Rn
10377 Error if any register is R15. */
e16bb312 10378
c19d1205
ZW		 10379static void
10380do_smla (void)
e16bb312 10381{
c19d1205
ZW		 10382 inst.instruction |= inst.operands[0].reg << 16;
10383 inst.instruction |= inst.operands[1].reg;
10384 inst.instruction |= inst.operands[2].reg << 8;
10385 inst.instruction |= inst.operands[3].reg << 12;
10386}
a737bd4d 10387
c19d1205
ZW		 10388/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10389 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10390 Error if any register is R15.
10391 Warning if Rdlo == Rdhi. */
a737bd4d 10392
c19d1205
ZW		 10393static void
10394do_smlal (void)
10395{
10396 inst.instruction |= inst.operands[0].reg << 12;
10397 inst.instruction |= inst.operands[1].reg << 16;
10398 inst.instruction |= inst.operands[2].reg;
10399 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 10400
c19d1205
ZW		 10401 if (inst.operands[0].reg == inst.operands[1].reg)
10402 as_tsktsk (_("rdhi and rdlo must be different"));
10403}
a737bd4d 10404
c19d1205
ZW		 10405/* ARM V5E (El Segundo) signed-multiply (argument parse)
10406 SMULxy{cond} Rd,Rm,Rs
10407 Error if any register is R15. */
a737bd4d 10408
c19d1205
ZW		 10409static void
10410do_smul (void)
10411{
10412 inst.instruction |= inst.operands[0].reg << 16;
10413 inst.instruction |= inst.operands[1].reg;
10414 inst.instruction |= inst.operands[2].reg << 8;
10415}
a737bd4d 10416
b6702015
PB		 10417/* ARM V6 srs (argument parse). The variable fields in the encoding are
10418 the same for both ARM and Thumb-2. */
a737bd4d 10419
c19d1205
ZW		 10420static void
10421do_srs (void)
10422{
b6702015
PB		 10423 int reg;
10424
10425 if (inst.operands[0].present)
10426 {
10427 reg = inst.operands[0].reg;
fdfde340 10428 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB		 10429 }
10430 else
fdfde340 10431 reg = REG_SP;
b6702015
PB		 10432
10433 inst.instruction |= reg << 16;
10434 inst.instruction |= inst.operands[1].imm;
10435 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW		 10436 inst.instruction |= WRITE_BACK;
10437}
a737bd4d 10438
c19d1205 10439/* ARM V6 strex (argument parse). */
a737bd4d 10440
c19d1205
ZW		 10441static void
10442do_strex (void)
10443{
10444 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10445 || inst.operands[2].postind || inst.operands[2].writeback
10446 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC		 10447 || inst.operands[2].negative
10448 /* See comment in do_ldrex(). */
10449 || (inst.operands[2].reg == REG_PC),
10450 BAD_ADDR_MODE);
a737bd4d 10451
c19d1205
ZW		 10452 constraint (inst.operands[0].reg == inst.operands[1].reg
10453 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 10454
e2b0ab59
AV		 10455 constraint (inst.relocs[0].exp.X_op != O_constant
10456 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 10457 _("offset must be zero in ARM encoding"));
a737bd4d 10458
c19d1205
ZW		 10459 inst.instruction |= inst.operands[0].reg << 12;
10460 inst.instruction |= inst.operands[1].reg;
10461 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 10462 inst.relocs[0].type = BFD_RELOC_UNUSED;
e16bb312
NC		 10463}
10464
877807f8
NC		 10465static void
10466do_t_strexbh (void)
10467{
10468 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10469 || inst.operands[2].postind || inst.operands[2].writeback
10470 || inst.operands[2].immisreg || inst.operands[2].shifted
10471 || inst.operands[2].negative,
10472 BAD_ADDR_MODE);
10473
10474 constraint (inst.operands[0].reg == inst.operands[1].reg
10475 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10476
10477 do_rm_rd_rn ();
10478}
10479
e16bb312 10480static void
c19d1205 10481do_strexd (void)
e16bb312 10482{
c19d1205
ZW		 10483 constraint (inst.operands[1].reg % 2 != 0,
10484 _("even register required"));
10485 constraint (inst.operands[2].present
10486 && inst.operands[2].reg != inst.operands[1].reg + 1,
10487 _("can only store two consecutive registers"));
10488 /* If op 2 were present and equal to PC, this function wouldn't
10489 have been called in the first place. */
10490 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 10491
c19d1205
ZW		 10492 constraint (inst.operands[0].reg == inst.operands[1].reg
10493 || inst.operands[0].reg == inst.operands[1].reg + 1
10494 || inst.operands[0].reg == inst.operands[3].reg,
10495 BAD_OVERLAP);
e16bb312 10496
c19d1205
ZW		 10497 inst.instruction |= inst.operands[0].reg << 12;
10498 inst.instruction |= inst.operands[1].reg;
10499 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC		 10500}
10501
9eb6c0f1
MGD		 10502/* ARM V8 STRL. */
10503static void
4b8c8c02 10504do_stlex (void)
9eb6c0f1
MGD		 10505{
10506 constraint (inst.operands[0].reg == inst.operands[1].reg
10507 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10508
10509 do_rd_rm_rn ();
10510}
10511
10512static void
4b8c8c02 10513do_t_stlex (void)
9eb6c0f1
MGD		 10514{
10515 constraint (inst.operands[0].reg == inst.operands[1].reg
10516 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10517
10518 do_rm_rd_rn ();
10519}
10520
c19d1205
ZW		 10521/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10522 extends it to 32-bits, and adds the result to a value in another
10523 register. You can specify a rotation by 0, 8, 16, or 24 bits
10524 before extracting the 16-bit value.
10525 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10526 Condition defaults to COND_ALWAYS.
10527 Error if any register uses R15. */
10528
e16bb312 10529static void
c19d1205 10530do_sxtah (void)
e16bb312 10531{
c19d1205
ZW		 10532 inst.instruction |= inst.operands[0].reg << 12;
10533 inst.instruction |= inst.operands[1].reg << 16;
10534 inst.instruction |= inst.operands[2].reg;
10535 inst.instruction |= inst.operands[3].imm << 10;
10536}
e16bb312 10537
c19d1205 10538/* ARM V6 SXTH.
e16bb312 10539
c19d1205
ZW		 10540 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10541 Condition defaults to COND_ALWAYS.
10542 Error if any register uses R15. */
e16bb312
NC		 10543
10544static void
c19d1205 10545do_sxth (void)
e16bb312 10546{
c19d1205
ZW		 10547 inst.instruction |= inst.operands[0].reg << 12;
10548 inst.instruction |= inst.operands[1].reg;
10549 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 10550}
c19d1205
ZW		 10551\f
10552/* VFP instructions. In a logical order: SP variant first, monad
10553 before dyad, arithmetic then move then load/store. */
e16bb312
NC		 10554
10555static void
c19d1205 10556do_vfp_sp_monadic (void)
e16bb312 10557{
57785aa2
AV		 10558 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10559 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10560 _(BAD_FPU));
10561
5287ad62
JB		 10562 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10563 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 10564}
10565
10566static void
c19d1205 10567do_vfp_sp_dyadic (void)
e16bb312 10568{
5287ad62
JB		 10569 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10570 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10571 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 10572}
10573
10574static void
c19d1205 10575do_vfp_sp_compare_z (void)
e16bb312 10576{
5287ad62 10577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC		 10578}
10579
10580static void
c19d1205 10581do_vfp_dp_sp_cvt (void)
e16bb312 10582{
5287ad62
JB		 10583 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10584 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 10585}
10586
10587static void
c19d1205 10588do_vfp_sp_dp_cvt (void)
e16bb312 10589{
5287ad62
JB		 10590 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10591 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC		 10592}
10593
10594static void
c19d1205 10595do_vfp_reg_from_sp (void)
e16bb312 10596{
57785aa2
AV		 10597 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10598 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10599 _(BAD_FPU));
10600
c19d1205 10601 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 10602 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC		 10603}
10604
10605static void
c19d1205 10606do_vfp_reg2_from_sp2 (void)
e16bb312 10607{
c19d1205
ZW		 10608 constraint (inst.operands[2].imm != 2,
10609 _("only two consecutive VFP SP registers allowed here"));
10610 inst.instruction |= inst.operands[0].reg << 12;
10611 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 10612 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 10613}
10614
10615static void
c19d1205 10616do_vfp_sp_from_reg (void)
e16bb312 10617{
57785aa2
AV		 10618 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10619 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10620 _(BAD_FPU));
10621
5287ad62 10622 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 10623 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC		 10624}
10625
10626static void
c19d1205 10627do_vfp_sp2_from_reg2 (void)
e16bb312 10628{
c19d1205
ZW		 10629 constraint (inst.operands[0].imm != 2,
10630 _("only two consecutive VFP SP registers allowed here"));
5287ad62 10631 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW		 10632 inst.instruction |= inst.operands[1].reg << 12;
10633 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC		 10634}
10635
10636static void
c19d1205 10637do_vfp_sp_ldst (void)
e16bb312 10638{
5287ad62 10639 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 10640 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 10641}
10642
10643static void
c19d1205 10644do_vfp_dp_ldst (void)
e16bb312 10645{
5287ad62 10646 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 10647 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 10648}
10649
c19d1205 10650
e16bb312 10651static void
c19d1205 10652vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10653{
c19d1205
ZW		 10654 if (inst.operands[0].writeback)
10655 inst.instruction |= WRITE_BACK;
10656 else
10657 constraint (ldstm_type != VFP_LDSTMIA,
10658 _("this addressing mode requires base-register writeback"));
10659 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10660 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 10661 inst.instruction |= inst.operands[1].imm;
e16bb312
NC		 10662}
10663
10664static void
c19d1205 10665vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10666{
c19d1205 10667 int count;
e16bb312 10668
c19d1205
ZW		 10669 if (inst.operands[0].writeback)
10670 inst.instruction |= WRITE_BACK;
10671 else
10672 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10673 _("this addressing mode requires base-register writeback"));
e16bb312 10674
c19d1205 10675 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10676 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 10677
c19d1205
ZW		 10678 count = inst.operands[1].imm << 1;
10679 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10680 count += 1;
e16bb312 10681
c19d1205 10682 inst.instruction |= count;
e16bb312
NC		 10683}
10684
10685static void
c19d1205 10686do_vfp_sp_ldstmia (void)
e16bb312 10687{
c19d1205 10688 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 10689}
10690
10691static void
c19d1205 10692do_vfp_sp_ldstmdb (void)
e16bb312 10693{
c19d1205 10694 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 10695}
10696
10697static void
c19d1205 10698do_vfp_dp_ldstmia (void)
e16bb312 10699{
c19d1205 10700 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 10701}
10702
10703static void
c19d1205 10704do_vfp_dp_ldstmdb (void)
e16bb312 10705{
c19d1205 10706 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 10707}
10708
10709static void
c19d1205 10710do_vfp_xp_ldstmia (void)
e16bb312 10711{
c19d1205
ZW		 10712 vfp_dp_ldstm (VFP_LDSTMIAX);
10713}
e16bb312 10714
c19d1205
ZW		 10715static void
10716do_vfp_xp_ldstmdb (void)
10717{
10718 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 10719}
5287ad62
JB		 10720
10721static void
10722do_vfp_dp_rd_rm (void)
10723{
57785aa2
AV		 10724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10725 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10726 _(BAD_FPU));
10727
5287ad62
JB		 10728 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10729 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10730}
10731
10732static void
10733do_vfp_dp_rn_rd (void)
10734{
10735 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10736 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10737}
10738
10739static void
10740do_vfp_dp_rd_rn (void)
10741{
10742 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10743 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10744}
10745
10746static void
10747do_vfp_dp_rd_rn_rm (void)
10748{
57785aa2
AV		 10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10751 _(BAD_FPU));
10752
5287ad62
JB		 10753 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10754 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10755 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10756}
10757
10758static void
10759do_vfp_dp_rd (void)
10760{
10761 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10762}
10763
10764static void
10765do_vfp_dp_rm_rd_rn (void)
10766{
57785aa2
AV		 10767 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10768 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10769 _(BAD_FPU));
10770
5287ad62
JB		 10771 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10772 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10773 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10774}
10775
10776/* VFPv3 instructions. */
10777static void
10778do_vfp_sp_const (void)
10779{
10780 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB		 10781 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10782 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 10783}
10784
10785static void
10786do_vfp_dp_const (void)
10787{
10788 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB		 10789 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10790 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 10791}
10792
10793static void
10794vfp_conv (int srcsize)
10795{
5f1af56b
MGD		 10796 int immbits = srcsize - inst.operands[1].imm;
10797
fa94de6b
RM		 10798 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10799 {
5f1af56b 10800 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
477330fc 10801 i.e. immbits must be in range 0 - 16. */
5f1af56b
MGD		 10802 inst.error = _("immediate value out of range, expected range [0, 16]");
10803 return;
10804 }
fa94de6b 10805 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
5f1af56b
MGD		 10806 {
10807 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
477330fc 10808 i.e. immbits must be in range 0 - 31. */
5f1af56b
MGD		 10809 inst.error = _("immediate value out of range, expected range [1, 32]");
10810 return;
10811 }
10812
5287ad62
JB		 10813 inst.instruction |= (immbits & 1) << 5;
10814 inst.instruction |= (immbits >> 1);
10815}
10816
10817static void
10818do_vfp_sp_conv_16 (void)
10819{
10820 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10821 vfp_conv (16);
10822}
10823
10824static void
10825do_vfp_dp_conv_16 (void)
10826{
10827 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10828 vfp_conv (16);
10829}
10830
10831static void
10832do_vfp_sp_conv_32 (void)
10833{
10834 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10835 vfp_conv (32);
10836}
10837
10838static void
10839do_vfp_dp_conv_32 (void)
10840{
10841 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10842 vfp_conv (32);
10843}
c19d1205
ZW		 10844\f
10845/* FPA instructions. Also in a logical order. */
e16bb312 10846
c19d1205
ZW		 10847static void
10848do_fpa_cmp (void)
10849{
10850 inst.instruction |= inst.operands[0].reg << 16;
10851 inst.instruction |= inst.operands[1].reg;
10852}
b99bd4ef
NC		 10853
10854static void
c19d1205 10855do_fpa_ldmstm (void)
b99bd4ef 10856{
c19d1205
ZW		 10857 inst.instruction |= inst.operands[0].reg << 12;
10858 switch (inst.operands[1].imm)
10859 {
10860 case 1: inst.instruction |= CP_T_X; break;
10861 case 2: inst.instruction |= CP_T_Y; break;
10862 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10863 case 4: break;
10864 default: abort ();
10865 }
b99bd4ef 10866
c19d1205
ZW		 10867 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10868 {
10869 /* The instruction specified "ea" or "fd", so we can only accept
10870 [Rn]{!}. The instruction does not really support stacking or
10871 unstacking, so we have to emulate these by setting appropriate
10872 bits and offsets. */
e2b0ab59
AV		 10873 constraint (inst.relocs[0].exp.X_op != O_constant
10874 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 10875 _("this instruction does not support indexing"));
b99bd4ef 10876
c19d1205 10877 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
e2b0ab59 10878 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 10879
c19d1205 10880 if (!(inst.instruction & INDEX_UP))
e2b0ab59 10881 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
b99bd4ef 10882
c19d1205
ZW		 10883 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
10884 {
10885 inst.operands[2].preind = 0;
10886 inst.operands[2].postind = 1;
10887 }
10888 }
b99bd4ef 10889
c19d1205 10890 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 10891}
c19d1205
ZW		 10892\f
10893/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 10894
c19d1205
ZW		 10895static void
10896do_iwmmxt_tandorc (void)
10897{
10898 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10899}
b99bd4ef 10900
c19d1205
ZW		 10901static void
10902do_iwmmxt_textrc (void)
10903{
10904 inst.instruction |= inst.operands[0].reg << 12;
10905 inst.instruction |= inst.operands[1].imm;
10906}
b99bd4ef
NC		 10907
10908static void
c19d1205 10909do_iwmmxt_textrm (void)
b99bd4ef 10910{
c19d1205
ZW		 10911 inst.instruction |= inst.operands[0].reg << 12;
10912 inst.instruction |= inst.operands[1].reg << 16;
10913 inst.instruction |= inst.operands[2].imm;
10914}
b99bd4ef 10915
c19d1205
ZW		 10916static void
10917do_iwmmxt_tinsr (void)
10918{
10919 inst.instruction |= inst.operands[0].reg << 16;
10920 inst.instruction |= inst.operands[1].reg << 12;
10921 inst.instruction |= inst.operands[2].imm;
10922}
b99bd4ef 10923
c19d1205
ZW		 10924static void
10925do_iwmmxt_tmia (void)
10926{
10927 inst.instruction |= inst.operands[0].reg << 5;
10928 inst.instruction |= inst.operands[1].reg;
10929 inst.instruction |= inst.operands[2].reg << 12;
10930}
b99bd4ef 10931
c19d1205
ZW		 10932static void
10933do_iwmmxt_waligni (void)
10934{
10935 inst.instruction |= inst.operands[0].reg << 12;
10936 inst.instruction |= inst.operands[1].reg << 16;
10937 inst.instruction |= inst.operands[2].reg;
10938 inst.instruction |= inst.operands[3].imm << 20;
10939}
b99bd4ef 10940
2d447fca
JM		 10941static void
10942do_iwmmxt_wmerge (void)
10943{
10944 inst.instruction |= inst.operands[0].reg << 12;
10945 inst.instruction |= inst.operands[1].reg << 16;
10946 inst.instruction |= inst.operands[2].reg;
10947 inst.instruction |= inst.operands[3].imm << 21;
10948}
10949
c19d1205
ZW		 10950static void
10951do_iwmmxt_wmov (void)
10952{
10953 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10954 inst.instruction |= inst.operands[0].reg << 12;
10955 inst.instruction |= inst.operands[1].reg << 16;
10956 inst.instruction |= inst.operands[1].reg;
10957}
b99bd4ef 10958
c19d1205
ZW		 10959static void
10960do_iwmmxt_wldstbh (void)
10961{
8f06b2d8 10962 int reloc;
c19d1205 10963 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB		 10964 if (thumb_mode)
10965 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10966 else
10967 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10968 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC		 10969}
10970
c19d1205
ZW		 10971static void
10972do_iwmmxt_wldstw (void)
10973{
10974 /* RIWR_RIWC clears .isreg for a control register. */
10975 if (!inst.operands[0].isreg)
10976 {
10977 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10978 inst.instruction |= 0xf0000000;
10979 }
b99bd4ef 10980
c19d1205
ZW		 10981 inst.instruction |= inst.operands[0].reg << 12;
10982 encode_arm_cp_address (1, TRUE, TRUE, 0);
10983}
b99bd4ef
NC		 10984
10985static void
c19d1205 10986do_iwmmxt_wldstd (void)
b99bd4ef 10987{
c19d1205 10988 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM		 10989 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10990 && inst.operands[1].immisreg)
10991 {
10992 inst.instruction &= ~0x1a000ff;
eff0bc54 10993 inst.instruction |= (0xfU << 28);
2d447fca
JM		 10994 if (inst.operands[1].preind)
10995 inst.instruction |= PRE_INDEX;
10996 if (!inst.operands[1].negative)
10997 inst.instruction |= INDEX_UP;
10998 if (inst.operands[1].writeback)
10999 inst.instruction |= WRITE_BACK;
11000 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 11001 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
2d447fca
JM		 11002 inst.instruction |= inst.operands[1].imm;
11003 }
11004 else
11005 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 11006}
b99bd4ef 11007
c19d1205
ZW		 11008static void
11009do_iwmmxt_wshufh (void)
11010{
11011 inst.instruction |= inst.operands[0].reg << 12;
11012 inst.instruction |= inst.operands[1].reg << 16;
11013 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
11014 inst.instruction |= (inst.operands[2].imm & 0x0f);
11015}
b99bd4ef 11016
c19d1205
ZW		 11017static void
11018do_iwmmxt_wzero (void)
11019{
11020 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11021 inst.instruction |= inst.operands[0].reg;
11022 inst.instruction |= inst.operands[0].reg << 12;
11023 inst.instruction |= inst.operands[0].reg << 16;
11024}
2d447fca
JM		 11025
11026static void
11027do_iwmmxt_wrwrwr_or_imm5 (void)
11028{
11029 if (inst.operands[2].isreg)
11030 do_rd_rn_rm ();
11031 else {
11032 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
11033 _("immediate operand requires iWMMXt2"));
11034 do_rd_rn ();
11035 if (inst.operands[2].imm == 0)
11036 {
11037 switch ((inst.instruction >> 20) & 0xf)
11038 {
11039 case 4:
11040 case 5:
11041 case 6:
5f4273c7 11042 case 7:
2d447fca
JM		 11043 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11044 inst.operands[2].imm = 16;
11045 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
11046 break;
11047 case 8:
11048 case 9:
11049 case 10:
11050 case 11:
11051 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11052 inst.operands[2].imm = 32;
11053 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
11054 break;
11055 case 12:
11056 case 13:
11057 case 14:
11058 case 15:
11059 {
11060 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11061 unsigned long wrn;
11062 wrn = (inst.instruction >> 16) & 0xf;
11063 inst.instruction &= 0xff0fff0f;
11064 inst.instruction |= wrn;
11065 /* Bail out here; the instruction is now assembled. */
11066 return;
11067 }
11068 }
11069 }
11070 /* Map 32 -> 0, etc. */
11071 inst.operands[2].imm &= 0x1f;
eff0bc54 11072 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
2d447fca
JM		 11073 }
11074}
c19d1205
ZW		 11075\f
11076/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11077 operations first, then control, shift, and load/store. */
b99bd4ef 11078
c19d1205 11079/* Insns like "foo X,Y,Z". */
b99bd4ef 11080
c19d1205
ZW		 11081static void
11082do_mav_triple (void)
11083{
11084 inst.instruction |= inst.operands[0].reg << 16;
11085 inst.instruction |= inst.operands[1].reg;
11086 inst.instruction |= inst.operands[2].reg << 12;
11087}
b99bd4ef 11088
c19d1205
ZW		 11089/* Insns like "foo W,X,Y,Z".
11090 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 11091
c19d1205
ZW		 11092static void
11093do_mav_quad (void)
11094{
11095 inst.instruction |= inst.operands[0].reg << 5;
11096 inst.instruction |= inst.operands[1].reg << 12;
11097 inst.instruction |= inst.operands[2].reg << 16;
11098 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC		 11099}
11100
c19d1205
ZW		 11101/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11102static void
11103do_mav_dspsc (void)
a737bd4d 11104{
c19d1205
ZW		 11105 inst.instruction |= inst.operands[1].reg << 12;
11106}
a737bd4d 11107
c19d1205
ZW		 11108/* Maverick shift immediate instructions.
11109 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11110 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 11111
c19d1205
ZW		 11112static void
11113do_mav_shift (void)
11114{
11115 int imm = inst.operands[2].imm;
a737bd4d 11116
c19d1205
ZW		 11117 inst.instruction |= inst.operands[0].reg << 12;
11118 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 11119
c19d1205
ZW		 11120 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11121 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11122 Bit 4 should be 0. */
11123 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 11124
c19d1205
ZW		 11125 inst.instruction |= imm;
11126}
11127\f
11128/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 11129
c19d1205
ZW		 11130/* Xscale multiply-accumulate (argument parse)
11131 MIAcc acc0,Rm,Rs
11132 MIAPHcc acc0,Rm,Rs
11133 MIAxycc acc0,Rm,Rs. */
a737bd4d 11134
c19d1205
ZW		 11135static void
11136do_xsc_mia (void)
11137{
11138 inst.instruction |= inst.operands[1].reg;
11139 inst.instruction |= inst.operands[2].reg << 12;
11140}
a737bd4d 11141
c19d1205 11142/* Xscale move-accumulator-register (argument parse)
a737bd4d 11143
c19d1205 11144 MARcc acc0,RdLo,RdHi. */
b99bd4ef 11145
c19d1205
ZW		 11146static void
11147do_xsc_mar (void)
11148{
11149 inst.instruction |= inst.operands[1].reg << 12;
11150 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 11151}
11152
c19d1205 11153/* Xscale move-register-accumulator (argument parse)
b99bd4ef 11154
c19d1205 11155 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC		 11156
11157static void
c19d1205 11158do_xsc_mra (void)
b99bd4ef 11159{
c19d1205
ZW		 11160 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
11161 inst.instruction |= inst.operands[0].reg << 12;
11162 inst.instruction |= inst.operands[1].reg << 16;
11163}
11164\f
11165/* Encoding functions relevant only to Thumb. */
b99bd4ef 11166
c19d1205
ZW		 11167/* inst.operands[i] is a shifted-register operand; encode
11168 it into inst.instruction in the format used by Thumb32. */
11169
11170static void
11171encode_thumb32_shifted_operand (int i)
11172{
e2b0ab59 11173 unsigned int value = inst.relocs[0].exp.X_add_number;
c19d1205 11174 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 11175
9c3c69f2
PB		 11176 constraint (inst.operands[i].immisreg,
11177 _("shift by register not allowed in thumb mode"));
c19d1205
ZW		 11178 inst.instruction |= inst.operands[i].reg;
11179 if (shift == SHIFT_RRX)
11180 inst.instruction |= SHIFT_ROR << 4;
11181 else
b99bd4ef 11182 {
e2b0ab59 11183 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW		 11184 _("expression too complex"));
11185
11186 constraint (value > 32
11187 || (value == 32 && (shift == SHIFT_LSL
11188 || shift == SHIFT_ROR)),
11189 _("shift expression is too large"));
11190
11191 if (value == 0)
11192 shift = SHIFT_LSL;
11193 else if (value == 32)
11194 value = 0;
11195
11196 inst.instruction |= shift << 4;
11197 inst.instruction |= (value & 0x1c) << 10;
11198 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 11199 }
c19d1205 11200}
b99bd4ef 11201
b99bd4ef 11202
c19d1205
ZW		 11203/* inst.operands[i] was set up by parse_address. Encode it into a
11204 Thumb32 format load or store instruction. Reject forms that cannot
11205 be used with such instructions. If is_t is true, reject forms that
11206 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG		 11207 that cannot be used with a D instruction. If it is a store insn,
11208 reject PC in Rn. */
b99bd4ef 11209
c19d1205
ZW		 11210static void
11211encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11212{
5be8be5d 11213 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW		 11214
11215 constraint (!inst.operands[i].isreg,
53365c0d 11216 _("Instruction does not support =N addresses"));
b99bd4ef 11217
c19d1205
ZW		 11218 inst.instruction |= inst.operands[i].reg << 16;
11219 if (inst.operands[i].immisreg)
b99bd4ef 11220 {
5be8be5d 11221 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW		 11222 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11223 constraint (inst.operands[i].negative,
11224 _("Thumb does not support negative register indexing"));
11225 constraint (inst.operands[i].postind,
11226 _("Thumb does not support register post-indexing"));
11227 constraint (inst.operands[i].writeback,
11228 _("Thumb does not support register indexing with writeback"));
11229 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11230 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 11231
f40d1643 11232 inst.instruction |= inst.operands[i].imm;
c19d1205 11233 if (inst.operands[i].shifted)
b99bd4ef 11234 {
e2b0ab59 11235 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 11236 _("expression too complex"));
e2b0ab59
AV		 11237 constraint (inst.relocs[0].exp.X_add_number < 0
11238 || inst.relocs[0].exp.X_add_number > 3,
c19d1205 11239 _("shift out of range"));
e2b0ab59 11240 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
c19d1205 11241 }
e2b0ab59 11242 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205
ZW		 11243 }
11244 else if (inst.operands[i].preind)
11245 {
5be8be5d 11246 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 11247 constraint (is_t && inst.operands[i].writeback,
c19d1205 11248 _("cannot use writeback with this instruction"));
4755303e
WN		 11249 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11250 BAD_PC_ADDRESSING);
c19d1205
ZW		 11251
11252 if (is_d)
11253 {
11254 inst.instruction |= 0x01000000;
11255 if (inst.operands[i].writeback)
11256 inst.instruction |= 0x00200000;
b99bd4ef 11257 }
c19d1205 11258 else
b99bd4ef 11259 {
c19d1205
ZW		 11260 inst.instruction |= 0x00000c00;
11261 if (inst.operands[i].writeback)
11262 inst.instruction |= 0x00000100;
b99bd4ef 11263 }
e2b0ab59 11264 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 11265 }
c19d1205 11266 else if (inst.operands[i].postind)
b99bd4ef 11267 {
9c2799c2 11268 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 11269 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11270 constraint (is_t, _("cannot use post-indexing with this instruction"));
11271
11272 if (is_d)
11273 inst.instruction |= 0x00200000;
11274 else
11275 inst.instruction |= 0x00000900;
e2b0ab59 11276 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
c19d1205
ZW		 11277 }
11278 else /* unindexed - only for coprocessor */
11279 inst.error = _("instruction does not accept unindexed addressing");
11280}
11281
e39c1607 11282/* Table of Thumb instructions which exist in 16- and/or 32-bit
c19d1205
ZW		 11283 encodings (the latter only in post-V6T2 cores). The index is the
11284 value used in the insns table below. When there is more than one
11285 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB		 11286 holds variant (1).
11287 Also contains several pseudo-instructions used during relaxation. */
c19d1205 11288#define T16_32_TAB \
21d799b5
NC		 11289 X(_adc, 4140, eb400000), \
11290 X(_adcs, 4140, eb500000), \
11291 X(_add, 1c00, eb000000), \
11292 X(_adds, 1c00, eb100000), \
11293 X(_addi, 0000, f1000000), \
11294 X(_addis, 0000, f1100000), \
11295 X(_add_pc,000f, f20f0000), \
11296 X(_add_sp,000d, f10d0000), \
11297 X(_adr, 000f, f20f0000), \
11298 X(_and, 4000, ea000000), \
11299 X(_ands, 4000, ea100000), \
11300 X(_asr, 1000, fa40f000), \
11301 X(_asrs, 1000, fa50f000), \
11302 X(_b, e000, f000b000), \
11303 X(_bcond, d000, f0008000), \
4389b29a 11304 X(_bf, 0000, f040e001), \
f6b2b12d 11305 X(_bfcsel,0000, f000e001), \
f1c7f421 11306 X(_bfx, 0000, f060e001), \
65d1bc05 11307 X(_bfl, 0000, f000c001), \
f1c7f421 11308 X(_bflx, 0000, f070e001), \
21d799b5
NC		 11309 X(_bic, 4380, ea200000), \
11310 X(_bics, 4380, ea300000), \
e39c1607
SD		 11311 X(_cinc, 0000, ea509000), \
11312 X(_cinv, 0000, ea50a000), \
21d799b5
NC		 11313 X(_cmn, 42c0, eb100f00), \
11314 X(_cmp, 2800, ebb00f00), \
e39c1607 11315 X(_cneg, 0000, ea50b000), \
21d799b5
NC		 11316 X(_cpsie, b660, f3af8400), \
11317 X(_cpsid, b670, f3af8600), \
11318 X(_cpy, 4600, ea4f0000), \
e39c1607
SD		 11319 X(_csel, 0000, ea508000), \
11320 X(_cset, 0000, ea5f900f), \
11321 X(_csetm, 0000, ea5fa00f), \
11322 X(_csinc, 0000, ea509000), \
11323 X(_csinv, 0000, ea50a000), \
11324 X(_csneg, 0000, ea50b000), \
21d799b5 11325 X(_dec_sp,80dd, f1ad0d00), \
60f993ce 11326 X(_dls, 0000, f040e001), \
1f6234a3 11327 X(_dlstp, 0000, f000e001), \
21d799b5
NC		 11328 X(_eor, 4040, ea800000), \
11329 X(_eors, 4040, ea900000), \
11330 X(_inc_sp,00dd, f10d0d00), \
1f6234a3 11331 X(_lctp, 0000, f00fe001), \
21d799b5
NC		 11332 X(_ldmia, c800, e8900000), \
11333 X(_ldr, 6800, f8500000), \
11334 X(_ldrb, 7800, f8100000), \
11335 X(_ldrh, 8800, f8300000), \
11336 X(_ldrsb, 5600, f9100000), \
11337 X(_ldrsh, 5e00, f9300000), \
11338 X(_ldr_pc,4800, f85f0000), \
11339 X(_ldr_pc2,4800, f85f0000), \
11340 X(_ldr_sp,9800, f85d0000), \
60f993ce 11341 X(_le, 0000, f00fc001), \
1f6234a3 11342 X(_letp, 0000, f01fc001), \
21d799b5
NC		 11343 X(_lsl, 0000, fa00f000), \
11344 X(_lsls, 0000, fa10f000), \
11345 X(_lsr, 0800, fa20f000), \
11346 X(_lsrs, 0800, fa30f000), \
11347 X(_mov, 2000, ea4f0000), \
11348 X(_movs, 2000, ea5f0000), \
11349 X(_mul, 4340, fb00f000), \
11350 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11351 X(_mvn, 43c0, ea6f0000), \
11352 X(_mvns, 43c0, ea7f0000), \
11353 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11354 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11355 X(_orr, 4300, ea400000), \
11356 X(_orrs, 4300, ea500000), \
11357 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11358 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11359 X(_rev, ba00, fa90f080), \
11360 X(_rev16, ba40, fa90f090), \
11361 X(_revsh, bac0, fa90f0b0), \
11362 X(_ror, 41c0, fa60f000), \
11363 X(_rors, 41c0, fa70f000), \
11364 X(_sbc, 4180, eb600000), \
11365 X(_sbcs, 4180, eb700000), \
11366 X(_stmia, c000, e8800000), \
11367 X(_str, 6000, f8400000), \
11368 X(_strb, 7000, f8000000), \
11369 X(_strh, 8000, f8200000), \
11370 X(_str_sp,9000, f84d0000), \
11371 X(_sub, 1e00, eba00000), \
11372 X(_subs, 1e00, ebb00000), \
11373 X(_subi, 8000, f1a00000), \
11374 X(_subis, 8000, f1b00000), \
11375 X(_sxtb, b240, fa4ff080), \
11376 X(_sxth, b200, fa0ff080), \
11377 X(_tst, 4200, ea100f00), \
11378 X(_uxtb, b2c0, fa5ff080), \
11379 X(_uxth, b280, fa1ff080), \
11380 X(_nop, bf00, f3af8000), \
11381 X(_yield, bf10, f3af8001), \
11382 X(_wfe, bf20, f3af8002), \
11383 X(_wfi, bf30, f3af8003), \
60f993ce 11384 X(_wls, 0000, f040c001), \
1f6234a3 11385 X(_wlstp, 0000, f000c001), \
53c4b28b 11386 X(_sev, bf40, f3af8004), \
74db7efb
NC		 11387 X(_sevl, bf50, f3af8005), \
11388 X(_udf, de00, f7f0a000)
c19d1205
ZW		 11389
11390/* To catch errors in encoding functions, the codes are all offset by
11391 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11392 as 16-bit instructions. */
21d799b5 11393#define X(a,b,c) T_MNEM##a
c19d1205
ZW		 11394enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11395#undef X
11396
11397#define X(a,b,c) 0x##b
11398static const unsigned short thumb_op16[] = { T16_32_TAB };
11399#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11400#undef X
11401
11402#define X(a,b,c) 0x##c
11403static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC		 11404#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11405#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW		 11406#undef X
11407#undef T16_32_TAB
11408
11409/* Thumb instruction encoders, in alphabetical order. */
11410
92e90b6e 11411/* ADDW or SUBW. */
c921be7d 11412
92e90b6e
PB		 11413static void
11414do_t_add_sub_w (void)
11415{
11416 int Rd, Rn;
11417
11418 Rd = inst.operands[0].reg;
11419 Rn = inst.operands[1].reg;
11420
539d4391
NC		 11421 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11422 is the SP-{plus,minus}-immediate form of the instruction. */
11423 if (Rn == REG_SP)
11424 constraint (Rd == REG_PC, BAD_PC);
11425 else
11426 reject_bad_reg (Rd);
fdfde340 11427
92e90b6e 11428 inst.instruction |= (Rn << 16) | (Rd << 8);
e2b0ab59 11429 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
92e90b6e
PB		 11430}
11431
c19d1205 11432/* Parse an add or subtract instruction. We get here with inst.instruction
33eaf5de 11433 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
c19d1205
ZW		 11434
11435static void
11436do_t_add_sub (void)
11437{
11438 int Rd, Rs, Rn;
11439
11440 Rd = inst.operands[0].reg;
11441 Rs = (inst.operands[1].present
11442 ? inst.operands[1].reg /* Rd, Rs, foo */
11443 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11444
e07e6e58 11445 if (Rd == REG_PC)
5ee91343 11446 set_pred_insn_type_last ();
e07e6e58 11447
c19d1205
ZW		 11448 if (unified_syntax)
11449 {
0110f2b8
PB		 11450 bfd_boolean flags;
11451 bfd_boolean narrow;
11452 int opcode;
11453
11454 flags = (inst.instruction == T_MNEM_adds
11455 || inst.instruction == T_MNEM_subs);
11456 if (flags)
5ee91343 11457 narrow = !in_pred_block ();
0110f2b8 11458 else
5ee91343 11459 narrow = in_pred_block ();
c19d1205 11460 if (!inst.operands[2].isreg)
b99bd4ef 11461 {
16805f35
PB		 11462 int add;
11463
5c8ed6a4
JW		 11464 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11465 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340 11466
16805f35
PB		 11467 add = (inst.instruction == T_MNEM_add
11468 || inst.instruction == T_MNEM_adds);
0110f2b8
PB		 11469 opcode = 0;
11470 if (inst.size_req != 4)
11471 {
0110f2b8 11472 /* Attempt to use a narrow opcode, with relaxation if
477330fc 11473 appropriate. */
0110f2b8
PB		 11474 if (Rd == REG_SP && Rs == REG_SP && !flags)
11475 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11476 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11477 opcode = T_MNEM_add_sp;
11478 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11479 opcode = T_MNEM_add_pc;
11480 else if (Rd <= 7 && Rs <= 7 && narrow)
11481 {
11482 if (flags)
11483 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11484 else
11485 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11486 }
11487 if (opcode)
11488 {
11489 inst.instruction = THUMB_OP16(opcode);
11490 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59
AV		 11491 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11492 || (inst.relocs[0].type
11493 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
a9f02af8
MG		 11494 {
11495 if (inst.size_req == 2)
e2b0ab59 11496 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
a9f02af8
MG		 11497 else
11498 inst.relax = opcode;
11499 }
0110f2b8
PB		 11500 }
11501 else
11502 constraint (inst.size_req == 2, BAD_HIREG);
11503 }
11504 if (inst.size_req == 4
11505 || (inst.size_req != 2 && !opcode))
11506 {
e2b0ab59
AV		 11507 constraint ((inst.relocs[0].type
11508 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11509 && (inst.relocs[0].type
11510 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8 11511 THUMB1_RELOC_ONLY);
efd81785
PB		 11512 if (Rd == REG_PC)
11513 {
fdfde340 11514 constraint (add, BAD_PC);
efd81785
PB		 11515 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11516 _("only SUBS PC, LR, #const allowed"));
e2b0ab59 11517 constraint (inst.relocs[0].exp.X_op != O_constant,
efd81785 11518 _("expression too complex"));
e2b0ab59
AV		 11519 constraint (inst.relocs[0].exp.X_add_number < 0
11520 || inst.relocs[0].exp.X_add_number > 0xff,
efd81785
PB		 11521 _("immediate value out of range"));
11522 inst.instruction = T2_SUBS_PC_LR
e2b0ab59
AV		 11523 | inst.relocs[0].exp.X_add_number;
11524 inst.relocs[0].type = BFD_RELOC_UNUSED;
efd81785
PB		 11525 return;
11526 }
11527 else if (Rs == REG_PC)
16805f35
PB		 11528 {
11529 /* Always use addw/subw. */
11530 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
e2b0ab59 11531 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
16805f35
PB		 11532 }
11533 else
11534 {
11535 inst.instruction = THUMB_OP32 (inst.instruction);
11536 inst.instruction = (inst.instruction & 0xe1ffffff)
11537 | 0x10000000;
11538 if (flags)
e2b0ab59 11539 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
16805f35 11540 else
e2b0ab59 11541 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
16805f35 11542 }
dc4503c6
PB		 11543 inst.instruction |= Rd << 8;
11544 inst.instruction |= Rs << 16;
0110f2b8 11545 }
b99bd4ef 11546 }
c19d1205
ZW		 11547 else
11548 {
e2b0ab59 11549 unsigned int value = inst.relocs[0].exp.X_add_number;
5f4cb198
NC		 11550 unsigned int shift = inst.operands[2].shift_kind;
11551
c19d1205
ZW		 11552 Rn = inst.operands[2].reg;
11553 /* See if we can do this with a 16-bit instruction. */
11554 if (!inst.operands[2].shifted && inst.size_req != 4)
11555 {
e27ec89e
PB		 11556 if (Rd > 7 || Rs > 7 || Rn > 7)
11557 narrow = FALSE;
11558
11559 if (narrow)
c19d1205 11560 {
e27ec89e
PB		 11561 inst.instruction = ((inst.instruction == T_MNEM_adds
11562 || inst.instruction == T_MNEM_add)
c19d1205
ZW		 11563 ? T_OPCODE_ADD_R3
11564 : T_OPCODE_SUB_R3);
11565 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11566 return;
11567 }
b99bd4ef 11568
7e806470 11569 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 11570 {
7e806470
PB		 11571 /* Thumb-1 cores (except v6-M) require at least one high
11572 register in a narrow non flag setting add. */
11573 if (Rd > 7 || Rn > 7
11574 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11575 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 11576 {
7e806470
PB		 11577 if (Rd == Rn)
11578 {
11579 Rn = Rs;
11580 Rs = Rd;
11581 }
c19d1205
ZW		 11582 inst.instruction = T_OPCODE_ADD_HI;
11583 inst.instruction |= (Rd & 8) << 4;
11584 inst.instruction |= (Rd & 7);
11585 inst.instruction |= Rn << 3;
11586 return;
11587 }
c19d1205
ZW		 11588 }
11589 }
c921be7d 11590
fdfde340 11591 constraint (Rd == REG_PC, BAD_PC);
5c8ed6a4
JW		 11592 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11593 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340
JM		 11594 constraint (Rs == REG_PC, BAD_PC);
11595 reject_bad_reg (Rn);
11596
c19d1205
ZW		 11597 /* If we get here, it can't be done in 16 bits. */
11598 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11599 _("shift must be constant"));
11600 inst.instruction = THUMB_OP32 (inst.instruction);
11601 inst.instruction |= Rd << 8;
11602 inst.instruction |= Rs << 16;
5f4cb198
NC		 11603 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11604 _("shift value over 3 not allowed in thumb mode"));
11605 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11606 _("only LSL shift allowed in thumb mode"));
c19d1205
ZW		 11607 encode_thumb32_shifted_operand (2);
11608 }
11609 }
11610 else
11611 {
11612 constraint (inst.instruction == T_MNEM_adds
11613 || inst.instruction == T_MNEM_subs,
11614 BAD_THUMB32);
b99bd4ef 11615
c19d1205 11616 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 11617 {
c19d1205
ZW		 11618 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11619 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11620 BAD_HIREG);
11621
11622 inst.instruction = (inst.instruction == T_MNEM_add
11623 ? 0x0000 : 0x8000);
11624 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59 11625 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC		 11626 return;
11627 }
11628
c19d1205
ZW		 11629 Rn = inst.operands[2].reg;
11630 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 11631
c19d1205
ZW		 11632 /* We now have Rd, Rs, and Rn set to registers. */
11633 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 11634 {
c19d1205
ZW		 11635 /* Can't do this for SUB. */
11636 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11637 inst.instruction = T_OPCODE_ADD_HI;
11638 inst.instruction |= (Rd & 8) << 4;
11639 inst.instruction |= (Rd & 7);
11640 if (Rs == Rd)
11641 inst.instruction |= Rn << 3;
11642 else if (Rn == Rd)
11643 inst.instruction |= Rs << 3;
11644 else
11645 constraint (1, _("dest must overlap one source register"));
11646 }
11647 else
11648 {
11649 inst.instruction = (inst.instruction == T_MNEM_add
11650 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11651 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 11652 }
b99bd4ef 11653 }
b99bd4ef
NC		 11654}
11655
c19d1205
ZW		 11656static void
11657do_t_adr (void)
11658{
fdfde340
JM		 11659 unsigned Rd;
11660
11661 Rd = inst.operands[0].reg;
11662 reject_bad_reg (Rd);
11663
11664 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB		 11665 {
11666 /* Defer to section relaxation. */
11667 inst.relax = inst.instruction;
11668 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 11669 inst.instruction |= Rd << 4;
0110f2b8
PB		 11670 }
11671 else if (unified_syntax && inst.size_req != 2)
e9f89963 11672 {
0110f2b8 11673 /* Generate a 32-bit opcode. */
e9f89963 11674 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11675 inst.instruction |= Rd << 8;
e2b0ab59
AV		 11676 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11677 inst.relocs[0].pc_rel = 1;
e9f89963
PB		 11678 }
11679 else
11680 {
0110f2b8 11681 /* Generate a 16-bit opcode. */
e9f89963 11682 inst.instruction = THUMB_OP16 (inst.instruction);
e2b0ab59
AV		 11683 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11684 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11685 inst.relocs[0].pc_rel = 1;
fdfde340 11686 inst.instruction |= Rd << 4;
e9f89963 11687 }
52a86f84 11688
e2b0ab59
AV		 11689 if (inst.relocs[0].exp.X_op == O_symbol
11690 && inst.relocs[0].exp.X_add_symbol != NULL
11691 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11692 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11693 inst.relocs[0].exp.X_add_number += 1;
c19d1205 11694}
b99bd4ef 11695
c19d1205
ZW		 11696/* Arithmetic instructions for which there is just one 16-bit
11697 instruction encoding, and it allows only two low registers.
11698 For maximal compatibility with ARM syntax, we allow three register
11699 operands even when Thumb-32 instructions are not available, as long
11700 as the first two are identical. For instance, both "sbc r0,r1" and
11701 "sbc r0,r0,r1" are allowed. */
b99bd4ef 11702static void
c19d1205 11703do_t_arit3 (void)
b99bd4ef 11704{
c19d1205 11705 int Rd, Rs, Rn;
b99bd4ef 11706
c19d1205
ZW		 11707 Rd = inst.operands[0].reg;
11708 Rs = (inst.operands[1].present
11709 ? inst.operands[1].reg /* Rd, Rs, foo */
11710 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11711 Rn = inst.operands[2].reg;
b99bd4ef 11712
fdfde340
JM		 11713 reject_bad_reg (Rd);
11714 reject_bad_reg (Rs);
11715 if (inst.operands[2].isreg)
11716 reject_bad_reg (Rn);
11717
c19d1205 11718 if (unified_syntax)
b99bd4ef 11719 {
c19d1205
ZW		 11720 if (!inst.operands[2].isreg)
11721 {
11722 /* For an immediate, we always generate a 32-bit opcode;
11723 section relaxation will shrink it later if possible. */
11724 inst.instruction = THUMB_OP32 (inst.instruction);
11725 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11726 inst.instruction |= Rd << 8;
11727 inst.instruction |= Rs << 16;
e2b0ab59 11728 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
c19d1205
ZW		 11729 }
11730 else
11731 {
e27ec89e
PB		 11732 bfd_boolean narrow;
11733
c19d1205 11734 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11735 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11736 narrow = !in_pred_block ();
e27ec89e 11737 else
5ee91343 11738 narrow = in_pred_block ();
e27ec89e
PB		 11739
11740 if (Rd > 7 || Rn > 7 || Rs > 7)
11741 narrow = FALSE;
11742 if (inst.operands[2].shifted)
11743 narrow = FALSE;
11744 if (inst.size_req == 4)
11745 narrow = FALSE;
11746
11747 if (narrow
c19d1205
ZW		 11748 && Rd == Rs)
11749 {
11750 inst.instruction = THUMB_OP16 (inst.instruction);
11751 inst.instruction |= Rd;
11752 inst.instruction |= Rn << 3;
11753 return;
11754 }
b99bd4ef 11755
c19d1205
ZW		 11756 /* If we get here, it can't be done in 16 bits. */
11757 constraint (inst.operands[2].shifted
11758 && inst.operands[2].immisreg,
11759 _("shift must be constant"));
11760 inst.instruction = THUMB_OP32 (inst.instruction);
11761 inst.instruction |= Rd << 8;
11762 inst.instruction |= Rs << 16;
11763 encode_thumb32_shifted_operand (2);
11764 }
a737bd4d 11765 }
c19d1205 11766 else
b99bd4ef 11767 {
c19d1205
ZW		 11768 /* On its face this is a lie - the instruction does set the
11769 flags. However, the only supported mnemonic in this mode
11770 says it doesn't. */
11771 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 11772
c19d1205
ZW		 11773 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11774 _("unshifted register required"));
11775 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11776 constraint (Rd != Rs,
11777 _("dest and source1 must be the same register"));
a737bd4d 11778
c19d1205
ZW		 11779 inst.instruction = THUMB_OP16 (inst.instruction);
11780 inst.instruction |= Rd;
11781 inst.instruction |= Rn << 3;
b99bd4ef 11782 }
a737bd4d 11783}
b99bd4ef 11784
c19d1205
ZW		 11785/* Similarly, but for instructions where the arithmetic operation is
11786 commutative, so we can allow either of them to be different from
11787 the destination operand in a 16-bit instruction. For instance, all
11788 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11789 accepted. */
11790static void
11791do_t_arit3c (void)
a737bd4d 11792{
c19d1205 11793 int Rd, Rs, Rn;
b99bd4ef 11794
c19d1205
ZW		 11795 Rd = inst.operands[0].reg;
11796 Rs = (inst.operands[1].present
11797 ? inst.operands[1].reg /* Rd, Rs, foo */
11798 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11799 Rn = inst.operands[2].reg;
c921be7d 11800
fdfde340
JM		 11801 reject_bad_reg (Rd);
11802 reject_bad_reg (Rs);
11803 if (inst.operands[2].isreg)
11804 reject_bad_reg (Rn);
a737bd4d 11805
c19d1205 11806 if (unified_syntax)
a737bd4d 11807 {
c19d1205 11808 if (!inst.operands[2].isreg)
b99bd4ef 11809 {
c19d1205
ZW		 11810 /* For an immediate, we always generate a 32-bit opcode;
11811 section relaxation will shrink it later if possible. */
11812 inst.instruction = THUMB_OP32 (inst.instruction);
11813 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11814 inst.instruction |= Rd << 8;
11815 inst.instruction |= Rs << 16;
e2b0ab59 11816 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 11817 }
c19d1205 11818 else
a737bd4d 11819 {
e27ec89e
PB		 11820 bfd_boolean narrow;
11821
c19d1205 11822 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11823 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11824 narrow = !in_pred_block ();
e27ec89e 11825 else
5ee91343 11826 narrow = in_pred_block ();
e27ec89e
PB		 11827
11828 if (Rd > 7 || Rn > 7 || Rs > 7)
11829 narrow = FALSE;
11830 if (inst.operands[2].shifted)
11831 narrow = FALSE;
11832 if (inst.size_req == 4)
11833 narrow = FALSE;
11834
11835 if (narrow)
a737bd4d 11836 {
c19d1205 11837 if (Rd == Rs)
a737bd4d 11838 {
c19d1205
ZW		 11839 inst.instruction = THUMB_OP16 (inst.instruction);
11840 inst.instruction |= Rd;
11841 inst.instruction |= Rn << 3;
11842 return;
a737bd4d 11843 }
c19d1205 11844 if (Rd == Rn)
a737bd4d 11845 {
c19d1205
ZW		 11846 inst.instruction = THUMB_OP16 (inst.instruction);
11847 inst.instruction |= Rd;
11848 inst.instruction |= Rs << 3;
11849 return;
a737bd4d
NC		 11850 }
11851 }
c19d1205
ZW		 11852
11853 /* If we get here, it can't be done in 16 bits. */
11854 constraint (inst.operands[2].shifted
11855 && inst.operands[2].immisreg,
11856 _("shift must be constant"));
11857 inst.instruction = THUMB_OP32 (inst.instruction);
11858 inst.instruction |= Rd << 8;
11859 inst.instruction |= Rs << 16;
11860 encode_thumb32_shifted_operand (2);
a737bd4d 11861 }
b99bd4ef 11862 }
c19d1205
ZW		 11863 else
11864 {
11865 /* On its face this is a lie - the instruction does set the
11866 flags. However, the only supported mnemonic in this mode
11867 says it doesn't. */
11868 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 11869
c19d1205
ZW		 11870 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11871 _("unshifted register required"));
11872 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11873
11874 inst.instruction = THUMB_OP16 (inst.instruction);
11875 inst.instruction |= Rd;
11876
11877 if (Rd == Rs)
11878 inst.instruction |= Rn << 3;
11879 else if (Rd == Rn)
11880 inst.instruction |= Rs << 3;
11881 else
11882 constraint (1, _("dest must overlap one source register"));
11883 }
a737bd4d
NC		 11884}
11885
c19d1205
ZW		 11886static void
11887do_t_bfc (void)
a737bd4d 11888{
fdfde340 11889 unsigned Rd;
c19d1205
ZW		 11890 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11891 constraint (msb > 32, _("bit-field extends past end of register"));
11892 /* The instruction encoding stores the LSB and MSB,
11893 not the LSB and width. */
fdfde340
JM		 11894 Rd = inst.operands[0].reg;
11895 reject_bad_reg (Rd);
11896 inst.instruction |= Rd << 8;
c19d1205
ZW		 11897 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11898 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11899 inst.instruction |= msb - 1;
b99bd4ef
NC		 11900}
11901
c19d1205
ZW		 11902static void
11903do_t_bfi (void)
b99bd4ef 11904{
fdfde340 11905 int Rd, Rn;
c19d1205 11906 unsigned int msb;
b99bd4ef 11907
fdfde340
JM		 11908 Rd = inst.operands[0].reg;
11909 reject_bad_reg (Rd);
11910
c19d1205
ZW		 11911 /* #0 in second position is alternative syntax for bfc, which is
11912 the same instruction but with REG_PC in the Rm field. */
11913 if (!inst.operands[1].isreg)
fdfde340
JM		 11914 Rn = REG_PC;
11915 else
11916 {
11917 Rn = inst.operands[1].reg;
11918 reject_bad_reg (Rn);
11919 }
b99bd4ef 11920
c19d1205
ZW		 11921 msb = inst.operands[2].imm + inst.operands[3].imm;
11922 constraint (msb > 32, _("bit-field extends past end of register"));
11923 /* The instruction encoding stores the LSB and MSB,
11924 not the LSB and width. */
fdfde340
JM		 11925 inst.instruction |= Rd << 8;
11926 inst.instruction |= Rn << 16;
c19d1205
ZW		 11927 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11928 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11929 inst.instruction |= msb - 1;
b99bd4ef
NC		 11930}
11931
c19d1205
ZW		 11932static void
11933do_t_bfx (void)
b99bd4ef 11934{
fdfde340
JM		 11935 unsigned Rd, Rn;
11936
11937 Rd = inst.operands[0].reg;
11938 Rn = inst.operands[1].reg;
11939
11940 reject_bad_reg (Rd);
11941 reject_bad_reg (Rn);
11942
c19d1205
ZW		 11943 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11944 _("bit-field extends past end of register"));
fdfde340
JM		 11945 inst.instruction |= Rd << 8;
11946 inst.instruction |= Rn << 16;
c19d1205
ZW		 11947 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11948 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11949 inst.instruction |= inst.operands[3].imm - 1;
11950}
b99bd4ef 11951
c19d1205
ZW		 11952/* ARM V5 Thumb BLX (argument parse)
11953 BLX <target_addr> which is BLX(1)
11954 BLX <Rm> which is BLX(2)
11955 Unfortunately, there are two different opcodes for this mnemonic.
11956 So, the insns[].value is not used, and the code here zaps values
11957 into inst.instruction.
b99bd4ef 11958
c19d1205
ZW		 11959 ??? How to take advantage of the additional two bits of displacement
11960 available in Thumb32 mode? Need new relocation? */
b99bd4ef 11961
c19d1205
ZW		 11962static void
11963do_t_blx (void)
11964{
5ee91343 11965 set_pred_insn_type_last ();
e07e6e58 11966
c19d1205 11967 if (inst.operands[0].isreg)
fdfde340
JM		 11968 {
11969 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11970 /* We have a register, so this is BLX(2). */
11971 inst.instruction |= inst.operands[0].reg << 3;
11972 }
b99bd4ef
NC		 11973 else
11974 {
c19d1205 11975 /* No register. This must be BLX(1). */
2fc8bdac 11976 inst.instruction = 0xf000e800;
0855e32b 11977 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
b99bd4ef
NC		 11978 }
11979}
11980
c19d1205
ZW		 11981static void
11982do_t_branch (void)
b99bd4ef 11983{
0110f2b8 11984 int opcode;
dfa9f0d5 11985 int cond;
2fe88214 11986 bfd_reloc_code_real_type reloc;
dfa9f0d5 11987
e07e6e58 11988 cond = inst.cond;
5ee91343 11989 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
e07e6e58 11990
5ee91343 11991 if (in_pred_block ())
dfa9f0d5
PB		 11992 {
11993 /* Conditional branches inside IT blocks are encoded as unconditional
477330fc 11994 branches. */
dfa9f0d5 11995 cond = COND_ALWAYS;
dfa9f0d5
PB		 11996 }
11997 else
11998 cond = inst.cond;
11999
12000 if (cond != COND_ALWAYS)
0110f2b8
PB		 12001 opcode = T_MNEM_bcond;
12002 else
12003 opcode = inst.instruction;
12004
12d6b0b7
RS		 12005 if (unified_syntax
12006 && (inst.size_req == 4
10960bfb
PB		 12007 || (inst.size_req != 2
12008 && (inst.operands[0].hasreloc
e2b0ab59 12009 || inst.relocs[0].exp.X_op == O_constant))))
c19d1205 12010 {
0110f2b8 12011 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 12012 if (cond == COND_ALWAYS)
9ae92b05 12013 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW		 12014 else
12015 {
ff8646ee
TP		 12016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
12017 _("selected architecture does not support "
12018 "wide conditional branch instruction"));
12019
9c2799c2 12020 gas_assert (cond != 0xF);
dfa9f0d5 12021 inst.instruction |= cond << 22;
9ae92b05 12022 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
c19d1205
ZW		 12023 }
12024 }
b99bd4ef
NC		 12025 else
12026 {
0110f2b8 12027 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 12028 if (cond == COND_ALWAYS)
9ae92b05 12029 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
c19d1205 12030 else
b99bd4ef 12031 {
dfa9f0d5 12032 inst.instruction |= cond << 8;
9ae92b05 12033 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 12034 }
0110f2b8
PB		 12035 /* Allow section relaxation. */
12036 if (unified_syntax && inst.size_req != 2)
12037 inst.relax = opcode;
b99bd4ef 12038 }
e2b0ab59
AV		 12039 inst.relocs[0].type = reloc;
12040 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC		 12041}
12042
8884b720 12043/* Actually do the work for Thumb state bkpt and hlt. The only difference
bacebabc 12044 between the two is the maximum immediate allowed - which is passed in
8884b720 12045 RANGE. */
b99bd4ef 12046static void
8884b720 12047do_t_bkpt_hlt1 (int range)
b99bd4ef 12048{
dfa9f0d5
PB		 12049 constraint (inst.cond != COND_ALWAYS,
12050 _("instruction is always unconditional"));
c19d1205 12051 if (inst.operands[0].present)
b99bd4ef 12052 {
8884b720 12053 constraint (inst.operands[0].imm > range,
c19d1205
ZW		 12054 _("immediate value out of range"));
12055 inst.instruction |= inst.operands[0].imm;
b99bd4ef 12056 }
8884b720 12057
5ee91343 12058 set_pred_insn_type (NEUTRAL_IT_INSN);
8884b720
MGD		 12059}
12060
12061static void
12062do_t_hlt (void)
12063{
12064 do_t_bkpt_hlt1 (63);
12065}
12066
12067static void
12068do_t_bkpt (void)
12069{
12070 do_t_bkpt_hlt1 (255);
b99bd4ef
NC		 12071}
12072
12073static void
c19d1205 12074do_t_branch23 (void)
b99bd4ef 12075{
5ee91343 12076 set_pred_insn_type_last ();
0855e32b 12077 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
fa94de6b 12078
0855e32b
NS		 12079 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12080 this file. We used to simply ignore the PLT reloc type here --
12081 the branch encoding is now needed to deal with TLSCALL relocs.
12082 So if we see a PLT reloc now, put it back to how it used to be to
12083 keep the preexisting behaviour. */
e2b0ab59
AV		 12084 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
12085 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a 12086
4343666d 12087#if defined(OBJ_COFF)
c19d1205
ZW		 12088 /* If the destination of the branch is a defined symbol which does not have
12089 the THUMB_FUNC attribute, then we must be calling a function which has
12090 the (interfacearm) attribute. We look for the Thumb entry point to that
12091 function and change the branch to refer to that function instead. */
e2b0ab59
AV		 12092 if ( inst.relocs[0].exp.X_op == O_symbol
12093 && inst.relocs[0].exp.X_add_symbol != NULL
12094 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
12095 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
12096 inst.relocs[0].exp.X_add_symbol
12097 = find_real_start (inst.relocs[0].exp.X_add_symbol);
4343666d 12098#endif
90e4755a
RE		 12099}
12100
12101static void
c19d1205 12102do_t_bx (void)
90e4755a 12103{
5ee91343 12104 set_pred_insn_type_last ();
c19d1205
ZW		 12105 inst.instruction |= inst.operands[0].reg << 3;
12106 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12107 should cause the alignment to be checked once it is known. This is
12108 because BX PC only works if the instruction is word aligned. */
12109}
90e4755a 12110
c19d1205
ZW		 12111static void
12112do_t_bxj (void)
12113{
fdfde340 12114 int Rm;
90e4755a 12115
5ee91343 12116 set_pred_insn_type_last ();
fdfde340
JM		 12117 Rm = inst.operands[0].reg;
12118 reject_bad_reg (Rm);
12119 inst.instruction |= Rm << 16;
90e4755a
RE		 12120}
12121
12122static void
c19d1205 12123do_t_clz (void)
90e4755a 12124{
fdfde340
JM		 12125 unsigned Rd;
12126 unsigned Rm;
12127
12128 Rd = inst.operands[0].reg;
12129 Rm = inst.operands[1].reg;
12130
12131 reject_bad_reg (Rd);
12132 reject_bad_reg (Rm);
12133
12134 inst.instruction |= Rd << 8;
12135 inst.instruction |= Rm << 16;
12136 inst.instruction |= Rm;
c19d1205 12137}
90e4755a 12138
e39c1607
SD		 12139/* For the Armv8.1-M conditional instructions. */
12140static void
12141do_t_cond (void)
12142{
12143 unsigned Rd, Rn, Rm;
12144 signed int cond;
12145
12146 constraint (inst.cond != COND_ALWAYS, BAD_COND);
12147
12148 Rd = inst.operands[0].reg;
12149 switch (inst.instruction)
12150 {
12151 case T_MNEM_csinc:
12152 case T_MNEM_csinv:
12153 case T_MNEM_csneg:
12154 case T_MNEM_csel:
12155 Rn = inst.operands[1].reg;
12156 Rm = inst.operands[2].reg;
12157 cond = inst.operands[3].imm;
12158 constraint (Rn == REG_SP, BAD_SP);
12159 constraint (Rm == REG_SP, BAD_SP);
12160 break;
12161
12162 case T_MNEM_cinc:
12163 case T_MNEM_cinv:
12164 case T_MNEM_cneg:
12165 Rn = inst.operands[1].reg;
12166 cond = inst.operands[2].imm;
12167 /* Invert the last bit to invert the cond. */
12168 cond = TOGGLE_BIT (cond, 0);
12169 constraint (Rn == REG_SP, BAD_SP);
12170 Rm = Rn;
12171 break;
12172
12173 case T_MNEM_csetm:
12174 case T_MNEM_cset:
12175 cond = inst.operands[1].imm;
12176 /* Invert the last bit to invert the cond. */
12177 cond = TOGGLE_BIT (cond, 0);
12178 Rn = REG_PC;
12179 Rm = REG_PC;
12180 break;
12181
12182 default: abort ();
12183 }
12184
12185 set_pred_insn_type (OUTSIDE_PRED_INSN);
12186 inst.instruction = THUMB_OP32 (inst.instruction);
12187 inst.instruction |= Rd << 8;
12188 inst.instruction |= Rn << 16;
12189 inst.instruction |= Rm;
12190 inst.instruction |= cond << 4;
12191}
12192
91d8b670
JG		 12193static void
12194do_t_csdb (void)
12195{
5ee91343 12196 set_pred_insn_type (OUTSIDE_PRED_INSN);
91d8b670
JG		 12197}
12198
dfa9f0d5
PB		 12199static void
12200do_t_cps (void)
12201{
5ee91343 12202 set_pred_insn_type (OUTSIDE_PRED_INSN);
dfa9f0d5
PB		 12203 inst.instruction |= inst.operands[0].imm;
12204}
12205
c19d1205
ZW		 12206static void
12207do_t_cpsi (void)
12208{
5ee91343 12209 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205 12210 if (unified_syntax
62b3e311
PB		 12211 && (inst.operands[1].present || inst.size_req == 4)
12212 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 12213 {
c19d1205
ZW		 12214 unsigned int imod = (inst.instruction & 0x0030) >> 4;
12215 inst.instruction = 0xf3af8000;
12216 inst.instruction |= imod << 9;
12217 inst.instruction |= inst.operands[0].imm << 5;
12218 if (inst.operands[1].present)
12219 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 12220 }
c19d1205 12221 else
90e4755a 12222 {
62b3e311
PB		 12223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
12224 && (inst.operands[0].imm & 4),
12225 _("selected processor does not support 'A' form "
12226 "of this instruction"));
12227 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW		 12228 _("Thumb does not support the 2-argument "
12229 "form of this instruction"));
12230 inst.instruction |= inst.operands[0].imm;
90e4755a 12231 }
90e4755a
RE		 12232}
12233
c19d1205
ZW		 12234/* THUMB CPY instruction (argument parse). */
12235
90e4755a 12236static void
c19d1205 12237do_t_cpy (void)
90e4755a 12238{
c19d1205 12239 if (inst.size_req == 4)
90e4755a 12240 {
c19d1205
ZW		 12241 inst.instruction = THUMB_OP32 (T_MNEM_mov);
12242 inst.instruction |= inst.operands[0].reg << 8;
12243 inst.instruction |= inst.operands[1].reg;
90e4755a 12244 }
c19d1205 12245 else
90e4755a 12246 {
c19d1205
ZW		 12247 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12248 inst.instruction |= (inst.operands[0].reg & 0x7);
12249 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 12250 }
90e4755a
RE		 12251}
12252
90e4755a 12253static void
25fe350b 12254do_t_cbz (void)
90e4755a 12255{
5ee91343 12256 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW		 12257 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12258 inst.instruction |= inst.operands[0].reg;
e2b0ab59
AV		 12259 inst.relocs[0].pc_rel = 1;
12260 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
c19d1205 12261}
90e4755a 12262
62b3e311
PB		 12263static void
12264do_t_dbg (void)
12265{
12266 inst.instruction |= inst.operands[0].imm;
12267}
12268
12269static void
12270do_t_div (void)
12271{
fdfde340
JM		 12272 unsigned Rd, Rn, Rm;
12273
12274 Rd = inst.operands[0].reg;
12275 Rn = (inst.operands[1].present
12276 ? inst.operands[1].reg : Rd);
12277 Rm = inst.operands[2].reg;
12278
12279 reject_bad_reg (Rd);
12280 reject_bad_reg (Rn);
12281 reject_bad_reg (Rm);
12282
12283 inst.instruction |= Rd << 8;
12284 inst.instruction |= Rn << 16;
12285 inst.instruction |= Rm;
62b3e311
PB		 12286}
12287
c19d1205
ZW		 12288static void
12289do_t_hint (void)
12290{
12291 if (unified_syntax && inst.size_req == 4)
12292 inst.instruction = THUMB_OP32 (inst.instruction);
12293 else
12294 inst.instruction = THUMB_OP16 (inst.instruction);
12295}
90e4755a 12296
c19d1205
ZW		 12297static void
12298do_t_it (void)
12299{
12300 unsigned int cond = inst.operands[0].imm;
e27ec89e 12301
5ee91343
AV		 12302 set_pred_insn_type (IT_INSN);
12303 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12304 now_pred.cc = cond;
12305 now_pred.warn_deprecated = FALSE;
12306 now_pred.type = SCALAR_PRED;
e27ec89e
PB		 12307
12308 /* If the condition is a negative condition, invert the mask. */
c19d1205 12309 if ((cond & 0x1) == 0x0)
90e4755a 12310 {
c19d1205 12311 unsigned int mask = inst.instruction & 0x000f;
90e4755a 12312
c19d1205 12313 if ((mask & 0x7) == 0)
5a01bb1d
MGD		 12314 {
12315 /* No conversion needed. */
5ee91343 12316 now_pred.block_length = 1;
5a01bb1d 12317 }
c19d1205 12318 else if ((mask & 0x3) == 0)
5a01bb1d
MGD		 12319 {
12320 mask ^= 0x8;
5ee91343 12321 now_pred.block_length = 2;
5a01bb1d 12322 }
e27ec89e 12323 else if ((mask & 0x1) == 0)
5a01bb1d
MGD		 12324 {
12325 mask ^= 0xC;
5ee91343 12326 now_pred.block_length = 3;
5a01bb1d 12327 }
c19d1205 12328 else
5a01bb1d
MGD		 12329 {
12330 mask ^= 0xE;
5ee91343 12331 now_pred.block_length = 4;
5a01bb1d 12332 }
90e4755a 12333
e27ec89e
PB		 12334 inst.instruction &= 0xfff0;
12335 inst.instruction |= mask;
c19d1205 12336 }
90e4755a 12337
c19d1205
ZW		 12338 inst.instruction |= cond << 4;
12339}
90e4755a 12340
3c707909
PB		 12341/* Helper function used for both push/pop and ldm/stm. */
12342static void
4b5a202f
AV		 12343encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12344 bfd_boolean writeback)
3c707909 12345{
4b5a202f 12346 bfd_boolean load, store;
3c707909 12347
4b5a202f
AV		 12348 gas_assert (base != -1 || !do_io);
12349 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12350 store = do_io && !load;
3c707909
PB		 12351
12352 if (mask & (1 << 13))
12353 inst.error = _("SP not allowed in register list");
1e5b0379 12354
4b5a202f 12355 if (do_io && (mask & (1 << base)) != 0
1e5b0379
NC		 12356 && writeback)
12357 inst.error = _("having the base register in the register list when "
12358 "using write back is UNPREDICTABLE");
12359
3c707909
PB		 12360 if (load)
12361 {
e07e6e58 12362 if (mask & (1 << 15))
477330fc
RM		 12363 {
12364 if (mask & (1 << 14))
12365 inst.error = _("LR and PC should not both be in register list");
12366 else
5ee91343 12367 set_pred_insn_type_last ();
477330fc 12368 }
3c707909 12369 }
4b5a202f 12370 else if (store)
3c707909
PB		 12371 {
12372 if (mask & (1 << 15))
12373 inst.error = _("PC not allowed in register list");
3c707909
PB		 12374 }
12375
4b5a202f 12376 if (do_io && ((mask & (mask - 1)) == 0))
3c707909
PB		 12377 {
12378 /* Single register transfers implemented as str/ldr. */
12379 if (writeback)
12380 {
12381 if (inst.instruction & (1 << 23))
12382 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12383 else
12384 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12385 }
12386 else
12387 {
12388 if (inst.instruction & (1 << 23))
12389 inst.instruction = 0x00800000; /* ia -> [base] */
12390 else
12391 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12392 }
12393
12394 inst.instruction |= 0xf8400000;
12395 if (load)
12396 inst.instruction |= 0x00100000;
12397
5f4273c7 12398 mask = ffs (mask) - 1;
3c707909
PB		 12399 mask <<= 12;
12400 }
12401 else if (writeback)
12402 inst.instruction |= WRITE_BACK;
12403
12404 inst.instruction |= mask;
4b5a202f
AV		 12405 if (do_io)
12406 inst.instruction |= base << 16;
3c707909
PB		 12407}
12408
c19d1205
ZW		 12409static void
12410do_t_ldmstm (void)
12411{
12412 /* This really doesn't seem worth it. */
e2b0ab59 12413 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205
ZW		 12414 _("expression too complex"));
12415 constraint (inst.operands[1].writeback,
12416 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 12417
c19d1205
ZW		 12418 if (unified_syntax)
12419 {
3c707909
PB		 12420 bfd_boolean narrow;
12421 unsigned mask;
12422
12423 narrow = FALSE;
c19d1205
ZW		 12424 /* See if we can use a 16-bit instruction. */
12425 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12426 && inst.size_req != 4
3c707909 12427 && !(inst.operands[1].imm & ~0xff))
90e4755a 12428 {
3c707909 12429 mask = 1 << inst.operands[0].reg;
90e4755a 12430
eab4f823 12431 if (inst.operands[0].reg <= 7)
90e4755a 12432 {
3c707909 12433 if (inst.instruction == T_MNEM_stmia
eab4f823
MGD		 12434 ? inst.operands[0].writeback
12435 : (inst.operands[0].writeback
12436 == !(inst.operands[1].imm & mask)))
477330fc 12437 {
eab4f823
MGD		 12438 if (inst.instruction == T_MNEM_stmia
12439 && (inst.operands[1].imm & mask)
12440 && (inst.operands[1].imm & (mask - 1)))
12441 as_warn (_("value stored for r%d is UNKNOWN"),
12442 inst.operands[0].reg);
3c707909 12443
eab4f823
MGD		 12444 inst.instruction = THUMB_OP16 (inst.instruction);
12445 inst.instruction |= inst.operands[0].reg << 8;
12446 inst.instruction |= inst.operands[1].imm;
12447 narrow = TRUE;
12448 }
12449 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12450 {
12451 /* This means 1 register in reg list one of 3 situations:
12452 1. Instruction is stmia, but without writeback.
12453 2. lmdia without writeback, but with Rn not in
477330fc 12454 reglist.
eab4f823
MGD		 12455 3. ldmia with writeback, but with Rn in reglist.
12456 Case 3 is UNPREDICTABLE behaviour, so we handle
12457 case 1 and 2 which can be converted into a 16-bit
12458 str or ldr. The SP cases are handled below. */
12459 unsigned long opcode;
12460 /* First, record an error for Case 3. */
12461 if (inst.operands[1].imm & mask
12462 && inst.operands[0].writeback)
fa94de6b 12463 inst.error =
eab4f823
MGD		 12464 _("having the base register in the register list when "
12465 "using write back is UNPREDICTABLE");
fa94de6b
RM		 12466
12467 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
eab4f823
MGD		 12468 : T_MNEM_ldr);
12469 inst.instruction = THUMB_OP16 (opcode);
12470 inst.instruction |= inst.operands[0].reg << 3;
12471 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12472 narrow = TRUE;
12473 }
90e4755a 12474 }
eab4f823 12475 else if (inst.operands[0] .reg == REG_SP)
90e4755a 12476 {
eab4f823
MGD		 12477 if (inst.operands[0].writeback)
12478 {
fa94de6b 12479 inst.instruction =
eab4f823 12480 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12481 ? T_MNEM_push : T_MNEM_pop);
eab4f823 12482 inst.instruction |= inst.operands[1].imm;
477330fc 12483 narrow = TRUE;
eab4f823
MGD		 12484 }
12485 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12486 {
fa94de6b 12487 inst.instruction =
eab4f823 12488 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12489 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
eab4f823 12490 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
477330fc 12491 narrow = TRUE;
eab4f823 12492 }
90e4755a 12493 }
3c707909
PB		 12494 }
12495
12496 if (!narrow)
12497 {
c19d1205
ZW		 12498 if (inst.instruction < 0xffff)
12499 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 12500
4b5a202f
AV		 12501 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12502 inst.operands[1].imm,
12503 inst.operands[0].writeback);
90e4755a
RE		 12504 }
12505 }
c19d1205 12506 else
90e4755a 12507 {
c19d1205
ZW		 12508 constraint (inst.operands[0].reg > 7
12509 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB		 12510 constraint (inst.instruction != T_MNEM_ldmia
12511 && inst.instruction != T_MNEM_stmia,
12512 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 12513 if (inst.instruction == T_MNEM_stmia)
f03698e6 12514 {
c19d1205
ZW		 12515 if (!inst.operands[0].writeback)
12516 as_warn (_("this instruction will write back the base register"));
12517 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12518 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 12519 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 12520 inst.operands[0].reg);
f03698e6 12521 }
c19d1205 12522 else
90e4755a 12523 {
c19d1205
ZW		 12524 if (!inst.operands[0].writeback
12525 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12526 as_warn (_("this instruction will write back the base register"));
12527 else if (inst.operands[0].writeback
12528 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12529 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE		 12530 }
12531
c19d1205
ZW		 12532 inst.instruction = THUMB_OP16 (inst.instruction);
12533 inst.instruction |= inst.operands[0].reg << 8;
12534 inst.instruction |= inst.operands[1].imm;
12535 }
12536}
e28cd48c 12537
c19d1205
ZW		 12538static void
12539do_t_ldrex (void)
12540{
12541 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12542 || inst.operands[1].postind || inst.operands[1].writeback
12543 || inst.operands[1].immisreg || inst.operands[1].shifted
12544 || inst.operands[1].negative,
01cfc07f 12545 BAD_ADDR_MODE);
e28cd48c 12546
5be8be5d
DG		 12547 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12548
c19d1205
ZW		 12549 inst.instruction |= inst.operands[0].reg << 12;
12550 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 12551 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
c19d1205 12552}
e28cd48c 12553
c19d1205
ZW		 12554static void
12555do_t_ldrexd (void)
12556{
12557 if (!inst.operands[1].present)
1cac9012 12558 {
c19d1205
ZW		 12559 constraint (inst.operands[0].reg == REG_LR,
12560 _("r14 not allowed as first register "
12561 "when second register is omitted"));
12562 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 12563 }
c19d1205
ZW		 12564 constraint (inst.operands[0].reg == inst.operands[1].reg,
12565 BAD_OVERLAP);
b99bd4ef 12566
c19d1205
ZW		 12567 inst.instruction |= inst.operands[0].reg << 12;
12568 inst.instruction |= inst.operands[1].reg << 8;
12569 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 12570}
12571
12572static void
c19d1205 12573do_t_ldst (void)
b99bd4ef 12574{
0110f2b8
PB		 12575 unsigned long opcode;
12576 int Rn;
12577
e07e6e58
NC		 12578 if (inst.operands[0].isreg
12579 && !inst.operands[0].preind
12580 && inst.operands[0].reg == REG_PC)
5ee91343 12581 set_pred_insn_type_last ();
e07e6e58 12582
0110f2b8 12583 opcode = inst.instruction;
c19d1205 12584 if (unified_syntax)
b99bd4ef 12585 {
53365c0d
PB		 12586 if (!inst.operands[1].isreg)
12587 {
12588 if (opcode <= 0xffff)
12589 inst.instruction = THUMB_OP32 (opcode);
8335d6aa 12590 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
53365c0d
PB		 12591 return;
12592 }
0110f2b8
PB		 12593 if (inst.operands[1].isreg
12594 && !inst.operands[1].writeback
c19d1205
ZW		 12595 && !inst.operands[1].shifted && !inst.operands[1].postind
12596 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB		 12597 && opcode <= 0xffff
12598 && inst.size_req != 4)
c19d1205 12599 {
0110f2b8
PB		 12600 /* Insn may have a 16-bit form. */
12601 Rn = inst.operands[1].reg;
12602 if (inst.operands[1].immisreg)
12603 {
12604 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 12605 /* [Rn, Rik] */
0110f2b8
PB		 12606 if (Rn <= 7 && inst.operands[1].imm <= 7)
12607 goto op16;
5be8be5d
DG		 12608 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12609 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB		 12610 }
12611 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12612 && opcode != T_MNEM_ldrsb)
12613 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12614 || (Rn == REG_SP && opcode == T_MNEM_str))
12615 {
12616 /* [Rn, #const] */
12617 if (Rn > 7)
12618 {
12619 if (Rn == REG_PC)
12620 {
e2b0ab59 12621 if (inst.relocs[0].pc_rel)
0110f2b8
PB		 12622 opcode = T_MNEM_ldr_pc2;
12623 else
12624 opcode = T_MNEM_ldr_pc;
12625 }
12626 else
12627 {
12628 if (opcode == T_MNEM_ldr)
12629 opcode = T_MNEM_ldr_sp;
12630 else
12631 opcode = T_MNEM_str_sp;
12632 }
12633 inst.instruction = inst.operands[0].reg << 8;
12634 }
12635 else
12636 {
12637 inst.instruction = inst.operands[0].reg;
12638 inst.instruction |= inst.operands[1].reg << 3;
12639 }
12640 inst.instruction |= THUMB_OP16 (opcode);
12641 if (inst.size_req == 2)
e2b0ab59 12642 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
0110f2b8
PB		 12643 else
12644 inst.relax = opcode;
12645 return;
12646 }
c19d1205 12647 }
0110f2b8 12648 /* Definitely a 32-bit variant. */
5be8be5d 12649
8d67f500
NC		 12650 /* Warning for Erratum 752419. */
12651 if (opcode == T_MNEM_ldr
12652 && inst.operands[0].reg == REG_SP
12653 && inst.operands[1].writeback == 1
12654 && !inst.operands[1].immisreg)
12655 {
12656 if (no_cpu_selected ()
12657 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
477330fc
RM		 12658 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12659 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
8d67f500
NC		 12660 as_warn (_("This instruction may be unpredictable "
12661 "if executed on M-profile cores "
12662 "with interrupts enabled."));
12663 }
12664
5be8be5d 12665 /* Do some validations regarding addressing modes. */
1be5fd2e 12666 if (inst.operands[1].immisreg)
5be8be5d
DG		 12667 reject_bad_reg (inst.operands[1].imm);
12668
1be5fd2e
NC		 12669 constraint (inst.operands[1].writeback == 1
12670 && inst.operands[0].reg == inst.operands[1].reg,
12671 BAD_OVERLAP);
12672
0110f2b8 12673 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW		 12674 inst.instruction |= inst.operands[0].reg << 12;
12675 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
1be5fd2e 12676 check_ldr_r15_aligned ();
b99bd4ef
NC		 12677 return;
12678 }
12679
c19d1205
ZW		 12680 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12681
12682 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 12683 {
c19d1205
ZW		 12684 /* Only [Rn,Rm] is acceptable. */
12685 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12686 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12687 || inst.operands[1].postind || inst.operands[1].shifted
12688 || inst.operands[1].negative,
12689 _("Thumb does not support this addressing mode"));
12690 inst.instruction = THUMB_OP16 (inst.instruction);
12691 goto op16;
b99bd4ef 12692 }
5f4273c7 12693
c19d1205
ZW		 12694 inst.instruction = THUMB_OP16 (inst.instruction);
12695 if (!inst.operands[1].isreg)
8335d6aa 12696 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
c19d1205 12697 return;
b99bd4ef 12698
c19d1205
ZW		 12699 constraint (!inst.operands[1].preind
12700 || inst.operands[1].shifted
12701 || inst.operands[1].writeback,
12702 _("Thumb does not support this addressing mode"));
12703 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 12704 {
c19d1205
ZW		 12705 constraint (inst.instruction & 0x0600,
12706 _("byte or halfword not valid for base register"));
12707 constraint (inst.operands[1].reg == REG_PC
12708 && !(inst.instruction & THUMB_LOAD_BIT),
12709 _("r15 based store not allowed"));
12710 constraint (inst.operands[1].immisreg,
12711 _("invalid base register for register offset"));
b99bd4ef 12712
c19d1205
ZW		 12713 if (inst.operands[1].reg == REG_PC)
12714 inst.instruction = T_OPCODE_LDR_PC;
12715 else if (inst.instruction & THUMB_LOAD_BIT)
12716 inst.instruction = T_OPCODE_LDR_SP;
12717 else
12718 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 12719
c19d1205 12720 inst.instruction |= inst.operands[0].reg << 8;
e2b0ab59 12721 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW		 12722 return;
12723 }
90e4755a 12724
c19d1205
ZW		 12725 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12726 if (!inst.operands[1].immisreg)
12727 {
12728 /* Immediate offset. */
12729 inst.instruction |= inst.operands[0].reg;
12730 inst.instruction |= inst.operands[1].reg << 3;
e2b0ab59 12731 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW		 12732 return;
12733 }
90e4755a 12734
c19d1205
ZW		 12735 /* Register offset. */
12736 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12737 constraint (inst.operands[1].negative,
12738 _("Thumb does not support this addressing mode"));
90e4755a 12739
c19d1205
ZW		 12740 op16:
12741 switch (inst.instruction)
12742 {
12743 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12744 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12745 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12746 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12747 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12748 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12749 case 0x5600 /* ldrsb */:
12750 case 0x5e00 /* ldrsh */: break;
12751 default: abort ();
12752 }
90e4755a 12753
c19d1205
ZW		 12754 inst.instruction |= inst.operands[0].reg;
12755 inst.instruction |= inst.operands[1].reg << 3;
12756 inst.instruction |= inst.operands[1].imm << 6;
12757}
90e4755a 12758
c19d1205
ZW		 12759static void
12760do_t_ldstd (void)
12761{
12762 if (!inst.operands[1].present)
b99bd4ef 12763 {
c19d1205
ZW		 12764 inst.operands[1].reg = inst.operands[0].reg + 1;
12765 constraint (inst.operands[0].reg == REG_LR,
12766 _("r14 not allowed here"));
bd340a04 12767 constraint (inst.operands[0].reg == REG_R12,
477330fc 12768 _("r12 not allowed here"));
b99bd4ef 12769 }
bd340a04
MGD		 12770
12771 if (inst.operands[2].writeback
12772 && (inst.operands[0].reg == inst.operands[2].reg
12773 || inst.operands[1].reg == inst.operands[2].reg))
12774 as_warn (_("base register written back, and overlaps "
477330fc 12775 "one of transfer registers"));
bd340a04 12776
c19d1205
ZW		 12777 inst.instruction |= inst.operands[0].reg << 12;
12778 inst.instruction |= inst.operands[1].reg << 8;
12779 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC		 12780}
12781
c19d1205
ZW		 12782static void
12783do_t_ldstt (void)
12784{
12785 inst.instruction |= inst.operands[0].reg << 12;
12786 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12787}
a737bd4d 12788
b99bd4ef 12789static void
c19d1205 12790do_t_mla (void)
b99bd4ef 12791{
fdfde340 12792 unsigned Rd, Rn, Rm, Ra;
c921be7d 12793
fdfde340
JM		 12794 Rd = inst.operands[0].reg;
12795 Rn = inst.operands[1].reg;
12796 Rm = inst.operands[2].reg;
12797 Ra = inst.operands[3].reg;
12798
12799 reject_bad_reg (Rd);
12800 reject_bad_reg (Rn);
12801 reject_bad_reg (Rm);
12802 reject_bad_reg (Ra);
12803
12804 inst.instruction |= Rd << 8;
12805 inst.instruction |= Rn << 16;
12806 inst.instruction |= Rm;
12807 inst.instruction |= Ra << 12;
c19d1205 12808}
b99bd4ef 12809
c19d1205
ZW		 12810static void
12811do_t_mlal (void)
12812{
fdfde340
JM		 12813 unsigned RdLo, RdHi, Rn, Rm;
12814
12815 RdLo = inst.operands[0].reg;
12816 RdHi = inst.operands[1].reg;
12817 Rn = inst.operands[2].reg;
12818 Rm = inst.operands[3].reg;
12819
12820 reject_bad_reg (RdLo);
12821 reject_bad_reg (RdHi);
12822 reject_bad_reg (Rn);
12823 reject_bad_reg (Rm);
12824
12825 inst.instruction |= RdLo << 12;
12826 inst.instruction |= RdHi << 8;
12827 inst.instruction |= Rn << 16;
12828 inst.instruction |= Rm;
c19d1205 12829}
b99bd4ef 12830
c19d1205
ZW		 12831static void
12832do_t_mov_cmp (void)
12833{
fdfde340
JM		 12834 unsigned Rn, Rm;
12835
12836 Rn = inst.operands[0].reg;
12837 Rm = inst.operands[1].reg;
12838
e07e6e58 12839 if (Rn == REG_PC)
5ee91343 12840 set_pred_insn_type_last ();
e07e6e58 12841
c19d1205 12842 if (unified_syntax)
b99bd4ef 12843 {
c19d1205
ZW		 12844 int r0off = (inst.instruction == T_MNEM_mov
12845 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 12846 unsigned long opcode;
3d388997
PB		 12847 bfd_boolean narrow;
12848 bfd_boolean low_regs;
12849
fdfde340 12850 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 12851 opcode = inst.instruction;
5ee91343 12852 if (in_pred_block ())
0110f2b8 12853 narrow = opcode != T_MNEM_movs;
3d388997 12854 else
0110f2b8 12855 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB		 12856 if (inst.size_req == 4
12857 || inst.operands[1].shifted)
12858 narrow = FALSE;
12859
efd81785
PB		 12860 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12861 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12862 && !inst.operands[1].shifted
fdfde340
JM		 12863 && Rn == REG_PC
12864 && Rm == REG_LR)
efd81785
PB		 12865 {
12866 inst.instruction = T2_SUBS_PC_LR;
12867 return;
12868 }
12869
fdfde340
JM		 12870 if (opcode == T_MNEM_cmp)
12871 {
12872 constraint (Rn == REG_PC, BAD_PC);
94206790
MM		 12873 if (narrow)
12874 {
12875 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12876 but valid. */
12877 warn_deprecated_sp (Rm);
12878 /* R15 was documented as a valid choice for Rm in ARMv6,
12879 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12880 tools reject R15, so we do too. */
12881 constraint (Rm == REG_PC, BAD_PC);
12882 }
12883 else
12884 reject_bad_reg (Rm);
fdfde340
JM		 12885 }
12886 else if (opcode == T_MNEM_mov
12887 || opcode == T_MNEM_movs)
12888 {
12889 if (inst.operands[1].isreg)
12890 {
12891 if (opcode == T_MNEM_movs)
12892 {
12893 reject_bad_reg (Rn);
12894 reject_bad_reg (Rm);
12895 }
76fa04a4
MGD		 12896 else if (narrow)
12897 {
12898 /* This is mov.n. */
12899 if ((Rn == REG_SP || Rn == REG_PC)
12900 && (Rm == REG_SP || Rm == REG_PC))
12901 {
5c3696f8 12902 as_tsktsk (_("Use of r%u as a source register is "
76fa04a4
MGD		 12903 "deprecated when r%u is the destination "
12904 "register."), Rm, Rn);
12905 }
12906 }
12907 else
12908 {
12909 /* This is mov.w. */
12910 constraint (Rn == REG_PC, BAD_PC);
12911 constraint (Rm == REG_PC, BAD_PC);
5c8ed6a4
JW		 12912 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12913 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
76fa04a4 12914 }
fdfde340
JM		 12915 }
12916 else
12917 reject_bad_reg (Rn);
12918 }
12919
c19d1205
ZW		 12920 if (!inst.operands[1].isreg)
12921 {
0110f2b8 12922 /* Immediate operand. */
5ee91343 12923 if (!in_pred_block () && opcode == T_MNEM_mov)
0110f2b8
PB		 12924 narrow = 0;
12925 if (low_regs && narrow)
12926 {
12927 inst.instruction = THUMB_OP16 (opcode);
fdfde340 12928 inst.instruction |= Rn << 8;
e2b0ab59
AV		 12929 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12930 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
72d98d16 12931 {
a9f02af8 12932 if (inst.size_req == 2)
e2b0ab59 12933 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
a9f02af8
MG		 12934 else
12935 inst.relax = opcode;
72d98d16 12936 }
0110f2b8
PB		 12937 }
12938 else
12939 {
e2b0ab59
AV		 12940 constraint ((inst.relocs[0].type
12941 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
12942 && (inst.relocs[0].type
12943 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8
MG		 12944 THUMB1_RELOC_ONLY);
12945
0110f2b8
PB		 12946 inst.instruction = THUMB_OP32 (inst.instruction);
12947 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 12948 inst.instruction |= Rn << r0off;
e2b0ab59 12949 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8 12950 }
c19d1205 12951 }
728ca7c9
PB		 12952 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12953 && (inst.instruction == T_MNEM_mov
12954 || inst.instruction == T_MNEM_movs))
12955 {
12956 /* Register shifts are encoded as separate shift instructions. */
12957 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
12958
5ee91343 12959 if (in_pred_block ())
728ca7c9
PB		 12960 narrow = !flags;
12961 else
12962 narrow = flags;
12963
12964 if (inst.size_req == 4)
12965 narrow = FALSE;
12966
12967 if (!low_regs || inst.operands[1].imm > 7)
12968 narrow = FALSE;
12969
fdfde340 12970 if (Rn != Rm)
728ca7c9
PB		 12971 narrow = FALSE;
12972
12973 switch (inst.operands[1].shift_kind)
12974 {
12975 case SHIFT_LSL:
12976 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
12977 break;
12978 case SHIFT_ASR:
12979 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
12980 break;
12981 case SHIFT_LSR:
12982 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
12983 break;
12984 case SHIFT_ROR:
12985 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
12986 break;
12987 default:
5f4273c7 12988 abort ();
728ca7c9
PB		 12989 }
12990
12991 inst.instruction = opcode;
12992 if (narrow)
12993 {
fdfde340 12994 inst.instruction |= Rn;
728ca7c9
PB		 12995 inst.instruction |= inst.operands[1].imm << 3;
12996 }
12997 else
12998 {
12999 if (flags)
13000 inst.instruction |= CONDS_BIT;
13001
fdfde340
JM		 13002 inst.instruction |= Rn << 8;
13003 inst.instruction |= Rm << 16;
728ca7c9
PB		 13004 inst.instruction |= inst.operands[1].imm;
13005 }
13006 }
3d388997 13007 else if (!narrow)
c19d1205 13008 {
728ca7c9
PB		 13009 /* Some mov with immediate shift have narrow variants.
13010 Register shifts are handled above. */
13011 if (low_regs && inst.operands[1].shifted
13012 && (inst.instruction == T_MNEM_mov
13013 || inst.instruction == T_MNEM_movs))
13014 {
5ee91343 13015 if (in_pred_block ())
728ca7c9
PB		 13016 narrow = (inst.instruction == T_MNEM_mov);
13017 else
13018 narrow = (inst.instruction == T_MNEM_movs);
13019 }
13020
13021 if (narrow)
13022 {
13023 switch (inst.operands[1].shift_kind)
13024 {
13025 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13026 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13027 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13028 default: narrow = FALSE; break;
13029 }
13030 }
13031
13032 if (narrow)
13033 {
fdfde340
JM		 13034 inst.instruction |= Rn;
13035 inst.instruction |= Rm << 3;
e2b0ab59 13036 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
728ca7c9
PB		 13037 }
13038 else
13039 {
13040 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 13041 inst.instruction |= Rn << r0off;
728ca7c9
PB		 13042 encode_thumb32_shifted_operand (1);
13043 }
c19d1205
ZW		 13044 }
13045 else
13046 switch (inst.instruction)
13047 {
13048 case T_MNEM_mov:
837b3435 13049 /* In v4t or v5t a move of two lowregs produces unpredictable
c6400f8a
MGD		 13050 results. Don't allow this. */
13051 if (low_regs)
13052 {
13053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
13054 "MOV Rd, Rs with two low registers is not "
13055 "permitted on this architecture");
fa94de6b 13056 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
c6400f8a
MGD		 13057 arm_ext_v6);
13058 }
13059
c19d1205 13060 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM		 13061 inst.instruction |= (Rn & 0x8) << 4;
13062 inst.instruction |= (Rn & 0x7);
13063 inst.instruction |= Rm << 3;
c19d1205 13064 break;
b99bd4ef 13065
c19d1205
ZW		 13066 case T_MNEM_movs:
13067 /* We know we have low registers at this point.
941a8a52
MGD		 13068 Generate LSLS Rd, Rs, #0. */
13069 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM		 13070 inst.instruction |= Rn;
13071 inst.instruction |= Rm << 3;
c19d1205
ZW		 13072 break;
13073
13074 case T_MNEM_cmp:
3d388997 13075 if (low_regs)
c19d1205
ZW		 13076 {
13077 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM		 13078 inst.instruction |= Rn;
13079 inst.instruction |= Rm << 3;
c19d1205
ZW		 13080 }
13081 else
13082 {
13083 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM		 13084 inst.instruction |= (Rn & 0x8) << 4;
13085 inst.instruction |= (Rn & 0x7);
13086 inst.instruction |= Rm << 3;
c19d1205
ZW		 13087 }
13088 break;
13089 }
b99bd4ef
NC		 13090 return;
13091 }
13092
c19d1205 13093 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC		 13094
13095 /* PR 10443: Do not silently ignore shifted operands. */
13096 constraint (inst.operands[1].shifted,
13097 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13098
c19d1205 13099 if (inst.operands[1].isreg)
b99bd4ef 13100 {
fdfde340 13101 if (Rn < 8 && Rm < 8)
b99bd4ef 13102 {
c19d1205
ZW		 13103 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13104 since a MOV instruction produces unpredictable results. */
13105 if (inst.instruction == T_OPCODE_MOV_I8)
13106 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 13107 else
c19d1205 13108 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 13109
fdfde340
JM		 13110 inst.instruction |= Rn;
13111 inst.instruction |= Rm << 3;
b99bd4ef
NC		 13112 }
13113 else
13114 {
c19d1205
ZW		 13115 if (inst.instruction == T_OPCODE_MOV_I8)
13116 inst.instruction = T_OPCODE_MOV_HR;
13117 else
13118 inst.instruction = T_OPCODE_CMP_HR;
13119 do_t_cpy ();
b99bd4ef
NC		 13120 }
13121 }
c19d1205 13122 else
b99bd4ef 13123 {
fdfde340 13124 constraint (Rn > 7,
c19d1205 13125 _("only lo regs allowed with immediate"));
fdfde340 13126 inst.instruction |= Rn << 8;
e2b0ab59 13127 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
c19d1205
ZW		 13128 }
13129}
b99bd4ef 13130
c19d1205
ZW		 13131static void
13132do_t_mov16 (void)
13133{
fdfde340 13134 unsigned Rd;
b6895b4f
PB		 13135 bfd_vma imm;
13136 bfd_boolean top;
13137
13138 top = (inst.instruction & 0x00800000) != 0;
e2b0ab59 13139 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
b6895b4f 13140 {
33eaf5de 13141 constraint (top, _(":lower16: not allowed in this instruction"));
e2b0ab59 13142 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
b6895b4f 13143 }
e2b0ab59 13144 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
b6895b4f 13145 {
33eaf5de 13146 constraint (!top, _(":upper16: not allowed in this instruction"));
e2b0ab59 13147 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
b6895b4f
PB		 13148 }
13149
fdfde340
JM		 13150 Rd = inst.operands[0].reg;
13151 reject_bad_reg (Rd);
13152
13153 inst.instruction |= Rd << 8;
e2b0ab59 13154 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 13155 {
e2b0ab59 13156 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB		 13157 inst.instruction |= (imm & 0xf000) << 4;
13158 inst.instruction |= (imm & 0x0800) << 15;
13159 inst.instruction |= (imm & 0x0700) << 4;
13160 inst.instruction |= (imm & 0x00ff);
13161 }
c19d1205 13162}
b99bd4ef 13163
c19d1205
ZW		 13164static void
13165do_t_mvn_tst (void)
13166{
fdfde340 13167 unsigned Rn, Rm;
c921be7d 13168
fdfde340
JM		 13169 Rn = inst.operands[0].reg;
13170 Rm = inst.operands[1].reg;
13171
13172 if (inst.instruction == T_MNEM_cmp
13173 || inst.instruction == T_MNEM_cmn)
13174 constraint (Rn == REG_PC, BAD_PC);
13175 else
13176 reject_bad_reg (Rn);
13177 reject_bad_reg (Rm);
13178
c19d1205
ZW		 13179 if (unified_syntax)
13180 {
13181 int r0off = (inst.instruction == T_MNEM_mvn
13182 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB		 13183 bfd_boolean narrow;
13184
13185 if (inst.size_req == 4
13186 || inst.instruction > 0xffff
13187 || inst.operands[1].shifted
fdfde340 13188 || Rn > 7 || Rm > 7)
3d388997 13189 narrow = FALSE;
fe8b4cc3
KT		 13190 else if (inst.instruction == T_MNEM_cmn
13191 || inst.instruction == T_MNEM_tst)
3d388997
PB		 13192 narrow = TRUE;
13193 else if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13194 narrow = !in_pred_block ();
3d388997 13195 else
5ee91343 13196 narrow = in_pred_block ();
3d388997 13197
c19d1205 13198 if (!inst.operands[1].isreg)
b99bd4ef 13199 {
c19d1205
ZW		 13200 /* For an immediate, we always generate a 32-bit opcode;
13201 section relaxation will shrink it later if possible. */
13202 if (inst.instruction < 0xffff)
13203 inst.instruction = THUMB_OP32 (inst.instruction);
13204 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 13205 inst.instruction |= Rn << r0off;
e2b0ab59 13206 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 13207 }
c19d1205 13208 else
b99bd4ef 13209 {
c19d1205 13210 /* See if we can do this with a 16-bit instruction. */
3d388997 13211 if (narrow)
b99bd4ef 13212 {
c19d1205 13213 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13214 inst.instruction |= Rn;
13215 inst.instruction |= Rm << 3;
b99bd4ef 13216 }
c19d1205 13217 else
b99bd4ef 13218 {
c19d1205
ZW		 13219 constraint (inst.operands[1].shifted
13220 && inst.operands[1].immisreg,
13221 _("shift must be constant"));
13222 if (inst.instruction < 0xffff)
13223 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 13224 inst.instruction |= Rn << r0off;
c19d1205 13225 encode_thumb32_shifted_operand (1);
b99bd4ef 13226 }
b99bd4ef
NC		 13227 }
13228 }
13229 else
13230 {
c19d1205
ZW		 13231 constraint (inst.instruction > 0xffff
13232 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13233 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13234 _("unshifted register required"));
fdfde340 13235 constraint (Rn > 7 || Rm > 7,
c19d1205 13236 BAD_HIREG);
b99bd4ef 13237
c19d1205 13238 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13239 inst.instruction |= Rn;
13240 inst.instruction |= Rm << 3;
b99bd4ef 13241 }
b99bd4ef
NC		 13242}
13243
b05fe5cf 13244static void
c19d1205 13245do_t_mrs (void)
b05fe5cf 13246{
fdfde340 13247 unsigned Rd;
037e8744
JB		 13248
13249 if (do_vfp_nsyn_mrs () == SUCCESS)
13250 return;
13251
90ec0d68
MGD		 13252 Rd = inst.operands[0].reg;
13253 reject_bad_reg (Rd);
13254 inst.instruction |= Rd << 8;
13255
13256 if (inst.operands[1].isreg)
62b3e311 13257 {
90ec0d68
MGD		 13258 unsigned br = inst.operands[1].reg;
13259 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
13260 as_bad (_("bad register for mrs"));
13261
13262 inst.instruction |= br & (0xf << 16);
13263 inst.instruction |= (br & 0x300) >> 4;
13264 inst.instruction |= (br & SPSR_BIT) >> 2;
62b3e311
PB		 13265 }
13266 else
13267 {
90ec0d68 13268 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
5f4273c7 13269
d2cd1205 13270 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
1a43faaf
NC		 13271 {
13272 /* PR gas/12698: The constraint is only applied for m_profile.
13273 If the user has specified -march=all, we want to ignore it as
13274 we are building for any CPU type, including non-m variants. */
823d2571
TG		 13275 bfd_boolean m_profile =
13276 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf
NC		 13277 constraint ((flags != 0) && m_profile, _("selected processor does "
13278 "not support requested special purpose register"));
13279 }
90ec0d68 13280 else
d2cd1205
JB		 13281 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13282 devices). */
13283 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13284 _("'APSR', 'CPSR' or 'SPSR' expected"));
fdfde340 13285
90ec0d68
MGD		 13286 inst.instruction |= (flags & SPSR_BIT) >> 2;
13287 inst.instruction |= inst.operands[1].imm & 0xff;
13288 inst.instruction |= 0xf0000;
13289 }
c19d1205 13290}
b05fe5cf 13291
c19d1205
ZW		 13292static void
13293do_t_msr (void)
13294{
62b3e311 13295 int flags;
fdfde340 13296 unsigned Rn;
62b3e311 13297
037e8744
JB		 13298 if (do_vfp_nsyn_msr () == SUCCESS)
13299 return;
13300
c19d1205
ZW		 13301 constraint (!inst.operands[1].isreg,
13302 _("Thumb encoding does not support an immediate here"));
90ec0d68
MGD		 13303
13304 if (inst.operands[0].isreg)
13305 flags = (int)(inst.operands[0].reg);
13306 else
13307 flags = inst.operands[0].imm;
13308
d2cd1205 13309 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
62b3e311 13310 {
d2cd1205
JB		 13311 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13312
1a43faaf 13313 /* PR gas/12698: The constraint is only applied for m_profile.
477330fc
RM		 13314 If the user has specified -march=all, we want to ignore it as
13315 we are building for any CPU type, including non-m variants. */
823d2571
TG		 13316 bfd_boolean m_profile =
13317 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf 13318 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
477330fc
RM		 13319 && (bits & ~(PSR_s | PSR_f)) != 0)
13320 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13321 && bits != PSR_f)) && m_profile,
13322 _("selected processor does not support requested special "
13323 "purpose register"));
62b3e311
PB		 13324 }
13325 else
d2cd1205
JB		 13326 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13327 "requested special purpose register"));
c921be7d 13328
fdfde340
JM		 13329 Rn = inst.operands[1].reg;
13330 reject_bad_reg (Rn);
13331
62b3e311 13332 inst.instruction |= (flags & SPSR_BIT) >> 2;
90ec0d68
MGD		 13333 inst.instruction |= (flags & 0xf0000) >> 8;
13334 inst.instruction |= (flags & 0x300) >> 4;
62b3e311 13335 inst.instruction |= (flags & 0xff);
fdfde340 13336 inst.instruction |= Rn << 16;
c19d1205 13337}
b05fe5cf 13338
c19d1205
ZW		 13339static void
13340do_t_mul (void)
13341{
17828f45 13342 bfd_boolean narrow;
fdfde340 13343 unsigned Rd, Rn, Rm;
17828f45 13344
c19d1205
ZW		 13345 if (!inst.operands[2].present)
13346 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 13347
fdfde340
JM		 13348 Rd = inst.operands[0].reg;
13349 Rn = inst.operands[1].reg;
13350 Rm = inst.operands[2].reg;
13351
17828f45 13352 if (unified_syntax)
b05fe5cf 13353 {
17828f45 13354 if (inst.size_req == 4
fdfde340
JM		 13355 || (Rd != Rn
13356 && Rd != Rm)
13357 || Rn > 7
13358 || Rm > 7)
17828f45
JM		 13359 narrow = FALSE;
13360 else if (inst.instruction == T_MNEM_muls)
5ee91343 13361 narrow = !in_pred_block ();
17828f45 13362 else
5ee91343 13363 narrow = in_pred_block ();
b05fe5cf 13364 }
c19d1205 13365 else
b05fe5cf 13366 {
17828f45 13367 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 13368 constraint (Rn > 7 || Rm > 7,
c19d1205 13369 BAD_HIREG);
17828f45
JM		 13370 narrow = TRUE;
13371 }
b05fe5cf 13372
17828f45
JM		 13373 if (narrow)
13374 {
13375 /* 16-bit MULS/Conditional MUL. */
c19d1205 13376 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 13377 inst.instruction |= Rd;
b05fe5cf 13378
fdfde340
JM		 13379 if (Rd == Rn)
13380 inst.instruction |= Rm << 3;
13381 else if (Rd == Rm)
13382 inst.instruction |= Rn << 3;
c19d1205
ZW		 13383 else
13384 constraint (1, _("dest must overlap one source register"));
13385 }
17828f45
JM		 13386 else
13387 {
e07e6e58
NC		 13388 constraint (inst.instruction != T_MNEM_mul,
13389 _("Thumb-2 MUL must not set flags"));
17828f45
JM		 13390 /* 32-bit MUL. */
13391 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 13392 inst.instruction |= Rd << 8;
13393 inst.instruction |= Rn << 16;
13394 inst.instruction |= Rm << 0;
13395
13396 reject_bad_reg (Rd);
13397 reject_bad_reg (Rn);
13398 reject_bad_reg (Rm);
17828f45 13399 }
c19d1205 13400}
b05fe5cf 13401
c19d1205
ZW		 13402static void
13403do_t_mull (void)
13404{
fdfde340 13405 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 13406
fdfde340
JM		 13407 RdLo = inst.operands[0].reg;
13408 RdHi = inst.operands[1].reg;
13409 Rn = inst.operands[2].reg;
13410 Rm = inst.operands[3].reg;
13411
13412 reject_bad_reg (RdLo);
13413 reject_bad_reg (RdHi);
13414 reject_bad_reg (Rn);
13415 reject_bad_reg (Rm);
13416
13417 inst.instruction |= RdLo << 12;
13418 inst.instruction |= RdHi << 8;
13419 inst.instruction |= Rn << 16;
13420 inst.instruction |= Rm;
13421
13422 if (RdLo == RdHi)
c19d1205
ZW		 13423 as_tsktsk (_("rdhi and rdlo must be different"));
13424}
b05fe5cf 13425
c19d1205
ZW		 13426static void
13427do_t_nop (void)
13428{
5ee91343 13429 set_pred_insn_type (NEUTRAL_IT_INSN);
e07e6e58 13430
c19d1205
ZW		 13431 if (unified_syntax)
13432 {
13433 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 13434 {
c19d1205
ZW		 13435 inst.instruction = THUMB_OP32 (inst.instruction);
13436 inst.instruction |= inst.operands[0].imm;
13437 }
13438 else
13439 {
bc2d1808
NC		 13440 /* PR9722: Check for Thumb2 availability before
13441 generating a thumb2 nop instruction. */
afa62d5e 13442 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC		 13443 {
13444 inst.instruction = THUMB_OP16 (inst.instruction);
13445 inst.instruction |= inst.operands[0].imm << 4;
13446 }
13447 else
13448 inst.instruction = 0x46c0;
c19d1205
ZW		 13449 }
13450 }
13451 else
13452 {
13453 constraint (inst.operands[0].present,
13454 _("Thumb does not support NOP with hints"));
13455 inst.instruction = 0x46c0;
13456 }
13457}
b05fe5cf 13458
c19d1205
ZW		 13459static void
13460do_t_neg (void)
13461{
13462 if (unified_syntax)
13463 {
3d388997
PB		 13464 bfd_boolean narrow;
13465
13466 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13467 narrow = !in_pred_block ();
3d388997 13468 else
5ee91343 13469 narrow = in_pred_block ();
3d388997
PB		 13470 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13471 narrow = FALSE;
13472 if (inst.size_req == 4)
13473 narrow = FALSE;
13474
13475 if (!narrow)
c19d1205
ZW		 13476 {
13477 inst.instruction = THUMB_OP32 (inst.instruction);
13478 inst.instruction |= inst.operands[0].reg << 8;
13479 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW		 13480 }
13481 else
13482 {
c19d1205
ZW		 13483 inst.instruction = THUMB_OP16 (inst.instruction);
13484 inst.instruction |= inst.operands[0].reg;
13485 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW		 13486 }
13487 }
13488 else
13489 {
c19d1205
ZW		 13490 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13491 BAD_HIREG);
13492 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13493
13494 inst.instruction = THUMB_OP16 (inst.instruction);
13495 inst.instruction |= inst.operands[0].reg;
13496 inst.instruction |= inst.operands[1].reg << 3;
13497 }
13498}
13499
1c444d06
JM		 13500static void
13501do_t_orn (void)
13502{
13503 unsigned Rd, Rn;
13504
13505 Rd = inst.operands[0].reg;
13506 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13507
fdfde340
JM		 13508 reject_bad_reg (Rd);
13509 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13510 reject_bad_reg (Rn);
13511
1c444d06
JM		 13512 inst.instruction |= Rd << 8;
13513 inst.instruction |= Rn << 16;
13514
13515 if (!inst.operands[2].isreg)
13516 {
13517 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13518 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
1c444d06
JM		 13519 }
13520 else
13521 {
13522 unsigned Rm;
13523
13524 Rm = inst.operands[2].reg;
fdfde340 13525 reject_bad_reg (Rm);
1c444d06
JM		 13526
13527 constraint (inst.operands[2].shifted
13528 && inst.operands[2].immisreg,
13529 _("shift must be constant"));
13530 encode_thumb32_shifted_operand (2);
13531 }
13532}
13533
c19d1205
ZW		 13534static void
13535do_t_pkhbt (void)
13536{
fdfde340
JM		 13537 unsigned Rd, Rn, Rm;
13538
13539 Rd = inst.operands[0].reg;
13540 Rn = inst.operands[1].reg;
13541 Rm = inst.operands[2].reg;
13542
13543 reject_bad_reg (Rd);
13544 reject_bad_reg (Rn);
13545 reject_bad_reg (Rm);
13546
13547 inst.instruction |= Rd << 8;
13548 inst.instruction |= Rn << 16;
13549 inst.instruction |= Rm;
c19d1205
ZW		 13550 if (inst.operands[3].present)
13551 {
e2b0ab59
AV		 13552 unsigned int val = inst.relocs[0].exp.X_add_number;
13553 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW		 13554 _("expression too complex"));
13555 inst.instruction |= (val & 0x1c) << 10;
13556 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 13557 }
c19d1205 13558}
b05fe5cf 13559
c19d1205
ZW		 13560static void
13561do_t_pkhtb (void)
13562{
13563 if (!inst.operands[3].present)
1ef52f49
NC		 13564 {
13565 unsigned Rtmp;
13566
13567 inst.instruction &= ~0x00000020;
13568
13569 /* PR 10168. Swap the Rm and Rn registers. */
13570 Rtmp = inst.operands[1].reg;
13571 inst.operands[1].reg = inst.operands[2].reg;
13572 inst.operands[2].reg = Rtmp;
13573 }
c19d1205 13574 do_t_pkhbt ();
b05fe5cf
ZW		 13575}
13576
c19d1205
ZW		 13577static void
13578do_t_pld (void)
13579{
fdfde340
JM		 13580 if (inst.operands[0].immisreg)
13581 reject_bad_reg (inst.operands[0].imm);
13582
c19d1205
ZW		 13583 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13584}
b05fe5cf 13585
c19d1205
ZW		 13586static void
13587do_t_push_pop (void)
b99bd4ef 13588{
e9f89963 13589 unsigned mask;
5f4273c7 13590
c19d1205
ZW		 13591 constraint (inst.operands[0].writeback,
13592 _("push/pop do not support {reglist}^"));
e2b0ab59 13593 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205 13594 _("expression too complex"));
b99bd4ef 13595
e9f89963 13596 mask = inst.operands[0].imm;
d3bfe16e 13597 if (inst.size_req != 4 && (mask & ~0xff) == 0)
3c707909 13598 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
d3bfe16e 13599 else if (inst.size_req != 4
c6025a80 13600 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
d3bfe16e 13601 ? REG_LR : REG_PC)))
b99bd4ef 13602 {
c19d1205
ZW		 13603 inst.instruction = THUMB_OP16 (inst.instruction);
13604 inst.instruction |= THUMB_PP_PC_LR;
3c707909 13605 inst.instruction |= mask & 0xff;
c19d1205
ZW		 13606 }
13607 else if (unified_syntax)
13608 {
3c707909 13609 inst.instruction = THUMB_OP32 (inst.instruction);
4b5a202f
AV		 13610 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13611 }
13612 else
13613 {
13614 inst.error = _("invalid register list to push/pop instruction");
13615 return;
c19d1205 13616 }
4b5a202f
AV		 13617}
13618
13619static void
13620do_t_clrm (void)
13621{
13622 if (unified_syntax)
13623 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
c19d1205
ZW		 13624 else
13625 {
13626 inst.error = _("invalid register list to push/pop instruction");
13627 return;
13628 }
c19d1205 13629}
b99bd4ef 13630
efd6b359
AV		 13631static void
13632do_t_vscclrm (void)
13633{
13634 if (inst.operands[0].issingle)
13635 {
13636 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13637 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13638 inst.instruction |= inst.operands[0].imm;
13639 }
13640 else
13641 {
13642 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13643 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13644 inst.instruction |= 1 << 8;
13645 inst.instruction |= inst.operands[0].imm << 1;
13646 }
13647}
13648
c19d1205
ZW		 13649static void
13650do_t_rbit (void)
13651{
fdfde340
JM		 13652 unsigned Rd, Rm;
13653
13654 Rd = inst.operands[0].reg;
13655 Rm = inst.operands[1].reg;
13656
13657 reject_bad_reg (Rd);
13658 reject_bad_reg (Rm);
13659
13660 inst.instruction |= Rd << 8;
13661 inst.instruction |= Rm << 16;
13662 inst.instruction |= Rm;
c19d1205 13663}
b99bd4ef 13664
c19d1205
ZW		 13665static void
13666do_t_rev (void)
13667{
fdfde340
JM		 13668 unsigned Rd, Rm;
13669
13670 Rd = inst.operands[0].reg;
13671 Rm = inst.operands[1].reg;
13672
13673 reject_bad_reg (Rd);
13674 reject_bad_reg (Rm);
13675
13676 if (Rd <= 7 && Rm <= 7
c19d1205
ZW		 13677 && inst.size_req != 4)
13678 {
13679 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13680 inst.instruction |= Rd;
13681 inst.instruction |= Rm << 3;
c19d1205
ZW		 13682 }
13683 else if (unified_syntax)
13684 {
13685 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 13686 inst.instruction |= Rd << 8;
13687 inst.instruction |= Rm << 16;
13688 inst.instruction |= Rm;
c19d1205
ZW		 13689 }
13690 else
13691 inst.error = BAD_HIREG;
13692}
b99bd4ef 13693
1c444d06
JM		 13694static void
13695do_t_rrx (void)
13696{
13697 unsigned Rd, Rm;
13698
13699 Rd = inst.operands[0].reg;
13700 Rm = inst.operands[1].reg;
13701
fdfde340
JM		 13702 reject_bad_reg (Rd);
13703 reject_bad_reg (Rm);
c921be7d 13704
1c444d06
JM		 13705 inst.instruction |= Rd << 8;
13706 inst.instruction |= Rm;
13707}
13708
c19d1205
ZW		 13709static void
13710do_t_rsb (void)
13711{
fdfde340 13712 unsigned Rd, Rs;
b99bd4ef 13713
c19d1205
ZW		 13714 Rd = inst.operands[0].reg;
13715 Rs = (inst.operands[1].present
13716 ? inst.operands[1].reg /* Rd, Rs, foo */
13717 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 13718
fdfde340
JM		 13719 reject_bad_reg (Rd);
13720 reject_bad_reg (Rs);
13721 if (inst.operands[2].isreg)
13722 reject_bad_reg (inst.operands[2].reg);
13723
c19d1205
ZW		 13724 inst.instruction |= Rd << 8;
13725 inst.instruction |= Rs << 16;
13726 if (!inst.operands[2].isreg)
13727 {
026d3abb
PB		 13728 bfd_boolean narrow;
13729
13730 if ((inst.instruction & 0x00100000) != 0)
5ee91343 13731 narrow = !in_pred_block ();
026d3abb 13732 else
5ee91343 13733 narrow = in_pred_block ();
026d3abb
PB		 13734
13735 if (Rd > 7 || Rs > 7)
13736 narrow = FALSE;
13737
13738 if (inst.size_req == 4 || !unified_syntax)
13739 narrow = FALSE;
13740
e2b0ab59
AV		 13741 if (inst.relocs[0].exp.X_op != O_constant
13742 || inst.relocs[0].exp.X_add_number != 0)
026d3abb
PB		 13743 narrow = FALSE;
13744
13745 /* Turn rsb #0 into 16-bit neg. We should probably do this via
477330fc 13746 relaxation, but it doesn't seem worth the hassle. */
026d3abb
PB		 13747 if (narrow)
13748 {
e2b0ab59 13749 inst.relocs[0].type = BFD_RELOC_UNUSED;
026d3abb
PB		 13750 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13751 inst.instruction |= Rs << 3;
13752 inst.instruction |= Rd;
13753 }
13754 else
13755 {
13756 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13757 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
026d3abb 13758 }
c19d1205
ZW		 13759 }
13760 else
13761 encode_thumb32_shifted_operand (2);
13762}
b99bd4ef 13763
c19d1205
ZW		 13764static void
13765do_t_setend (void)
13766{
12e37cbc
MGD		 13767 if (warn_on_deprecated
13768 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 13769 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 13770
5ee91343 13771 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW		 13772 if (inst.operands[0].imm)
13773 inst.instruction |= 0x8;
13774}
b99bd4ef 13775
c19d1205
ZW		 13776static void
13777do_t_shift (void)
13778{
13779 if (!inst.operands[1].present)
13780 inst.operands[1].reg = inst.operands[0].reg;
13781
13782 if (unified_syntax)
13783 {
3d388997
PB		 13784 bfd_boolean narrow;
13785 int shift_kind;
13786
13787 switch (inst.instruction)
13788 {
13789 case T_MNEM_asr:
13790 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13791 case T_MNEM_lsl:
13792 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13793 case T_MNEM_lsr:
13794 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13795 case T_MNEM_ror:
13796 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13797 default: abort ();
13798 }
13799
13800 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13801 narrow = !in_pred_block ();
3d388997 13802 else
5ee91343 13803 narrow = in_pred_block ();
3d388997
PB		 13804 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13805 narrow = FALSE;
13806 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13807 narrow = FALSE;
13808 if (inst.operands[2].isreg
13809 && (inst.operands[1].reg != inst.operands[0].reg
13810 || inst.operands[2].reg > 7))
13811 narrow = FALSE;
13812 if (inst.size_req == 4)
13813 narrow = FALSE;
13814
fdfde340
JM		 13815 reject_bad_reg (inst.operands[0].reg);
13816 reject_bad_reg (inst.operands[1].reg);
c921be7d 13817
3d388997 13818 if (!narrow)
c19d1205
ZW		 13819 {
13820 if (inst.operands[2].isreg)
b99bd4ef 13821 {
fdfde340 13822 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW		 13823 inst.instruction = THUMB_OP32 (inst.instruction);
13824 inst.instruction |= inst.operands[0].reg << 8;
13825 inst.instruction |= inst.operands[1].reg << 16;
13826 inst.instruction |= inst.operands[2].reg;
94342ec3
NC		 13827
13828 /* PR 12854: Error on extraneous shifts. */
13829 constraint (inst.operands[2].shifted,
13830 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 13831 }
13832 else
13833 {
13834 inst.operands[1].shifted = 1;
3d388997 13835 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW		 13836 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13837 ? T_MNEM_movs : T_MNEM_mov);
13838 inst.instruction |= inst.operands[0].reg << 8;
13839 encode_thumb32_shifted_operand (1);
13840 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
e2b0ab59 13841 inst.relocs[0].type = BFD_RELOC_UNUSED;
b99bd4ef
NC		 13842 }
13843 }
13844 else
13845 {
c19d1205 13846 if (inst.operands[2].isreg)
b99bd4ef 13847 {
3d388997 13848 switch (shift_kind)
b99bd4ef 13849 {
3d388997
PB		 13850 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13851 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13852 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13853 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 13854 default: abort ();
b99bd4ef 13855 }
5f4273c7 13856
c19d1205
ZW		 13857 inst.instruction |= inst.operands[0].reg;
13858 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 13859
13860 /* PR 12854: Error on extraneous shifts. */
13861 constraint (inst.operands[2].shifted,
13862 _("extraneous shift as part of operand to shift insn"));
b99bd4ef
NC		 13863 }
13864 else
13865 {
3d388997 13866 switch (shift_kind)
b99bd4ef 13867 {
3d388997
PB		 13868 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13869 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13870 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 13871 default: abort ();
b99bd4ef 13872 }
e2b0ab59 13873 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW		 13874 inst.instruction |= inst.operands[0].reg;
13875 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 13876 }
13877 }
c19d1205
ZW		 13878 }
13879 else
13880 {
13881 constraint (inst.operands[0].reg > 7
13882 || inst.operands[1].reg > 7, BAD_HIREG);
13883 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 13884
c19d1205
ZW		 13885 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13886 {
13887 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13888 constraint (inst.operands[0].reg != inst.operands[1].reg,
13889 _("source1 and dest must be same register"));
b99bd4ef 13890
c19d1205
ZW		 13891 switch (inst.instruction)
13892 {
13893 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13894 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13895 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13896 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13897 default: abort ();
13898 }
5f4273c7 13899
c19d1205
ZW		 13900 inst.instruction |= inst.operands[0].reg;
13901 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 13902
13903 /* PR 12854: Error on extraneous shifts. */
13904 constraint (inst.operands[2].shifted,
13905 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 13906 }
13907 else
b99bd4ef 13908 {
c19d1205
ZW		 13909 switch (inst.instruction)
13910 {
13911 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13912 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13913 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13914 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13915 default: abort ();
13916 }
e2b0ab59 13917 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW		 13918 inst.instruction |= inst.operands[0].reg;
13919 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 13920 }
13921 }
b99bd4ef
NC		 13922}
13923
13924static void
c19d1205 13925do_t_simd (void)
b99bd4ef 13926{
fdfde340
JM		 13927 unsigned Rd, Rn, Rm;
13928
13929 Rd = inst.operands[0].reg;
13930 Rn = inst.operands[1].reg;
13931 Rm = inst.operands[2].reg;
13932
13933 reject_bad_reg (Rd);
13934 reject_bad_reg (Rn);
13935 reject_bad_reg (Rm);
13936
13937 inst.instruction |= Rd << 8;
13938 inst.instruction |= Rn << 16;
13939 inst.instruction |= Rm;
c19d1205 13940}
b99bd4ef 13941
03ee1b7f
NC		 13942static void
13943do_t_simd2 (void)
13944{
13945 unsigned Rd, Rn, Rm;
13946
13947 Rd = inst.operands[0].reg;
13948 Rm = inst.operands[1].reg;
13949 Rn = inst.operands[2].reg;
13950
13951 reject_bad_reg (Rd);
13952 reject_bad_reg (Rn);
13953 reject_bad_reg (Rm);
13954
13955 inst.instruction |= Rd << 8;
13956 inst.instruction |= Rn << 16;
13957 inst.instruction |= Rm;
13958}
13959
c19d1205 13960static void
3eb17e6b 13961do_t_smc (void)
c19d1205 13962{
e2b0ab59 13963 unsigned int value = inst.relocs[0].exp.X_add_number;
f4c65163
MGD		 13964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
13965 _("SMC is not permitted on this architecture"));
e2b0ab59 13966 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 13967 _("expression too complex"));
ba85f98c
BW		 13968 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
13969
e2b0ab59 13970 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205 13971 inst.instruction |= (value & 0x000f) << 16;
ba85f98c 13972
24382199 13973 /* PR gas/15623: SMC instructions must be last in an IT block. */
5ee91343 13974 set_pred_insn_type_last ();
c19d1205 13975}
b99bd4ef 13976
90ec0d68
MGD		 13977static void
13978do_t_hvc (void)
13979{
e2b0ab59 13980 unsigned int value = inst.relocs[0].exp.X_add_number;
90ec0d68 13981
e2b0ab59 13982 inst.relocs[0].type = BFD_RELOC_UNUSED;
90ec0d68
MGD		 13983 inst.instruction |= (value & 0x0fff);
13984 inst.instruction |= (value & 0xf000) << 4;
13985}
13986
c19d1205 13987static void
3a21c15a 13988do_t_ssat_usat (int bias)
c19d1205 13989{
fdfde340
JM		 13990 unsigned Rd, Rn;
13991
13992 Rd = inst.operands[0].reg;
13993 Rn = inst.operands[2].reg;
13994
13995 reject_bad_reg (Rd);
13996 reject_bad_reg (Rn);
13997
13998 inst.instruction |= Rd << 8;
3a21c15a 13999 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 14000 inst.instruction |= Rn << 16;
b99bd4ef 14001
c19d1205 14002 if (inst.operands[3].present)
b99bd4ef 14003 {
e2b0ab59 14004 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
3a21c15a 14005
e2b0ab59 14006 inst.relocs[0].type = BFD_RELOC_UNUSED;
3a21c15a 14007
e2b0ab59 14008 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 14009 _("expression too complex"));
b99bd4ef 14010
3a21c15a 14011 if (shift_amount != 0)
6189168b 14012 {
3a21c15a
NC		 14013 constraint (shift_amount > 31,
14014 _("shift expression is too large"));
14015
c19d1205 14016 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC		 14017 inst.instruction |= 0x00200000; /* sh bit. */
14018
14019 inst.instruction |= (shift_amount & 0x1c) << 10;
14020 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC		 14021 }
14022 }
b99bd4ef 14023}
c921be7d 14024
3a21c15a
NC		 14025static void
14026do_t_ssat (void)
14027{
14028 do_t_ssat_usat (1);
14029}
b99bd4ef 14030
0dd132b6 14031static void
c19d1205 14032do_t_ssat16 (void)
0dd132b6 14033{
fdfde340
JM		 14034 unsigned Rd, Rn;
14035
14036 Rd = inst.operands[0].reg;
14037 Rn = inst.operands[2].reg;
14038
14039 reject_bad_reg (Rd);
14040 reject_bad_reg (Rn);
14041
14042 inst.instruction |= Rd << 8;
c19d1205 14043 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 14044 inst.instruction |= Rn << 16;
c19d1205 14045}
0dd132b6 14046
c19d1205
ZW		 14047static void
14048do_t_strex (void)
14049{
14050 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
14051 || inst.operands[2].postind || inst.operands[2].writeback
14052 || inst.operands[2].immisreg || inst.operands[2].shifted
14053 || inst.operands[2].negative,
01cfc07f 14054 BAD_ADDR_MODE);
0dd132b6 14055
5be8be5d
DG		 14056 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
14057
c19d1205
ZW		 14058 inst.instruction |= inst.operands[0].reg << 8;
14059 inst.instruction |= inst.operands[1].reg << 12;
14060 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 14061 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC		 14062}
14063
b99bd4ef 14064static void
c19d1205 14065do_t_strexd (void)
b99bd4ef 14066{
c19d1205
ZW		 14067 if (!inst.operands[2].present)
14068 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 14069
c19d1205
ZW		 14070 constraint (inst.operands[0].reg == inst.operands[1].reg
14071 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 14072 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 14073 BAD_OVERLAP);
b99bd4ef 14074
c19d1205
ZW		 14075 inst.instruction |= inst.operands[0].reg;
14076 inst.instruction |= inst.operands[1].reg << 12;
14077 inst.instruction |= inst.operands[2].reg << 8;
14078 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC		 14079}
14080
14081static void
c19d1205 14082do_t_sxtah (void)
b99bd4ef 14083{
fdfde340
JM		 14084 unsigned Rd, Rn, Rm;
14085
14086 Rd = inst.operands[0].reg;
14087 Rn = inst.operands[1].reg;
14088 Rm = inst.operands[2].reg;
14089
14090 reject_bad_reg (Rd);
14091 reject_bad_reg (Rn);
14092 reject_bad_reg (Rm);
14093
14094 inst.instruction |= Rd << 8;
14095 inst.instruction |= Rn << 16;
14096 inst.instruction |= Rm;
c19d1205
ZW		 14097 inst.instruction |= inst.operands[3].imm << 4;
14098}
b99bd4ef 14099
c19d1205
ZW		 14100static void
14101do_t_sxth (void)
14102{
fdfde340
JM		 14103 unsigned Rd, Rm;
14104
14105 Rd = inst.operands[0].reg;
14106 Rm = inst.operands[1].reg;
14107
14108 reject_bad_reg (Rd);
14109 reject_bad_reg (Rm);
c921be7d
NC		 14110
14111 if (inst.instruction <= 0xffff
14112 && inst.size_req != 4
fdfde340 14113 && Rd <= 7 && Rm <= 7
c19d1205 14114 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 14115 {
c19d1205 14116 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 14117 inst.instruction |= Rd;
14118 inst.instruction |= Rm << 3;
b99bd4ef 14119 }
c19d1205 14120 else if (unified_syntax)
b99bd4ef 14121 {
c19d1205
ZW		 14122 if (inst.instruction <= 0xffff)
14123 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 14124 inst.instruction |= Rd << 8;
14125 inst.instruction |= Rm;
c19d1205 14126 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 14127 }
c19d1205 14128 else
b99bd4ef 14129 {
c19d1205
ZW		 14130 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
14131 _("Thumb encoding does not support rotation"));
14132 constraint (1, BAD_HIREG);
b99bd4ef 14133 }
c19d1205 14134}
b99bd4ef 14135
c19d1205
ZW		 14136static void
14137do_t_swi (void)
14138{
e2b0ab59 14139 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
c19d1205 14140}
b99bd4ef 14141
92e90b6e
PB		 14142static void
14143do_t_tb (void)
14144{
fdfde340 14145 unsigned Rn, Rm;
92e90b6e
PB		 14146 int half;
14147
14148 half = (inst.instruction & 0x10) != 0;
5ee91343 14149 set_pred_insn_type_last ();
dfa9f0d5
PB		 14150 constraint (inst.operands[0].immisreg,
14151 _("instruction requires register index"));
fdfde340
JM		 14152
14153 Rn = inst.operands[0].reg;
14154 Rm = inst.operands[0].imm;
c921be7d 14155
5c8ed6a4
JW		 14156 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
14157 constraint (Rn == REG_SP, BAD_SP);
fdfde340
JM		 14158 reject_bad_reg (Rm);
14159
92e90b6e
PB		 14160 constraint (!half && inst.operands[0].shifted,
14161 _("instruction does not allow shifted index"));
fdfde340 14162 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB		 14163}
14164
74db7efb
NC		 14165static void
14166do_t_udf (void)
14167{
14168 if (!inst.operands[0].present)
14169 inst.operands[0].imm = 0;
14170
14171 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14172 {
14173 constraint (inst.size_req == 2,
14174 _("immediate value out of range"));
14175 inst.instruction = THUMB_OP32 (inst.instruction);
14176 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14177 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14178 }
14179 else
14180 {
14181 inst.instruction = THUMB_OP16 (inst.instruction);
14182 inst.instruction |= inst.operands[0].imm;
14183 }
14184
5ee91343 14185 set_pred_insn_type (NEUTRAL_IT_INSN);
74db7efb
NC		 14186}
14187
14188
c19d1205
ZW		 14189static void
14190do_t_usat (void)
14191{
3a21c15a 14192 do_t_ssat_usat (0);
b99bd4ef
NC		 14193}
14194
14195static void
c19d1205 14196do_t_usat16 (void)
b99bd4ef 14197{
fdfde340
JM		 14198 unsigned Rd, Rn;
14199
14200 Rd = inst.operands[0].reg;
14201 Rn = inst.operands[2].reg;
14202
14203 reject_bad_reg (Rd);
14204 reject_bad_reg (Rn);
14205
14206 inst.instruction |= Rd << 8;
c19d1205 14207 inst.instruction |= inst.operands[1].imm;
fdfde340 14208 inst.instruction |= Rn << 16;
b99bd4ef 14209}
c19d1205 14210
e12437dc
AV		 14211/* Checking the range of the branch offset (VAL) with NBITS bits
14212 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14213static int
14214v8_1_branch_value_check (int val, int nbits, int is_signed)
14215{
14216 gas_assert (nbits > 0 && nbits <= 32);
14217 if (is_signed)
14218 {
14219 int cmp = (1 << (nbits - 1));
14220 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
14221 return FAIL;
14222 }
14223 else
14224 {
14225 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
14226 return FAIL;
14227 }
14228 return SUCCESS;
14229}
14230
4389b29a
AV		 14231/* For branches in Armv8.1-M Mainline. */
14232static void
14233do_t_branch_future (void)
14234{
14235 unsigned long insn = inst.instruction;
14236
14237 inst.instruction = THUMB_OP32 (inst.instruction);
14238 if (inst.operands[0].hasreloc == 0)
14239 {
14240 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
14241 as_bad (BAD_BRANCH_OFF);
14242
14243 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14244 }
14245 else
14246 {
14247 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14248 inst.relocs[0].pc_rel = 1;
14249 }
14250
14251 switch (insn)
14252 {
14253 case T_MNEM_bf:
14254 if (inst.operands[1].hasreloc == 0)
14255 {
14256 int val = inst.operands[1].imm;
14257 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
14258 as_bad (BAD_BRANCH_OFF);
14259
14260 int immA = (val & 0x0001f000) >> 12;
14261 int immB = (val & 0x00000ffc) >> 2;
14262 int immC = (val & 0x00000002) >> 1;
14263 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14264 }
14265 else
14266 {
14267 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14268 inst.relocs[1].pc_rel = 1;
14269 }
14270 break;
14271
65d1bc05
AV		 14272 case T_MNEM_bfl:
14273 if (inst.operands[1].hasreloc == 0)
14274 {
14275 int val = inst.operands[1].imm;
14276 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
14277 as_bad (BAD_BRANCH_OFF);
14278
14279 int immA = (val & 0x0007f000) >> 12;
14280 int immB = (val & 0x00000ffc) >> 2;
14281 int immC = (val & 0x00000002) >> 1;
14282 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14283 }
14284 else
14285 {
14286 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14287 inst.relocs[1].pc_rel = 1;
14288 }
14289 break;
14290
f6b2b12d
AV		 14291 case T_MNEM_bfcsel:
14292 /* Operand 1. */
14293 if (inst.operands[1].hasreloc == 0)
14294 {
14295 int val = inst.operands[1].imm;
14296 int immA = (val & 0x00001000) >> 12;
14297 int immB = (val & 0x00000ffc) >> 2;
14298 int immC = (val & 0x00000002) >> 1;
14299 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14300 }
14301 else
14302 {
14303 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14304 inst.relocs[1].pc_rel = 1;
14305 }
14306
14307 /* Operand 2. */
14308 if (inst.operands[2].hasreloc == 0)
14309 {
14310 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14311 int val2 = inst.operands[2].imm;
14312 int val0 = inst.operands[0].imm & 0x1f;
14313 int diff = val2 - val0;
14314 if (diff == 4)
14315 inst.instruction |= 1 << 17; /* T bit. */
14316 else if (diff != 2)
14317 as_bad (_("out of range label-relative fixup value"));
14318 }
14319 else
14320 {
14321 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14322 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14323 inst.relocs[2].pc_rel = 1;
14324 }
14325
14326 /* Operand 3. */
14327 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14328 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14329 break;
14330
f1c7f421
AV		 14331 case T_MNEM_bfx:
14332 case T_MNEM_bflx:
14333 inst.instruction |= inst.operands[1].reg << 16;
14334 break;
14335
4389b29a
AV		 14336 default: abort ();
14337 }
14338}
14339
60f993ce
AV		 14340/* Helper function for do_t_loloop to handle relocations. */
14341static void
14342v8_1_loop_reloc (int is_le)
14343{
14344 if (inst.relocs[0].exp.X_op == O_constant)
14345 {
14346 int value = inst.relocs[0].exp.X_add_number;
14347 value = (is_le) ? -value : value;
14348
14349 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14350 as_bad (BAD_BRANCH_OFF);
14351
14352 int imml, immh;
14353
14354 immh = (value & 0x00000ffc) >> 2;
14355 imml = (value & 0x00000002) >> 1;
14356
14357 inst.instruction |= (imml << 11) | (immh << 1);
14358 }
14359 else
14360 {
14361 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14362 inst.relocs[0].pc_rel = 1;
14363 }
14364}
14365
08132bdd
SP		 14366/* For shifts with four operands in MVE. */
14367static void
14368do_mve_scalar_shift1 (void)
14369{
14370 unsigned int value = inst.operands[2].imm;
14371
14372 inst.instruction |= inst.operands[0].reg << 16;
14373 inst.instruction |= inst.operands[1].reg << 8;
14374
14375 /* Setting the bit for saturation. */
14376 inst.instruction |= ((value == 64) ? 0: 1) << 7;
14377
14378 /* Assuming Rm is already checked not to be 11x1. */
14379 constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP);
14380 constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP);
14381 inst.instruction |= inst.operands[3].reg << 12;
14382}
14383
23d00a41
SD		 14384/* For shifts in MVE. */
14385static void
14386do_mve_scalar_shift (void)
14387{
14388 if (!inst.operands[2].present)
14389 {
14390 inst.operands[2] = inst.operands[1];
14391 inst.operands[1].reg = 0xf;
14392 }
14393
14394 inst.instruction |= inst.operands[0].reg << 16;
14395 inst.instruction |= inst.operands[1].reg << 8;
14396
14397 if (inst.operands[2].isreg)
14398 {
14399 /* Assuming Rm is already checked not to be 11x1. */
14400 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14401 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14402 inst.instruction |= inst.operands[2].reg << 12;
14403 }
14404 else
14405 {
14406 /* Assuming imm is already checked as [1,32]. */
14407 unsigned int value = inst.operands[2].imm;
14408 inst.instruction |= (value & 0x1c) << 10;
14409 inst.instruction |= (value & 0x03) << 6;
14410 /* Change last 4 bits from 0xd to 0xf. */
14411 inst.instruction |= 0x2;
14412 }
14413}
14414
a302e574
AV		 14415/* MVE instruction encoder helpers. */
14416#define M_MNEM_vabav 0xee800f01
14417#define M_MNEM_vmladav 0xeef00e00
14418#define M_MNEM_vmladava 0xeef00e20
14419#define M_MNEM_vmladavx 0xeef01e00
14420#define M_MNEM_vmladavax 0xeef01e20
14421#define M_MNEM_vmlsdav 0xeef00e01
14422#define M_MNEM_vmlsdava 0xeef00e21
14423#define M_MNEM_vmlsdavx 0xeef01e01
14424#define M_MNEM_vmlsdavax 0xeef01e21
886e1c73
AV		 14425#define M_MNEM_vmullt 0xee011e00
14426#define M_MNEM_vmullb 0xee010e00
efd0b310 14427#define M_MNEM_vctp 0xf000e801
35c228db
AV		 14428#define M_MNEM_vst20 0xfc801e00
14429#define M_MNEM_vst21 0xfc801e20
14430#define M_MNEM_vst40 0xfc801e01
14431#define M_MNEM_vst41 0xfc801e21
14432#define M_MNEM_vst42 0xfc801e41
14433#define M_MNEM_vst43 0xfc801e61
14434#define M_MNEM_vld20 0xfc901e00
14435#define M_MNEM_vld21 0xfc901e20
14436#define M_MNEM_vld40 0xfc901e01
14437#define M_MNEM_vld41 0xfc901e21
14438#define M_MNEM_vld42 0xfc901e41
14439#define M_MNEM_vld43 0xfc901e61
f5f10c66
AV		 14440#define M_MNEM_vstrb 0xec000e00
14441#define M_MNEM_vstrh 0xec000e10
14442#define M_MNEM_vstrw 0xec000e40
14443#define M_MNEM_vstrd 0xec000e50
14444#define M_MNEM_vldrb 0xec100e00
14445#define M_MNEM_vldrh 0xec100e10
14446#define M_MNEM_vldrw 0xec100e40
14447#define M_MNEM_vldrd 0xec100e50
57785aa2
AV		 14448#define M_MNEM_vmovlt 0xeea01f40
14449#define M_MNEM_vmovlb 0xeea00f40
14450#define M_MNEM_vmovnt 0xfe311e81
14451#define M_MNEM_vmovnb 0xfe310e81
c2dafc2a
AV		 14452#define M_MNEM_vadc 0xee300f00
14453#define M_MNEM_vadci 0xee301f00
14454#define M_MNEM_vbrsr 0xfe011e60
26c1e780
AV		 14455#define M_MNEM_vaddlv 0xee890f00
14456#define M_MNEM_vaddlva 0xee890f20
14457#define M_MNEM_vaddv 0xeef10f00
14458#define M_MNEM_vaddva 0xeef10f20
b409bdb6
AV		 14459#define M_MNEM_vddup 0xee011f6e
14460#define M_MNEM_vdwdup 0xee011f60
14461#define M_MNEM_vidup 0xee010f6e
14462#define M_MNEM_viwdup 0xee010f60
13ccd4c0
AV		 14463#define M_MNEM_vmaxv 0xeee20f00
14464#define M_MNEM_vmaxav 0xeee00f00
14465#define M_MNEM_vminv 0xeee20f80
14466#define M_MNEM_vminav 0xeee00f80
93925576
AV		 14467#define M_MNEM_vmlaldav 0xee800e00
14468#define M_MNEM_vmlaldava 0xee800e20
14469#define M_MNEM_vmlaldavx 0xee801e00
14470#define M_MNEM_vmlaldavax 0xee801e20
14471#define M_MNEM_vmlsldav 0xee800e01
14472#define M_MNEM_vmlsldava 0xee800e21
14473#define M_MNEM_vmlsldavx 0xee801e01
14474#define M_MNEM_vmlsldavax 0xee801e21
14475#define M_MNEM_vrmlaldavhx 0xee801f00
14476#define M_MNEM_vrmlaldavhax 0xee801f20
14477#define M_MNEM_vrmlsldavh 0xfe800e01
14478#define M_MNEM_vrmlsldavha 0xfe800e21
14479#define M_MNEM_vrmlsldavhx 0xfe801e01
14480#define M_MNEM_vrmlsldavhax 0xfe801e21
1be7aba3
AV		 14481#define M_MNEM_vqmovnt 0xee331e01
14482#define M_MNEM_vqmovnb 0xee330e01
14483#define M_MNEM_vqmovunt 0xee311e81
14484#define M_MNEM_vqmovunb 0xee310e81
4aa88b50
AV		 14485#define M_MNEM_vshrnt 0xee801fc1
14486#define M_MNEM_vshrnb 0xee800fc1
14487#define M_MNEM_vrshrnt 0xfe801fc1
14488#define M_MNEM_vqshrnt 0xee801f40
14489#define M_MNEM_vqshrnb 0xee800f40
14490#define M_MNEM_vqshrunt 0xee801fc0
14491#define M_MNEM_vqshrunb 0xee800fc0
14492#define M_MNEM_vrshrnb 0xfe800fc1
14493#define M_MNEM_vqrshrnt 0xee801f41
14494#define M_MNEM_vqrshrnb 0xee800f41
14495#define M_MNEM_vqrshrunt 0xfe801fc0
14496#define M_MNEM_vqrshrunb 0xfe800fc0
a302e574 14497
5287ad62 14498/* Neon instruction encoder helpers. */
5f4273c7 14499
5287ad62 14500/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 14501
5287ad62
JB		 14502/* An "invalid" code for the following tables. */
14503#define N_INV -1u
14504
14505struct neon_tab_entry
b99bd4ef 14506{
5287ad62
JB		 14507 unsigned integer;
14508 unsigned float_or_poly;
14509 unsigned scalar_or_imm;
14510};
5f4273c7 14511
5287ad62
JB		 14512/* Map overloaded Neon opcodes to their respective encodings. */
14513#define NEON_ENC_TAB \
14514 X(vabd, 0x0000700, 0x1200d00, N_INV), \
5ee91343 14515 X(vabdl, 0x0800700, N_INV, N_INV), \
5287ad62
JB		 14516 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14517 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14518 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14519 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14520 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14521 X(vadd, 0x0000800, 0x0000d00, N_INV), \
5ee91343 14522 X(vaddl, 0x0800000, N_INV, N_INV), \
5287ad62 14523 X(vsub, 0x1000800, 0x0200d00, N_INV), \
5ee91343 14524 X(vsubl, 0x0800200, N_INV, N_INV), \
5287ad62
JB		 14525 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14526 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14527 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14528 /* Register variants of the following two instructions are encoded as
e07e6e58 14529 vcge / vcgt with the operands reversed. */ \
92559b5b
PB		 14530 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14531 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB		 14532 X(vfma, N_INV, 0x0000c10, N_INV), \
14533 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB		 14534 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14535 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14536 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14537 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14538 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14539 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14540 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14541 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14542 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14543 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14544 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
d6b4b13e
MW		 14545 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14546 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
5287ad62
JB		 14547 X(vshl, 0x0000400, N_INV, 0x0800510), \
14548 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14549 X(vand, 0x0000110, N_INV, 0x0800030), \
14550 X(vbic, 0x0100110, N_INV, 0x0800030), \
14551 X(veor, 0x1000110, N_INV, N_INV), \
14552 X(vorn, 0x0300110, N_INV, 0x0800010), \
14553 X(vorr, 0x0200110, N_INV, 0x0800010), \
14554 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14555 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14556 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14557 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14558 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14559 X(vst1, 0x0000000, 0x0800000, N_INV), \
14560 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14561 X(vst2, 0x0000100, 0x0800100, N_INV), \
14562 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14563 X(vst3, 0x0000200, 0x0800200, N_INV), \
14564 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14565 X(vst4, 0x0000300, 0x0800300, N_INV), \
14566 X(vmovn, 0x1b20200, N_INV, N_INV), \
14567 X(vtrn, 0x1b20080, N_INV, N_INV), \
14568 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB		 14569 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14570 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB		 14571 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14572 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB		 14573 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14574 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB		 14575 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14576 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14577 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
33399f07
MGD		 14578 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14579 X(vseleq, 0xe000a00, N_INV, N_INV), \
14580 X(vselvs, 0xe100a00, N_INV, N_INV), \
14581 X(vselge, 0xe200a00, N_INV, N_INV), \
73924fbc
MGD		 14582 X(vselgt, 0xe300a00, N_INV, N_INV), \
14583 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
7e8e6784 14584 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
30bdf752
MGD		 14585 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14586 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
91ff7894 14587 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
48adcd8e 14588 X(aes, 0x3b00300, N_INV, N_INV), \
3c9017d2
MGD		 14589 X(sha3op, 0x2000c00, N_INV, N_INV), \
14590 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14591 X(sha2op, 0x3ba0380, N_INV, N_INV)
5287ad62
JB		 14592
14593enum neon_opc
14594{
14595#define X(OPC,I,F,S) N_MNEM_##OPC
14596NEON_ENC_TAB
14597#undef X
14598};
b99bd4ef 14599
5287ad62
JB		 14600static const struct neon_tab_entry neon_enc_tab[] =
14601{
14602#define X(OPC,I,F,S) { (I), (F), (S) }
14603NEON_ENC_TAB
14604#undef X
14605};
b99bd4ef 14606
88714cb8
DG		 14607/* Do not use these macros; instead, use NEON_ENCODE defined below. */
14608#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14609#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14610#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14611#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14612#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14613#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14614#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14615#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14616#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14617#define NEON_ENC_SINGLE_(X) \
037e8744 14618 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 14619#define NEON_ENC_DOUBLE_(X) \
037e8744 14620 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
33399f07
MGD		 14621#define NEON_ENC_FPV8_(X) \
14622 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
5287ad62 14623
88714cb8
DG		 14624#define NEON_ENCODE(type, inst) \
14625 do \
14626 { \
14627 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14628 inst.is_neon = 1; \
14629 } \
14630 while (0)
14631
14632#define check_neon_suffixes \
14633 do \
14634 { \
14635 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14636 { \
14637 as_bad (_("invalid neon suffix for non neon instruction")); \
14638 return; \
14639 } \
14640 } \
14641 while (0)
14642
037e8744
JB		 14643/* Define shapes for instruction operands. The following mnemonic characters
14644 are used in this table:
5287ad62 14645
037e8744 14646 F - VFP S<n> register
5287ad62
JB		 14647 D - Neon D<n> register
14648 Q - Neon Q<n> register
14649 I - Immediate
14650 S - Scalar
14651 R - ARM register
14652 L - D<n> register list
5f4273c7 14653
037e8744
JB		 14654 This table is used to generate various data:
14655 - enumerations of the form NS_DDR to be used as arguments to
14656 neon_select_shape.
14657 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 14658 - a table used to drive neon_select_shape. */
b99bd4ef 14659
037e8744 14660#define NEON_SHAPE_DEF \
93925576 14661 X(4, (R, R, Q, Q), QUAD), \
b409bdb6 14662 X(4, (Q, R, R, I), QUAD), \
57785aa2
AV		 14663 X(4, (R, R, S, S), QUAD), \
14664 X(4, (S, S, R, R), QUAD), \
b409bdb6 14665 X(3, (Q, R, I), QUAD), \
1b883319
AV		 14666 X(3, (I, Q, Q), QUAD), \
14667 X(3, (I, Q, R), QUAD), \
a302e574 14668 X(3, (R, Q, Q), QUAD), \
037e8744
JB		 14669 X(3, (D, D, D), DOUBLE), \
14670 X(3, (Q, Q, Q), QUAD), \
14671 X(3, (D, D, I), DOUBLE), \
14672 X(3, (Q, Q, I), QUAD), \
14673 X(3, (D, D, S), DOUBLE), \
14674 X(3, (Q, Q, S), QUAD), \
5ee91343 14675 X(3, (Q, Q, R), QUAD), \
26c1e780
AV		 14676 X(3, (R, R, Q), QUAD), \
14677 X(2, (R, Q), QUAD), \
037e8744
JB		 14678 X(2, (D, D), DOUBLE), \
14679 X(2, (Q, Q), QUAD), \
14680 X(2, (D, S), DOUBLE), \
14681 X(2, (Q, S), QUAD), \
14682 X(2, (D, R), DOUBLE), \
14683 X(2, (Q, R), QUAD), \
14684 X(2, (D, I), DOUBLE), \
14685 X(2, (Q, I), QUAD), \
14686 X(3, (D, L, D), DOUBLE), \
14687 X(2, (D, Q), MIXED), \
14688 X(2, (Q, D), MIXED), \
14689 X(3, (D, Q, I), MIXED), \
14690 X(3, (Q, D, I), MIXED), \
14691 X(3, (Q, D, D), MIXED), \
14692 X(3, (D, Q, Q), MIXED), \
14693 X(3, (Q, Q, D), MIXED), \
14694 X(3, (Q, D, S), MIXED), \
14695 X(3, (D, Q, S), MIXED), \
14696 X(4, (D, D, D, I), DOUBLE), \
14697 X(4, (Q, Q, Q, I), QUAD), \
c28eeff2
SN		 14698 X(4, (D, D, S, I), DOUBLE), \
14699 X(4, (Q, Q, S, I), QUAD), \
037e8744
JB		 14700 X(2, (F, F), SINGLE), \
14701 X(3, (F, F, F), SINGLE), \
14702 X(2, (F, I), SINGLE), \
14703 X(2, (F, D), MIXED), \
14704 X(2, (D, F), MIXED), \
14705 X(3, (F, F, I), MIXED), \
14706 X(4, (R, R, F, F), SINGLE), \
14707 X(4, (F, F, R, R), SINGLE), \
14708 X(3, (D, R, R), DOUBLE), \
14709 X(3, (R, R, D), DOUBLE), \
14710 X(2, (S, R), SINGLE), \
14711 X(2, (R, S), SINGLE), \
14712 X(2, (F, R), SINGLE), \
d54af2d0 14713 X(2, (R, F), SINGLE), \
1f6234a3
AV		 14714/* Used for MVE tail predicated loop instructions. */\
14715 X(2, (R, R), QUAD), \
d54af2d0
RL		 14716/* Half float shape supported so far. */\
14717 X (2, (H, D), MIXED), \
14718 X (2, (D, H), MIXED), \
14719 X (2, (H, F), MIXED), \
14720 X (2, (F, H), MIXED), \
14721 X (2, (H, H), HALF), \
14722 X (2, (H, R), HALF), \
14723 X (2, (R, H), HALF), \
14724 X (2, (H, I), HALF), \
14725 X (3, (H, H, H), HALF), \
14726 X (3, (H, F, I), MIXED), \
dec41383
JW		 14727 X (3, (F, H, I), MIXED), \
14728 X (3, (D, H, H), MIXED), \
14729 X (3, (D, H, S), MIXED)
037e8744
JB		 14730
14731#define S2(A,B) NS_##A##B
14732#define S3(A,B,C) NS_##A##B##C
14733#define S4(A,B,C,D) NS_##A##B##C##D
14734
14735#define X(N, L, C) S##N L
14736
5287ad62
JB		 14737enum neon_shape
14738{
037e8744
JB		 14739 NEON_SHAPE_DEF,
14740 NS_NULL
5287ad62 14741};
b99bd4ef 14742
037e8744
JB		 14743#undef X
14744#undef S2
14745#undef S3
14746#undef S4
14747
14748enum neon_shape_class
14749{
d54af2d0 14750 SC_HALF,
037e8744
JB		 14751 SC_SINGLE,
14752 SC_DOUBLE,
14753 SC_QUAD,
14754 SC_MIXED
14755};
14756
14757#define X(N, L, C) SC_##C
14758
14759static enum neon_shape_class neon_shape_class[] =
14760{
14761 NEON_SHAPE_DEF
14762};
14763
14764#undef X
14765
14766enum neon_shape_el
14767{
d54af2d0 14768 SE_H,
037e8744
JB		 14769 SE_F,
14770 SE_D,
14771 SE_Q,
14772 SE_I,
14773 SE_S,
14774 SE_R,
14775 SE_L
14776};
14777
14778/* Register widths of above. */
14779static unsigned neon_shape_el_size[] =
14780{
d54af2d0 14781 16,
037e8744
JB		 14782 32,
14783 64,
14784 128,
14785 0,
14786 32,
14787 32,
14788 0
14789};
14790
14791struct neon_shape_info
14792{
14793 unsigned els;
14794 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14795};
14796
14797#define S2(A,B) { SE_##A, SE_##B }
14798#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14799#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14800
14801#define X(N, L, C) { N, S##N L }
14802
14803static struct neon_shape_info neon_shape_tab[] =
14804{
14805 NEON_SHAPE_DEF
14806};
14807
14808#undef X
14809#undef S2
14810#undef S3
14811#undef S4
14812
5287ad62
JB		 14813/* Bit masks used in type checking given instructions.
14814 'N_EQK' means the type must be the same as (or based on in some way) the key
14815 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14816 set, various other bits can be set as well in order to modify the meaning of
14817 the type constraint. */
14818
14819enum neon_type_mask
14820{
8e79c3df
CM		 14821 N_S8 = 0x0000001,
14822 N_S16 = 0x0000002,
14823 N_S32 = 0x0000004,
14824 N_S64 = 0x0000008,
14825 N_U8 = 0x0000010,
14826 N_U16 = 0x0000020,
14827 N_U32 = 0x0000040,
14828 N_U64 = 0x0000080,
14829 N_I8 = 0x0000100,
14830 N_I16 = 0x0000200,
14831 N_I32 = 0x0000400,
14832 N_I64 = 0x0000800,
14833 N_8 = 0x0001000,
14834 N_16 = 0x0002000,
14835 N_32 = 0x0004000,
14836 N_64 = 0x0008000,
14837 N_P8 = 0x0010000,
14838 N_P16 = 0x0020000,
14839 N_F16 = 0x0040000,
14840 N_F32 = 0x0080000,
14841 N_F64 = 0x0100000,
4f51b4bd 14842 N_P64 = 0x0200000,
c921be7d
NC		 14843 N_KEY = 0x1000000, /* Key element (main type specifier). */
14844 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 14845 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
91ff7894 14846 N_UNT = 0x8000000, /* Must be explicitly untyped. */
c921be7d
NC		 14847 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14848 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
14849 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14850 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14851 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14852 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
14853 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 14854 N_UTYP = 0,
4f51b4bd 14855 N_MAX_NONSPECIAL = N_P64
5287ad62
JB		 14856};
14857
dcbf9037
JB		 14858#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14859
5287ad62
JB		 14860#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14861#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14862#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
cc933301
JW		 14863#define N_S_32 (N_S8 | N_S16 | N_S32)
14864#define N_F_16_32 (N_F16 | N_F32)
14865#define N_SUF_32 (N_SU_32 | N_F_16_32)
5287ad62 14866#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
cc933301 14867#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
d54af2d0 14868#define N_F_ALL (N_F16 | N_F32 | N_F64)
5ee91343
AV		 14869#define N_I_MVE (N_I8 | N_I16 | N_I32)
14870#define N_F_MVE (N_F16 | N_F32)
14871#define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
5287ad62
JB		 14872
14873/* Pass this as the first type argument to neon_check_type to ignore types
14874 altogether. */
14875#define N_IGNORE_TYPE (N_KEY | N_EQK)
14876
037e8744
JB		 14877/* Select a "shape" for the current instruction (describing register types or
14878 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14879 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14880 function of operand parsing, so this function doesn't need to be called.
14881 Shapes should be listed in order of decreasing length. */
5287ad62
JB		 14882
14883static enum neon_shape
037e8744 14884neon_select_shape (enum neon_shape shape, ...)
5287ad62 14885{
037e8744
JB		 14886 va_list ap;
14887 enum neon_shape first_shape = shape;
5287ad62
JB		 14888
14889 /* Fix missing optional operands. FIXME: we don't know at this point how
14890 many arguments we should have, so this makes the assumption that we have
14891 > 1. This is true of all current Neon opcodes, I think, but may not be
14892 true in the future. */
14893 if (!inst.operands[1].present)
14894 inst.operands[1] = inst.operands[0];
14895
037e8744 14896 va_start (ap, shape);
5f4273c7 14897
21d799b5 14898 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB		 14899 {
14900 unsigned j;
14901 int matches = 1;
14902
14903 for (j = 0; j < neon_shape_tab[shape].els; j++)
477330fc
RM		 14904 {
14905 if (!inst.operands[j].present)
14906 {
14907 matches = 0;
14908 break;
14909 }
14910
14911 switch (neon_shape_tab[shape].el[j])
14912 {
d54af2d0
RL		 14913 /* If a .f16, .16, .u16, .s16 type specifier is given over
14914 a VFP single precision register operand, it's essentially
14915 means only half of the register is used.
14916
14917 If the type specifier is given after the mnemonics, the
14918 information is stored in inst.vectype. If the type specifier
14919 is given after register operand, the information is stored
14920 in inst.operands[].vectype.
14921
14922 When there is only one type specifier, and all the register
14923 operands are the same type of hardware register, the type
14924 specifier applies to all register operands.
14925
14926 If no type specifier is given, the shape is inferred from
14927 operand information.
14928
14929 for example:
14930 vadd.f16 s0, s1, s2: NS_HHH
14931 vabs.f16 s0, s1: NS_HH
14932 vmov.f16 s0, r1: NS_HR
14933 vmov.f16 r0, s1: NS_RH
14934 vcvt.f16 r0, s1: NS_RH
14935 vcvt.f16.s32 s2, s2, #29: NS_HFI
14936 vcvt.f16.s32 s2, s2: NS_HF
14937 */
14938 case SE_H:
14939 if (!(inst.operands[j].isreg
14940 && inst.operands[j].isvec
14941 && inst.operands[j].issingle
14942 && !inst.operands[j].isquad
14943 && ((inst.vectype.elems == 1
14944 && inst.vectype.el[0].size == 16)
14945 || (inst.vectype.elems > 1
14946 && inst.vectype.el[j].size == 16)
14947 || (inst.vectype.elems == 0
14948 && inst.operands[j].vectype.type != NT_invtype
14949 && inst.operands[j].vectype.size == 16))))
14950 matches = 0;
14951 break;
14952
477330fc
RM		 14953 case SE_F:
14954 if (!(inst.operands[j].isreg
14955 && inst.operands[j].isvec
14956 && inst.operands[j].issingle
d54af2d0
RL		 14957 && !inst.operands[j].isquad
14958 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14959 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14960 || (inst.vectype.elems == 0
14961 && (inst.operands[j].vectype.size == 32
14962 || inst.operands[j].vectype.type == NT_invtype)))))
477330fc
RM		 14963 matches = 0;
14964 break;
14965
14966 case SE_D:
14967 if (!(inst.operands[j].isreg
14968 && inst.operands[j].isvec
14969 && !inst.operands[j].isquad
14970 && !inst.operands[j].issingle))
14971 matches = 0;
14972 break;
14973
14974 case SE_R:
14975 if (!(inst.operands[j].isreg
14976 && !inst.operands[j].isvec))
14977 matches = 0;
14978 break;
14979
14980 case SE_Q:
14981 if (!(inst.operands[j].isreg
14982 && inst.operands[j].isvec
14983 && inst.operands[j].isquad
14984 && !inst.operands[j].issingle))
14985 matches = 0;
14986 break;
14987
14988 case SE_I:
14989 if (!(!inst.operands[j].isreg
14990 && !inst.operands[j].isscalar))
14991 matches = 0;
14992 break;
14993
14994 case SE_S:
14995 if (!(!inst.operands[j].isreg
14996 && inst.operands[j].isscalar))
14997 matches = 0;
14998 break;
14999
15000 case SE_L:
15001 break;
15002 }
3fde54a2
JZ		 15003 if (!matches)
15004 break;
477330fc 15005 }
ad6cec43
MGD		 15006 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
15007 /* We've matched all the entries in the shape table, and we don't
15008 have any left over operands which have not been matched. */
477330fc 15009 break;
037e8744 15010 }
5f4273c7 15011
037e8744 15012 va_end (ap);
5287ad62 15013
037e8744
JB		 15014 if (shape == NS_NULL && first_shape != NS_NULL)
15015 first_error (_("invalid instruction shape"));
5287ad62 15016
037e8744
JB		 15017 return shape;
15018}
5287ad62 15019
037e8744
JB		 15020/* True if SHAPE is predominantly a quadword operation (most of the time, this
15021 means the Q bit should be set). */
15022
15023static int
15024neon_quad (enum neon_shape shape)
15025{
15026 return neon_shape_class[shape] == SC_QUAD;
5287ad62 15027}
037e8744 15028
5287ad62
JB		 15029static void
15030neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
477330fc 15031 unsigned *g_size)
5287ad62
JB		 15032{
15033 /* Allow modification to be made to types which are constrained to be
15034 based on the key element, based on bits set alongside N_EQK. */
15035 if ((typebits & N_EQK) != 0)
15036 {
15037 if ((typebits & N_HLF) != 0)
15038 *g_size /= 2;
15039 else if ((typebits & N_DBL) != 0)
15040 *g_size *= 2;
15041 if ((typebits & N_SGN) != 0)
15042 *g_type = NT_signed;
15043 else if ((typebits & N_UNS) != 0)
477330fc 15044 *g_type = NT_unsigned;
5287ad62 15045 else if ((typebits & N_INT) != 0)
477330fc 15046 *g_type = NT_integer;
5287ad62 15047 else if ((typebits & N_FLT) != 0)
477330fc 15048 *g_type = NT_float;
dcbf9037 15049 else if ((typebits & N_SIZ) != 0)
477330fc 15050 *g_type = NT_untyped;
5287ad62
JB		 15051 }
15052}
5f4273c7 15053
5287ad62
JB		 15054/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15055 operand type, i.e. the single type specified in a Neon instruction when it
15056 is the only one given. */
15057
15058static struct neon_type_el
15059neon_type_promote (struct neon_type_el *key, unsigned thisarg)
15060{
15061 struct neon_type_el dest = *key;
5f4273c7 15062
9c2799c2 15063 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 15064
5287ad62
JB		 15065 neon_modify_type_size (thisarg, &dest.type, &dest.size);
15066
15067 return dest;
15068}
15069
15070/* Convert Neon type and size into compact bitmask representation. */
15071
15072static enum neon_type_mask
15073type_chk_of_el_type (enum neon_el_type type, unsigned size)
15074{
15075 switch (type)
15076 {
15077 case NT_untyped:
15078 switch (size)
477330fc
RM		 15079 {
15080 case 8: return N_8;
15081 case 16: return N_16;
15082 case 32: return N_32;
15083 case 64: return N_64;
15084 default: ;
15085 }
5287ad62
JB		 15086 break;
15087
15088 case NT_integer:
15089 switch (size)
477330fc
RM		 15090 {
15091 case 8: return N_I8;
15092 case 16: return N_I16;
15093 case 32: return N_I32;
15094 case 64: return N_I64;
15095 default: ;
15096 }
5287ad62
JB		 15097 break;
15098
15099 case NT_float:
037e8744 15100 switch (size)
477330fc 15101 {
8e79c3df 15102 case 16: return N_F16;
477330fc
RM		 15103 case 32: return N_F32;
15104 case 64: return N_F64;
15105 default: ;
15106 }
5287ad62
JB		 15107 break;
15108
15109 case NT_poly:
15110 switch (size)
477330fc
RM		 15111 {
15112 case 8: return N_P8;
15113 case 16: return N_P16;
4f51b4bd 15114 case 64: return N_P64;
477330fc
RM		 15115 default: ;
15116 }
5287ad62
JB		 15117 break;
15118
15119 case NT_signed:
15120 switch (size)
477330fc
RM		 15121 {
15122 case 8: return N_S8;
15123 case 16: return N_S16;
15124 case 32: return N_S32;
15125 case 64: return N_S64;
15126 default: ;
15127 }
5287ad62
JB		 15128 break;
15129
15130 case NT_unsigned:
15131 switch (size)
477330fc
RM		 15132 {
15133 case 8: return N_U8;
15134 case 16: return N_U16;
15135 case 32: return N_U32;
15136 case 64: return N_U64;
15137 default: ;
15138 }
5287ad62
JB		 15139 break;
15140
15141 default: ;
15142 }
5f4273c7 15143
5287ad62
JB		 15144 return N_UTYP;
15145}
15146
15147/* Convert compact Neon bitmask type representation to a type and size. Only
15148 handles the case where a single bit is set in the mask. */
15149
dcbf9037 15150static int
5287ad62 15151el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
477330fc 15152 enum neon_type_mask mask)
5287ad62 15153{
dcbf9037
JB		 15154 if ((mask & N_EQK) != 0)
15155 return FAIL;
15156
5287ad62
JB		 15157 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
15158 *size = 8;
c70a8987 15159 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
5287ad62 15160 *size = 16;
dcbf9037 15161 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 15162 *size = 32;
4f51b4bd 15163 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
5287ad62 15164 *size = 64;
dcbf9037
JB		 15165 else
15166 return FAIL;
15167
5287ad62
JB		 15168 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
15169 *type = NT_signed;
dcbf9037 15170 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 15171 *type = NT_unsigned;
dcbf9037 15172 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 15173 *type = NT_integer;
dcbf9037 15174 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 15175 *type = NT_untyped;
4f51b4bd 15176 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
5287ad62 15177 *type = NT_poly;
d54af2d0 15178 else if ((mask & (N_F_ALL)) != 0)
5287ad62 15179 *type = NT_float;
dcbf9037
JB		 15180 else
15181 return FAIL;
5f4273c7 15182
dcbf9037 15183 return SUCCESS;
5287ad62
JB		 15184}
15185
15186/* Modify a bitmask of allowed types. This is only needed for type
15187 relaxation. */
15188
15189static unsigned
15190modify_types_allowed (unsigned allowed, unsigned mods)
15191{
15192 unsigned size;
15193 enum neon_el_type type;
15194 unsigned destmask;
15195 int i;
5f4273c7 15196
5287ad62 15197 destmask = 0;
5f4273c7 15198
5287ad62
JB		 15199 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
15200 {
21d799b5 15201 if (el_type_of_type_chk (&type, &size,
477330fc
RM		 15202 (enum neon_type_mask) (allowed & i)) == SUCCESS)
15203 {
15204 neon_modify_type_size (mods, &type, &size);
15205 destmask |= type_chk_of_el_type (type, size);
15206 }
5287ad62 15207 }
5f4273c7 15208
5287ad62
JB		 15209 return destmask;
15210}
15211
15212/* Check type and return type classification.
15213 The manual states (paraphrase): If one datatype is given, it indicates the
15214 type given in:
15215 - the second operand, if there is one
15216 - the operand, if there is no second operand
15217 - the result, if there are no operands.
15218 This isn't quite good enough though, so we use a concept of a "key" datatype
15219 which is set on a per-instruction basis, which is the one which matters when
15220 only one data type is written.
15221 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 15222 Neon instructions should call it before performing bit encoding. */
5287ad62
JB		 15223
15224static struct neon_type_el
15225neon_check_type (unsigned els, enum neon_shape ns, ...)
15226{
15227 va_list ap;
15228 unsigned i, pass, key_el = 0;
15229 unsigned types[NEON_MAX_TYPE_ELS];
15230 enum neon_el_type k_type = NT_invtype;
15231 unsigned k_size = -1u;
15232 struct neon_type_el badtype = {NT_invtype, -1};
15233 unsigned key_allowed = 0;
15234
15235 /* Optional registers in Neon instructions are always (not) in operand 1.
15236 Fill in the missing operand here, if it was omitted. */
15237 if (els > 1 && !inst.operands[1].present)
15238 inst.operands[1] = inst.operands[0];
15239
15240 /* Suck up all the varargs. */
15241 va_start (ap, ns);
15242 for (i = 0; i < els; i++)
15243 {
15244 unsigned thisarg = va_arg (ap, unsigned);
15245 if (thisarg == N_IGNORE_TYPE)
477330fc
RM		 15246 {
15247 va_end (ap);
15248 return badtype;
15249 }
5287ad62
JB		 15250 types[i] = thisarg;
15251 if ((thisarg & N_KEY) != 0)
477330fc 15252 key_el = i;
5287ad62
JB		 15253 }
15254 va_end (ap);
15255
dcbf9037
JB		 15256 if (inst.vectype.elems > 0)
15257 for (i = 0; i < els; i++)
15258 if (inst.operands[i].vectype.type != NT_invtype)
477330fc
RM		 15259 {
15260 first_error (_("types specified in both the mnemonic and operands"));
15261 return badtype;
15262 }
dcbf9037 15263
5287ad62
JB		 15264 /* Duplicate inst.vectype elements here as necessary.
15265 FIXME: No idea if this is exactly the same as the ARM assembler,
15266 particularly when an insn takes one register and one non-register
15267 operand. */
15268 if (inst.vectype.elems == 1 && els > 1)
15269 {
15270 unsigned j;
15271 inst.vectype.elems = els;
15272 inst.vectype.el[key_el] = inst.vectype.el[0];
15273 for (j = 0; j < els; j++)
477330fc
RM		 15274 if (j != key_el)
15275 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15276 types[j]);
dcbf9037
JB		 15277 }
15278 else if (inst.vectype.elems == 0 && els > 0)
15279 {
15280 unsigned j;
15281 /* No types were given after the mnemonic, so look for types specified
477330fc
RM		 15282 after each operand. We allow some flexibility here; as long as the
15283 "key" operand has a type, we can infer the others. */
dcbf9037 15284 for (j = 0; j < els; j++)
477330fc
RM		 15285 if (inst.operands[j].vectype.type != NT_invtype)
15286 inst.vectype.el[j] = inst.operands[j].vectype;
dcbf9037
JB		 15287
15288 if (inst.operands[key_el].vectype.type != NT_invtype)
477330fc
RM		 15289 {
15290 for (j = 0; j < els; j++)
15291 if (inst.operands[j].vectype.type == NT_invtype)
15292 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15293 types[j]);
15294 }
dcbf9037 15295 else
477330fc
RM		 15296 {
15297 first_error (_("operand types can't be inferred"));
15298 return badtype;
15299 }
5287ad62
JB		 15300 }
15301 else if (inst.vectype.elems != els)
15302 {
dcbf9037 15303 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB		 15304 return badtype;
15305 }
15306
15307 for (pass = 0; pass < 2; pass++)
15308 {
15309 for (i = 0; i < els; i++)
477330fc
RM		 15310 {
15311 unsigned thisarg = types[i];
15312 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15313 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15314 enum neon_el_type g_type = inst.vectype.el[i].type;
15315 unsigned g_size = inst.vectype.el[i].size;
15316
15317 /* Decay more-specific signed & unsigned types to sign-insensitive
5287ad62 15318 integer types if sign-specific variants are unavailable. */
477330fc 15319 if ((g_type == NT_signed || g_type == NT_unsigned)
5287ad62
JB		 15320 && (types_allowed & N_SU_ALL) == 0)
15321 g_type = NT_integer;
15322
477330fc 15323 /* If only untyped args are allowed, decay any more specific types to
5287ad62
JB		 15324 them. Some instructions only care about signs for some element
15325 sizes, so handle that properly. */
477330fc 15326 if (((types_allowed & N_UNT) == 0)
91ff7894
MGD		 15327 && ((g_size == 8 && (types_allowed & N_8) != 0)
15328 || (g_size == 16 && (types_allowed & N_16) != 0)
15329 || (g_size == 32 && (types_allowed & N_32) != 0)
15330 || (g_size == 64 && (types_allowed & N_64) != 0)))
5287ad62
JB		 15331 g_type = NT_untyped;
15332
477330fc
RM		 15333 if (pass == 0)
15334 {
15335 if ((thisarg & N_KEY) != 0)
15336 {
15337 k_type = g_type;
15338 k_size = g_size;
15339 key_allowed = thisarg & ~N_KEY;
cc933301
JW		 15340
15341 /* Check architecture constraint on FP16 extension. */
15342 if (k_size == 16
15343 && k_type == NT_float
15344 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15345 {
15346 inst.error = _(BAD_FP16);
15347 return badtype;
15348 }
477330fc
RM		 15349 }
15350 }
15351 else
15352 {
15353 if ((thisarg & N_VFP) != 0)
15354 {
15355 enum neon_shape_el regshape;
15356 unsigned regwidth, match;
99b253c5
NC		 15357
15358 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15359 if (ns == NS_NULL)
15360 {
15361 first_error (_("invalid instruction shape"));
15362 return badtype;
15363 }
477330fc
RM		 15364 regshape = neon_shape_tab[ns].el[i];
15365 regwidth = neon_shape_el_size[regshape];
15366
15367 /* In VFP mode, operands must match register widths. If we
15368 have a key operand, use its width, else use the width of
15369 the current operand. */
15370 if (k_size != -1u)
15371 match = k_size;
15372 else
15373 match = g_size;
15374
9db2f6b4
RL		 15375 /* FP16 will use a single precision register. */
15376 if (regwidth == 32 && match == 16)
15377 {
15378 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15379 match = regwidth;
15380 else
15381 {
15382 inst.error = _(BAD_FP16);
15383 return badtype;
15384 }
15385 }
15386
477330fc
RM		 15387 if (regwidth != match)
15388 {
15389 first_error (_("operand size must match register width"));
15390 return badtype;
15391 }
15392 }
15393
15394 if ((thisarg & N_EQK) == 0)
15395 {
15396 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15397
15398 if ((given_type & types_allowed) == 0)
15399 {
a302e574 15400 first_error (BAD_SIMD_TYPE);
477330fc
RM		 15401 return badtype;
15402 }
15403 }
15404 else
15405 {
15406 enum neon_el_type mod_k_type = k_type;
15407 unsigned mod_k_size = k_size;
15408 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15409 if (g_type != mod_k_type || g_size != mod_k_size)
15410 {
15411 first_error (_("inconsistent types in Neon instruction"));
15412 return badtype;
15413 }
15414 }
15415 }
15416 }
5287ad62
JB		 15417 }
15418
15419 return inst.vectype.el[key_el];
15420}
15421
037e8744 15422/* Neon-style VFP instruction forwarding. */
5287ad62 15423
037e8744
JB		 15424/* Thumb VFP instructions have 0xE in the condition field. */
15425
15426static void
15427do_vfp_cond_or_thumb (void)
5287ad62 15428{
88714cb8
DG		 15429 inst.is_neon = 1;
15430
5287ad62 15431 if (thumb_mode)
037e8744 15432 inst.instruction |= 0xe0000000;
5287ad62 15433 else
037e8744 15434 inst.instruction |= inst.cond << 28;
5287ad62
JB		 15435}
15436
037e8744
JB		 15437/* Look up and encode a simple mnemonic, for use as a helper function for the
15438 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15439 etc. It is assumed that operand parsing has already been done, and that the
15440 operands are in the form expected by the given opcode (this isn't necessarily
15441 the same as the form in which they were parsed, hence some massaging must
15442 take place before this function is called).
15443 Checks current arch version against that in the looked-up opcode. */
5287ad62 15444
037e8744
JB		 15445static void
15446do_vfp_nsyn_opcode (const char *opname)
5287ad62 15447{
037e8744 15448 const struct asm_opcode *opcode;
5f4273c7 15449
21d799b5 15450 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 15451
037e8744
JB		 15452 if (!opcode)
15453 abort ();
5287ad62 15454
037e8744 15455 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
477330fc
RM		 15456 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15457 _(BAD_FPU));
5287ad62 15458
88714cb8
DG		 15459 inst.is_neon = 1;
15460
037e8744
JB		 15461 if (thumb_mode)
15462 {
15463 inst.instruction = opcode->tvalue;
15464 opcode->tencode ();
15465 }
15466 else
15467 {
15468 inst.instruction = (inst.cond << 28) | opcode->avalue;
15469 opcode->aencode ();
15470 }
15471}
5287ad62
JB		 15472
15473static void
037e8744 15474do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 15475{
037e8744
JB		 15476 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15477
9db2f6b4 15478 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB		 15479 {
15480 if (is_add)
477330fc 15481 do_vfp_nsyn_opcode ("fadds");
037e8744 15482 else
477330fc 15483 do_vfp_nsyn_opcode ("fsubs");
9db2f6b4
RL		 15484
15485 /* ARMv8.2 fp16 instruction. */
15486 if (rs == NS_HHH)
15487 do_scalar_fp16_v82_encode ();
037e8744
JB		 15488 }
15489 else
15490 {
15491 if (is_add)
477330fc 15492 do_vfp_nsyn_opcode ("faddd");
037e8744 15493 else
477330fc 15494 do_vfp_nsyn_opcode ("fsubd");
037e8744
JB		 15495 }
15496}
15497
15498/* Check operand types to see if this is a VFP instruction, and if so call
15499 PFN (). */
15500
15501static int
15502try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15503{
15504 enum neon_shape rs;
15505 struct neon_type_el et;
15506
15507 switch (args)
15508 {
15509 case 2:
9db2f6b4
RL		 15510 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15511 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
037e8744 15512 break;
5f4273c7 15513
037e8744 15514 case 3:
9db2f6b4
RL		 15515 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15516 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15517 N_F_ALL | N_KEY | N_VFP);
037e8744
JB		 15518 break;
15519
15520 default:
15521 abort ();
15522 }
15523
15524 if (et.type != NT_invtype)
15525 {
15526 pfn (rs);
15527 return SUCCESS;
15528 }
037e8744 15529
99b253c5 15530 inst.error = NULL;
037e8744
JB		 15531 return FAIL;
15532}
15533
15534static void
15535do_vfp_nsyn_mla_mls (enum neon_shape rs)
15536{
15537 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 15538
9db2f6b4 15539 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB		 15540 {
15541 if (is_mla)
477330fc 15542 do_vfp_nsyn_opcode ("fmacs");
037e8744 15543 else
477330fc 15544 do_vfp_nsyn_opcode ("fnmacs");
9db2f6b4
RL		 15545
15546 /* ARMv8.2 fp16 instruction. */
15547 if (rs == NS_HHH)
15548 do_scalar_fp16_v82_encode ();
037e8744
JB		 15549 }
15550 else
15551 {
15552 if (is_mla)
477330fc 15553 do_vfp_nsyn_opcode ("fmacd");
037e8744 15554 else
477330fc 15555 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB		 15556 }
15557}
15558
62f3b8c8
PB		 15559static void
15560do_vfp_nsyn_fma_fms (enum neon_shape rs)
15561{
15562 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15563
9db2f6b4 15564 if (rs == NS_FFF || rs == NS_HHH)
62f3b8c8
PB		 15565 {
15566 if (is_fma)
477330fc 15567 do_vfp_nsyn_opcode ("ffmas");
62f3b8c8 15568 else
477330fc 15569 do_vfp_nsyn_opcode ("ffnmas");
9db2f6b4
RL		 15570
15571 /* ARMv8.2 fp16 instruction. */
15572 if (rs == NS_HHH)
15573 do_scalar_fp16_v82_encode ();
62f3b8c8
PB		 15574 }
15575 else
15576 {
15577 if (is_fma)
477330fc 15578 do_vfp_nsyn_opcode ("ffmad");
62f3b8c8 15579 else
477330fc 15580 do_vfp_nsyn_opcode ("ffnmad");
62f3b8c8
PB		 15581 }
15582}
15583
037e8744
JB		 15584static void
15585do_vfp_nsyn_mul (enum neon_shape rs)
15586{
9db2f6b4
RL		 15587 if (rs == NS_FFF || rs == NS_HHH)
15588 {
15589 do_vfp_nsyn_opcode ("fmuls");
15590
15591 /* ARMv8.2 fp16 instruction. */
15592 if (rs == NS_HHH)
15593 do_scalar_fp16_v82_encode ();
15594 }
037e8744
JB		 15595 else
15596 do_vfp_nsyn_opcode ("fmuld");
15597}
15598
15599static void
15600do_vfp_nsyn_abs_neg (enum neon_shape rs)
15601{
15602 int is_neg = (inst.instruction & 0x80) != 0;
9db2f6b4 15603 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
037e8744 15604
9db2f6b4 15605 if (rs == NS_FF || rs == NS_HH)
037e8744
JB		 15606 {
15607 if (is_neg)
477330fc 15608 do_vfp_nsyn_opcode ("fnegs");
037e8744 15609 else
477330fc 15610 do_vfp_nsyn_opcode ("fabss");
9db2f6b4
RL		 15611
15612 /* ARMv8.2 fp16 instruction. */
15613 if (rs == NS_HH)
15614 do_scalar_fp16_v82_encode ();
037e8744
JB		 15615 }
15616 else
15617 {
15618 if (is_neg)
477330fc 15619 do_vfp_nsyn_opcode ("fnegd");
037e8744 15620 else
477330fc 15621 do_vfp_nsyn_opcode ("fabsd");
037e8744
JB		 15622 }
15623}
15624
15625/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15626 insns belong to Neon, and are handled elsewhere. */
15627
15628static void
15629do_vfp_nsyn_ldm_stm (int is_dbmode)
15630{
15631 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15632 if (is_ldm)
15633 {
15634 if (is_dbmode)
477330fc 15635 do_vfp_nsyn_opcode ("fldmdbs");
037e8744 15636 else
477330fc 15637 do_vfp_nsyn_opcode ("fldmias");
037e8744
JB		 15638 }
15639 else
15640 {
15641 if (is_dbmode)
477330fc 15642 do_vfp_nsyn_opcode ("fstmdbs");
037e8744 15643 else
477330fc 15644 do_vfp_nsyn_opcode ("fstmias");
037e8744
JB		 15645 }
15646}
15647
037e8744
JB		 15648static void
15649do_vfp_nsyn_sqrt (void)
15650{
9db2f6b4
RL		 15651 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15652 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 15653
9db2f6b4
RL		 15654 if (rs == NS_FF || rs == NS_HH)
15655 {
15656 do_vfp_nsyn_opcode ("fsqrts");
15657
15658 /* ARMv8.2 fp16 instruction. */
15659 if (rs == NS_HH)
15660 do_scalar_fp16_v82_encode ();
15661 }
037e8744
JB		 15662 else
15663 do_vfp_nsyn_opcode ("fsqrtd");
15664}
15665
15666static void
15667do_vfp_nsyn_div (void)
15668{
9db2f6b4 15669 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15670 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15671 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15672
9db2f6b4
RL		 15673 if (rs == NS_FFF || rs == NS_HHH)
15674 {
15675 do_vfp_nsyn_opcode ("fdivs");
15676
15677 /* ARMv8.2 fp16 instruction. */
15678 if (rs == NS_HHH)
15679 do_scalar_fp16_v82_encode ();
15680 }
037e8744
JB		 15681 else
15682 do_vfp_nsyn_opcode ("fdivd");
15683}
15684
15685static void
15686do_vfp_nsyn_nmul (void)
15687{
9db2f6b4 15688 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15689 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15690 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15691
9db2f6b4 15692 if (rs == NS_FFF || rs == NS_HHH)
037e8744 15693 {
88714cb8 15694 NEON_ENCODE (SINGLE, inst);
037e8744 15695 do_vfp_sp_dyadic ();
9db2f6b4
RL		 15696
15697 /* ARMv8.2 fp16 instruction. */
15698 if (rs == NS_HHH)
15699 do_scalar_fp16_v82_encode ();
037e8744
JB		 15700 }
15701 else
15702 {
88714cb8 15703 NEON_ENCODE (DOUBLE, inst);
037e8744
JB		 15704 do_vfp_dp_rd_rn_rm ();
15705 }
15706 do_vfp_cond_or_thumb ();
9db2f6b4 15707
037e8744
JB		 15708}
15709
1b883319
AV		 15710/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15711 (0, 1, 2, 3). */
15712
15713static unsigned
15714neon_logbits (unsigned x)
15715{
15716 return ffs (x) - 4;
15717}
15718
15719#define LOW4(R) ((R) & 0xf)
15720#define HI1(R) (((R) >> 4) & 1)
15721
15722static unsigned
15723mve_get_vcmp_vpt_cond (struct neon_type_el et)
15724{
15725 switch (et.type)
15726 {
15727 default:
15728 first_error (BAD_EL_TYPE);
15729 return 0;
15730 case NT_float:
15731 switch (inst.operands[0].imm)
15732 {
15733 default:
15734 first_error (_("invalid condition"));
15735 return 0;
15736 case 0x0:
15737 /* eq. */
15738 return 0;
15739 case 0x1:
15740 /* ne. */
15741 return 1;
15742 case 0xa:
15743 /* ge/ */
15744 return 4;
15745 case 0xb:
15746 /* lt. */
15747 return 5;
15748 case 0xc:
15749 /* gt. */
15750 return 6;
15751 case 0xd:
15752 /* le. */
15753 return 7;
15754 }
15755 case NT_integer:
15756 /* only accept eq and ne. */
15757 if (inst.operands[0].imm > 1)
15758 {
15759 first_error (_("invalid condition"));
15760 return 0;
15761 }
15762 return inst.operands[0].imm;
15763 case NT_unsigned:
15764 if (inst.operands[0].imm == 0x2)
15765 return 2;
15766 else if (inst.operands[0].imm == 0x8)
15767 return 3;
15768 else
15769 {
15770 first_error (_("invalid condition"));
15771 return 0;
15772 }
15773 case NT_signed:
15774 switch (inst.operands[0].imm)
15775 {
15776 default:
15777 first_error (_("invalid condition"));
15778 return 0;
15779 case 0xa:
15780 /* ge. */
15781 return 4;
15782 case 0xb:
15783 /* lt. */
15784 return 5;
15785 case 0xc:
15786 /* gt. */
15787 return 6;
15788 case 0xd:
15789 /* le. */
15790 return 7;
15791 }
15792 }
15793 /* Should be unreachable. */
15794 abort ();
15795}
15796
efd0b310
SP		 15797/* For VCTP (create vector tail predicate) in MVE. */
15798static void
15799do_mve_vctp (void)
15800{
15801 int dt = 0;
15802 unsigned size = 0x0;
15803
15804 if (inst.cond > COND_ALWAYS)
15805 inst.pred_insn_type = INSIDE_VPT_INSN;
15806 else
15807 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15808
15809 /* This is a typical MVE instruction which has no type but have size 8, 16,
15810 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15811 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15812 if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped))
15813 dt = inst.vectype.el[0].size;
15814
15815 /* Setting this does not indicate an actual NEON instruction, but only
15816 indicates that the mnemonic accepts neon-style type suffixes. */
15817 inst.is_neon = 1;
15818
15819 switch (dt)
15820 {
15821 case 8:
15822 break;
15823 case 16:
15824 size = 0x1; break;
15825 case 32:
15826 size = 0x2; break;
15827 case 64:
15828 size = 0x3; break;
15829 default:
15830 first_error (_("Type is not allowed for this instruction"));
15831 }
15832 inst.instruction |= size << 20;
15833 inst.instruction |= inst.operands[0].reg << 16;
15834}
15835
1b883319
AV		 15836static void
15837do_mve_vpt (void)
15838{
15839 /* We are dealing with a vector predicated block. */
15840 if (inst.operands[0].present)
15841 {
15842 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15843 struct neon_type_el et
15844 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15845 N_EQK);
15846
15847 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15848
15849 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15850
15851 if (et.type == NT_invtype)
15852 return;
15853
15854 if (et.type == NT_float)
15855 {
15856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15857 BAD_FPU);
15858 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
15859 inst.instruction |= (et.size == 16) << 28;
15860 inst.instruction |= 0x3 << 20;
15861 }
15862 else
15863 {
15864 constraint (et.size != 8 && et.size != 16 && et.size != 32,
15865 BAD_EL_TYPE);
15866 inst.instruction |= 1 << 28;
15867 inst.instruction |= neon_logbits (et.size) << 20;
15868 }
15869
15870 if (inst.operands[2].isquad)
15871 {
15872 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15873 inst.instruction |= LOW4 (inst.operands[2].reg);
15874 inst.instruction |= (fcond & 0x2) >> 1;
15875 }
15876 else
15877 {
15878 if (inst.operands[2].reg == REG_SP)
15879 as_tsktsk (MVE_BAD_SP);
15880 inst.instruction |= 1 << 6;
15881 inst.instruction |= (fcond & 0x2) << 4;
15882 inst.instruction |= inst.operands[2].reg;
15883 }
15884 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15885 inst.instruction |= (fcond & 0x4) << 10;
15886 inst.instruction |= (fcond & 0x1) << 7;
15887
15888 }
15889 set_pred_insn_type (VPT_INSN);
15890 now_pred.cc = 0;
15891 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15892 | ((inst.instruction & 0xe000) >> 13);
15893 now_pred.warn_deprecated = FALSE;
15894 now_pred.type = VECTOR_PRED;
15895 inst.is_neon = 1;
15896}
15897
15898static void
15899do_mve_vcmp (void)
15900{
15901 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
15902 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15903 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
15904 if (!inst.operands[2].present)
15905 first_error (_("MVE vector or ARM register expected"));
15906 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15907
15908 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15909 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15910 && inst.operands[1].isquad)
15911 {
15912 inst.instruction = N_MNEM_vcmp;
15913 inst.cond = 0x10;
15914 }
15915
15916 if (inst.cond > COND_ALWAYS)
15917 inst.pred_insn_type = INSIDE_VPT_INSN;
15918 else
15919 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15920
15921 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15922 struct neon_type_el et
15923 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15924 N_EQK);
15925
15926 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15927 && !inst.operands[2].iszr, BAD_PC);
15928
15929 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15930
15931 inst.instruction = 0xee010f00;
15932 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15933 inst.instruction |= (fcond & 0x4) << 10;
15934 inst.instruction |= (fcond & 0x1) << 7;
15935 if (et.type == NT_float)
15936 {
15937 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15938 BAD_FPU);
15939 inst.instruction |= (et.size == 16) << 28;
15940 inst.instruction |= 0x3 << 20;
15941 }
15942 else
15943 {
15944 inst.instruction |= 1 << 28;
15945 inst.instruction |= neon_logbits (et.size) << 20;
15946 }
15947 if (inst.operands[2].isquad)
15948 {
15949 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15950 inst.instruction |= (fcond & 0x2) >> 1;
15951 inst.instruction |= LOW4 (inst.operands[2].reg);
15952 }
15953 else
15954 {
15955 if (inst.operands[2].reg == REG_SP)
15956 as_tsktsk (MVE_BAD_SP);
15957 inst.instruction |= 1 << 6;
15958 inst.instruction |= (fcond & 0x2) << 4;
15959 inst.instruction |= inst.operands[2].reg;
15960 }
15961
15962 inst.is_neon = 1;
15963 return;
15964}
15965
935295b5
AV		 15966static void
15967do_mve_vmaxa_vmina (void)
15968{
15969 if (inst.cond > COND_ALWAYS)
15970 inst.pred_insn_type = INSIDE_VPT_INSN;
15971 else
15972 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15973
15974 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15975 struct neon_type_el et
15976 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
15977
15978 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15979 inst.instruction |= neon_logbits (et.size) << 18;
15980 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15981 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15982 inst.instruction |= LOW4 (inst.operands[1].reg);
15983 inst.is_neon = 1;
15984}
15985
f30ee27c
AV		 15986static void
15987do_mve_vfmas (void)
15988{
15989 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15990 struct neon_type_el et
15991 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
15992
15993 if (inst.cond > COND_ALWAYS)
15994 inst.pred_insn_type = INSIDE_VPT_INSN;
15995 else
15996 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15997
15998 if (inst.operands[2].reg == REG_SP)
15999 as_tsktsk (MVE_BAD_SP);
16000 else if (inst.operands[2].reg == REG_PC)
16001 as_tsktsk (MVE_BAD_PC);
16002
16003 inst.instruction |= (et.size == 16) << 28;
16004 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16005 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16006 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16007 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16008 inst.instruction |= inst.operands[2].reg;
16009 inst.is_neon = 1;
16010}
16011
b409bdb6
AV		 16012static void
16013do_mve_viddup (void)
16014{
16015 if (inst.cond > COND_ALWAYS)
16016 inst.pred_insn_type = INSIDE_VPT_INSN;
16017 else
16018 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16019
16020 unsigned imm = inst.relocs[0].exp.X_add_number;
16021 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
16022 _("immediate must be either 1, 2, 4 or 8"));
16023
16024 enum neon_shape rs;
16025 struct neon_type_el et;
16026 unsigned Rm;
16027 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
16028 {
16029 rs = neon_select_shape (NS_QRI, NS_NULL);
16030 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
16031 Rm = 7;
16032 }
16033 else
16034 {
16035 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
16036 if (inst.operands[2].reg == REG_SP)
16037 as_tsktsk (MVE_BAD_SP);
16038 else if (inst.operands[2].reg == REG_PC)
16039 first_error (BAD_PC);
16040
16041 rs = neon_select_shape (NS_QRRI, NS_NULL);
16042 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
16043 Rm = inst.operands[2].reg >> 1;
16044 }
16045 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16046 inst.instruction |= neon_logbits (et.size) << 20;
16047 inst.instruction |= inst.operands[1].reg << 16;
16048 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16049 inst.instruction |= (imm > 2) << 7;
16050 inst.instruction |= Rm << 1;
16051 inst.instruction |= (imm == 2 || imm == 8);
16052 inst.is_neon = 1;
16053}
16054
2d78f95b
AV		 16055static void
16056do_mve_vmlas (void)
16057{
16058 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16059 struct neon_type_el et
16060 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16061
16062 if (inst.operands[2].reg == REG_PC)
16063 as_tsktsk (MVE_BAD_PC);
16064 else if (inst.operands[2].reg == REG_SP)
16065 as_tsktsk (MVE_BAD_SP);
16066
16067 if (inst.cond > COND_ALWAYS)
16068 inst.pred_insn_type = INSIDE_VPT_INSN;
16069 else
16070 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16071
16072 inst.instruction |= (et.type == NT_unsigned) << 28;
16073 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16074 inst.instruction |= neon_logbits (et.size) << 20;
16075 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16076 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16077 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16078 inst.instruction |= inst.operands[2].reg;
16079 inst.is_neon = 1;
16080}
16081
acca5630
AV		 16082static void
16083do_mve_vshll (void)
16084{
16085 struct neon_type_el et
16086 = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY);
16087
16088 if (inst.cond > COND_ALWAYS)
16089 inst.pred_insn_type = INSIDE_VPT_INSN;
16090 else
16091 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16092
16093 int imm = inst.operands[2].imm;
16094 constraint (imm < 1 || (unsigned)imm > et.size,
16095 _("immediate value out of range"));
16096
16097 if ((unsigned)imm == et.size)
16098 {
16099 inst.instruction |= neon_logbits (et.size) << 18;
16100 inst.instruction |= 0x110001;
16101 }
16102 else
16103 {
16104 inst.instruction |= (et.size + imm) << 16;
16105 inst.instruction |= 0x800140;
16106 }
16107
16108 inst.instruction |= (et.type == NT_unsigned) << 28;
16109 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16110 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16111 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16112 inst.instruction |= LOW4 (inst.operands[1].reg);
16113 inst.is_neon = 1;
16114}
16115
16116static void
16117do_mve_vshlc (void)
16118{
16119 if (inst.cond > COND_ALWAYS)
16120 inst.pred_insn_type = INSIDE_VPT_INSN;
16121 else
16122 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16123
16124 if (inst.operands[1].reg == REG_PC)
16125 as_tsktsk (MVE_BAD_PC);
16126 else if (inst.operands[1].reg == REG_SP)
16127 as_tsktsk (MVE_BAD_SP);
16128
16129 int imm = inst.operands[2].imm;
16130 constraint (imm < 1 || imm > 32, _("immediate value out of range"));
16131
16132 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16133 inst.instruction |= (imm & 0x1f) << 16;
16134 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16135 inst.instruction |= inst.operands[1].reg;
16136 inst.is_neon = 1;
16137}
16138
4aa88b50
AV		 16139static void
16140do_mve_vshrn (void)
16141{
16142 unsigned types;
16143 switch (inst.instruction)
16144 {
16145 case M_MNEM_vshrnt:
16146 case M_MNEM_vshrnb:
16147 case M_MNEM_vrshrnt:
16148 case M_MNEM_vrshrnb:
16149 types = N_I16 | N_I32;
16150 break;
16151 case M_MNEM_vqshrnt:
16152 case M_MNEM_vqshrnb:
16153 case M_MNEM_vqrshrnt:
16154 case M_MNEM_vqrshrnb:
16155 types = N_U16 | N_U32 | N_S16 | N_S32;
16156 break;
16157 case M_MNEM_vqshrunt:
16158 case M_MNEM_vqshrunb:
16159 case M_MNEM_vqrshrunt:
16160 case M_MNEM_vqrshrunb:
16161 types = N_S16 | N_S32;
16162 break;
16163 default:
16164 abort ();
16165 }
16166
16167 struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
16168
16169 if (inst.cond > COND_ALWAYS)
16170 inst.pred_insn_type = INSIDE_VPT_INSN;
16171 else
16172 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16173
16174 unsigned Qd = inst.operands[0].reg;
16175 unsigned Qm = inst.operands[1].reg;
16176 unsigned imm = inst.operands[2].imm;
16177 constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
16178 et.size == 16
16179 ? _("immediate operand expected in the range [1,8]")
16180 : _("immediate operand expected in the range [1,16]"));
16181
16182 inst.instruction |= (et.type == NT_unsigned) << 28;
16183 inst.instruction |= HI1 (Qd) << 22;
16184 inst.instruction |= (et.size - imm) << 16;
16185 inst.instruction |= LOW4 (Qd) << 12;
16186 inst.instruction |= HI1 (Qm) << 5;
16187 inst.instruction |= LOW4 (Qm);
16188 inst.is_neon = 1;
16189}
16190
1be7aba3
AV		 16191static void
16192do_mve_vqmovn (void)
16193{
16194 struct neon_type_el et;
16195 if (inst.instruction == M_MNEM_vqmovnt
16196 || inst.instruction == M_MNEM_vqmovnb)
16197 et = neon_check_type (2, NS_QQ, N_EQK,
16198 N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
16199 else
16200 et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
16201
16202 if (inst.cond > COND_ALWAYS)
16203 inst.pred_insn_type = INSIDE_VPT_INSN;
16204 else
16205 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16206
16207 inst.instruction |= (et.type == NT_unsigned) << 28;
16208 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16209 inst.instruction |= (et.size == 32) << 18;
16210 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16211 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16212 inst.instruction |= LOW4 (inst.operands[1].reg);
16213 inst.is_neon = 1;
16214}
16215
3063888e
AV		 16216static void
16217do_mve_vpsel (void)
16218{
16219 neon_select_shape (NS_QQQ, NS_NULL);
16220
16221 if (inst.cond > COND_ALWAYS)
16222 inst.pred_insn_type = INSIDE_VPT_INSN;
16223 else
16224 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16225
16226 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16227 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16228 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16229 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16230 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16231 inst.instruction |= LOW4 (inst.operands[2].reg);
16232 inst.is_neon = 1;
16233}
16234
16235static void
16236do_mve_vpnot (void)
16237{
16238 if (inst.cond > COND_ALWAYS)
16239 inst.pred_insn_type = INSIDE_VPT_INSN;
16240 else
16241 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16242}
16243
935295b5
AV		 16244static void
16245do_mve_vmaxnma_vminnma (void)
16246{
16247 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16248 struct neon_type_el et
16249 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
16250
16251 if (inst.cond > COND_ALWAYS)
16252 inst.pred_insn_type = INSIDE_VPT_INSN;
16253 else
16254 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16255
16256 inst.instruction |= (et.size == 16) << 28;
16257 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16258 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16259 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16260 inst.instruction |= LOW4 (inst.operands[1].reg);
16261 inst.is_neon = 1;
16262}
16263
5d281bf0
AV		 16264static void
16265do_mve_vcmul (void)
16266{
16267 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
16268 struct neon_type_el et
16269 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
16270
16271 if (inst.cond > COND_ALWAYS)
16272 inst.pred_insn_type = INSIDE_VPT_INSN;
16273 else
16274 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16275
16276 unsigned rot = inst.relocs[0].exp.X_add_number;
16277 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
16278 _("immediate out of range"));
16279
16280 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16281 || inst.operands[0].reg == inst.operands[2].reg))
16282 as_tsktsk (BAD_MVE_SRCDEST);
16283
16284 inst.instruction |= (et.size == 32) << 28;
16285 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16286 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16287 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16288 inst.instruction |= (rot > 90) << 12;
16289 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16290 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16291 inst.instruction |= LOW4 (inst.operands[2].reg);
16292 inst.instruction |= (rot == 90 || rot == 270);
16293 inst.is_neon = 1;
16294}
16295
1f6234a3
AV		 16296/* To handle the Low Overhead Loop instructions
16297 in Armv8.1-M Mainline and MVE. */
16298static void
16299do_t_loloop (void)
16300{
16301 unsigned long insn = inst.instruction;
16302
16303 inst.instruction = THUMB_OP32 (inst.instruction);
16304
16305 if (insn == T_MNEM_lctp)
16306 return;
16307
16308 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN);
16309
16310 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16311 {
16312 struct neon_type_el et
16313 = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16314 inst.instruction |= neon_logbits (et.size) << 20;
16315 inst.is_neon = 1;
16316 }
16317
16318 switch (insn)
16319 {
16320 case T_MNEM_letp:
16321 constraint (!inst.operands[0].present,
16322 _("expected LR"));
16323 /* fall through. */
16324 case T_MNEM_le:
16325 /* le <label>. */
16326 if (!inst.operands[0].present)
16327 inst.instruction |= 1 << 21;
16328
16329 v8_1_loop_reloc (TRUE);
16330 break;
16331
16332 case T_MNEM_wls:
16333 case T_MNEM_wlstp:
16334 v8_1_loop_reloc (FALSE);
16335 /* fall through. */
16336 case T_MNEM_dlstp:
16337 case T_MNEM_dls:
16338 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16339
16340 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16341 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16342 else if (inst.operands[1].reg == REG_PC)
16343 as_tsktsk (MVE_BAD_PC);
16344 if (inst.operands[1].reg == REG_SP)
16345 as_tsktsk (MVE_BAD_SP);
16346
16347 inst.instruction |= (inst.operands[1].reg << 16);
16348 break;
16349
16350 default:
16351 abort ();
16352 }
16353}
16354
16355
037e8744
JB		 16356static void
16357do_vfp_nsyn_cmp (void)
16358{
9db2f6b4 16359 enum neon_shape rs;
1b883319
AV		 16360 if (!inst.operands[0].isreg)
16361 {
16362 do_mve_vcmp ();
16363 return;
16364 }
16365 else
16366 {
16367 constraint (inst.operands[2].present, BAD_SYNTAX);
16368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
16369 BAD_FPU);
16370 }
16371
037e8744
JB		 16372 if (inst.operands[1].isreg)
16373 {
9db2f6b4
RL		 16374 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
16375 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 16376
9db2f6b4 16377 if (rs == NS_FF || rs == NS_HH)
477330fc
RM		 16378 {
16379 NEON_ENCODE (SINGLE, inst);
16380 do_vfp_sp_monadic ();
16381 }
037e8744 16382 else
477330fc
RM		 16383 {
16384 NEON_ENCODE (DOUBLE, inst);
16385 do_vfp_dp_rd_rm ();
16386 }
037e8744
JB		 16387 }
16388 else
16389 {
9db2f6b4
RL		 16390 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
16391 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
037e8744
JB		 16392
16393 switch (inst.instruction & 0x0fffffff)
477330fc
RM		 16394 {
16395 case N_MNEM_vcmp:
16396 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16397 break;
16398 case N_MNEM_vcmpe:
16399 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16400 break;
16401 default:
16402 abort ();
16403 }
5f4273c7 16404
9db2f6b4 16405 if (rs == NS_FI || rs == NS_HI)
477330fc
RM		 16406 {
16407 NEON_ENCODE (SINGLE, inst);
16408 do_vfp_sp_compare_z ();
16409 }
037e8744 16410 else
477330fc
RM		 16411 {
16412 NEON_ENCODE (DOUBLE, inst);
16413 do_vfp_dp_rd ();
16414 }
037e8744
JB		 16415 }
16416 do_vfp_cond_or_thumb ();
9db2f6b4
RL		 16417
16418 /* ARMv8.2 fp16 instruction. */
16419 if (rs == NS_HI || rs == NS_HH)
16420 do_scalar_fp16_v82_encode ();
037e8744
JB		 16421}
16422
16423static void
16424nsyn_insert_sp (void)
16425{
16426 inst.operands[1] = inst.operands[0];
16427 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 16428 inst.operands[0].reg = REG_SP;
037e8744
JB		 16429 inst.operands[0].isreg = 1;
16430 inst.operands[0].writeback = 1;
16431 inst.operands[0].present = 1;
16432}
16433
16434static void
16435do_vfp_nsyn_push (void)
16436{
16437 nsyn_insert_sp ();
b126985e
NC		 16438
16439 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16440 _("register list must contain at least 1 and at most 16 "
16441 "registers"));
16442
037e8744
JB		 16443 if (inst.operands[1].issingle)
16444 do_vfp_nsyn_opcode ("fstmdbs");
16445 else
16446 do_vfp_nsyn_opcode ("fstmdbd");
16447}
16448
16449static void
16450do_vfp_nsyn_pop (void)
16451{
16452 nsyn_insert_sp ();
b126985e
NC		 16453
16454 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16455 _("register list must contain at least 1 and at most 16 "
16456 "registers"));
16457
037e8744 16458 if (inst.operands[1].issingle)
22b5b651 16459 do_vfp_nsyn_opcode ("fldmias");
037e8744 16460 else
22b5b651 16461 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB		 16462}
16463
16464/* Fix up Neon data-processing instructions, ORing in the correct bits for
16465 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16466
88714cb8
DG		 16467static void
16468neon_dp_fixup (struct arm_it* insn)
037e8744 16469{
88714cb8
DG		 16470 unsigned int i = insn->instruction;
16471 insn->is_neon = 1;
16472
037e8744
JB		 16473 if (thumb_mode)
16474 {
16475 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16476 if (i & (1 << 24))
477330fc 16477 i |= 1 << 28;
5f4273c7 16478
037e8744 16479 i &= ~(1 << 24);
5f4273c7 16480
037e8744
JB		 16481 i |= 0xef000000;
16482 }
16483 else
16484 i |= 0xf2000000;
5f4273c7 16485
88714cb8 16486 insn->instruction = i;
037e8744
JB		 16487}
16488
5ee91343 16489static void
7df54120 16490mve_encode_qqr (int size, int U, int fp)
5ee91343
AV		 16491{
16492 if (inst.operands[2].reg == REG_SP)
16493 as_tsktsk (MVE_BAD_SP);
16494 else if (inst.operands[2].reg == REG_PC)
16495 as_tsktsk (MVE_BAD_PC);
16496
16497 if (fp)
16498 {
16499 /* vadd. */
16500 if (((unsigned)inst.instruction) == 0xd00)
16501 inst.instruction = 0xee300f40;
16502 /* vsub. */
16503 else if (((unsigned)inst.instruction) == 0x200d00)
16504 inst.instruction = 0xee301f40;
a8465a06
AV		 16505 /* vmul. */
16506 else if (((unsigned)inst.instruction) == 0x1000d10)
16507 inst.instruction = 0xee310e60;
5ee91343
AV		 16508
16509 /* Setting size which is 1 for F16 and 0 for F32. */
16510 inst.instruction |= (size == 16) << 28;
16511 }
16512 else
16513 {
16514 /* vadd. */
16515 if (((unsigned)inst.instruction) == 0x800)
16516 inst.instruction = 0xee010f40;
16517 /* vsub. */
16518 else if (((unsigned)inst.instruction) == 0x1000800)
16519 inst.instruction = 0xee011f40;
7df54120
AV		 16520 /* vhadd. */
16521 else if (((unsigned)inst.instruction) == 0)
16522 inst.instruction = 0xee000f40;
16523 /* vhsub. */
16524 else if (((unsigned)inst.instruction) == 0x200)
16525 inst.instruction = 0xee001f40;
a8465a06
AV		 16526 /* vmla. */
16527 else if (((unsigned)inst.instruction) == 0x900)
16528 inst.instruction = 0xee010e40;
16529 /* vmul. */
16530 else if (((unsigned)inst.instruction) == 0x910)
16531 inst.instruction = 0xee011e60;
16532 /* vqadd. */
16533 else if (((unsigned)inst.instruction) == 0x10)
16534 inst.instruction = 0xee000f60;
16535 /* vqsub. */
16536 else if (((unsigned)inst.instruction) == 0x210)
16537 inst.instruction = 0xee001f60;
42b16635
AV		 16538 /* vqrdmlah. */
16539 else if (((unsigned)inst.instruction) == 0x3000b10)
16540 inst.instruction = 0xee000e40;
16541 /* vqdmulh. */
16542 else if (((unsigned)inst.instruction) == 0x0000b00)
16543 inst.instruction = 0xee010e60;
16544 /* vqrdmulh. */
16545 else if (((unsigned)inst.instruction) == 0x1000b00)
16546 inst.instruction = 0xfe010e60;
7df54120
AV		 16547
16548 /* Set U-bit. */
16549 inst.instruction |= U << 28;
16550
5ee91343
AV		 16551 /* Setting bits for size. */
16552 inst.instruction |= neon_logbits (size) << 20;
16553 }
16554 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16555 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16556 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16557 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16558 inst.instruction |= inst.operands[2].reg;
16559 inst.is_neon = 1;
16560}
16561
a302e574
AV		 16562static void
16563mve_encode_rqq (unsigned bit28, unsigned size)
16564{
16565 inst.instruction |= bit28 << 28;
16566 inst.instruction |= neon_logbits (size) << 20;
16567 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16568 inst.instruction |= inst.operands[0].reg << 12;
16569 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16570 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16571 inst.instruction |= LOW4 (inst.operands[2].reg);
16572 inst.is_neon = 1;
16573}
16574
886e1c73
AV		 16575static void
16576mve_encode_qqq (int ubit, int size)
16577{
16578
16579 inst.instruction |= (ubit != 0) << 28;
16580 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16581 inst.instruction |= neon_logbits (size) << 20;
16582 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16583 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16584 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16585 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16586 inst.instruction |= LOW4 (inst.operands[2].reg);
16587
16588 inst.is_neon = 1;
16589}
16590
26c1e780
AV		 16591static void
16592mve_encode_rq (unsigned bit28, unsigned size)
16593{
16594 inst.instruction |= bit28 << 28;
16595 inst.instruction |= neon_logbits (size) << 18;
16596 inst.instruction |= inst.operands[0].reg << 12;
16597 inst.instruction |= LOW4 (inst.operands[1].reg);
16598 inst.is_neon = 1;
16599}
886e1c73 16600
93925576
AV		 16601static void
16602mve_encode_rrqq (unsigned U, unsigned size)
16603{
16604 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16605
16606 inst.instruction |= U << 28;
16607 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16608 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16609 inst.instruction |= (size == 32) << 16;
16610 inst.instruction |= inst.operands[0].reg << 12;
16611 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16612 inst.instruction |= inst.operands[3].reg;
16613 inst.is_neon = 1;
16614}
16615
037e8744
JB		 16616/* Encode insns with bit pattern:
16617
16618 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16619 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 16620
037e8744
JB		 16621 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16622 different meaning for some instruction. */
16623
16624static void
16625neon_three_same (int isquad, int ubit, int size)
16626{
16627 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16628 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16629 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16630 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16631 inst.instruction |= LOW4 (inst.operands[2].reg);
16632 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16633 inst.instruction |= (isquad != 0) << 6;
16634 inst.instruction |= (ubit != 0) << 24;
16635 if (size != -1)
16636 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 16637
88714cb8 16638 neon_dp_fixup (&inst);
037e8744
JB		 16639}
16640
16641/* Encode instructions of the form:
16642
16643 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16644 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB		 16645
16646 Don't write size if SIZE == -1. */
16647
16648static void
16649neon_two_same (int qbit, int ubit, int size)
16650{
16651 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16652 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16653 inst.instruction |= LOW4 (inst.operands[1].reg);
16654 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16655 inst.instruction |= (qbit != 0) << 6;
16656 inst.instruction |= (ubit != 0) << 24;
16657
16658 if (size != -1)
16659 inst.instruction |= neon_logbits (size) << 18;
16660
88714cb8 16661 neon_dp_fixup (&inst);
5287ad62
JB		 16662}
16663
7df54120
AV		 16664enum vfp_or_neon_is_neon_bits
16665{
16666NEON_CHECK_CC = 1,
16667NEON_CHECK_ARCH = 2,
16668NEON_CHECK_ARCH8 = 4
16669};
16670
16671/* Call this function if an instruction which may have belonged to the VFP or
16672 Neon instruction sets, but turned out to be a Neon instruction (due to the
16673 operand types involved, etc.). We have to check and/or fix-up a couple of
16674 things:
16675
16676 - Make sure the user hasn't attempted to make a Neon instruction
16677 conditional.
16678 - Alter the value in the condition code field if necessary.
16679 - Make sure that the arch supports Neon instructions.
16680
16681 Which of these operations take place depends on bits from enum
16682 vfp_or_neon_is_neon_bits.
16683
16684 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16685 current instruction's condition is COND_ALWAYS, the condition field is
16686 changed to inst.uncond_value. This is necessary because instructions shared
16687 between VFP and Neon may be conditional for the VFP variants only, and the
16688 unconditional Neon version must have, e.g., 0xF in the condition field. */
16689
16690static int
16691vfp_or_neon_is_neon (unsigned check)
16692{
16693/* Conditions are always legal in Thumb mode (IT blocks). */
16694if (!thumb_mode && (check & NEON_CHECK_CC))
16695 {
16696 if (inst.cond != COND_ALWAYS)
16697 {
16698 first_error (_(BAD_COND));
16699 return FAIL;
16700 }
16701 if (inst.uncond_value != -1)
16702 inst.instruction |= inst.uncond_value << 28;
16703 }
16704
16705
16706 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16707 || ((check & NEON_CHECK_ARCH8)
16708 && !mark_feature_used (&fpu_neon_ext_armv8)))
16709 {
16710 first_error (_(BAD_FPU));
16711 return FAIL;
16712 }
16713
16714return SUCCESS;
16715}
16716
64c350f2
AV		 16717
16718/* Return TRUE if the SIMD instruction is available for the current
16719 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16720 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16721 vfp_or_neon_is_neon for the NEON specific checks. */
16722
16723static bfd_boolean
7df54120
AV		 16724check_simd_pred_availability (int fp, unsigned check)
16725{
16726if (inst.cond > COND_ALWAYS)
16727 {
16728 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16729 {
16730 inst.error = BAD_FPU;
64c350f2 16731 return FALSE;
7df54120
AV		 16732 }
16733 inst.pred_insn_type = INSIDE_VPT_INSN;
16734 }
16735else if (inst.cond < COND_ALWAYS)
16736 {
16737 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16738 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16739 else if (vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16740 return FALSE;
7df54120
AV		 16741 }
16742else
16743 {
16744 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16745 && vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16746 return FALSE;
7df54120
AV		 16747
16748 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16749 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16750 }
64c350f2 16751return TRUE;
7df54120
AV		 16752}
16753
5287ad62
JB		 16754/* Neon instruction encoders, in approximate order of appearance. */
16755
16756static void
16757do_neon_dyadic_i_su (void)
16758{
64c350f2 16759 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
7df54120
AV		 16760 return;
16761
16762 enum neon_shape rs;
16763 struct neon_type_el et;
16764 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16765 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16766 else
16767 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16768
16769 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16770
16771
16772 if (rs != NS_QQR)
16773 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16774 else
16775 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
5287ad62
JB		 16776}
16777
16778static void
16779do_neon_dyadic_i64_su (void)
16780{
64c350f2 16781 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
a8465a06
AV		 16782 return;
16783 enum neon_shape rs;
16784 struct neon_type_el et;
16785 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16786 {
16787 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16788 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16789 }
16790 else
16791 {
16792 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16793 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16794 }
16795 if (rs == NS_QQR)
16796 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16797 else
16798 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 16799}
16800
16801static void
16802neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
477330fc 16803 unsigned immbits)
5287ad62
JB		 16804{
16805 unsigned size = et.size >> 3;
16806 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16807 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16808 inst.instruction |= LOW4 (inst.operands[1].reg);
16809 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16810 inst.instruction |= (isquad != 0) << 6;
16811 inst.instruction |= immbits << 16;
16812 inst.instruction |= (size >> 3) << 7;
16813 inst.instruction |= (size & 0x7) << 19;
16814 if (write_ubit)
16815 inst.instruction |= (uval != 0) << 24;
16816
88714cb8 16817 neon_dp_fixup (&inst);
5287ad62
JB		 16818}
16819
16820static void
5150f0d8 16821do_neon_shl (void)
5287ad62 16822{
64c350f2 16823 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 16824 return;
16825
5287ad62
JB		 16826 if (!inst.operands[2].isreg)
16827 {
5150f0d8
AV		 16828 enum neon_shape rs;
16829 struct neon_type_el et;
16830 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16831 {
16832 rs = neon_select_shape (NS_QQI, NS_NULL);
16833 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE);
16834 }
16835 else
16836 {
16837 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16838 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16839 }
cb3b1e65
JB		 16840 int imm = inst.operands[2].imm;
16841
16842 constraint (imm < 0 || (unsigned)imm >= et.size,
16843 _("immediate out of range for shift"));
88714cb8 16844 NEON_ENCODE (IMMED, inst);
cb3b1e65 16845 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 16846 }
16847 else
16848 {
5150f0d8
AV		 16849 enum neon_shape rs;
16850 struct neon_type_el et;
16851 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16852 {
16853 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16854 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16855 }
16856 else
16857 {
16858 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16859 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16860 }
16861
16862
16863 if (rs == NS_QQR)
16864 {
16865 constraint (inst.operands[0].reg != inst.operands[1].reg,
16866 _("invalid instruction shape"));
16867 if (inst.operands[2].reg == REG_SP)
16868 as_tsktsk (MVE_BAD_SP);
16869 else if (inst.operands[2].reg == REG_PC)
16870 as_tsktsk (MVE_BAD_PC);
16871
16872 inst.instruction = 0xee311e60;
16873 inst.instruction |= (et.type == NT_unsigned) << 28;
16874 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16875 inst.instruction |= neon_logbits (et.size) << 18;
16876 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16877 inst.instruction |= inst.operands[2].reg;
16878 inst.is_neon = 1;
16879 }
16880 else
16881 {
16882 unsigned int tmp;
16883
16884 /* VSHL/VQSHL 3-register variants have syntax such as:
16885 vshl.xx Dd, Dm, Dn
16886 whereas other 3-register operations encoded by neon_three_same have
16887 syntax like:
16888 vadd.xx Dd, Dn, Dm
16889 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16890 operands[2].reg here. */
16891 tmp = inst.operands[2].reg;
16892 inst.operands[2].reg = inst.operands[1].reg;
16893 inst.operands[1].reg = tmp;
16894 NEON_ENCODE (INTEGER, inst);
16895 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16896 }
5287ad62
JB		 16897 }
16898}
16899
16900static void
5150f0d8 16901do_neon_qshl (void)
5287ad62 16902{
64c350f2 16903 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 16904 return;
16905
5287ad62
JB		 16906 if (!inst.operands[2].isreg)
16907 {
5150f0d8
AV		 16908 enum neon_shape rs;
16909 struct neon_type_el et;
16910 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16911 {
16912 rs = neon_select_shape (NS_QQI, NS_NULL);
16913 et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE);
16914 }
16915 else
16916 {
16917 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16918 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16919 }
cb3b1e65 16920 int imm = inst.operands[2].imm;
627907b7 16921
cb3b1e65
JB		 16922 constraint (imm < 0 || (unsigned)imm >= et.size,
16923 _("immediate out of range for shift"));
88714cb8 16924 NEON_ENCODE (IMMED, inst);
cb3b1e65 16925 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
5287ad62
JB		 16926 }
16927 else
16928 {
5150f0d8
AV		 16929 enum neon_shape rs;
16930 struct neon_type_el et;
627907b7 16931
5150f0d8
AV		 16932 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16933 {
16934 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16935 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16936 }
16937 else
16938 {
16939 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16940 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16941 }
16942
16943 if (rs == NS_QQR)
16944 {
16945 constraint (inst.operands[0].reg != inst.operands[1].reg,
16946 _("invalid instruction shape"));
16947 if (inst.operands[2].reg == REG_SP)
16948 as_tsktsk (MVE_BAD_SP);
16949 else if (inst.operands[2].reg == REG_PC)
16950 as_tsktsk (MVE_BAD_PC);
16951
16952 inst.instruction = 0xee311ee0;
16953 inst.instruction |= (et.type == NT_unsigned) << 28;
16954 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16955 inst.instruction |= neon_logbits (et.size) << 18;
16956 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16957 inst.instruction |= inst.operands[2].reg;
16958 inst.is_neon = 1;
16959 }
16960 else
16961 {
16962 unsigned int tmp;
16963
16964 /* See note in do_neon_shl. */
16965 tmp = inst.operands[2].reg;
16966 inst.operands[2].reg = inst.operands[1].reg;
16967 inst.operands[1].reg = tmp;
16968 NEON_ENCODE (INTEGER, inst);
16969 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16970 }
5287ad62
JB		 16971 }
16972}
16973
627907b7
JB		 16974static void
16975do_neon_rshl (void)
16976{
64c350f2 16977 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
1be7aba3
AV		 16978 return;
16979
16980 enum neon_shape rs;
16981 struct neon_type_el et;
16982 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16983 {
16984 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16985 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16986 }
16987 else
16988 {
16989 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16990 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16991 }
16992
627907b7
JB		 16993 unsigned int tmp;
16994
1be7aba3
AV		 16995 if (rs == NS_QQR)
16996 {
16997 if (inst.operands[2].reg == REG_PC)
16998 as_tsktsk (MVE_BAD_PC);
16999 else if (inst.operands[2].reg == REG_SP)
17000 as_tsktsk (MVE_BAD_SP);
17001
17002 constraint (inst.operands[0].reg != inst.operands[1].reg,
17003 _("invalid instruction shape"));
17004
17005 if (inst.instruction == 0x0000510)
17006 /* We are dealing with vqrshl. */
17007 inst.instruction = 0xee331ee0;
17008 else
17009 /* We are dealing with vrshl. */
17010 inst.instruction = 0xee331e60;
17011
17012 inst.instruction |= (et.type == NT_unsigned) << 28;
17013 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17014 inst.instruction |= neon_logbits (et.size) << 18;
17015 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17016 inst.instruction |= inst.operands[2].reg;
17017 inst.is_neon = 1;
17018 }
17019 else
17020 {
17021 tmp = inst.operands[2].reg;
17022 inst.operands[2].reg = inst.operands[1].reg;
17023 inst.operands[1].reg = tmp;
17024 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17025 }
627907b7
JB		 17026}
17027
5287ad62
JB		 17028static int
17029neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
17030{
036dc3f7
PB		 17031 /* Handle .I8 pseudo-instructions. */
17032 if (size == 8)
5287ad62 17033 {
5287ad62 17034 /* Unfortunately, this will make everything apart from zero out-of-range.
477330fc
RM		 17035 FIXME is this the intended semantics? There doesn't seem much point in
17036 accepting .I8 if so. */
5287ad62
JB		 17037 immediate |= immediate << 8;
17038 size = 16;
036dc3f7
PB		 17039 }
17040
17041 if (size >= 32)
17042 {
17043 if (immediate == (immediate & 0x000000ff))
17044 {
17045 *immbits = immediate;
17046 return 0x1;
17047 }
17048 else if (immediate == (immediate & 0x0000ff00))
17049 {
17050 *immbits = immediate >> 8;
17051 return 0x3;
17052 }
17053 else if (immediate == (immediate & 0x00ff0000))
17054 {
17055 *immbits = immediate >> 16;
17056 return 0x5;
17057 }
17058 else if (immediate == (immediate & 0xff000000))
17059 {
17060 *immbits = immediate >> 24;
17061 return 0x7;
17062 }
17063 if ((immediate & 0xffff) != (immediate >> 16))
17064 goto bad_immediate;
17065 immediate &= 0xffff;
5287ad62
JB		 17066 }
17067
17068 if (immediate == (immediate & 0x000000ff))
17069 {
17070 *immbits = immediate;
036dc3f7 17071 return 0x9;
5287ad62
JB		 17072 }
17073 else if (immediate == (immediate & 0x0000ff00))
17074 {
17075 *immbits = immediate >> 8;
036dc3f7 17076 return 0xb;
5287ad62
JB		 17077 }
17078
17079 bad_immediate:
dcbf9037 17080 first_error (_("immediate value out of range"));
5287ad62
JB		 17081 return FAIL;
17082}
17083
5287ad62
JB		 17084static void
17085do_neon_logic (void)
17086{
17087 if (inst.operands[2].present && inst.operands[2].isreg)
17088 {
037e8744 17089 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
f601a00c 17090 if (rs == NS_QQQ
64c350f2
AV		 17091 && !check_simd_pred_availability (FALSE,
17092 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV		 17093 return;
17094 else if (rs != NS_QQQ
17095 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17096 first_error (BAD_FPU);
17097
5287ad62
JB		 17098 neon_check_type (3, rs, N_IGNORE_TYPE);
17099 /* U bit and size field were set as part of the bitmask. */
88714cb8 17100 NEON_ENCODE (INTEGER, inst);
037e8744 17101 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 17102 }
17103 else
17104 {
4316f0d2
DG		 17105 const int three_ops_form = (inst.operands[2].present
17106 && !inst.operands[2].isreg);
17107 const int immoperand = (three_ops_form ? 2 : 1);
17108 enum neon_shape rs = (three_ops_form
17109 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
17110 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
f601a00c
AV		 17111 /* Because neon_select_shape makes the second operand a copy of the first
17112 if the second operand is not present. */
17113 if (rs == NS_QQI
64c350f2
AV		 17114 && !check_simd_pred_availability (FALSE,
17115 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV		 17116 return;
17117 else if (rs != NS_QQI
17118 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17119 first_error (BAD_FPU);
17120
17121 struct neon_type_el et;
17122 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17123 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
17124 else
17125 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
17126 | N_KEY, N_EQK);
17127
17128 if (et.type == NT_invtype)
17129 return;
21d799b5 17130 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB		 17131 unsigned immbits;
17132 int cmode;
5f4273c7 17133
5f4273c7 17134
4316f0d2
DG		 17135 if (three_ops_form)
17136 constraint (inst.operands[0].reg != inst.operands[1].reg,
17137 _("first and second operands shall be the same register"));
17138
88714cb8 17139 NEON_ENCODE (IMMED, inst);
5287ad62 17140
4316f0d2 17141 immbits = inst.operands[immoperand].imm;
036dc3f7
PB		 17142 if (et.size == 64)
17143 {
17144 /* .i64 is a pseudo-op, so the immediate must be a repeating
17145 pattern. */
4316f0d2
DG		 17146 if (immbits != (inst.operands[immoperand].regisimm ?
17147 inst.operands[immoperand].reg : 0))
036dc3f7
PB		 17148 {
17149 /* Set immbits to an invalid constant. */
17150 immbits = 0xdeadbeef;
17151 }
17152 }
17153
5287ad62 17154 switch (opcode)
477330fc
RM		 17155 {
17156 case N_MNEM_vbic:
17157 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17158 break;
17159
17160 case N_MNEM_vorr:
17161 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17162 break;
17163
17164 case N_MNEM_vand:
17165 /* Pseudo-instruction for VBIC. */
17166 neon_invert_size (&immbits, 0, et.size);
17167 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17168 break;
17169
17170 case N_MNEM_vorn:
17171 /* Pseudo-instruction for VORR. */
17172 neon_invert_size (&immbits, 0, et.size);
17173 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17174 break;
17175
17176 default:
17177 abort ();
17178 }
5287ad62
JB		 17179
17180 if (cmode == FAIL)
477330fc 17181 return;
5287ad62 17182
037e8744 17183 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 17184 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17185 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17186 inst.instruction |= cmode << 8;
17187 neon_write_immbits (immbits);
5f4273c7 17188
88714cb8 17189 neon_dp_fixup (&inst);
5287ad62
JB		 17190 }
17191}
17192
17193static void
17194do_neon_bitfield (void)
17195{
037e8744 17196 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 17197 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 17198 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 17199}
17200
17201static void
dcbf9037 17202neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
477330fc 17203 unsigned destbits)
5287ad62 17204{
5ee91343 17205 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
dcbf9037 17206 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
477330fc 17207 types | N_KEY);
5287ad62
JB		 17208 if (et.type == NT_float)
17209 {
88714cb8 17210 NEON_ENCODE (FLOAT, inst);
5ee91343 17211 if (rs == NS_QQR)
7df54120 17212 mve_encode_qqr (et.size, 0, 1);
5ee91343
AV		 17213 else
17214 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 17215 }
17216 else
17217 {
88714cb8 17218 NEON_ENCODE (INTEGER, inst);
5ee91343 17219 if (rs == NS_QQR)
a8465a06 17220 mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
5ee91343
AV		 17221 else
17222 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB		 17223 }
17224}
17225
5287ad62
JB		 17226
17227static void
17228do_neon_dyadic_if_su_d (void)
17229{
17230 /* This version only allow D registers, but that constraint is enforced during
17231 operand parsing so we don't need to do anything extra here. */
dcbf9037 17232 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 17233}
17234
5287ad62
JB		 17235static void
17236do_neon_dyadic_if_i_d (void)
17237{
428e3f1f
PB		 17238 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17239 affected if we specify unsigned args. */
17240 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB		 17241}
17242
f5f10c66
AV		 17243static void
17244do_mve_vstr_vldr_QI (int size, int elsize, int load)
17245{
17246 constraint (size < 32, BAD_ADDR_MODE);
17247 constraint (size != elsize, BAD_EL_TYPE);
17248 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17249 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17250 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17251 _("destination register and offset register may not be the"
17252 " same"));
17253
17254 int imm = inst.relocs[0].exp.X_add_number;
17255 int add = 1;
17256 if (imm < 0)
17257 {
17258 add = 0;
17259 imm = -imm;
17260 }
17261 constraint ((imm % (size / 8) != 0)
17262 || imm > (0x7f << neon_logbits (size)),
17263 (size == 32) ? _("immediate must be a multiple of 4 in the"
17264 " range of +/-[0,508]")
17265 : _("immediate must be a multiple of 8 in the"
17266 " range of +/-[0,1016]"));
17267 inst.instruction |= 0x11 << 24;
17268 inst.instruction |= add << 23;
17269 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17270 inst.instruction |= inst.operands[1].writeback << 21;
17271 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17272 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17273 inst.instruction |= 1 << 12;
17274 inst.instruction |= (size == 64) << 8;
17275 inst.instruction &= 0xffffff00;
17276 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17277 inst.instruction |= imm >> neon_logbits (size);
17278}
17279
17280static void
17281do_mve_vstr_vldr_RQ (int size, int elsize, int load)
17282{
17283 unsigned os = inst.operands[1].imm >> 5;
17284 constraint (os != 0 && size == 8,
17285 _("can not shift offsets when accessing less than half-word"));
17286 constraint (os && os != neon_logbits (size),
17287 _("shift immediate must be 1, 2 or 3 for half-word, word"
17288 " or double-word accesses respectively"));
17289 if (inst.operands[1].reg == REG_PC)
17290 as_tsktsk (MVE_BAD_PC);
17291
17292 switch (size)
17293 {
17294 case 8:
17295 constraint (elsize >= 64, BAD_EL_TYPE);
17296 break;
17297 case 16:
17298 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17299 break;
17300 case 32:
17301 case 64:
17302 constraint (elsize != size, BAD_EL_TYPE);
17303 break;
17304 default:
17305 break;
17306 }
17307 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17308 BAD_ADDR_MODE);
17309 if (load)
17310 {
17311 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17312 _("destination register and offset register may not be"
17313 " the same"));
17314 constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
17315 BAD_EL_TYPE);
17316 constraint (inst.vectype.el[0].type != NT_unsigned
17317 && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
17318 inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
17319 }
17320 else
17321 {
17322 constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
17323 }
17324
17325 inst.instruction |= 1 << 23;
17326 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17327 inst.instruction |= inst.operands[1].reg << 16;
17328 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17329 inst.instruction |= neon_logbits (elsize) << 7;
17330 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17331 inst.instruction |= LOW4 (inst.operands[1].imm);
17332 inst.instruction |= !!os;
17333}
17334
17335static void
17336do_mve_vstr_vldr_RI (int size, int elsize, int load)
17337{
17338 enum neon_el_type type = inst.vectype.el[0].type;
17339
17340 constraint (size >= 64, BAD_ADDR_MODE);
17341 switch (size)
17342 {
17343 case 16:
17344 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17345 break;
17346 case 32:
17347 constraint (elsize != size, BAD_EL_TYPE);
17348 break;
17349 default:
17350 break;
17351 }
17352 if (load)
17353 {
17354 constraint (elsize != size && type != NT_unsigned
17355 && type != NT_signed, BAD_EL_TYPE);
17356 }
17357 else
17358 {
17359 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
17360 }
17361
17362 int imm = inst.relocs[0].exp.X_add_number;
17363 int add = 1;
17364 if (imm < 0)
17365 {
17366 add = 0;
17367 imm = -imm;
17368 }
17369
17370 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
17371 {
17372 switch (size)
17373 {
17374 case 8:
17375 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17376 break;
17377 case 16:
17378 constraint (1, _("immediate must be a multiple of 2 in the"
17379 " range of +/-[0,254]"));
17380 break;
17381 case 32:
17382 constraint (1, _("immediate must be a multiple of 4 in the"
17383 " range of +/-[0,508]"));
17384 break;
17385 }
17386 }
17387
17388 if (size != elsize)
17389 {
17390 constraint (inst.operands[1].reg > 7, BAD_HIREG);
17391 constraint (inst.operands[0].reg > 14,
17392 _("MVE vector register in the range [Q0..Q7] expected"));
17393 inst.instruction |= (load && type == NT_unsigned) << 28;
17394 inst.instruction |= (size == 16) << 19;
17395 inst.instruction |= neon_logbits (elsize) << 7;
17396 }
17397 else
17398 {
17399 if (inst.operands[1].reg == REG_PC)
17400 as_tsktsk (MVE_BAD_PC);
17401 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17402 as_tsktsk (MVE_BAD_SP);
17403 inst.instruction |= 1 << 12;
17404 inst.instruction |= neon_logbits (size) << 7;
17405 }
17406 inst.instruction |= inst.operands[1].preind << 24;
17407 inst.instruction |= add << 23;
17408 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17409 inst.instruction |= inst.operands[1].writeback << 21;
17410 inst.instruction |= inst.operands[1].reg << 16;
17411 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17412 inst.instruction &= 0xffffff80;
17413 inst.instruction |= imm >> neon_logbits (size);
17414
17415}
17416
17417static void
17418do_mve_vstr_vldr (void)
17419{
17420 unsigned size;
17421 int load = 0;
17422
17423 if (inst.cond > COND_ALWAYS)
17424 inst.pred_insn_type = INSIDE_VPT_INSN;
17425 else
17426 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17427
17428 switch (inst.instruction)
17429 {
17430 default:
17431 gas_assert (0);
17432 break;
17433 case M_MNEM_vldrb:
17434 load = 1;
17435 /* fall through. */
17436 case M_MNEM_vstrb:
17437 size = 8;
17438 break;
17439 case M_MNEM_vldrh:
17440 load = 1;
17441 /* fall through. */
17442 case M_MNEM_vstrh:
17443 size = 16;
17444 break;
17445 case M_MNEM_vldrw:
17446 load = 1;
17447 /* fall through. */
17448 case M_MNEM_vstrw:
17449 size = 32;
17450 break;
17451 case M_MNEM_vldrd:
17452 load = 1;
17453 /* fall through. */
17454 case M_MNEM_vstrd:
17455 size = 64;
17456 break;
17457 }
17458 unsigned elsize = inst.vectype.el[0].size;
17459
17460 if (inst.operands[1].isquad)
17461 {
17462 /* We are dealing with [Q, imm]{!} cases. */
17463 do_mve_vstr_vldr_QI (size, elsize, load);
17464 }
17465 else
17466 {
17467 if (inst.operands[1].immisreg == 2)
17468 {
17469 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17470 do_mve_vstr_vldr_RQ (size, elsize, load);
17471 }
17472 else if (!inst.operands[1].immisreg)
17473 {
17474 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17475 do_mve_vstr_vldr_RI (size, elsize, load);
17476 }
17477 else
17478 constraint (1, BAD_ADDR_MODE);
17479 }
17480
17481 inst.is_neon = 1;
17482}
17483
35c228db
AV		 17484static void
17485do_mve_vst_vld (void)
17486{
17487 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17488 return;
17489
17490 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17491 || inst.relocs[0].exp.X_add_number != 0
17492 || inst.operands[1].immisreg != 0,
17493 BAD_ADDR_MODE);
17494 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17495 if (inst.operands[1].reg == REG_PC)
17496 as_tsktsk (MVE_BAD_PC);
17497 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17498 as_tsktsk (MVE_BAD_SP);
17499
17500
17501 /* These instructions are one of the "exceptions" mentioned in
17502 handle_pred_state. They are MVE instructions that are not VPT compatible
17503 and do not accept a VPT code, thus appending such a code is a syntax
17504 error. */
17505 if (inst.cond > COND_ALWAYS)
17506 first_error (BAD_SYNTAX);
17507 /* If we append a scalar condition code we can set this to
17508 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17509 else if (inst.cond < COND_ALWAYS)
17510 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17511 else
17512 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17513
17514 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17515 inst.instruction |= inst.operands[1].writeback << 21;
17516 inst.instruction |= inst.operands[1].reg << 16;
17517 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17518 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17519 inst.is_neon = 1;
17520}
17521
26c1e780
AV		 17522static void
17523do_mve_vaddlv (void)
17524{
17525 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
17526 struct neon_type_el et
17527 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
17528
17529 if (et.type == NT_invtype)
17530 first_error (BAD_EL_TYPE);
17531
17532 if (inst.cond > COND_ALWAYS)
17533 inst.pred_insn_type = INSIDE_VPT_INSN;
17534 else
17535 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17536
17537 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17538
17539 inst.instruction |= (et.type == NT_unsigned) << 28;
17540 inst.instruction |= inst.operands[1].reg << 19;
17541 inst.instruction |= inst.operands[0].reg << 12;
17542 inst.instruction |= inst.operands[2].reg;
17543 inst.is_neon = 1;
17544}
17545
5287ad62 17546static void
5ee91343 17547do_neon_dyadic_if_su (void)
5287ad62 17548{
5ee91343
AV		 17549 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17550 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17551 N_SUF_32 | N_KEY);
17552
935295b5
AV		 17553 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17554 || inst.instruction == ((unsigned) N_MNEM_vmin))
17555 && et.type == NT_float
17556 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
17557
64c350f2
AV		 17558 if (!check_simd_pred_availability (et.type == NT_float,
17559 NEON_CHECK_ARCH | NEON_CHECK_CC))
037e8744
JB		 17560 return;
17561
5ee91343
AV		 17562 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17563}
17564
17565static void
17566do_neon_addsub_if_i (void)
17567{
17568 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
17569 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
037e8744
JB		 17570 return;
17571
5ee91343
AV		 17572 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17573 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
17574 N_EQK, N_IF_32 | N_I64 | N_KEY);
17575
17576 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
17577 /* If we are parsing Q registers and the element types match MVE, which NEON
17578 also supports, then we must check whether this is an instruction that can
17579 be used by both MVE/NEON. This distinction can be made based on whether
17580 they are predicated or not. */
17581 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
17582 {
64c350f2
AV		 17583 if (!check_simd_pred_availability (et.type == NT_float,
17584 NEON_CHECK_ARCH | NEON_CHECK_CC))
5ee91343
AV		 17585 return;
17586 }
17587 else
17588 {
17589 /* If they are either in a D register or are using an unsupported. */
17590 if (rs != NS_QQR
17591 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17592 return;
17593 }
17594
5287ad62
JB		 17595 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17596 affected if we specify unsigned args. */
dcbf9037 17597 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB		 17598}
17599
17600/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17601 result to be:
17602 V<op> A,B (A is operand 0, B is operand 2)
17603 to mean:
17604 V<op> A,B,A
17605 not:
17606 V<op> A,B,B
17607 so handle that case specially. */
17608
17609static void
17610neon_exchange_operands (void)
17611{
5287ad62
JB		 17612 if (inst.operands[1].present)
17613 {
e1fa0163
NC		 17614 void *scratch = xmalloc (sizeof (inst.operands[0]));
17615
5287ad62
JB		 17616 /* Swap operands[1] and operands[2]. */
17617 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17618 inst.operands[1] = inst.operands[2];
17619 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
e1fa0163 17620 free (scratch);
5287ad62
JB		 17621 }
17622 else
17623 {
17624 inst.operands[1] = inst.operands[2];
17625 inst.operands[2] = inst.operands[0];
17626 }
17627}
17628
17629static void
17630neon_compare (unsigned regtypes, unsigned immtypes, int invert)
17631{
17632 if (inst.operands[2].isreg)
17633 {
17634 if (invert)
477330fc 17635 neon_exchange_operands ();
dcbf9037 17636 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB		 17637 }
17638 else
17639 {
037e8744 17640 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037 17641 struct neon_type_el et = neon_check_type (2, rs,
477330fc 17642 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 17643
88714cb8 17644 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 17645 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17646 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17647 inst.instruction |= LOW4 (inst.operands[1].reg);
17648 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 17649 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 17650 inst.instruction |= (et.type == NT_float) << 10;
17651 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 17652
88714cb8 17653 neon_dp_fixup (&inst);
5287ad62
JB		 17654 }
17655}
17656
17657static void
17658do_neon_cmp (void)
17659{
cc933301 17660 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
5287ad62
JB		 17661}
17662
17663static void
17664do_neon_cmp_inv (void)
17665{
cc933301 17666 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
5287ad62
JB		 17667}
17668
17669static void
17670do_neon_ceq (void)
17671{
17672 neon_compare (N_IF_32, N_IF_32, FALSE);
17673}
17674
17675/* For multiply instructions, we have the possibility of 16-bit or 32-bit
17676 scalars, which are encoded in 5 bits, M : Rm.
17677 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17678 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
c604a79a
JW		 17679 index in M.
17680
17681 Dot Product instructions are similar to multiply instructions except elsize
17682 should always be 32.
17683
17684 This function translates SCALAR, which is GAS's internal encoding of indexed
17685 scalar register, to raw encoding. There is also register and index range
17686 check based on ELSIZE. */
5287ad62
JB		 17687
17688static unsigned
17689neon_scalar_for_mul (unsigned scalar, unsigned elsize)
17690{
dcbf9037
JB		 17691 unsigned regno = NEON_SCALAR_REG (scalar);
17692 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB		 17693
17694 switch (elsize)
17695 {
17696 case 16:
17697 if (regno > 7 || elno > 3)
477330fc 17698 goto bad_scalar;
5287ad62 17699 return regno | (elno << 3);
5f4273c7 17700
5287ad62
JB		 17701 case 32:
17702 if (regno > 15 || elno > 1)
477330fc 17703 goto bad_scalar;
5287ad62
JB		 17704 return regno | (elno << 4);
17705
17706 default:
17707 bad_scalar:
dcbf9037 17708 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB		 17709 }
17710
17711 return 0;
17712}
17713
17714/* Encode multiply / multiply-accumulate scalar instructions. */
17715
17716static void
17717neon_mul_mac (struct neon_type_el et, int ubit)
17718{
dcbf9037
JB		 17719 unsigned scalar;
17720
17721 /* Give a more helpful error message if we have an invalid type. */
17722 if (et.type == NT_invtype)
17723 return;
5f4273c7 17724
dcbf9037 17725 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB		 17726 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17727 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17728 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17729 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17730 inst.instruction |= LOW4 (scalar);
17731 inst.instruction |= HI1 (scalar) << 5;
17732 inst.instruction |= (et.type == NT_float) << 8;
17733 inst.instruction |= neon_logbits (et.size) << 20;
17734 inst.instruction |= (ubit != 0) << 24;
17735
88714cb8 17736 neon_dp_fixup (&inst);
5287ad62
JB		 17737}
17738
17739static void
17740do_neon_mac_maybe_scalar (void)
17741{
037e8744
JB		 17742 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17743 return;
17744
64c350f2 17745 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB		 17746 return;
17747
5287ad62
JB		 17748 if (inst.operands[2].isscalar)
17749 {
a8465a06 17750 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 17751 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 17752 struct neon_type_el et = neon_check_type (3, rs,
589a7d88 17753 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
88714cb8 17754 NEON_ENCODE (SCALAR, inst);
037e8744 17755 neon_mul_mac (et, neon_quad (rs));
5287ad62 17756 }
a8465a06
AV		 17757 else if (!inst.operands[2].isvec)
17758 {
17759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17760
17761 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17762 neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17763
17764 neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17765 }
5287ad62 17766 else
428e3f1f 17767 {
a8465a06 17768 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
428e3f1f
PB		 17769 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17770 affected if we specify unsigned args. */
17771 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17772 }
5287ad62
JB		 17773}
17774
62f3b8c8
PB		 17775static void
17776do_neon_fmac (void)
17777{
d58196e0
AV		 17778 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
17779 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
62f3b8c8
PB		 17780 return;
17781
64c350f2 17782 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH))
62f3b8c8
PB		 17783 return;
17784
d58196e0
AV		 17785 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17786 {
17787 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17788 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17789 N_EQK);
17790
17791 if (rs == NS_QQR)
17792 {
17793 if (inst.operands[2].reg == REG_SP)
17794 as_tsktsk (MVE_BAD_SP);
17795 else if (inst.operands[2].reg == REG_PC)
17796 as_tsktsk (MVE_BAD_PC);
17797
17798 inst.instruction = 0xee310e40;
17799 inst.instruction |= (et.size == 16) << 28;
17800 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17801 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17802 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17803 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17804 inst.instruction |= inst.operands[2].reg;
17805 inst.is_neon = 1;
17806 return;
17807 }
17808 }
17809 else
17810 {
17811 constraint (!inst.operands[2].isvec, BAD_FPU);
17812 }
17813
62f3b8c8
PB		 17814 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17815}
17816
5287ad62
JB		 17817static void
17818do_neon_tst (void)
17819{
037e8744 17820 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 17821 struct neon_type_el et = neon_check_type (3, rs,
17822 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 17823 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 17824}
17825
17826/* VMUL with 3 registers allows the P8 type. The scalar version supports the
17827 same types as the MAC equivalents. The polynomial type for this instruction
17828 is encoded the same as the integer type. */
17829
17830static void
17831do_neon_mul (void)
17832{
037e8744
JB		 17833 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
17834 return;
17835
64c350f2 17836 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB		 17837 return;
17838
5287ad62 17839 if (inst.operands[2].isscalar)
a8465a06
AV		 17840 {
17841 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17842 do_neon_mac_maybe_scalar ();
17843 }
5287ad62 17844 else
a8465a06
AV		 17845 {
17846 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17847 {
17848 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17849 struct neon_type_el et
17850 = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
17851 if (et.type == NT_float)
17852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
17853 BAD_FPU);
17854
17855 neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
17856 }
17857 else
17858 {
17859 constraint (!inst.operands[2].isvec, BAD_FPU);
17860 neon_dyadic_misc (NT_poly,
17861 N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
17862 }
17863 }
5287ad62
JB		 17864}
17865
17866static void
17867do_neon_qdmulh (void)
17868{
64c350f2 17869 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV		 17870 return;
17871
5287ad62
JB		 17872 if (inst.operands[2].isscalar)
17873 {
42b16635 17874 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 17875 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 17876 struct neon_type_el et = neon_check_type (3, rs,
477330fc 17877 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 17878 NEON_ENCODE (SCALAR, inst);
037e8744 17879 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 17880 }
17881 else
17882 {
42b16635
AV		 17883 enum neon_shape rs;
17884 struct neon_type_el et;
17885 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17886 {
17887 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17888 et = neon_check_type (3, rs,
17889 N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17890 }
17891 else
17892 {
17893 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17894 et = neon_check_type (3, rs,
17895 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17896 }
17897
88714cb8 17898 NEON_ENCODE (INTEGER, inst);
42b16635
AV		 17899 if (rs == NS_QQR)
17900 mve_encode_qqr (et.size, 0, 0);
17901 else
17902 /* The U bit (rounding) comes from bit mask. */
17903 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 17904 }
17905}
17906
26c1e780
AV		 17907static void
17908do_mve_vaddv (void)
17909{
17910 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17911 struct neon_type_el et
17912 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
17913
17914 if (et.type == NT_invtype)
17915 first_error (BAD_EL_TYPE);
17916
17917 if (inst.cond > COND_ALWAYS)
17918 inst.pred_insn_type = INSIDE_VPT_INSN;
17919 else
17920 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17921
17922 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17923
17924 mve_encode_rq (et.type == NT_unsigned, et.size);
17925}
17926
7df54120
AV		 17927static void
17928do_mve_vhcadd (void)
17929{
17930 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
17931 struct neon_type_el et
17932 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17933
17934 if (inst.cond > COND_ALWAYS)
17935 inst.pred_insn_type = INSIDE_VPT_INSN;
17936 else
17937 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17938
17939 unsigned rot = inst.relocs[0].exp.X_add_number;
17940 constraint (rot != 90 && rot != 270, _("immediate out of range"));
17941
17942 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17943 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17944 "operand makes instruction UNPREDICTABLE"));
17945
17946 mve_encode_qqq (0, et.size);
17947 inst.instruction |= (rot == 270) << 12;
17948 inst.is_neon = 1;
17949}
17950
35d1cfc2
AV		 17951static void
17952do_mve_vqdmull (void)
17953{
17954 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17955 struct neon_type_el et
17956 = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17957
17958 if (et.size == 32
17959 && (inst.operands[0].reg == inst.operands[1].reg
17960 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
17961 as_tsktsk (BAD_MVE_SRCDEST);
17962
17963 if (inst.cond > COND_ALWAYS)
17964 inst.pred_insn_type = INSIDE_VPT_INSN;
17965 else
17966 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17967
17968 if (rs == NS_QQQ)
17969 {
17970 mve_encode_qqq (et.size == 32, 64);
17971 inst.instruction |= 1;
17972 }
17973 else
17974 {
17975 mve_encode_qqr (64, et.size == 32, 0);
17976 inst.instruction |= 0x3 << 5;
17977 }
17978}
17979
c2dafc2a
AV		 17980static void
17981do_mve_vadc (void)
17982{
17983 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17984 struct neon_type_el et
17985 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
17986
17987 if (et.type == NT_invtype)
17988 first_error (BAD_EL_TYPE);
17989
17990 if (inst.cond > COND_ALWAYS)
17991 inst.pred_insn_type = INSIDE_VPT_INSN;
17992 else
17993 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17994
17995 mve_encode_qqq (0, 64);
17996}
17997
17998static void
17999do_mve_vbrsr (void)
18000{
18001 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18002 struct neon_type_el et
18003 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18004
18005 if (inst.cond > COND_ALWAYS)
18006 inst.pred_insn_type = INSIDE_VPT_INSN;
18007 else
18008 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18009
7df54120 18010 mve_encode_qqr (et.size, 0, 0);
c2dafc2a
AV		 18011}
18012
18013static void
18014do_mve_vsbc (void)
18015{
18016 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
18017
18018 if (inst.cond > COND_ALWAYS)
18019 inst.pred_insn_type = INSIDE_VPT_INSN;
18020 else
18021 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18022
18023 mve_encode_qqq (1, 64);
18024}
18025
2d78f95b
AV		 18026static void
18027do_mve_vmulh (void)
18028{
18029 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18030 struct neon_type_el et
18031 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
18032
18033 if (inst.cond > COND_ALWAYS)
18034 inst.pred_insn_type = INSIDE_VPT_INSN;
18035 else
18036 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18037
18038 mve_encode_qqq (et.type == NT_unsigned, et.size);
18039}
18040
42b16635
AV		 18041static void
18042do_mve_vqdmlah (void)
18043{
18044 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18045 struct neon_type_el et
23d188c7 18046 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
42b16635
AV		 18047
18048 if (inst.cond > COND_ALWAYS)
18049 inst.pred_insn_type = INSIDE_VPT_INSN;
18050 else
18051 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18052
18053 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
18054}
8b8b22a4
AV		 18055
18056static void
18057do_mve_vqdmladh (void)
18058{
18059 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18060 struct neon_type_el et
18061 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18062
18063 if (inst.cond > COND_ALWAYS)
18064 inst.pred_insn_type = INSIDE_VPT_INSN;
18065 else
18066 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18067
8b8b22a4
AV		 18068 mve_encode_qqq (0, et.size);
18069}
18070
18071
886e1c73
AV		 18072static void
18073do_mve_vmull (void)
18074{
18075
18076 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
18077 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
18078 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18079 && inst.cond == COND_ALWAYS
18080 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
18081 {
18082 if (rs == NS_QQQ)
18083 {
18084
18085 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
18086 N_SUF_32 | N_F64 | N_P8
18087 | N_P16 | N_I_MVE | N_KEY);
18088 if (((et.type == NT_poly) && et.size == 8
18089 && ARM_CPU_IS_ANY (cpu_variant))
18090 || (et.type == NT_integer) || (et.type == NT_float))
18091 goto neon_vmul;
18092 }
18093 else
18094 goto neon_vmul;
18095 }
18096
18097 constraint (rs != NS_QQQ, BAD_FPU);
18098 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
18099 N_SU_32 | N_P8 | N_P16 | N_KEY);
18100
18101 /* We are dealing with MVE's vmullt. */
18102 if (et.size == 32
18103 && (inst.operands[0].reg == inst.operands[1].reg
18104 || inst.operands[0].reg == inst.operands[2].reg))
18105 as_tsktsk (BAD_MVE_SRCDEST);
18106
18107 if (inst.cond > COND_ALWAYS)
18108 inst.pred_insn_type = INSIDE_VPT_INSN;
18109 else
18110 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18111
18112 if (et.type == NT_poly)
18113 mve_encode_qqq (neon_logbits (et.size), 64);
18114 else
18115 mve_encode_qqq (et.type == NT_unsigned, et.size);
18116
18117 return;
18118
18119neon_vmul:
18120 inst.instruction = N_MNEM_vmul;
18121 inst.cond = 0xb;
18122 if (thumb_mode)
18123 inst.pred_insn_type = INSIDE_IT_INSN;
18124 do_neon_mul ();
18125}
18126
a302e574
AV		 18127static void
18128do_mve_vabav (void)
18129{
18130 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18131
18132 if (rs == NS_NULL)
18133 return;
18134
18135 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18136 return;
18137
18138 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
18139 | N_S16 | N_S32 | N_U8 | N_U16
18140 | N_U32);
18141
18142 if (inst.cond > COND_ALWAYS)
18143 inst.pred_insn_type = INSIDE_VPT_INSN;
18144 else
18145 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18146
18147 mve_encode_rqq (et.type == NT_unsigned, et.size);
18148}
18149
18150static void
18151do_mve_vmladav (void)
18152{
18153 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18154 struct neon_type_el et = neon_check_type (3, rs,
18155 N_EQK, N_EQK, N_SU_MVE | N_KEY);
18156
18157 if (et.type == NT_unsigned
18158 && (inst.instruction == M_MNEM_vmladavx
18159 || inst.instruction == M_MNEM_vmladavax
18160 || inst.instruction == M_MNEM_vmlsdav
18161 || inst.instruction == M_MNEM_vmlsdava
18162 || inst.instruction == M_MNEM_vmlsdavx
18163 || inst.instruction == M_MNEM_vmlsdavax))
18164 first_error (BAD_SIMD_TYPE);
18165
18166 constraint (inst.operands[2].reg > 14,
18167 _("MVE vector register in the range [Q0..Q7] expected"));
18168
18169 if (inst.cond > COND_ALWAYS)
18170 inst.pred_insn_type = INSIDE_VPT_INSN;
18171 else
18172 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18173
18174 if (inst.instruction == M_MNEM_vmlsdav
18175 || inst.instruction == M_MNEM_vmlsdava
18176 || inst.instruction == M_MNEM_vmlsdavx
18177 || inst.instruction == M_MNEM_vmlsdavax)
18178 inst.instruction |= (et.size == 8) << 28;
18179 else
18180 inst.instruction |= (et.size == 8) << 8;
18181
18182 mve_encode_rqq (et.type == NT_unsigned, 64);
18183 inst.instruction |= (et.size == 32) << 16;
18184}
18185
93925576
AV		 18186static void
18187do_mve_vmlaldav (void)
18188{
18189 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
18190 struct neon_type_el et
18191 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
18192 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
18193
18194 if (et.type == NT_unsigned
18195 && (inst.instruction == M_MNEM_vmlsldav
18196 || inst.instruction == M_MNEM_vmlsldava
18197 || inst.instruction == M_MNEM_vmlsldavx
18198 || inst.instruction == M_MNEM_vmlsldavax))
18199 first_error (BAD_SIMD_TYPE);
18200
18201 if (inst.cond > COND_ALWAYS)
18202 inst.pred_insn_type = INSIDE_VPT_INSN;
18203 else
18204 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18205
18206 mve_encode_rrqq (et.type == NT_unsigned, et.size);
18207}
18208
18209static void
18210do_mve_vrmlaldavh (void)
18211{
18212 struct neon_type_el et;
18213 if (inst.instruction == M_MNEM_vrmlsldavh
18214 || inst.instruction == M_MNEM_vrmlsldavha
18215 || inst.instruction == M_MNEM_vrmlsldavhx
18216 || inst.instruction == M_MNEM_vrmlsldavhax)
18217 {
18218 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18219 if (inst.operands[1].reg == REG_SP)
18220 as_tsktsk (MVE_BAD_SP);
18221 }
18222 else
18223 {
18224 if (inst.instruction == M_MNEM_vrmlaldavhx
18225 || inst.instruction == M_MNEM_vrmlaldavhax)
18226 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18227 else
18228 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
18229 N_U32 | N_S32 | N_KEY);
18230 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18231 with vmax/min instructions, making the use of SP in assembly really
18232 nonsensical, so instead of issuing a warning like we do for other uses
18233 of SP for the odd register operand we error out. */
18234 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18235 }
18236
18237 /* Make sure we still check the second operand is an odd one and that PC is
18238 disallowed. This because we are parsing for any GPR operand, to be able
18239 to distinguish between giving a warning or an error for SP as described
18240 above. */
18241 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18242 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18243
18244 if (inst.cond > COND_ALWAYS)
18245 inst.pred_insn_type = INSIDE_VPT_INSN;
18246 else
18247 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18248
18249 mve_encode_rrqq (et.type == NT_unsigned, 0);
18250}
18251
18252
8cd78170
AV		 18253static void
18254do_mve_vmaxnmv (void)
18255{
18256 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18257 struct neon_type_el et
18258 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
18259
18260 if (inst.cond > COND_ALWAYS)
18261 inst.pred_insn_type = INSIDE_VPT_INSN;
18262 else
18263 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18264
18265 if (inst.operands[0].reg == REG_SP)
18266 as_tsktsk (MVE_BAD_SP);
18267 else if (inst.operands[0].reg == REG_PC)
18268 as_tsktsk (MVE_BAD_PC);
18269
18270 mve_encode_rq (et.size == 16, 64);
18271}
18272
13ccd4c0
AV		 18273static void
18274do_mve_vmaxv (void)
18275{
18276 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18277 struct neon_type_el et;
18278
18279 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18280 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
18281 else
18282 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18283
18284 if (inst.cond > COND_ALWAYS)
18285 inst.pred_insn_type = INSIDE_VPT_INSN;
18286 else
18287 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18288
18289 if (inst.operands[0].reg == REG_SP)
18290 as_tsktsk (MVE_BAD_SP);
18291 else if (inst.operands[0].reg == REG_PC)
18292 as_tsktsk (MVE_BAD_PC);
18293
18294 mve_encode_rq (et.type == NT_unsigned, et.size);
18295}
18296
18297
643afb90
MW		 18298static void
18299do_neon_qrdmlah (void)
18300{
64c350f2 18301 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV		 18302 return;
18303 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
643afb90 18304 {
42b16635
AV		 18305 /* Check we're on the correct architecture. */
18306 if (!mark_feature_used (&fpu_neon_ext_armv8))
18307 inst.error
18308 = _("instruction form not available on this architecture.");
18309 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
18310 {
18311 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18312 record_feature_use (&fpu_neon_ext_v8_1);
18313 }
18314 if (inst.operands[2].isscalar)
18315 {
18316 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18317 struct neon_type_el et = neon_check_type (3, rs,
18318 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18319 NEON_ENCODE (SCALAR, inst);
18320 neon_mul_mac (et, neon_quad (rs));
18321 }
18322 else
18323 {
18324 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18325 struct neon_type_el et = neon_check_type (3, rs,
18326 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18327 NEON_ENCODE (INTEGER, inst);
18328 /* The U bit (rounding) comes from bit mask. */
18329 neon_three_same (neon_quad (rs), 0, et.size);
18330 }
643afb90
MW		 18331 }
18332 else
18333 {
42b16635
AV		 18334 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18335 struct neon_type_el et
23d188c7 18336 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
42b16635 18337
643afb90 18338 NEON_ENCODE (INTEGER, inst);
42b16635 18339 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
643afb90
MW		 18340 }
18341}
18342
5287ad62
JB		 18343static void
18344do_neon_fcmp_absolute (void)
18345{
037e8744 18346 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW		 18347 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18348 N_F_16_32 | N_KEY);
5287ad62 18349 /* Size field comes from bit mask. */
cc933301 18350 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 18351}
18352
18353static void
18354do_neon_fcmp_absolute_inv (void)
18355{
18356 neon_exchange_operands ();
18357 do_neon_fcmp_absolute ();
18358}
18359
18360static void
18361do_neon_step (void)
18362{
037e8744 18363 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW		 18364 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18365 N_F_16_32 | N_KEY);
18366 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 18367}
18368
18369static void
18370do_neon_abs_neg (void)
18371{
037e8744
JB		 18372 enum neon_shape rs;
18373 struct neon_type_el et;
5f4273c7 18374
037e8744
JB		 18375 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
18376 return;
18377
037e8744 18378 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
cc933301 18379 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
5f4273c7 18380
64c350f2
AV		 18381 if (!check_simd_pred_availability (et.type == NT_float,
18382 NEON_CHECK_ARCH | NEON_CHECK_CC))
485dee97
AV		 18383 return;
18384
5287ad62
JB		 18385 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18386 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18387 inst.instruction |= LOW4 (inst.operands[1].reg);
18388 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 18389 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 18390 inst.instruction |= (et.type == NT_float) << 10;
18391 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18392
88714cb8 18393 neon_dp_fixup (&inst);
5287ad62
JB		 18394}
18395
18396static void
18397do_neon_sli (void)
18398{
64c350f2 18399 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 18400 return;
18401
18402 enum neon_shape rs;
18403 struct neon_type_el et;
18404 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18405 {
18406 rs = neon_select_shape (NS_QQI, NS_NULL);
18407 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18408 }
18409 else
18410 {
18411 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18412 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18413 }
18414
18415
5287ad62
JB		 18416 int imm = inst.operands[2].imm;
18417 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18418 _("immediate out of range for insert"));
037e8744 18419 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 18420}
18421
18422static void
18423do_neon_sri (void)
18424{
64c350f2 18425 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 18426 return;
18427
18428 enum neon_shape rs;
18429 struct neon_type_el et;
18430 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18431 {
18432 rs = neon_select_shape (NS_QQI, NS_NULL);
18433 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18434 }
18435 else
18436 {
18437 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18438 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18439 }
18440
5287ad62
JB		 18441 int imm = inst.operands[2].imm;
18442 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18443 _("immediate out of range for insert"));
037e8744 18444 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB		 18445}
18446
18447static void
18448do_neon_qshlu_imm (void)
18449{
64c350f2 18450 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 18451 return;
18452
18453 enum neon_shape rs;
18454 struct neon_type_el et;
18455 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18456 {
18457 rs = neon_select_shape (NS_QQI, NS_NULL);
18458 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18459 }
18460 else
18461 {
18462 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18463 et = neon_check_type (2, rs, N_EQK | N_UNS,
18464 N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
18465 }
18466
5287ad62
JB		 18467 int imm = inst.operands[2].imm;
18468 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18469 _("immediate out of range for shift"));
5287ad62
JB		 18470 /* Only encodes the 'U present' variant of the instruction.
18471 In this case, signed types have OP (bit 8) set to 0.
18472 Unsigned types have OP set to 1. */
18473 inst.instruction |= (et.type == NT_unsigned) << 8;
18474 /* The rest of the bits are the same as other immediate shifts. */
037e8744 18475 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 18476}
18477
18478static void
18479do_neon_qmovn (void)
18480{
18481 struct neon_type_el et = neon_check_type (2, NS_DQ,
18482 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18483 /* Saturating move where operands can be signed or unsigned, and the
18484 destination has the same signedness. */
88714cb8 18485 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18486 if (et.type == NT_unsigned)
18487 inst.instruction |= 0xc0;
18488 else
18489 inst.instruction |= 0x80;
18490 neon_two_same (0, 1, et.size / 2);
18491}
18492
18493static void
18494do_neon_qmovun (void)
18495{
18496 struct neon_type_el et = neon_check_type (2, NS_DQ,
18497 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18498 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 18499 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18500 neon_two_same (0, 1, et.size / 2);
18501}
18502
18503static void
18504do_neon_rshift_sat_narrow (void)
18505{
18506 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18507 or unsigned. If operands are unsigned, results must also be unsigned. */
18508 struct neon_type_el et = neon_check_type (2, NS_DQI,
18509 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18510 int imm = inst.operands[2].imm;
18511 /* This gets the bounds check, size encoding and immediate bits calculation
18512 right. */
18513 et.size /= 2;
5f4273c7 18514
5287ad62
JB		 18515 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18516 VQMOVN.I<size> <Dd>, <Qm>. */
18517 if (imm == 0)
18518 {
18519 inst.operands[2].present = 0;
18520 inst.instruction = N_MNEM_vqmovn;
18521 do_neon_qmovn ();
18522 return;
18523 }
5f4273c7 18524
5287ad62 18525 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18526 _("immediate out of range"));
5287ad62
JB		 18527 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
18528}
18529
18530static void
18531do_neon_rshift_sat_narrow_u (void)
18532{
18533 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18534 or unsigned. If operands are unsigned, results must also be unsigned. */
18535 struct neon_type_el et = neon_check_type (2, NS_DQI,
18536 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18537 int imm = inst.operands[2].imm;
18538 /* This gets the bounds check, size encoding and immediate bits calculation
18539 right. */
18540 et.size /= 2;
18541
18542 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18543 VQMOVUN.I<size> <Dd>, <Qm>. */
18544 if (imm == 0)
18545 {
18546 inst.operands[2].present = 0;
18547 inst.instruction = N_MNEM_vqmovun;
18548 do_neon_qmovun ();
18549 return;
18550 }
18551
18552 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18553 _("immediate out of range"));
5287ad62
JB		 18554 /* FIXME: The manual is kind of unclear about what value U should have in
18555 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18556 must be 1. */
18557 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
18558}
18559
18560static void
18561do_neon_movn (void)
18562{
18563 struct neon_type_el et = neon_check_type (2, NS_DQ,
18564 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 18565 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18566 neon_two_same (0, 1, et.size / 2);
18567}
18568
18569static void
18570do_neon_rshift_narrow (void)
18571{
18572 struct neon_type_el et = neon_check_type (2, NS_DQI,
18573 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18574 int imm = inst.operands[2].imm;
18575 /* This gets the bounds check, size encoding and immediate bits calculation
18576 right. */
18577 et.size /= 2;
5f4273c7 18578
5287ad62
JB		 18579 /* If immediate is zero then we are a pseudo-instruction for
18580 VMOVN.I<size> <Dd>, <Qm> */
18581 if (imm == 0)
18582 {
18583 inst.operands[2].present = 0;
18584 inst.instruction = N_MNEM_vmovn;
18585 do_neon_movn ();
18586 return;
18587 }
5f4273c7 18588
5287ad62 18589 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18590 _("immediate out of range for narrowing operation"));
5287ad62
JB		 18591 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
18592}
18593
18594static void
18595do_neon_shll (void)
18596{
18597 /* FIXME: Type checking when lengthening. */
18598 struct neon_type_el et = neon_check_type (2, NS_QDI,
18599 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
18600 unsigned imm = inst.operands[2].imm;
18601
18602 if (imm == et.size)
18603 {
18604 /* Maximum shift variant. */
88714cb8 18605 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18606 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18607 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18608 inst.instruction |= LOW4 (inst.operands[1].reg);
18609 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18610 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18611
88714cb8 18612 neon_dp_fixup (&inst);
5287ad62
JB		 18613 }
18614 else
18615 {
18616 /* A more-specific type check for non-max versions. */
18617 et = neon_check_type (2, NS_QDI,
477330fc 18618 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 18619 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 18620 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
18621 }
18622}
18623
037e8744 18624/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB		 18625 the current instruction is. */
18626
6b9a8b67
MGD		 18627#define CVT_FLAVOUR_VAR \
18628 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18629 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18630 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18631 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18632 /* Half-precision conversions. */ \
cc933301
JW		 18633 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18634 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18635 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18636 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
6b9a8b67
MGD		 18637 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18638 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
9db2f6b4
RL		 18639 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18640 Compared with single/double precision variants, only the co-processor \
18641 field is different, so the encoding flow is reused here. */ \
18642 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18643 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18644 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18645 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
6b9a8b67
MGD		 18646 /* VFP instructions. */ \
18647 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18648 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18649 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18650 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18651 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18652 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18653 /* VFP instructions with bitshift. */ \
18654 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18655 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18656 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18657 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18658 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18659 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18660 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18661 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18662
18663#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18664 neon_cvt_flavour_##C,
18665
18666/* The different types of conversions we can do. */
18667enum neon_cvt_flavour
18668{
18669 CVT_FLAVOUR_VAR
18670 neon_cvt_flavour_invalid,
18671 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
18672};
18673
18674#undef CVT_VAR
18675
18676static enum neon_cvt_flavour
18677get_neon_cvt_flavour (enum neon_shape rs)
5287ad62 18678{
6b9a8b67
MGD		 18679#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18680 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18681 if (et.type != NT_invtype) \
18682 { \
18683 inst.error = NULL; \
18684 return (neon_cvt_flavour_##C); \
5287ad62 18685 }
6b9a8b67 18686
5287ad62 18687 struct neon_type_el et;
037e8744 18688 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
477330fc 18689 || rs == NS_FF) ? N_VFP : 0;
037e8744
JB		 18690 /* The instruction versions which take an immediate take one register
18691 argument, which is extended to the width of the full register. Thus the
18692 "source" and "destination" registers must have the same width. Hack that
18693 here by making the size equal to the key (wider, in this case) operand. */
18694 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 18695
6b9a8b67
MGD		 18696 CVT_FLAVOUR_VAR;
18697
18698 return neon_cvt_flavour_invalid;
5287ad62
JB		 18699#undef CVT_VAR
18700}
18701
7e8e6784
MGD		 18702enum neon_cvt_mode
18703{
18704 neon_cvt_mode_a,
18705 neon_cvt_mode_n,
18706 neon_cvt_mode_p,
18707 neon_cvt_mode_m,
18708 neon_cvt_mode_z,
30bdf752
MGD		 18709 neon_cvt_mode_x,
18710 neon_cvt_mode_r
7e8e6784
MGD		 18711};
18712
037e8744
JB		 18713/* Neon-syntax VFP conversions. */
18714
5287ad62 18715static void
6b9a8b67 18716do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
5287ad62 18717{
037e8744 18718 const char *opname = 0;
5f4273c7 18719
d54af2d0
RL		 18720 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
18721 || rs == NS_FHI || rs == NS_HFI)
5287ad62 18722 {
037e8744
JB		 18723 /* Conversions with immediate bitshift. */
18724 const char *enc[] =
477330fc 18725 {
6b9a8b67
MGD		 18726#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18727 CVT_FLAVOUR_VAR
18728 NULL
18729#undef CVT_VAR
477330fc 18730 };
037e8744 18731
6b9a8b67 18732 if (flavour < (int) ARRAY_SIZE (enc))
477330fc
RM		 18733 {
18734 opname = enc[flavour];
18735 constraint (inst.operands[0].reg != inst.operands[1].reg,
18736 _("operands 0 and 1 must be the same register"));
18737 inst.operands[1] = inst.operands[2];
18738 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18739 }
5287ad62
JB		 18740 }
18741 else
18742 {
037e8744
JB		 18743 /* Conversions without bitshift. */
18744 const char *enc[] =
477330fc 18745 {
6b9a8b67
MGD		 18746#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18747 CVT_FLAVOUR_VAR
18748 NULL
18749#undef CVT_VAR
477330fc 18750 };
037e8744 18751
6b9a8b67 18752 if (flavour < (int) ARRAY_SIZE (enc))
477330fc 18753 opname = enc[flavour];
037e8744
JB		 18754 }
18755
18756 if (opname)
18757 do_vfp_nsyn_opcode (opname);
9db2f6b4
RL		 18758
18759 /* ARMv8.2 fp16 VCVT instruction. */
18760 if (flavour == neon_cvt_flavour_s32_f16
18761 || flavour == neon_cvt_flavour_u32_f16
18762 || flavour == neon_cvt_flavour_f16_u32
18763 || flavour == neon_cvt_flavour_f16_s32)
18764 do_scalar_fp16_v82_encode ();
037e8744
JB		 18765}
18766
18767static void
18768do_vfp_nsyn_cvtz (void)
18769{
d54af2d0 18770 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
6b9a8b67 18771 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744
JB		 18772 const char *enc[] =
18773 {
6b9a8b67
MGD		 18774#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18775 CVT_FLAVOUR_VAR
18776 NULL
18777#undef CVT_VAR
037e8744
JB		 18778 };
18779
6b9a8b67 18780 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
037e8744
JB		 18781 do_vfp_nsyn_opcode (enc[flavour]);
18782}
f31fef98 18783
037e8744 18784static void
bacebabc 18785do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
7e8e6784
MGD		 18786 enum neon_cvt_mode mode)
18787{
18788 int sz, op;
18789 int rm;
18790
a715796b
TG		 18791 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18792 D register operands. */
18793 if (flavour == neon_cvt_flavour_s32_f64
18794 || flavour == neon_cvt_flavour_u32_f64)
18795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18796 _(BAD_FPU));
18797
9db2f6b4
RL		 18798 if (flavour == neon_cvt_flavour_s32_f16
18799 || flavour == neon_cvt_flavour_u32_f16)
18800 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
18801 _(BAD_FP16));
18802
5ee91343 18803 set_pred_insn_type (OUTSIDE_PRED_INSN);
7e8e6784
MGD		 18804
18805 switch (flavour)
18806 {
18807 case neon_cvt_flavour_s32_f64:
18808 sz = 1;
827f64ff 18809 op = 1;
7e8e6784
MGD		 18810 break;
18811 case neon_cvt_flavour_s32_f32:
18812 sz = 0;
18813 op = 1;
18814 break;
9db2f6b4
RL		 18815 case neon_cvt_flavour_s32_f16:
18816 sz = 0;
18817 op = 1;
18818 break;
7e8e6784
MGD		 18819 case neon_cvt_flavour_u32_f64:
18820 sz = 1;
18821 op = 0;
18822 break;
18823 case neon_cvt_flavour_u32_f32:
18824 sz = 0;
18825 op = 0;
18826 break;
9db2f6b4
RL		 18827 case neon_cvt_flavour_u32_f16:
18828 sz = 0;
18829 op = 0;
18830 break;
7e8e6784
MGD		 18831 default:
18832 first_error (_("invalid instruction shape"));
18833 return;
18834 }
18835
18836 switch (mode)
18837 {
18838 case neon_cvt_mode_a: rm = 0; break;
18839 case neon_cvt_mode_n: rm = 1; break;
18840 case neon_cvt_mode_p: rm = 2; break;
18841 case neon_cvt_mode_m: rm = 3; break;
18842 default: first_error (_("invalid rounding mode")); return;
18843 }
18844
18845 NEON_ENCODE (FPV8, inst);
18846 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
18847 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
18848 inst.instruction |= sz << 8;
9db2f6b4
RL		 18849
18850 /* ARMv8.2 fp16 VCVT instruction. */
18851 if (flavour == neon_cvt_flavour_s32_f16
18852 ||flavour == neon_cvt_flavour_u32_f16)
18853 do_scalar_fp16_v82_encode ();
7e8e6784
MGD		 18854 inst.instruction |= op << 7;
18855 inst.instruction |= rm << 16;
18856 inst.instruction |= 0xf0000000;
18857 inst.is_neon = TRUE;
18858}
18859
18860static void
18861do_neon_cvt_1 (enum neon_cvt_mode mode)
037e8744
JB		 18862{
18863 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
d54af2d0
RL		 18864 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
18865 NS_FH, NS_HF, NS_FHI, NS_HFI,
18866 NS_NULL);
6b9a8b67 18867 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744 18868
cc933301
JW		 18869 if (flavour == neon_cvt_flavour_invalid)
18870 return;
18871
e3e535bc 18872 /* PR11109: Handle round-to-zero for VCVT conversions. */
7e8e6784 18873 if (mode == neon_cvt_mode_z
e3e535bc 18874 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
cc933301
JW		 18875 && (flavour == neon_cvt_flavour_s16_f16
18876 || flavour == neon_cvt_flavour_u16_f16
18877 || flavour == neon_cvt_flavour_s32_f32
bacebabc
RM		 18878 || flavour == neon_cvt_flavour_u32_f32
18879 || flavour == neon_cvt_flavour_s32_f64
6b9a8b67 18880 || flavour == neon_cvt_flavour_u32_f64)
e3e535bc
NC		 18881 && (rs == NS_FD || rs == NS_FF))
18882 {
18883 do_vfp_nsyn_cvtz ();
18884 return;
18885 }
18886
9db2f6b4
RL		 18887 /* ARMv8.2 fp16 VCVT conversions. */
18888 if (mode == neon_cvt_mode_z
18889 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
18890 && (flavour == neon_cvt_flavour_s32_f16
18891 || flavour == neon_cvt_flavour_u32_f16)
18892 && (rs == NS_FH))
18893 {
18894 do_vfp_nsyn_cvtz ();
18895 do_scalar_fp16_v82_encode ();
18896 return;
18897 }
18898
037e8744 18899 /* VFP rather than Neon conversions. */
6b9a8b67 18900 if (flavour >= neon_cvt_flavour_first_fp)
037e8744 18901 {
7e8e6784
MGD		 18902 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18903 do_vfp_nsyn_cvt (rs, flavour);
18904 else
18905 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18906
037e8744
JB		 18907 return;
18908 }
18909
18910 switch (rs)
18911 {
037e8744 18912 case NS_QQI:
dd9634d9
AV		 18913 if (mode == neon_cvt_mode_z
18914 && (flavour == neon_cvt_flavour_f16_s16
18915 || flavour == neon_cvt_flavour_f16_u16
18916 || flavour == neon_cvt_flavour_s16_f16
18917 || flavour == neon_cvt_flavour_u16_f16
18918 || flavour == neon_cvt_flavour_f32_u32
18919 || flavour == neon_cvt_flavour_f32_s32
18920 || flavour == neon_cvt_flavour_s32_f32
18921 || flavour == neon_cvt_flavour_u32_f32))
18922 {
64c350f2
AV		 18923 if (!check_simd_pred_availability (TRUE,
18924 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV		 18925 return;
18926 }
18927 else if (mode == neon_cvt_mode_n)
18928 {
18929 /* We are dealing with vcvt with the 'ne' condition. */
18930 inst.cond = 0x1;
18931 inst.instruction = N_MNEM_vcvt;
18932 do_neon_cvt_1 (neon_cvt_mode_z);
18933 return;
18934 }
18935 /* fall through. */
18936 case NS_DDI:
037e8744 18937 {
477330fc 18938 unsigned immbits;
cc933301
JW		 18939 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18940 0x0000100, 0x1000100, 0x0, 0x1000000};
35997600 18941
dd9634d9
AV		 18942 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18943 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18944 return;
18945
18946 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18947 {
18948 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
18949 _("immediate value out of range"));
18950 switch (flavour)
18951 {
18952 case neon_cvt_flavour_f16_s16:
18953 case neon_cvt_flavour_f16_u16:
18954 case neon_cvt_flavour_s16_f16:
18955 case neon_cvt_flavour_u16_f16:
18956 constraint (inst.operands[2].imm > 16,
18957 _("immediate value out of range"));
18958 break;
18959 case neon_cvt_flavour_f32_u32:
18960 case neon_cvt_flavour_f32_s32:
18961 case neon_cvt_flavour_s32_f32:
18962 case neon_cvt_flavour_u32_f32:
18963 constraint (inst.operands[2].imm > 32,
18964 _("immediate value out of range"));
18965 break;
18966 default:
18967 inst.error = BAD_FPU;
18968 return;
18969 }
18970 }
037e8744 18971
477330fc
RM		 18972 /* Fixed-point conversion with #0 immediate is encoded as an
18973 integer conversion. */
18974 if (inst.operands[2].present && inst.operands[2].imm == 0)
18975 goto int_encode;
477330fc
RM		 18976 NEON_ENCODE (IMMED, inst);
18977 if (flavour != neon_cvt_flavour_invalid)
18978 inst.instruction |= enctab[flavour];
18979 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18980 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18981 inst.instruction |= LOW4 (inst.operands[1].reg);
18982 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18983 inst.instruction |= neon_quad (rs) << 6;
18984 inst.instruction |= 1 << 21;
cc933301
JW		 18985 if (flavour < neon_cvt_flavour_s16_f16)
18986 {
18987 inst.instruction |= 1 << 21;
18988 immbits = 32 - inst.operands[2].imm;
18989 inst.instruction |= immbits << 16;
18990 }
18991 else
18992 {
18993 inst.instruction |= 3 << 20;
18994 immbits = 16 - inst.operands[2].imm;
18995 inst.instruction |= immbits << 16;
18996 inst.instruction &= ~(1 << 9);
18997 }
477330fc
RM		 18998
18999 neon_dp_fixup (&inst);
037e8744
JB		 19000 }
19001 break;
19002
037e8744 19003 case NS_QQ:
dd9634d9
AV		 19004 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
19005 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
19006 && (flavour == neon_cvt_flavour_s16_f16
19007 || flavour == neon_cvt_flavour_u16_f16
19008 || flavour == neon_cvt_flavour_s32_f32
19009 || flavour == neon_cvt_flavour_u32_f32))
19010 {
64c350f2
AV		 19011 if (!check_simd_pred_availability (TRUE,
19012 NEON_CHECK_CC | NEON_CHECK_ARCH8))
dd9634d9
AV		 19013 return;
19014 }
19015 else if (mode == neon_cvt_mode_z
19016 && (flavour == neon_cvt_flavour_f16_s16
19017 || flavour == neon_cvt_flavour_f16_u16
19018 || flavour == neon_cvt_flavour_s16_f16
19019 || flavour == neon_cvt_flavour_u16_f16
19020 || flavour == neon_cvt_flavour_f32_u32
19021 || flavour == neon_cvt_flavour_f32_s32
19022 || flavour == neon_cvt_flavour_s32_f32
19023 || flavour == neon_cvt_flavour_u32_f32))
19024 {
64c350f2
AV		 19025 if (!check_simd_pred_availability (TRUE,
19026 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV		 19027 return;
19028 }
19029 /* fall through. */
19030 case NS_DD:
7e8e6784
MGD		 19031 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
19032 {
7e8e6784 19033
dd9634d9 19034 NEON_ENCODE (FLOAT, inst);
64c350f2
AV		 19035 if (!check_simd_pred_availability (TRUE,
19036 NEON_CHECK_CC | NEON_CHECK_ARCH8))
7e8e6784
MGD		 19037 return;
19038
19039 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19040 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19041 inst.instruction |= LOW4 (inst.operands[1].reg);
19042 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19043 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 19044 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
19045 || flavour == neon_cvt_flavour_u32_f32) << 7;
7e8e6784 19046 inst.instruction |= mode << 8;
cc933301
JW		 19047 if (flavour == neon_cvt_flavour_u16_f16
19048 || flavour == neon_cvt_flavour_s16_f16)
19049 /* Mask off the original size bits and reencode them. */
19050 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
19051
7e8e6784
MGD		 19052 if (thumb_mode)
19053 inst.instruction |= 0xfc000000;
19054 else
19055 inst.instruction |= 0xf0000000;
19056 }
19057 else
19058 {
037e8744 19059 int_encode:
7e8e6784 19060 {
cc933301
JW		 19061 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
19062 0x100, 0x180, 0x0, 0x080};
037e8744 19063
7e8e6784 19064 NEON_ENCODE (INTEGER, inst);
037e8744 19065
dd9634d9
AV		 19066 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19067 {
19068 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19069 return;
19070 }
037e8744 19071
7e8e6784
MGD		 19072 if (flavour != neon_cvt_flavour_invalid)
19073 inst.instruction |= enctab[flavour];
037e8744 19074
7e8e6784
MGD		 19075 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19076 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19077 inst.instruction |= LOW4 (inst.operands[1].reg);
19078 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19079 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 19080 if (flavour >= neon_cvt_flavour_s16_f16
19081 && flavour <= neon_cvt_flavour_f16_u16)
19082 /* Half precision. */
19083 inst.instruction |= 1 << 18;
19084 else
19085 inst.instruction |= 2 << 18;
037e8744 19086
7e8e6784
MGD		 19087 neon_dp_fixup (&inst);
19088 }
19089 }
19090 break;
037e8744 19091
8e79c3df
CM		 19092 /* Half-precision conversions for Advanced SIMD -- neon. */
19093 case NS_QD:
19094 case NS_DQ:
bc52d49c
MM		 19095 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19096 return;
8e79c3df
CM		 19097
19098 if ((rs == NS_DQ)
19099 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
19100 {
19101 as_bad (_("operand size must match register width"));
19102 break;
19103 }
19104
19105 if ((rs == NS_QD)
19106 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
19107 {
19108 as_bad (_("operand size must match register width"));
19109 break;
19110 }
19111
19112 if (rs == NS_DQ)
477330fc 19113 inst.instruction = 0x3b60600;
8e79c3df
CM		 19114 else
19115 inst.instruction = 0x3b60700;
19116
19117 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19118 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19119 inst.instruction |= LOW4 (inst.operands[1].reg);
19120 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 19121 neon_dp_fixup (&inst);
8e79c3df
CM		 19122 break;
19123
037e8744
JB		 19124 default:
19125 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
7e8e6784
MGD		 19126 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19127 do_vfp_nsyn_cvt (rs, flavour);
19128 else
19129 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
5287ad62 19130 }
5287ad62
JB		 19131}
19132
e3e535bc
NC		 19133static void
19134do_neon_cvtr (void)
19135{
7e8e6784 19136 do_neon_cvt_1 (neon_cvt_mode_x);
e3e535bc
NC		 19137}
19138
19139static void
19140do_neon_cvt (void)
19141{
7e8e6784
MGD		 19142 do_neon_cvt_1 (neon_cvt_mode_z);
19143}
19144
19145static void
19146do_neon_cvta (void)
19147{
19148 do_neon_cvt_1 (neon_cvt_mode_a);
19149}
19150
19151static void
19152do_neon_cvtn (void)
19153{
19154 do_neon_cvt_1 (neon_cvt_mode_n);
19155}
19156
19157static void
19158do_neon_cvtp (void)
19159{
19160 do_neon_cvt_1 (neon_cvt_mode_p);
19161}
19162
19163static void
19164do_neon_cvtm (void)
19165{
19166 do_neon_cvt_1 (neon_cvt_mode_m);
e3e535bc
NC		 19167}
19168
8e79c3df 19169static void
c70a8987 19170do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
8e79c3df 19171{
c70a8987
MGD		 19172 if (is_double)
19173 mark_feature_used (&fpu_vfp_ext_armv8);
8e79c3df 19174
c70a8987
MGD		 19175 encode_arm_vfp_reg (inst.operands[0].reg,
19176 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
19177 encode_arm_vfp_reg (inst.operands[1].reg,
19178 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
19179 inst.instruction |= to ? 0x10000 : 0;
19180 inst.instruction |= t ? 0x80 : 0;
19181 inst.instruction |= is_double ? 0x100 : 0;
19182 do_vfp_cond_or_thumb ();
19183}
8e79c3df 19184
c70a8987
MGD		 19185static void
19186do_neon_cvttb_1 (bfd_boolean t)
19187{
d54af2d0 19188 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
dd9634d9 19189 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
8e79c3df 19190
c70a8987
MGD		 19191 if (rs == NS_NULL)
19192 return;
dd9634d9
AV		 19193 else if (rs == NS_QQ || rs == NS_QQI)
19194 {
19195 int single_to_half = 0;
64c350f2 19196 if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH))
dd9634d9
AV		 19197 return;
19198
19199 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19200
19201 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19202 && (flavour == neon_cvt_flavour_u16_f16
19203 || flavour == neon_cvt_flavour_s16_f16
19204 || flavour == neon_cvt_flavour_f16_s16
19205 || flavour == neon_cvt_flavour_f16_u16
19206 || flavour == neon_cvt_flavour_u32_f32
19207 || flavour == neon_cvt_flavour_s32_f32
19208 || flavour == neon_cvt_flavour_f32_s32
19209 || flavour == neon_cvt_flavour_f32_u32))
19210 {
19211 inst.cond = 0xf;
19212 inst.instruction = N_MNEM_vcvt;
19213 set_pred_insn_type (INSIDE_VPT_INSN);
19214 do_neon_cvt_1 (neon_cvt_mode_z);
19215 return;
19216 }
19217 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
19218 single_to_half = 1;
19219 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
19220 {
19221 first_error (BAD_FPU);
19222 return;
19223 }
19224
19225 inst.instruction = 0xee3f0e01;
19226 inst.instruction |= single_to_half << 28;
19227 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19228 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
19229 inst.instruction |= t << 12;
19230 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19231 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
19232 inst.is_neon = 1;
19233 }
c70a8987
MGD		 19234 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
19235 {
19236 inst.error = NULL;
19237 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
19238 }
19239 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
19240 {
19241 inst.error = NULL;
19242 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
19243 }
19244 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
19245 {
a715796b
TG		 19246 /* The VCVTB and VCVTT instructions with D-register operands
19247 don't work for SP only targets. */
19248 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19249 _(BAD_FPU));
19250
c70a8987
MGD		 19251 inst.error = NULL;
19252 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
19253 }
19254 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
19255 {
a715796b
TG		 19256 /* The VCVTB and VCVTT instructions with D-register operands
19257 don't work for SP only targets. */
19258 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19259 _(BAD_FPU));
19260
c70a8987
MGD		 19261 inst.error = NULL;
19262 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
19263 }
19264 else
19265 return;
19266}
19267
19268static void
19269do_neon_cvtb (void)
19270{
19271 do_neon_cvttb_1 (FALSE);
8e79c3df
CM		 19272}
19273
19274
19275static void
19276do_neon_cvtt (void)
19277{
c70a8987 19278 do_neon_cvttb_1 (TRUE);
8e79c3df
CM		 19279}
19280
5287ad62
JB		 19281static void
19282neon_move_immediate (void)
19283{
037e8744
JB		 19284 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
19285 struct neon_type_el et = neon_check_type (2, rs,
19286 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 19287 unsigned immlo, immhi = 0, immbits;
c96612cc 19288 int op, cmode, float_p;
5287ad62 19289
037e8744 19290 constraint (et.type == NT_invtype,
477330fc 19291 _("operand size must be specified for immediate VMOV"));
037e8744 19292
5287ad62
JB		 19293 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19294 op = (inst.instruction & (1 << 5)) != 0;
19295
19296 immlo = inst.operands[1].imm;
19297 if (inst.operands[1].regisimm)
19298 immhi = inst.operands[1].reg;
19299
19300 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
477330fc 19301 _("immediate has bits set outside the operand size"));
5287ad62 19302
c96612cc
JB		 19303 float_p = inst.operands[1].immisfloat;
19304
19305 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
477330fc 19306 et.size, et.type)) == FAIL)
5287ad62
JB		 19307 {
19308 /* Invert relevant bits only. */
19309 neon_invert_size (&immlo, &immhi, et.size);
19310 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
477330fc
RM		 19311 with one or the other; those cases are caught by
19312 neon_cmode_for_move_imm. */
5287ad62 19313 op = !op;
c96612cc
JB		 19314 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
19315 &op, et.size, et.type)) == FAIL)
477330fc
RM		 19316 {
19317 first_error (_("immediate out of range"));
19318 return;
19319 }
5287ad62
JB		 19320 }
19321
19322 inst.instruction &= ~(1 << 5);
19323 inst.instruction |= op << 5;
19324
19325 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19326 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 19327 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19328 inst.instruction |= cmode << 8;
19329
19330 neon_write_immbits (immbits);
19331}
19332
19333static void
19334do_neon_mvn (void)
19335{
64c350f2 19336 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV		 19337 return;
19338
5287ad62
JB		 19339 if (inst.operands[1].isreg)
19340 {
1a186d29
AV		 19341 enum neon_shape rs;
19342 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19343 rs = neon_select_shape (NS_QQ, NS_NULL);
19344 else
19345 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 19346
88714cb8 19347 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 19348 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19349 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19350 inst.instruction |= LOW4 (inst.operands[1].reg);
19351 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 19352 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19353 }
19354 else
19355 {
88714cb8 19356 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 19357 neon_move_immediate ();
19358 }
19359
88714cb8 19360 neon_dp_fixup (&inst);
1a186d29
AV		 19361
19362 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19363 {
19364 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
19365 constraint ((inst.instruction & 0xd00) == 0xd00,
19366 _("immediate value out of range"));
19367 }
5287ad62
JB		 19368}
19369
19370/* Encode instructions of form:
19371
19372 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 19373 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB		 19374
19375static void
19376neon_mixed_length (struct neon_type_el et, unsigned size)
19377{
19378 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19379 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19380 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19381 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19382 inst.instruction |= LOW4 (inst.operands[2].reg);
19383 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19384 inst.instruction |= (et.type == NT_unsigned) << 24;
19385 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 19386
88714cb8 19387 neon_dp_fixup (&inst);
5287ad62
JB		 19388}
19389
19390static void
19391do_neon_dyadic_long (void)
19392{
5ee91343
AV		 19393 enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
19394 if (rs == NS_QDD)
19395 {
19396 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
19397 return;
19398
19399 NEON_ENCODE (INTEGER, inst);
19400 /* FIXME: Type checking for lengthening op. */
19401 struct neon_type_el et = neon_check_type (3, NS_QDD,
19402 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
19403 neon_mixed_length (et, et.size);
19404 }
19405 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19406 && (inst.cond == 0xf || inst.cond == 0x10))
19407 {
19408 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19409 in an IT block with le/lt conditions. */
19410
19411 if (inst.cond == 0xf)
19412 inst.cond = 0xb;
19413 else if (inst.cond == 0x10)
19414 inst.cond = 0xd;
19415
19416 inst.pred_insn_type = INSIDE_IT_INSN;
19417
19418 if (inst.instruction == N_MNEM_vaddl)
19419 {
19420 inst.instruction = N_MNEM_vadd;
19421 do_neon_addsub_if_i ();
19422 }
19423 else if (inst.instruction == N_MNEM_vsubl)
19424 {
19425 inst.instruction = N_MNEM_vsub;
19426 do_neon_addsub_if_i ();
19427 }
19428 else if (inst.instruction == N_MNEM_vabdl)
19429 {
19430 inst.instruction = N_MNEM_vabd;
19431 do_neon_dyadic_if_su ();
19432 }
19433 }
19434 else
19435 first_error (BAD_FPU);
5287ad62
JB		 19436}
19437
19438static void
19439do_neon_abal (void)
19440{
19441 struct neon_type_el et = neon_check_type (3, NS_QDD,
19442 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
19443 neon_mixed_length (et, et.size);
19444}
19445
19446static void
19447neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
19448{
19449 if (inst.operands[2].isscalar)
19450 {
dcbf9037 19451 struct neon_type_el et = neon_check_type (3, NS_QDS,
477330fc 19452 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 19453 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 19454 neon_mul_mac (et, et.type == NT_unsigned);
19455 }
19456 else
19457 {
19458 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19459 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 19460 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 19461 neon_mixed_length (et, et.size);
19462 }
19463}
19464
19465static void
19466do_neon_mac_maybe_scalar_long (void)
19467{
19468 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
19469}
19470
dec41383
JW		 19471/* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19472 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19473
19474static unsigned
19475neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
19476{
19477 unsigned regno = NEON_SCALAR_REG (scalar);
19478 unsigned elno = NEON_SCALAR_INDEX (scalar);
19479
19480 if (quad_p)
19481 {
19482 if (regno > 7 || elno > 3)
19483 goto bad_scalar;
19484
19485 return ((regno & 0x7)
19486 | ((elno & 0x1) << 3)
19487 | (((elno >> 1) & 0x1) << 5));
19488 }
19489 else
19490 {
19491 if (regno > 15 || elno > 1)
19492 goto bad_scalar;
19493
19494 return (((regno & 0x1) << 5)
19495 | ((regno >> 1) & 0x7)
19496 | ((elno & 0x1) << 3));
19497 }
19498
19499bad_scalar:
19500 first_error (_("scalar out of range for multiply instruction"));
19501 return 0;
19502}
19503
19504static void
19505do_neon_fmac_maybe_scalar_long (int subtype)
19506{
19507 enum neon_shape rs;
19508 int high8;
19509 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19510 field (bits[21:20]) has different meaning. For scalar index variant, it's
19511 used to differentiate add and subtract, otherwise it's with fixed value
19512 0x2. */
19513 int size = -1;
19514
19515 if (inst.cond != COND_ALWAYS)
19516 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19517 "behaviour is UNPREDICTABLE"));
19518
01f48020 19519 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
dec41383
JW		 19520 _(BAD_FP16));
19521
19522 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
19523 _(BAD_FPU));
19524
19525 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19526 be a scalar index register. */
19527 if (inst.operands[2].isscalar)
19528 {
19529 high8 = 0xfe000000;
19530 if (subtype)
19531 size = 16;
19532 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
19533 }
19534 else
19535 {
19536 high8 = 0xfc000000;
19537 size = 32;
19538 if (subtype)
19539 inst.instruction |= (0x1 << 23);
19540 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
19541 }
19542
19543 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
19544
19545 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19546 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19547 so we simply pass -1 as size. */
19548 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
19549 neon_three_same (quad_p, 0, size);
19550
19551 /* Undo neon_dp_fixup. Redo the high eight bits. */
19552 inst.instruction &= 0x00ffffff;
19553 inst.instruction |= high8;
19554
19555#define LOW1(R) ((R) & 0x1)
19556#define HI4(R) (((R) >> 1) & 0xf)
19557 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19558 whether the instruction is in Q form and whether Vm is a scalar indexed
19559 operand. */
19560 if (inst.operands[2].isscalar)
19561 {
19562 unsigned rm
19563 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19564 inst.instruction &= 0xffffffd0;
19565 inst.instruction |= rm;
19566
19567 if (!quad_p)
19568 {
19569 /* Redo Rn as well. */
19570 inst.instruction &= 0xfff0ff7f;
19571 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19572 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19573 }
19574 }
19575 else if (!quad_p)
19576 {
19577 /* Redo Rn and Rm. */
19578 inst.instruction &= 0xfff0ff50;
19579 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19580 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19581 inst.instruction |= HI4 (inst.operands[2].reg);
19582 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19583 }
19584}
19585
19586static void
19587do_neon_vfmal (void)
19588{
19589 return do_neon_fmac_maybe_scalar_long (0);
19590}
19591
19592static void
19593do_neon_vfmsl (void)
19594{
19595 return do_neon_fmac_maybe_scalar_long (1);
19596}
19597
5287ad62
JB		 19598static void
19599do_neon_dyadic_wide (void)
19600{
19601 struct neon_type_el et = neon_check_type (3, NS_QQD,
19602 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
19603 neon_mixed_length (et, et.size);
19604}
19605
19606static void
19607do_neon_dyadic_narrow (void)
19608{
19609 struct neon_type_el et = neon_check_type (3, NS_QDD,
19610 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB		 19611 /* Operand sign is unimportant, and the U bit is part of the opcode,
19612 so force the operand type to integer. */
19613 et.type = NT_integer;
5287ad62
JB		 19614 neon_mixed_length (et, et.size / 2);
19615}
19616
19617static void
19618do_neon_mul_sat_scalar_long (void)
19619{
19620 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
19621}
19622
19623static void
19624do_neon_vmull (void)
19625{
19626 if (inst.operands[2].isscalar)
19627 do_neon_mac_maybe_scalar_long ();
19628 else
19629 {
19630 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19631 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
4f51b4bd 19632
5287ad62 19633 if (et.type == NT_poly)
477330fc 19634 NEON_ENCODE (POLY, inst);
5287ad62 19635 else
477330fc 19636 NEON_ENCODE (INTEGER, inst);
4f51b4bd
MGD		 19637
19638 /* For polynomial encoding the U bit must be zero, and the size must
19639 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19640 obviously, as 0b10). */
19641 if (et.size == 64)
19642 {
19643 /* Check we're on the correct architecture. */
19644 if (!mark_feature_used (&fpu_crypto_ext_armv8))
19645 inst.error =
19646 _("Instruction form not available on this architecture.");
19647
19648 et.size = 32;
19649 }
19650
5287ad62
JB		 19651 neon_mixed_length (et, et.size);
19652 }
19653}
19654
19655static void
19656do_neon_ext (void)
19657{
037e8744 19658 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB		 19659 struct neon_type_el et = neon_check_type (3, rs,
19660 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
19661 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC		 19662
19663 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
19664 _("shift out of range"));
5287ad62
JB		 19665 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19666 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19667 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19668 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19669 inst.instruction |= LOW4 (inst.operands[2].reg);
19670 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 19671 inst.instruction |= neon_quad (rs) << 6;
5287ad62 19672 inst.instruction |= imm << 8;
5f4273c7 19673
88714cb8 19674 neon_dp_fixup (&inst);
5287ad62
JB		 19675}
19676
19677static void
19678do_neon_rev (void)
19679{
64c350f2 19680 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 19681 return;
19682
19683 enum neon_shape rs;
19684 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19685 rs = neon_select_shape (NS_QQ, NS_NULL);
19686 else
19687 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19688
5287ad62
JB		 19689 struct neon_type_el et = neon_check_type (2, rs,
19690 N_EQK, N_8 | N_16 | N_32 | N_KEY);
4401c241 19691
5287ad62
JB		 19692 unsigned op = (inst.instruction >> 7) & 3;
19693 /* N (width of reversed regions) is encoded as part of the bitmask. We
19694 extract it here to check the elements to be reversed are smaller.
19695 Otherwise we'd get a reserved instruction. */
19696 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
4401c241
AV		 19697
19698 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
19699 && inst.operands[0].reg == inst.operands[1].reg)
19700 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19701 " operands makes instruction UNPREDICTABLE"));
19702
9c2799c2 19703 gas_assert (elsize != 0);
5287ad62 19704 constraint (et.size >= elsize,
477330fc 19705 _("elements must be smaller than reversal region"));
037e8744 19706 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 19707}
19708
19709static void
19710do_neon_dup (void)
19711{
19712 if (inst.operands[1].isscalar)
19713 {
b409bdb6
AV		 19714 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19715 BAD_FPU);
037e8744 19716 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037 19717 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19718 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 19719 unsigned sizebits = et.size >> 3;
dcbf9037 19720 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 19721 int logsize = neon_logbits (et.size);
dcbf9037 19722 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB		 19723
19724 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
477330fc 19725 return;
037e8744 19726
88714cb8 19727 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 19728 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19729 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19730 inst.instruction |= LOW4 (dm);
19731 inst.instruction |= HI1 (dm) << 5;
037e8744 19732 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19733 inst.instruction |= x << 17;
19734 inst.instruction |= sizebits << 16;
5f4273c7 19735
88714cb8 19736 neon_dp_fixup (&inst);
5287ad62
JB		 19737 }
19738 else
19739 {
037e8744
JB		 19740 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
19741 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19742 N_8 | N_16 | N_32 | N_KEY, N_EQK);
b409bdb6
AV		 19743 if (rs == NS_QR)
19744 {
64c350f2 19745 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH))
b409bdb6
AV		 19746 return;
19747 }
19748 else
19749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19750 BAD_FPU);
19751
19752 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19753 {
19754 if (inst.operands[1].reg == REG_SP)
19755 as_tsktsk (MVE_BAD_SP);
19756 else if (inst.operands[1].reg == REG_PC)
19757 as_tsktsk (MVE_BAD_PC);
19758 }
19759
5287ad62 19760 /* Duplicate ARM register to lanes of vector. */
88714cb8 19761 NEON_ENCODE (ARMREG, inst);
5287ad62 19762 switch (et.size)
477330fc
RM		 19763 {
19764 case 8: inst.instruction |= 0x400000; break;
19765 case 16: inst.instruction |= 0x000020; break;
19766 case 32: inst.instruction |= 0x000000; break;
19767 default: break;
19768 }
5287ad62
JB		 19769 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19770 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19771 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 19772 inst.instruction |= neon_quad (rs) << 21;
5287ad62 19773 /* The encoding for this instruction is identical for the ARM and Thumb
477330fc 19774 variants, except for the condition field. */
037e8744 19775 do_vfp_cond_or_thumb ();
5287ad62
JB		 19776 }
19777}
19778
57785aa2
AV		 19779static void
19780do_mve_mov (int toQ)
19781{
19782 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19783 return;
19784 if (inst.cond > COND_ALWAYS)
19785 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19786
19787 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19788 if (toQ)
19789 {
19790 Q0 = 0;
19791 Q1 = 1;
19792 Rt = 2;
19793 Rt2 = 3;
19794 }
19795
19796 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
19797 _("Index one must be [2,3] and index two must be two less than"
19798 " index one."));
19799 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
19800 _("General purpose registers may not be the same"));
19801 constraint (inst.operands[Rt].reg == REG_SP
19802 || inst.operands[Rt2].reg == REG_SP,
19803 BAD_SP);
19804 constraint (inst.operands[Rt].reg == REG_PC
19805 || inst.operands[Rt2].reg == REG_PC,
19806 BAD_PC);
19807
19808 inst.instruction = 0xec000f00;
19809 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
19810 inst.instruction |= !!toQ << 20;
19811 inst.instruction |= inst.operands[Rt2].reg << 16;
19812 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
19813 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
19814 inst.instruction |= inst.operands[Rt].reg;
19815}
19816
19817static void
19818do_mve_movn (void)
19819{
19820 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19821 return;
19822
19823 if (inst.cond > COND_ALWAYS)
19824 inst.pred_insn_type = INSIDE_VPT_INSN;
19825 else
19826 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
19827
19828 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
19829 | N_KEY);
19830
19831 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19832 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
19833 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19834 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19835 inst.instruction |= LOW4 (inst.operands[1].reg);
19836 inst.is_neon = 1;
19837
19838}
19839
5287ad62
JB		 19840/* VMOV has particularly many variations. It can be one of:
19841 0. VMOV<c><q> <Qd>, <Qm>
19842 1. VMOV<c><q> <Dd>, <Dm>
19843 (Register operations, which are VORR with Rm = Rn.)
19844 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19845 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19846 (Immediate loads.)
19847 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19848 (ARM register to scalar.)
19849 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19850 (Two ARM registers to vector.)
19851 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19852 (Scalar to ARM register.)
19853 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19854 (Vector to two ARM registers.)
037e8744
JB		 19855 8. VMOV.F32 <Sd>, <Sm>
19856 9. VMOV.F64 <Dd>, <Dm>
19857 (VFP register moves.)
19858 10. VMOV.F32 <Sd>, #imm
19859 11. VMOV.F64 <Dd>, #imm
19860 (VFP float immediate load.)
19861 12. VMOV <Rd>, <Sm>
19862 (VFP single to ARM reg.)
19863 13. VMOV <Sd>, <Rm>
19864 (ARM reg to VFP single.)
19865 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19866 (Two ARM regs to two VFP singles.)
19867 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19868 (Two VFP singles to two ARM regs.)
57785aa2
AV		 19869 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19870 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19871 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19872 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
5f4273c7 19873
037e8744
JB		 19874 These cases can be disambiguated using neon_select_shape, except cases 1/9
19875 and 3/11 which depend on the operand type too.
5f4273c7 19876
5287ad62 19877 All the encoded bits are hardcoded by this function.
5f4273c7 19878
b7fc2769
JB		 19879 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19880 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 19881
5287ad62 19882 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 19883 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB		 19884
19885static void
19886do_neon_mov (void)
19887{
57785aa2
AV		 19888 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
19889 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
19890 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
19891 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
19892 NS_NULL);
037e8744
JB		 19893 struct neon_type_el et;
19894 const char *ldconst = 0;
5287ad62 19895
037e8744 19896 switch (rs)
5287ad62 19897 {
037e8744
JB		 19898 case NS_DD: /* case 1/9. */
19899 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19900 /* It is not an error here if no type is given. */
19901 inst.error = NULL;
1c1e0fe5
SP		 19902
19903 /* In MVE we interpret the following instructions as same, so ignoring
19904 the following type (float) and size (64) checks.
19905 a: VMOV<c><q> <Dd>, <Dm>
19906 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
19907 if ((et.type == NT_float && et.size == 64)
19908 || (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
477330fc
RM		 19909 {
19910 do_vfp_nsyn_opcode ("fcpyd");
19911 break;
19912 }
037e8744 19913 /* fall through. */
5287ad62 19914
037e8744
JB		 19915 case NS_QQ: /* case 0/1. */
19916 {
64c350f2
AV		 19917 if (!check_simd_pred_availability (FALSE,
19918 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc
RM		 19919 return;
19920 /* The architecture manual I have doesn't explicitly state which
19921 value the U bit should have for register->register moves, but
19922 the equivalent VORR instruction has U = 0, so do that. */
19923 inst.instruction = 0x0200110;
19924 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19925 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19926 inst.instruction |= LOW4 (inst.operands[1].reg);
19927 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19928 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19929 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19930 inst.instruction |= neon_quad (rs) << 6;
19931
19932 neon_dp_fixup (&inst);
037e8744
JB		 19933 }
19934 break;
5f4273c7 19935
037e8744
JB		 19936 case NS_DI: /* case 3/11. */
19937 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19938 inst.error = NULL;
19939 if (et.type == NT_float && et.size == 64)
477330fc
RM		 19940 {
19941 /* case 11 (fconstd). */
19942 ldconst = "fconstd";
19943 goto encode_fconstd;
19944 }
037e8744
JB		 19945 /* fall through. */
19946
19947 case NS_QI: /* case 2/3. */
64c350f2
AV		 19948 if (!check_simd_pred_availability (FALSE,
19949 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc 19950 return;
037e8744
JB		 19951 inst.instruction = 0x0800010;
19952 neon_move_immediate ();
88714cb8 19953 neon_dp_fixup (&inst);
5287ad62 19954 break;
5f4273c7 19955
037e8744
JB		 19956 case NS_SR: /* case 4. */
19957 {
477330fc
RM		 19958 unsigned bcdebits = 0;
19959 int logsize;
19960 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
19961 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
037e8744 19962
05ac0ffb
JB		 19963 /* .<size> is optional here, defaulting to .32. */
19964 if (inst.vectype.elems == 0
19965 && inst.operands[0].vectype.type == NT_invtype
19966 && inst.operands[1].vectype.type == NT_invtype)
19967 {
19968 inst.vectype.el[0].type = NT_untyped;
19969 inst.vectype.el[0].size = 32;
19970 inst.vectype.elems = 1;
19971 }
19972
477330fc
RM		 19973 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
19974 logsize = neon_logbits (et.size);
19975
57785aa2
AV		 19976 if (et.size != 32)
19977 {
19978 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19979 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
19980 return;
19981 }
19982 else
19983 {
19984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19985 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19986 _(BAD_FPU));
19987 }
19988
19989 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19990 {
19991 if (inst.operands[1].reg == REG_SP)
19992 as_tsktsk (MVE_BAD_SP);
19993 else if (inst.operands[1].reg == REG_PC)
19994 as_tsktsk (MVE_BAD_PC);
19995 }
19996 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
19997
477330fc 19998 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2
AV		 19999 constraint (x >= size / et.size, _("scalar index out of range"));
20000
477330fc
RM		 20001
20002 switch (et.size)
20003 {
20004 case 8: bcdebits = 0x8; break;
20005 case 16: bcdebits = 0x1; break;
20006 case 32: bcdebits = 0x0; break;
20007 default: ;
20008 }
20009
57785aa2 20010 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM		 20011
20012 inst.instruction = 0xe000b10;
20013 do_vfp_cond_or_thumb ();
20014 inst.instruction |= LOW4 (dn) << 16;
20015 inst.instruction |= HI1 (dn) << 7;
20016 inst.instruction |= inst.operands[1].reg << 12;
20017 inst.instruction |= (bcdebits & 3) << 5;
57785aa2
AV		 20018 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
20019 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB		 20020 }
20021 break;
5f4273c7 20022
037e8744 20023 case NS_DRR: /* case 5 (fmdrr). */
57785aa2
AV		 20024 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20025 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 20026 _(BAD_FPU));
b7fc2769 20027
037e8744
JB		 20028 inst.instruction = 0xc400b10;
20029 do_vfp_cond_or_thumb ();
20030 inst.instruction |= LOW4 (inst.operands[0].reg);
20031 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
20032 inst.instruction |= inst.operands[1].reg << 12;
20033 inst.instruction |= inst.operands[2].reg << 16;
20034 break;
5f4273c7 20035
037e8744
JB		 20036 case NS_RS: /* case 6. */
20037 {
477330fc
RM		 20038 unsigned logsize;
20039 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
20040 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
20041 unsigned abcdebits = 0;
037e8744 20042
05ac0ffb
JB		 20043 /* .<dt> is optional here, defaulting to .32. */
20044 if (inst.vectype.elems == 0
20045 && inst.operands[0].vectype.type == NT_invtype
20046 && inst.operands[1].vectype.type == NT_invtype)
20047 {
20048 inst.vectype.el[0].type = NT_untyped;
20049 inst.vectype.el[0].size = 32;
20050 inst.vectype.elems = 1;
20051 }
20052
91d6fa6a
NC		 20053 et = neon_check_type (2, NS_NULL,
20054 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
477330fc
RM		 20055 logsize = neon_logbits (et.size);
20056
57785aa2
AV		 20057 if (et.size != 32)
20058 {
20059 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20060 && vfp_or_neon_is_neon (NEON_CHECK_CC
20061 | NEON_CHECK_ARCH) == FAIL)
20062 return;
20063 }
20064 else
20065 {
20066 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20067 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20068 _(BAD_FPU));
20069 }
20070
20071 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20072 {
20073 if (inst.operands[0].reg == REG_SP)
20074 as_tsktsk (MVE_BAD_SP);
20075 else if (inst.operands[0].reg == REG_PC)
20076 as_tsktsk (MVE_BAD_PC);
20077 }
20078
20079 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
20080
477330fc 20081 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2 20082 constraint (x >= size / et.size, _("scalar index out of range"));
477330fc
RM		 20083
20084 switch (et.size)
20085 {
20086 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
20087 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
20088 case 32: abcdebits = 0x00; break;
20089 default: ;
20090 }
20091
57785aa2 20092 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM		 20093 inst.instruction = 0xe100b10;
20094 do_vfp_cond_or_thumb ();
20095 inst.instruction |= LOW4 (dn) << 16;
20096 inst.instruction |= HI1 (dn) << 7;
20097 inst.instruction |= inst.operands[0].reg << 12;
20098 inst.instruction |= (abcdebits & 3) << 5;
20099 inst.instruction |= (abcdebits >> 2) << 21;
57785aa2 20100 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB		 20101 }
20102 break;
5f4273c7 20103
037e8744 20104 case NS_RRD: /* case 7 (fmrrd). */
57785aa2
AV		 20105 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20106 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 20107 _(BAD_FPU));
037e8744
JB		 20108
20109 inst.instruction = 0xc500b10;
20110 do_vfp_cond_or_thumb ();
20111 inst.instruction |= inst.operands[0].reg << 12;
20112 inst.instruction |= inst.operands[1].reg << 16;
20113 inst.instruction |= LOW4 (inst.operands[2].reg);
20114 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20115 break;
5f4273c7 20116
037e8744
JB		 20117 case NS_FF: /* case 8 (fcpys). */
20118 do_vfp_nsyn_opcode ("fcpys");
20119 break;
5f4273c7 20120
9db2f6b4 20121 case NS_HI:
037e8744
JB		 20122 case NS_FI: /* case 10 (fconsts). */
20123 ldconst = "fconsts";
4ef4710f 20124 encode_fconstd:
58ed5c38
TC		 20125 if (!inst.operands[1].immisfloat)
20126 {
4ef4710f 20127 unsigned new_imm;
58ed5c38 20128 /* Immediate has to fit in 8 bits so float is enough. */
4ef4710f
NC		 20129 float imm = (float) inst.operands[1].imm;
20130 memcpy (&new_imm, &imm, sizeof (float));
20131 /* But the assembly may have been written to provide an integer
20132 bit pattern that equates to a float, so check that the
20133 conversion has worked. */
20134 if (is_quarter_float (new_imm))
20135 {
20136 if (is_quarter_float (inst.operands[1].imm))
20137 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20138
20139 inst.operands[1].imm = new_imm;
20140 inst.operands[1].immisfloat = 1;
20141 }
58ed5c38
TC		 20142 }
20143
037e8744 20144 if (is_quarter_float (inst.operands[1].imm))
477330fc
RM		 20145 {
20146 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
20147 do_vfp_nsyn_opcode (ldconst);
9db2f6b4
RL		 20148
20149 /* ARMv8.2 fp16 vmov.f16 instruction. */
20150 if (rs == NS_HI)
20151 do_scalar_fp16_v82_encode ();
477330fc 20152 }
5287ad62 20153 else
477330fc 20154 first_error (_("immediate out of range"));
037e8744 20155 break;
5f4273c7 20156
9db2f6b4 20157 case NS_RH:
037e8744
JB		 20158 case NS_RF: /* case 12 (fmrs). */
20159 do_vfp_nsyn_opcode ("fmrs");
9db2f6b4
RL		 20160 /* ARMv8.2 fp16 vmov.f16 instruction. */
20161 if (rs == NS_RH)
20162 do_scalar_fp16_v82_encode ();
037e8744 20163 break;
5f4273c7 20164
9db2f6b4 20165 case NS_HR:
037e8744
JB		 20166 case NS_FR: /* case 13 (fmsr). */
20167 do_vfp_nsyn_opcode ("fmsr");
9db2f6b4
RL		 20168 /* ARMv8.2 fp16 vmov.f16 instruction. */
20169 if (rs == NS_HR)
20170 do_scalar_fp16_v82_encode ();
037e8744 20171 break;
5f4273c7 20172
57785aa2
AV		 20173 case NS_RRSS:
20174 do_mve_mov (0);
20175 break;
20176 case NS_SSRR:
20177 do_mve_mov (1);
20178 break;
20179
037e8744
JB		 20180 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20181 (one of which is a list), but we have parsed four. Do some fiddling to
20182 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20183 expect. */
20184 case NS_RRFF: /* case 14 (fmrrs). */
57785aa2
AV		 20185 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20186 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20187 _(BAD_FPU));
037e8744 20188 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
477330fc 20189 _("VFP registers must be adjacent"));
037e8744
JB		 20190 inst.operands[2].imm = 2;
20191 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20192 do_vfp_nsyn_opcode ("fmrrs");
20193 break;
5f4273c7 20194
037e8744 20195 case NS_FFRR: /* case 15 (fmsrr). */
57785aa2
AV		 20196 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20197 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20198 _(BAD_FPU));
037e8744 20199 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
477330fc 20200 _("VFP registers must be adjacent"));
037e8744
JB		 20201 inst.operands[1] = inst.operands[2];
20202 inst.operands[2] = inst.operands[3];
20203 inst.operands[0].imm = 2;
20204 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20205 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 20206 break;
5f4273c7 20207
4c261dff
NC		 20208 case NS_NULL:
20209 /* neon_select_shape has determined that the instruction
20210 shape is wrong and has already set the error message. */
20211 break;
20212
5287ad62
JB		 20213 default:
20214 abort ();
20215 }
20216}
20217
57785aa2
AV		 20218static void
20219do_mve_movl (void)
20220{
20221 if (!(inst.operands[0].present && inst.operands[0].isquad
20222 && inst.operands[1].present && inst.operands[1].isquad
20223 && !inst.operands[2].present))
20224 {
20225 inst.instruction = 0;
20226 inst.cond = 0xb;
20227 if (thumb_mode)
20228 set_pred_insn_type (INSIDE_IT_INSN);
20229 do_neon_mov ();
20230 return;
20231 }
20232
20233 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20234 return;
20235
20236 if (inst.cond != COND_ALWAYS)
20237 inst.pred_insn_type = INSIDE_VPT_INSN;
20238
20239 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
20240 | N_S16 | N_U16 | N_KEY);
20241
20242 inst.instruction |= (et.type == NT_unsigned) << 28;
20243 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20244 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20245 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20246 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20247 inst.instruction |= LOW4 (inst.operands[1].reg);
20248 inst.is_neon = 1;
20249}
20250
5287ad62
JB		 20251static void
20252do_neon_rshift_round_imm (void)
20253{
64c350f2 20254 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 20255 return;
20256
20257 enum neon_shape rs;
20258 struct neon_type_el et;
20259
20260 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20261 {
20262 rs = neon_select_shape (NS_QQI, NS_NULL);
20263 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
20264 }
20265 else
20266 {
20267 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
20268 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
20269 }
5287ad62
JB		 20270 int imm = inst.operands[2].imm;
20271
20272 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20273 if (imm == 0)
20274 {
20275 inst.operands[2].present = 0;
20276 do_neon_mov ();
20277 return;
20278 }
20279
20280 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 20281 _("immediate out of range for shift"));
037e8744 20282 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 20283 et.size - imm);
5287ad62
JB		 20284}
20285
9db2f6b4
RL		 20286static void
20287do_neon_movhf (void)
20288{
20289 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
20290 constraint (rs != NS_HH, _("invalid suffix"));
20291
7bdf778b
ASDV		 20292 if (inst.cond != COND_ALWAYS)
20293 {
20294 if (thumb_mode)
20295 {
20296 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20297 " the behaviour is UNPREDICTABLE"));
20298 }
20299 else
20300 {
20301 inst.error = BAD_COND;
20302 return;
20303 }
20304 }
20305
9db2f6b4
RL		 20306 do_vfp_sp_monadic ();
20307
20308 inst.is_neon = 1;
20309 inst.instruction |= 0xf0000000;
20310}
20311
5287ad62
JB		 20312static void
20313do_neon_movl (void)
20314{
20315 struct neon_type_el et = neon_check_type (2, NS_QD,
20316 N_EQK | N_DBL, N_SU_32 | N_KEY);
20317 unsigned sizebits = et.size >> 3;
20318 inst.instruction |= sizebits << 19;
20319 neon_two_same (0, et.type == NT_unsigned, -1);
20320}
20321
20322static void
20323do_neon_trn (void)
20324{
037e8744 20325 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20326 struct neon_type_el et = neon_check_type (2, rs,
20327 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 20328 NEON_ENCODE (INTEGER, inst);
037e8744 20329 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20330}
20331
20332static void
20333do_neon_zip_uzp (void)
20334{
037e8744 20335 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20336 struct neon_type_el et = neon_check_type (2, rs,
20337 N_EQK, N_8 | N_16 | N_32 | N_KEY);
20338 if (rs == NS_DD && et.size == 32)
20339 {
20340 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20341 inst.instruction = N_MNEM_vtrn;
20342 do_neon_trn ();
20343 return;
20344 }
037e8744 20345 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20346}
20347
20348static void
20349do_neon_sat_abs_neg (void)
20350{
64c350f2 20351 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV		 20352 return;
20353
20354 enum neon_shape rs;
20355 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20356 rs = neon_select_shape (NS_QQ, NS_NULL);
20357 else
20358 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20359 struct neon_type_el et = neon_check_type (2, rs,
20360 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20361 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20362}
20363
20364static void
20365do_neon_pair_long (void)
20366{
037e8744 20367 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20368 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
20369 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20370 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 20371 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20372}
20373
20374static void
20375do_neon_recip_est (void)
20376{
037e8744 20377 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62 20378 struct neon_type_el et = neon_check_type (2, rs,
cc933301 20379 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
5287ad62 20380 inst.instruction |= (et.type == NT_float) << 8;
037e8744 20381 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20382}
20383
20384static void
20385do_neon_cls (void)
20386{
64c350f2 20387 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV		 20388 return;
20389
20390 enum neon_shape rs;
20391 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20392 rs = neon_select_shape (NS_QQ, NS_NULL);
20393 else
20394 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20395
5287ad62
JB		 20396 struct neon_type_el et = neon_check_type (2, rs,
20397 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20398 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20399}
20400
20401static void
20402do_neon_clz (void)
20403{
64c350f2 20404 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV		 20405 return;
20406
20407 enum neon_shape rs;
20408 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20409 rs = neon_select_shape (NS_QQ, NS_NULL);
20410 else
20411 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20412
5287ad62
JB		 20413 struct neon_type_el et = neon_check_type (2, rs,
20414 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 20415 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20416}
20417
20418static void
20419do_neon_cnt (void)
20420{
037e8744 20421 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20422 struct neon_type_el et = neon_check_type (2, rs,
20423 N_EQK | N_INT, N_8 | N_KEY);
037e8744 20424 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20425}
20426
20427static void
20428do_neon_swp (void)
20429{
037e8744
JB		 20430 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20431 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB		 20432}
20433
20434static void
20435do_neon_tbl_tbx (void)
20436{
20437 unsigned listlenbits;
dcbf9037 20438 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 20439
5287ad62
JB		 20440 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20441 {
dcbf9037 20442 first_error (_("bad list length for table lookup"));
5287ad62
JB		 20443 return;
20444 }
5f4273c7 20445
5287ad62
JB		 20446 listlenbits = inst.operands[1].imm - 1;
20447 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20448 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20449 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20450 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20451 inst.instruction |= LOW4 (inst.operands[2].reg);
20452 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20453 inst.instruction |= listlenbits << 8;
5f4273c7 20454
88714cb8 20455 neon_dp_fixup (&inst);
5287ad62
JB		 20456}
20457
20458static void
20459do_neon_ldm_stm (void)
20460{
20461 /* P, U and L bits are part of bitmask. */
20462 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20463 unsigned offsetbits = inst.operands[1].imm * 2;
20464
037e8744
JB		 20465 if (inst.operands[1].issingle)
20466 {
20467 do_vfp_nsyn_ldm_stm (is_dbmode);
20468 return;
20469 }
20470
5287ad62 20471 constraint (is_dbmode && !inst.operands[0].writeback,
477330fc 20472 _("writeback (!) must be used for VLDMDB and VSTMDB"));
5287ad62
JB		 20473
20474 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
477330fc
RM		 20475 _("register list must contain at least 1 and at most 16 "
20476 "registers"));
5287ad62
JB		 20477
20478 inst.instruction |= inst.operands[0].reg << 16;
20479 inst.instruction |= inst.operands[0].writeback << 21;
20480 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20481 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20482
20483 inst.instruction |= offsetbits;
5f4273c7 20484
037e8744 20485 do_vfp_cond_or_thumb ();
5287ad62
JB		 20486}
20487
20488static void
20489do_neon_ldr_str (void)
20490{
5287ad62 20491 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 20492
6844b2c2
MGD		 20493 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20494 And is UNPREDICTABLE in thumb mode. */
fa94de6b 20495 if (!is_ldr
6844b2c2 20496 && inst.operands[1].reg == REG_PC
ba86b375 20497 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
6844b2c2 20498 {
94dcf8bf 20499 if (thumb_mode)
6844b2c2 20500 inst.error = _("Use of PC here is UNPREDICTABLE");
94dcf8bf 20501 else if (warn_on_deprecated)
5c3696f8 20502 as_tsktsk (_("Use of PC here is deprecated"));
6844b2c2
MGD		 20503 }
20504
037e8744
JB		 20505 if (inst.operands[0].issingle)
20506 {
cd2f129f 20507 if (is_ldr)
477330fc 20508 do_vfp_nsyn_opcode ("flds");
cd2f129f 20509 else
477330fc 20510 do_vfp_nsyn_opcode ("fsts");
9db2f6b4
RL		 20511
20512 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20513 if (inst.vectype.el[0].size == 16)
20514 do_scalar_fp16_v82_encode ();
5287ad62
JB		 20515 }
20516 else
5287ad62 20517 {
cd2f129f 20518 if (is_ldr)
477330fc 20519 do_vfp_nsyn_opcode ("fldd");
5287ad62 20520 else
477330fc 20521 do_vfp_nsyn_opcode ("fstd");
5287ad62 20522 }
5287ad62
JB		 20523}
20524
32c36c3c
AV		 20525static void
20526do_t_vldr_vstr_sysreg (void)
20527{
20528 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
20529 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20530
20531 /* Use of PC is UNPREDICTABLE. */
20532 if (inst.operands[1].reg == REG_PC)
20533 inst.error = _("Use of PC here is UNPREDICTABLE");
20534
20535 if (inst.operands[1].immisreg)
20536 inst.error = _("instruction does not accept register index");
20537
20538 if (!inst.operands[1].isreg)
20539 inst.error = _("instruction does not accept PC-relative addressing");
20540
20541 if (abs (inst.operands[1].imm) >= (1 << 7))
20542 inst.error = _("immediate value out of range");
20543
20544 inst.instruction = 0xec000f80;
20545 if (is_vldr)
20546 inst.instruction |= 1 << sysreg_vldr_bitno;
20547 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
20548 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20549 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20550}
20551
20552static void
20553do_vldr_vstr (void)
20554{
20555 bfd_boolean sysreg_op = !inst.operands[0].isreg;
20556
20557 /* VLDR/VSTR (System Register). */
20558 if (sysreg_op)
20559 {
20560 if (!mark_feature_used (&arm_ext_v8_1m_main))
20561 as_bad (_("Instruction not permitted on this architecture"));
20562
20563 do_t_vldr_vstr_sysreg ();
20564 }
20565 /* VLDR/VSTR. */
20566 else
20567 {
20568 if (!mark_feature_used (&fpu_vfp_ext_v1xd))
20569 as_bad (_("Instruction not permitted on this architecture"));
20570 do_neon_ldr_str ();
20571 }
20572}
20573
5287ad62
JB		 20574/* "interleave" version also handles non-interleaving register VLD1/VST1
20575 instructions. */
20576
20577static void
20578do_neon_ld_st_interleave (void)
20579{
037e8744 20580 struct neon_type_el et = neon_check_type (1, NS_NULL,
477330fc 20581 N_8 | N_16 | N_32 | N_64);
5287ad62
JB		 20582 unsigned alignbits = 0;
20583 unsigned idx;
20584 /* The bits in this table go:
20585 0: register stride of one (0) or two (1)
20586 1,2: register list length, minus one (1, 2, 3, 4).
20587 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20588 We use -1 for invalid entries. */
20589 const int typetable[] =
20590 {
20591 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20592 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20593 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20594 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20595 };
20596 int typebits;
20597
dcbf9037
JB		 20598 if (et.type == NT_invtype)
20599 return;
20600
5287ad62
JB		 20601 if (inst.operands[1].immisalign)
20602 switch (inst.operands[1].imm >> 8)
20603 {
20604 case 64: alignbits = 1; break;
20605 case 128:
477330fc 20606 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
e23c0ad8 20607 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
477330fc
RM		 20608 goto bad_alignment;
20609 alignbits = 2;
20610 break;
5287ad62 20611 case 256:
477330fc
RM		 20612 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20613 goto bad_alignment;
20614 alignbits = 3;
20615 break;
5287ad62
JB		 20616 default:
20617 bad_alignment:
477330fc
RM		 20618 first_error (_("bad alignment"));
20619 return;
5287ad62
JB		 20620 }
20621
20622 inst.instruction |= alignbits << 4;
20623 inst.instruction |= neon_logbits (et.size) << 6;
20624
20625 /* Bits [4:6] of the immediate in a list specifier encode register stride
20626 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20627 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20628 up the right value for "type" in a table based on this value and the given
20629 list style, then stick it back. */
20630 idx = ((inst.operands[0].imm >> 4) & 7)
477330fc 20631 | (((inst.instruction >> 8) & 3) << 3);
5287ad62
JB		 20632
20633 typebits = typetable[idx];
5f4273c7 20634
5287ad62 20635 constraint (typebits == -1, _("bad list type for instruction"));
1d50d57c 20636 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
35c228db 20637 BAD_EL_TYPE);
5287ad62
JB		 20638
20639 inst.instruction &= ~0xf00;
20640 inst.instruction |= typebits << 8;
20641}
20642
20643/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20644 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20645 otherwise. The variable arguments are a list of pairs of legal (size, align)
20646 values, terminated with -1. */
20647
20648static int
aa8a0863 20649neon_alignment_bit (int size, int align, int *do_alignment, ...)
5287ad62
JB		 20650{
20651 va_list ap;
20652 int result = FAIL, thissize, thisalign;
5f4273c7 20653
5287ad62
JB		 20654 if (!inst.operands[1].immisalign)
20655 {
aa8a0863 20656 *do_alignment = 0;
5287ad62
JB		 20657 return SUCCESS;
20658 }
5f4273c7 20659
aa8a0863 20660 va_start (ap, do_alignment);
5287ad62
JB		 20661
20662 do
20663 {
20664 thissize = va_arg (ap, int);
20665 if (thissize == -1)
477330fc 20666 break;
5287ad62
JB		 20667 thisalign = va_arg (ap, int);
20668
20669 if (size == thissize && align == thisalign)
477330fc 20670 result = SUCCESS;
5287ad62
JB		 20671 }
20672 while (result != SUCCESS);
20673
20674 va_end (ap);
20675
20676 if (result == SUCCESS)
aa8a0863 20677 *do_alignment = 1;
5287ad62 20678 else
dcbf9037 20679 first_error (_("unsupported alignment for instruction"));
5f4273c7 20680
5287ad62
JB		 20681 return result;
20682}
20683
20684static void
20685do_neon_ld_st_lane (void)
20686{
037e8744 20687 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 20688 int align_good, do_alignment = 0;
5287ad62
JB		 20689 int logsize = neon_logbits (et.size);
20690 int align = inst.operands[1].imm >> 8;
20691 int n = (inst.instruction >> 8) & 3;
20692 int max_el = 64 / et.size;
5f4273c7 20693
dcbf9037
JB		 20694 if (et.type == NT_invtype)
20695 return;
5f4273c7 20696
5287ad62 20697 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
477330fc 20698 _("bad list length"));
5287ad62 20699 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
477330fc 20700 _("scalar index out of range"));
5287ad62 20701 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
477330fc
RM		 20702 && et.size == 8,
20703 _("stride of 2 unavailable when element size is 8"));
5f4273c7 20704
5287ad62
JB		 20705 switch (n)
20706 {
20707 case 0: /* VLD1 / VST1. */
aa8a0863 20708 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
477330fc 20709 32, 32, -1);
5287ad62 20710 if (align_good == FAIL)
477330fc 20711 return;
aa8a0863 20712 if (do_alignment)
477330fc
RM		 20713 {
20714 unsigned alignbits = 0;
20715 switch (et.size)
20716 {
20717 case 16: alignbits = 0x1; break;
20718 case 32: alignbits = 0x3; break;
20719 default: ;
20720 }
20721 inst.instruction |= alignbits << 4;
20722 }
5287ad62
JB		 20723 break;
20724
20725 case 1: /* VLD2 / VST2. */
aa8a0863
TS		 20726 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
20727 16, 32, 32, 64, -1);
5287ad62 20728 if (align_good == FAIL)
477330fc 20729 return;
aa8a0863 20730 if (do_alignment)
477330fc 20731 inst.instruction |= 1 << 4;
5287ad62
JB		 20732 break;
20733
20734 case 2: /* VLD3 / VST3. */
20735 constraint (inst.operands[1].immisalign,
477330fc 20736 _("can't use alignment with this instruction"));
5287ad62
JB		 20737 break;
20738
20739 case 3: /* VLD4 / VST4. */
aa8a0863 20740 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc 20741 16, 64, 32, 64, 32, 128, -1);
5287ad62 20742 if (align_good == FAIL)
477330fc 20743 return;
aa8a0863 20744 if (do_alignment)
477330fc
RM		 20745 {
20746 unsigned alignbits = 0;
20747 switch (et.size)
20748 {
20749 case 8: alignbits = 0x1; break;
20750 case 16: alignbits = 0x1; break;
20751 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
20752 default: ;
20753 }
20754 inst.instruction |= alignbits << 4;
20755 }
5287ad62
JB		 20756 break;
20757
20758 default: ;
20759 }
20760
20761 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20762 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20763 inst.instruction |= 1 << (4 + logsize);
5f4273c7 20764
5287ad62
JB		 20765 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
20766 inst.instruction |= logsize << 10;
20767}
20768
20769/* Encode single n-element structure to all lanes VLD<n> instructions. */
20770
20771static void
20772do_neon_ld_dup (void)
20773{
037e8744 20774 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 20775 int align_good, do_alignment = 0;
5287ad62 20776
dcbf9037
JB		 20777 if (et.type == NT_invtype)
20778 return;
20779
5287ad62
JB		 20780 switch ((inst.instruction >> 8) & 3)
20781 {
20782 case 0: /* VLD1. */
9c2799c2 20783 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62 20784 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863 20785 &do_alignment, 16, 16, 32, 32, -1);
5287ad62 20786 if (align_good == FAIL)
477330fc 20787 return;
5287ad62 20788 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
477330fc
RM		 20789 {
20790 case 1: break;
20791 case 2: inst.instruction |= 1 << 5; break;
20792 default: first_error (_("bad list length")); return;
20793 }
5287ad62
JB		 20794 inst.instruction |= neon_logbits (et.size) << 6;
20795 break;
20796
20797 case 1: /* VLD2. */
20798 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863
TS		 20799 &do_alignment, 8, 16, 16, 32, 32, 64,
20800 -1);
5287ad62 20801 if (align_good == FAIL)
477330fc 20802 return;
5287ad62 20803 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
477330fc 20804 _("bad list length"));
5287ad62 20805 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 20806 inst.instruction |= 1 << 5;
5287ad62
JB		 20807 inst.instruction |= neon_logbits (et.size) << 6;
20808 break;
20809
20810 case 2: /* VLD3. */
20811 constraint (inst.operands[1].immisalign,
477330fc 20812 _("can't use alignment with this instruction"));
5287ad62 20813 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
477330fc 20814 _("bad list length"));
5287ad62 20815 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 20816 inst.instruction |= 1 << 5;
5287ad62
JB		 20817 inst.instruction |= neon_logbits (et.size) << 6;
20818 break;
20819
20820 case 3: /* VLD4. */
20821 {
477330fc 20822 int align = inst.operands[1].imm >> 8;
aa8a0863 20823 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc
RM		 20824 16, 64, 32, 64, 32, 128, -1);
20825 if (align_good == FAIL)
20826 return;
20827 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
20828 _("bad list length"));
20829 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20830 inst.instruction |= 1 << 5;
20831 if (et.size == 32 && align == 128)
20832 inst.instruction |= 0x3 << 6;
20833 else
20834 inst.instruction |= neon_logbits (et.size) << 6;
5287ad62
JB		 20835 }
20836 break;
20837
20838 default: ;
20839 }
20840
aa8a0863 20841 inst.instruction |= do_alignment << 4;
5287ad62
JB		 20842}
20843
20844/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20845 apart from bits [11:4]. */
20846
20847static void
20848do_neon_ldx_stx (void)
20849{
b1a769ed
DG		 20850 if (inst.operands[1].isreg)
20851 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
20852
5287ad62
JB		 20853 switch (NEON_LANE (inst.operands[0].imm))
20854 {
20855 case NEON_INTERLEAVE_LANES:
88714cb8 20856 NEON_ENCODE (INTERLV, inst);
5287ad62
JB		 20857 do_neon_ld_st_interleave ();
20858 break;
5f4273c7 20859
5287ad62 20860 case NEON_ALL_LANES:
88714cb8 20861 NEON_ENCODE (DUP, inst);
2d51fb74
JB		 20862 if (inst.instruction == N_INV)
20863 {
20864 first_error ("only loads support such operands");
20865 break;
20866 }
5287ad62
JB		 20867 do_neon_ld_dup ();
20868 break;
5f4273c7 20869
5287ad62 20870 default:
88714cb8 20871 NEON_ENCODE (LANE, inst);
5287ad62
JB		 20872 do_neon_ld_st_lane ();
20873 }
20874
20875 /* L bit comes from bit mask. */
20876 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20877 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20878 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 20879
5287ad62
JB		 20880 if (inst.operands[1].postind)
20881 {
20882 int postreg = inst.operands[1].imm & 0xf;
20883 constraint (!inst.operands[1].immisreg,
477330fc 20884 _("post-index must be a register"));
5287ad62 20885 constraint (postreg == 0xd || postreg == 0xf,
477330fc 20886 _("bad register for post-index"));
5287ad62
JB		 20887 inst.instruction |= postreg;
20888 }
4f2374c7 20889 else
5287ad62 20890 {
4f2374c7 20891 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
e2b0ab59
AV		 20892 constraint (inst.relocs[0].exp.X_op != O_constant
20893 || inst.relocs[0].exp.X_add_number != 0,
4f2374c7
WN		 20894 BAD_ADDR_MODE);
20895
20896 if (inst.operands[1].writeback)
20897 {
20898 inst.instruction |= 0xd;
20899 }
20900 else
20901 inst.instruction |= 0xf;
5287ad62 20902 }
5f4273c7 20903
5287ad62
JB		 20904 if (thumb_mode)
20905 inst.instruction |= 0xf9000000;
20906 else
20907 inst.instruction |= 0xf4000000;
20908}
33399f07
MGD		 20909
20910/* FP v8. */
20911static void
20912do_vfp_nsyn_fpv8 (enum neon_shape rs)
20913{
a715796b
TG		 20914 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20915 D register operands. */
20916 if (neon_shape_class[rs] == SC_DOUBLE)
20917 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20918 _(BAD_FPU));
20919
33399f07
MGD		 20920 NEON_ENCODE (FPV8, inst);
20921
9db2f6b4
RL		 20922 if (rs == NS_FFF || rs == NS_HHH)
20923 {
20924 do_vfp_sp_dyadic ();
20925
20926 /* ARMv8.2 fp16 instruction. */
20927 if (rs == NS_HHH)
20928 do_scalar_fp16_v82_encode ();
20929 }
33399f07
MGD		 20930 else
20931 do_vfp_dp_rd_rn_rm ();
20932
20933 if (rs == NS_DDD)
20934 inst.instruction |= 0x100;
20935
20936 inst.instruction |= 0xf0000000;
20937}
20938
20939static void
20940do_vsel (void)
20941{
5ee91343 20942 set_pred_insn_type (OUTSIDE_PRED_INSN);
33399f07
MGD		 20943
20944 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
20945 first_error (_("invalid instruction shape"));
20946}
20947
73924fbc
MGD		 20948static void
20949do_vmaxnm (void)
20950{
935295b5
AV		 20951 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20952 set_pred_insn_type (OUTSIDE_PRED_INSN);
73924fbc
MGD		 20953
20954 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
20955 return;
20956
64c350f2 20957 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8))
73924fbc
MGD		 20958 return;
20959
cc933301 20960 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
73924fbc
MGD		 20961}
20962
30bdf752
MGD		 20963static void
20964do_vrint_1 (enum neon_cvt_mode mode)
20965{
9db2f6b4 20966 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
30bdf752
MGD		 20967 struct neon_type_el et;
20968
20969 if (rs == NS_NULL)
20970 return;
20971
a715796b
TG		 20972 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20973 D register operands. */
20974 if (neon_shape_class[rs] == SC_DOUBLE)
20975 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20976 _(BAD_FPU));
20977
9db2f6b4
RL		 20978 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
20979 | N_VFP);
30bdf752
MGD		 20980 if (et.type != NT_invtype)
20981 {
20982 /* VFP encodings. */
20983 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
20984 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
5ee91343 20985 set_pred_insn_type (OUTSIDE_PRED_INSN);
30bdf752
MGD		 20986
20987 NEON_ENCODE (FPV8, inst);
9db2f6b4 20988 if (rs == NS_FF || rs == NS_HH)
30bdf752
MGD		 20989 do_vfp_sp_monadic ();
20990 else
20991 do_vfp_dp_rd_rm ();
20992
20993 switch (mode)
20994 {
20995 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
20996 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
20997 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
20998 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
20999 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
21000 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
21001 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
21002 default: abort ();
21003 }
21004
21005 inst.instruction |= (rs == NS_DD) << 8;
21006 do_vfp_cond_or_thumb ();
9db2f6b4
RL		 21007
21008 /* ARMv8.2 fp16 vrint instruction. */
21009 if (rs == NS_HH)
21010 do_scalar_fp16_v82_encode ();
30bdf752
MGD		 21011 }
21012 else
21013 {
21014 /* Neon encodings (or something broken...). */
21015 inst.error = NULL;
cc933301 21016 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
30bdf752
MGD		 21017
21018 if (et.type == NT_invtype)
21019 return;
21020
64c350f2
AV		 21021 if (!check_simd_pred_availability (TRUE,
21022 NEON_CHECK_CC | NEON_CHECK_ARCH8))
30bdf752
MGD		 21023 return;
21024
a710b305
AV		 21025 NEON_ENCODE (FLOAT, inst);
21026
30bdf752
MGD		 21027 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21028 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21029 inst.instruction |= LOW4 (inst.operands[1].reg);
21030 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21031 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 21032 /* Mask off the original size bits and reencode them. */
21033 inst.instruction = ((inst.instruction & 0xfff3ffff)
21034 | neon_logbits (et.size) << 18);
21035
30bdf752
MGD		 21036 switch (mode)
21037 {
21038 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
21039 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
21040 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
21041 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
21042 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
21043 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
21044 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
21045 default: abort ();
21046 }
21047
21048 if (thumb_mode)
21049 inst.instruction |= 0xfc000000;
21050 else
21051 inst.instruction |= 0xf0000000;
21052 }
21053}
21054
21055static void
21056do_vrintx (void)
21057{
21058 do_vrint_1 (neon_cvt_mode_x);
21059}
21060
21061static void
21062do_vrintz (void)
21063{
21064 do_vrint_1 (neon_cvt_mode_z);
21065}
21066
21067static void
21068do_vrintr (void)
21069{
21070 do_vrint_1 (neon_cvt_mode_r);
21071}
21072
21073static void
21074do_vrinta (void)
21075{
21076 do_vrint_1 (neon_cvt_mode_a);
21077}
21078
21079static void
21080do_vrintn (void)
21081{
21082 do_vrint_1 (neon_cvt_mode_n);
21083}
21084
21085static void
21086do_vrintp (void)
21087{
21088 do_vrint_1 (neon_cvt_mode_p);
21089}
21090
21091static void
21092do_vrintm (void)
21093{
21094 do_vrint_1 (neon_cvt_mode_m);
21095}
21096
c28eeff2
SN		 21097static unsigned
21098neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
21099{
21100 unsigned regno = NEON_SCALAR_REG (opnd);
21101 unsigned elno = NEON_SCALAR_INDEX (opnd);
21102
21103 if (elsize == 16 && elno < 2 && regno < 16)
21104 return regno | (elno << 4);
21105 else if (elsize == 32 && elno == 0)
21106 return regno;
21107
21108 first_error (_("scalar out of range"));
21109 return 0;
21110}
21111
21112static void
21113do_vcmla (void)
21114{
5d281bf0
AV		 21115 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
21116 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21117 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV		 21118 constraint (inst.relocs[0].exp.X_op != O_constant,
21119 _("expression too complex"));
21120 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2
SN		 21121 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
21122 _("immediate out of range"));
21123 rot /= 90;
5d281bf0 21124
64c350f2
AV		 21125 if (!check_simd_pred_availability (TRUE,
21126 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV		 21127 return;
21128
c28eeff2
SN		 21129 if (inst.operands[2].isscalar)
21130 {
5d281bf0
AV		 21131 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21132 first_error (_("invalid instruction shape"));
c28eeff2
SN		 21133 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
21134 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21135 N_KEY | N_F16 | N_F32).size;
21136 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
21137 inst.is_neon = 1;
21138 inst.instruction = 0xfe000800;
21139 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21140 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21141 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21142 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21143 inst.instruction |= LOW4 (m);
21144 inst.instruction |= HI1 (m) << 5;
21145 inst.instruction |= neon_quad (rs) << 6;
21146 inst.instruction |= rot << 20;
21147 inst.instruction |= (size == 32) << 23;
21148 }
21149 else
21150 {
5d281bf0
AV		 21151 enum neon_shape rs;
21152 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21153 rs = neon_select_shape (NS_QQQI, NS_NULL);
21154 else
21155 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21156
c28eeff2
SN		 21157 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21158 N_KEY | N_F16 | N_F32).size;
5d281bf0
AV		 21159 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
21160 && (inst.operands[0].reg == inst.operands[1].reg
21161 || inst.operands[0].reg == inst.operands[2].reg))
21162 as_tsktsk (BAD_MVE_SRCDEST);
21163
c28eeff2
SN		 21164 neon_three_same (neon_quad (rs), 0, -1);
21165 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21166 inst.instruction |= 0xfc200800;
21167 inst.instruction |= rot << 23;
21168 inst.instruction |= (size == 32) << 20;
21169 }
21170}
21171
21172static void
21173do_vcadd (void)
21174{
5d281bf0
AV		 21175 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
21176 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21177 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV		 21178 constraint (inst.relocs[0].exp.X_op != O_constant,
21179 _("expression too complex"));
5d281bf0 21180
e2b0ab59 21181 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2 21182 constraint (rot != 90 && rot != 270, _("immediate out of range"));
5d281bf0
AV		 21183 enum neon_shape rs;
21184 struct neon_type_el et;
21185 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21186 {
21187 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21188 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
21189 }
21190 else
21191 {
21192 rs = neon_select_shape (NS_QQQI, NS_NULL);
21193 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
21194 | N_I16 | N_I32);
21195 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
21196 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21197 "operand makes instruction UNPREDICTABLE"));
21198 }
21199
21200 if (et.type == NT_invtype)
21201 return;
21202
64c350f2
AV		 21203 if (!check_simd_pred_availability (et.type == NT_float,
21204 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV		 21205 return;
21206
21207 if (et.type == NT_float)
21208 {
21209 neon_three_same (neon_quad (rs), 0, -1);
21210 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21211 inst.instruction |= 0xfc800800;
21212 inst.instruction |= (rot == 270) << 24;
21213 inst.instruction |= (et.size == 32) << 20;
21214 }
21215 else
21216 {
21217 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
21218 inst.instruction = 0xfe000f00;
21219 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21220 inst.instruction |= neon_logbits (et.size) << 20;
21221 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21222 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21223 inst.instruction |= (rot == 270) << 12;
21224 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21225 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21226 inst.instruction |= LOW4 (inst.operands[2].reg);
21227 inst.is_neon = 1;
21228 }
c28eeff2
SN		 21229}
21230
c604a79a
JW		 21231/* Dot Product instructions encoding support. */
21232
21233static void
21234do_neon_dotproduct (int unsigned_p)
21235{
21236 enum neon_shape rs;
21237 unsigned scalar_oprd2 = 0;
21238 int high8;
21239
21240 if (inst.cond != COND_ALWAYS)
21241 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21242 "is UNPREDICTABLE"));
21243
21244 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
21245 _(BAD_FPU));
21246
21247 /* Dot Product instructions are in three-same D/Q register format or the third
21248 operand can be a scalar index register. */
21249 if (inst.operands[2].isscalar)
21250 {
21251 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21252 high8 = 0xfe000000;
21253 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21254 }
21255 else
21256 {
21257 high8 = 0xfc000000;
21258 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21259 }
21260
21261 if (unsigned_p)
21262 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
21263 else
21264 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
21265
21266 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21267 Product instruction, so we pass 0 as the "ubit" parameter. And the
21268 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21269 neon_three_same (neon_quad (rs), 0, 32);
21270
21271 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21272 different NEON three-same encoding. */
21273 inst.instruction &= 0x00ffffff;
21274 inst.instruction |= high8;
21275 /* Encode 'U' bit which indicates signedness. */
21276 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21277 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21278 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21279 the instruction encoding. */
21280 if (inst.operands[2].isscalar)
21281 {
21282 inst.instruction &= 0xffffffd0;
21283 inst.instruction |= LOW4 (scalar_oprd2);
21284 inst.instruction |= HI1 (scalar_oprd2) << 5;
21285 }
21286}
21287
21288/* Dot Product instructions for signed integer. */
21289
21290static void
21291do_neon_dotproduct_s (void)
21292{
21293 return do_neon_dotproduct (0);
21294}
21295
21296/* Dot Product instructions for unsigned integer. */
21297
21298static void
21299do_neon_dotproduct_u (void)
21300{
21301 return do_neon_dotproduct (1);
21302}
21303
91ff7894
MGD		 21304/* Crypto v1 instructions. */
21305static void
21306do_crypto_2op_1 (unsigned elttype, int op)
21307{
5ee91343 21308 set_pred_insn_type (OUTSIDE_PRED_INSN);
91ff7894
MGD		 21309
21310 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
21311 == NT_invtype)
21312 return;
21313
21314 inst.error = NULL;
21315
21316 NEON_ENCODE (INTEGER, inst);
21317 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21318 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21319 inst.instruction |= LOW4 (inst.operands[1].reg);
21320 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21321 if (op != -1)
21322 inst.instruction |= op << 6;
21323
21324 if (thumb_mode)
21325 inst.instruction |= 0xfc000000;
21326 else
21327 inst.instruction |= 0xf0000000;
21328}
21329
48adcd8e
MGD		 21330static void
21331do_crypto_3op_1 (int u, int op)
21332{
5ee91343 21333 set_pred_insn_type (OUTSIDE_PRED_INSN);
48adcd8e
MGD		 21334
21335 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
21336 N_32 | N_UNT | N_KEY).type == NT_invtype)
21337 return;
21338
21339 inst.error = NULL;
21340
21341 NEON_ENCODE (INTEGER, inst);
21342 neon_three_same (1, u, 8 << op);
21343}
21344
91ff7894
MGD		 21345static void
21346do_aese (void)
21347{
21348 do_crypto_2op_1 (N_8, 0);
21349}
21350
21351static void
21352do_aesd (void)
21353{
21354 do_crypto_2op_1 (N_8, 1);
21355}
21356
21357static void
21358do_aesmc (void)
21359{
21360 do_crypto_2op_1 (N_8, 2);
21361}
21362
21363static void
21364do_aesimc (void)
21365{
21366 do_crypto_2op_1 (N_8, 3);
21367}
21368
48adcd8e
MGD		 21369static void
21370do_sha1c (void)
21371{
21372 do_crypto_3op_1 (0, 0);
21373}
21374
21375static void
21376do_sha1p (void)
21377{
21378 do_crypto_3op_1 (0, 1);
21379}
21380
21381static void
21382do_sha1m (void)
21383{
21384 do_crypto_3op_1 (0, 2);
21385}
21386
21387static void
21388do_sha1su0 (void)
21389{
21390 do_crypto_3op_1 (0, 3);
21391}
91ff7894 21392
48adcd8e
MGD		 21393static void
21394do_sha256h (void)
21395{
21396 do_crypto_3op_1 (1, 0);
21397}
21398
21399static void
21400do_sha256h2 (void)
21401{
21402 do_crypto_3op_1 (1, 1);
21403}
21404
21405static void
21406do_sha256su1 (void)
21407{
21408 do_crypto_3op_1 (1, 2);
21409}
3c9017d2
MGD		 21410
21411static void
21412do_sha1h (void)
21413{
21414 do_crypto_2op_1 (N_32, -1);
21415}
21416
21417static void
21418do_sha1su1 (void)
21419{
21420 do_crypto_2op_1 (N_32, 0);
21421}
21422
21423static void
21424do_sha256su0 (void)
21425{
21426 do_crypto_2op_1 (N_32, 1);
21427}
dd5181d5
KT		 21428
21429static void
21430do_crc32_1 (unsigned int poly, unsigned int sz)
21431{
21432 unsigned int Rd = inst.operands[0].reg;
21433 unsigned int Rn = inst.operands[1].reg;
21434 unsigned int Rm = inst.operands[2].reg;
21435
5ee91343 21436 set_pred_insn_type (OUTSIDE_PRED_INSN);
dd5181d5
KT		 21437 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
21438 inst.instruction |= LOW4 (Rn) << 16;
21439 inst.instruction |= LOW4 (Rm);
21440 inst.instruction |= sz << (thumb_mode ? 4 : 21);
21441 inst.instruction |= poly << (thumb_mode ? 20 : 9);
21442
21443 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
21444 as_warn (UNPRED_REG ("r15"));
dd5181d5
KT		 21445}
21446
21447static void
21448do_crc32b (void)
21449{
21450 do_crc32_1 (0, 0);
21451}
21452
21453static void
21454do_crc32h (void)
21455{
21456 do_crc32_1 (0, 1);
21457}
21458
21459static void
21460do_crc32w (void)
21461{
21462 do_crc32_1 (0, 2);
21463}
21464
21465static void
21466do_crc32cb (void)
21467{
21468 do_crc32_1 (1, 0);
21469}
21470
21471static void
21472do_crc32ch (void)
21473{
21474 do_crc32_1 (1, 1);
21475}
21476
21477static void
21478do_crc32cw (void)
21479{
21480 do_crc32_1 (1, 2);
21481}
21482
49e8a725
SN		 21483static void
21484do_vjcvt (void)
21485{
21486 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21487 _(BAD_FPU));
21488 neon_check_type (2, NS_FD, N_S32, N_F64);
21489 do_vfp_sp_dp_cvt ();
21490 do_vfp_cond_or_thumb ();
21491}
21492
5287ad62
JB		 21493\f
21494/* Overall per-instruction processing. */
21495
21496/* We need to be able to fix up arbitrary expressions in some statements.
21497 This is so that we can handle symbols that are an arbitrary distance from
21498 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21499 which returns part of an address in a form which will be valid for
21500 a data instruction. We do this by pushing the expression into a symbol
21501 in the expr_section, and creating a fix for that. */
21502
21503static void
21504fix_new_arm (fragS * frag,
21505 int where,
21506 short int size,
21507 expressionS * exp,
21508 int pc_rel,
21509 int reloc)
21510{
21511 fixS * new_fix;
21512
21513 switch (exp->X_op)
21514 {
21515 case O_constant:
6e7ce2cd
PB		 21516 if (pc_rel)
21517 {
21518 /* Create an absolute valued symbol, so we have something to
477330fc
RM		 21519 refer to in the object file. Unfortunately for us, gas's
21520 generic expression parsing will already have folded out
21521 any use of .set foo/.type foo %function that may have
21522 been used to set type information of the target location,
21523 that's being specified symbolically. We have to presume
21524 the user knows what they are doing. */
6e7ce2cd
PB		 21525 char name[16 + 8];
21526 symbolS *symbol;
21527
21528 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
21529
21530 symbol = symbol_find_or_make (name);
21531 S_SET_SEGMENT (symbol, absolute_section);
21532 symbol_set_frag (symbol, &zero_address_frag);
21533 S_SET_VALUE (symbol, exp->X_add_number);
21534 exp->X_op = O_symbol;
21535 exp->X_add_symbol = symbol;
21536 exp->X_add_number = 0;
21537 }
21538 /* FALLTHROUGH */
5287ad62
JB		 21539 case O_symbol:
21540 case O_add:
21541 case O_subtract:
21d799b5 21542 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
477330fc 21543 (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 21544 break;
21545
21546 default:
21d799b5 21547 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
477330fc 21548 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 21549 break;
21550 }
21551
21552 /* Mark whether the fix is to a THUMB instruction, or an ARM
21553 instruction. */
21554 new_fix->tc_fix_data = thumb_mode;
21555}
21556
21557/* Create a frg for an instruction requiring relaxation. */
21558static void
21559output_relax_insn (void)
21560{
21561 char * to;
21562 symbolS *sym;
0110f2b8
PB		 21563 int offset;
21564
6e1cb1a6
PB		 21565 /* The size of the instruction is unknown, so tie the debug info to the
21566 start of the instruction. */
21567 dwarf2_emit_insn (0);
6e1cb1a6 21568
e2b0ab59 21569 switch (inst.relocs[0].exp.X_op)
0110f2b8
PB		 21570 {
21571 case O_symbol:
e2b0ab59
AV		 21572 sym = inst.relocs[0].exp.X_add_symbol;
21573 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB		 21574 break;
21575 case O_constant:
21576 sym = NULL;
e2b0ab59 21577 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB		 21578 break;
21579 default:
e2b0ab59 21580 sym = make_expr_symbol (&inst.relocs[0].exp);
0110f2b8
PB		 21581 offset = 0;
21582 break;
21583 }
21584 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
21585 inst.relax, sym, offset, NULL/*offset, opcode*/);
21586 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB		 21587}
21588
21589/* Write a 32-bit thumb instruction to buf. */
21590static void
21591put_thumb32_insn (char * buf, unsigned long insn)
21592{
21593 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
21594 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
21595}
21596
b99bd4ef 21597static void
c19d1205 21598output_inst (const char * str)
b99bd4ef 21599{
c19d1205 21600 char * to = NULL;
b99bd4ef 21601
c19d1205 21602 if (inst.error)
b99bd4ef 21603 {
c19d1205 21604 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC		 21605 return;
21606 }
5f4273c7
NC		 21607 if (inst.relax)
21608 {
21609 output_relax_insn ();
0110f2b8 21610 return;
5f4273c7 21611 }
c19d1205
ZW		 21612 if (inst.size == 0)
21613 return;
b99bd4ef 21614
c19d1205 21615 to = frag_more (inst.size);
8dc2430f
NC		 21616 /* PR 9814: Record the thumb mode into the current frag so that we know
21617 what type of NOP padding to use, if necessary. We override any previous
21618 setting so that if the mode has changed then the NOPS that we use will
21619 match the encoding of the last instruction in the frag. */
cd000bff 21620 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW		 21621
21622 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 21623 {
9c2799c2 21624 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 21625 put_thumb32_insn (to, inst.instruction);
b99bd4ef 21626 }
c19d1205 21627 else if (inst.size > INSN_SIZE)
b99bd4ef 21628 {
9c2799c2 21629 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW		 21630 md_number_to_chars (to, inst.instruction, INSN_SIZE);
21631 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 21632 }
c19d1205
ZW		 21633 else
21634 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 21635
e2b0ab59
AV		 21636 int r;
21637 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
21638 {
21639 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
21640 fix_new_arm (frag_now, to - frag_now->fr_literal,
21641 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
21642 inst.relocs[r].type);
21643 }
b99bd4ef 21644
c19d1205 21645 dwarf2_emit_insn (inst.size);
c19d1205 21646}
b99bd4ef 21647
e07e6e58
NC		 21648static char *
21649output_it_inst (int cond, int mask, char * to)
21650{
21651 unsigned long instruction = 0xbf00;
21652
21653 mask &= 0xf;
21654 instruction |= mask;
21655 instruction |= cond << 4;
21656
21657 if (to == NULL)
21658 {
21659 to = frag_more (2);
21660#ifdef OBJ_ELF
21661 dwarf2_emit_insn (2);
21662#endif
21663 }
21664
21665 md_number_to_chars (to, instruction, 2);
21666
21667 return to;
21668}
21669
c19d1205
ZW		 21670/* Tag values used in struct asm_opcode's tag field. */
21671enum opcode_tag
21672{
21673 OT_unconditional, /* Instruction cannot be conditionalized.
21674 The ARM condition field is still 0xE. */
21675 OT_unconditionalF, /* Instruction cannot be conditionalized
21676 and carries 0xF in its ARM condition field. */
21677 OT_csuffix, /* Instruction takes a conditional suffix. */
5ee91343
AV		 21678 OT_csuffixF, /* Some forms of the instruction take a scalar
21679 conditional suffix, others place 0xF where the
21680 condition field would be, others take a vector
21681 conditional suffix. */
c19d1205
ZW		 21682 OT_cinfix3, /* Instruction takes a conditional infix,
21683 beginning at character index 3. (In
21684 unified mode, it becomes a suffix.) */
088fa78e
KH		 21685 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
21686 tsts, cmps, cmns, and teqs. */
e3cb604e
PB		 21687 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
21688 character index 3, even in unified mode. Used for
21689 legacy instructions where suffix and infix forms
21690 may be ambiguous. */
c19d1205 21691 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 21692 suffix or an infix at character index 3. */
c19d1205
ZW		 21693 OT_odd_infix_unc, /* This is the unconditional variant of an
21694 instruction that takes a conditional infix
21695 at an unusual position. In unified mode,
21696 this variant will accept a suffix. */
21697 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
21698 are the conditional variants of instructions that
21699 take conditional infixes in unusual positions.
21700 The infix appears at character index
21701 (tag - OT_odd_infix_0). These are not accepted
21702 in unified mode. */
21703};
b99bd4ef 21704
c19d1205
ZW		 21705/* Subroutine of md_assemble, responsible for looking up the primary
21706 opcode from the mnemonic the user wrote. STR points to the
21707 beginning of the mnemonic.
21708
21709 This is not simply a hash table lookup, because of conditional
21710 variants. Most instructions have conditional variants, which are
21711 expressed with a _conditional affix_ to the mnemonic. If we were
21712 to encode each conditional variant as a literal string in the opcode
21713 table, it would have approximately 20,000 entries.
21714
21715 Most mnemonics take this affix as a suffix, and in unified syntax,
21716 'most' is upgraded to 'all'. However, in the divided syntax, some
21717 instructions take the affix as an infix, notably the s-variants of
21718 the arithmetic instructions. Of those instructions, all but six
21719 have the infix appear after the third character of the mnemonic.
21720
21721 Accordingly, the algorithm for looking up primary opcodes given
21722 an identifier is:
21723
21724 1. Look up the identifier in the opcode table.
21725 If we find a match, go to step U.
21726
21727 2. Look up the last two characters of the identifier in the
21728 conditions table. If we find a match, look up the first N-2
21729 characters of the identifier in the opcode table. If we
21730 find a match, go to step CE.
21731
21732 3. Look up the fourth and fifth characters of the identifier in
21733 the conditions table. If we find a match, extract those
21734 characters from the identifier, and look up the remaining
21735 characters in the opcode table. If we find a match, go
21736 to step CM.
21737
21738 4. Fail.
21739
21740 U. Examine the tag field of the opcode structure, in case this is
21741 one of the six instructions with its conditional infix in an
21742 unusual place. If it is, the tag tells us where to find the
21743 infix; look it up in the conditions table and set inst.cond
21744 accordingly. Otherwise, this is an unconditional instruction.
21745 Again set inst.cond accordingly. Return the opcode structure.
21746
21747 CE. Examine the tag field to make sure this is an instruction that
21748 should receive a conditional suffix. If it is not, fail.
21749 Otherwise, set inst.cond from the suffix we already looked up,
21750 and return the opcode structure.
21751
21752 CM. Examine the tag field to make sure this is an instruction that
21753 should receive a conditional infix after the third character.
21754 If it is not, fail. Otherwise, undo the edits to the current
21755 line of input and proceed as for case CE. */
21756
21757static const struct asm_opcode *
21758opcode_lookup (char **str)
21759{
21760 char *end, *base;
21761 char *affix;
21762 const struct asm_opcode *opcode;
21763 const struct asm_cond *cond;
e3cb604e 21764 char save[2];
c19d1205
ZW		 21765
21766 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 21767 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 21768 for (base = end = *str; *end != '\0'; end++)
721a8186 21769 if (*end == ' ' || *end == '.')
c19d1205 21770 break;
b99bd4ef 21771
c19d1205 21772 if (end == base)
c921be7d 21773 return NULL;
b99bd4ef 21774
5287ad62 21775 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 21776 if (end[0] == '.')
b99bd4ef 21777 {
5287ad62 21778 int offset = 2;
5f4273c7 21779
267d2029 21780 /* The .w and .n suffixes are only valid if the unified syntax is in
477330fc 21781 use. */
267d2029 21782 if (unified_syntax && end[1] == 'w')
c19d1205 21783 inst.size_req = 4;
267d2029 21784 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW		 21785 inst.size_req = 2;
21786 else
477330fc 21787 offset = 0;
5287ad62
JB		 21788
21789 inst.vectype.elems = 0;
21790
21791 *str = end + offset;
b99bd4ef 21792
5f4273c7 21793 if (end[offset] == '.')
5287ad62 21794 {
267d2029 21795 /* See if we have a Neon type suffix (possible in either unified or
477330fc
RM		 21796 non-unified ARM syntax mode). */
21797 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 21798 return NULL;
477330fc 21799 }
5287ad62 21800 else if (end[offset] != '\0' && end[offset] != ' ')
477330fc 21801 return NULL;
b99bd4ef 21802 }
c19d1205
ZW		 21803 else
21804 *str = end;
b99bd4ef 21805
c19d1205 21806 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5 21807 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 21808 end - base);
c19d1205 21809 if (opcode)
b99bd4ef 21810 {
c19d1205
ZW		 21811 /* step U */
21812 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 21813 {
c19d1205
ZW		 21814 inst.cond = COND_ALWAYS;
21815 return opcode;
b99bd4ef 21816 }
b99bd4ef 21817
278df34e 21818 if (warn_on_deprecated && unified_syntax)
5c3696f8 21819 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205 21820 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 21821 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 21822 gas_assert (cond);
b99bd4ef 21823
c19d1205
ZW		 21824 inst.cond = cond->value;
21825 return opcode;
21826 }
5ee91343
AV		 21827 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21828 {
21829 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21830 */
21831 if (end - base < 2)
21832 return NULL;
21833 affix = end - 1;
21834 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
21835 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21836 affix - base);
21837 /* If this opcode can not be vector predicated then don't accept it with a
21838 vector predication code. */
21839 if (opcode && !opcode->mayBeVecPred)
21840 opcode = NULL;
21841 }
21842 if (!opcode || !cond)
21843 {
21844 /* Cannot have a conditional suffix on a mnemonic of less than two
21845 characters. */
21846 if (end - base < 3)
21847 return NULL;
b99bd4ef 21848
5ee91343
AV		 21849 /* Look for suffixed mnemonic. */
21850 affix = end - 2;
21851 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
21852 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21853 affix - base);
21854 }
b99bd4ef 21855
c19d1205
ZW		 21856 if (opcode && cond)
21857 {
21858 /* step CE */
21859 switch (opcode->tag)
21860 {
e3cb604e
PB		 21861 case OT_cinfix3_legacy:
21862 /* Ignore conditional suffixes matched on infix only mnemonics. */
21863 break;
21864
c19d1205 21865 case OT_cinfix3:
088fa78e 21866 case OT_cinfix3_deprecated:
c19d1205
ZW		 21867 case OT_odd_infix_unc:
21868 if (!unified_syntax)
0198d5e6 21869 return NULL;
1a0670f3 21870 /* Fall through. */
c19d1205
ZW		 21871
21872 case OT_csuffix:
477330fc 21873 case OT_csuffixF:
c19d1205
ZW		 21874 case OT_csuf_or_in3:
21875 inst.cond = cond->value;
21876 return opcode;
21877
21878 case OT_unconditional:
21879 case OT_unconditionalF:
dfa9f0d5 21880 if (thumb_mode)
c921be7d 21881 inst.cond = cond->value;
dfa9f0d5
PB		 21882 else
21883 {
c921be7d 21884 /* Delayed diagnostic. */
dfa9f0d5
PB		 21885 inst.error = BAD_COND;
21886 inst.cond = COND_ALWAYS;
21887 }
c19d1205 21888 return opcode;
b99bd4ef 21889
c19d1205 21890 default:
c921be7d 21891 return NULL;
c19d1205
ZW		 21892 }
21893 }
b99bd4ef 21894
c19d1205
ZW		 21895 /* Cannot have a usual-position infix on a mnemonic of less than
21896 six characters (five would be a suffix). */
21897 if (end - base < 6)
c921be7d 21898 return NULL;
b99bd4ef 21899
c19d1205
ZW		 21900 /* Look for infixed mnemonic in the usual position. */
21901 affix = base + 3;
21d799b5 21902 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 21903 if (!cond)
c921be7d 21904 return NULL;
e3cb604e
PB		 21905
21906 memcpy (save, affix, 2);
21907 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5 21908 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 21909 (end - base) - 2);
e3cb604e
PB		 21910 memmove (affix + 2, affix, (end - affix) - 2);
21911 memcpy (affix, save, 2);
21912
088fa78e
KH		 21913 if (opcode
21914 && (opcode->tag == OT_cinfix3
21915 || opcode->tag == OT_cinfix3_deprecated
21916 || opcode->tag == OT_csuf_or_in3
21917 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 21918 {
c921be7d 21919 /* Step CM. */
278df34e 21920 if (warn_on_deprecated && unified_syntax
088fa78e
KH		 21921 && (opcode->tag == OT_cinfix3
21922 || opcode->tag == OT_cinfix3_deprecated))
5c3696f8 21923 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205
ZW		 21924
21925 inst.cond = cond->value;
21926 return opcode;
b99bd4ef
NC		 21927 }
21928
c921be7d 21929 return NULL;
b99bd4ef
NC		 21930}
21931
e07e6e58
NC		 21932/* This function generates an initial IT instruction, leaving its block
21933 virtually open for the new instructions. Eventually,
5ee91343 21934 the mask will be updated by now_pred_add_mask () each time
e07e6e58
NC		 21935 a new instruction needs to be included in the IT block.
21936 Finally, the block is closed with close_automatic_it_block ().
21937 The block closure can be requested either from md_assemble (),
21938 a tencode (), or due to a label hook. */
21939
21940static void
21941new_automatic_it_block (int cond)
21942{
5ee91343
AV		 21943 now_pred.state = AUTOMATIC_PRED_BLOCK;
21944 now_pred.mask = 0x18;
21945 now_pred.cc = cond;
21946 now_pred.block_length = 1;
cd000bff 21947 mapping_state (MAP_THUMB);
5ee91343
AV		 21948 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
21949 now_pred.warn_deprecated = FALSE;
21950 now_pred.insn_cond = TRUE;
e07e6e58
NC		 21951}
21952
21953/* Close an automatic IT block.
21954 See comments in new_automatic_it_block (). */
21955
21956static void
21957close_automatic_it_block (void)
21958{
5ee91343
AV		 21959 now_pred.mask = 0x10;
21960 now_pred.block_length = 0;
e07e6e58
NC		 21961}
21962
21963/* Update the mask of the current automatically-generated IT
21964 instruction. See comments in new_automatic_it_block (). */
21965
21966static void
5ee91343 21967now_pred_add_mask (int cond)
e07e6e58
NC		 21968{
21969#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21970#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
477330fc 21971 | ((bitvalue) << (nbit)))
e07e6e58 21972 const int resulting_bit = (cond & 1);
c921be7d 21973
5ee91343
AV		 21974 now_pred.mask &= 0xf;
21975 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 21976 resulting_bit,
5ee91343
AV		 21977 (5 - now_pred.block_length));
21978 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 21979 1,
5ee91343
AV		 21980 ((5 - now_pred.block_length) - 1));
21981 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
e07e6e58
NC		 21982
21983#undef CLEAR_BIT
21984#undef SET_BIT_VALUE
e07e6e58
NC		 21985}
21986
21987/* The IT blocks handling machinery is accessed through the these functions:
21988 it_fsm_pre_encode () from md_assemble ()
5ee91343
AV		 21989 set_pred_insn_type () optional, from the tencode functions
21990 set_pred_insn_type_last () ditto
21991 in_pred_block () ditto
e07e6e58 21992 it_fsm_post_encode () from md_assemble ()
33eaf5de 21993 force_automatic_it_block_close () from label handling functions
e07e6e58
NC		 21994
21995 Rationale:
21996 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
477330fc
RM		 21997 initializing the IT insn type with a generic initial value depending
21998 on the inst.condition.
e07e6e58 21999 2) During the tencode function, two things may happen:
477330fc 22000 a) The tencode function overrides the IT insn type by
5ee91343
AV		 22001 calling either set_pred_insn_type (type) or
22002 set_pred_insn_type_last ().
477330fc 22003 b) The tencode function queries the IT block state by
5ee91343 22004 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
477330fc 22005
5ee91343
AV		 22006 Both set_pred_insn_type and in_pred_block run the internal FSM state
22007 handling function (handle_pred_state), because: a) setting the IT insn
477330fc
RM		 22008 type may incur in an invalid state (exiting the function),
22009 and b) querying the state requires the FSM to be updated.
22010 Specifically we want to avoid creating an IT block for conditional
22011 branches, so it_fsm_pre_encode is actually a guess and we can't
22012 determine whether an IT block is required until the tencode () routine
22013 has decided what type of instruction this actually it.
5ee91343
AV		 22014 Because of this, if set_pred_insn_type and in_pred_block have to be
22015 used, set_pred_insn_type has to be called first.
477330fc 22016
5ee91343
AV		 22017 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22018 that determines the insn IT type depending on the inst.cond code.
477330fc
RM		 22019 When a tencode () routine encodes an instruction that can be
22020 either outside an IT block, or, in the case of being inside, has to be
5ee91343 22021 the last one, set_pred_insn_type_last () will determine the proper
477330fc 22022 IT instruction type based on the inst.cond code. Otherwise,
5ee91343 22023 set_pred_insn_type can be called for overriding that logic or
477330fc
RM		 22024 for covering other cases.
22025
5ee91343
AV		 22026 Calling handle_pred_state () may not transition the IT block state to
22027 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
477330fc 22028 still queried. Instead, if the FSM determines that the state should
5ee91343 22029 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
477330fc
RM		 22030 after the tencode () function: that's what it_fsm_post_encode () does.
22031
5ee91343 22032 Since in_pred_block () calls the state handling function to get an
477330fc
RM		 22033 updated state, an error may occur (due to invalid insns combination).
22034 In that case, inst.error is set.
22035 Therefore, inst.error has to be checked after the execution of
22036 the tencode () routine.
e07e6e58
NC		 22037
22038 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
477330fc 22039 any pending state change (if any) that didn't take place in
5ee91343 22040 handle_pred_state () as explained above. */
e07e6e58
NC		 22041
22042static void
22043it_fsm_pre_encode (void)
22044{
22045 if (inst.cond != COND_ALWAYS)
5ee91343 22046 inst.pred_insn_type = INSIDE_IT_INSN;
e07e6e58 22047 else
5ee91343 22048 inst.pred_insn_type = OUTSIDE_PRED_INSN;
e07e6e58 22049
5ee91343 22050 now_pred.state_handled = 0;
e07e6e58
NC		 22051}
22052
22053/* IT state FSM handling function. */
5ee91343
AV		 22054/* MVE instructions and non-MVE instructions are handled differently because of
22055 the introduction of VPT blocks.
22056 Specifications say that any non-MVE instruction inside a VPT block is
22057 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22058 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
35c228db 22059 few exceptions we have MVE_UNPREDICABLE_INSN.
5ee91343
AV		 22060 The error messages provided depending on the different combinations possible
22061 are described in the cases below:
22062 For 'most' MVE instructions:
22063 1) In an IT block, with an IT code: syntax error
22064 2) In an IT block, with a VPT code: error: must be in a VPT block
22065 3) In an IT block, with no code: warning: UNPREDICTABLE
22066 4) In a VPT block, with an IT code: syntax error
22067 5) In a VPT block, with a VPT code: OK!
22068 6) In a VPT block, with no code: error: missing code
22069 7) Outside a pred block, with an IT code: error: syntax error
22070 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22071 9) Outside a pred block, with no code: OK!
22072 For non-MVE instructions:
22073 10) In an IT block, with an IT code: OK!
22074 11) In an IT block, with a VPT code: syntax error
22075 12) In an IT block, with no code: error: missing code
22076 13) In a VPT block, with an IT code: error: should be in an IT block
22077 14) In a VPT block, with a VPT code: syntax error
22078 15) In a VPT block, with no code: UNPREDICTABLE
22079 16) Outside a pred block, with an IT code: error: should be in an IT block
22080 17) Outside a pred block, with a VPT code: syntax error
22081 18) Outside a pred block, with no code: OK!
22082 */
22083
e07e6e58
NC		 22084
22085static int
5ee91343 22086handle_pred_state (void)
e07e6e58 22087{
5ee91343
AV		 22088 now_pred.state_handled = 1;
22089 now_pred.insn_cond = FALSE;
e07e6e58 22090
5ee91343 22091 switch (now_pred.state)
e07e6e58 22092 {
5ee91343
AV		 22093 case OUTSIDE_PRED_BLOCK:
22094 switch (inst.pred_insn_type)
e07e6e58 22095 {
35c228db 22096 case MVE_UNPREDICABLE_INSN:
5ee91343
AV		 22097 case MVE_OUTSIDE_PRED_INSN:
22098 if (inst.cond < COND_ALWAYS)
22099 {
22100 /* Case 7: Outside a pred block, with an IT code: error: syntax
22101 error. */
22102 inst.error = BAD_SYNTAX;
22103 return FAIL;
22104 }
22105 /* Case 9: Outside a pred block, with no code: OK! */
22106 break;
22107 case OUTSIDE_PRED_INSN:
22108 if (inst.cond > COND_ALWAYS)
22109 {
22110 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22111 */
22112 inst.error = BAD_SYNTAX;
22113 return FAIL;
22114 }
22115 /* Case 18: Outside a pred block, with no code: OK! */
e07e6e58
NC		 22116 break;
22117
5ee91343
AV		 22118 case INSIDE_VPT_INSN:
22119 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22120 a VPT block. */
22121 inst.error = BAD_OUT_VPT;
22122 return FAIL;
22123
e07e6e58
NC		 22124 case INSIDE_IT_INSN:
22125 case INSIDE_IT_LAST_INSN:
5ee91343 22126 if (inst.cond < COND_ALWAYS)
e07e6e58 22127 {
5ee91343
AV		 22128 /* Case 16: Outside a pred block, with an IT code: error: should
22129 be in an IT block. */
22130 if (thumb_mode == 0)
e07e6e58 22131 {
5ee91343
AV		 22132 if (unified_syntax
22133 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
22134 as_tsktsk (_("Warning: conditional outside an IT block"\
22135 " for Thumb."));
e07e6e58
NC		 22136 }
22137 else
22138 {
5ee91343
AV		 22139 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
22140 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
22141 {
22142 /* Automatically generate the IT instruction. */
22143 new_automatic_it_block (inst.cond);
22144 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
22145 close_automatic_it_block ();
22146 }
22147 else
22148 {
22149 inst.error = BAD_OUT_IT;
22150 return FAIL;
22151 }
e07e6e58 22152 }
5ee91343 22153 break;
e07e6e58 22154 }
5ee91343
AV		 22155 else if (inst.cond > COND_ALWAYS)
22156 {
22157 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22158 */
22159 inst.error = BAD_SYNTAX;
22160 return FAIL;
22161 }
22162 else
22163 gas_assert (0);
e07e6e58
NC		 22164 case IF_INSIDE_IT_LAST_INSN:
22165 case NEUTRAL_IT_INSN:
22166 break;
22167
5ee91343
AV		 22168 case VPT_INSN:
22169 if (inst.cond != COND_ALWAYS)
22170 first_error (BAD_SYNTAX);
22171 now_pred.state = MANUAL_PRED_BLOCK;
22172 now_pred.block_length = 0;
22173 now_pred.type = VECTOR_PRED;
22174 now_pred.cc = 0;
22175 break;
e07e6e58 22176 case IT_INSN:
5ee91343
AV		 22177 now_pred.state = MANUAL_PRED_BLOCK;
22178 now_pred.block_length = 0;
22179 now_pred.type = SCALAR_PRED;
e07e6e58
NC		 22180 break;
22181 }
22182 break;
22183
5ee91343 22184 case AUTOMATIC_PRED_BLOCK:
e07e6e58
NC		 22185 /* Three things may happen now:
22186 a) We should increment current it block size;
22187 b) We should close current it block (closing insn or 4 insns);
22188 c) We should close current it block and start a new one (due
22189 to incompatible conditions or
22190 4 insns-length block reached). */
22191
5ee91343 22192 switch (inst.pred_insn_type)
e07e6e58 22193 {
5ee91343
AV		 22194 case INSIDE_VPT_INSN:
22195 case VPT_INSN:
35c228db 22196 case MVE_UNPREDICABLE_INSN:
5ee91343
AV		 22197 case MVE_OUTSIDE_PRED_INSN:
22198 gas_assert (0);
22199 case OUTSIDE_PRED_INSN:
2b0f3761 22200 /* The closure of the block shall happen immediately,
5ee91343 22201 so any in_pred_block () call reports the block as closed. */
e07e6e58
NC		 22202 force_automatic_it_block_close ();
22203 break;
22204
22205 case INSIDE_IT_INSN:
22206 case INSIDE_IT_LAST_INSN:
22207 case IF_INSIDE_IT_LAST_INSN:
5ee91343 22208 now_pred.block_length++;
e07e6e58 22209
5ee91343
AV		 22210 if (now_pred.block_length > 4
22211 || !now_pred_compatible (inst.cond))
e07e6e58
NC		 22212 {
22213 force_automatic_it_block_close ();
5ee91343 22214 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
e07e6e58
NC		 22215 new_automatic_it_block (inst.cond);
22216 }
22217 else
22218 {
5ee91343
AV		 22219 now_pred.insn_cond = TRUE;
22220 now_pred_add_mask (inst.cond);
e07e6e58
NC		 22221 }
22222
5ee91343
AV		 22223 if (now_pred.state == AUTOMATIC_PRED_BLOCK
22224 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
22225 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
e07e6e58
NC		 22226 close_automatic_it_block ();
22227 break;
22228
22229 case NEUTRAL_IT_INSN:
5ee91343
AV		 22230 now_pred.block_length++;
22231 now_pred.insn_cond = TRUE;
e07e6e58 22232
5ee91343 22233 if (now_pred.block_length > 4)
e07e6e58
NC		 22234 force_automatic_it_block_close ();
22235 else
5ee91343 22236 now_pred_add_mask (now_pred.cc & 1);
e07e6e58
NC		 22237 break;
22238
22239 case IT_INSN:
22240 close_automatic_it_block ();
5ee91343 22241 now_pred.state = MANUAL_PRED_BLOCK;
e07e6e58
NC		 22242 break;
22243 }
22244 break;
22245
5ee91343 22246 case MANUAL_PRED_BLOCK:
e07e6e58 22247 {
5ee91343
AV		 22248 int cond, is_last;
22249 if (now_pred.type == SCALAR_PRED)
e07e6e58 22250 {
5ee91343
AV		 22251 /* Check conditional suffixes. */
22252 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
22253 now_pred.mask <<= 1;
22254 now_pred.mask &= 0x1f;
22255 is_last = (now_pred.mask == 0x10);
22256 }
22257 else
22258 {
22259 now_pred.cc ^= (now_pred.mask >> 4);
22260 cond = now_pred.cc + 0xf;
22261 now_pred.mask <<= 1;
22262 now_pred.mask &= 0x1f;
22263 is_last = now_pred.mask == 0x10;
22264 }
22265 now_pred.insn_cond = TRUE;
e07e6e58 22266
5ee91343
AV		 22267 switch (inst.pred_insn_type)
22268 {
22269 case OUTSIDE_PRED_INSN:
22270 if (now_pred.type == SCALAR_PRED)
22271 {
22272 if (inst.cond == COND_ALWAYS)
22273 {
22274 /* Case 12: In an IT block, with no code: error: missing
22275 code. */
22276 inst.error = BAD_NOT_IT;
22277 return FAIL;
22278 }
22279 else if (inst.cond > COND_ALWAYS)
22280 {
22281 /* Case 11: In an IT block, with a VPT code: syntax error.
22282 */
22283 inst.error = BAD_SYNTAX;
22284 return FAIL;
22285 }
22286 else if (thumb_mode)
22287 {
22288 /* This is for some special cases where a non-MVE
22289 instruction is not allowed in an IT block, such as cbz,
22290 but are put into one with a condition code.
22291 You could argue this should be a syntax error, but we
22292 gave the 'not allowed in IT block' diagnostic in the
22293 past so we will keep doing so. */
22294 inst.error = BAD_NOT_IT;
22295 return FAIL;
22296 }
22297 break;
22298 }
22299 else
22300 {
22301 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22302 as_tsktsk (MVE_NOT_VPT);
22303 return SUCCESS;
22304 }
22305 case MVE_OUTSIDE_PRED_INSN:
22306 if (now_pred.type == SCALAR_PRED)
22307 {
22308 if (inst.cond == COND_ALWAYS)
22309 {
22310 /* Case 3: In an IT block, with no code: warning:
22311 UNPREDICTABLE. */
22312 as_tsktsk (MVE_NOT_IT);
22313 return SUCCESS;
22314 }
22315 else if (inst.cond < COND_ALWAYS)
22316 {
22317 /* Case 1: In an IT block, with an IT code: syntax error.
22318 */
22319 inst.error = BAD_SYNTAX;
22320 return FAIL;
22321 }
22322 else
22323 gas_assert (0);
22324 }
22325 else
22326 {
22327 if (inst.cond < COND_ALWAYS)
22328 {
22329 /* Case 4: In a VPT block, with an IT code: syntax error.
22330 */
22331 inst.error = BAD_SYNTAX;
22332 return FAIL;
22333 }
22334 else if (inst.cond == COND_ALWAYS)
22335 {
22336 /* Case 6: In a VPT block, with no code: error: missing
22337 code. */
22338 inst.error = BAD_NOT_VPT;
22339 return FAIL;
22340 }
22341 else
22342 {
22343 gas_assert (0);
22344 }
22345 }
35c228db
AV		 22346 case MVE_UNPREDICABLE_INSN:
22347 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
22348 return SUCCESS;
e07e6e58 22349 case INSIDE_IT_INSN:
5ee91343 22350 if (inst.cond > COND_ALWAYS)
e07e6e58 22351 {
5ee91343
AV		 22352 /* Case 11: In an IT block, with a VPT code: syntax error. */
22353 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22354 inst.error = BAD_SYNTAX;
22355 return FAIL;
22356 }
22357 else if (now_pred.type == SCALAR_PRED)
22358 {
22359 /* Case 10: In an IT block, with an IT code: OK! */
22360 if (cond != inst.cond)
22361 {
22362 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
22363 BAD_VPT_COND;
22364 return FAIL;
22365 }
22366 }
22367 else
22368 {
22369 /* Case 13: In a VPT block, with an IT code: error: should be
22370 in an IT block. */
22371 inst.error = BAD_OUT_IT;
e07e6e58
NC		 22372 return FAIL;
22373 }
22374 break;
22375
5ee91343
AV		 22376 case INSIDE_VPT_INSN:
22377 if (now_pred.type == SCALAR_PRED)
22378 {
22379 /* Case 2: In an IT block, with a VPT code: error: must be in a
22380 VPT block. */
22381 inst.error = BAD_OUT_VPT;
22382 return FAIL;
22383 }
22384 /* Case 5: In a VPT block, with a VPT code: OK! */
22385 else if (cond != inst.cond)
22386 {
22387 inst.error = BAD_VPT_COND;
22388 return FAIL;
22389 }
22390 break;
e07e6e58
NC		 22391 case INSIDE_IT_LAST_INSN:
22392 case IF_INSIDE_IT_LAST_INSN:
5ee91343
AV		 22393 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
22394 {
22395 /* Case 4: In a VPT block, with an IT code: syntax error. */
22396 /* Case 11: In an IT block, with a VPT code: syntax error. */
22397 inst.error = BAD_SYNTAX;
22398 return FAIL;
22399 }
22400 else if (cond != inst.cond)
e07e6e58
NC		 22401 {
22402 inst.error = BAD_IT_COND;
22403 return FAIL;
22404 }
22405 if (!is_last)
22406 {
22407 inst.error = BAD_BRANCH;
22408 return FAIL;
22409 }
22410 break;
22411
22412 case NEUTRAL_IT_INSN:
5ee91343
AV		 22413 /* The BKPT instruction is unconditional even in a IT or VPT
22414 block. */
e07e6e58
NC		 22415 break;
22416
22417 case IT_INSN:
5ee91343
AV		 22418 if (now_pred.type == SCALAR_PRED)
22419 {
22420 inst.error = BAD_IT_IT;
22421 return FAIL;
22422 }
22423 /* fall through. */
22424 case VPT_INSN:
22425 if (inst.cond == COND_ALWAYS)
22426 {
22427 /* Executing a VPT/VPST instruction inside an IT block or a
22428 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22429 */
22430 if (now_pred.type == SCALAR_PRED)
22431 as_tsktsk (MVE_NOT_IT);
22432 else
22433 as_tsktsk (MVE_NOT_VPT);
22434 return SUCCESS;
22435 }
22436 else
22437 {
22438 /* VPT/VPST do not accept condition codes. */
22439 inst.error = BAD_SYNTAX;
22440 return FAIL;
22441 }
e07e6e58 22442 }
5ee91343 22443 }
e07e6e58
NC		 22444 break;
22445 }
22446
22447 return SUCCESS;
22448}
22449
5a01bb1d
MGD		 22450struct depr_insn_mask
22451{
22452 unsigned long pattern;
22453 unsigned long mask;
22454 const char* description;
22455};
22456
22457/* List of 16-bit instruction patterns deprecated in an IT block in
22458 ARMv8. */
22459static const struct depr_insn_mask depr_it_insns[] = {
22460 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22461 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22462 { 0xa000, 0xb800, N_("ADR") },
22463 { 0x4800, 0xf800, N_("Literal loads") },
22464 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22465 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
c8de034b
JW		 22466 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22467 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22468 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
5a01bb1d
MGD		 22469 { 0, 0, NULL }
22470};
22471
e07e6e58
NC		 22472static void
22473it_fsm_post_encode (void)
22474{
22475 int is_last;
22476
5ee91343
AV		 22477 if (!now_pred.state_handled)
22478 handle_pred_state ();
e07e6e58 22479
5ee91343
AV		 22480 if (now_pred.insn_cond
22481 && !now_pred.warn_deprecated
5a01bb1d 22482 && warn_on_deprecated
df9909b8
TP		 22483 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
22484 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
5a01bb1d
MGD		 22485 {
22486 if (inst.instruction >= 0x10000)
22487 {
5c3696f8 22488 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
df9909b8 22489 "performance deprecated in ARMv8-A and ARMv8-R"));
5ee91343 22490 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 22491 }
22492 else
22493 {
22494 const struct depr_insn_mask *p = depr_it_insns;
22495
22496 while (p->mask != 0)
22497 {
22498 if ((inst.instruction & p->mask) == p->pattern)
22499 {
df9909b8
TP		 22500 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22501 "instructions of the following class are "
22502 "performance deprecated in ARMv8-A and "
22503 "ARMv8-R: %s"), p->description);
5ee91343 22504 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 22505 break;
22506 }
22507
22508 ++p;
22509 }
22510 }
22511
5ee91343 22512 if (now_pred.block_length > 1)
5a01bb1d 22513 {
5c3696f8 22514 as_tsktsk (_("IT blocks containing more than one conditional "
df9909b8
TP		 22515 "instruction are performance deprecated in ARMv8-A and "
22516 "ARMv8-R"));
5ee91343 22517 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 22518 }
22519 }
22520
5ee91343
AV		 22521 is_last = (now_pred.mask == 0x10);
22522 if (is_last)
22523 {
22524 now_pred.state = OUTSIDE_PRED_BLOCK;
22525 now_pred.mask = 0;
22526 }
e07e6e58
NC		 22527}
22528
22529static void
22530force_automatic_it_block_close (void)
22531{
5ee91343 22532 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
e07e6e58
NC		 22533 {
22534 close_automatic_it_block ();
5ee91343
AV		 22535 now_pred.state = OUTSIDE_PRED_BLOCK;
22536 now_pred.mask = 0;
e07e6e58
NC		 22537 }
22538}
22539
22540static int
5ee91343 22541in_pred_block (void)
e07e6e58 22542{
5ee91343
AV		 22543 if (!now_pred.state_handled)
22544 handle_pred_state ();
e07e6e58 22545
5ee91343 22546 return now_pred.state != OUTSIDE_PRED_BLOCK;
e07e6e58
NC		 22547}
22548
ff8646ee
TP		 22549/* Whether OPCODE only has T32 encoding. Since this function is only used by
22550 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22551 here, hence the "known" in the function name. */
fc289b0a
TP		 22552
22553static bfd_boolean
ff8646ee 22554known_t32_only_insn (const struct asm_opcode *opcode)
fc289b0a
TP		 22555{
22556 /* Original Thumb-1 wide instruction. */
22557 if (opcode->tencode == do_t_blx
22558 || opcode->tencode == do_t_branch23
22559 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
22560 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
22561 return TRUE;
22562
16a1fa25
TP		 22563 /* Wide-only instruction added to ARMv8-M Baseline. */
22564 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
ff8646ee
TP		 22565 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
22566 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
22567 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
22568 return TRUE;
22569
22570 return FALSE;
22571}
22572
22573/* Whether wide instruction variant can be used if available for a valid OPCODE
22574 in ARCH. */
22575
22576static bfd_boolean
22577t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
22578{
22579 if (known_t32_only_insn (opcode))
22580 return TRUE;
22581
22582 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22583 of variant T3 of B.W is checked in do_t_branch. */
22584 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22585 && opcode->tencode == do_t_branch)
22586 return TRUE;
22587
bada4342
JW		 22588 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22589 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22590 && opcode->tencode == do_t_mov_cmp
22591 /* Make sure CMP instruction is not affected. */
22592 && opcode->aencode == do_mov)
22593 return TRUE;
22594
ff8646ee
TP		 22595 /* Wide instruction variants of all instructions with narrow *and* wide
22596 variants become available with ARMv6t2. Other opcodes are either
22597 narrow-only or wide-only and are thus available if OPCODE is valid. */
22598 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
22599 return TRUE;
22600
22601 /* OPCODE with narrow only instruction variant or wide variant not
22602 available. */
fc289b0a
TP		 22603 return FALSE;
22604}
22605
c19d1205
ZW		 22606void
22607md_assemble (char *str)
b99bd4ef 22608{
c19d1205
ZW		 22609 char *p = str;
22610 const struct asm_opcode * opcode;
b99bd4ef 22611
c19d1205
ZW		 22612 /* Align the previous label if needed. */
22613 if (last_label_seen != NULL)
b99bd4ef 22614 {
c19d1205
ZW		 22615 symbol_set_frag (last_label_seen, frag_now);
22616 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
22617 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC		 22618 }
22619
c19d1205 22620 memset (&inst, '\0', sizeof (inst));
e2b0ab59
AV		 22621 int r;
22622 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
22623 inst.relocs[r].type = BFD_RELOC_UNUSED;
b99bd4ef 22624
c19d1205
ZW		 22625 opcode = opcode_lookup (&p);
22626 if (!opcode)
b99bd4ef 22627 {
c19d1205 22628 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 22629 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d 22630 if (! create_register_alias (str, p)
477330fc 22631 && ! create_neon_reg_alias (str, p))
c19d1205 22632 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 22633
b99bd4ef
NC		 22634 return;
22635 }
22636
278df34e 22637 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
5c3696f8 22638 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
088fa78e 22639
037e8744
JB		 22640 /* The value which unconditional instructions should have in place of the
22641 condition field. */
22642 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
22643
c19d1205 22644 if (thumb_mode)
b99bd4ef 22645 {
e74cfd16 22646 arm_feature_set variant;
8f06b2d8
PB		 22647
22648 variant = cpu_variant;
22649 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB		 22650 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
22651 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 22652 /* Check that this instruction is supported for this CPU. */
62b3e311
PB		 22653 if (!opcode->tvariant
22654 || (thumb_mode == 1
22655 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 22656 {
173205ca
TP		 22657 if (opcode->tencode == do_t_swi)
22658 as_bad (_("SVC is not permitted on this architecture"));
22659 else
22660 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
b99bd4ef
NC		 22661 return;
22662 }
c19d1205
ZW		 22663 if (inst.cond != COND_ALWAYS && !unified_syntax
22664 && opcode->tencode != do_t_branch)
b99bd4ef 22665 {
c19d1205 22666 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC		 22667 return;
22668 }
22669
fc289b0a
TP		 22670 /* Two things are addressed here:
22671 1) Implicit require narrow instructions on Thumb-1.
22672 This avoids relaxation accidentally introducing Thumb-2
22673 instructions.
22674 2) Reject wide instructions in non Thumb-2 cores.
22675
22676 Only instructions with narrow and wide variants need to be handled
22677 but selecting all non wide-only instructions is easier. */
22678 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
ff8646ee 22679 && !t32_insn_ok (variant, opcode))
076d447c 22680 {
fc289b0a
TP		 22681 if (inst.size_req == 0)
22682 inst.size_req = 2;
22683 else if (inst.size_req == 4)
752d5da4 22684 {
ff8646ee
TP		 22685 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
22686 as_bad (_("selected processor does not support 32bit wide "
22687 "variant of instruction `%s'"), str);
22688 else
22689 as_bad (_("selected processor does not support `%s' in "
22690 "Thumb-2 mode"), str);
fc289b0a 22691 return;
752d5da4 22692 }
076d447c
PB		 22693 }
22694
c19d1205
ZW		 22695 inst.instruction = opcode->tvalue;
22696
5be8be5d 22697 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
477330fc 22698 {
5ee91343 22699 /* Prepare the pred_insn_type for those encodings that don't set
477330fc
RM		 22700 it. */
22701 it_fsm_pre_encode ();
c19d1205 22702
477330fc 22703 opcode->tencode ();
e07e6e58 22704
477330fc
RM		 22705 it_fsm_post_encode ();
22706 }
e27ec89e 22707
0110f2b8 22708 if (!(inst.error || inst.relax))
b99bd4ef 22709 {
9c2799c2 22710 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW		 22711 inst.size = (inst.instruction > 0xffff ? 4 : 2);
22712 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 22713 {
c19d1205 22714 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC		 22715 return;
22716 }
22717 }
076d447c
PB		 22718
22719 /* Something has gone badly wrong if we try to relax a fixed size
477330fc 22720 instruction. */
9c2799c2 22721 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 22722
e74cfd16
PB		 22723 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22724 *opcode->tvariant);
ee065d83 22725 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
fc289b0a
TP		 22726 set those bits when Thumb-2 32-bit instructions are seen. The impact
22727 of relaxable instructions will be considered later after we finish all
22728 relaxation. */
ff8646ee
TP		 22729 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
22730 variant = arm_arch_none;
22731 else
22732 variant = cpu_variant;
22733 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
e74cfd16
PB		 22734 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22735 arm_ext_v6t2);
cd000bff 22736
88714cb8
DG		 22737 check_neon_suffixes;
22738
cd000bff 22739 if (!inst.error)
c877a2f2
NC		 22740 {
22741 mapping_state (MAP_THUMB);
22742 }
c19d1205 22743 }
3e9e4fcf 22744 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 22745 {
845b51d6
PB		 22746 bfd_boolean is_bx;
22747
22748 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22749 is_bx = (opcode->aencode == do_bx);
22750
c19d1205 22751 /* Check that this instruction is supported for this CPU. */
845b51d6
PB		 22752 if (!(is_bx && fix_v4bx)
22753 && !(opcode->avariant &&
22754 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 22755 {
84b52b66 22756 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
c19d1205 22757 return;
b99bd4ef 22758 }
c19d1205 22759 if (inst.size_req)
b99bd4ef 22760 {
c19d1205
ZW		 22761 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
22762 return;
b99bd4ef
NC		 22763 }
22764
c19d1205
ZW		 22765 inst.instruction = opcode->avalue;
22766 if (opcode->tag == OT_unconditionalF)
eff0bc54 22767 inst.instruction |= 0xFU << 28;
c19d1205
ZW		 22768 else
22769 inst.instruction |= inst.cond << 28;
22770 inst.size = INSN_SIZE;
5be8be5d 22771 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
477330fc
RM		 22772 {
22773 it_fsm_pre_encode ();
22774 opcode->aencode ();
22775 it_fsm_post_encode ();
22776 }
ee065d83 22777 /* Arm mode bx is marked as both v4T and v5 because it's still required
477330fc 22778 on a hypothetical non-thumb v5 core. */
845b51d6 22779 if (is_bx)
e74cfd16 22780 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 22781 else
e74cfd16
PB		 22782 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
22783 *opcode->avariant);
88714cb8
DG		 22784
22785 check_neon_suffixes;
22786
cd000bff 22787 if (!inst.error)
c877a2f2
NC		 22788 {
22789 mapping_state (MAP_ARM);
22790 }
b99bd4ef 22791 }
3e9e4fcf
JB		 22792 else
22793 {
22794 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22795 "-- `%s'"), str);
22796 return;
22797 }
c19d1205
ZW		 22798 output_inst (str);
22799}
b99bd4ef 22800
e07e6e58 22801static void
5ee91343 22802check_pred_blocks_finished (void)
e07e6e58
NC		 22803{
22804#ifdef OBJ_ELF
22805 asection *sect;
22806
22807 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
5ee91343
AV		 22808 if (seg_info (sect)->tc_segment_info_data.current_pred.state
22809 == MANUAL_PRED_BLOCK)
e07e6e58 22810 {
5ee91343
AV		 22811 if (now_pred.type == SCALAR_PRED)
22812 as_warn (_("section '%s' finished with an open IT block."),
22813 sect->name);
22814 else
22815 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22816 sect->name);
e07e6e58
NC		 22817 }
22818#else
5ee91343
AV		 22819 if (now_pred.state == MANUAL_PRED_BLOCK)
22820 {
22821 if (now_pred.type == SCALAR_PRED)
22822 as_warn (_("file finished with an open IT block."));
22823 else
22824 as_warn (_("file finished with an open VPT/VPST block."));
22825 }
e07e6e58
NC		 22826#endif
22827}
22828
c19d1205
ZW		 22829/* Various frobbings of labels and their addresses. */
22830
22831void
22832arm_start_line_hook (void)
22833{
22834 last_label_seen = NULL;
b99bd4ef
NC		 22835}
22836
c19d1205
ZW		 22837void
22838arm_frob_label (symbolS * sym)
b99bd4ef 22839{
c19d1205 22840 last_label_seen = sym;
b99bd4ef 22841
c19d1205 22842 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 22843
c19d1205
ZW		 22844#if defined OBJ_COFF || defined OBJ_ELF
22845 ARM_SET_INTERWORK (sym, support_interwork);
22846#endif
b99bd4ef 22847
e07e6e58
NC		 22848 force_automatic_it_block_close ();
22849
5f4273c7 22850 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW		 22851 as Thumb functions. This is because these labels, whilst
22852 they exist inside Thumb code, are not the entry points for
22853 possible ARM->Thumb calls. Also, these labels can be used
22854 as part of a computed goto or switch statement. eg gcc
22855 can generate code that looks like this:
b99bd4ef 22856
c19d1205
ZW		 22857 ldr r2, [pc, .Laaa]
22858 lsl r3, r3, #2
22859 ldr r2, [r3, r2]
22860 mov pc, r2
b99bd4ef 22861
c19d1205
ZW		 22862 .Lbbb: .word .Lxxx
22863 .Lccc: .word .Lyyy
22864 ..etc...
22865 .Laaa: .word Lbbb
b99bd4ef 22866
c19d1205
ZW		 22867 The first instruction loads the address of the jump table.
22868 The second instruction converts a table index into a byte offset.
22869 The third instruction gets the jump address out of the table.
22870 The fourth instruction performs the jump.
b99bd4ef 22871
c19d1205
ZW		 22872 If the address stored at .Laaa is that of a symbol which has the
22873 Thumb_Func bit set, then the linker will arrange for this address
22874 to have the bottom bit set, which in turn would mean that the
22875 address computation performed by the third instruction would end
22876 up with the bottom bit set. Since the ARM is capable of unaligned
22877 word loads, the instruction would then load the incorrect address
22878 out of the jump table, and chaos would ensue. */
22879 if (label_is_thumb_function_name
22880 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
22881 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 22882 {
c19d1205
ZW		 22883 /* When the address of a Thumb function is taken the bottom
22884 bit of that address should be set. This will allow
22885 interworking between Arm and Thumb functions to work
22886 correctly. */
b99bd4ef 22887
c19d1205 22888 THUMB_SET_FUNC (sym, 1);
b99bd4ef 22889
c19d1205 22890 label_is_thumb_function_name = FALSE;
b99bd4ef 22891 }
07a53e5c 22892
07a53e5c 22893 dwarf2_emit_label (sym);
b99bd4ef
NC		 22894}
22895
c921be7d 22896bfd_boolean
c19d1205 22897arm_data_in_code (void)
b99bd4ef 22898{
c19d1205 22899 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 22900 {
c19d1205
ZW		 22901 *input_line_pointer = '/';
22902 input_line_pointer += 5;
22903 *input_line_pointer = 0;
c921be7d 22904 return TRUE;
b99bd4ef
NC		 22905 }
22906
c921be7d 22907 return FALSE;
b99bd4ef
NC		 22908}
22909
c19d1205
ZW		 22910char *
22911arm_canonicalize_symbol_name (char * name)
b99bd4ef 22912{
c19d1205 22913 int len;
b99bd4ef 22914
c19d1205
ZW		 22915 if (thumb_mode && (len = strlen (name)) > 5
22916 && streq (name + len - 5, "/data"))
22917 *(name + len - 5) = 0;
b99bd4ef 22918
c19d1205 22919 return name;
b99bd4ef 22920}
c19d1205
ZW		 22921\f
22922/* Table of all register names defined by default. The user can
22923 define additional names with .req. Note that all register names
22924 should appear in both upper and lowercase variants. Some registers
22925 also have mixed-case names. */
b99bd4ef 22926
dcbf9037 22927#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 22928#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 22929#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW		 22930#define REGSET(p,t) \
22931 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22932 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22933 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22934 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB		 22935#define REGSETH(p,t) \
22936 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22937 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22938 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22939 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22940#define REGSET2(p,t) \
22941 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22942 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22943 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22944 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
90ec0d68
MGD		 22945#define SPLRBANK(base,bank,t) \
22946 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22947 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22948 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22949 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22950 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22951 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
7ed4c4c5 22952
c19d1205 22953static const struct reg_entry reg_names[] =
7ed4c4c5 22954{
c19d1205
ZW		 22955 /* ARM integer registers. */
22956 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 22957
c19d1205
ZW		 22958 /* ATPCS synonyms. */
22959 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
22960 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
22961 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 22962
c19d1205
ZW		 22963 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
22964 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
22965 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 22966
c19d1205
ZW		 22967 /* Well-known aliases. */
22968 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
22969 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
22970
22971 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
22972 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
22973
1b883319
AV		 22974 /* Defining the new Zero register from ARMv8.1-M. */
22975 REGDEF(zr,15,ZR),
22976 REGDEF(ZR,15,ZR),
22977
c19d1205
ZW		 22978 /* Coprocessor numbers. */
22979 REGSET(p, CP), REGSET(P, CP),
22980
22981 /* Coprocessor register numbers. The "cr" variants are for backward
22982 compatibility. */
22983 REGSET(c, CN), REGSET(C, CN),
22984 REGSET(cr, CN), REGSET(CR, CN),
22985
90ec0d68
MGD		 22986 /* ARM banked registers. */
22987 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
22988 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
22989 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
22990 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
22991 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
22992 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
22993 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
22994
22995 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
22996 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
22997 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
22998 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
22999 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
1472d06f 23000 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
90ec0d68
MGD		 23001 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
23002 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
23003
23004 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
23005 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
23006 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
23007 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
23008 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
23009 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
23010 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
fa94de6b 23011 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
90ec0d68
MGD		 23012 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
23013
c19d1205
ZW		 23014 /* FPA registers. */
23015 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
23016 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
23017
23018 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
23019 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
23020
23021 /* VFP SP registers. */
5287ad62
JB		 23022 REGSET(s,VFS), REGSET(S,VFS),
23023 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW		 23024
23025 /* VFP DP Registers. */
5287ad62
JB		 23026 REGSET(d,VFD), REGSET(D,VFD),
23027 /* Extra Neon DP registers. */
23028 REGSETH(d,VFD), REGSETH(D,VFD),
23029
23030 /* Neon QP registers. */
23031 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW		 23032
23033 /* VFP control registers. */
23034 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
23035 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB		 23036 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
23037 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
23038 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
23039 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
40c7d507 23040 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
ba6cd17f
SD		 23041 REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC),
23042 REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
23043 REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
23044 REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
c19d1205
ZW		 23045
23046 /* Maverick DSP coprocessor registers. */
23047 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
23048 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
23049
23050 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
23051 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
23052 REGDEF(dspsc,0,DSPSC),
23053
23054 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
23055 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
23056 REGDEF(DSPSC,0,DSPSC),
23057
23058 /* iWMMXt data registers - p0, c0-15. */
23059 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
23060
23061 /* iWMMXt control registers - p1, c0-3. */
23062 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
23063 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
23064 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
23065 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
23066
23067 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23068 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
23069 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
23070 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
23071 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
23072
23073 /* XScale accumulator registers. */
23074 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
23075};
23076#undef REGDEF
23077#undef REGNUM
23078#undef REGSET
7ed4c4c5 23079
c19d1205
ZW		 23080/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23081 within psr_required_here. */
23082static const struct asm_psr psrs[] =
23083{
23084 /* Backward compatibility notation. Note that "all" is no longer
23085 truly all possible PSR bits. */
23086 {"all", PSR_c | PSR_f},
23087 {"flg", PSR_f},
23088 {"ctl", PSR_c},
23089
23090 /* Individual flags. */
23091 {"f", PSR_f},
23092 {"c", PSR_c},
23093 {"x", PSR_x},
23094 {"s", PSR_s},
59b42a0d 23095
c19d1205
ZW		 23096 /* Combinations of flags. */
23097 {"fs", PSR_f | PSR_s},
23098 {"fx", PSR_f | PSR_x},
23099 {"fc", PSR_f | PSR_c},
23100 {"sf", PSR_s | PSR_f},
23101 {"sx", PSR_s | PSR_x},
23102 {"sc", PSR_s | PSR_c},
23103 {"xf", PSR_x | PSR_f},
23104 {"xs", PSR_x | PSR_s},
23105 {"xc", PSR_x | PSR_c},
23106 {"cf", PSR_c | PSR_f},
23107 {"cs", PSR_c | PSR_s},
23108 {"cx", PSR_c | PSR_x},
23109 {"fsx", PSR_f | PSR_s | PSR_x},
23110 {"fsc", PSR_f | PSR_s | PSR_c},
23111 {"fxs", PSR_f | PSR_x | PSR_s},
23112 {"fxc", PSR_f | PSR_x | PSR_c},
23113 {"fcs", PSR_f | PSR_c | PSR_s},
23114 {"fcx", PSR_f | PSR_c | PSR_x},
23115 {"sfx", PSR_s | PSR_f | PSR_x},
23116 {"sfc", PSR_s | PSR_f | PSR_c},
23117 {"sxf", PSR_s | PSR_x | PSR_f},
23118 {"sxc", PSR_s | PSR_x | PSR_c},
23119 {"scf", PSR_s | PSR_c | PSR_f},
23120 {"scx", PSR_s | PSR_c | PSR_x},
23121 {"xfs", PSR_x | PSR_f | PSR_s},
23122 {"xfc", PSR_x | PSR_f | PSR_c},
23123 {"xsf", PSR_x | PSR_s | PSR_f},
23124 {"xsc", PSR_x | PSR_s | PSR_c},
23125 {"xcf", PSR_x | PSR_c | PSR_f},
23126 {"xcs", PSR_x | PSR_c | PSR_s},
23127 {"cfs", PSR_c | PSR_f | PSR_s},
23128 {"cfx", PSR_c | PSR_f | PSR_x},
23129 {"csf", PSR_c | PSR_s | PSR_f},
23130 {"csx", PSR_c | PSR_s | PSR_x},
23131 {"cxf", PSR_c | PSR_x | PSR_f},
23132 {"cxs", PSR_c | PSR_x | PSR_s},
23133 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
23134 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
23135 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
23136 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
23137 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
23138 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
23139 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
23140 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
23141 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
23142 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
23143 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
23144 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
23145 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
23146 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
23147 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
23148 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
23149 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
23150 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
23151 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
23152 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
23153 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
23154 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
23155 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
23156 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
23157};
23158
62b3e311
PB		 23159/* Table of V7M psr names. */
23160static const struct asm_psr v7m_psrs[] =
23161{
1a336194
TP		 23162 {"apsr", 0x0 }, {"APSR", 0x0 },
23163 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23164 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23165 {"psr", 0x3 }, {"PSR", 0x3 },
23166 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23167 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23168 {"epsr", 0x6 }, {"EPSR", 0x6 },
23169 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23170 {"msp", 0x8 }, {"MSP", 0x8 },
23171 {"psp", 0x9 }, {"PSP", 0x9 },
23172 {"msplim", 0xa }, {"MSPLIM", 0xa },
23173 {"psplim", 0xb }, {"PSPLIM", 0xb },
23174 {"primask", 0x10}, {"PRIMASK", 0x10},
23175 {"basepri", 0x11}, {"BASEPRI", 0x11},
23176 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
1a336194
TP		 23177 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23178 {"control", 0x14}, {"CONTROL", 0x14},
23179 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23180 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23181 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23182 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23183 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23184 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23185 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23186 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23187 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
62b3e311
PB		 23188};
23189
c19d1205
ZW		 23190/* Table of all shift-in-operand names. */
23191static const struct asm_shift_name shift_names [] =
b99bd4ef 23192{
c19d1205
ZW		 23193 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
23194 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
23195 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
23196 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
23197 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
f5f10c66
AV		 23198 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
23199 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
c19d1205 23200};
b99bd4ef 23201
c19d1205
ZW		 23202/* Table of all explicit relocation names. */
23203#ifdef OBJ_ELF
23204static struct reloc_entry reloc_names[] =
23205{
23206 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
23207 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
23208 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
23209 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
23210 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
23211 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
23212 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
23213 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
23214 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
23215 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6 23216 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
0855e32b
NS		 23217 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
23218 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
477330fc 23219 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
0855e32b 23220 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
477330fc 23221 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
0855e32b 23222 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
188fd7ae
CL		 23223 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
23224 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
23225 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
23226 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
23227 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
23228 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
5c5a4843
CL		 23229 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
23230 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
23231 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
23232 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
c19d1205
ZW		 23233};
23234#endif
b99bd4ef 23235
5ee91343 23236/* Table of all conditional affixes. */
c19d1205
ZW		 23237static const struct asm_cond conds[] =
23238{
23239 {"eq", 0x0},
23240 {"ne", 0x1},
23241 {"cs", 0x2}, {"hs", 0x2},
23242 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23243 {"mi", 0x4},
23244 {"pl", 0x5},
23245 {"vs", 0x6},
23246 {"vc", 0x7},
23247 {"hi", 0x8},
23248 {"ls", 0x9},
23249 {"ge", 0xa},
23250 {"lt", 0xb},
23251 {"gt", 0xc},
23252 {"le", 0xd},
23253 {"al", 0xe}
23254};
5ee91343
AV		 23255static const struct asm_cond vconds[] =
23256{
23257 {"t", 0xf},
23258 {"e", 0x10}
23259};
bfae80f2 23260
e797f7e0 23261#define UL_BARRIER(L,U,CODE,FEAT) \
823d2571
TG		 23262 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23263 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
e797f7e0 23264
62b3e311
PB		 23265static struct asm_barrier_opt barrier_opt_names[] =
23266{
e797f7e0
MGD		 23267 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
23268 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
23269 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
23270 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
23271 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
23272 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
23273 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
23274 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
23275 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
23276 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
23277 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
23278 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
23279 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
23280 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
23281 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
23282 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
62b3e311
PB		 23283};
23284
e797f7e0
MGD		 23285#undef UL_BARRIER
23286
c19d1205
ZW		 23287/* Table of ARM-format instructions. */
23288
23289/* Macros for gluing together operand strings. N.B. In all cases
23290 other than OPS0, the trailing OP_stop comes from default
23291 zero-initialization of the unspecified elements of the array. */
23292#define OPS0() { OP_stop, }
23293#define OPS1(a) { OP_##a, }
23294#define OPS2(a,b) { OP_##a,OP_##b, }
23295#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23296#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23297#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23298#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23299
5be8be5d
DG		 23300/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23301 This is useful when mixing operands for ARM and THUMB, i.e. using the
23302 MIX_ARM_THUMB_OPERANDS macro.
23303 In order to use these macros, prefix the number of operands with _
23304 e.g. _3. */
23305#define OPS_1(a) { a, }
23306#define OPS_2(a,b) { a,b, }
23307#define OPS_3(a,b,c) { a,b,c, }
23308#define OPS_4(a,b,c,d) { a,b,c,d, }
23309#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23310#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23311
c19d1205
ZW		 23312/* These macros abstract out the exact format of the mnemonic table and
23313 save some repeated characters. */
23314
23315/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23316#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 23317 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
5ee91343 23318 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW		 23319
23320/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23321 a T_MNEM_xyz enumerator. */
23322#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23323 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 23324#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23325 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW		 23326
23327/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23328 infix after the third character. */
23329#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 23330 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
5ee91343 23331 THUMB_VARIANT, do_##ae, do_##te, 0 }
088fa78e 23332#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 23333 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
5ee91343 23334 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 23335#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23336 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 23337#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23338 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 23339#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23340 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 23341#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23342 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205 23343
c19d1205 23344/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB		 23345 field is still 0xE. Many of the Thumb variants can be executed
23346 conditionally, so this is checked separately. */
c19d1205 23347#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 23348 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23349 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 23350
dd5181d5
KT		 23351/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23352 Used by mnemonics that have very minimal differences in the encoding for
23353 ARM and Thumb variants and can be handled in a common function. */
23354#define TUEc(mnem, op, top, nops, ops, en) \
23355 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23356 THUMB_VARIANT, do_##en, do_##en, 0 }
dd5181d5 23357
c19d1205
ZW		 23358/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23359 condition code field. */
23360#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 23361 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23362 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW		 23363
23364/* ARM-only variants of all the above. */
6a86118a 23365#define CE(mnem, op, nops, ops, ae) \
5ee91343 23366 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 23367
23368#define C3(mnem, op, nops, ops, ae) \
5ee91343 23369 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 23370
cf3cf39d
TP		 23371/* Thumb-only variants of TCE and TUE. */
23372#define ToC(mnem, top, nops, ops, te) \
23373 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
5ee91343 23374 do_##te, 0 }
cf3cf39d
TP		 23375
23376#define ToU(mnem, top, nops, ops, te) \
23377 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
5ee91343 23378 NULL, do_##te, 0 }
cf3cf39d 23379
4389b29a
AV		 23380/* T_MNEM_xyz enumerator variants of ToC. */
23381#define toC(mnem, top, nops, ops, te) \
23382 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
5ee91343 23383 do_##te, 0 }
4389b29a 23384
f6b2b12d
AV		 23385/* T_MNEM_xyz enumerator variants of ToU. */
23386#define toU(mnem, top, nops, ops, te) \
23387 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
5ee91343 23388 NULL, do_##te, 0 }
f6b2b12d 23389
e3cb604e
PB		 23390/* Legacy mnemonics that always have conditional infix after the third
23391 character. */
23392#define CL(mnem, op, nops, ops, ae) \
21d799b5 23393 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 23394 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
e3cb604e 23395
8f06b2d8
PB		 23396/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23397#define cCE(mnem, op, nops, ops, ae) \
5ee91343 23398 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 23399
57785aa2
AV		 23400/* mov instructions that are shared between coprocessor and MVE. */
23401#define mcCE(mnem, op, nops, ops, ae) \
23402 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23403
e3cb604e
PB		 23404/* Legacy coprocessor instructions where conditional infix and conditional
23405 suffix are ambiguous. For consistency this includes all FPA instructions,
23406 not just the potentially ambiguous ones. */
23407#define cCL(mnem, op, nops, ops, ae) \
21d799b5 23408 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 23409 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
e3cb604e
PB		 23410
23411/* Coprocessor, takes either a suffix or a position-3 infix
23412 (for an FPA corner case). */
23413#define C3E(mnem, op, nops, ops, ae) \
21d799b5 23414 { mnem, OPS##nops ops, OT_csuf_or_in3, \
5ee91343 23415 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 23416
6a86118a 23417#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC		 23418 { m1 #m2 m3, OPS##nops ops, \
23419 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
5ee91343 23420 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 23421
23422#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC		 23423 xCM_ (m1, , m2, op, nops, ops, ae), \
23424 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23425 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23426 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23427 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23428 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23429 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23430 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23431 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23432 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23433 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23434 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23435 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23436 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23437 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23438 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23439 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23440 xCM_ (m1, le, m2, op, nops, ops, ae), \
23441 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC		 23442
23443#define UE(mnem, op, nops, ops, ae) \
5ee91343 23444 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 23445
23446#define UF(mnem, op, nops, ops, ae) \
5ee91343 23447 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 23448
5287ad62
JB		 23449/* Neon data-processing. ARM versions are unconditional with cond=0xf.
23450 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23451 use the same encoding function for each. */
23452#define NUF(mnem, op, nops, ops, enc) \
23453 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
5ee91343 23454 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB		 23455
23456/* Neon data processing, version which indirects through neon_enc_tab for
23457 the various overloaded versions of opcodes. */
23458#define nUF(mnem, op, nops, ops, enc) \
21d799b5 23459 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5ee91343 23460 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB		 23461
23462/* Neon insn with conditional suffix for the ARM version, non-overloaded
23463 version. */
5ee91343 23464#define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
037e8744 23465 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5ee91343 23466 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 23467
037e8744 23468#define NCE(mnem, op, nops, ops, enc) \
5ee91343 23469 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB		 23470
23471#define NCEF(mnem, op, nops, ops, enc) \
5ee91343 23472 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
037e8744 23473
5287ad62 23474/* Neon insn with conditional suffix for the ARM version, overloaded types. */
5ee91343 23475#define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21d799b5 23476 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5ee91343 23477 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 23478
037e8744 23479#define nCE(mnem, op, nops, ops, enc) \
5ee91343 23480 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB		 23481
23482#define nCEF(mnem, op, nops, ops, enc) \
5ee91343
AV		 23483 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23484
23485/* */
23486#define mCEF(mnem, op, nops, ops, enc) \
a302e574 23487 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
5ee91343
AV		 23488 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23489
23490
23491/* nCEF but for MVE predicated instructions. */
23492#define mnCEF(mnem, op, nops, ops, enc) \
23493 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23494
23495/* nCE but for MVE predicated instructions. */
23496#define mnCE(mnem, op, nops, ops, enc) \
23497 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
037e8744 23498
5ee91343
AV		 23499/* NUF but for potentially MVE predicated instructions. */
23500#define MNUF(mnem, op, nops, ops, enc) \
23501 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23502 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23503
23504/* nUF but for potentially MVE predicated instructions. */
23505#define mnUF(mnem, op, nops, ops, enc) \
23506 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23507 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23508
23509/* ToC but for potentially MVE predicated instructions. */
23510#define mToC(mnem, top, nops, ops, te) \
23511 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23512 do_##te, 1 }
23513
23514/* NCE but for MVE predicated instructions. */
23515#define MNCE(mnem, op, nops, ops, enc) \
23516 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23517
23518/* NCEF but for MVE predicated instructions. */
23519#define MNCEF(mnem, op, nops, ops, enc) \
23520 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
c19d1205
ZW		 23521#define do_0 0
23522
c19d1205 23523static const struct asm_opcode insns[] =
bfae80f2 23524{
74db7efb
NC		 23525#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23526#define THUMB_VARIANT & arm_ext_v4t
21d799b5
NC		 23527 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
23528 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
23529 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
23530 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
23531 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
23532 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
23533 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
23534 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
23535 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
23536 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
23537 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
23538 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
23539 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
23540 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
23541 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
23542 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW		 23543
23544 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23545 for setting PSR flag bits. They are obsolete in V6 and do not
23546 have Thumb equivalents. */
21d799b5
NC		 23547 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23548 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23549 CL("tstp", 110f000, 2, (RR, SH), cmp),
23550 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23551 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23552 CL("cmpp", 150f000, 2, (RR, SH), cmp),
23553 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23554 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23555 CL("cmnp", 170f000, 2, (RR, SH), cmp),
23556
23557 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
72d98d16 23558 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
21d799b5
NC		 23559 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
23560 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
23561
23562 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG		 23563 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
23564 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
23565 OP_RRnpc),
23566 OP_ADDRGLDR),ldst, t_ldst),
23567 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC		 23568
23569 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23570 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23571 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23572 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23573 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23574 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23575
21d799b5
NC		 23576 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
23577 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 23578
c19d1205 23579 /* Pseudo ops. */
21d799b5 23580 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 23581 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 23582 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
74db7efb 23583 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
c19d1205
ZW		 23584
23585 /* Thumb-compatibility pseudo ops. */
21d799b5
NC		 23586 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
23587 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
23588 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
23589 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
23590 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
23591 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
23592 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
23593 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
23594 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
23595 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
23596 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
23597 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 23598
16a4cf17 23599 /* These may simplify to neg. */
21d799b5
NC		 23600 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
23601 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 23602
173205ca
TP		 23603#undef THUMB_VARIANT
23604#define THUMB_VARIANT & arm_ext_os
23605
23606 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
23607 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
23608
c921be7d
NC		 23609#undef THUMB_VARIANT
23610#define THUMB_VARIANT & arm_ext_v6
23611
21d799b5 23612 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW		 23613
23614 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC		 23615#undef THUMB_VARIANT
23616#define THUMB_VARIANT & arm_ext_v6t2
23617
21d799b5
NC		 23618 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23619 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23620 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 23621
5be8be5d
DG		 23622 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23623 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23624 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
23625 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 23626
21d799b5
NC		 23627 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23628 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 23629
21d799b5
NC		 23630 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23631 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW		 23632
23633 /* V1 instructions with no Thumb analogue at all. */
21d799b5 23634 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW		 23635 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
23636
23637 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
23638 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
23639 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
23640 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
23641 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
23642 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
23643 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
23644 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
23645
c921be7d
NC		 23646#undef ARM_VARIANT
23647#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23648#undef THUMB_VARIANT
23649#define THUMB_VARIANT & arm_ext_v4t
23650
21d799b5
NC		 23651 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
23652 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 23653
c921be7d
NC		 23654#undef THUMB_VARIANT
23655#define THUMB_VARIANT & arm_ext_v6t2
23656
21d799b5 23657 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW		 23658 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
23659
23660 /* Generic coprocessor instructions. */
21d799b5
NC		 23661 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23662 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23663 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23664 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23665 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23666 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
db472d6f 23667 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 23668
c921be7d
NC		 23669#undef ARM_VARIANT
23670#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23671
21d799b5 23672 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW		 23673 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
23674
c921be7d
NC		 23675#undef ARM_VARIANT
23676#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23677#undef THUMB_VARIANT
23678#define THUMB_VARIANT & arm_ext_msr
23679
d2cd1205
JB		 23680 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
23681 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
c19d1205 23682
c921be7d
NC		 23683#undef ARM_VARIANT
23684#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23685#undef THUMB_VARIANT
23686#define THUMB_VARIANT & arm_ext_v6t2
23687
21d799b5
NC		 23688 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23689 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23690 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23691 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23692 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23693 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23694 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23695 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 23696
c921be7d
NC		 23697#undef ARM_VARIANT
23698#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23699#undef THUMB_VARIANT
23700#define THUMB_VARIANT & arm_ext_v4t
23701
5be8be5d
DG		 23702 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23703 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23704 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23705 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
56c0a61f
RE		 23706 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23707 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 23708
c921be7d
NC		 23709#undef ARM_VARIANT
23710#define ARM_VARIANT & arm_ext_v4t_5
23711
c19d1205
ZW		 23712 /* ARM Architecture 4T. */
23713 /* Note: bx (and blx) are required on V5, even if the processor does
23714 not support Thumb. */
21d799b5 23715 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 23716
c921be7d
NC		 23717#undef ARM_VARIANT
23718#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23719#undef THUMB_VARIANT
23720#define THUMB_VARIANT & arm_ext_v5t
23721
c19d1205
ZW		 23722 /* Note: blx has 2 variants; the .value coded here is for
23723 BLX(2). Only this variant has conditional execution. */
21d799b5
NC		 23724 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
23725 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 23726
c921be7d
NC		 23727#undef THUMB_VARIANT
23728#define THUMB_VARIANT & arm_ext_v6t2
23729
21d799b5
NC		 23730 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
23731 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23732 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23733 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23734 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23735 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23736 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
23737 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 23738
c921be7d 23739#undef ARM_VARIANT
74db7efb
NC		 23740#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23741#undef THUMB_VARIANT
23742#define THUMB_VARIANT & arm_ext_v5exp
c921be7d 23743
21d799b5
NC		 23744 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23745 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23746 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23747 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 23748
21d799b5
NC		 23749 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23750 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 23751
21d799b5
NC		 23752 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23753 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23754 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23755 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 23756
21d799b5
NC		 23757 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23758 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23759 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23760 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 23761
21d799b5
NC		 23762 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23763 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 23764
03ee1b7f
NC		 23765 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23766 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23767 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23768 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 23769
c921be7d 23770#undef ARM_VARIANT
74db7efb
NC		 23771#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23772#undef THUMB_VARIANT
23773#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23774
21d799b5 23775 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG		 23776 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
23777 ldrd, t_ldstd),
23778 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
23779 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 23780
21d799b5
NC		 23781 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23782 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 23783
c921be7d
NC		 23784#undef ARM_VARIANT
23785#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23786
21d799b5 23787 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 23788
c921be7d
NC		 23789#undef ARM_VARIANT
23790#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23791#undef THUMB_VARIANT
23792#define THUMB_VARIANT & arm_ext_v6
23793
21d799b5
NC		 23794 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
23795 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
23796 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23797 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23798 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23799 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23800 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23801 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23802 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23803 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 23804
c921be7d 23805#undef THUMB_VARIANT
ff8646ee 23806#define THUMB_VARIANT & arm_ext_v6t2_v8m
c921be7d 23807
5be8be5d
DG		 23808 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
23809 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23810 strex, t_strex),
ff8646ee
TP		 23811#undef THUMB_VARIANT
23812#define THUMB_VARIANT & arm_ext_v6t2
23813
21d799b5
NC		 23814 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23815 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 23816
21d799b5
NC		 23817 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
23818 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 23819
9e3c6df6 23820/* ARM V6 not included in V7M. */
c921be7d
NC		 23821#undef THUMB_VARIANT
23822#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6 23823 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6 23824 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
9e3c6df6
PB		 23825 UF(rfeib, 9900a00, 1, (RRw), rfe),
23826 UF(rfeda, 8100a00, 1, (RRw), rfe),
23827 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23828 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6
RE		 23829 UF(rfefa, 8100a00, 1, (RRw), rfe),
23830 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23831 UF(rfeed, 9900a00, 1, (RRw), rfe),
9e3c6df6 23832 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
d709e4e6
RE		 23833 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
23834 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
9e3c6df6 23835 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
d709e4e6 23836 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
9e3c6df6 23837 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
d709e4e6 23838 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
9e3c6df6 23839 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
d709e4e6 23840 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
941c9cad 23841 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
c921be7d 23842
9e3c6df6
PB		 23843/* ARM V6 not included in V7M (eg. integer SIMD). */
23844#undef THUMB_VARIANT
23845#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC		 23846 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
23847 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
23848 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23849 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23850 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23851 /* Old name for QASX. */
74db7efb 23852 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 23853 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23854 /* Old name for QSAX. */
74db7efb 23855 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23856 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23857 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23858 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23859 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23860 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23861 /* Old name for SASX. */
74db7efb 23862 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23863 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23864 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23865 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23866 /* Old name for SHASX. */
21d799b5 23867 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23868 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23869 /* Old name for SHSAX. */
21d799b5
NC		 23870 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23871 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23872 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23873 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23874 /* Old name for SSAX. */
74db7efb 23875 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23876 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23877 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23878 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23879 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23880 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23881 /* Old name for UASX. */
74db7efb 23882 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23883 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23884 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23885 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23886 /* Old name for UHASX. */
21d799b5
NC		 23887 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23888 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23889 /* Old name for UHSAX. */
21d799b5
NC		 23890 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23891 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23892 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23893 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23894 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23895 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23896 /* Old name for UQASX. */
21d799b5
NC		 23897 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23898 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23899 /* Old name for UQSAX. */
21d799b5
NC		 23900 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23901 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23902 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23903 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23904 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23905 /* Old name for USAX. */
74db7efb 23906 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 23907 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23908 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23909 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23910 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23911 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23912 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23913 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23914 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23915 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23916 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23917 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23918 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23919 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23920 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23921 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23922 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23923 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23924 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23925 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23926 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23927 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23928 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23929 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23930 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23931 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23932 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23933 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23934 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC		 23935 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
23936 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
23937 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23938 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23939 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 23940
c921be7d 23941#undef ARM_VARIANT
55e8aae7 23942#define ARM_VARIANT & arm_ext_v6k_v6t2
c921be7d 23943#undef THUMB_VARIANT
55e8aae7 23944#define THUMB_VARIANT & arm_ext_v6k_v6t2
c921be7d 23945
21d799b5
NC		 23946 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
23947 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
23948 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
23949 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 23950
c921be7d
NC		 23951#undef THUMB_VARIANT
23952#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG		 23953 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
23954 ldrexd, t_ldrexd),
23955 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
23956 RRnpcb), strexd, t_strexd),
ebdca51a 23957
c921be7d 23958#undef THUMB_VARIANT
ff8646ee 23959#define THUMB_VARIANT & arm_ext_v6t2_v8m
5be8be5d
DG		 23960 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
23961 rd_rn, rd_rn),
23962 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
23963 rd_rn, rd_rn),
23964 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 23965 strex, t_strexbh),
5be8be5d 23966 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 23967 strex, t_strexbh),
21d799b5 23968 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 23969
c921be7d 23970#undef ARM_VARIANT
f4c65163 23971#define ARM_VARIANT & arm_ext_sec
74db7efb 23972#undef THUMB_VARIANT
f4c65163 23973#define THUMB_VARIANT & arm_ext_sec
c921be7d 23974
21d799b5 23975 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 23976
90ec0d68
MGD		 23977#undef ARM_VARIANT
23978#define ARM_VARIANT & arm_ext_virt
23979#undef THUMB_VARIANT
23980#define THUMB_VARIANT & arm_ext_virt
23981
23982 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
23983 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
23984
ddfded2f
MW		 23985#undef ARM_VARIANT
23986#define ARM_VARIANT & arm_ext_pan
23987#undef THUMB_VARIANT
23988#define THUMB_VARIANT & arm_ext_pan
23989
23990 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
23991
c921be7d 23992#undef ARM_VARIANT
74db7efb 23993#define ARM_VARIANT & arm_ext_v6t2
f4c65163
MGD		 23994#undef THUMB_VARIANT
23995#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23996
21d799b5
NC		 23997 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
23998 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
23999 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
24000 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 24001
21d799b5 24002 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
21d799b5 24003 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 24004
5be8be5d
DG		 24005 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24006 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24007 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24008 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 24009
91d8b670
JG		 24010#undef ARM_VARIANT
24011#define ARM_VARIANT & arm_ext_v3
24012#undef THUMB_VARIANT
24013#define THUMB_VARIANT & arm_ext_v6t2
24014
24015 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
c597cc3d
SD		 24016 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
24017 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
91d8b670
JG		 24018
24019#undef ARM_VARIANT
24020#define ARM_VARIANT & arm_ext_v6t2
ff8646ee
TP		 24021#undef THUMB_VARIANT
24022#define THUMB_VARIANT & arm_ext_v6t2_v8m
24023 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
24024 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
24025
bf3eeda7 24026 /* Thumb-only instructions. */
74db7efb 24027#undef ARM_VARIANT
bf3eeda7
NS		 24028#define ARM_VARIANT NULL
24029 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
24030 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC		 24031
24032 /* ARM does not really have an IT instruction, so always allow it.
24033 The opcode is copied from Thumb in order to allow warnings in
24034 -mimplicit-it=[never | arm] modes. */
24035#undef ARM_VARIANT
24036#define ARM_VARIANT & arm_ext_v1
ff8646ee
TP		 24037#undef THUMB_VARIANT
24038#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 24039
21d799b5
NC		 24040 TUE("it", bf08, bf08, 1, (COND), it, t_it),
24041 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
24042 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
24043 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
24044 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
24045 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
24046 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
24047 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
24048 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
24049 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
24050 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
24051 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
24052 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
24053 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
24054 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 24055 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC		 24056 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
24057 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 24058
92e90b6e 24059 /* Thumb2 only instructions. */
c921be7d
NC		 24060#undef ARM_VARIANT
24061#define ARM_VARIANT NULL
92e90b6e 24062
21d799b5
NC		 24063 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24064 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24065 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
24066 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
24067 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
24068 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 24069
eea54501
MGD		 24070 /* Hardware division instructions. */
24071#undef ARM_VARIANT
24072#define ARM_VARIANT & arm_ext_adiv
c921be7d
NC		 24073#undef THUMB_VARIANT
24074#define THUMB_VARIANT & arm_ext_div
24075
eea54501
MGD		 24076 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
24077 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
62b3e311 24078
7e806470 24079 /* ARM V6M/V7 instructions. */
c921be7d
NC		 24080#undef ARM_VARIANT
24081#define ARM_VARIANT & arm_ext_barrier
24082#undef THUMB_VARIANT
24083#define THUMB_VARIANT & arm_ext_barrier
24084
ccb84d65
JB		 24085 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
24086 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
24087 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
7e806470 24088
62b3e311 24089 /* ARM V7 instructions. */
c921be7d
NC		 24090#undef ARM_VARIANT
24091#define ARM_VARIANT & arm_ext_v7
24092#undef THUMB_VARIANT
24093#define THUMB_VARIANT & arm_ext_v7
24094
21d799b5
NC		 24095 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
24096 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 24097
74db7efb 24098#undef ARM_VARIANT
60e5ef9f 24099#define ARM_VARIANT & arm_ext_mp
74db7efb 24100#undef THUMB_VARIANT
60e5ef9f
MGD		 24101#define THUMB_VARIANT & arm_ext_mp
24102
24103 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
24104
53c4b28b
MGD		 24105 /* AArchv8 instructions. */
24106#undef ARM_VARIANT
24107#define ARM_VARIANT & arm_ext_v8
4ed7ed8d
TP		 24108
24109/* Instructions shared between armv8-a and armv8-m. */
53c4b28b 24110#undef THUMB_VARIANT
4ed7ed8d 24111#define THUMB_VARIANT & arm_ext_atomics
53c4b28b 24112
4ed7ed8d
TP		 24113 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24114 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24115 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24116 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24117 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24118 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
4b8c8c02 24119 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
4b8c8c02
RE		 24120 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
24121 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24122 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
24123 stlex, t_stlex),
4b8c8c02
RE		 24124 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
24125 stlex, t_stlex),
24126 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
24127 stlex, t_stlex),
4ed7ed8d
TP		 24128#undef THUMB_VARIANT
24129#define THUMB_VARIANT & arm_ext_v8
53c4b28b 24130
4ed7ed8d 24131 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
4ed7ed8d
TP		 24132 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
24133 ldrexd, t_ldrexd),
24134 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
24135 strexd, t_strexd),
f7dd2fb2
TC		 24136
24137/* Defined in V8 but is in undefined encoding space for earlier
24138 architectures. However earlier architectures are required to treat
24139 this instuction as a semihosting trap as well. Hence while not explicitly
24140 defined as such, it is in fact correct to define the instruction for all
24141 architectures. */
24142#undef THUMB_VARIANT
24143#define THUMB_VARIANT & arm_ext_v1
24144#undef ARM_VARIANT
24145#define ARM_VARIANT & arm_ext_v1
24146 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
24147
8884b720 24148 /* ARMv8 T32 only. */
74db7efb 24149#undef ARM_VARIANT
b79f7053
MGD		 24150#define ARM_VARIANT NULL
24151 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
24152 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
24153 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
24154
33399f07
MGD		 24155 /* FP for ARMv8. */
24156#undef ARM_VARIANT
a715796b 24157#define ARM_VARIANT & fpu_vfp_ext_armv8xd
33399f07 24158#undef THUMB_VARIANT
a715796b 24159#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
33399f07
MGD		 24160
24161 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
24162 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
24163 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
24164 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
30bdf752 24165 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
a710b305
AV		 24166 mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz),
24167 mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx),
24168 mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta),
24169 mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn),
24170 mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp),
24171 mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm),
33399f07 24172
91ff7894
MGD		 24173 /* Crypto v1 extensions. */
24174#undef ARM_VARIANT
24175#define ARM_VARIANT & fpu_crypto_ext_armv8
24176#undef THUMB_VARIANT
24177#define THUMB_VARIANT & fpu_crypto_ext_armv8
24178
24179 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
24180 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
24181 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
24182 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
48adcd8e
MGD		 24183 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
24184 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
24185 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
24186 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
24187 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
24188 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
24189 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
3c9017d2
MGD		 24190 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
24191 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
24192 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
91ff7894 24193
dd5181d5 24194#undef ARM_VARIANT
74db7efb 24195#define ARM_VARIANT & crc_ext_armv8
dd5181d5
KT		 24196#undef THUMB_VARIANT
24197#define THUMB_VARIANT & crc_ext_armv8
24198 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
24199 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
24200 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
24201 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
24202 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
24203 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
24204
105bde57
MW		 24205 /* ARMv8.2 RAS extension. */
24206#undef ARM_VARIANT
4d1464f2 24207#define ARM_VARIANT & arm_ext_ras
105bde57 24208#undef THUMB_VARIANT
4d1464f2 24209#define THUMB_VARIANT & arm_ext_ras
105bde57
MW		 24210 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
24211
49e8a725
SN		 24212#undef ARM_VARIANT
24213#define ARM_VARIANT & arm_ext_v8_3
24214#undef THUMB_VARIANT
24215#define THUMB_VARIANT & arm_ext_v8_3
24216 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
24217
c604a79a
JW		 24218#undef ARM_VARIANT
24219#define ARM_VARIANT & fpu_neon_ext_dotprod
24220#undef THUMB_VARIANT
24221#define THUMB_VARIANT & fpu_neon_ext_dotprod
24222 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
24223 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
24224
c921be7d
NC		 24225#undef ARM_VARIANT
24226#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
53c4b28b
MGD		 24227#undef THUMB_VARIANT
24228#define THUMB_VARIANT NULL
c921be7d 24229
21d799b5
NC		 24230 cCE("wfs", e200110, 1, (RR), rd),
24231 cCE("rfs", e300110, 1, (RR), rd),
24232 cCE("wfc", e400110, 1, (RR), rd),
24233 cCE("rfc", e500110, 1, (RR), rd),
24234
24235 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
24236 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
24237 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
24238 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
24239
24240 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
24241 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
24242 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
24243 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
24244
24245 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
24246 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
24247 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
24248 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
24249 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
24250 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
24251 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
24252 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
24253 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
24254 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
24255 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
24256 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
24257
24258 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
24259 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
24260 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
24261 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
24262 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
24263 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
24264 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
24265 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
24266 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
24267 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
24268 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
24269 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
24270
24271 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
24272 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
24273 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
24274 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
24275 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
24276 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
24277 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
24278 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
24279 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
24280 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
24281 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
24282 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
24283
24284 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
24285 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
24286 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
24287 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
24288 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
24289 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
24290 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
24291 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
24292 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
24293 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
24294 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
24295 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
24296
24297 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
24298 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
24299 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
24300 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
24301 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
24302 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
24303 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
24304 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
24305 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
24306 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
24307 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
24308 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
24309
24310 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
24311 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
24312 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
24313 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
24314 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
24315 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
24316 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
24317 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
24318 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
24319 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
24320 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
24321 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
24322
24323 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
24324 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
24325 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
24326 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
24327 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
24328 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
24329 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
24330 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
24331 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
24332 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
24333 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
24334 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
24335
24336 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
24337 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
24338 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
24339 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
24340 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
24341 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
24342 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
24343 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
24344 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
24345 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
24346 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
24347 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
24348
24349 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
24350 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
24351 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
24352 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
24353 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
24354 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
24355 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
24356 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
24357 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
24358 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
24359 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
24360 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
24361
24362 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
24363 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
24364 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
24365 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
24366 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
24367 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
24368 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
24369 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
24370 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
24371 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
24372 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
24373 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
24374
24375 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
24376 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
24377 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
24378 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
24379 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
24380 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
24381 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
24382 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
24383 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
24384 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
24385 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
24386 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
24387
24388 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
24389 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
24390 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
24391 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
24392 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
24393 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
24394 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
24395 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
24396 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
24397 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
24398 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
24399 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
24400
24401 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
24402 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
24403 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
24404 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
24405 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
24406 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
24407 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
24408 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
24409 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
24410 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
24411 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
24412 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
24413
24414 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
24415 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
24416 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
24417 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
24418 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
24419 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
24420 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
24421 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
24422 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
24423 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
24424 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
24425 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
24426
24427 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
24428 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
24429 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
24430 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
24431 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
24432 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
24433 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
24434 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
24435 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
24436 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
24437 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
24438 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
24439
24440 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
24441 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
24442 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
24443 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
24444 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
24445 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
24446 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
24447 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
24448 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
24449 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
24450 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
24451 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
24452
24453 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
24454 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
24455 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
24456 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
24457 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
24458 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24459 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24460 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24461 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
24462 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
24463 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
24464 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
24465
24466 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
24467 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
24468 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
24469 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
24470 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
24471 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24472 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24473 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24474 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
24475 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
24476 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
24477 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
24478
24479 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
24480 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
24481 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
24482 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
24483 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
24484 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24485 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24486 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24487 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
24488 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
24489 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
24490 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
24491
24492 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
24493 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
24494 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
24495 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
24496 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
24497 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24498 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24499 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24500 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
24501 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
24502 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
24503 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
24504
24505 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
24506 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
24507 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
24508 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
24509 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
24510 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24511 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24512 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24513 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
24514 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
24515 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
24516 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
24517
24518 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
24519 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
24520 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
24521 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
24522 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
24523 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24524 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24525 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24526 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
24527 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
24528 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
24529 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
24530
24531 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
24532 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
24533 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
24534 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
24535 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
24536 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24537 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24538 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24539 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
24540 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
24541 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
24542 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
24543
24544 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
24545 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
24546 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
24547 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
24548 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
24549 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24550 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24551 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24552 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
24553 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
24554 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
24555 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
24556
24557 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
24558 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
24559 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
24560 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
24561 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
24562 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24563 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24564 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24565 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
24566 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
24567 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
24568 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
24569
24570 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
24571 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
24572 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
24573 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
24574 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
24575 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24576 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24577 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24578 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
24579 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
24580 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
24581 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
24582
24583 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24584 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24585 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24586 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24587 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24588 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24589 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24590 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24591 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24592 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24593 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24594 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24595
24596 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24597 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24598 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24599 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24600 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24601 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24602 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24603 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24604 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24605 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24606 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24607 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24608
24609 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24610 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24611 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24612 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24613 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24614 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24615 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24616 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24617 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24618 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24619 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24620 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24621
24622 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
24623 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
24624 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
24625 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
24626
24627 cCL("flts", e000110, 2, (RF, RR), rn_rd),
24628 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
24629 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
24630 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
24631 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
24632 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
24633 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
24634 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
24635 cCL("flte", e080110, 2, (RF, RR), rn_rd),
24636 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
24637 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
24638 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 24639
c19d1205
ZW		 24640 /* The implementation of the FIX instruction is broken on some
24641 assemblers, in that it accepts a precision specifier as well as a
24642 rounding specifier, despite the fact that this is meaningless.
24643 To be more compatible, we accept it as well, though of course it
24644 does not set any bits. */
21d799b5
NC		 24645 cCE("fix", e100110, 2, (RR, RF), rd_rm),
24646 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
24647 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
24648 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
24649 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
24650 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
24651 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
24652 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
24653 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
24654 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
24655 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
24656 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
24657 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 24658
c19d1205 24659 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC		 24660#undef ARM_VARIANT
24661#define ARM_VARIANT & fpu_fpa_ext_v2
24662
21d799b5
NC		 24663 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24664 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24665 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24666 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24667 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24668 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 24669
c921be7d
NC		 24670#undef ARM_VARIANT
24671#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
ba6cd17f
SD		 24672#undef THUMB_VARIANT
24673#define THUMB_VARIANT & arm_ext_v6t2
24674 mcCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vmrs),
24675 mcCE(vmsr, ee00a10, 2, (RVC, RR), vmsr),
24676#undef THUMB_VARIANT
c921be7d 24677
c19d1205 24678 /* Moves and type conversions. */
21d799b5
NC		 24679 cCE("fmstat", ef1fa10, 0, (), noargs),
24680 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
24681 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
24682 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
24683 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24684 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
24685 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24686 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
24687 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW		 24688
24689 /* Memory operations. */
21d799b5
NC		 24690 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
24691 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
55881a11
MGD		 24692 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24693 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24694 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24695 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24696 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24697 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24698 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24699 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24700 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24701 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24702 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24703 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24704 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24705 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24706 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24707 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 24708
c19d1205 24709 /* Monadic operations. */
21d799b5
NC		 24710 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
24711 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
24712 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW		 24713
24714 /* Dyadic operations. */
21d799b5
NC		 24715 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24716 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24717 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24718 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24719 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24720 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24721 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24722 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24723 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 24724
c19d1205 24725 /* Comparisons. */
21d799b5
NC		 24726 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
24727 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
24728 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
24729 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 24730
62f3b8c8
PB		 24731 /* Double precision load/store are still present on single precision
24732 implementations. */
24733 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
24734 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
55881a11
MGD		 24735 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24736 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24737 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24738 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24739 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24740 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24741 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24742 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 24743
c921be7d
NC		 24744#undef ARM_VARIANT
24745#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24746
c19d1205 24747 /* Moves and type conversions. */
21d799b5
NC		 24748 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24749 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24750 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
24751 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
24752 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
24753 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
24754 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24755 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
24756 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24757 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24758 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24759 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 24760
c19d1205 24761 /* Monadic operations. */
21d799b5
NC		 24762 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24763 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24764 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW		 24765
24766 /* Dyadic operations. */
21d799b5
NC		 24767 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24768 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24769 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24770 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24771 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24772 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24773 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24774 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24775 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 24776
c19d1205 24777 /* Comparisons. */
21d799b5
NC		 24778 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24779 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
24780 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24781 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 24782
037e8744
JB		 24783/* Instructions which may belong to either the Neon or VFP instruction sets.
24784 Individual encoder functions perform additional architecture checks. */
c921be7d
NC		 24785#undef ARM_VARIANT
24786#define ARM_VARIANT & fpu_vfp_ext_v1xd
24787#undef THUMB_VARIANT
24788#define THUMB_VARIANT & fpu_vfp_ext_v1xd
24789
037e8744
JB		 24790 /* These mnemonics are unique to VFP. */
24791 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
24792 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC		 24793 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24794 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24795 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
037e8744
JB		 24796 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
24797 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
24798 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
24799
24800 /* Mnemonics shared by Neon and VFP. */
21d799b5 24801 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 24802
55881a11
MGD		 24803 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24804 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24805 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24806 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24807 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24808 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
037e8744 24809
dd9634d9 24810 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
e3e535bc 24811 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
dd9634d9
AV		 24812 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
24813 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
f31fef98 24814
037e8744
JB		 24815
24816 /* NOTE: All VMOV encoding is special-cased! */
037e8744
JB		 24817 NCE(vmovq, 0, 1, (VMOV), neon_mov),
24818
32c36c3c
AV		 24819#undef THUMB_VARIANT
24820/* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24821 by different feature bits. Since we are setting the Thumb guard, we can
24822 require Thumb-1 which makes it a nop guard and set the right feature bit in
24823 do_vldr_vstr (). */
24824#define THUMB_VARIANT & arm_ext_v4t
24825 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24826 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24827
9db2f6b4
RL		 24828#undef ARM_VARIANT
24829#define ARM_VARIANT & arm_ext_fp16
24830#undef THUMB_VARIANT
24831#define THUMB_VARIANT & arm_ext_fp16
24832 /* New instructions added from v8.2, allowing the extraction and insertion of
24833 the upper 16 bits of a 32-bit vector register. */
24834 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
24835 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
24836
dec41383
JW		 24837 /* New backported fma/fms instructions optional in v8.2. */
24838 NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
24839 NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
24840
c921be7d
NC		 24841#undef THUMB_VARIANT
24842#define THUMB_VARIANT & fpu_neon_ext_v1
24843#undef ARM_VARIANT
24844#define ARM_VARIANT & fpu_neon_ext_v1
24845
5287ad62
JB		 24846 /* Data processing with three registers of the same length. */
24847 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24848 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
24849 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
5287ad62 24850 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62 24851 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62
JB		 24852 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
24853 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 24854 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
5287ad62 24855 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7 24856 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
627907b7 24857 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62 24858 /* If not immediate, fall back to neon_dyadic_i64_su.
5150f0d8
AV		 24859 shl should accept I8 I16 I32 I64,
24860 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24861 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl),
24862 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl),
5287ad62 24863 /* Logic ops, types optional & ignored. */
4316f0d2 24864 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24865 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24866 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24867 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24868 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB		 24869 /* Bitfield ops, untyped. */
24870 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24871 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24872 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24873 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24874 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24875 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
cc933301 24876 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21d799b5 24877 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 24878 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 24879 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB		 24880 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24881 back to neon_dyadic_if_su. */
21d799b5
NC		 24882 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24883 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24884 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24885 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24886 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24887 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
24888 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24889 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 24890 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC		 24891 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
24892 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 24893 /* As above, D registers only. */
21d799b5
NC		 24894 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
24895 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 24896 /* Int and float variants, signedness unimportant. */
21d799b5
NC		 24897 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24898 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24899 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 24900 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC		 24901 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
24902 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB		 24903 /* vtst takes sizes 8, 16, 32. */
24904 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
24905 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
24906 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 24907 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 24908 /* VQD{R}MULH takes S16 S32. */
21d799b5 24909 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
21d799b5 24910 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB		 24911 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24912 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
24913 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24914 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB		 24915 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24916 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
24917 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24918 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB		 24919 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24920 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
24921 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24922 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
d6b4b13e 24923 /* ARM v8.1 extension. */
643afb90
MW		 24924 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
24925 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
24926 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
5287ad62
JB		 24927
24928 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 24929 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB		 24930 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
24931
24932 /* Data processing with two registers and a shift amount. */
24933 /* Right shifts, and variants with rounding.
24934 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 24935 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
5287ad62
JB		 24936 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
24937 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24938 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24939 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24940 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24941 /* Shift and insert. Sizes accepted 8 16 32 64. */
5287ad62 24942 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
5287ad62
JB		 24943 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
24944 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62
JB		 24945 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
24946 /* Right shift immediate, saturating & narrowing, with rounding variants.
24947 Types accepted S16 S32 S64 U16 U32 U64. */
24948 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24949 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24950 /* As above, unsigned. Types accepted S16 S32 S64. */
24951 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24952 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24953 /* Right shift narrowing. Types accepted I16 I32 I64. */
24954 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24955 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24956 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 24957 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 24958 /* CVT with optional immediate for fixed-point variant. */
21d799b5 24959 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 24960
4316f0d2 24961 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB		 24962
24963 /* Data processing, three registers of different lengths. */
24964 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24965 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
5287ad62
JB		 24966 /* If not scalar, fall back to neon_dyadic_long.
24967 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC		 24968 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
24969 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB		 24970 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24971 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24972 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24973 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24974 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24975 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24976 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24977 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24978 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC		 24979 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24980 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24981 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB		 24982 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24983 S16 S32 U16 U32. */
21d799b5 24984 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB		 24985
24986 /* Extract. Size 8. */
3b8d421e
PB		 24987 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
24988 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB		 24989
24990 /* Two registers, miscellaneous. */
24991 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
5287ad62 24992 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
5287ad62 24993 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
5287ad62
JB		 24994 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
24995 /* Vector replicate. Sizes 8 16 32. */
21d799b5 24996 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB		 24997 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24998 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
24999 /* VMOVN. Types I16 I32 I64. */
21d799b5 25000 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 25001 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 25002 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 25003 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 25004 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB		 25005 /* VZIP / VUZP. Sizes 8 16 32. */
25006 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
25007 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
25008 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
25009 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
25010 /* VQABS / VQNEG. Types S8 S16 S32. */
5287ad62 25011 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
5287ad62
JB		 25012 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
25013 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25014 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
25015 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
25016 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
25017 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
cc933301 25018 /* Reciprocal estimates. Types U32 F16 F32. */
5287ad62
JB		 25019 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
25020 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
25021 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
25022 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
25023 /* VCLS. Types S8 S16 S32. */
5287ad62
JB		 25024 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
25025 /* VCLZ. Types I8 I16 I32. */
5287ad62
JB		 25026 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
25027 /* VCNT. Size 8. */
25028 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
25029 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
25030 /* Two address, untyped. */
25031 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
25032 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
25033 /* VTRN. Sizes 8 16 32. */
21d799b5
NC		 25034 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
25035 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB		 25036
25037 /* Table lookup. Size 8. */
25038 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25039 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25040
c921be7d
NC		 25041#undef THUMB_VARIANT
25042#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25043#undef ARM_VARIANT
25044#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25045
5287ad62 25046 /* Neon element/structure load/store. */
21d799b5
NC		 25047 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25048 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25049 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25050 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25051 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25052 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25053 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
25054 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 25055
c921be7d 25056#undef THUMB_VARIANT
74db7efb
NC		 25057#define THUMB_VARIANT & fpu_vfp_ext_v3xd
25058#undef ARM_VARIANT
25059#define ARM_VARIANT & fpu_vfp_ext_v3xd
62f3b8c8
PB		 25060 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
25061 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25062 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25063 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25064 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25065 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25066 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25067 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25068 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25069
74db7efb 25070#undef THUMB_VARIANT
c921be7d
NC		 25071#define THUMB_VARIANT & fpu_vfp_ext_v3
25072#undef ARM_VARIANT
25073#define ARM_VARIANT & fpu_vfp_ext_v3
25074
21d799b5 25075 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 25076 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25077 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25078 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25079 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25080 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25081 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25082 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25083 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 25084
74db7efb
NC		 25085#undef ARM_VARIANT
25086#define ARM_VARIANT & fpu_vfp_ext_fma
25087#undef THUMB_VARIANT
25088#define THUMB_VARIANT & fpu_vfp_ext_fma
d58196e0 25089 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
62f3b8c8
PB		 25090 VFP FMA variant; NEON and VFP FMA always includes the NEON
25091 FMA instructions. */
d58196e0
AV		 25092 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
25093 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
25094
62f3b8c8
PB		 25095 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25096 the v form should always be used. */
25097 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25098 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25099 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25100 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25101 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25102 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25103
5287ad62 25104#undef THUMB_VARIANT
c921be7d
NC		 25105#undef ARM_VARIANT
25106#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25107
21d799b5
NC		 25108 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25109 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25110 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25111 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25112 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25113 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25114 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
25115 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 25116
c921be7d
NC		 25117#undef ARM_VARIANT
25118#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25119
21d799b5
NC		 25120 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
25121 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
25122 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
25123 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
25124 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
25125 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
25126 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
25127 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
25128 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
74db7efb
NC		 25129 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25130 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25131 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25132 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25133 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25134 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21d799b5
NC		 25135 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25136 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25137 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25138 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
25139 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
25140 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25141 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25142 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25143 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25144 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25145 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
74db7efb
NC		 25146 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
25147 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
25148 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
21d799b5
NC		 25149 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
25150 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
25151 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
25152 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
25153 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
25154 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
25155 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
25156 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
25157 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25158 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25159 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25160 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25161 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25162 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25163 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25164 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25165 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25166 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
74db7efb
NC		 25167 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25168 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25169 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25170 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 25171 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25172 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25173 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25174 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25175 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25176 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25177 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25178 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25179 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 25180 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25181 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25182 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25183 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25184 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25185 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 25186 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25187 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25188 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
25189 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
25190 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25191 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25192 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25193 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25194 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25195 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25196 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25197 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25198 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25199 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25200 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25201 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25202 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25203 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25204 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25205 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25206 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25207 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25208 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
25209 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25210 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25211 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25212 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25213 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 25214 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25215 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25216 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25217 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25218 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25219 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 25220 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25221 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25222 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25223 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25224 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25225 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25226 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25227 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25228 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25229 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25230 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
25231 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25232 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25233 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25234 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25235 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25236 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25237 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25238 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25239 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25240 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25241 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25242 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25243 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25244 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25245 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25246 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25247 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25248 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25249 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25250 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25251 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
25252 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
25253 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25254 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25255 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25256 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25257 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25258 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25259 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25260 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25261 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25262 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
25263 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
25264 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
25265 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
25266 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
25267 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
25268 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25269 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25270 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25271 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
25272 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
25273 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
25274 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
25275 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
25276 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
25277 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25278 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25279 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25280 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25281 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 25282
c921be7d
NC		 25283#undef ARM_VARIANT
25284#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25285
21d799b5
NC		 25286 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
25287 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
25288 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
25289 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
25290 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
25291 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
25292 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25293 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25294 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25295 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25296 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25297 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25298 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25299 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25300 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25301 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25302 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25303 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25304 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25305 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25306 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
25307 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25308 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25309 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25310 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25311 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25312 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25313 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25314 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25315 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25316 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25317 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25318 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25319 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25320 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25321 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25322 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25323 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25324 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25325 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25326 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25327 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25328 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25329 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25330 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25331 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25332 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25333 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25334 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25335 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25336 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25337 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25338 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25339 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25340 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25341 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25342 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 25343
c921be7d
NC		 25344#undef ARM_VARIANT
25345#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25346
21d799b5
NC		 25347 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
25348 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
25349 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
25350 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
25351 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
25352 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
25353 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
25354 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
25355 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
25356 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
25357 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
25358 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
25359 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
25360 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
74db7efb
NC		 25361 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
25362 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
25363 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
25364 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
25365 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
25366 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
25367 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
25368 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
25369 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
25370 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
21d799b5
NC		 25371 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
25372 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
25373 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
25374 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
74db7efb
NC		 25375 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
25376 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
21d799b5
NC		 25377 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
25378 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
25379 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
25380 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
74db7efb
NC		 25381 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
25382 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
25383 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
25384 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
25385 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
25386 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
21d799b5
NC		 25387 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
25388 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
74db7efb
NC		 25389 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
25390 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
21d799b5
NC		 25391 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
25392 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
25393 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
25394 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
25395 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
25396 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
25397 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
25398 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
25399 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
25400 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
25401 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
25402 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
25403 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
25404 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
25405 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
25406 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
25407 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
25408 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
25409 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
25410 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
25411 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25412 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25413 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25414 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25415 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25416 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25417 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25418 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
74db7efb
NC		 25419 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
25420 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21d799b5
NC		 25421 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
25422 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
4ed7ed8d 25423
7fadb25d
SD		 25424 /* ARMv8.5-A instructions. */
25425#undef ARM_VARIANT
25426#define ARM_VARIANT & arm_ext_sb
25427#undef THUMB_VARIANT
25428#define THUMB_VARIANT & arm_ext_sb
25429 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
25430
dad0c3bf
SD		 25431#undef ARM_VARIANT
25432#define ARM_VARIANT & arm_ext_predres
25433#undef THUMB_VARIANT
25434#define THUMB_VARIANT & arm_ext_predres
25435 CE("cfprctx", e070f93, 1, (RRnpc), rd),
25436 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
25437 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
25438
16a1fa25 25439 /* ARMv8-M instructions. */
4ed7ed8d
TP		 25440#undef ARM_VARIANT
25441#define ARM_VARIANT NULL
25442#undef THUMB_VARIANT
25443#define THUMB_VARIANT & arm_ext_v8m
cf3cf39d
TP		 25444 ToU("sg", e97fe97f, 0, (), noargs),
25445 ToC("blxns", 4784, 1, (RRnpc), t_blx),
25446 ToC("bxns", 4704, 1, (RRnpc), t_bx),
25447 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
25448 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
25449 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
25450 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
16a1fa25
TP		 25451
25452 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25453 instructions behave as nop if no VFP is present. */
25454#undef THUMB_VARIANT
25455#define THUMB_VARIANT & arm_ext_v8m_main
cf3cf39d
TP		 25456 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
25457 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
4389b29a
AV		 25458
25459 /* Armv8.1-M Mainline instructions. */
25460#undef THUMB_VARIANT
25461#define THUMB_VARIANT & arm_ext_v8_1m_main
e39c1607
SD		 25462 toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25463 toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25464 toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25465 toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25466 toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond),
25467 toU("cset", _cset, 2, (RRnpcsp, COND), t_cond),
25468 toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25469 toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25470 toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25471
4389b29a 25472 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
f6b2b12d 25473 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
f1c7f421 25474 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
65d1bc05 25475 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
f1c7f421 25476 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
60f993ce
AV		 25477
25478 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
25479 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
25480 toU("le", _le, 2, (oLR, EXP), t_loloop),
4b5a202f 25481
efd6b359 25482 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
5ee91343
AV		 25483 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
25484
25485#undef THUMB_VARIANT
25486#define THUMB_VARIANT & mve_ext
23d00a41
SD		 25487 ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
25488 ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift),
25489 ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
08132bdd
SP		 25490 ToC("uqrshll", ea51010d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
25491 ToC("sqrshrl", ea51012d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
23d00a41
SD		 25492 ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift),
25493 ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift),
25494 ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift),
25495 ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift),
25496 ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
25497 ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
25498 ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift),
25499 ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift),
25500 ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift),
25501 ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift),
1b883319
AV		 25502
25503 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25504 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25505 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25506 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25507 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25508 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25509 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25510 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25511 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25512 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25513 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25514 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25515 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25516 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25517 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25518
5ee91343
AV		 25519 ToC("vpst", fe710f4d, 0, (), mve_vpt),
25520 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
25521 ToC("vpste", fe718f4d, 0, (), mve_vpt),
25522 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
25523 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
25524 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
25525 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
25526 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
25527 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
25528 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
25529 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
25530 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
25531 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
25532 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
25533 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
25534
a302e574 25535 /* MVE and MVE FP only. */
7df54120 25536 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
efd0b310 25537 mCEF(vctp, _vctp, 1, (RRnpc), mve_vctp),
c2dafc2a
AV		 25538 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
25539 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
25540 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
25541 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
886e1c73 25542 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
a302e574
AV		 25543 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
25544 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25545 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25546 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25547 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25548 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25549 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25550 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25551 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25552 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25553 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25554
35c228db
AV		 25555 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25556 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25557 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25558 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25559 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25560 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25561 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25562 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25563 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25564 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25565 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25566 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
f5f10c66
AV		 25567 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25568 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25569 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25570 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25571 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25572 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25573 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25574 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
35c228db 25575
57785aa2
AV		 25576 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
25577 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
c2dafc2a 25578 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
26c1e780
AV		 25579 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
25580 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
25581 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
25582 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
b409bdb6
AV		 25583 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
25584 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
25585 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
25586 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
935295b5
AV		 25587 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
25588 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
13ccd4c0
AV		 25589 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
25590 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
25591 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
25592 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
57785aa2 25593
93925576
AV		 25594 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25595 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25596 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25597 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25598 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25599 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25600 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25601 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25602 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25603 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25604 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25605 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25606 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25607 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25608 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25609 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25610 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25611 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25612 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25613 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25614
2d78f95b
AV		 25615 mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
25616 mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
25617 mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
3063888e
AV		 25618 mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
25619 mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
2d78f95b 25620
8b8b22a4
AV		 25621 mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25622 mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25623 mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25624 mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25625 mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25626 mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25627 mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25628 mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
42b16635
AV		 25629 mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25630 mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25631 mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
35d1cfc2
AV		 25632 mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
25633 mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
1be7aba3
AV		 25634 mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn),
25635 mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn),
25636 mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
25637 mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
8b8b22a4 25638
4aa88b50
AV		 25639 mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25640 mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25641 mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25642 mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25643 mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25644 mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25645 mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25646 mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25647 mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25648 mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25649 mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25650 mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25651
acca5630
AV		 25652 mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc),
25653 mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll),
25654 mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll),
25655
1f6234a3
AV		 25656 toU("dlstp", _dlstp, 2, (LR, RR), t_loloop),
25657 toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop),
25658 toU("letp", _letp, 2, (LR, EXP), t_loloop),
25659 toU("lctp", _lctp, 0, (), t_loloop),
25660
5d281bf0
AV		 25661#undef THUMB_VARIANT
25662#define THUMB_VARIANT & mve_fp_ext
25663 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
f30ee27c 25664 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
935295b5
AV		 25665 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
25666 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
8cd78170
AV		 25667 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
25668 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
25669 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
25670 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
5d281bf0 25671
5ee91343 25672#undef ARM_VARIANT
57785aa2 25673#define ARM_VARIANT & fpu_vfp_ext_v1
5ee91343
AV		 25674#undef THUMB_VARIANT
25675#define THUMB_VARIANT & arm_ext_v6t2
a8465a06
AV		 25676 mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
25677 mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
5ee91343 25678
57785aa2
AV		 25679 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25680
25681#undef ARM_VARIANT
25682#define ARM_VARIANT & fpu_vfp_ext_v1xd
25683
25684 MNCE(vmov, 0, 1, (VMOV), neon_mov),
25685 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
25686 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
25687 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
25688
886e1c73
AV		 25689 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
25690 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
25691 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
5ee91343 25692
485dee97
AV		 25693 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25694 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25695
57785aa2
AV		 25696 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
25697 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
25698
1b883319
AV		 25699 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25700 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25701
57785aa2
AV		 25702#undef ARM_VARIANT
25703#define ARM_VARIANT & fpu_vfp_ext_v2
25704
25705 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
25706 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
25707 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
25708 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
25709
dd9634d9
AV		 25710#undef ARM_VARIANT
25711#define ARM_VARIANT & fpu_vfp_ext_armv8xd
25712 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
25713 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
25714 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
25715 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
935295b5
AV		 25716 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
25717 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
dd9634d9
AV		 25718
25719#undef ARM_VARIANT
5ee91343 25720#define ARM_VARIANT & fpu_neon_ext_v1
f601a00c 25721 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
5ee91343
AV		 25722 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
25723 mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
25724 mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
f601a00c
AV		 25725 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25726 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25727 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25728 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25729 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
f30ee27c
AV		 25730 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
25731 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
b409bdb6 25732 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
7df54120
AV		 25733 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
25734 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
25735 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
935295b5
AV		 25736 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
25737 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
a8465a06
AV		 25738 MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
25739 MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
1a186d29
AV		 25740 mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
25741 MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
25742 MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
42b16635
AV		 25743 mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
25744 mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
25745 mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
1be7aba3
AV		 25746 MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
25747 MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
4401c241
AV		 25748 MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25749 MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25750 MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli),
25751 MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
25752 MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev),
25753 MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev),
25754 MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev),
5150f0d8
AV		 25755 mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl),
25756 mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl),
25757 MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm),
5d281bf0
AV		 25758
25759#undef ARM_VARIANT
25760#define ARM_VARIANT & arm_ext_v8_3
25761#undef THUMB_VARIANT
25762#define THUMB_VARIANT & arm_ext_v6t2_v8m
25763 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
25764 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
c19d1205
ZW		 25765};
25766#undef ARM_VARIANT
25767#undef THUMB_VARIANT
25768#undef TCE
c19d1205
ZW		 25769#undef TUE
25770#undef TUF
25771#undef TCC
8f06b2d8 25772#undef cCE
e3cb604e
PB		 25773#undef cCL
25774#undef C3E
4389b29a 25775#undef C3
c19d1205
ZW		 25776#undef CE
25777#undef CM
4389b29a 25778#undef CL
c19d1205
ZW		 25779#undef UE
25780#undef UF
25781#undef UT
5287ad62
JB		 25782#undef NUF
25783#undef nUF
25784#undef NCE
25785#undef nCE
c19d1205
ZW		 25786#undef OPS0
25787#undef OPS1
25788#undef OPS2
25789#undef OPS3
25790#undef OPS4
25791#undef OPS5
25792#undef OPS6
25793#undef do_0
4389b29a
AV		 25794#undef ToC
25795#undef toC
25796#undef ToU
f6b2b12d 25797#undef toU
c19d1205
ZW		 25798\f
25799/* MD interface: bits in the object file. */
bfae80f2 25800
c19d1205
ZW		 25801/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25802 for use in the a.out file, and stores them in the array pointed to by buf.
25803 This knows about the endian-ness of the target machine and does
25804 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25805 2 (short) and 4 (long) Floating numbers are put out as a series of
25806 LITTLENUMS (shorts, here at least). */
b99bd4ef 25807
c19d1205
ZW		 25808void
25809md_number_to_chars (char * buf, valueT val, int n)
25810{
25811 if (target_big_endian)
25812 number_to_chars_bigendian (buf, val, n);
25813 else
25814 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE		 25815}
25816
c19d1205
ZW		 25817static valueT
25818md_chars_to_number (char * buf, int n)
bfae80f2 25819{
c19d1205
ZW		 25820 valueT result = 0;
25821 unsigned char * where = (unsigned char *) buf;
bfae80f2 25822
c19d1205 25823 if (target_big_endian)
b99bd4ef 25824 {
c19d1205
ZW		 25825 while (n--)
25826 {
25827 result <<= 8;
25828 result |= (*where++ & 255);
25829 }
b99bd4ef 25830 }
c19d1205 25831 else
b99bd4ef 25832 {
c19d1205
ZW		 25833 while (n--)
25834 {
25835 result <<= 8;
25836 result |= (where[n] & 255);
25837 }
bfae80f2 25838 }
b99bd4ef 25839
c19d1205 25840 return result;
bfae80f2 25841}
b99bd4ef 25842
c19d1205 25843/* MD interface: Sections. */
b99bd4ef 25844
fa94de6b
RM		 25845/* Calculate the maximum variable size (i.e., excluding fr_fix)
25846 that an rs_machine_dependent frag may reach. */
25847
25848unsigned int
25849arm_frag_max_var (fragS *fragp)
25850{
25851 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25852 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25853
25854 Note that we generate relaxable instructions even for cases that don't
25855 really need it, like an immediate that's a trivial constant. So we're
25856 overestimating the instruction size for some of those cases. Rather
25857 than putting more intelligence here, it would probably be better to
25858 avoid generating a relaxation frag in the first place when it can be
25859 determined up front that a short instruction will suffice. */
25860
25861 gas_assert (fragp->fr_type == rs_machine_dependent);
25862 return INSN_SIZE;
25863}
25864
0110f2b8
PB		 25865/* Estimate the size of a frag before relaxing. Assume everything fits in
25866 2 bytes. */
25867
c19d1205 25868int
0110f2b8 25869md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW		 25870 segT segtype ATTRIBUTE_UNUSED)
25871{
0110f2b8
PB		 25872 fragp->fr_var = 2;
25873 return 2;
25874}
25875
25876/* Convert a machine dependent frag. */
25877
25878void
25879md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
25880{
25881 unsigned long insn;
25882 unsigned long old_op;
25883 char *buf;
25884 expressionS exp;
25885 fixS *fixp;
25886 int reloc_type;
25887 int pc_rel;
25888 int opcode;
25889
25890 buf = fragp->fr_literal + fragp->fr_fix;
25891
25892 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC		 25893 if (fragp->fr_symbol)
25894 {
0110f2b8
PB		 25895 exp.X_op = O_symbol;
25896 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC		 25897 }
25898 else
25899 {
0110f2b8 25900 exp.X_op = O_constant;
5f4273c7 25901 }
0110f2b8
PB		 25902 exp.X_add_number = fragp->fr_offset;
25903 opcode = fragp->fr_subtype;
25904 switch (opcode)
25905 {
25906 case T_MNEM_ldr_pc:
25907 case T_MNEM_ldr_pc2:
25908 case T_MNEM_ldr_sp:
25909 case T_MNEM_str_sp:
25910 case T_MNEM_ldr:
25911 case T_MNEM_ldrb:
25912 case T_MNEM_ldrh:
25913 case T_MNEM_str:
25914 case T_MNEM_strb:
25915 case T_MNEM_strh:
25916 if (fragp->fr_var == 4)
25917 {
5f4273c7 25918 insn = THUMB_OP32 (opcode);
0110f2b8
PB		 25919 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
25920 {
25921 insn |= (old_op & 0x700) << 4;
25922 }
25923 else
25924 {
25925 insn |= (old_op & 7) << 12;
25926 insn |= (old_op & 0x38) << 13;
25927 }
25928 insn |= 0x00000c00;
25929 put_thumb32_insn (buf, insn);
25930 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
25931 }
25932 else
25933 {
25934 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
25935 }
25936 pc_rel = (opcode == T_MNEM_ldr_pc2);
25937 break;
25938 case T_MNEM_adr:
25939 if (fragp->fr_var == 4)
25940 {
25941 insn = THUMB_OP32 (opcode);
25942 insn |= (old_op & 0xf0) << 4;
25943 put_thumb32_insn (buf, insn);
25944 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
25945 }
25946 else
25947 {
25948 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25949 exp.X_add_number -= 4;
25950 }
25951 pc_rel = 1;
25952 break;
25953 case T_MNEM_mov:
25954 case T_MNEM_movs:
25955 case T_MNEM_cmp:
25956 case T_MNEM_cmn:
25957 if (fragp->fr_var == 4)
25958 {
25959 int r0off = (opcode == T_MNEM_mov
25960 || opcode == T_MNEM_movs) ? 0 : 8;
25961 insn = THUMB_OP32 (opcode);
25962 insn = (insn & 0xe1ffffff) | 0x10000000;
25963 insn |= (old_op & 0x700) << r0off;
25964 put_thumb32_insn (buf, insn);
25965 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
25966 }
25967 else
25968 {
25969 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
25970 }
25971 pc_rel = 0;
25972 break;
25973 case T_MNEM_b:
25974 if (fragp->fr_var == 4)
25975 {
25976 insn = THUMB_OP32(opcode);
25977 put_thumb32_insn (buf, insn);
25978 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
25979 }
25980 else
25981 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
25982 pc_rel = 1;
25983 break;
25984 case T_MNEM_bcond:
25985 if (fragp->fr_var == 4)
25986 {
25987 insn = THUMB_OP32(opcode);
25988 insn |= (old_op & 0xf00) << 14;
25989 put_thumb32_insn (buf, insn);
25990 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
25991 }
25992 else
25993 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
25994 pc_rel = 1;
25995 break;
25996 case T_MNEM_add_sp:
25997 case T_MNEM_add_pc:
25998 case T_MNEM_inc_sp:
25999 case T_MNEM_dec_sp:
26000 if (fragp->fr_var == 4)
26001 {
26002 /* ??? Choose between add and addw. */
26003 insn = THUMB_OP32 (opcode);
26004 insn |= (old_op & 0xf0) << 4;
26005 put_thumb32_insn (buf, insn);
16805f35
PB		 26006 if (opcode == T_MNEM_add_pc)
26007 reloc_type = BFD_RELOC_ARM_T32_IMM12;
26008 else
26009 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB		 26010 }
26011 else
26012 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26013 pc_rel = 0;
26014 break;
26015
26016 case T_MNEM_addi:
26017 case T_MNEM_addis:
26018 case T_MNEM_subi:
26019 case T_MNEM_subis:
26020 if (fragp->fr_var == 4)
26021 {
26022 insn = THUMB_OP32 (opcode);
26023 insn |= (old_op & 0xf0) << 4;
26024 insn |= (old_op & 0xf) << 16;
26025 put_thumb32_insn (buf, insn);
16805f35
PB		 26026 if (insn & (1 << 20))
26027 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
26028 else
26029 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB		 26030 }
26031 else
26032 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26033 pc_rel = 0;
26034 break;
26035 default:
5f4273c7 26036 abort ();
0110f2b8
PB		 26037 }
26038 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 26039 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB		 26040 fixp->fx_file = fragp->fr_file;
26041 fixp->fx_line = fragp->fr_line;
26042 fragp->fr_fix += fragp->fr_var;
3cfdb781
TG		 26043
26044 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26045 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
26046 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
26047 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
0110f2b8
PB		 26048}
26049
26050/* Return the size of a relaxable immediate operand instruction.
26051 SHIFT and SIZE specify the form of the allowable immediate. */
26052static int
26053relax_immediate (fragS *fragp, int size, int shift)
26054{
26055 offsetT offset;
26056 offsetT mask;
26057 offsetT low;
26058
26059 /* ??? Should be able to do better than this. */
26060 if (fragp->fr_symbol)
26061 return 4;
26062
26063 low = (1 << shift) - 1;
26064 mask = (1 << (shift + size)) - (1 << shift);
26065 offset = fragp->fr_offset;
26066 /* Force misaligned offsets to 32-bit variant. */
26067 if (offset & low)
5e77afaa 26068 return 4;
0110f2b8
PB		 26069 if (offset & ~mask)
26070 return 4;
26071 return 2;
26072}
26073
5e77afaa
PB		 26074/* Get the address of a symbol during relaxation. */
26075static addressT
5f4273c7 26076relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB		 26077{
26078 fragS *sym_frag;
26079 addressT addr;
26080 symbolS *sym;
26081
26082 sym = fragp->fr_symbol;
26083 sym_frag = symbol_get_frag (sym);
26084 know (S_GET_SEGMENT (sym) != absolute_section
26085 || sym_frag == &zero_address_frag);
26086 addr = S_GET_VALUE (sym) + fragp->fr_offset;
26087
26088 /* If frag has yet to be reached on this pass, assume it will
26089 move by STRETCH just as we did. If this is not so, it will
26090 be because some frag between grows, and that will force
26091 another pass. */
26092
26093 if (stretch != 0
26094 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB		 26095 {
26096 fragS *f;
26097
26098 /* Adjust stretch for any alignment frag. Note that if have
26099 been expanding the earlier code, the symbol may be
26100 defined in what appears to be an earlier frag. FIXME:
26101 This doesn't handle the fr_subtype field, which specifies
26102 a maximum number of bytes to skip when doing an
26103 alignment. */
26104 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
26105 {
26106 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
26107 {
26108 if (stretch < 0)
26109 stretch = - ((- stretch)
26110 & ~ ((1 << (int) f->fr_offset) - 1));
26111 else
26112 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
26113 if (stretch == 0)
26114 break;
26115 }
26116 }
26117 if (f != NULL)
26118 addr += stretch;
26119 }
5e77afaa
PB		 26120
26121 return addr;
26122}
26123
0110f2b8
PB		 26124/* Return the size of a relaxable adr pseudo-instruction or PC-relative
26125 load. */
26126static int
5e77afaa 26127relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB		 26128{
26129 addressT addr;
26130 offsetT val;
26131
26132 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC		 26133 if (fragp->fr_symbol == NULL
26134 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 26135 || sec != S_GET_SEGMENT (fragp->fr_symbol)
26136 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 26137 return 4;
26138
5f4273c7 26139 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 26140 addr = fragp->fr_address + fragp->fr_fix;
26141 addr = (addr + 4) & ~3;
5e77afaa 26142 /* Force misaligned targets to 32-bit variant. */
0110f2b8 26143 if (val & 3)
5e77afaa 26144 return 4;
0110f2b8
PB		 26145 val -= addr;
26146 if (val < 0 || val > 1020)
26147 return 4;
26148 return 2;
26149}
26150
26151/* Return the size of a relaxable add/sub immediate instruction. */
26152static int
26153relax_addsub (fragS *fragp, asection *sec)
26154{
26155 char *buf;
26156 int op;
26157
26158 buf = fragp->fr_literal + fragp->fr_fix;
26159 op = bfd_get_16(sec->owner, buf);
26160 if ((op & 0xf) == ((op >> 4) & 0xf))
26161 return relax_immediate (fragp, 8, 0);
26162 else
26163 return relax_immediate (fragp, 3, 0);
26164}
26165
e83a675f
RE		 26166/* Return TRUE iff the definition of symbol S could be pre-empted
26167 (overridden) at link or load time. */
26168static bfd_boolean
26169symbol_preemptible (symbolS *s)
26170{
26171 /* Weak symbols can always be pre-empted. */
26172 if (S_IS_WEAK (s))
26173 return TRUE;
26174
26175 /* Non-global symbols cannot be pre-empted. */
26176 if (! S_IS_EXTERNAL (s))
26177 return FALSE;
26178
26179#ifdef OBJ_ELF
26180 /* In ELF, a global symbol can be marked protected, or private. In that
26181 case it can't be pre-empted (other definitions in the same link unit
26182 would violate the ODR). */
26183 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
26184 return FALSE;
26185#endif
26186
26187 /* Other global symbols might be pre-empted. */
26188 return TRUE;
26189}
0110f2b8
PB		 26190
26191/* Return the size of a relaxable branch instruction. BITS is the
26192 size of the offset field in the narrow instruction. */
26193
26194static int
5e77afaa 26195relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB		 26196{
26197 addressT addr;
26198 offsetT val;
26199 offsetT limit;
26200
26201 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 26202 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 26203 || sec != S_GET_SEGMENT (fragp->fr_symbol)
26204 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 26205 return 4;
26206
267bf995 26207#ifdef OBJ_ELF
e83a675f 26208 /* A branch to a function in ARM state will require interworking. */
267bf995
RR		 26209 if (S_IS_DEFINED (fragp->fr_symbol)
26210 && ARM_IS_FUNC (fragp->fr_symbol))
26211 return 4;
e83a675f 26212#endif
0d9b4b55 26213
e83a675f 26214 if (symbol_preemptible (fragp->fr_symbol))
0d9b4b55 26215 return 4;
267bf995 26216
5f4273c7 26217 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 26218 addr = fragp->fr_address + fragp->fr_fix + 4;
26219 val -= addr;
26220
26221 /* Offset is a signed value *2 */
26222 limit = 1 << bits;
26223 if (val >= limit || val < -limit)
26224 return 4;
26225 return 2;
26226}
26227
26228
26229/* Relax a machine dependent frag. This returns the amount by which
26230 the current size of the frag should change. */
26231
26232int
5e77afaa 26233arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB		 26234{
26235 int oldsize;
26236 int newsize;
26237
26238 oldsize = fragp->fr_var;
26239 switch (fragp->fr_subtype)
26240 {
26241 case T_MNEM_ldr_pc2:
5f4273c7 26242 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 26243 break;
26244 case T_MNEM_ldr_pc:
26245 case T_MNEM_ldr_sp:
26246 case T_MNEM_str_sp:
5f4273c7 26247 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB		 26248 break;
26249 case T_MNEM_ldr:
26250 case T_MNEM_str:
5f4273c7 26251 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB		 26252 break;
26253 case T_MNEM_ldrh:
26254 case T_MNEM_strh:
5f4273c7 26255 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB		 26256 break;
26257 case T_MNEM_ldrb:
26258 case T_MNEM_strb:
5f4273c7 26259 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB		 26260 break;
26261 case T_MNEM_adr:
5f4273c7 26262 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 26263 break;
26264 case T_MNEM_mov:
26265 case T_MNEM_movs:
26266 case T_MNEM_cmp:
26267 case T_MNEM_cmn:
5f4273c7 26268 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB		 26269 break;
26270 case T_MNEM_b:
5f4273c7 26271 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB		 26272 break;
26273 case T_MNEM_bcond:
5f4273c7 26274 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB		 26275 break;
26276 case T_MNEM_add_sp:
26277 case T_MNEM_add_pc:
26278 newsize = relax_immediate (fragp, 8, 2);
26279 break;
26280 case T_MNEM_inc_sp:
26281 case T_MNEM_dec_sp:
26282 newsize = relax_immediate (fragp, 7, 2);
26283 break;
26284 case T_MNEM_addi:
26285 case T_MNEM_addis:
26286 case T_MNEM_subi:
26287 case T_MNEM_subis:
26288 newsize = relax_addsub (fragp, sec);
26289 break;
26290 default:
5f4273c7 26291 abort ();
0110f2b8 26292 }
5e77afaa
PB		 26293
26294 fragp->fr_var = newsize;
26295 /* Freeze wide instructions that are at or before the same location as
26296 in the previous pass. This avoids infinite loops.
5f4273c7
NC		 26297 Don't freeze them unconditionally because targets may be artificially
26298 misaligned by the expansion of preceding frags. */
5e77afaa 26299 if (stretch <= 0 && newsize > 2)
0110f2b8 26300 {
0110f2b8 26301 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 26302 frag_wane (fragp);
0110f2b8 26303 }
5e77afaa 26304
0110f2b8 26305 return newsize - oldsize;
c19d1205 26306}
b99bd4ef 26307
c19d1205 26308/* Round up a section size to the appropriate boundary. */
b99bd4ef 26309
c19d1205
ZW		 26310valueT
26311md_section_align (segT segment ATTRIBUTE_UNUSED,
26312 valueT size)
26313{
6844c0cc 26314 return size;
bfae80f2 26315}
b99bd4ef 26316
c19d1205
ZW		 26317/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26318 of an rs_align_code fragment. */
26319
26320void
26321arm_handle_align (fragS * fragP)
bfae80f2 26322{
d9235011 26323 static unsigned char const arm_noop[2][2][4] =
e7495e45
NS		 26324 {
26325 { /* ARMv1 */
26326 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26327 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26328 },
26329 { /* ARMv6k */
26330 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26331 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26332 },
26333 };
d9235011 26334 static unsigned char const thumb_noop[2][2][2] =
e7495e45
NS		 26335 {
26336 { /* Thumb-1 */
26337 {0xc0, 0x46}, /* LE */
26338 {0x46, 0xc0}, /* BE */
26339 },
26340 { /* Thumb-2 */
26341 {0x00, 0xbf}, /* LE */
26342 {0xbf, 0x00} /* BE */
26343 }
26344 };
d9235011 26345 static unsigned char const wide_thumb_noop[2][4] =
e7495e45
NS		 26346 { /* Wide Thumb-2 */
26347 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26348 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26349 };
c921be7d 26350
e7495e45 26351 unsigned bytes, fix, noop_size;
c19d1205 26352 char * p;
d9235011
TS		 26353 const unsigned char * noop;
26354 const unsigned char *narrow_noop = NULL;
cd000bff
DJ		 26355#ifdef OBJ_ELF
26356 enum mstate state;
26357#endif
bfae80f2 26358
c19d1205 26359 if (fragP->fr_type != rs_align_code)
bfae80f2
RE		 26360 return;
26361
c19d1205
ZW		 26362 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
26363 p = fragP->fr_literal + fragP->fr_fix;
26364 fix = 0;
bfae80f2 26365
c19d1205
ZW		 26366 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
26367 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 26368
cd000bff 26369 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 26370
cd000bff 26371 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 26372 {
7f78eb34
JW		 26373 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
26374 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
e7495e45
NS		 26375 {
26376 narrow_noop = thumb_noop[1][target_big_endian];
26377 noop = wide_thumb_noop[target_big_endian];
26378 }
c19d1205 26379 else
e7495e45
NS		 26380 noop = thumb_noop[0][target_big_endian];
26381 noop_size = 2;
cd000bff
DJ		 26382#ifdef OBJ_ELF
26383 state = MAP_THUMB;
26384#endif
7ed4c4c5
NC		 26385 }
26386 else
26387 {
7f78eb34
JW		 26388 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
26389 ? selected_cpu : arm_arch_none,
26390 arm_ext_v6k) != 0]
e7495e45
NS		 26391 [target_big_endian];
26392 noop_size = 4;
cd000bff
DJ		 26393#ifdef OBJ_ELF
26394 state = MAP_ARM;
26395#endif
7ed4c4c5 26396 }
c921be7d 26397
e7495e45 26398 fragP->fr_var = noop_size;
c921be7d 26399
c19d1205 26400 if (bytes & (noop_size - 1))
7ed4c4c5 26401 {
c19d1205 26402 fix = bytes & (noop_size - 1);
cd000bff
DJ		 26403#ifdef OBJ_ELF
26404 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
26405#endif
c19d1205
ZW		 26406 memset (p, 0, fix);
26407 p += fix;
26408 bytes -= fix;
a737bd4d 26409 }
a737bd4d 26410
e7495e45
NS		 26411 if (narrow_noop)
26412 {
26413 if (bytes & noop_size)
26414 {
26415 /* Insert a narrow noop. */
26416 memcpy (p, narrow_noop, noop_size);
26417 p += noop_size;
26418 bytes -= noop_size;
26419 fix += noop_size;
26420 }
26421
26422 /* Use wide noops for the remainder */
26423 noop_size = 4;
26424 }
26425
c19d1205 26426 while (bytes >= noop_size)
a737bd4d 26427 {
c19d1205
ZW		 26428 memcpy (p, noop, noop_size);
26429 p += noop_size;
26430 bytes -= noop_size;
26431 fix += noop_size;
a737bd4d
NC		 26432 }
26433
c19d1205 26434 fragP->fr_fix += fix;
a737bd4d
NC		 26435}
26436
c19d1205
ZW		 26437/* Called from md_do_align. Used to create an alignment
26438 frag in a code section. */
26439
26440void
26441arm_frag_align_code (int n, int max)
bfae80f2 26442{
c19d1205 26443 char * p;
7ed4c4c5 26444
c19d1205 26445 /* We assume that there will never be a requirement
6ec8e702 26446 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 26447 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC		 26448 {
26449 char err_msg[128];
26450
fa94de6b 26451 sprintf (err_msg,
477330fc
RM		 26452 _("alignments greater than %d bytes not supported in .text sections."),
26453 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 26454 as_fatal ("%s", err_msg);
6ec8e702 26455 }
bfae80f2 26456
c19d1205
ZW		 26457 p = frag_var (rs_align_code,
26458 MAX_MEM_FOR_RS_ALIGN_CODE,
26459 1,
26460 (relax_substateT) max,
26461 (symbolS *) NULL,
26462 (offsetT) n,
26463 (char *) NULL);
26464 *p = 0;
26465}
bfae80f2 26466
8dc2430f
NC		 26467/* Perform target specific initialisation of a frag.
26468 Note - despite the name this initialisation is not done when the frag
26469 is created, but only when its type is assigned. A frag can be created
26470 and used a long time before its type is set, so beware of assuming that
33eaf5de 26471 this initialisation is performed first. */
bfae80f2 26472
cd000bff
DJ		 26473#ifndef OBJ_ELF
26474void
26475arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
26476{
26477 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 26478 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ		 26479}
26480
26481#else /* OBJ_ELF is defined. */
c19d1205 26482void
cd000bff 26483arm_init_frag (fragS * fragP, int max_chars)
c19d1205 26484{
e8d84ca1 26485 bfd_boolean frag_thumb_mode;
b968d18a 26486
8dc2430f
NC		 26487 /* If the current ARM vs THUMB mode has not already
26488 been recorded into this frag then do so now. */
cd000bff 26489 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
b968d18a
JW		 26490 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
26491
e8d84ca1
NC		 26492 /* PR 21809: Do not set a mapping state for debug sections
26493 - it just confuses other tools. */
26494 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
26495 return;
26496
b968d18a 26497 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
cd000bff 26498
f9c1b181
RL		 26499 /* Record a mapping symbol for alignment frags. We will delete this
26500 later if the alignment ends up empty. */
26501 switch (fragP->fr_type)
26502 {
26503 case rs_align:
26504 case rs_align_test:
26505 case rs_fill:
26506 mapping_state_2 (MAP_DATA, max_chars);
26507 break;
26508 case rs_align_code:
b968d18a 26509 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
f9c1b181
RL		 26510 break;
26511 default:
26512 break;
cd000bff 26513 }
bfae80f2
RE		 26514}
26515
c19d1205
ZW		 26516/* When we change sections we need to issue a new mapping symbol. */
26517
26518void
26519arm_elf_change_section (void)
bfae80f2 26520{
c19d1205
ZW		 26521 /* Link an unlinked unwind index table section to the .text section. */
26522 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
26523 && elf_linked_to_section (now_seg) == NULL)
26524 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE		 26525}
26526
c19d1205
ZW		 26527int
26528arm_elf_section_type (const char * str, size_t len)
e45d0630 26529{
c19d1205
ZW		 26530 if (len == 5 && strncmp (str, "exidx", 5) == 0)
26531 return SHT_ARM_EXIDX;
e45d0630 26532
c19d1205
ZW		 26533 return -1;
26534}
26535\f
26536/* Code to deal with unwinding tables. */
e45d0630 26537
c19d1205 26538static void add_unwind_adjustsp (offsetT);
e45d0630 26539
5f4273c7 26540/* Generate any deferred unwind frame offset. */
e45d0630 26541
bfae80f2 26542static void
c19d1205 26543flush_pending_unwind (void)
bfae80f2 26544{
c19d1205 26545 offsetT offset;
bfae80f2 26546
c19d1205
ZW		 26547 offset = unwind.pending_offset;
26548 unwind.pending_offset = 0;
26549 if (offset != 0)
26550 add_unwind_adjustsp (offset);
bfae80f2
RE		 26551}
26552
c19d1205
ZW		 26553/* Add an opcode to this list for this function. Two-byte opcodes should
26554 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26555 order. */
26556
bfae80f2 26557static void
c19d1205 26558add_unwind_opcode (valueT op, int length)
bfae80f2 26559{
c19d1205
ZW		 26560 /* Add any deferred stack adjustment. */
26561 if (unwind.pending_offset)
26562 flush_pending_unwind ();
bfae80f2 26563
c19d1205 26564 unwind.sp_restored = 0;
bfae80f2 26565
c19d1205 26566 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 26567 {
c19d1205
ZW		 26568 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
26569 if (unwind.opcodes)
325801bd
TS		 26570 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
26571 unwind.opcode_alloc);
c19d1205 26572 else
325801bd 26573 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
bfae80f2 26574 }
c19d1205 26575 while (length > 0)
bfae80f2 26576 {
c19d1205
ZW		 26577 length--;
26578 unwind.opcodes[unwind.opcode_count] = op & 0xff;
26579 op >>= 8;
26580 unwind.opcode_count++;
bfae80f2 26581 }
bfae80f2
RE		 26582}
26583
c19d1205
ZW		 26584/* Add unwind opcodes to adjust the stack pointer. */
26585
bfae80f2 26586static void
c19d1205 26587add_unwind_adjustsp (offsetT offset)
bfae80f2 26588{
c19d1205 26589 valueT op;
bfae80f2 26590
c19d1205 26591 if (offset > 0x200)
bfae80f2 26592 {
c19d1205
ZW		 26593 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26594 char bytes[5];
26595 int n;
26596 valueT o;
bfae80f2 26597
c19d1205
ZW		 26598 /* Long form: 0xb2, uleb128. */
26599 /* This might not fit in a word so add the individual bytes,
26600 remembering the list is built in reverse order. */
26601 o = (valueT) ((offset - 0x204) >> 2);
26602 if (o == 0)
26603 add_unwind_opcode (0, 1);
bfae80f2 26604
c19d1205
ZW		 26605 /* Calculate the uleb128 encoding of the offset. */
26606 n = 0;
26607 while (o)
26608 {
26609 bytes[n] = o & 0x7f;
26610 o >>= 7;
26611 if (o)
26612 bytes[n] |= 0x80;
26613 n++;
26614 }
26615 /* Add the insn. */
26616 for (; n; n--)
26617 add_unwind_opcode (bytes[n - 1], 1);
26618 add_unwind_opcode (0xb2, 1);
26619 }
26620 else if (offset > 0x100)
bfae80f2 26621 {
c19d1205
ZW		 26622 /* Two short opcodes. */
26623 add_unwind_opcode (0x3f, 1);
26624 op = (offset - 0x104) >> 2;
26625 add_unwind_opcode (op, 1);
bfae80f2 26626 }
c19d1205
ZW		 26627 else if (offset > 0)
26628 {
26629 /* Short opcode. */
26630 op = (offset - 4) >> 2;
26631 add_unwind_opcode (op, 1);
26632 }
26633 else if (offset < 0)
bfae80f2 26634 {
c19d1205
ZW		 26635 offset = -offset;
26636 while (offset > 0x100)
bfae80f2 26637 {
c19d1205
ZW		 26638 add_unwind_opcode (0x7f, 1);
26639 offset -= 0x100;
bfae80f2 26640 }
c19d1205
ZW		 26641 op = ((offset - 4) >> 2) | 0x40;
26642 add_unwind_opcode (op, 1);
bfae80f2 26643 }
bfae80f2
RE		 26644}
26645
c19d1205 26646/* Finish the list of unwind opcodes for this function. */
0198d5e6 26647
c19d1205
ZW		 26648static void
26649finish_unwind_opcodes (void)
bfae80f2 26650{
c19d1205 26651 valueT op;
bfae80f2 26652
c19d1205 26653 if (unwind.fp_used)
bfae80f2 26654 {
708587a4 26655 /* Adjust sp as necessary. */
c19d1205
ZW		 26656 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
26657 flush_pending_unwind ();
bfae80f2 26658
c19d1205
ZW		 26659 /* After restoring sp from the frame pointer. */
26660 op = 0x90 | unwind.fp_reg;
26661 add_unwind_opcode (op, 1);
26662 }
26663 else
26664 flush_pending_unwind ();
bfae80f2
RE		 26665}
26666
bfae80f2 26667
c19d1205
ZW		 26668/* Start an exception table entry. If idx is nonzero this is an index table
26669 entry. */
bfae80f2
RE		 26670
26671static void
c19d1205 26672start_unwind_section (const segT text_seg, int idx)
bfae80f2 26673{
c19d1205
ZW		 26674 const char * text_name;
26675 const char * prefix;
26676 const char * prefix_once;
26677 const char * group_name;
c19d1205 26678 char * sec_name;
c19d1205
ZW		 26679 int type;
26680 int flags;
26681 int linkonce;
bfae80f2 26682
c19d1205 26683 if (idx)
bfae80f2 26684 {
c19d1205
ZW		 26685 prefix = ELF_STRING_ARM_unwind;
26686 prefix_once = ELF_STRING_ARM_unwind_once;
26687 type = SHT_ARM_EXIDX;
bfae80f2 26688 }
c19d1205 26689 else
bfae80f2 26690 {
c19d1205
ZW		 26691 prefix = ELF_STRING_ARM_unwind_info;
26692 prefix_once = ELF_STRING_ARM_unwind_info_once;
26693 type = SHT_PROGBITS;
bfae80f2
RE		 26694 }
26695
c19d1205
ZW		 26696 text_name = segment_name (text_seg);
26697 if (streq (text_name, ".text"))
26698 text_name = "";
26699
26700 if (strncmp (text_name, ".gnu.linkonce.t.",
26701 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 26702 {
c19d1205
ZW		 26703 prefix = prefix_once;
26704 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE		 26705 }
26706
29a2809e 26707 sec_name = concat (prefix, text_name, (char *) NULL);
bfae80f2 26708
c19d1205
ZW		 26709 flags = SHF_ALLOC;
26710 linkonce = 0;
26711 group_name = 0;
bfae80f2 26712
c19d1205
ZW		 26713 /* Handle COMDAT group. */
26714 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 26715 {
c19d1205
ZW		 26716 group_name = elf_group_name (text_seg);
26717 if (group_name == NULL)
26718 {
bd3ba5d1 26719 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW		 26720 segment_name (text_seg));
26721 ignore_rest_of_line ();
26722 return;
26723 }
26724 flags |= SHF_GROUP;
26725 linkonce = 1;
bfae80f2
RE		 26726 }
26727
a91e1603
L		 26728 obj_elf_change_section (sec_name, type, 0, flags, 0, group_name,
26729 linkonce, 0);
bfae80f2 26730
5f4273c7 26731 /* Set the section link for index tables. */
c19d1205
ZW		 26732 if (idx)
26733 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE		 26734}
26735
bfae80f2 26736
c19d1205
ZW		 26737/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26738 personality routine data. Returns zero, or the index table value for
cad0da33 26739 an inline entry. */
c19d1205
ZW		 26740
26741static valueT
26742create_unwind_entry (int have_data)
bfae80f2 26743{
c19d1205
ZW		 26744 int size;
26745 addressT where;
26746 char *ptr;
26747 /* The current word of data. */
26748 valueT data;
26749 /* The number of bytes left in this word. */
26750 int n;
bfae80f2 26751
c19d1205 26752 finish_unwind_opcodes ();
bfae80f2 26753
c19d1205
ZW		 26754 /* Remember the current text section. */
26755 unwind.saved_seg = now_seg;
26756 unwind.saved_subseg = now_subseg;
bfae80f2 26757
c19d1205 26758 start_unwind_section (now_seg, 0);
bfae80f2 26759
c19d1205 26760 if (unwind.personality_routine == NULL)
bfae80f2 26761 {
c19d1205
ZW		 26762 if (unwind.personality_index == -2)
26763 {
26764 if (have_data)
5f4273c7 26765 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW		 26766 return 1; /* EXIDX_CANTUNWIND. */
26767 }
bfae80f2 26768
c19d1205
ZW		 26769 /* Use a default personality routine if none is specified. */
26770 if (unwind.personality_index == -1)
26771 {
26772 if (unwind.opcode_count > 3)
26773 unwind.personality_index = 1;
26774 else
26775 unwind.personality_index = 0;
26776 }
bfae80f2 26777
c19d1205
ZW		 26778 /* Space for the personality routine entry. */
26779 if (unwind.personality_index == 0)
26780 {
26781 if (unwind.opcode_count > 3)
26782 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 26783
c19d1205
ZW		 26784 if (!have_data)
26785 {
26786 /* All the data is inline in the index table. */
26787 data = 0x80;
26788 n = 3;
26789 while (unwind.opcode_count > 0)
26790 {
26791 unwind.opcode_count--;
26792 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26793 n--;
26794 }
bfae80f2 26795
c19d1205
ZW		 26796 /* Pad with "finish" opcodes. */
26797 while (n--)
26798 data = (data << 8) | 0xb0;
bfae80f2 26799
c19d1205
ZW		 26800 return data;
26801 }
26802 size = 0;
26803 }
26804 else
26805 /* We get two opcodes "free" in the first word. */
26806 size = unwind.opcode_count - 2;
26807 }
26808 else
5011093d 26809 {
cad0da33
NC		 26810 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26811 if (unwind.personality_index != -1)
26812 {
26813 as_bad (_("attempt to recreate an unwind entry"));
26814 return 1;
26815 }
5011093d
NC		 26816
26817 /* An extra byte is required for the opcode count. */
26818 size = unwind.opcode_count + 1;
26819 }
bfae80f2 26820
c19d1205
ZW		 26821 size = (size + 3) >> 2;
26822 if (size > 0xff)
26823 as_bad (_("too many unwind opcodes"));
bfae80f2 26824
c19d1205
ZW		 26825 frag_align (2, 0, 0);
26826 record_alignment (now_seg, 2);
26827 unwind.table_entry = expr_build_dot ();
26828
26829 /* Allocate the table entry. */
26830 ptr = frag_more ((size << 2) + 4);
74929e7b
NC		 26831 /* PR 13449: Zero the table entries in case some of them are not used. */
26832 memset (ptr, 0, (size << 2) + 4);
c19d1205 26833 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 26834
c19d1205 26835 switch (unwind.personality_index)
bfae80f2 26836 {
c19d1205
ZW		 26837 case -1:
26838 /* ??? Should this be a PLT generating relocation? */
26839 /* Custom personality routine. */
26840 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
26841 BFD_RELOC_ARM_PREL31);
bfae80f2 26842
c19d1205
ZW		 26843 where += 4;
26844 ptr += 4;
bfae80f2 26845
c19d1205 26846 /* Set the first byte to the number of additional words. */
5011093d 26847 data = size > 0 ? size - 1 : 0;
c19d1205
ZW		 26848 n = 3;
26849 break;
bfae80f2 26850
c19d1205
ZW		 26851 /* ABI defined personality routines. */
26852 case 0:
26853 /* Three opcodes bytes are packed into the first word. */
26854 data = 0x80;
26855 n = 3;
26856 break;
bfae80f2 26857
c19d1205
ZW		 26858 case 1:
26859 case 2:
26860 /* The size and first two opcode bytes go in the first word. */
26861 data = ((0x80 + unwind.personality_index) << 8) | size;
26862 n = 2;
26863 break;
bfae80f2 26864
c19d1205
ZW		 26865 default:
26866 /* Should never happen. */
26867 abort ();
26868 }
bfae80f2 26869
c19d1205
ZW		 26870 /* Pack the opcodes into words (MSB first), reversing the list at the same
26871 time. */
26872 while (unwind.opcode_count > 0)
26873 {
26874 if (n == 0)
26875 {
26876 md_number_to_chars (ptr, data, 4);
26877 ptr += 4;
26878 n = 4;
26879 data = 0;
26880 }
26881 unwind.opcode_count--;
26882 n--;
26883 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26884 }
26885
26886 /* Finish off the last word. */
26887 if (n < 4)
26888 {
26889 /* Pad with "finish" opcodes. */
26890 while (n--)
26891 data = (data << 8) | 0xb0;
26892
26893 md_number_to_chars (ptr, data, 4);
26894 }
26895
26896 if (!have_data)
26897 {
26898 /* Add an empty descriptor if there is no user-specified data. */
26899 ptr = frag_more (4);
26900 md_number_to_chars (ptr, 0, 4);
26901 }
26902
26903 return 0;
bfae80f2
RE		 26904}
26905
f0927246
NC		 26906
26907/* Initialize the DWARF-2 unwind information for this procedure. */
26908
26909void
26910tc_arm_frame_initial_instructions (void)
26911{
26912 cfi_add_CFA_def_cfa (REG_SP, 0);
26913}
26914#endif /* OBJ_ELF */
26915
c19d1205
ZW		 26916/* Convert REGNAME to a DWARF-2 register number. */
26917
26918int
1df69f4f 26919tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 26920{
1df69f4f 26921 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
1f5afe1c
NC		 26922 if (reg != FAIL)
26923 return reg;
c19d1205 26924
1f5afe1c
NC		 26925 /* PR 16694: Allow VFP registers as well. */
26926 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
26927 if (reg != FAIL)
26928 return 64 + reg;
c19d1205 26929
1f5afe1c
NC		 26930 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
26931 if (reg != FAIL)
26932 return reg + 256;
26933
0198d5e6 26934 return FAIL;
bfae80f2
RE		 26935}
26936
f0927246 26937#ifdef TE_PE
c19d1205 26938void
f0927246 26939tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 26940{
91d6fa6a 26941 expressionS exp;
bfae80f2 26942
91d6fa6a
NC		 26943 exp.X_op = O_secrel;
26944 exp.X_add_symbol = symbol;
26945 exp.X_add_number = 0;
26946 emit_expr (&exp, size);
f0927246
NC		 26947}
26948#endif
bfae80f2 26949
c19d1205 26950/* MD interface: Symbol and relocation handling. */
bfae80f2 26951
2fc8bdac
ZW		 26952/* Return the address within the segment that a PC-relative fixup is
26953 relative to. For ARM, PC-relative fixups applied to instructions
26954 are generally relative to the location of the fixup plus 8 bytes.
26955 Thumb branches are offset by 4, and Thumb loads relative to PC
26956 require special handling. */
bfae80f2 26957
c19d1205 26958long
2fc8bdac 26959md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 26960{
2fc8bdac
ZW		 26961 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
26962
26963 /* If this is pc-relative and we are going to emit a relocation
26964 then we just want to put out any pipeline compensation that the linker
53baae48
NC		 26965 will need. Otherwise we want to use the calculated base.
26966 For WinCE we skip the bias for externals as well, since this
26967 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 26968 if (fixP->fx_pcrel
2fc8bdac 26969 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC		 26970 || (arm_force_relocation (fixP)
26971#ifdef TE_WINCE
26972 && !S_IS_EXTERNAL (fixP->fx_addsy)
26973#endif
26974 )))
2fc8bdac 26975 base = 0;
bfae80f2 26976
267bf995 26977
c19d1205 26978 switch (fixP->fx_r_type)
bfae80f2 26979 {
2fc8bdac
ZW		 26980 /* PC relative addressing on the Thumb is slightly odd as the
26981 bottom two bits of the PC are forced to zero for the
26982 calculation. This happens *after* application of the
26983 pipeline offset. However, Thumb adrl already adjusts for
26984 this, so we need not do it again. */
c19d1205 26985 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 26986 return base & ~3;
c19d1205
ZW		 26987
26988 case BFD_RELOC_ARM_THUMB_OFFSET:
26989 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 26990 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 26991 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 26992 return (base + 4) & ~3;
c19d1205 26993
2fc8bdac 26994 /* Thumb branches are simply offset by +4. */
e12437dc 26995 case BFD_RELOC_THUMB_PCREL_BRANCH5:
2fc8bdac
ZW		 26996 case BFD_RELOC_THUMB_PCREL_BRANCH7:
26997 case BFD_RELOC_THUMB_PCREL_BRANCH9:
26998 case BFD_RELOC_THUMB_PCREL_BRANCH12:
26999 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 27000 case BFD_RELOC_THUMB_PCREL_BRANCH25:
f6b2b12d 27001 case BFD_RELOC_THUMB_PCREL_BFCSEL:
e5d6e09e 27002 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 27003 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 27004 case BFD_RELOC_ARM_THUMB_BF13:
60f993ce 27005 case BFD_RELOC_ARM_THUMB_LOOP12:
2fc8bdac 27006 return base + 4;
bfae80f2 27007
267bf995 27008 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL		 27009 if (fixP->fx_addsy
27010 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27011 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995 27012 && ARM_IS_FUNC (fixP->fx_addsy)
477330fc
RM		 27013 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27014 base = fixP->fx_where + fixP->fx_frag->fr_address;
267bf995
RR		 27015 return base + 4;
27016
00adf2d4
JB		 27017 /* BLX is like branches above, but forces the low two bits of PC to
27018 zero. */
486499d0
CL		 27019 case BFD_RELOC_THUMB_PCREL_BLX:
27020 if (fixP->fx_addsy
27021 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27022 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 27023 && THUMB_IS_FUNC (fixP->fx_addsy)
27024 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27025 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB		 27026 return (base + 4) & ~3;
27027
2fc8bdac
ZW		 27028 /* ARM mode branches are offset by +8. However, the Windows CE
27029 loader expects the relocation not to take this into account. */
267bf995 27030 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL		 27031 if (fixP->fx_addsy
27032 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27033 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 27034 && ARM_IS_FUNC (fixP->fx_addsy)
27035 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27036 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 27037 return base + 8;
267bf995 27038
486499d0
CL		 27039 case BFD_RELOC_ARM_PCREL_CALL:
27040 if (fixP->fx_addsy
27041 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27042 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 27043 && THUMB_IS_FUNC (fixP->fx_addsy)
27044 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27045 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 27046 return base + 8;
267bf995 27047
2fc8bdac 27048 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 27049 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 27050 case BFD_RELOC_ARM_PLT32:
c19d1205 27051#ifdef TE_WINCE
5f4273c7 27052 /* When handling fixups immediately, because we have already
477330fc 27053 discovered the value of a symbol, or the address of the frag involved
53baae48 27054 we must account for the offset by +8, as the OS loader will never see the reloc.
477330fc
RM		 27055 see fixup_segment() in write.c
27056 The S_IS_EXTERNAL test handles the case of global symbols.
27057 Those need the calculated base, not just the pipe compensation the linker will need. */
53baae48
NC		 27058 if (fixP->fx_pcrel
27059 && fixP->fx_addsy != NULL
27060 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27061 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
27062 return base + 8;
2fc8bdac 27063 return base;
c19d1205 27064#else
2fc8bdac 27065 return base + 8;
c19d1205 27066#endif
2fc8bdac 27067
267bf995 27068
2fc8bdac
ZW		 27069 /* ARM mode loads relative to PC are also offset by +8. Unlike
27070 branches, the Windows CE loader *does* expect the relocation
27071 to take this into account. */
27072 case BFD_RELOC_ARM_OFFSET_IMM:
27073 case BFD_RELOC_ARM_OFFSET_IMM8:
27074 case BFD_RELOC_ARM_HWLITERAL:
27075 case BFD_RELOC_ARM_LITERAL:
27076 case BFD_RELOC_ARM_CP_OFF_IMM:
27077 return base + 8;
27078
27079
27080 /* Other PC-relative relocations are un-offset. */
27081 default:
27082 return base;
27083 }
bfae80f2
RE		 27084}
27085
8b2d793c
NC		 27086static bfd_boolean flag_warn_syms = TRUE;
27087
ae8714c2
NC		 27088bfd_boolean
27089arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
bfae80f2 27090{
8b2d793c
NC		 27091 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27092 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27093 does mean that the resulting code might be very confusing to the reader.
27094 Also this warning can be triggered if the user omits an operand before
27095 an immediate address, eg:
27096
27097 LDR =foo
27098
27099 GAS treats this as an assignment of the value of the symbol foo to a
27100 symbol LDR, and so (without this code) it will not issue any kind of
27101 warning or error message.
27102
27103 Note - ARM instructions are case-insensitive but the strings in the hash
27104 table are all stored in lower case, so we must first ensure that name is
ae8714c2
NC		 27105 lower case too. */
27106 if (flag_warn_syms && arm_ops_hsh)
8b2d793c
NC		 27107 {
27108 char * nbuf = strdup (name);
27109 char * p;
27110
27111 for (p = nbuf; *p; p++)
27112 *p = TOLOWER (*p);
27113 if (hash_find (arm_ops_hsh, nbuf) != NULL)
27114 {
27115 static struct hash_control * already_warned = NULL;
27116
27117 if (already_warned == NULL)
27118 already_warned = hash_new ();
27119 /* Only warn about the symbol once. To keep the code
27120 simple we let hash_insert do the lookup for us. */
3076e594 27121 if (hash_insert (already_warned, nbuf, NULL) == NULL)
ae8714c2 27122 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
8b2d793c
NC		 27123 }
27124 else
27125 free (nbuf);
27126 }
3739860c 27127
ae8714c2
NC		 27128 return FALSE;
27129}
27130
27131/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27132 Otherwise we have no need to default values of symbols. */
27133
27134symbolS *
27135md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
27136{
27137#ifdef OBJ_ELF
27138 if (name[0] == '_' && name[1] == 'G'
27139 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
27140 {
27141 if (!GOT_symbol)
27142 {
27143 if (symbol_find (name))
27144 as_bad (_("GOT already in the symbol table"));
27145
27146 GOT_symbol = symbol_new (name, undefined_section,
27147 (valueT) 0, & zero_address_frag);
27148 }
27149
27150 return GOT_symbol;
27151 }
27152#endif
27153
c921be7d 27154 return NULL;
bfae80f2
RE		 27155}
27156
55cf6793 27157/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW		 27158 computed as two separate immediate values, added together. We
27159 already know that this value cannot be computed by just one ARM
27160 instruction. */
27161
27162static unsigned int
27163validate_immediate_twopart (unsigned int val,
27164 unsigned int * highpart)
bfae80f2 27165{
c19d1205
ZW		 27166 unsigned int a;
27167 unsigned int i;
bfae80f2 27168
c19d1205
ZW		 27169 for (i = 0; i < 32; i += 2)
27170 if (((a = rotate_left (val, i)) & 0xff) != 0)
27171 {
27172 if (a & 0xff00)
27173 {
27174 if (a & ~ 0xffff)
27175 continue;
27176 * highpart = (a >> 8) | ((i + 24) << 7);
27177 }
27178 else if (a & 0xff0000)
27179 {
27180 if (a & 0xff000000)
27181 continue;
27182 * highpart = (a >> 16) | ((i + 16) << 7);
27183 }
27184 else
27185 {
9c2799c2 27186 gas_assert (a & 0xff000000);
c19d1205
ZW		 27187 * highpart = (a >> 24) | ((i + 8) << 7);
27188 }
bfae80f2 27189
c19d1205
ZW		 27190 return (a & 0xff) | (i << 7);
27191 }
bfae80f2 27192
c19d1205 27193 return FAIL;
bfae80f2
RE		 27194}
27195
c19d1205
ZW		 27196static int
27197validate_offset_imm (unsigned int val, int hwse)
27198{
27199 if ((hwse && val > 255) || val > 4095)
27200 return FAIL;
27201 return val;
27202}
bfae80f2 27203
55cf6793 27204/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW		 27205 negative immediate constant by altering the instruction. A bit of
27206 a hack really.
27207 MOV <-> MVN
27208 AND <-> BIC
27209 ADC <-> SBC
27210 by inverting the second operand, and
27211 ADD <-> SUB
27212 CMP <-> CMN
27213 by negating the second operand. */
bfae80f2 27214
c19d1205
ZW		 27215static int
27216negate_data_op (unsigned long * instruction,
27217 unsigned long value)
bfae80f2 27218{
c19d1205
ZW		 27219 int op, new_inst;
27220 unsigned long negated, inverted;
bfae80f2 27221
c19d1205
ZW		 27222 negated = encode_arm_immediate (-value);
27223 inverted = encode_arm_immediate (~value);
bfae80f2 27224
c19d1205
ZW		 27225 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
27226 switch (op)
bfae80f2 27227 {
c19d1205
ZW		 27228 /* First negates. */
27229 case OPCODE_SUB: /* ADD <-> SUB */
27230 new_inst = OPCODE_ADD;
27231 value = negated;
27232 break;
bfae80f2 27233
c19d1205
ZW		 27234 case OPCODE_ADD:
27235 new_inst = OPCODE_SUB;
27236 value = negated;
27237 break;
bfae80f2 27238
c19d1205
ZW		 27239 case OPCODE_CMP: /* CMP <-> CMN */
27240 new_inst = OPCODE_CMN;
27241 value = negated;
27242 break;
bfae80f2 27243
c19d1205
ZW		 27244 case OPCODE_CMN:
27245 new_inst = OPCODE_CMP;
27246 value = negated;
27247 break;
bfae80f2 27248
c19d1205
ZW		 27249 /* Now Inverted ops. */
27250 case OPCODE_MOV: /* MOV <-> MVN */
27251 new_inst = OPCODE_MVN;
27252 value = inverted;
27253 break;
bfae80f2 27254
c19d1205
ZW		 27255 case OPCODE_MVN:
27256 new_inst = OPCODE_MOV;
27257 value = inverted;
27258 break;
bfae80f2 27259
c19d1205
ZW		 27260 case OPCODE_AND: /* AND <-> BIC */
27261 new_inst = OPCODE_BIC;
27262 value = inverted;
27263 break;
bfae80f2 27264
c19d1205
ZW		 27265 case OPCODE_BIC:
27266 new_inst = OPCODE_AND;
27267 value = inverted;
27268 break;
bfae80f2 27269
c19d1205
ZW		 27270 case OPCODE_ADC: /* ADC <-> SBC */
27271 new_inst = OPCODE_SBC;
27272 value = inverted;
27273 break;
bfae80f2 27274
c19d1205
ZW		 27275 case OPCODE_SBC:
27276 new_inst = OPCODE_ADC;
27277 value = inverted;
27278 break;
bfae80f2 27279
c19d1205
ZW		 27280 /* We cannot do anything. */
27281 default:
27282 return FAIL;
b99bd4ef
NC		 27283 }
27284
c19d1205
ZW		 27285 if (value == (unsigned) FAIL)
27286 return FAIL;
27287
27288 *instruction &= OPCODE_MASK;
27289 *instruction |= new_inst << DATA_OP_SHIFT;
27290 return value;
b99bd4ef
NC		 27291}
27292
ef8d22e6
PB		 27293/* Like negate_data_op, but for Thumb-2. */
27294
27295static unsigned int
16dd5e42 27296thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB		 27297{
27298 int op, new_inst;
27299 int rd;
16dd5e42 27300 unsigned int negated, inverted;
ef8d22e6
PB		 27301
27302 negated = encode_thumb32_immediate (-value);
27303 inverted = encode_thumb32_immediate (~value);
27304
27305 rd = (*instruction >> 8) & 0xf;
27306 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
27307 switch (op)
27308 {
27309 /* ADD <-> SUB. Includes CMP <-> CMN. */
27310 case T2_OPCODE_SUB:
27311 new_inst = T2_OPCODE_ADD;
27312 value = negated;
27313 break;
27314
27315 case T2_OPCODE_ADD:
27316 new_inst = T2_OPCODE_SUB;
27317 value = negated;
27318 break;
27319
27320 /* ORR <-> ORN. Includes MOV <-> MVN. */
27321 case T2_OPCODE_ORR:
27322 new_inst = T2_OPCODE_ORN;
27323 value = inverted;
27324 break;
27325
27326 case T2_OPCODE_ORN:
27327 new_inst = T2_OPCODE_ORR;
27328 value = inverted;
27329 break;
27330
27331 /* AND <-> BIC. TST has no inverted equivalent. */
27332 case T2_OPCODE_AND:
27333 new_inst = T2_OPCODE_BIC;
27334 if (rd == 15)
27335 value = FAIL;
27336 else
27337 value = inverted;
27338 break;
27339
27340 case T2_OPCODE_BIC:
27341 new_inst = T2_OPCODE_AND;
27342 value = inverted;
27343 break;
27344
27345 /* ADC <-> SBC */
27346 case T2_OPCODE_ADC:
27347 new_inst = T2_OPCODE_SBC;
27348 value = inverted;
27349 break;
27350
27351 case T2_OPCODE_SBC:
27352 new_inst = T2_OPCODE_ADC;
27353 value = inverted;
27354 break;
27355
27356 /* We cannot do anything. */
27357 default:
27358 return FAIL;
27359 }
27360
16dd5e42 27361 if (value == (unsigned int)FAIL)
ef8d22e6
PB		 27362 return FAIL;
27363
27364 *instruction &= T2_OPCODE_MASK;
27365 *instruction |= new_inst << T2_DATA_OP_SHIFT;
27366 return value;
27367}
27368
8f06b2d8 27369/* Read a 32-bit thumb instruction from buf. */
0198d5e6 27370
8f06b2d8
PB		 27371static unsigned long
27372get_thumb32_insn (char * buf)
27373{
27374 unsigned long insn;
27375 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
27376 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27377
27378 return insn;
27379}
27380
a8bc6c78
PB		 27381/* We usually want to set the low bit on the address of thumb function
27382 symbols. In particular .word foo - . should have the low bit set.
27383 Generic code tries to fold the difference of two symbols to
27384 a constant. Prevent this and force a relocation when the first symbols
27385 is a thumb function. */
c921be7d
NC		 27386
27387bfd_boolean
a8bc6c78
PB		 27388arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
27389{
27390 if (op == O_subtract
27391 && l->X_op == O_symbol
27392 && r->X_op == O_symbol
27393 && THUMB_IS_FUNC (l->X_add_symbol))
27394 {
27395 l->X_op = O_subtract;
27396 l->X_op_symbol = r->X_add_symbol;
27397 l->X_add_number -= r->X_add_number;
c921be7d 27398 return TRUE;
a8bc6c78 27399 }
c921be7d 27400
a8bc6c78 27401 /* Process as normal. */
c921be7d 27402 return FALSE;
a8bc6c78
PB		 27403}
27404
4a42ebbc
RR		 27405/* Encode Thumb2 unconditional branches and calls. The encoding
27406 for the 2 are identical for the immediate values. */
27407
27408static void
27409encode_thumb2_b_bl_offset (char * buf, offsetT value)
27410{
27411#define T2I1I2MASK ((1 << 13) | (1 << 11))
27412 offsetT newval;
27413 offsetT newval2;
27414 addressT S, I1, I2, lo, hi;
27415
27416 S = (value >> 24) & 0x01;
27417 I1 = (value >> 23) & 0x01;
27418 I2 = (value >> 22) & 0x01;
27419 hi = (value >> 12) & 0x3ff;
fa94de6b 27420 lo = (value >> 1) & 0x7ff;
4a42ebbc
RR		 27421 newval = md_chars_to_number (buf, THUMB_SIZE);
27422 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27423 newval |= (S << 10) | hi;
27424 newval2 &= ~T2I1I2MASK;
27425 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
27426 md_number_to_chars (buf, newval, THUMB_SIZE);
27427 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27428}
27429
c19d1205 27430void
55cf6793 27431md_apply_fix (fixS * fixP,
c19d1205
ZW		 27432 valueT * valP,
27433 segT seg)
27434{
27435 offsetT value = * valP;
27436 offsetT newval;
27437 unsigned int newimm;
27438 unsigned long temp;
27439 int sign;
27440 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 27441
9c2799c2 27442 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 27443
c19d1205 27444 /* Note whether this will delete the relocation. */
4962c51a 27445
c19d1205
ZW		 27446 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
27447 fixP->fx_done = 1;
b99bd4ef 27448
adbaf948 27449 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 27450 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW		 27451 for emit_reloc. */
27452 value &= 0xffffffff;
27453 value ^= 0x80000000;
5f4273c7 27454 value -= 0x80000000;
adbaf948
ZW		 27455
27456 *valP = value;
c19d1205 27457 fixP->fx_addnumber = value;
b99bd4ef 27458
adbaf948
ZW		 27459 /* Same treatment for fixP->fx_offset. */
27460 fixP->fx_offset &= 0xffffffff;
27461 fixP->fx_offset ^= 0x80000000;
27462 fixP->fx_offset -= 0x80000000;
27463
c19d1205 27464 switch (fixP->fx_r_type)
b99bd4ef 27465 {
c19d1205
ZW		 27466 case BFD_RELOC_NONE:
27467 /* This will need to go in the object file. */
27468 fixP->fx_done = 0;
27469 break;
b99bd4ef 27470
c19d1205
ZW		 27471 case BFD_RELOC_ARM_IMMEDIATE:
27472 /* We claim that this fixup has been processed here,
27473 even if in fact we generate an error because we do
27474 not have a reloc for it, so tc_gen_reloc will reject it. */
27475 fixP->fx_done = 1;
b99bd4ef 27476
77db8e2e 27477 if (fixP->fx_addsy)
b99bd4ef 27478 {
77db8e2e 27479 const char *msg = 0;
b99bd4ef 27480
77db8e2e
NC		 27481 if (! S_IS_DEFINED (fixP->fx_addsy))
27482 msg = _("undefined symbol %s used as an immediate value");
27483 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27484 msg = _("symbol %s is in a different section");
27485 else if (S_IS_WEAK (fixP->fx_addsy))
27486 msg = _("symbol %s is weak and may be overridden later");
27487
27488 if (msg)
27489 {
27490 as_bad_where (fixP->fx_file, fixP->fx_line,
27491 msg, S_GET_NAME (fixP->fx_addsy));
27492 break;
27493 }
42e5fcbf
AS		 27494 }
27495
c19d1205
ZW		 27496 temp = md_chars_to_number (buf, INSN_SIZE);
27497
5e73442d
SL		 27498 /* If the offset is negative, we should use encoding A2 for ADR. */
27499 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
27500 newimm = negate_data_op (&temp, value);
27501 else
27502 {
27503 newimm = encode_arm_immediate (value);
27504
27505 /* If the instruction will fail, see if we can fix things up by
27506 changing the opcode. */
27507 if (newimm == (unsigned int) FAIL)
27508 newimm = negate_data_op (&temp, value);
bada4342
JW		 27509 /* MOV accepts both ARM modified immediate (A1 encoding) and
27510 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27511 When disassembling, MOV is preferred when there is no encoding
27512 overlap. */
27513 if (newimm == (unsigned int) FAIL
27514 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
27515 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
27516 && !((temp >> SBIT_SHIFT) & 0x1)
27517 && value >= 0 && value <= 0xffff)
27518 {
27519 /* Clear bits[23:20] to change encoding from A1 to A2. */
27520 temp &= 0xff0fffff;
27521 /* Encoding high 4bits imm. Code below will encode the remaining
27522 low 12bits. */
27523 temp |= (value & 0x0000f000) << 4;
27524 newimm = value & 0x00000fff;
27525 }
5e73442d
SL		 27526 }
27527
27528 if (newimm == (unsigned int) FAIL)
b99bd4ef 27529 {
c19d1205
ZW		 27530 as_bad_where (fixP->fx_file, fixP->fx_line,
27531 _("invalid constant (%lx) after fixup"),
27532 (unsigned long) value);
27533 break;
b99bd4ef 27534 }
b99bd4ef 27535
c19d1205
ZW		 27536 newimm |= (temp & 0xfffff000);
27537 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
27538 break;
b99bd4ef 27539
c19d1205
ZW		 27540 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
27541 {
27542 unsigned int highpart = 0;
27543 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 27544
77db8e2e 27545 if (fixP->fx_addsy)
42e5fcbf 27546 {
77db8e2e 27547 const char *msg = 0;
42e5fcbf 27548
77db8e2e
NC		 27549 if (! S_IS_DEFINED (fixP->fx_addsy))
27550 msg = _("undefined symbol %s used as an immediate value");
27551 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27552 msg = _("symbol %s is in a different section");
27553 else if (S_IS_WEAK (fixP->fx_addsy))
27554 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 27555
77db8e2e
NC		 27556 if (msg)
27557 {
27558 as_bad_where (fixP->fx_file, fixP->fx_line,
27559 msg, S_GET_NAME (fixP->fx_addsy));
27560 break;
27561 }
27562 }
fa94de6b 27563
c19d1205
ZW		 27564 newimm = encode_arm_immediate (value);
27565 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 27566
c19d1205
ZW		 27567 /* If the instruction will fail, see if we can fix things up by
27568 changing the opcode. */
27569 if (newimm == (unsigned int) FAIL
27570 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
27571 {
27572 /* No ? OK - try using two ADD instructions to generate
27573 the value. */
27574 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 27575
c19d1205
ZW		 27576 /* Yes - then make sure that the second instruction is
27577 also an add. */
27578 if (newimm != (unsigned int) FAIL)
27579 newinsn = temp;
27580 /* Still No ? Try using a negated value. */
27581 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
27582 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
27583 /* Otherwise - give up. */
27584 else
27585 {
27586 as_bad_where (fixP->fx_file, fixP->fx_line,
27587 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27588 (long) value);
27589 break;
27590 }
b99bd4ef 27591
c19d1205
ZW		 27592 /* Replace the first operand in the 2nd instruction (which
27593 is the PC) with the destination register. We have
27594 already added in the PC in the first instruction and we
27595 do not want to do it again. */
27596 newinsn &= ~ 0xf0000;
27597 newinsn |= ((newinsn & 0x0f000) << 4);
27598 }
b99bd4ef 27599
c19d1205
ZW		 27600 newimm |= (temp & 0xfffff000);
27601 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 27602
c19d1205
ZW		 27603 highpart |= (newinsn & 0xfffff000);
27604 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
27605 }
27606 break;
b99bd4ef 27607
c19d1205 27608 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 27609 if (!fixP->fx_done && seg->use_rela_p)
27610 value = 0;
1a0670f3 27611 /* Fall through. */
00a97672 27612
c19d1205 27613 case BFD_RELOC_ARM_LITERAL:
26d97720 27614 sign = value > 0;
b99bd4ef 27615
c19d1205
ZW		 27616 if (value < 0)
27617 value = - value;
b99bd4ef 27618
c19d1205 27619 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 27620 {
c19d1205
ZW		 27621 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
27622 as_bad_where (fixP->fx_file, fixP->fx_line,
27623 _("invalid literal constant: pool needs to be closer"));
27624 else
27625 as_bad_where (fixP->fx_file, fixP->fx_line,
27626 _("bad immediate value for offset (%ld)"),
27627 (long) value);
27628 break;
f03698e6
RE		 27629 }
27630
c19d1205 27631 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 27632 if (value == 0)
27633 newval &= 0xfffff000;
27634 else
27635 {
27636 newval &= 0xff7ff000;
27637 newval |= value | (sign ? INDEX_UP : 0);
27638 }
c19d1205
ZW		 27639 md_number_to_chars (buf, newval, INSN_SIZE);
27640 break;
b99bd4ef 27641
c19d1205
ZW		 27642 case BFD_RELOC_ARM_OFFSET_IMM8:
27643 case BFD_RELOC_ARM_HWLITERAL:
26d97720 27644 sign = value > 0;
b99bd4ef 27645
c19d1205
ZW		 27646 if (value < 0)
27647 value = - value;
b99bd4ef 27648
c19d1205 27649 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 27650 {
c19d1205
ZW		 27651 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
27652 as_bad_where (fixP->fx_file, fixP->fx_line,
27653 _("invalid literal constant: pool needs to be closer"));
27654 else
427d0db6
RM		 27655 as_bad_where (fixP->fx_file, fixP->fx_line,
27656 _("bad immediate value for 8-bit offset (%ld)"),
27657 (long) value);
c19d1205 27658 break;
b99bd4ef
NC		 27659 }
27660
c19d1205 27661 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 27662 if (value == 0)
27663 newval &= 0xfffff0f0;
27664 else
27665 {
27666 newval &= 0xff7ff0f0;
27667 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
27668 }
c19d1205
ZW		 27669 md_number_to_chars (buf, newval, INSN_SIZE);
27670 break;
b99bd4ef 27671
c19d1205
ZW		 27672 case BFD_RELOC_ARM_T32_OFFSET_U8:
27673 if (value < 0 || value > 1020 || value % 4 != 0)
27674 as_bad_where (fixP->fx_file, fixP->fx_line,
27675 _("bad immediate value for offset (%ld)"), (long) value);
27676 value /= 4;
b99bd4ef 27677
c19d1205 27678 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW		 27679 newval |= value;
27680 md_number_to_chars (buf+2, newval, THUMB_SIZE);
27681 break;
b99bd4ef 27682
c19d1205
ZW		 27683 case BFD_RELOC_ARM_T32_OFFSET_IMM:
27684 /* This is a complicated relocation used for all varieties of Thumb32
27685 load/store instruction with immediate offset:
27686
27687 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
477330fc 27688 *4, optional writeback(W)
c19d1205
ZW		 27689 (doubleword load/store)
27690
27691 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27692 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27693 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27694 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27695 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27696
27697 Uppercase letters indicate bits that are already encoded at
27698 this point. Lowercase letters are our problem. For the
27699 second block of instructions, the secondary opcode nybble
27700 (bits 8..11) is present, and bit 23 is zero, even if this is
27701 a PC-relative operation. */
27702 newval = md_chars_to_number (buf, THUMB_SIZE);
27703 newval <<= 16;
27704 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 27705
c19d1205 27706 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 27707 {
c19d1205
ZW		 27708 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27709 if (value >= 0)
27710 newval |= (1 << 23);
27711 else
27712 value = -value;
27713 if (value % 4 != 0)
27714 {
27715 as_bad_where (fixP->fx_file, fixP->fx_line,
27716 _("offset not a multiple of 4"));
27717 break;
27718 }
27719 value /= 4;
216d22bc 27720 if (value > 0xff)
c19d1205
ZW		 27721 {
27722 as_bad_where (fixP->fx_file, fixP->fx_line,
27723 _("offset out of range"));
27724 break;
27725 }
27726 newval &= ~0xff;
b99bd4ef 27727 }
c19d1205 27728 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 27729 {
c19d1205
ZW		 27730 /* PC-relative, 12-bit offset. */
27731 if (value >= 0)
27732 newval |= (1 << 23);
27733 else
27734 value = -value;
216d22bc 27735 if (value > 0xfff)
c19d1205
ZW		 27736 {
27737 as_bad_where (fixP->fx_file, fixP->fx_line,
27738 _("offset out of range"));
27739 break;
27740 }
27741 newval &= ~0xfff;
b99bd4ef 27742 }
c19d1205 27743 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 27744 {
c19d1205
ZW		 27745 /* Writeback: 8-bit, +/- offset. */
27746 if (value >= 0)
27747 newval |= (1 << 9);
27748 else
27749 value = -value;
216d22bc 27750 if (value > 0xff)
c19d1205
ZW		 27751 {
27752 as_bad_where (fixP->fx_file, fixP->fx_line,
27753 _("offset out of range"));
27754 break;
27755 }
27756 newval &= ~0xff;
b99bd4ef 27757 }
c19d1205 27758 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 27759 {
c19d1205 27760 /* T-instruction: positive 8-bit offset. */
216d22bc 27761 if (value < 0 || value > 0xff)
b99bd4ef 27762 {
c19d1205
ZW		 27763 as_bad_where (fixP->fx_file, fixP->fx_line,
27764 _("offset out of range"));
27765 break;
b99bd4ef 27766 }
c19d1205
ZW		 27767 newval &= ~0xff;
27768 newval |= value;
b99bd4ef
NC		 27769 }
27770 else
b99bd4ef 27771 {
c19d1205
ZW		 27772 /* Positive 12-bit or negative 8-bit offset. */
27773 int limit;
27774 if (value >= 0)
b99bd4ef 27775 {
c19d1205
ZW		 27776 newval |= (1 << 23);
27777 limit = 0xfff;
27778 }
27779 else
27780 {
27781 value = -value;
27782 limit = 0xff;
27783 }
27784 if (value > limit)
27785 {
27786 as_bad_where (fixP->fx_file, fixP->fx_line,
27787 _("offset out of range"));
27788 break;
b99bd4ef 27789 }
c19d1205 27790 newval &= ~limit;
b99bd4ef 27791 }
b99bd4ef 27792
c19d1205
ZW		 27793 newval |= value;
27794 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
27795 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
27796 break;
404ff6b5 27797
c19d1205
ZW		 27798 case BFD_RELOC_ARM_SHIFT_IMM:
27799 newval = md_chars_to_number (buf, INSN_SIZE);
27800 if (((unsigned long) value) > 32
27801 || (value == 32
27802 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
27803 {
27804 as_bad_where (fixP->fx_file, fixP->fx_line,
27805 _("shift expression is too large"));
27806 break;
27807 }
404ff6b5 27808
c19d1205
ZW		 27809 if (value == 0)
27810 /* Shifts of zero must be done as lsl. */
27811 newval &= ~0x60;
27812 else if (value == 32)
27813 value = 0;
27814 newval &= 0xfffff07f;
27815 newval |= (value & 0x1f) << 7;
27816 md_number_to_chars (buf, newval, INSN_SIZE);
27817 break;
404ff6b5 27818
c19d1205 27819 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 27820 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 27821 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 27822 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW		 27823 /* We claim that this fixup has been processed here,
27824 even if in fact we generate an error because we do
27825 not have a reloc for it, so tc_gen_reloc will reject it. */
27826 fixP->fx_done = 1;
404ff6b5 27827
c19d1205
ZW		 27828 if (fixP->fx_addsy
27829 && ! S_IS_DEFINED (fixP->fx_addsy))
27830 {
27831 as_bad_where (fixP->fx_file, fixP->fx_line,
27832 _("undefined symbol %s used as an immediate value"),
27833 S_GET_NAME (fixP->fx_addsy));
27834 break;
27835 }
404ff6b5 27836
c19d1205
ZW		 27837 newval = md_chars_to_number (buf, THUMB_SIZE);
27838 newval <<= 16;
27839 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 27840
16805f35 27841 newimm = FAIL;
bada4342
JW		 27842 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
27843 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27844 Thumb2 modified immediate encoding (T2). */
27845 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
16805f35 27846 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB		 27847 {
27848 newimm = encode_thumb32_immediate (value);
27849 if (newimm == (unsigned int) FAIL)
27850 newimm = thumb32_negate_data_op (&newval, value);
27851 }
bada4342 27852 if (newimm == (unsigned int) FAIL)
92e90b6e 27853 {
bada4342 27854 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
e9f89963 27855 {
bada4342
JW		 27856 /* Turn add/sum into addw/subw. */
27857 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
27858 newval = (newval & 0xfeffffff) | 0x02000000;
27859 /* No flat 12-bit imm encoding for addsw/subsw. */
27860 if ((newval & 0x00100000) == 0)
40f246e3 27861 {
bada4342
JW		 27862 /* 12 bit immediate for addw/subw. */
27863 if (value < 0)
27864 {
27865 value = -value;
27866 newval ^= 0x00a00000;
27867 }
27868 if (value > 0xfff)
27869 newimm = (unsigned int) FAIL;
27870 else
27871 newimm = value;
27872 }
27873 }
27874 else
27875 {
27876 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27877 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27878 disassembling, MOV is preferred when there is no encoding
db7bf105 27879 overlap. */
bada4342 27880 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
db7bf105
NC		 27881 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27882 but with the Rn field [19:16] set to 1111. */
27883 && (((newval >> 16) & 0xf) == 0xf)
bada4342
JW		 27884 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
27885 && !((newval >> T2_SBIT_SHIFT) & 0x1)
db7bf105 27886 && value >= 0 && value <= 0xffff)
bada4342
JW		 27887 {
27888 /* Toggle bit[25] to change encoding from T2 to T3. */
27889 newval ^= 1 << 25;
27890 /* Clear bits[19:16]. */
27891 newval &= 0xfff0ffff;
27892 /* Encoding high 4bits imm. Code below will encode the
27893 remaining low 12bits. */
27894 newval |= (value & 0x0000f000) << 4;
27895 newimm = value & 0x00000fff;
40f246e3 27896 }
e9f89963 27897 }
92e90b6e 27898 }
cc8a6dd0 27899
c19d1205 27900 if (newimm == (unsigned int)FAIL)
3631a3c8 27901 {
c19d1205
ZW		 27902 as_bad_where (fixP->fx_file, fixP->fx_line,
27903 _("invalid constant (%lx) after fixup"),
27904 (unsigned long) value);
27905 break;
3631a3c8
NC		 27906 }
27907
c19d1205
ZW		 27908 newval |= (newimm & 0x800) << 15;
27909 newval |= (newimm & 0x700) << 4;
27910 newval |= (newimm & 0x0ff);
cc8a6dd0 27911
c19d1205
ZW		 27912 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
27913 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
27914 break;
a737bd4d 27915
3eb17e6b 27916 case BFD_RELOC_ARM_SMC:
ba85f98c 27917 if (((unsigned long) value) > 0xf)
c19d1205 27918 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 27919 _("invalid smc expression"));
ba85f98c 27920
2fc8bdac 27921 newval = md_chars_to_number (buf, INSN_SIZE);
ba85f98c 27922 newval |= (value & 0xf);
c19d1205
ZW		 27923 md_number_to_chars (buf, newval, INSN_SIZE);
27924 break;
a737bd4d 27925
90ec0d68
MGD		 27926 case BFD_RELOC_ARM_HVC:
27927 if (((unsigned long) value) > 0xffff)
27928 as_bad_where (fixP->fx_file, fixP->fx_line,
27929 _("invalid hvc expression"));
27930 newval = md_chars_to_number (buf, INSN_SIZE);
27931 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
27932 md_number_to_chars (buf, newval, INSN_SIZE);
27933 break;
27934
c19d1205 27935 case BFD_RELOC_ARM_SWI:
adbaf948 27936 if (fixP->tc_fix_data != 0)
c19d1205
ZW		 27937 {
27938 if (((unsigned long) value) > 0xff)
27939 as_bad_where (fixP->fx_file, fixP->fx_line,
27940 _("invalid swi expression"));
2fc8bdac 27941 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW		 27942 newval |= value;
27943 md_number_to_chars (buf, newval, THUMB_SIZE);
27944 }
27945 else
27946 {
27947 if (((unsigned long) value) > 0x00ffffff)
27948 as_bad_where (fixP->fx_file, fixP->fx_line,
27949 _("invalid swi expression"));
2fc8bdac 27950 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 27951 newval |= value;
27952 md_number_to_chars (buf, newval, INSN_SIZE);
27953 }
27954 break;
a737bd4d 27955
c19d1205
ZW		 27956 case BFD_RELOC_ARM_MULTI:
27957 if (((unsigned long) value) > 0xffff)
27958 as_bad_where (fixP->fx_file, fixP->fx_line,
27959 _("invalid expression in load/store multiple"));
27960 newval = value | md_chars_to_number (buf, INSN_SIZE);
27961 md_number_to_chars (buf, newval, INSN_SIZE);
27962 break;
a737bd4d 27963
c19d1205 27964#ifdef OBJ_ELF
39b41c9c 27965 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR		 27966
27967 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27968 && fixP->fx_addsy
34e77a92 27969 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 27970 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27971 && THUMB_IS_FUNC (fixP->fx_addsy))
27972 /* Flip the bl to blx. This is a simple flip
27973 bit here because we generate PCREL_CALL for
27974 unconditional bls. */
27975 {
27976 newval = md_chars_to_number (buf, INSN_SIZE);
27977 newval = newval | 0x10000000;
27978 md_number_to_chars (buf, newval, INSN_SIZE);
27979 temp = 1;
27980 fixP->fx_done = 1;
27981 }
39b41c9c
PB		 27982 else
27983 temp = 3;
27984 goto arm_branch_common;
27985
27986 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR		 27987 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27988 && fixP->fx_addsy
34e77a92 27989 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 27990 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27991 && THUMB_IS_FUNC (fixP->fx_addsy))
27992 {
27993 /* This would map to a bl<cond>, b<cond>,
27994 b<always> to a Thumb function. We
27995 need to force a relocation for this particular
27996 case. */
27997 newval = md_chars_to_number (buf, INSN_SIZE);
27998 fixP->fx_done = 0;
27999 }
1a0670f3 28000 /* Fall through. */
267bf995 28001
2fc8bdac 28002 case BFD_RELOC_ARM_PLT32:
c19d1205 28003#endif
39b41c9c
PB		 28004 case BFD_RELOC_ARM_PCREL_BRANCH:
28005 temp = 3;
28006 goto arm_branch_common;
a737bd4d 28007
39b41c9c 28008 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 28009
39b41c9c 28010 temp = 1;
267bf995
RR		 28011 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28012 && fixP->fx_addsy
34e77a92 28013 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28014 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28015 && ARM_IS_FUNC (fixP->fx_addsy))
28016 {
28017 /* Flip the blx to a bl and warn. */
28018 const char *name = S_GET_NAME (fixP->fx_addsy);
28019 newval = 0xeb000000;
28020 as_warn_where (fixP->fx_file, fixP->fx_line,
28021 _("blx to '%s' an ARM ISA state function changed to bl"),
28022 name);
28023 md_number_to_chars (buf, newval, INSN_SIZE);
28024 temp = 3;
28025 fixP->fx_done = 1;
28026 }
28027
28028#ifdef OBJ_ELF
28029 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
477330fc 28030 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
267bf995
RR		 28031#endif
28032
39b41c9c 28033 arm_branch_common:
c19d1205 28034 /* We are going to store value (shifted right by two) in the
39b41c9c
PB		 28035 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28036 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
de194d85 28037 also be clear. */
39b41c9c 28038 if (value & temp)
c19d1205 28039 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW		 28040 _("misaligned branch destination"));
28041 if ((value & (offsetT)0xfe000000) != (offsetT)0
28042 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
08f10d51 28043 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28044
2fc8bdac 28045 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 28046 {
2fc8bdac
ZW		 28047 newval = md_chars_to_number (buf, INSN_SIZE);
28048 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB		 28049 /* Set the H bit on BLX instructions. */
28050 if (temp == 1)
28051 {
28052 if (value & 2)
28053 newval |= 0x01000000;
28054 else
28055 newval &= ~0x01000000;
28056 }
2fc8bdac 28057 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 28058 }
c19d1205 28059 break;
a737bd4d 28060
25fe350b
MS		 28061 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
28062 /* CBZ can only branch forward. */
a737bd4d 28063
738755b0 28064 /* Attempts to use CBZ to branch to the next instruction
477330fc
RM		 28065 (which, strictly speaking, are prohibited) will be turned into
28066 no-ops.
738755b0
MS		 28067
28068 FIXME: It may be better to remove the instruction completely and
28069 perform relaxation. */
28070 if (value == -2)
2fc8bdac
ZW		 28071 {
28072 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 28073 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW		 28074 md_number_to_chars (buf, newval, THUMB_SIZE);
28075 }
738755b0
MS		 28076 else
28077 {
28078 if (value & ~0x7e)
08f10d51 28079 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
738755b0 28080
477330fc 28081 if (fixP->fx_done || !seg->use_rela_p)
738755b0
MS		 28082 {
28083 newval = md_chars_to_number (buf, THUMB_SIZE);
28084 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
28085 md_number_to_chars (buf, newval, THUMB_SIZE);
28086 }
28087 }
c19d1205 28088 break;
a737bd4d 28089
c19d1205 28090 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac 28091 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
08f10d51 28092 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28093
2fc8bdac
ZW		 28094 if (fixP->fx_done || !seg->use_rela_p)
28095 {
28096 newval = md_chars_to_number (buf, THUMB_SIZE);
28097 newval |= (value & 0x1ff) >> 1;
28098 md_number_to_chars (buf, newval, THUMB_SIZE);
28099 }
c19d1205 28100 break;
a737bd4d 28101
c19d1205 28102 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac 28103 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
08f10d51 28104 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28105
2fc8bdac
ZW		 28106 if (fixP->fx_done || !seg->use_rela_p)
28107 {
28108 newval = md_chars_to_number (buf, THUMB_SIZE);
28109 newval |= (value & 0xfff) >> 1;
28110 md_number_to_chars (buf, newval, THUMB_SIZE);
28111 }
c19d1205 28112 break;
a737bd4d 28113
c19d1205 28114 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR		 28115 if (fixP->fx_addsy
28116 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 28117 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28118 && ARM_IS_FUNC (fixP->fx_addsy)
28119 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28120 {
28121 /* Force a relocation for a branch 20 bits wide. */
28122 fixP->fx_done = 0;
28123 }
08f10d51 28124 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
2fc8bdac
ZW		 28125 as_bad_where (fixP->fx_file, fixP->fx_line,
28126 _("conditional branch out of range"));
404ff6b5 28127
2fc8bdac
ZW		 28128 if (fixP->fx_done || !seg->use_rela_p)
28129 {
28130 offsetT newval2;
28131 addressT S, J1, J2, lo, hi;
404ff6b5 28132
2fc8bdac
ZW		 28133 S = (value & 0x00100000) >> 20;
28134 J2 = (value & 0x00080000) >> 19;
28135 J1 = (value & 0x00040000) >> 18;
28136 hi = (value & 0x0003f000) >> 12;
28137 lo = (value & 0x00000ffe) >> 1;
6c43fab6 28138
2fc8bdac
ZW		 28139 newval = md_chars_to_number (buf, THUMB_SIZE);
28140 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28141 newval |= (S << 10) | hi;
28142 newval2 |= (J1 << 13) | (J2 << 11) | lo;
28143 md_number_to_chars (buf, newval, THUMB_SIZE);
28144 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28145 }
c19d1205 28146 break;
6c43fab6 28147
c19d1205 28148 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR		 28149 /* If there is a blx from a thumb state function to
28150 another thumb function flip this to a bl and warn
28151 about it. */
28152
28153 if (fixP->fx_addsy
34e77a92 28154 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28155 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28156 && THUMB_IS_FUNC (fixP->fx_addsy))
28157 {
28158 const char *name = S_GET_NAME (fixP->fx_addsy);
28159 as_warn_where (fixP->fx_file, fixP->fx_line,
28160 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28161 name);
28162 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28163 newval = newval | 0x1000;
28164 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
28165 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
28166 fixP->fx_done = 1;
28167 }
28168
28169
28170 goto thumb_bl_common;
28171
c19d1205 28172 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR		 28173 /* A bl from Thumb state ISA to an internal ARM state function
28174 is converted to a blx. */
28175 if (fixP->fx_addsy
28176 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 28177 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28178 && ARM_IS_FUNC (fixP->fx_addsy)
28179 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28180 {
28181 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28182 newval = newval & ~0x1000;
28183 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
28184 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
28185 fixP->fx_done = 1;
28186 }
28187
28188 thumb_bl_common:
28189
2fc8bdac
ZW		 28190 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
28191 /* For a BLX instruction, make sure that the relocation is rounded up
28192 to a word boundary. This follows the semantics of the instruction
28193 which specifies that bit 1 of the target address will come from bit
28194 1 of the base address. */
d406f3e4
JB		 28195 value = (value + 3) & ~ 3;
28196
28197#ifdef OBJ_ELF
28198 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
28199 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
28200 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
28201#endif
404ff6b5 28202
2b2f5df9
NC		 28203 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
28204 {
fc289b0a 28205 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
2b2f5df9
NC		 28206 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
28207 else if ((value & ~0x1ffffff)
28208 && ((value & ~0x1ffffff) != ~0x1ffffff))
28209 as_bad_where (fixP->fx_file, fixP->fx_line,
28210 _("Thumb2 branch out of range"));
28211 }
4a42ebbc
RR		 28212
28213 if (fixP->fx_done || !seg->use_rela_p)
28214 encode_thumb2_b_bl_offset (buf, value);
28215
c19d1205 28216 break;
404ff6b5 28217
c19d1205 28218 case BFD_RELOC_THUMB_PCREL_BRANCH25:
08f10d51
NC		 28219 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
28220 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
6c43fab6 28221
2fc8bdac 28222 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 28223 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 28224
2fc8bdac 28225 break;
a737bd4d 28226
2fc8bdac
ZW		 28227 case BFD_RELOC_8:
28228 if (fixP->fx_done || !seg->use_rela_p)
4b1a927e 28229 *buf = value;
c19d1205 28230 break;
a737bd4d 28231
c19d1205 28232 case BFD_RELOC_16:
2fc8bdac 28233 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 28234 md_number_to_chars (buf, value, 2);
c19d1205 28235 break;
a737bd4d 28236
c19d1205 28237#ifdef OBJ_ELF
0855e32b
NS		 28238 case BFD_RELOC_ARM_TLS_CALL:
28239 case BFD_RELOC_ARM_THM_TLS_CALL:
28240 case BFD_RELOC_ARM_TLS_DESCSEQ:
28241 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
0855e32b 28242 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 28243 case BFD_RELOC_ARM_TLS_GD32:
28244 case BFD_RELOC_ARM_TLS_LE32:
28245 case BFD_RELOC_ARM_TLS_IE32:
28246 case BFD_RELOC_ARM_TLS_LDM32:
28247 case BFD_RELOC_ARM_TLS_LDO32:
28248 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4b1a927e 28249 break;
6c43fab6 28250
5c5a4843
CL		 28251 /* Same handling as above, but with the arm_fdpic guard. */
28252 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
28253 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
28254 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
28255 if (arm_fdpic)
28256 {
28257 S_SET_THREAD_LOCAL (fixP->fx_addsy);
28258 }
28259 else
28260 {
28261 as_bad_where (fixP->fx_file, fixP->fx_line,
28262 _("Relocation supported only in FDPIC mode"));
28263 }
28264 break;
28265
c19d1205
ZW		 28266 case BFD_RELOC_ARM_GOT32:
28267 case BFD_RELOC_ARM_GOTOFF:
c19d1205 28268 break;
b43420e6
NC		 28269
28270 case BFD_RELOC_ARM_GOT_PREL:
28271 if (fixP->fx_done || !seg->use_rela_p)
477330fc 28272 md_number_to_chars (buf, value, 4);
b43420e6
NC		 28273 break;
28274
9a6f4e97
NS		 28275 case BFD_RELOC_ARM_TARGET2:
28276 /* TARGET2 is not partial-inplace, so we need to write the
477330fc
RM		 28277 addend here for REL targets, because it won't be written out
28278 during reloc processing later. */
9a6f4e97
NS		 28279 if (fixP->fx_done || !seg->use_rela_p)
28280 md_number_to_chars (buf, fixP->fx_offset, 4);
28281 break;
188fd7ae
CL		 28282
28283 /* Relocations for FDPIC. */
28284 case BFD_RELOC_ARM_GOTFUNCDESC:
28285 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
28286 case BFD_RELOC_ARM_FUNCDESC:
28287 if (arm_fdpic)
28288 {
28289 if (fixP->fx_done || !seg->use_rela_p)
28290 md_number_to_chars (buf, 0, 4);
28291 }
28292 else
28293 {
28294 as_bad_where (fixP->fx_file, fixP->fx_line,
28295 _("Relocation supported only in FDPIC mode"));
28296 }
28297 break;
c19d1205 28298#endif
6c43fab6 28299
c19d1205
ZW		 28300 case BFD_RELOC_RVA:
28301 case BFD_RELOC_32:
28302 case BFD_RELOC_ARM_TARGET1:
28303 case BFD_RELOC_ARM_ROSEGREL32:
28304 case BFD_RELOC_ARM_SBREL32:
28305 case BFD_RELOC_32_PCREL:
f0927246
NC		 28306#ifdef TE_PE
28307 case BFD_RELOC_32_SECREL:
28308#endif
2fc8bdac 28309 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC		 28310#ifdef TE_WINCE
28311 /* For WinCE we only do this for pcrel fixups. */
28312 if (fixP->fx_done || fixP->fx_pcrel)
28313#endif
28314 md_number_to_chars (buf, value, 4);
c19d1205 28315 break;
6c43fab6 28316
c19d1205
ZW		 28317#ifdef OBJ_ELF
28318 case BFD_RELOC_ARM_PREL31:
2fc8bdac 28319 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW		 28320 {
28321 newval = md_chars_to_number (buf, 4) & 0x80000000;
28322 if ((value ^ (value >> 1)) & 0x40000000)
28323 {
28324 as_bad_where (fixP->fx_file, fixP->fx_line,
28325 _("rel31 relocation overflow"));
28326 }
28327 newval |= value & 0x7fffffff;
28328 md_number_to_chars (buf, newval, 4);
28329 }
28330 break;
c19d1205 28331#endif
a737bd4d 28332
c19d1205 28333 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 28334 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
32c36c3c 28335 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
9db2f6b4
RL		 28336 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
28337 newval = md_chars_to_number (buf, INSN_SIZE);
28338 else
28339 newval = get_thumb32_insn (buf);
28340 if ((newval & 0x0f200f00) == 0x0d000900)
28341 {
28342 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28343 has permitted values that are multiples of 2, in the range 0
28344 to 510. */
28345 if (value < -510 || value > 510 || (value & 1))
28346 as_bad_where (fixP->fx_file, fixP->fx_line,
28347 _("co-processor offset out of range"));
28348 }
32c36c3c
AV		 28349 else if ((newval & 0xfe001f80) == 0xec000f80)
28350 {
28351 if (value < -511 || value > 512 || (value & 3))
28352 as_bad_where (fixP->fx_file, fixP->fx_line,
28353 _("co-processor offset out of range"));
28354 }
9db2f6b4 28355 else if (value < -1023 || value > 1023 || (value & 3))
c19d1205
ZW		 28356 as_bad_where (fixP->fx_file, fixP->fx_line,
28357 _("co-processor offset out of range"));
28358 cp_off_common:
26d97720 28359 sign = value > 0;
c19d1205
ZW		 28360 if (value < 0)
28361 value = -value;
8f06b2d8
PB		 28362 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28363 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
28364 newval = md_chars_to_number (buf, INSN_SIZE);
28365 else
28366 newval = get_thumb32_insn (buf);
26d97720 28367 if (value == 0)
32c36c3c
AV		 28368 {
28369 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
28370 newval &= 0xffffff80;
28371 else
28372 newval &= 0xffffff00;
28373 }
26d97720
NS		 28374 else
28375 {
32c36c3c
AV		 28376 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
28377 newval &= 0xff7fff80;
28378 else
28379 newval &= 0xff7fff00;
9db2f6b4
RL		 28380 if ((newval & 0x0f200f00) == 0x0d000900)
28381 {
28382 /* This is a fp16 vstr/vldr.
28383
28384 It requires the immediate offset in the instruction is shifted
28385 left by 1 to be a half-word offset.
28386
28387 Here, left shift by 1 first, and later right shift by 2
28388 should get the right offset. */
28389 value <<= 1;
28390 }
26d97720
NS		 28391 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
28392 }
8f06b2d8
PB		 28393 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28394 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
28395 md_number_to_chars (buf, newval, INSN_SIZE);
28396 else
28397 put_thumb32_insn (buf, newval);
c19d1205 28398 break;
a737bd4d 28399
c19d1205 28400 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 28401 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW		 28402 if (value < -255 || value > 255)
28403 as_bad_where (fixP->fx_file, fixP->fx_line,
28404 _("co-processor offset out of range"));
df7849c5 28405 value *= 4;
c19d1205 28406 goto cp_off_common;
6c43fab6 28407
c19d1205
ZW		 28408 case BFD_RELOC_ARM_THUMB_OFFSET:
28409 newval = md_chars_to_number (buf, THUMB_SIZE);
28410 /* Exactly what ranges, and where the offset is inserted depends
28411 on the type of instruction, we can establish this from the
28412 top 4 bits. */
28413 switch (newval >> 12)
28414 {
28415 case 4: /* PC load. */
28416 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28417 forced to zero for these loads; md_pcrel_from has already
28418 compensated for this. */
28419 if (value & 3)
28420 as_bad_where (fixP->fx_file, fixP->fx_line,
28421 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC		 28422 (((unsigned long) fixP->fx_frag->fr_address
28423 + (unsigned long) fixP->fx_where) & ~3)
28424 + (unsigned long) value);
a737bd4d 28425
c19d1205
ZW		 28426 if (value & ~0x3fc)
28427 as_bad_where (fixP->fx_file, fixP->fx_line,
28428 _("invalid offset, value too big (0x%08lX)"),
28429 (long) value);
a737bd4d 28430
c19d1205
ZW		 28431 newval |= value >> 2;
28432 break;
a737bd4d 28433
c19d1205
ZW		 28434 case 9: /* SP load/store. */
28435 if (value & ~0x3fc)
28436 as_bad_where (fixP->fx_file, fixP->fx_line,
28437 _("invalid offset, value too big (0x%08lX)"),
28438 (long) value);
28439 newval |= value >> 2;
28440 break;
6c43fab6 28441
c19d1205
ZW		 28442 case 6: /* Word load/store. */
28443 if (value & ~0x7c)
28444 as_bad_where (fixP->fx_file, fixP->fx_line,
28445 _("invalid offset, value too big (0x%08lX)"),
28446 (long) value);
28447 newval |= value << 4; /* 6 - 2. */
28448 break;
a737bd4d 28449
c19d1205
ZW		 28450 case 7: /* Byte load/store. */
28451 if (value & ~0x1f)
28452 as_bad_where (fixP->fx_file, fixP->fx_line,
28453 _("invalid offset, value too big (0x%08lX)"),
28454 (long) value);
28455 newval |= value << 6;
28456 break;
a737bd4d 28457
c19d1205
ZW		 28458 case 8: /* Halfword load/store. */
28459 if (value & ~0x3e)
28460 as_bad_where (fixP->fx_file, fixP->fx_line,
28461 _("invalid offset, value too big (0x%08lX)"),
28462 (long) value);
28463 newval |= value << 5; /* 6 - 1. */
28464 break;
a737bd4d 28465
c19d1205
ZW		 28466 default:
28467 as_bad_where (fixP->fx_file, fixP->fx_line,
28468 "Unable to process relocation for thumb opcode: %lx",
28469 (unsigned long) newval);
28470 break;
28471 }
28472 md_number_to_chars (buf, newval, THUMB_SIZE);
28473 break;
a737bd4d 28474
c19d1205
ZW		 28475 case BFD_RELOC_ARM_THUMB_ADD:
28476 /* This is a complicated relocation, since we use it for all of
28477 the following immediate relocations:
a737bd4d 28478
c19d1205
ZW		 28479 3bit ADD/SUB
28480 8bit ADD/SUB
28481 9bit ADD/SUB SP word-aligned
28482 10bit ADD PC/SP word-aligned
a737bd4d 28483
c19d1205
ZW		 28484 The type of instruction being processed is encoded in the
28485 instruction field:
a737bd4d 28486
c19d1205
ZW		 28487 0x8000 SUB
28488 0x00F0 Rd
28489 0x000F Rs
28490 */
28491 newval = md_chars_to_number (buf, THUMB_SIZE);
28492 {
28493 int rd = (newval >> 4) & 0xf;
28494 int rs = newval & 0xf;
28495 int subtract = !!(newval & 0x8000);
a737bd4d 28496
c19d1205
ZW		 28497 /* Check for HI regs, only very restricted cases allowed:
28498 Adjusting SP, and using PC or SP to get an address. */
28499 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
28500 || (rs > 7 && rs != REG_SP && rs != REG_PC))
28501 as_bad_where (fixP->fx_file, fixP->fx_line,
28502 _("invalid Hi register with immediate"));
a737bd4d 28503
c19d1205
ZW		 28504 /* If value is negative, choose the opposite instruction. */
28505 if (value < 0)
28506 {
28507 value = -value;
28508 subtract = !subtract;
28509 if (value < 0)
28510 as_bad_where (fixP->fx_file, fixP->fx_line,
28511 _("immediate value out of range"));
28512 }
a737bd4d 28513
c19d1205
ZW		 28514 if (rd == REG_SP)
28515 {
75c11999 28516 if (value & ~0x1fc)
c19d1205
ZW		 28517 as_bad_where (fixP->fx_file, fixP->fx_line,
28518 _("invalid immediate for stack address calculation"));
28519 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
28520 newval |= value >> 2;
28521 }
28522 else if (rs == REG_PC || rs == REG_SP)
28523 {
c12d2c9d
NC		 28524 /* PR gas/18541. If the addition is for a defined symbol
28525 within range of an ADR instruction then accept it. */
28526 if (subtract
28527 && value == 4
28528 && fixP->fx_addsy != NULL)
28529 {
28530 subtract = 0;
28531
28532 if (! S_IS_DEFINED (fixP->fx_addsy)
28533 || S_GET_SEGMENT (fixP->fx_addsy) != seg
28534 || S_IS_WEAK (fixP->fx_addsy))
28535 {
28536 as_bad_where (fixP->fx_file, fixP->fx_line,
28537 _("address calculation needs a strongly defined nearby symbol"));
28538 }
28539 else
28540 {
28541 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
28542
28543 /* Round up to the next 4-byte boundary. */
28544 if (v & 3)
28545 v = (v + 3) & ~ 3;
28546 else
28547 v += 4;
28548 v = S_GET_VALUE (fixP->fx_addsy) - v;
28549
28550 if (v & ~0x3fc)
28551 {
28552 as_bad_where (fixP->fx_file, fixP->fx_line,
28553 _("symbol too far away"));
28554 }
28555 else
28556 {
28557 fixP->fx_done = 1;
28558 value = v;
28559 }
28560 }
28561 }
28562
c19d1205
ZW		 28563 if (subtract || value & ~0x3fc)
28564 as_bad_where (fixP->fx_file, fixP->fx_line,
28565 _("invalid immediate for address calculation (value = 0x%08lX)"),
5fc177c8 28566 (unsigned long) (subtract ? - value : value));
c19d1205
ZW		 28567 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
28568 newval |= rd << 8;
28569 newval |= value >> 2;
28570 }
28571 else if (rs == rd)
28572 {
28573 if (value & ~0xff)
28574 as_bad_where (fixP->fx_file, fixP->fx_line,
28575 _("immediate value out of range"));
28576 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
28577 newval |= (rd << 8) | value;
28578 }
28579 else
28580 {
28581 if (value & ~0x7)
28582 as_bad_where (fixP->fx_file, fixP->fx_line,
28583 _("immediate value out of range"));
28584 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
28585 newval |= rd | (rs << 3) | (value << 6);
28586 }
28587 }
28588 md_number_to_chars (buf, newval, THUMB_SIZE);
28589 break;
a737bd4d 28590
c19d1205
ZW		 28591 case BFD_RELOC_ARM_THUMB_IMM:
28592 newval = md_chars_to_number (buf, THUMB_SIZE);
28593 if (value < 0 || value > 255)
28594 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 28595 _("invalid immediate: %ld is out of range"),
c19d1205
ZW		 28596 (long) value);
28597 newval |= value;
28598 md_number_to_chars (buf, newval, THUMB_SIZE);
28599 break;
a737bd4d 28600
c19d1205
ZW		 28601 case BFD_RELOC_ARM_THUMB_SHIFT:
28602 /* 5bit shift value (0..32). LSL cannot take 32. */
28603 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
28604 temp = newval & 0xf800;
28605 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
28606 as_bad_where (fixP->fx_file, fixP->fx_line,
28607 _("invalid shift value: %ld"), (long) value);
28608 /* Shifts of zero must be encoded as LSL. */
28609 if (value == 0)
28610 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
28611 /* Shifts of 32 are encoded as zero. */
28612 else if (value == 32)
28613 value = 0;
28614 newval |= value << 6;
28615 md_number_to_chars (buf, newval, THUMB_SIZE);
28616 break;
a737bd4d 28617
c19d1205
ZW		 28618 case BFD_RELOC_VTABLE_INHERIT:
28619 case BFD_RELOC_VTABLE_ENTRY:
28620 fixP->fx_done = 0;
28621 return;
6c43fab6 28622
b6895b4f
PB		 28623 case BFD_RELOC_ARM_MOVW:
28624 case BFD_RELOC_ARM_MOVT:
28625 case BFD_RELOC_ARM_THUMB_MOVW:
28626 case BFD_RELOC_ARM_THUMB_MOVT:
28627 if (fixP->fx_done || !seg->use_rela_p)
28628 {
28629 /* REL format relocations are limited to a 16-bit addend. */
28630 if (!fixP->fx_done)
28631 {
39623e12 28632 if (value < -0x8000 || value > 0x7fff)
b6895b4f 28633 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 28634 _("offset out of range"));
b6895b4f
PB		 28635 }
28636 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
28637 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28638 {
28639 value >>= 16;
28640 }
28641
28642 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
28643 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28644 {
28645 newval = get_thumb32_insn (buf);
28646 newval &= 0xfbf08f00;
28647 newval |= (value & 0xf000) << 4;
28648 newval |= (value & 0x0800) << 15;
28649 newval |= (value & 0x0700) << 4;
28650 newval |= (value & 0x00ff);
28651 put_thumb32_insn (buf, newval);
28652 }
28653 else
28654 {
28655 newval = md_chars_to_number (buf, 4);
28656 newval &= 0xfff0f000;
28657 newval |= value & 0x0fff;
28658 newval |= (value & 0xf000) << 4;
28659 md_number_to_chars (buf, newval, 4);
28660 }
28661 }
28662 return;
28663
72d98d16
MG		 28664 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
28665 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
28666 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
28667 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
28668 gas_assert (!fixP->fx_done);
28669 {
28670 bfd_vma insn;
28671 bfd_boolean is_mov;
28672 bfd_vma encoded_addend = value;
28673
28674 /* Check that addend can be encoded in instruction. */
28675 if (!seg->use_rela_p && (value < 0 || value > 255))
28676 as_bad_where (fixP->fx_file, fixP->fx_line,
28677 _("the offset 0x%08lX is not representable"),
28678 (unsigned long) encoded_addend);
28679
28680 /* Extract the instruction. */
28681 insn = md_chars_to_number (buf, THUMB_SIZE);
28682 is_mov = (insn & 0xf800) == 0x2000;
28683
28684 /* Encode insn. */
28685 if (is_mov)
28686 {
28687 if (!seg->use_rela_p)
28688 insn |= encoded_addend;
28689 }
28690 else
28691 {
28692 int rd, rs;
28693
28694 /* Extract the instruction. */
28695 /* Encoding is the following
28696 0x8000 SUB
28697 0x00F0 Rd
28698 0x000F Rs
28699 */
28700 /* The following conditions must be true :
28701 - ADD
28702 - Rd == Rs
28703 - Rd <= 7
28704 */
28705 rd = (insn >> 4) & 0xf;
28706 rs = insn & 0xf;
28707 if ((insn & 0x8000) || (rd != rs) || rd > 7)
28708 as_bad_where (fixP->fx_file, fixP->fx_line,
28709 _("Unable to process relocation for thumb opcode: %lx"),
28710 (unsigned long) insn);
28711
28712 /* Encode as ADD immediate8 thumb 1 code. */
28713 insn = 0x3000 | (rd << 8);
28714
28715 /* Place the encoded addend into the first 8 bits of the
28716 instruction. */
28717 if (!seg->use_rela_p)
28718 insn |= encoded_addend;
28719 }
28720
28721 /* Update the instruction. */
28722 md_number_to_chars (buf, insn, THUMB_SIZE);
28723 }
28724 break;
28725
4962c51a
MS		 28726 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28727 case BFD_RELOC_ARM_ALU_PC_G0:
28728 case BFD_RELOC_ARM_ALU_PC_G1_NC:
28729 case BFD_RELOC_ARM_ALU_PC_G1:
28730 case BFD_RELOC_ARM_ALU_PC_G2:
28731 case BFD_RELOC_ARM_ALU_SB_G0_NC:
28732 case BFD_RELOC_ARM_ALU_SB_G0:
28733 case BFD_RELOC_ARM_ALU_SB_G1_NC:
28734 case BFD_RELOC_ARM_ALU_SB_G1:
28735 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 28736 gas_assert (!fixP->fx_done);
4962c51a
MS		 28737 if (!seg->use_rela_p)
28738 {
477330fc
RM		 28739 bfd_vma insn;
28740 bfd_vma encoded_addend;
3ca4a8ec 28741 bfd_vma addend_abs = llabs (value);
477330fc
RM		 28742
28743 /* Check that the absolute value of the addend can be
28744 expressed as an 8-bit constant plus a rotation. */
28745 encoded_addend = encode_arm_immediate (addend_abs);
28746 if (encoded_addend == (unsigned int) FAIL)
4962c51a 28747 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28748 _("the offset 0x%08lX is not representable"),
28749 (unsigned long) addend_abs);
28750
28751 /* Extract the instruction. */
28752 insn = md_chars_to_number (buf, INSN_SIZE);
28753
28754 /* If the addend is positive, use an ADD instruction.
28755 Otherwise use a SUB. Take care not to destroy the S bit. */
28756 insn &= 0xff1fffff;
28757 if (value < 0)
28758 insn |= 1 << 22;
28759 else
28760 insn |= 1 << 23;
28761
28762 /* Place the encoded addend into the first 12 bits of the
28763 instruction. */
28764 insn &= 0xfffff000;
28765 insn |= encoded_addend;
28766
28767 /* Update the instruction. */
28768 md_number_to_chars (buf, insn, INSN_SIZE);
4962c51a
MS		 28769 }
28770 break;
28771
28772 case BFD_RELOC_ARM_LDR_PC_G0:
28773 case BFD_RELOC_ARM_LDR_PC_G1:
28774 case BFD_RELOC_ARM_LDR_PC_G2:
28775 case BFD_RELOC_ARM_LDR_SB_G0:
28776 case BFD_RELOC_ARM_LDR_SB_G1:
28777 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 28778 gas_assert (!fixP->fx_done);
4962c51a 28779 if (!seg->use_rela_p)
477330fc
RM		 28780 {
28781 bfd_vma insn;
3ca4a8ec 28782 bfd_vma addend_abs = llabs (value);
4962c51a 28783
477330fc
RM		 28784 /* Check that the absolute value of the addend can be
28785 encoded in 12 bits. */
28786 if (addend_abs >= 0x1000)
4962c51a 28787 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28788 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28789 (unsigned long) addend_abs);
28790
28791 /* Extract the instruction. */
28792 insn = md_chars_to_number (buf, INSN_SIZE);
28793
28794 /* If the addend is negative, clear bit 23 of the instruction.
28795 Otherwise set it. */
28796 if (value < 0)
28797 insn &= ~(1 << 23);
28798 else
28799 insn |= 1 << 23;
28800
28801 /* Place the absolute value of the addend into the first 12 bits
28802 of the instruction. */
28803 insn &= 0xfffff000;
28804 insn |= addend_abs;
28805
28806 /* Update the instruction. */
28807 md_number_to_chars (buf, insn, INSN_SIZE);
28808 }
4962c51a
MS		 28809 break;
28810
28811 case BFD_RELOC_ARM_LDRS_PC_G0:
28812 case BFD_RELOC_ARM_LDRS_PC_G1:
28813 case BFD_RELOC_ARM_LDRS_PC_G2:
28814 case BFD_RELOC_ARM_LDRS_SB_G0:
28815 case BFD_RELOC_ARM_LDRS_SB_G1:
28816 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 28817 gas_assert (!fixP->fx_done);
4962c51a 28818 if (!seg->use_rela_p)
477330fc
RM		 28819 {
28820 bfd_vma insn;
3ca4a8ec 28821 bfd_vma addend_abs = llabs (value);
4962c51a 28822
477330fc
RM		 28823 /* Check that the absolute value of the addend can be
28824 encoded in 8 bits. */
28825 if (addend_abs >= 0x100)
4962c51a 28826 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28827 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28828 (unsigned long) addend_abs);
28829
28830 /* Extract the instruction. */
28831 insn = md_chars_to_number (buf, INSN_SIZE);
28832
28833 /* If the addend is negative, clear bit 23 of the instruction.
28834 Otherwise set it. */
28835 if (value < 0)
28836 insn &= ~(1 << 23);
28837 else
28838 insn |= 1 << 23;
28839
28840 /* Place the first four bits of the absolute value of the addend
28841 into the first 4 bits of the instruction, and the remaining
28842 four into bits 8 .. 11. */
28843 insn &= 0xfffff0f0;
28844 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
28845
28846 /* Update the instruction. */
28847 md_number_to_chars (buf, insn, INSN_SIZE);
28848 }
4962c51a
MS		 28849 break;
28850
28851 case BFD_RELOC_ARM_LDC_PC_G0:
28852 case BFD_RELOC_ARM_LDC_PC_G1:
28853 case BFD_RELOC_ARM_LDC_PC_G2:
28854 case BFD_RELOC_ARM_LDC_SB_G0:
28855 case BFD_RELOC_ARM_LDC_SB_G1:
28856 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 28857 gas_assert (!fixP->fx_done);
4962c51a 28858 if (!seg->use_rela_p)
477330fc
RM		 28859 {
28860 bfd_vma insn;
3ca4a8ec 28861 bfd_vma addend_abs = llabs (value);
4962c51a 28862
477330fc
RM		 28863 /* Check that the absolute value of the addend is a multiple of
28864 four and, when divided by four, fits in 8 bits. */
28865 if (addend_abs & 0x3)
4962c51a 28866 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28867 _("bad offset 0x%08lX (must be word-aligned)"),
28868 (unsigned long) addend_abs);
4962c51a 28869
477330fc 28870 if ((addend_abs >> 2) > 0xff)
4962c51a 28871 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28872 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28873 (unsigned long) addend_abs);
28874
28875 /* Extract the instruction. */
28876 insn = md_chars_to_number (buf, INSN_SIZE);
28877
28878 /* If the addend is negative, clear bit 23 of the instruction.
28879 Otherwise set it. */
28880 if (value < 0)
28881 insn &= ~(1 << 23);
28882 else
28883 insn |= 1 << 23;
28884
28885 /* Place the addend (divided by four) into the first eight
28886 bits of the instruction. */
28887 insn &= 0xfffffff0;
28888 insn |= addend_abs >> 2;
28889
28890 /* Update the instruction. */
28891 md_number_to_chars (buf, insn, INSN_SIZE);
28892 }
4962c51a
MS		 28893 break;
28894
e12437dc
AV		 28895 case BFD_RELOC_THUMB_PCREL_BRANCH5:
28896 if (fixP->fx_addsy
28897 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28898 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28899 && ARM_IS_FUNC (fixP->fx_addsy)
28900 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28901 {
28902 /* Force a relocation for a branch 5 bits wide. */
28903 fixP->fx_done = 0;
28904 }
28905 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
28906 as_bad_where (fixP->fx_file, fixP->fx_line,
28907 BAD_BRANCH_OFF);
28908
28909 if (fixP->fx_done || !seg->use_rela_p)
28910 {
28911 addressT boff = value >> 1;
28912
28913 newval = md_chars_to_number (buf, THUMB_SIZE);
28914 newval |= (boff << 7);
28915 md_number_to_chars (buf, newval, THUMB_SIZE);
28916 }
28917 break;
28918
f6b2b12d
AV		 28919 case BFD_RELOC_THUMB_PCREL_BFCSEL:
28920 if (fixP->fx_addsy
28921 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28922 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28923 && ARM_IS_FUNC (fixP->fx_addsy)
28924 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28925 {
28926 fixP->fx_done = 0;
28927 }
28928 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
28929 as_bad_where (fixP->fx_file, fixP->fx_line,
28930 _("branch out of range"));
28931
28932 if (fixP->fx_done || !seg->use_rela_p)
28933 {
28934 newval = md_chars_to_number (buf, THUMB_SIZE);
28935
28936 addressT boff = ((newval & 0x0780) >> 7) << 1;
28937 addressT diff = value - boff;
28938
28939 if (diff == 4)
28940 {
28941 newval |= 1 << 1; /* T bit. */
28942 }
28943 else if (diff != 2)
28944 {
28945 as_bad_where (fixP->fx_file, fixP->fx_line,
28946 _("out of range label-relative fixup value"));
28947 }
28948 md_number_to_chars (buf, newval, THUMB_SIZE);
28949 }
28950 break;
28951
e5d6e09e
AV		 28952 case BFD_RELOC_ARM_THUMB_BF17:
28953 if (fixP->fx_addsy
28954 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28955 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28956 && ARM_IS_FUNC (fixP->fx_addsy)
28957 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28958 {
28959 /* Force a relocation for a branch 17 bits wide. */
28960 fixP->fx_done = 0;
28961 }
28962
28963 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
28964 as_bad_where (fixP->fx_file, fixP->fx_line,
28965 BAD_BRANCH_OFF);
28966
28967 if (fixP->fx_done || !seg->use_rela_p)
28968 {
28969 offsetT newval2;
28970 addressT immA, immB, immC;
28971
28972 immA = (value & 0x0001f000) >> 12;
28973 immB = (value & 0x00000ffc) >> 2;
28974 immC = (value & 0x00000002) >> 1;
28975
28976 newval = md_chars_to_number (buf, THUMB_SIZE);
28977 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28978 newval |= immA;
28979 newval2 |= (immC << 11) | (immB << 1);
28980 md_number_to_chars (buf, newval, THUMB_SIZE);
28981 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28982 }
28983 break;
28984
1caf72a5
AV		 28985 case BFD_RELOC_ARM_THUMB_BF19:
28986 if (fixP->fx_addsy
28987 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28988 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28989 && ARM_IS_FUNC (fixP->fx_addsy)
28990 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28991 {
28992 /* Force a relocation for a branch 19 bits wide. */
28993 fixP->fx_done = 0;
28994 }
28995
28996 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
28997 as_bad_where (fixP->fx_file, fixP->fx_line,
28998 BAD_BRANCH_OFF);
28999
29000 if (fixP->fx_done || !seg->use_rela_p)
29001 {
29002 offsetT newval2;
29003 addressT immA, immB, immC;
29004
29005 immA = (value & 0x0007f000) >> 12;
29006 immB = (value & 0x00000ffc) >> 2;
29007 immC = (value & 0x00000002) >> 1;
29008
29009 newval = md_chars_to_number (buf, THUMB_SIZE);
29010 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29011 newval |= immA;
29012 newval2 |= (immC << 11) | (immB << 1);
29013 md_number_to_chars (buf, newval, THUMB_SIZE);
29014 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29015 }
29016 break;
29017
1889da70
AV		 29018 case BFD_RELOC_ARM_THUMB_BF13:
29019 if (fixP->fx_addsy
29020 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29021 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29022 && ARM_IS_FUNC (fixP->fx_addsy)
29023 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29024 {
29025 /* Force a relocation for a branch 13 bits wide. */
29026 fixP->fx_done = 0;
29027 }
29028
29029 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
29030 as_bad_where (fixP->fx_file, fixP->fx_line,
29031 BAD_BRANCH_OFF);
29032
29033 if (fixP->fx_done || !seg->use_rela_p)
29034 {
29035 offsetT newval2;
29036 addressT immA, immB, immC;
29037
29038 immA = (value & 0x00001000) >> 12;
29039 immB = (value & 0x00000ffc) >> 2;
29040 immC = (value & 0x00000002) >> 1;
29041
29042 newval = md_chars_to_number (buf, THUMB_SIZE);
29043 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29044 newval |= immA;
29045 newval2 |= (immC << 11) | (immB << 1);
29046 md_number_to_chars (buf, newval, THUMB_SIZE);
29047 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29048 }
29049 break;
29050
60f993ce
AV		 29051 case BFD_RELOC_ARM_THUMB_LOOP12:
29052 if (fixP->fx_addsy
29053 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29054 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29055 && ARM_IS_FUNC (fixP->fx_addsy)
29056 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29057 {
29058 /* Force a relocation for a branch 12 bits wide. */
29059 fixP->fx_done = 0;
29060 }
29061
29062 bfd_vma insn = get_thumb32_insn (buf);
1f6234a3 29063 /* le lr, <label>, le <label> or letp lr, <label> */
60f993ce 29064 if (((insn & 0xffffffff) == 0xf00fc001)
1f6234a3
AV		 29065 || ((insn & 0xffffffff) == 0xf02fc001)
29066 || ((insn & 0xffffffff) == 0xf01fc001))
60f993ce
AV		 29067 value = -value;
29068
29069 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
29070 as_bad_where (fixP->fx_file, fixP->fx_line,
29071 BAD_BRANCH_OFF);
29072 if (fixP->fx_done || !seg->use_rela_p)
29073 {
29074 addressT imml, immh;
29075
29076 immh = (value & 0x00000ffc) >> 2;
29077 imml = (value & 0x00000002) >> 1;
29078
29079 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29080 newval |= (imml << 11) | (immh << 1);
29081 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
29082 }
29083 break;
29084
845b51d6
PB		 29085 case BFD_RELOC_ARM_V4BX:
29086 /* This will need to go in the object file. */
29087 fixP->fx_done = 0;
29088 break;
29089
c19d1205
ZW		 29090 case BFD_RELOC_UNUSED:
29091 default:
29092 as_bad_where (fixP->fx_file, fixP->fx_line,
29093 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
29094 }
6c43fab6
RE		 29095}
29096
c19d1205
ZW		 29097/* Translate internal representation of relocation info to BFD target
29098 format. */
a737bd4d 29099
c19d1205 29100arelent *
00a97672 29101tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 29102{
c19d1205
ZW		 29103 arelent * reloc;
29104 bfd_reloc_code_real_type code;
a737bd4d 29105
325801bd 29106 reloc = XNEW (arelent);
a737bd4d 29107
325801bd 29108 reloc->sym_ptr_ptr = XNEW (asymbol *);
c19d1205
ZW		 29109 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
29110 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 29111
2fc8bdac 29112 if (fixp->fx_pcrel)
00a97672
RS		 29113 {
29114 if (section->use_rela_p)
29115 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
29116 else
29117 fixp->fx_offset = reloc->address;
29118 }
c19d1205 29119 reloc->addend = fixp->fx_offset;
a737bd4d 29120
c19d1205 29121 switch (fixp->fx_r_type)
a737bd4d 29122 {
c19d1205
ZW		 29123 case BFD_RELOC_8:
29124 if (fixp->fx_pcrel)
29125 {
29126 code = BFD_RELOC_8_PCREL;
29127 break;
29128 }
1a0670f3 29129 /* Fall through. */
a737bd4d 29130
c19d1205
ZW		 29131 case BFD_RELOC_16:
29132 if (fixp->fx_pcrel)
29133 {
29134 code = BFD_RELOC_16_PCREL;
29135 break;
29136 }
1a0670f3 29137 /* Fall through. */
6c43fab6 29138
c19d1205
ZW		 29139 case BFD_RELOC_32:
29140 if (fixp->fx_pcrel)
29141 {
29142 code = BFD_RELOC_32_PCREL;
29143 break;
29144 }
1a0670f3 29145 /* Fall through. */
a737bd4d 29146
b6895b4f
PB		 29147 case BFD_RELOC_ARM_MOVW:
29148 if (fixp->fx_pcrel)
29149 {
29150 code = BFD_RELOC_ARM_MOVW_PCREL;
29151 break;
29152 }
1a0670f3 29153 /* Fall through. */
b6895b4f
PB		 29154
29155 case BFD_RELOC_ARM_MOVT:
29156 if (fixp->fx_pcrel)
29157 {
29158 code = BFD_RELOC_ARM_MOVT_PCREL;
29159 break;
29160 }
1a0670f3 29161 /* Fall through. */
b6895b4f
PB		 29162
29163 case BFD_RELOC_ARM_THUMB_MOVW:
29164 if (fixp->fx_pcrel)
29165 {
29166 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
29167 break;
29168 }
1a0670f3 29169 /* Fall through. */
b6895b4f
PB		 29170
29171 case BFD_RELOC_ARM_THUMB_MOVT:
29172 if (fixp->fx_pcrel)
29173 {
29174 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
29175 break;
29176 }
1a0670f3 29177 /* Fall through. */
b6895b4f 29178
c19d1205
ZW		 29179 case BFD_RELOC_NONE:
29180 case BFD_RELOC_ARM_PCREL_BRANCH:
29181 case BFD_RELOC_ARM_PCREL_BLX:
29182 case BFD_RELOC_RVA:
29183 case BFD_RELOC_THUMB_PCREL_BRANCH7:
29184 case BFD_RELOC_THUMB_PCREL_BRANCH9:
29185 case BFD_RELOC_THUMB_PCREL_BRANCH12:
29186 case BFD_RELOC_THUMB_PCREL_BRANCH20:
29187 case BFD_RELOC_THUMB_PCREL_BRANCH23:
29188 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW		 29189 case BFD_RELOC_VTABLE_ENTRY:
29190 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC		 29191#ifdef TE_PE
29192 case BFD_RELOC_32_SECREL:
29193#endif
c19d1205
ZW		 29194 code = fixp->fx_r_type;
29195 break;
a737bd4d 29196
00adf2d4
JB		 29197 case BFD_RELOC_THUMB_PCREL_BLX:
29198#ifdef OBJ_ELF
29199 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
29200 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
29201 else
29202#endif
29203 code = BFD_RELOC_THUMB_PCREL_BLX;
29204 break;
29205
c19d1205
ZW		 29206 case BFD_RELOC_ARM_LITERAL:
29207 case BFD_RELOC_ARM_HWLITERAL:
29208 /* If this is called then the a literal has
29209 been referenced across a section boundary. */
29210 as_bad_where (fixp->fx_file, fixp->fx_line,
29211 _("literal referenced across section boundary"));
29212 return NULL;
a737bd4d 29213
c19d1205 29214#ifdef OBJ_ELF
0855e32b
NS		 29215 case BFD_RELOC_ARM_TLS_CALL:
29216 case BFD_RELOC_ARM_THM_TLS_CALL:
29217 case BFD_RELOC_ARM_TLS_DESCSEQ:
29218 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
c19d1205
ZW		 29219 case BFD_RELOC_ARM_GOT32:
29220 case BFD_RELOC_ARM_GOTOFF:
b43420e6 29221 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW		 29222 case BFD_RELOC_ARM_PLT32:
29223 case BFD_RELOC_ARM_TARGET1:
29224 case BFD_RELOC_ARM_ROSEGREL32:
29225 case BFD_RELOC_ARM_SBREL32:
29226 case BFD_RELOC_ARM_PREL31:
29227 case BFD_RELOC_ARM_TARGET2:
c19d1205 29228 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB		 29229 case BFD_RELOC_ARM_PCREL_CALL:
29230 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS		 29231 case BFD_RELOC_ARM_ALU_PC_G0_NC:
29232 case BFD_RELOC_ARM_ALU_PC_G0:
29233 case BFD_RELOC_ARM_ALU_PC_G1_NC:
29234 case BFD_RELOC_ARM_ALU_PC_G1:
29235 case BFD_RELOC_ARM_ALU_PC_G2:
29236 case BFD_RELOC_ARM_LDR_PC_G0:
29237 case BFD_RELOC_ARM_LDR_PC_G1:
29238 case BFD_RELOC_ARM_LDR_PC_G2:
29239 case BFD_RELOC_ARM_LDRS_PC_G0:
29240 case BFD_RELOC_ARM_LDRS_PC_G1:
29241 case BFD_RELOC_ARM_LDRS_PC_G2:
29242 case BFD_RELOC_ARM_LDC_PC_G0:
29243 case BFD_RELOC_ARM_LDC_PC_G1:
29244 case BFD_RELOC_ARM_LDC_PC_G2:
29245 case BFD_RELOC_ARM_ALU_SB_G0_NC:
29246 case BFD_RELOC_ARM_ALU_SB_G0:
29247 case BFD_RELOC_ARM_ALU_SB_G1_NC:
29248 case BFD_RELOC_ARM_ALU_SB_G1:
29249 case BFD_RELOC_ARM_ALU_SB_G2:
29250 case BFD_RELOC_ARM_LDR_SB_G0:
29251 case BFD_RELOC_ARM_LDR_SB_G1:
29252 case BFD_RELOC_ARM_LDR_SB_G2:
29253 case BFD_RELOC_ARM_LDRS_SB_G0:
29254 case BFD_RELOC_ARM_LDRS_SB_G1:
29255 case BFD_RELOC_ARM_LDRS_SB_G2:
29256 case BFD_RELOC_ARM_LDC_SB_G0:
29257 case BFD_RELOC_ARM_LDC_SB_G1:
29258 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 29259 case BFD_RELOC_ARM_V4BX:
72d98d16
MG		 29260 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
29261 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
29262 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
29263 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
188fd7ae
CL		 29264 case BFD_RELOC_ARM_GOTFUNCDESC:
29265 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
29266 case BFD_RELOC_ARM_FUNCDESC:
e5d6e09e 29267 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 29268 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 29269 case BFD_RELOC_ARM_THUMB_BF13:
c19d1205
ZW		 29270 code = fixp->fx_r_type;
29271 break;
a737bd4d 29272
0855e32b 29273 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205 29274 case BFD_RELOC_ARM_TLS_GD32:
5c5a4843 29275 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
75c11999 29276 case BFD_RELOC_ARM_TLS_LE32:
c19d1205 29277 case BFD_RELOC_ARM_TLS_IE32:
5c5a4843 29278 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
c19d1205 29279 case BFD_RELOC_ARM_TLS_LDM32:
5c5a4843 29280 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
c19d1205
ZW		 29281 /* BFD will include the symbol's address in the addend.
29282 But we don't want that, so subtract it out again here. */
29283 if (!S_IS_COMMON (fixp->fx_addsy))
29284 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
29285 code = fixp->fx_r_type;
29286 break;
29287#endif
a737bd4d 29288
c19d1205
ZW		 29289 case BFD_RELOC_ARM_IMMEDIATE:
29290 as_bad_where (fixp->fx_file, fixp->fx_line,
29291 _("internal relocation (type: IMMEDIATE) not fixed up"));
29292 return NULL;
a737bd4d 29293
c19d1205
ZW		 29294 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
29295 as_bad_where (fixp->fx_file, fixp->fx_line,
29296 _("ADRL used for a symbol not defined in the same file"));
29297 return NULL;
a737bd4d 29298
e12437dc 29299 case BFD_RELOC_THUMB_PCREL_BRANCH5:
f6b2b12d 29300 case BFD_RELOC_THUMB_PCREL_BFCSEL:
60f993ce 29301 case BFD_RELOC_ARM_THUMB_LOOP12:
e12437dc
AV		 29302 as_bad_where (fixp->fx_file, fixp->fx_line,
29303 _("%s used for a symbol not defined in the same file"),
29304 bfd_get_reloc_code_name (fixp->fx_r_type));
29305 return NULL;
29306
c19d1205 29307 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 29308 if (section->use_rela_p)
29309 {
29310 code = fixp->fx_r_type;
29311 break;
29312 }
29313
c19d1205
ZW		 29314 if (fixp->fx_addsy != NULL
29315 && !S_IS_DEFINED (fixp->fx_addsy)
29316 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 29317 {
c19d1205
ZW		 29318 as_bad_where (fixp->fx_file, fixp->fx_line,
29319 _("undefined local label `%s'"),
29320 S_GET_NAME (fixp->fx_addsy));
29321 return NULL;
a737bd4d
NC		 29322 }
29323
c19d1205
ZW		 29324 as_bad_where (fixp->fx_file, fixp->fx_line,
29325 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29326 return NULL;
a737bd4d 29327
c19d1205
ZW		 29328 default:
29329 {
e0471c16 29330 const char * type;
6c43fab6 29331
c19d1205
ZW		 29332 switch (fixp->fx_r_type)
29333 {
29334 case BFD_RELOC_NONE: type = "NONE"; break;
29335 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
29336 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 29337 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW		 29338 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
29339 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
29340 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
db187cb9 29341 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
8f06b2d8 29342 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW		 29343 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
29344 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
29345 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
29346 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
29347 default: type = _("<unknown>"); break;
29348 }
29349 as_bad_where (fixp->fx_file, fixp->fx_line,
29350 _("cannot represent %s relocation in this object file format"),
29351 type);
29352 return NULL;
29353 }
a737bd4d 29354 }
6c43fab6 29355
c19d1205
ZW		 29356#ifdef OBJ_ELF
29357 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
29358 && GOT_symbol
29359 && fixp->fx_addsy == GOT_symbol)
29360 {
29361 code = BFD_RELOC_ARM_GOTPC;
29362 reloc->addend = fixp->fx_offset = reloc->address;
29363 }
29364#endif
6c43fab6 29365
c19d1205 29366 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 29367
c19d1205
ZW		 29368 if (reloc->howto == NULL)
29369 {
29370 as_bad_where (fixp->fx_file, fixp->fx_line,
29371 _("cannot represent %s relocation in this object file format"),
29372 bfd_get_reloc_code_name (code));
29373 return NULL;
29374 }
6c43fab6 29375
c19d1205
ZW		 29376 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29377 vtable entry to be used in the relocation's section offset. */
29378 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
29379 reloc->address = fixp->fx_offset;
6c43fab6 29380
c19d1205 29381 return reloc;
6c43fab6
RE		 29382}
29383
c19d1205 29384/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 29385
c19d1205
ZW		 29386void
29387cons_fix_new_arm (fragS * frag,
29388 int where,
29389 int size,
62ebcb5c
AM		 29390 expressionS * exp,
29391 bfd_reloc_code_real_type reloc)
6c43fab6 29392{
c19d1205 29393 int pcrel = 0;
6c43fab6 29394
c19d1205
ZW		 29395 /* Pick a reloc.
29396 FIXME: @@ Should look at CPU word size. */
29397 switch (size)
29398 {
29399 case 1:
62ebcb5c 29400 reloc = BFD_RELOC_8;
c19d1205
ZW		 29401 break;
29402 case 2:
62ebcb5c 29403 reloc = BFD_RELOC_16;
c19d1205
ZW		 29404 break;
29405 case 4:
29406 default:
62ebcb5c 29407 reloc = BFD_RELOC_32;
c19d1205
ZW		 29408 break;
29409 case 8:
62ebcb5c 29410 reloc = BFD_RELOC_64;
c19d1205
ZW		 29411 break;
29412 }
6c43fab6 29413
f0927246
NC		 29414#ifdef TE_PE
29415 if (exp->X_op == O_secrel)
29416 {
29417 exp->X_op = O_symbol;
62ebcb5c 29418 reloc = BFD_RELOC_32_SECREL;
f0927246
NC		 29419 }
29420#endif
29421
62ebcb5c 29422 fix_new_exp (frag, where, size, exp, pcrel, reloc);
c19d1205 29423}
6c43fab6 29424
4343666d 29425#if defined (OBJ_COFF)
c19d1205
ZW		 29426void
29427arm_validate_fix (fixS * fixP)
6c43fab6 29428{
c19d1205
ZW		 29429 /* If the destination of the branch is a defined symbol which does not have
29430 the THUMB_FUNC attribute, then we must be calling a function which has
29431 the (interfacearm) attribute. We look for the Thumb entry point to that
29432 function and change the branch to refer to that function instead. */
29433 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
29434 && fixP->fx_addsy != NULL
29435 && S_IS_DEFINED (fixP->fx_addsy)
29436 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 29437 {
c19d1205 29438 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 29439 }
c19d1205
ZW		 29440}
29441#endif
6c43fab6 29442
267bf995 29443
c19d1205
ZW		 29444int
29445arm_force_relocation (struct fix * fixp)
29446{
29447#if defined (OBJ_COFF) && defined (TE_PE)
29448 if (fixp->fx_r_type == BFD_RELOC_RVA)
29449 return 1;
29450#endif
6c43fab6 29451
267bf995
RR		 29452 /* In case we have a call or a branch to a function in ARM ISA mode from
29453 a thumb function or vice-versa force the relocation. These relocations
29454 are cleared off for some cores that might have blx and simple transformations
29455 are possible. */
29456
29457#ifdef OBJ_ELF
29458 switch (fixp->fx_r_type)
29459 {
29460 case BFD_RELOC_ARM_PCREL_JUMP:
29461 case BFD_RELOC_ARM_PCREL_CALL:
29462 case BFD_RELOC_THUMB_PCREL_BLX:
29463 if (THUMB_IS_FUNC (fixp->fx_addsy))
29464 return 1;
29465 break;
29466
29467 case BFD_RELOC_ARM_PCREL_BLX:
29468 case BFD_RELOC_THUMB_PCREL_BRANCH25:
29469 case BFD_RELOC_THUMB_PCREL_BRANCH20:
29470 case BFD_RELOC_THUMB_PCREL_BRANCH23:
29471 if (ARM_IS_FUNC (fixp->fx_addsy))
29472 return 1;
29473 break;
29474
29475 default:
29476 break;
29477 }
29478#endif
29479
b5884301
PB		 29480 /* Resolve these relocations even if the symbol is extern or weak.
29481 Technically this is probably wrong due to symbol preemption.
29482 In practice these relocations do not have enough range to be useful
29483 at dynamic link time, and some code (e.g. in the Linux kernel)
29484 expects these references to be resolved. */
c19d1205
ZW		 29485 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
29486 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
b5884301 29487 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
0110f2b8 29488 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
b5884301
PB		 29489 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29490 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
29491 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
16805f35 29492 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB		 29493 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
29494 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
b5884301
PB		 29495 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
29496 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
29497 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
29498 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
c19d1205 29499 return 0;
a737bd4d 29500
4962c51a
MS		 29501 /* Always leave these relocations for the linker. */
29502 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29503 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29504 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
29505 return 1;
29506
f0291e4c
PB		 29507 /* Always generate relocations against function symbols. */
29508 if (fixp->fx_r_type == BFD_RELOC_32
29509 && fixp->fx_addsy
29510 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
29511 return 1;
29512
c19d1205 29513 return generic_force_reloc (fixp);
404ff6b5
AH		 29514}
29515
0ffdc86c 29516#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB		 29517/* Relocations against function names must be left unadjusted,
29518 so that the linker can use this information to generate interworking
29519 stubs. The MIPS version of this function
c19d1205
ZW		 29520 also prevents relocations that are mips-16 specific, but I do not
29521 know why it does this.
404ff6b5 29522
c19d1205
ZW		 29523 FIXME:
29524 There is one other problem that ought to be addressed here, but
29525 which currently is not: Taking the address of a label (rather
29526 than a function) and then later jumping to that address. Such
29527 addresses also ought to have their bottom bit set (assuming that
29528 they reside in Thumb code), but at the moment they will not. */
404ff6b5 29529
c19d1205
ZW		 29530bfd_boolean
29531arm_fix_adjustable (fixS * fixP)
404ff6b5 29532{
c19d1205
ZW		 29533 if (fixP->fx_addsy == NULL)
29534 return 1;
404ff6b5 29535
e28387c3
PB		 29536 /* Preserve relocations against symbols with function type. */
29537 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 29538 return FALSE;
e28387c3 29539
c19d1205
ZW		 29540 if (THUMB_IS_FUNC (fixP->fx_addsy)
29541 && fixP->fx_subsy == NULL)
c921be7d 29542 return FALSE;
a737bd4d 29543
c19d1205
ZW		 29544 /* We need the symbol name for the VTABLE entries. */
29545 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
29546 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 29547 return FALSE;
404ff6b5 29548
c19d1205
ZW		 29549 /* Don't allow symbols to be discarded on GOT related relocs. */
29550 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
29551 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
29552 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
29553 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
5c5a4843 29554 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
c19d1205
ZW		 29555 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
29556 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
5c5a4843 29557 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
c19d1205 29558 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
5c5a4843 29559 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
c19d1205 29560 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
0855e32b
NS		 29561 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
29562 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
29563 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
29564 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
29565 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
c19d1205 29566 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 29567 return FALSE;
a737bd4d 29568
4962c51a
MS		 29569 /* Similarly for group relocations. */
29570 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29571 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29572 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 29573 return FALSE;
4962c51a 29574
79947c54
CD		 29575 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29576 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
29577 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
29578 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
29579 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
29580 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
29581 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
29582 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
29583 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 29584 return FALSE;
79947c54 29585
72d98d16
MG		 29586 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29587 offsets, so keep these symbols. */
29588 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29589 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
29590 return FALSE;
29591
c921be7d 29592 return TRUE;
a737bd4d 29593}
0ffdc86c
NC		 29594#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29595
29596#ifdef OBJ_ELF
c19d1205
ZW		 29597const char *
29598elf32_arm_target_format (void)
404ff6b5 29599{
c19d1205
ZW		 29600#ifdef TE_SYMBIAN
29601 return (target_big_endian
29602 ? "elf32-bigarm-symbian"
29603 : "elf32-littlearm-symbian");
29604#elif defined (TE_VXWORKS)
29605 return (target_big_endian
29606 ? "elf32-bigarm-vxworks"
29607 : "elf32-littlearm-vxworks");
b38cadfb
NC		 29608#elif defined (TE_NACL)
29609 return (target_big_endian
29610 ? "elf32-bigarm-nacl"
29611 : "elf32-littlearm-nacl");
c19d1205 29612#else
18a20338
CL		 29613 if (arm_fdpic)
29614 {
29615 if (target_big_endian)
29616 return "elf32-bigarm-fdpic";
29617 else
29618 return "elf32-littlearm-fdpic";
29619 }
c19d1205 29620 else
18a20338
CL		 29621 {
29622 if (target_big_endian)
29623 return "elf32-bigarm";
29624 else
29625 return "elf32-littlearm";
29626 }
c19d1205 29627#endif
404ff6b5
AH		 29628}
29629
c19d1205
ZW		 29630void
29631armelf_frob_symbol (symbolS * symp,
29632 int * puntp)
404ff6b5 29633{
c19d1205
ZW		 29634 elf_frob_symbol (symp, puntp);
29635}
29636#endif
404ff6b5 29637
c19d1205 29638/* MD interface: Finalization. */
a737bd4d 29639
c19d1205
ZW		 29640void
29641arm_cleanup (void)
29642{
29643 literal_pool * pool;
a737bd4d 29644
5ee91343
AV		 29645 /* Ensure that all the predication blocks are properly closed. */
29646 check_pred_blocks_finished ();
e07e6e58 29647
c19d1205
ZW		 29648 for (pool = list_of_pools; pool; pool = pool->next)
29649 {
5f4273c7 29650 /* Put it at the end of the relevant section. */
c19d1205
ZW		 29651 subseg_set (pool->section, pool->sub_section);
29652#ifdef OBJ_ELF
29653 arm_elf_change_section ();
29654#endif
29655 s_ltorg (0);
29656 }
404ff6b5
AH		 29657}
29658
cd000bff
DJ		 29659#ifdef OBJ_ELF
29660/* Remove any excess mapping symbols generated for alignment frags in
29661 SEC. We may have created a mapping symbol before a zero byte
29662 alignment; remove it if there's a mapping symbol after the
29663 alignment. */
29664static void
29665check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
29666 void *dummy ATTRIBUTE_UNUSED)
29667{
29668 segment_info_type *seginfo = seg_info (sec);
29669 fragS *fragp;
29670
29671 if (seginfo == NULL || seginfo->frchainP == NULL)
29672 return;
29673
29674 for (fragp = seginfo->frchainP->frch_root;
29675 fragp != NULL;
29676 fragp = fragp->fr_next)
29677 {
29678 symbolS *sym = fragp->tc_frag_data.last_map;
29679 fragS *next = fragp->fr_next;
29680
29681 /* Variable-sized frags have been converted to fixed size by
29682 this point. But if this was variable-sized to start with,
29683 there will be a fixed-size frag after it. So don't handle
29684 next == NULL. */
29685 if (sym == NULL || next == NULL)
29686 continue;
29687
29688 if (S_GET_VALUE (sym) < next->fr_address)
29689 /* Not at the end of this frag. */
29690 continue;
29691 know (S_GET_VALUE (sym) == next->fr_address);
29692
29693 do
29694 {
29695 if (next->tc_frag_data.first_map != NULL)
29696 {
29697 /* Next frag starts with a mapping symbol. Discard this
29698 one. */
29699 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29700 break;
29701 }
29702
29703 if (next->fr_next == NULL)
29704 {
29705 /* This mapping symbol is at the end of the section. Discard
29706 it. */
29707 know (next->fr_fix == 0 && next->fr_var == 0);
29708 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29709 break;
29710 }
29711
29712 /* As long as we have empty frags without any mapping symbols,
29713 keep looking. */
29714 /* If the next frag is non-empty and does not start with a
29715 mapping symbol, then this mapping symbol is required. */
29716 if (next->fr_address != next->fr_next->fr_address)
29717 break;
29718
29719 next = next->fr_next;
29720 }
29721 while (next != NULL);
29722 }
29723}
29724#endif
29725
c19d1205
ZW		 29726/* Adjust the symbol table. This marks Thumb symbols as distinct from
29727 ARM ones. */
404ff6b5 29728
c19d1205
ZW		 29729void
29730arm_adjust_symtab (void)
404ff6b5 29731{
c19d1205
ZW		 29732#ifdef OBJ_COFF
29733 symbolS * sym;
404ff6b5 29734
c19d1205
ZW		 29735 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
29736 {
29737 if (ARM_IS_THUMB (sym))
29738 {
29739 if (THUMB_IS_FUNC (sym))
29740 {
29741 /* Mark the symbol as a Thumb function. */
29742 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
29743 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
29744 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 29745
c19d1205
ZW		 29746 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
29747 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
29748 else
29749 as_bad (_("%s: unexpected function type: %d"),
29750 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
29751 }
29752 else switch (S_GET_STORAGE_CLASS (sym))
29753 {
29754 case C_EXT:
29755 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
29756 break;
29757 case C_STAT:
29758 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
29759 break;
29760 case C_LABEL:
29761 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
29762 break;
29763 default:
29764 /* Do nothing. */
29765 break;
29766 }
29767 }
a737bd4d 29768
c19d1205
ZW		 29769 if (ARM_IS_INTERWORK (sym))
29770 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 29771 }
c19d1205
ZW		 29772#endif
29773#ifdef OBJ_ELF
29774 symbolS * sym;
29775 char bind;
404ff6b5 29776
c19d1205 29777 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 29778 {
c19d1205
ZW		 29779 if (ARM_IS_THUMB (sym))
29780 {
29781 elf_symbol_type * elf_sym;
404ff6b5 29782
c19d1205
ZW		 29783 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
29784 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 29785
b0796911
PB		 29786 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
29787 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW		 29788 {
29789 /* If it's a .thumb_func, declare it as so,
29790 otherwise tag label as .code 16. */
29791 if (THUMB_IS_FUNC (sym))
39d911fc
TP		 29792 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
29793 ST_BRANCH_TO_THUMB);
3ba67470 29794 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW		 29795 elf_sym->internal_elf_sym.st_info =
29796 ELF_ST_INFO (bind, STT_ARM_16BIT);
29797 }
29798 }
29799 }
cd000bff
DJ		 29800
29801 /* Remove any overlapping mapping symbols generated by alignment frags. */
29802 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
709001e9
MM		 29803 /* Now do generic ELF adjustments. */
29804 elf_adjust_symtab ();
c19d1205 29805#endif
404ff6b5
AH		 29806}
29807
c19d1205 29808/* MD interface: Initialization. */
404ff6b5 29809
a737bd4d 29810static void
c19d1205 29811set_constant_flonums (void)
a737bd4d 29812{
c19d1205 29813 int i;
404ff6b5 29814
c19d1205
ZW		 29815 for (i = 0; i < NUM_FLOAT_VALS; i++)
29816 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
29817 abort ();
a737bd4d 29818}
404ff6b5 29819
3e9e4fcf
JB		 29820/* Auto-select Thumb mode if it's the only available instruction set for the
29821 given architecture. */
29822
29823static void
29824autoselect_thumb_from_cpu_variant (void)
29825{
29826 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
29827 opcode_select (16);
29828}
29829
c19d1205
ZW		 29830void
29831md_begin (void)
a737bd4d 29832{
c19d1205
ZW		 29833 unsigned mach;
29834 unsigned int i;
404ff6b5 29835
c19d1205
ZW		 29836 if ( (arm_ops_hsh = hash_new ()) == NULL
29837 || (arm_cond_hsh = hash_new ()) == NULL
5ee91343 29838 || (arm_vcond_hsh = hash_new ()) == NULL
c19d1205
ZW		 29839 || (arm_shift_hsh = hash_new ()) == NULL
29840 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 29841 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 29842 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB		 29843 || (arm_reloc_hsh = hash_new ()) == NULL
29844 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW		 29845 as_fatal (_("virtual memory exhausted"));
29846
29847 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 29848 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 29849 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 29850 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
5ee91343
AV		 29851 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
29852 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
c19d1205 29853 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 29854 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 29855 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 29856 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 29857 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 29858 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
477330fc 29859 (void *) (v7m_psrs + i));
c19d1205 29860 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 29861 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB		 29862 for (i = 0;
29863 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
29864 i++)
d3ce72d0 29865 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 29866 (void *) (barrier_opt_names + i));
c19d1205 29867#ifdef OBJ_ELF
3da1d841
NC		 29868 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
29869 {
29870 struct reloc_entry * entry = reloc_names + i;
29871
29872 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
29873 /* This makes encode_branch() use the EABI versions of this relocation. */
29874 entry->reloc = BFD_RELOC_UNUSED;
29875
29876 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
29877 }
c19d1205
ZW		 29878#endif
29879
29880 set_constant_flonums ();
404ff6b5 29881
c19d1205
ZW		 29882 /* Set the cpu variant based on the command-line options. We prefer
29883 -mcpu= over -march= if both are set (as for GCC); and we prefer
29884 -mfpu= over any other way of setting the floating point unit.
29885 Use of legacy options with new options are faulted. */
e74cfd16 29886 if (legacy_cpu)
404ff6b5 29887 {
e74cfd16 29888 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW		 29889 as_bad (_("use of old and new-style options to set CPU type"));
29890
4d354d8b 29891 selected_arch = *legacy_cpu;
404ff6b5 29892 }
4d354d8b
TP		 29893 else if (mcpu_cpu_opt)
29894 {
29895 selected_arch = *mcpu_cpu_opt;
29896 selected_ext = *mcpu_ext_opt;
29897 }
29898 else if (march_cpu_opt)
c168ce07 29899 {
4d354d8b
TP		 29900 selected_arch = *march_cpu_opt;
29901 selected_ext = *march_ext_opt;
c168ce07 29902 }
4d354d8b 29903 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
404ff6b5 29904
e74cfd16 29905 if (legacy_fpu)
c19d1205 29906 {
e74cfd16 29907 if (mfpu_opt)
c19d1205 29908 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f 29909
4d354d8b 29910 selected_fpu = *legacy_fpu;
03b1477f 29911 }
4d354d8b
TP		 29912 else if (mfpu_opt)
29913 selected_fpu = *mfpu_opt;
29914 else
03b1477f 29915 {
45eb4c1b
NS		 29916#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29917 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE		 29918 /* Some environments specify a default FPU. If they don't, infer it
29919 from the processor. */
e74cfd16 29920 if (mcpu_fpu_opt)
4d354d8b 29921 selected_fpu = *mcpu_fpu_opt;
e7da50fa 29922 else if (march_fpu_opt)
4d354d8b 29923 selected_fpu = *march_fpu_opt;
39c2da32 29924#else
4d354d8b 29925 selected_fpu = fpu_default;
39c2da32 29926#endif
03b1477f
RE		 29927 }
29928
4d354d8b 29929 if (ARM_FEATURE_ZERO (selected_fpu))
03b1477f 29930 {
4d354d8b
TP		 29931 if (!no_cpu_selected ())
29932 selected_fpu = fpu_default;
03b1477f 29933 else
4d354d8b 29934 selected_fpu = fpu_arch_fpa;
03b1477f
RE		 29935 }
29936
ee065d83 29937#ifdef CPU_DEFAULT
4d354d8b 29938 if (ARM_FEATURE_ZERO (selected_arch))
ee065d83 29939 {
4d354d8b
TP		 29940 selected_arch = cpu_default;
29941 selected_cpu = selected_arch;
ee065d83 29942 }
4d354d8b 29943 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
e74cfd16 29944#else
4d354d8b
TP		 29945 /* Autodection of feature mode: allow all features in cpu_variant but leave
29946 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29947 after all instruction have been processed and we can decide what CPU
29948 should be selected. */
29949 if (ARM_FEATURE_ZERO (selected_arch))
29950 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
ee065d83 29951 else
4d354d8b 29952 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83 29953#endif
03b1477f 29954
3e9e4fcf
JB		 29955 autoselect_thumb_from_cpu_variant ();
29956
e74cfd16 29957 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 29958
f17c130b 29959#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 29960 {
7cc69913
NC		 29961 unsigned int flags = 0;
29962
29963#if defined OBJ_ELF
29964 flags = meabi_flags;
d507cf36
PB		 29965
29966 switch (meabi_flags)
33a392fb 29967 {
d507cf36 29968 case EF_ARM_EABI_UNKNOWN:
7cc69913 29969#endif
d507cf36
PB		 29970 /* Set the flags in the private structure. */
29971 if (uses_apcs_26) flags |= F_APCS26;
29972 if (support_interwork) flags |= F_INTERWORK;
29973 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 29974 if (pic_code) flags |= F_PIC;
e74cfd16 29975 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC		 29976 flags |= F_SOFT_FLOAT;
29977
d507cf36
PB		 29978 switch (mfloat_abi_opt)
29979 {
29980 case ARM_FLOAT_ABI_SOFT:
29981 case ARM_FLOAT_ABI_SOFTFP:
29982 flags |= F_SOFT_FLOAT;
29983 break;
33a392fb 29984
d507cf36
PB		 29985 case ARM_FLOAT_ABI_HARD:
29986 if (flags & F_SOFT_FLOAT)
29987 as_bad (_("hard-float conflicts with specified fpu"));
29988 break;
29989 }
03b1477f 29990
e74cfd16
PB		 29991 /* Using pure-endian doubles (even if soft-float). */
29992 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 29993 flags |= F_VFP_FLOAT;
f17c130b 29994
fde78edd 29995#if defined OBJ_ELF
e74cfd16 29996 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 29997 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB		 29998 break;
29999
8cb51566 30000 case EF_ARM_EABI_VER4:
3a4a14e9 30001 case EF_ARM_EABI_VER5:
c19d1205 30002 /* No additional flags to set. */
d507cf36
PB		 30003 break;
30004
30005 default:
30006 abort ();
30007 }
7cc69913 30008#endif
b99bd4ef
NC		 30009 bfd_set_private_flags (stdoutput, flags);
30010
30011 /* We have run out flags in the COFF header to encode the
30012 status of ATPCS support, so instead we create a dummy,
c19d1205 30013 empty, debug section called .arm.atpcs. */
b99bd4ef
NC		 30014 if (atpcs)
30015 {
30016 asection * sec;
30017
30018 sec = bfd_make_section (stdoutput, ".arm.atpcs");
30019
30020 if (sec != NULL)
30021 {
30022 bfd_set_section_flags
30023 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
30024 bfd_set_section_size (stdoutput, sec, 0);
30025 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
30026 }
30027 }
7cc69913 30028 }
f17c130b 30029#endif
b99bd4ef
NC		 30030
30031 /* Record the CPU type as well. */
2d447fca
JM		 30032 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
30033 mach = bfd_mach_arm_iWMMXt2;
30034 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 30035 mach = bfd_mach_arm_iWMMXt;
e74cfd16 30036 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 30037 mach = bfd_mach_arm_XScale;
e74cfd16 30038 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 30039 mach = bfd_mach_arm_ep9312;
e74cfd16 30040 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 30041 mach = bfd_mach_arm_5TE;
e74cfd16 30042 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 30043 {
e74cfd16 30044 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 30045 mach = bfd_mach_arm_5T;
30046 else
30047 mach = bfd_mach_arm_5;
30048 }
e74cfd16 30049 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 30050 {
e74cfd16 30051 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 30052 mach = bfd_mach_arm_4T;
30053 else
30054 mach = bfd_mach_arm_4;
30055 }
e74cfd16 30056 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 30057 mach = bfd_mach_arm_3M;
e74cfd16
PB		 30058 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
30059 mach = bfd_mach_arm_3;
30060 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
30061 mach = bfd_mach_arm_2a;
30062 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
30063 mach = bfd_mach_arm_2;
30064 else
30065 mach = bfd_mach_arm_unknown;
b99bd4ef
NC		 30066
30067 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
30068}
30069
c19d1205 30070/* Command line processing. */
b99bd4ef 30071
c19d1205
ZW		 30072/* md_parse_option
30073 Invocation line includes a switch not recognized by the base assembler.
30074 See if it's a processor-specific option.
b99bd4ef 30075
c19d1205
ZW		 30076 This routine is somewhat complicated by the need for backwards
30077 compatibility (since older releases of gcc can't be changed).
30078 The new options try to make the interface as compatible as
30079 possible with GCC.
b99bd4ef 30080
c19d1205 30081 New options (supported) are:
b99bd4ef 30082
c19d1205
ZW		 30083 -mcpu=<cpu name> Assemble for selected processor
30084 -march=<architecture name> Assemble for selected architecture
30085 -mfpu=<fpu architecture> Assemble for selected FPU.
30086 -EB/-mbig-endian Big-endian
30087 -EL/-mlittle-endian Little-endian
30088 -k Generate PIC code
30089 -mthumb Start in Thumb mode
30090 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 30091
278df34e 30092 -m[no-]warn-deprecated Warn about deprecated features
8b2d793c 30093 -m[no-]warn-syms Warn when symbols match instructions
267bf995 30094
c19d1205 30095 For now we will also provide support for:
b99bd4ef 30096
c19d1205
ZW		 30097 -mapcs-32 32-bit Program counter
30098 -mapcs-26 26-bit Program counter
30099 -macps-float Floats passed in FP registers
30100 -mapcs-reentrant Reentrant code
30101 -matpcs
30102 (sometime these will probably be replaced with -mapcs=<list of options>
30103 and -matpcs=<list of options>)
b99bd4ef 30104
c19d1205
ZW		 30105 The remaining options are only supported for back-wards compatibility.
30106 Cpu variants, the arm part is optional:
30107 -m[arm]1 Currently not supported.
30108 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30109 -m[arm]3 Arm 3 processor
30110 -m[arm]6[xx], Arm 6 processors
30111 -m[arm]7[xx][t][[d]m] Arm 7 processors
30112 -m[arm]8[10] Arm 8 processors
30113 -m[arm]9[20][tdmi] Arm 9 processors
30114 -mstrongarm[110[0]] StrongARM processors
30115 -mxscale XScale processors
30116 -m[arm]v[2345[t[e]]] Arm architectures
30117 -mall All (except the ARM1)
30118 FP variants:
30119 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30120 -mfpe-old (No float load/store multiples)
30121 -mvfpxd VFP Single precision
30122 -mvfp All VFP
30123 -mno-fpu Disable all floating point instructions
b99bd4ef 30124
c19d1205
ZW		 30125 The following CPU names are recognized:
30126 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30127 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30128 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30129 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30130 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30131 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30132 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 30133
c19d1205 30134 */
b99bd4ef 30135
c19d1205 30136const char * md_shortopts = "m:k";
b99bd4ef 30137
c19d1205
ZW		 30138#ifdef ARM_BI_ENDIAN
30139#define OPTION_EB (OPTION_MD_BASE + 0)
30140#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 30141#else
c19d1205
ZW		 30142#if TARGET_BYTES_BIG_ENDIAN
30143#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 30144#else
c19d1205
ZW		 30145#define OPTION_EL (OPTION_MD_BASE + 1)
30146#endif
b99bd4ef 30147#endif
845b51d6 30148#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
18a20338 30149#define OPTION_FDPIC (OPTION_MD_BASE + 3)
b99bd4ef 30150
c19d1205 30151struct option md_longopts[] =
b99bd4ef 30152{
c19d1205
ZW		 30153#ifdef OPTION_EB
30154 {"EB", no_argument, NULL, OPTION_EB},
30155#endif
30156#ifdef OPTION_EL
30157 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 30158#endif
845b51d6 30159 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
18a20338
CL		 30160#ifdef OBJ_ELF
30161 {"fdpic", no_argument, NULL, OPTION_FDPIC},
30162#endif
c19d1205
ZW		 30163 {NULL, no_argument, NULL, 0}
30164};
b99bd4ef 30165
c19d1205 30166size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 30167
c19d1205 30168struct arm_option_table
b99bd4ef 30169{
0198d5e6
TC		 30170 const char * option; /* Option name to match. */
30171 const char * help; /* Help information. */
30172 int * var; /* Variable to change. */
30173 int value; /* What to change it to. */
30174 const char * deprecated; /* If non-null, print this message. */
c19d1205 30175};
b99bd4ef 30176
c19d1205
ZW		 30177struct arm_option_table arm_opts[] =
30178{
30179 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
30180 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
30181 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30182 &support_interwork, 1, NULL},
30183 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
30184 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
30185 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
30186 1, NULL},
30187 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
30188 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
30189 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
30190 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
30191 NULL},
b99bd4ef 30192
c19d1205
ZW		 30193 /* These are recognized by the assembler, but have no affect on code. */
30194 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
30195 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS		 30196
30197 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
30198 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30199 &warn_on_deprecated, 0, NULL},
8b2d793c
NC		 30200 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
30201 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
e74cfd16
PB		 30202 {NULL, NULL, NULL, 0, NULL}
30203};
30204
30205struct arm_legacy_option_table
30206{
0198d5e6
TC		 30207 const char * option; /* Option name to match. */
30208 const arm_feature_set ** var; /* Variable to change. */
30209 const arm_feature_set value; /* What to change it to. */
30210 const char * deprecated; /* If non-null, print this message. */
e74cfd16 30211};
b99bd4ef 30212
e74cfd16
PB		 30213const struct arm_legacy_option_table arm_legacy_opts[] =
30214{
c19d1205
ZW		 30215 /* DON'T add any new processors to this list -- we want the whole list
30216 to go away... Add them to the processors table instead. */
e74cfd16
PB		 30217 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
30218 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
30219 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
30220 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
30221 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
30222 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
30223 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
30224 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
30225 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
30226 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
30227 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
30228 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
30229 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
30230 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
30231 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
30232 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
30233 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
30234 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
30235 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
30236 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
30237 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
30238 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
30239 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
30240 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
30241 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
30242 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
30243 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
30244 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
30245 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
30246 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
30247 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
30248 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
30249 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
30250 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
30251 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
30252 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
30253 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
30254 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
30255 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
30256 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
30257 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
30258 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
30259 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
30260 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
30261 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
30262 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
30263 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30264 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30265 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30266 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30267 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
30268 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
30269 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
30270 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
30271 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
30272 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
30273 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
30274 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
30275 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
30276 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
30277 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
30278 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
30279 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
30280 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
30281 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
30282 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
30283 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
30284 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
30285 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
30286 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30287 N_("use -mcpu=strongarm110")},
e74cfd16 30288 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30289 N_("use -mcpu=strongarm1100")},
e74cfd16 30290 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30291 N_("use -mcpu=strongarm1110")},
e74cfd16
PB		 30292 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
30293 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
30294 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 30295
c19d1205 30296 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB		 30297 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
30298 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
30299 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
30300 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
30301 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
30302 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
30303 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
30304 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
30305 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
30306 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
30307 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
30308 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
30309 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
30310 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
30311 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
30312 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
30313 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
30314 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 30315
c19d1205 30316 /* Floating point variants -- don't add any more to this list either. */
0198d5e6
TC		 30317 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
30318 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
30319 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
30320 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 30321 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 30322
e74cfd16 30323 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 30324};
7ed4c4c5 30325
c19d1205 30326struct arm_cpu_option_table
7ed4c4c5 30327{
0198d5e6
TC		 30328 const char * name;
30329 size_t name_len;
30330 const arm_feature_set value;
30331 const arm_feature_set ext;
c19d1205
ZW		 30332 /* For some CPUs we assume an FPU unless the user explicitly sets
30333 -mfpu=... */
0198d5e6 30334 const arm_feature_set default_fpu;
ee065d83
PB		 30335 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30336 case. */
0198d5e6 30337 const char * canonical_name;
c19d1205 30338};
7ed4c4c5 30339
c19d1205
ZW		 30340/* This list should, at a minimum, contain all the cpu names
30341 recognized by GCC. */
996b5569 30342#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
0198d5e6 30343
e74cfd16 30344static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 30345{
996b5569
TP		 30346 ARM_CPU_OPT ("all", NULL, ARM_ANY,
30347 ARM_ARCH_NONE,
30348 FPU_ARCH_FPA),
30349 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
30350 ARM_ARCH_NONE,
30351 FPU_ARCH_FPA),
30352 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
30353 ARM_ARCH_NONE,
30354 FPU_ARCH_FPA),
30355 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
30356 ARM_ARCH_NONE,
30357 FPU_ARCH_FPA),
30358 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
30359 ARM_ARCH_NONE,
30360 FPU_ARCH_FPA),
30361 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
30362 ARM_ARCH_NONE,
30363 FPU_ARCH_FPA),
30364 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
30365 ARM_ARCH_NONE,
30366 FPU_ARCH_FPA),
30367 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
30368 ARM_ARCH_NONE,
30369 FPU_ARCH_FPA),
30370 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
30371 ARM_ARCH_NONE,
30372 FPU_ARCH_FPA),
30373 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
30374 ARM_ARCH_NONE,
30375 FPU_ARCH_FPA),
30376 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
30377 ARM_ARCH_NONE,
30378 FPU_ARCH_FPA),
30379 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
30380 ARM_ARCH_NONE,
30381 FPU_ARCH_FPA),
30382 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
30383 ARM_ARCH_NONE,
30384 FPU_ARCH_FPA),
30385 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
30386 ARM_ARCH_NONE,
30387 FPU_ARCH_FPA),
30388 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
30389 ARM_ARCH_NONE,
30390 FPU_ARCH_FPA),
30391 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
30392 ARM_ARCH_NONE,
30393 FPU_ARCH_FPA),
30394 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
30395 ARM_ARCH_NONE,
30396 FPU_ARCH_FPA),
30397 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
30398 ARM_ARCH_NONE,
30399 FPU_ARCH_FPA),
30400 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
30401 ARM_ARCH_NONE,
30402 FPU_ARCH_FPA),
30403 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
30404 ARM_ARCH_NONE,
30405 FPU_ARCH_FPA),
30406 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
30407 ARM_ARCH_NONE,
30408 FPU_ARCH_FPA),
30409 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
30410 ARM_ARCH_NONE,
30411 FPU_ARCH_FPA),
30412 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
30413 ARM_ARCH_NONE,
30414 FPU_ARCH_FPA),
30415 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
30416 ARM_ARCH_NONE,
30417 FPU_ARCH_FPA),
30418 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
30419 ARM_ARCH_NONE,
30420 FPU_ARCH_FPA),
30421 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
30422 ARM_ARCH_NONE,
30423 FPU_ARCH_FPA),
30424 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
30425 ARM_ARCH_NONE,
30426 FPU_ARCH_FPA),
30427 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
30428 ARM_ARCH_NONE,
30429 FPU_ARCH_FPA),
30430 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
30431 ARM_ARCH_NONE,
30432 FPU_ARCH_FPA),
30433 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
30434 ARM_ARCH_NONE,
30435 FPU_ARCH_FPA),
30436 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
30437 ARM_ARCH_NONE,
30438 FPU_ARCH_FPA),
30439 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
30440 ARM_ARCH_NONE,
30441 FPU_ARCH_FPA),
30442 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
30443 ARM_ARCH_NONE,
30444 FPU_ARCH_FPA),
30445 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
30446 ARM_ARCH_NONE,
30447 FPU_ARCH_FPA),
30448 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
30449 ARM_ARCH_NONE,
30450 FPU_ARCH_FPA),
30451 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
30452 ARM_ARCH_NONE,
30453 FPU_ARCH_FPA),
30454 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
30455 ARM_ARCH_NONE,
30456 FPU_ARCH_FPA),
30457 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
30458 ARM_ARCH_NONE,
30459 FPU_ARCH_FPA),
30460 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
30461 ARM_ARCH_NONE,
30462 FPU_ARCH_FPA),
30463 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
30464 ARM_ARCH_NONE,
30465 FPU_ARCH_FPA),
30466 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
30467 ARM_ARCH_NONE,
30468 FPU_ARCH_FPA),
30469 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
30470 ARM_ARCH_NONE,
30471 FPU_ARCH_FPA),
30472 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
30473 ARM_ARCH_NONE,
30474 FPU_ARCH_FPA),
30475 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
30476 ARM_ARCH_NONE,
30477 FPU_ARCH_FPA),
30478 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
30479 ARM_ARCH_NONE,
30480 FPU_ARCH_FPA),
30481 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
30482 ARM_ARCH_NONE,
30483 FPU_ARCH_FPA),
30484
c19d1205
ZW		 30485 /* For V5 or later processors we default to using VFP; but the user
30486 should really set the FPU type explicitly. */
996b5569
TP		 30487 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
30488 ARM_ARCH_NONE,
30489 FPU_ARCH_VFP_V2),
30490 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
30491 ARM_ARCH_NONE,
30492 FPU_ARCH_VFP_V2),
30493 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30494 ARM_ARCH_NONE,
30495 FPU_ARCH_VFP_V2),
30496 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30497 ARM_ARCH_NONE,
30498 FPU_ARCH_VFP_V2),
30499 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
30500 ARM_ARCH_NONE,
30501 FPU_ARCH_VFP_V2),
30502 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
30503 ARM_ARCH_NONE,
30504 FPU_ARCH_VFP_V2),
30505 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
30506 ARM_ARCH_NONE,
30507 FPU_ARCH_VFP_V2),
30508 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
30509 ARM_ARCH_NONE,
30510 FPU_ARCH_VFP_V2),
30511 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
30512 ARM_ARCH_NONE,
30513 FPU_ARCH_VFP_V2),
30514 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
30515 ARM_ARCH_NONE,
30516 FPU_ARCH_VFP_V2),
30517 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
30518 ARM_ARCH_NONE,
30519 FPU_ARCH_VFP_V2),
30520 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
30521 ARM_ARCH_NONE,
30522 FPU_ARCH_VFP_V2),
30523 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
30524 ARM_ARCH_NONE,
30525 FPU_ARCH_VFP_V1),
30526 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
30527 ARM_ARCH_NONE,
30528 FPU_ARCH_VFP_V1),
30529 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
30530 ARM_ARCH_NONE,
30531 FPU_ARCH_VFP_V2),
30532 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
30533 ARM_ARCH_NONE,
30534 FPU_ARCH_VFP_V2),
30535 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
30536 ARM_ARCH_NONE,
30537 FPU_ARCH_VFP_V1),
30538 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
30539 ARM_ARCH_NONE,
30540 FPU_ARCH_VFP_V2),
30541 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
30542 ARM_ARCH_NONE,
30543 FPU_ARCH_VFP_V2),
30544 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
30545 ARM_ARCH_NONE,
30546 FPU_ARCH_VFP_V2),
30547 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
30548 ARM_ARCH_NONE,
30549 FPU_ARCH_VFP_V2),
30550 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
30551 ARM_ARCH_NONE,
30552 FPU_ARCH_VFP_V2),
30553 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
30554 ARM_ARCH_NONE,
30555 FPU_ARCH_VFP_V2),
30556 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
30557 ARM_ARCH_NONE,
30558 FPU_ARCH_VFP_V2),
30559 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
30560 ARM_ARCH_NONE,
30561 FPU_ARCH_VFP_V2),
30562 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
30563 ARM_ARCH_NONE,
30564 FPU_ARCH_VFP_V2),
30565 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
30566 ARM_ARCH_NONE,
30567 FPU_NONE),
30568 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
30569 ARM_ARCH_NONE,
30570 FPU_NONE),
30571 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
30572 ARM_ARCH_NONE,
30573 FPU_ARCH_VFP_V2),
30574 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
30575 ARM_ARCH_NONE,
30576 FPU_ARCH_VFP_V2),
30577 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
30578 ARM_ARCH_NONE,
30579 FPU_ARCH_VFP_V2),
30580 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
30581 ARM_ARCH_NONE,
30582 FPU_NONE),
30583 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
30584 ARM_ARCH_NONE,
30585 FPU_NONE),
30586 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
30587 ARM_ARCH_NONE,
30588 FPU_ARCH_VFP_V2),
30589 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
30590 ARM_ARCH_NONE,
30591 FPU_NONE),
30592 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
30593 ARM_ARCH_NONE,
30594 FPU_ARCH_VFP_V2),
30595 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
30596 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30597 FPU_NONE),
30598 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
30599 ARM_ARCH_NONE,
30600 FPU_ARCH_NEON_VFP_V4),
30601 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
30602 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30603 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30604 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
30605 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30606 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30607 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
30608 ARM_ARCH_NONE,
30609 FPU_ARCH_NEON_VFP_V4),
30610 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
30611 ARM_ARCH_NONE,
30612 FPU_ARCH_NEON_VFP_V4),
30613 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
30614 ARM_ARCH_NONE,
30615 FPU_ARCH_NEON_VFP_V4),
30616 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
30617 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30618 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30619 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
30620 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30621 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30622 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
30623 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30624 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG		 30625 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
30626 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 30627 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569
TP		 30628 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
30629 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30630 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30631 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
30632 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30633 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30634 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
30635 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30636 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG		 30637 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
30638 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 30639 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
7ebd1359 30640 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
30641 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30642 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
0535e5d7
DZ		 30643 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A,
30644 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30645 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
30646 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A,
30647 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30648 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
ef8df4ca
KT		 30649 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
30650 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30651 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569
TP		 30652 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
30653 ARM_ARCH_NONE,
30654 FPU_NONE),
30655 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
30656 ARM_ARCH_NONE,
30657 FPU_ARCH_VFP_V3D16),
30658 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
30659 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30660 FPU_NONE),
30661 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
30662 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30663 FPU_ARCH_VFP_V3D16),
30664 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
30665 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30666 FPU_ARCH_VFP_V3D16),
0cda1e19
TP		 30667 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
30668 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30669 FPU_ARCH_NEON_VFP_ARMV8),
0535e5d7
DZ		 30670 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN,
30671 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30672 FPU_NONE),
996b5569
TP		 30673 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
30674 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30675 FPU_NONE),
30676 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
30677 ARM_ARCH_NONE,
30678 FPU_NONE),
30679 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
30680 ARM_ARCH_NONE,
30681 FPU_NONE),
30682 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
30683 ARM_ARCH_NONE,
30684 FPU_NONE),
30685 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
30686 ARM_ARCH_NONE,
30687 FPU_NONE),
30688 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
30689 ARM_ARCH_NONE,
30690 FPU_NONE),
30691 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
30692 ARM_ARCH_NONE,
30693 FPU_NONE),
30694 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
30695 ARM_ARCH_NONE,
30696 FPU_NONE),
30697 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
30698 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30699 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
83f43c83
KT		 30700 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
30701 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30702 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
c19d1205 30703 /* ??? XSCALE is really an architecture. */
996b5569
TP		 30704 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
30705 ARM_ARCH_NONE,
30706 FPU_ARCH_VFP_V2),
30707
c19d1205 30708 /* ??? iwmmxt is not a processor. */
996b5569
TP		 30709 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
30710 ARM_ARCH_NONE,
30711 FPU_ARCH_VFP_V2),
30712 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
30713 ARM_ARCH_NONE,
30714 FPU_ARCH_VFP_V2),
30715 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
30716 ARM_ARCH_NONE,
30717 FPU_ARCH_VFP_V2),
30718
0198d5e6 30719 /* Maverick. */
996b5569
TP		 30720 ARM_CPU_OPT ("ep9312", "ARM920T",
30721 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
30722 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
30723
da4339ed 30724 /* Marvell processors. */
996b5569
TP		 30725 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
30726 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30727 FPU_ARCH_VFP_V3D16),
30728 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
30729 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30730 FPU_ARCH_NEON_VFP_V4),
da4339ed 30731
996b5569
TP		 30732 /* APM X-Gene family. */
30733 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
30734 ARM_ARCH_NONE,
30735 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30736 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
30737 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30738 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30739
30740 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 30741};
f3bad469 30742#undef ARM_CPU_OPT
7ed4c4c5 30743
34ef62f4
AV		 30744struct arm_ext_table
30745{
30746 const char * name;
30747 size_t name_len;
30748 const arm_feature_set merge;
30749 const arm_feature_set clear;
30750};
30751
c19d1205 30752struct arm_arch_option_table
7ed4c4c5 30753{
34ef62f4
AV		 30754 const char * name;
30755 size_t name_len;
30756 const arm_feature_set value;
30757 const arm_feature_set default_fpu;
30758 const struct arm_ext_table * ext_table;
30759};
30760
30761/* Used to add support for +E and +noE extension. */
30762#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30763/* Used to add support for a +E extension. */
30764#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30765/* Used to add support for a +noE extension. */
30766#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30767
30768#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30769 ~0 & ~FPU_ENDIAN_PURE)
30770
30771static const struct arm_ext_table armv5te_ext_table[] =
30772{
30773 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
30774 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30775};
30776
30777static const struct arm_ext_table armv7_ext_table[] =
30778{
30779 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30780 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30781};
30782
30783static const struct arm_ext_table armv7ve_ext_table[] =
30784{
30785 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
30786 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
30787 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30788 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30789 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30790 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
30791 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30792
30793 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
30794 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30795
30796 /* Aliases for +simd. */
30797 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30798
30799 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30800 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30801 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30802
30803 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30804};
30805
30806static const struct arm_ext_table armv7a_ext_table[] =
30807{
30808 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30809 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30810 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30811 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30812 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30813 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
30814 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30815
30816 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
30817 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30818
30819 /* Aliases for +simd. */
30820 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30821 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30822
30823 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30824 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30825
30826 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
30827 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
30828 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30829};
30830
30831static const struct arm_ext_table armv7r_ext_table[] =
30832{
30833 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
30834 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
30835 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30836 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30837 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
30838 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30839 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30840 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
30841 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30842};
30843
30844static const struct arm_ext_table armv7em_ext_table[] =
30845{
30846 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
30847 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30848 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
30849 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
30850 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30851 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
30852 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30853};
30854
30855static const struct arm_ext_table armv8a_ext_table[] =
30856{
30857 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30858 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30859 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30860 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30861
30862 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30863 should use the +simd option to turn on FP. */
30864 ARM_REMOVE ("fp", ALL_FP),
30865 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30866 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30867 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30868};
30869
30870
30871static const struct arm_ext_table armv81a_ext_table[] =
30872{
30873 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30874 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30875 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30876
30877 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30878 should use the +simd option to turn on FP. */
30879 ARM_REMOVE ("fp", ALL_FP),
30880 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30881 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30882 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30883};
30884
30885static const struct arm_ext_table armv82a_ext_table[] =
30886{
30887 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30888 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
30889 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
30890 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30891 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30892 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30893
30894 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30895 should use the +simd option to turn on FP. */
30896 ARM_REMOVE ("fp", ALL_FP),
30897 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30898 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30899 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30900};
30901
30902static const struct arm_ext_table armv84a_ext_table[] =
30903{
30904 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30905 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30906 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30907 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30908
30909 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30910 should use the +simd option to turn on FP. */
30911 ARM_REMOVE ("fp", ALL_FP),
30912 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30913 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30914 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30915};
30916
30917static const struct arm_ext_table armv85a_ext_table[] =
30918{
30919 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30920 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30921 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30922 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30923
30924 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30925 should use the +simd option to turn on FP. */
30926 ARM_REMOVE ("fp", ALL_FP),
30927 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30928};
30929
30930static const struct arm_ext_table armv8m_main_ext_table[] =
30931{
30932 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30933 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30934 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
30935 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30936 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30937};
30938
e0991585
AV		 30939static const struct arm_ext_table armv8_1m_main_ext_table[] =
30940{
30941 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30942 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30943 ARM_EXT ("fp",
30944 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30945 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
30946 ALL_FP),
30947 ARM_ADD ("fp.dp",
30948 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30949 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
a7ad558c
AV		 30950 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE),
30951 ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)),
30952 ARM_ADD ("mve.fp",
30953 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30954 FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 |
30955 FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
e0991585
AV		 30956 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30957};
30958
34ef62f4
AV		 30959static const struct arm_ext_table armv8r_ext_table[] =
30960{
30961 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30962 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30963 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30964 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30965 ARM_REMOVE ("fp", ALL_FP),
30966 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
30967 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
c19d1205 30968};
7ed4c4c5 30969
c19d1205
ZW		 30970/* This list should, at a minimum, contain all the architecture names
30971 recognized by GCC. */
34ef62f4
AV		 30972#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30973#define ARM_ARCH_OPT2(N, V, DF, ext) \
30974 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
0198d5e6 30975
e74cfd16 30976static const struct arm_arch_option_table arm_archs[] =
c19d1205 30977{
497d849d
TP		 30978 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
30979 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
30980 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
30981 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
30982 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
30983 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
30984 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
30985 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
30986 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
30987 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
30988 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
30989 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
30990 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
30991 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
34ef62f4
AV		 30992 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
30993 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
30994 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
30995 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30996 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30997 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
30998 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
f33026a9
MW		 30999 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31000 kept to preserve existing behaviour. */
34ef62f4
AV		 31001 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
31002 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
31003 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
31004 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
31005 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
f33026a9
MW		 31006 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31007 kept to preserve existing behaviour. */
34ef62f4
AV		 31008 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
31009 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
497d849d
TP		 31010 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
31011 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
34ef62f4 31012 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
c450d570
PB		 31013 /* The official spelling of the ARMv7 profile variants is the dashed form.
31014 Accept the non-dashed form for compatibility with old toolchains. */
34ef62f4
AV		 31015 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
31016 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
31017 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 31018 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4
AV		 31019 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
31020 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 31021 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4 31022 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
497d849d 31023 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
34ef62f4
AV		 31024 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
31025 armv8m_main),
e0991585
AV		 31026 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
31027 armv8_1m_main),
34ef62f4
AV		 31028 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
31029 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
31030 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
31031 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
31032 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
31033 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
31034 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
497d849d
TP		 31035 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
31036 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
31037 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
34ef62f4 31038 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 31039};
f3bad469 31040#undef ARM_ARCH_OPT
7ed4c4c5 31041
69133863 31042/* ISA extensions in the co-processor and main instruction set space. */
0198d5e6 31043
69133863 31044struct arm_option_extension_value_table
c19d1205 31045{
0198d5e6
TC		 31046 const char * name;
31047 size_t name_len;
31048 const arm_feature_set merge_value;
31049 const arm_feature_set clear_value;
d942732e
TP		 31050 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31051 indicates that an extension is available for all architectures while
31052 ARM_ANY marks an empty entry. */
0198d5e6 31053 const arm_feature_set allowed_archs[2];
c19d1205 31054};
7ed4c4c5 31055
0198d5e6
TC		 31056/* The following table must be in alphabetical order with a NULL last entry. */
31057
d942732e
TP		 31058#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31059#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
0198d5e6 31060
34ef62f4
AV		 31061/* DEPRECATED: Refrain from using this table to add any new extensions, instead
31062 use the context sensitive approach using arm_ext_table's. */
69133863 31063static const struct arm_option_extension_value_table arm_extensions[] =
c19d1205 31064{
823d2571
TG		 31065 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
31066 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
bca38921 31067 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
823d2571
TG		 31068 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
31069 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
c604a79a
JW		 31070 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
31071 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
31072 ARM_ARCH_V8_2A),
15afaa63
TP		 31073 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31074 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31075 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
823d2571
TG		 31076 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
31077 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
b8ec4e87
JW		 31078 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31079 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31080 ARM_ARCH_V8_2A),
01f48020
TC		 31081 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31082 | ARM_EXT2_FP16_FML),
31083 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31084 | ARM_EXT2_FP16_FML),
31085 ARM_ARCH_V8_2A),
d942732e 31086 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
823d2571 31087 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
d942732e
TP		 31088 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
31089 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
3d030cdb
TP		 31090 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31091 Thumb divide instruction. Due to this having the same name as the
31092 previous entry, this will be ignored when doing command-line parsing and
31093 only considered by build attribute selection code. */
31094 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
31095 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
31096 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
823d2571 31097 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
d942732e 31098 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
823d2571 31099 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
d942732e 31100 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
823d2571 31101 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
d942732e
TP		 31102 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
31103 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
823d2571 31104 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
d942732e
TP		 31105 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
31106 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
823d2571
TG		 31107 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
31108 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
31109 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
ddfded2f
MW		 31110 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
31111 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
ced40572 31112 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
dad0c3bf
SD		 31113 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
31114 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
31115 ARM_ARCH_V8A),
4d1464f2
MW		 31116 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
31117 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
ced40572 31118 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
643afb90
MW		 31119 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
31120 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
ced40572 31121 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
7fadb25d
SD		 31122 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
31123 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
31124 ARM_ARCH_V8A),
d942732e 31125 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
823d2571 31126 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
d942732e
TP		 31127 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
31128 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
643afb90
MW		 31129 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
31130 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
31131 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
823d2571
TG		 31132 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
31133 | ARM_EXT_DIV),
31134 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
31135 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
31136 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
d942732e
TP		 31137 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
31138 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
69133863 31139};
f3bad469 31140#undef ARM_EXT_OPT
69133863
MGD		 31141
31142/* ISA floating-point and Advanced SIMD extensions. */
31143struct arm_option_fpu_value_table
31144{
0198d5e6
TC		 31145 const char * name;
31146 const arm_feature_set value;
c19d1205 31147};
7ed4c4c5 31148
c19d1205
ZW		 31149/* This list should, at a minimum, contain all the fpu names
31150 recognized by GCC. */
69133863 31151static const struct arm_option_fpu_value_table arm_fpus[] =
c19d1205
ZW		 31152{
31153 {"softfpa", FPU_NONE},
31154 {"fpe", FPU_ARCH_FPE},
31155 {"fpe2", FPU_ARCH_FPE},
31156 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
31157 {"fpa", FPU_ARCH_FPA},
31158 {"fpa10", FPU_ARCH_FPA},
31159 {"fpa11", FPU_ARCH_FPA},
31160 {"arm7500fe", FPU_ARCH_FPA},
31161 {"softvfp", FPU_ARCH_VFP},
31162 {"softvfp+vfp", FPU_ARCH_VFP_V2},
31163 {"vfp", FPU_ARCH_VFP_V2},
31164 {"vfp9", FPU_ARCH_VFP_V2},
d5e0ba9c 31165 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
c19d1205
ZW		 31166 {"vfp10", FPU_ARCH_VFP_V2},
31167 {"vfp10-r0", FPU_ARCH_VFP_V1},
31168 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB		 31169 {"vfpv2", FPU_ARCH_VFP_V2},
31170 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 31171 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 31172 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB		 31173 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
31174 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
31175 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW		 31176 {"arm1020t", FPU_ARCH_VFP_V1},
31177 {"arm1020e", FPU_ARCH_VFP_V2},
d5e0ba9c 31178 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
c19d1205
ZW		 31179 {"arm1136jf-s", FPU_ARCH_VFP_V2},
31180 {"maverick", FPU_ARCH_MAVERICK},
d5e0ba9c 31181 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
d3375ddd 31182 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 31183 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB		 31184 {"vfpv4", FPU_ARCH_VFP_V4},
31185 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 31186 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
a715796b
TG		 31187 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
31188 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
62f3b8c8 31189 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
bca38921
MGD		 31190 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
31191 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
31192 {"crypto-neon-fp-armv8",
31193 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
d6b4b13e 31194 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
081e4c7d
MW		 31195 {"crypto-neon-fp-armv8.1",
31196 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
e74cfd16
PB		 31197 {NULL, ARM_ARCH_NONE}
31198};
31199
31200struct arm_option_value_table
31201{
e0471c16 31202 const char *name;
e74cfd16 31203 long value;
c19d1205 31204};
7ed4c4c5 31205
e74cfd16 31206static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW		 31207{
31208 {"hard", ARM_FLOAT_ABI_HARD},
31209 {"softfp", ARM_FLOAT_ABI_SOFTFP},
31210 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 31211 {NULL, 0}
c19d1205 31212};
7ed4c4c5 31213
c19d1205 31214#ifdef OBJ_ELF
3a4a14e9 31215/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 31216static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW		 31217{
31218 {"gnu", EF_ARM_EABI_UNKNOWN},
31219 {"4", EF_ARM_EABI_VER4},
3a4a14e9 31220 {"5", EF_ARM_EABI_VER5},
e74cfd16 31221 {NULL, 0}
c19d1205
ZW		 31222};
31223#endif
7ed4c4c5 31224
c19d1205
ZW		 31225struct arm_long_option_table
31226{
0198d5e6 31227 const char * option; /* Substring to match. */
e0471c16 31228 const char * help; /* Help information. */
17b9d67d 31229 int (* func) (const char * subopt); /* Function to decode sub-option. */
e0471c16 31230 const char * deprecated; /* If non-null, print this message. */
c19d1205 31231};
7ed4c4c5 31232
c921be7d 31233static bfd_boolean
c168ce07 31234arm_parse_extension (const char *str, const arm_feature_set *opt_set,
34ef62f4
AV		 31235 arm_feature_set *ext_set,
31236 const struct arm_ext_table *ext_table)
7ed4c4c5 31237{
69133863 31238 /* We insist on extensions being specified in alphabetical order, and with
fa94de6b
RM		 31239 extensions being added before being removed. We achieve this by having
31240 the global ARM_EXTENSIONS table in alphabetical order, and using the
69133863 31241 ADDING_VALUE variable to indicate whether we are adding an extension (1)
fa94de6b 31242 or removing it (0) and only allowing it to change in the order
69133863
MGD		 31243 -1 -> 1 -> 0. */
31244 const struct arm_option_extension_value_table * opt = NULL;
d942732e 31245 const arm_feature_set arm_any = ARM_ANY;
69133863
MGD		 31246 int adding_value = -1;
31247
c19d1205 31248 while (str != NULL && *str != 0)
7ed4c4c5 31249 {
82b8a785 31250 const char *ext;
f3bad469 31251 size_t len;
7ed4c4c5 31252
c19d1205
ZW		 31253 if (*str != '+')
31254 {
31255 as_bad (_("invalid architectural extension"));
c921be7d 31256 return FALSE;
c19d1205 31257 }
7ed4c4c5 31258
c19d1205
ZW		 31259 str++;
31260 ext = strchr (str, '+');
7ed4c4c5 31261
c19d1205 31262 if (ext != NULL)
f3bad469 31263 len = ext - str;
c19d1205 31264 else
f3bad469 31265 len = strlen (str);
7ed4c4c5 31266
f3bad469 31267 if (len >= 2 && strncmp (str, "no", 2) == 0)
69133863
MGD		 31268 {
31269 if (adding_value != 0)
31270 {
31271 adding_value = 0;
31272 opt = arm_extensions;
31273 }
31274
f3bad469 31275 len -= 2;
69133863
MGD		 31276 str += 2;
31277 }
f3bad469 31278 else if (len > 0)
69133863
MGD		 31279 {
31280 if (adding_value == -1)
31281 {
31282 adding_value = 1;
31283 opt = arm_extensions;
31284 }
31285 else if (adding_value != 1)
31286 {
31287 as_bad (_("must specify extensions to add before specifying "
31288 "those to remove"));
31289 return FALSE;
31290 }
31291 }
31292
f3bad469 31293 if (len == 0)
c19d1205
ZW		 31294 {
31295 as_bad (_("missing architectural extension"));
c921be7d 31296 return FALSE;
c19d1205 31297 }
7ed4c4c5 31298
69133863
MGD		 31299 gas_assert (adding_value != -1);
31300 gas_assert (opt != NULL);
31301
34ef62f4
AV		 31302 if (ext_table != NULL)
31303 {
31304 const struct arm_ext_table * ext_opt = ext_table;
31305 bfd_boolean found = FALSE;
31306 for (; ext_opt->name != NULL; ext_opt++)
31307 if (ext_opt->name_len == len
31308 && strncmp (ext_opt->name, str, len) == 0)
31309 {
31310 if (adding_value)
31311 {
31312 if (ARM_FEATURE_ZERO (ext_opt->merge))
31313 /* TODO: Option not supported. When we remove the
31314 legacy table this case should error out. */
31315 continue;
31316
31317 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
31318 }
31319 else
31320 {
31321 if (ARM_FEATURE_ZERO (ext_opt->clear))
31322 /* TODO: Option not supported. When we remove the
31323 legacy table this case should error out. */
31324 continue;
31325 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
31326 }
31327 found = TRUE;
31328 break;
31329 }
31330 if (found)
31331 {
31332 str = ext;
31333 continue;
31334 }
31335 }
31336
69133863
MGD		 31337 /* Scan over the options table trying to find an exact match. */
31338 for (; opt->name != NULL; opt++)
f3bad469 31339 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31340 {
d942732e
TP		 31341 int i, nb_allowed_archs =
31342 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
69133863 31343 /* Check we can apply the extension to this architecture. */
d942732e
TP		 31344 for (i = 0; i < nb_allowed_archs; i++)
31345 {
31346 /* Empty entry. */
31347 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
31348 continue;
c168ce07 31349 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
d942732e
TP		 31350 break;
31351 }
31352 if (i == nb_allowed_archs)
69133863
MGD		 31353 {
31354 as_bad (_("extension does not apply to the base architecture"));
31355 return FALSE;
31356 }
31357
31358 /* Add or remove the extension. */
31359 if (adding_value)
4d354d8b 31360 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
69133863 31361 else
4d354d8b 31362 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
69133863 31363
3d030cdb
TP		 31364 /* Allowing Thumb division instructions for ARMv7 in autodetection
31365 rely on this break so that duplicate extensions (extensions
31366 with the same name as a previous extension in the list) are not
31367 considered for command-line parsing. */
c19d1205
ZW		 31368 break;
31369 }
7ed4c4c5 31370
c19d1205
ZW		 31371 if (opt->name == NULL)
31372 {
69133863
MGD		 31373 /* Did we fail to find an extension because it wasn't specified in
31374 alphabetical order, or because it does not exist? */
31375
31376 for (opt = arm_extensions; opt->name != NULL; opt++)
f3bad469 31377 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
69133863
MGD		 31378 break;
31379
31380 if (opt->name == NULL)
31381 as_bad (_("unknown architectural extension `%s'"), str);
31382 else
31383 as_bad (_("architectural extensions must be specified in "
31384 "alphabetical order"));
31385
c921be7d 31386 return FALSE;
c19d1205 31387 }
69133863
MGD		 31388 else
31389 {
31390 /* We should skip the extension we've just matched the next time
31391 round. */
31392 opt++;
31393 }
7ed4c4c5 31394
c19d1205
ZW		 31395 str = ext;
31396 };
7ed4c4c5 31397
c921be7d 31398 return TRUE;
c19d1205 31399}
7ed4c4c5 31400
5312fe52
BW		 31401static bfd_boolean
31402arm_parse_fp16_opt (const char *str)
31403{
31404 if (strcasecmp (str, "ieee") == 0)
31405 fp16_format = ARM_FP16_FORMAT_IEEE;
31406 else if (strcasecmp (str, "alternative") == 0)
31407 fp16_format = ARM_FP16_FORMAT_ALTERNATIVE;
31408 else
31409 {
31410 as_bad (_("unrecognised float16 format \"%s\""), str);
31411 return FALSE;
31412 }
31413
31414 return TRUE;
31415}
31416
c921be7d 31417static bfd_boolean
17b9d67d 31418arm_parse_cpu (const char *str)
7ed4c4c5 31419{
f3bad469 31420 const struct arm_cpu_option_table *opt;
82b8a785 31421 const char *ext = strchr (str, '+');
f3bad469 31422 size_t len;
7ed4c4c5 31423
c19d1205 31424 if (ext != NULL)
f3bad469 31425 len = ext - str;
7ed4c4c5 31426 else
f3bad469 31427 len = strlen (str);
7ed4c4c5 31428
f3bad469 31429 if (len == 0)
7ed4c4c5 31430 {
c19d1205 31431 as_bad (_("missing cpu name `%s'"), str);
c921be7d 31432 return FALSE;
7ed4c4c5
NC		 31433 }
31434
c19d1205 31435 for (opt = arm_cpus; opt->name != NULL; opt++)
f3bad469 31436 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31437 {
c168ce07 31438 mcpu_cpu_opt = &opt->value;
4d354d8b
TP		 31439 if (mcpu_ext_opt == NULL)
31440 mcpu_ext_opt = XNEW (arm_feature_set);
31441 *mcpu_ext_opt = opt->ext;
e74cfd16 31442 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 31443 if (opt->canonical_name)
ef8e6722
JW		 31444 {
31445 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
31446 strcpy (selected_cpu_name, opt->canonical_name);
31447 }
ee065d83
PB		 31448 else
31449 {
f3bad469 31450 size_t i;
c921be7d 31451
ef8e6722
JW		 31452 if (len >= sizeof selected_cpu_name)
31453 len = (sizeof selected_cpu_name) - 1;
31454
f3bad469 31455 for (i = 0; i < len; i++)
ee065d83
PB		 31456 selected_cpu_name[i] = TOUPPER (opt->name[i]);
31457 selected_cpu_name[i] = 0;
31458 }
7ed4c4c5 31459
c19d1205 31460 if (ext != NULL)
34ef62f4 31461 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
7ed4c4c5 31462
c921be7d 31463 return TRUE;
c19d1205 31464 }
7ed4c4c5 31465
c19d1205 31466 as_bad (_("unknown cpu `%s'"), str);
c921be7d 31467 return FALSE;
7ed4c4c5
NC		 31468}
31469
c921be7d 31470static bfd_boolean
17b9d67d 31471arm_parse_arch (const char *str)
7ed4c4c5 31472{
e74cfd16 31473 const struct arm_arch_option_table *opt;
82b8a785 31474 const char *ext = strchr (str, '+');
f3bad469 31475 size_t len;
7ed4c4c5 31476
c19d1205 31477 if (ext != NULL)
f3bad469 31478 len = ext - str;
7ed4c4c5 31479 else
f3bad469 31480 len = strlen (str);
7ed4c4c5 31481
f3bad469 31482 if (len == 0)
7ed4c4c5 31483 {
c19d1205 31484 as_bad (_("missing architecture name `%s'"), str);
c921be7d 31485 return FALSE;
7ed4c4c5
NC		 31486 }
31487
c19d1205 31488 for (opt = arm_archs; opt->name != NULL; opt++)
f3bad469 31489 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31490 {
e74cfd16 31491 march_cpu_opt = &opt->value;
4d354d8b
TP		 31492 if (march_ext_opt == NULL)
31493 march_ext_opt = XNEW (arm_feature_set);
31494 *march_ext_opt = arm_arch_none;
e74cfd16 31495 march_fpu_opt = &opt->default_fpu;
5f4273c7 31496 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 31497
c19d1205 31498 if (ext != NULL)
34ef62f4
AV		 31499 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
31500 opt->ext_table);
7ed4c4c5 31501
c921be7d 31502 return TRUE;
c19d1205
ZW		 31503 }
31504
31505 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 31506 return FALSE;
7ed4c4c5 31507}
eb043451 31508
c921be7d 31509static bfd_boolean
17b9d67d 31510arm_parse_fpu (const char * str)
c19d1205 31511{
69133863 31512 const struct arm_option_fpu_value_table * opt;
b99bd4ef 31513
c19d1205
ZW		 31514 for (opt = arm_fpus; opt->name != NULL; opt++)
31515 if (streq (opt->name, str))
31516 {
e74cfd16 31517 mfpu_opt = &opt->value;
c921be7d 31518 return TRUE;
c19d1205 31519 }
b99bd4ef 31520
c19d1205 31521 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 31522 return FALSE;
c19d1205
ZW		 31523}
31524
c921be7d 31525static bfd_boolean
17b9d67d 31526arm_parse_float_abi (const char * str)
b99bd4ef 31527{
e74cfd16 31528 const struct arm_option_value_table * opt;
b99bd4ef 31529
c19d1205
ZW		 31530 for (opt = arm_float_abis; opt->name != NULL; opt++)
31531 if (streq (opt->name, str))
31532 {
31533 mfloat_abi_opt = opt->value;
c921be7d 31534 return TRUE;
c19d1205 31535 }
cc8a6dd0 31536
c19d1205 31537 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 31538 return FALSE;
c19d1205 31539}
b99bd4ef 31540
c19d1205 31541#ifdef OBJ_ELF
c921be7d 31542static bfd_boolean
17b9d67d 31543arm_parse_eabi (const char * str)
c19d1205 31544{
e74cfd16 31545 const struct arm_option_value_table *opt;
cc8a6dd0 31546
c19d1205
ZW		 31547 for (opt = arm_eabis; opt->name != NULL; opt++)
31548 if (streq (opt->name, str))
31549 {
31550 meabi_flags = opt->value;
c921be7d 31551 return TRUE;
c19d1205
ZW		 31552 }
31553 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 31554 return FALSE;
c19d1205
ZW		 31555}
31556#endif
cc8a6dd0 31557
c921be7d 31558static bfd_boolean
17b9d67d 31559arm_parse_it_mode (const char * str)
e07e6e58 31560{
c921be7d 31561 bfd_boolean ret = TRUE;
e07e6e58
NC		 31562
31563 if (streq ("arm", str))
31564 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
31565 else if (streq ("thumb", str))
31566 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
31567 else if (streq ("always", str))
31568 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
31569 else if (streq ("never", str))
31570 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
31571 else
31572 {
31573 as_bad (_("unknown implicit IT mode `%s', should be "\
477330fc 31574 "arm, thumb, always, or never."), str);
c921be7d 31575 ret = FALSE;
e07e6e58
NC		 31576 }
31577
31578 return ret;
31579}
31580
2e6976a8 31581static bfd_boolean
17b9d67d 31582arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
2e6976a8
DG		 31583{
31584 codecomposer_syntax = TRUE;
31585 arm_comment_chars[0] = ';';
31586 arm_line_separator_chars[0] = 0;
31587 return TRUE;
31588}
31589
c19d1205
ZW		 31590struct arm_long_option_table arm_long_opts[] =
31591{
31592 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31593 arm_parse_cpu, NULL},
31594 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31595 arm_parse_arch, NULL},
31596 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31597 arm_parse_fpu, NULL},
31598 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31599 arm_parse_float_abi, NULL},
31600#ifdef OBJ_ELF
7fac0536 31601 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW		 31602 arm_parse_eabi, NULL},
31603#endif
e07e6e58
NC		 31604 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31605 arm_parse_it_mode, NULL},
2e6976a8
DG		 31606 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31607 arm_ccs_mode, NULL},
5312fe52
BW		 31608 {"mfp16-format=",
31609 N_("[ieee|alternative]\n\
31610 set the encoding for half precision floating point "
31611 "numbers to IEEE\n\
31612 or Arm alternative format."),
31613 arm_parse_fp16_opt, NULL },
c19d1205
ZW		 31614 {NULL, NULL, 0, NULL}
31615};
cc8a6dd0 31616
c19d1205 31617int
17b9d67d 31618md_parse_option (int c, const char * arg)
c19d1205
ZW		 31619{
31620 struct arm_option_table *opt;
e74cfd16 31621 const struct arm_legacy_option_table *fopt;
c19d1205 31622 struct arm_long_option_table *lopt;
b99bd4ef 31623
c19d1205 31624 switch (c)
b99bd4ef 31625 {
c19d1205
ZW		 31626#ifdef OPTION_EB
31627 case OPTION_EB:
31628 target_big_endian = 1;
31629 break;
31630#endif
cc8a6dd0 31631
c19d1205
ZW		 31632#ifdef OPTION_EL
31633 case OPTION_EL:
31634 target_big_endian = 0;
31635 break;
31636#endif
b99bd4ef 31637
845b51d6
PB		 31638 case OPTION_FIX_V4BX:
31639 fix_v4bx = TRUE;
31640 break;
31641
18a20338
CL		 31642#ifdef OBJ_ELF
31643 case OPTION_FDPIC:
31644 arm_fdpic = TRUE;
31645 break;
31646#endif /* OBJ_ELF */
31647
c19d1205
ZW		 31648 case 'a':
31649 /* Listing option. Just ignore these, we don't support additional
31650 ones. */
31651 return 0;
b99bd4ef 31652
c19d1205
ZW		 31653 default:
31654 for (opt = arm_opts; opt->option != NULL; opt++)
31655 {
31656 if (c == opt->option[0]
31657 && ((arg == NULL && opt->option[1] == 0)
31658 || streq (arg, opt->option + 1)))
31659 {
c19d1205 31660 /* If the option is deprecated, tell the user. */
278df34e 31661 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW		 31662 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31663 arg ? arg : "", _(opt->deprecated));
b99bd4ef 31664
c19d1205
ZW		 31665 if (opt->var != NULL)
31666 *opt->var = opt->value;
cc8a6dd0 31667
c19d1205
ZW		 31668 return 1;
31669 }
31670 }
b99bd4ef 31671
e74cfd16
PB		 31672 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
31673 {
31674 if (c == fopt->option[0]
31675 && ((arg == NULL && fopt->option[1] == 0)
31676 || streq (arg, fopt->option + 1)))
31677 {
e74cfd16 31678 /* If the option is deprecated, tell the user. */
278df34e 31679 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB		 31680 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31681 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB		 31682
31683 if (fopt->var != NULL)
31684 *fopt->var = &fopt->value;
31685
31686 return 1;
31687 }
31688 }
31689
c19d1205
ZW		 31690 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31691 {
31692 /* These options are expected to have an argument. */
31693 if (c == lopt->option[0]
31694 && arg != NULL
31695 && strncmp (arg, lopt->option + 1,
31696 strlen (lopt->option + 1)) == 0)
31697 {
c19d1205 31698 /* If the option is deprecated, tell the user. */
278df34e 31699 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW		 31700 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
31701 _(lopt->deprecated));
b99bd4ef 31702
c19d1205
ZW		 31703 /* Call the sup-option parser. */
31704 return lopt->func (arg + strlen (lopt->option) - 1);
31705 }
31706 }
a737bd4d 31707
c19d1205
ZW		 31708 return 0;
31709 }
a394c00f 31710
c19d1205
ZW		 31711 return 1;
31712}
a394c00f 31713
c19d1205
ZW		 31714void
31715md_show_usage (FILE * fp)
a394c00f 31716{
c19d1205
ZW		 31717 struct arm_option_table *opt;
31718 struct arm_long_option_table *lopt;
a394c00f 31719
c19d1205 31720 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 31721
c19d1205
ZW		 31722 for (opt = arm_opts; opt->option != NULL; opt++)
31723 if (opt->help != NULL)
31724 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 31725
c19d1205
ZW		 31726 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31727 if (lopt->help != NULL)
31728 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 31729
c19d1205
ZW		 31730#ifdef OPTION_EB
31731 fprintf (fp, _("\
31732 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC		 31733#endif
31734
c19d1205
ZW		 31735#ifdef OPTION_EL
31736 fprintf (fp, _("\
31737 -EL assemble code for a little-endian cpu\n"));
a737bd4d 31738#endif
845b51d6
PB		 31739
31740 fprintf (fp, _("\
31741 --fix-v4bx Allow BX in ARMv4 code\n"));
18a20338
CL		 31742
31743#ifdef OBJ_ELF
31744 fprintf (fp, _("\
31745 --fdpic generate an FDPIC object file\n"));
31746#endif /* OBJ_ELF */
c19d1205 31747}
ee065d83 31748
ee065d83 31749#ifdef OBJ_ELF
0198d5e6 31750
62b3e311
PB		 31751typedef struct
31752{
31753 int val;
31754 arm_feature_set flags;
31755} cpu_arch_ver_table;
31756
2c6b98ea
TP		 31757/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31758 chronologically for architectures, with an exception for ARMv6-M and
31759 ARMv6S-M due to legacy reasons. No new architecture should have a
31760 special case. This allows for build attribute selection results to be
31761 stable when new architectures are added. */
62b3e311
PB		 31762static const cpu_arch_ver_table cpu_arch_ver[] =
31763{
031254f2
AV		 31764 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
31765 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
31766 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
31767 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
31768 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
31769 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
31770 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
31771 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
31772 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
31773 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
31774 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
31775 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
31776 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
31777 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
31778 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
31779 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
31780 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
31781 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
31782 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
31783 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
31784 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
31785 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
31786 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
31787 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
2c6b98ea
TP		 31788
31789 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31790 always selected build attributes to match those of ARMv6-M
31791 (resp. ARMv6S-M). However, due to these architectures being a strict
31792 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31793 would be selected when fully respecting chronology of architectures.
31794 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31795 move them before ARMv7 architectures. */
031254f2
AV		 31796 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
31797 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
31798
31799 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
31800 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
31801 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
31802 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
31803 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
31804 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
31805 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
31806 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
31807 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
31808 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
31809 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
31810 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
31811 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
31812 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
31813 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
31814 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
31815 {-1, ARM_ARCH_NONE}
62b3e311
PB		 31816};
31817
ee3c0378 31818/* Set an attribute if it has not already been set by the user. */
0198d5e6 31819
ee3c0378
AS		 31820static void
31821aeabi_set_attribute_int (int tag, int value)
31822{
31823 if (tag < 1
31824 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31825 || !attributes_set_explicitly[tag])
31826 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
31827}
31828
31829static void
31830aeabi_set_attribute_string (int tag, const char *value)
31831{
31832 if (tag < 1
31833 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31834 || !attributes_set_explicitly[tag])
31835 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
31836}
31837
2c6b98ea
TP		 31838/* Return whether features in the *NEEDED feature set are available via
31839 extensions for the architecture whose feature set is *ARCH_FSET. */
0198d5e6 31840
2c6b98ea
TP		 31841static bfd_boolean
31842have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
31843 const arm_feature_set *needed)
31844{
31845 int i, nb_allowed_archs;
31846 arm_feature_set ext_fset;
31847 const struct arm_option_extension_value_table *opt;
31848
31849 ext_fset = arm_arch_none;
31850 for (opt = arm_extensions; opt->name != NULL; opt++)
31851 {
31852 /* Extension does not provide any feature we need. */
31853 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
31854 continue;
31855
31856 nb_allowed_archs =
31857 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
31858 for (i = 0; i < nb_allowed_archs; i++)
31859 {
31860 /* Empty entry. */
31861 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
31862 break;
31863
31864 /* Extension is available, add it. */
31865 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
31866 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
31867 }
31868 }
31869
31870 /* Can we enable all features in *needed? */
31871 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
31872}
31873
31874/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31875 a given architecture feature set *ARCH_EXT_FSET including extension feature
31876 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31877 - if true, check for an exact match of the architecture modulo extensions;
31878 - otherwise, select build attribute value of the first superset
31879 architecture released so that results remains stable when new architectures
31880 are added.
31881 For -march/-mcpu=all the build attribute value of the most featureful
31882 architecture is returned. Tag_CPU_arch_profile result is returned in
31883 PROFILE. */
0198d5e6 31884
2c6b98ea
TP		 31885static int
31886get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
31887 const arm_feature_set *ext_fset,
31888 char *profile, int exact_match)
31889{
31890 arm_feature_set arch_fset;
31891 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
31892
31893 /* Select most featureful architecture with all its extensions if building
31894 for -march=all as the feature sets used to set build attributes. */
31895 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
31896 {
31897 /* Force revisiting of decision for each new architecture. */
031254f2 31898 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
2c6b98ea
TP		 31899 *profile = 'A';
31900 return TAG_CPU_ARCH_V8;
31901 }
31902
31903 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
31904
31905 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
31906 {
31907 arm_feature_set known_arch_fset;
31908
31909 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
31910 if (exact_match)
31911 {
31912 /* Base architecture match user-specified architecture and
31913 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31914 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
31915 {
31916 p_ver_ret = p_ver;
31917 goto found;
31918 }
31919 /* Base architecture match user-specified architecture only
31920 (eg. ARMv6-M in the same case as above). Record it in case we
31921 find a match with above condition. */
31922 else if (p_ver_ret == NULL
31923 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
31924 p_ver_ret = p_ver;
31925 }
31926 else
31927 {
31928
31929 /* Architecture has all features wanted. */
31930 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
31931 {
31932 arm_feature_set added_fset;
31933
31934 /* Compute features added by this architecture over the one
31935 recorded in p_ver_ret. */
31936 if (p_ver_ret != NULL)
31937 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
31938 p_ver_ret->flags);
31939 /* First architecture that match incl. with extensions, or the
31940 only difference in features over the recorded match is
31941 features that were optional and are now mandatory. */
31942 if (p_ver_ret == NULL
31943 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
31944 {
31945 p_ver_ret = p_ver;
31946 goto found;
31947 }
31948 }
31949 else if (p_ver_ret == NULL)
31950 {
31951 arm_feature_set needed_ext_fset;
31952
31953 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
31954
31955 /* Architecture has all features needed when using some
31956 extensions. Record it and continue searching in case there
31957 exist an architecture providing all needed features without
31958 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31959 OS extension). */
31960 if (have_ext_for_needed_feat_p (&known_arch_fset,
31961 &needed_ext_fset))
31962 p_ver_ret = p_ver;
31963 }
31964 }
31965 }
31966
31967 if (p_ver_ret == NULL)
31968 return -1;
31969
31970found:
31971 /* Tag_CPU_arch_profile. */
31972 if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
31973 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
31974 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
31975 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
31976 *profile = 'A';
31977 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
31978 *profile = 'R';
31979 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
31980 *profile = 'M';
31981 else
31982 *profile = '\0';
31983 return p_ver_ret->val;
31984}
31985
ee065d83 31986/* Set the public EABI object attributes. */
0198d5e6 31987
c168ce07 31988static void
ee065d83
PB		 31989aeabi_set_public_attributes (void)
31990{
b90d5ba0 31991 char profile = '\0';
2c6b98ea 31992 int arch = -1;
90ec0d68 31993 int virt_sec = 0;
bca38921 31994 int fp16_optional = 0;
2c6b98ea
TP		 31995 int skip_exact_match = 0;
31996 arm_feature_set flags, flags_arch, flags_ext;
ee065d83 31997
54bab281
TP		 31998 /* Autodetection mode, choose the architecture based the instructions
31999 actually used. */
32000 if (no_cpu_selected ())
32001 {
32002 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
ddd7f988 32003
54bab281
TP		 32004 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
32005 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
ddd7f988 32006
54bab281
TP		 32007 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
32008 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
ddd7f988 32009
54bab281 32010 /* Code run during relaxation relies on selected_cpu being set. */
4d354d8b
TP		 32011 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
32012 flags_ext = arm_arch_none;
32013 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
32014 selected_ext = flags_ext;
54bab281
TP		 32015 selected_cpu = flags;
32016 }
32017 /* Otherwise, choose the architecture based on the capabilities of the
32018 requested cpu. */
32019 else
4d354d8b
TP		 32020 {
32021 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
32022 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
32023 flags_ext = selected_ext;
32024 flags = selected_cpu;
32025 }
32026 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
7f78eb34 32027
ddd7f988 32028 /* Allow the user to override the reported architecture. */
4d354d8b 32029 if (!ARM_FEATURE_ZERO (selected_object_arch))
7a1d4c38 32030 {
4d354d8b 32031 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
2c6b98ea 32032 flags_ext = arm_arch_none;
7a1d4c38 32033 }
2c6b98ea 32034 else
4d354d8b 32035 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
2c6b98ea
TP		 32036
32037 /* When this function is run again after relaxation has happened there is no
32038 way to determine whether an architecture or CPU was specified by the user:
32039 - selected_cpu is set above for relaxation to work;
32040 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32041 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32042 Therefore, if not in -march=all case we first try an exact match and fall
32043 back to autodetection. */
32044 if (!skip_exact_match)
32045 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
32046 if (arch == -1)
32047 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
32048 if (arch == -1)
32049 as_bad (_("no architecture contains all the instructions used\n"));
9e3c6df6 32050
ee065d83
PB		 32051 /* Tag_CPU_name. */
32052 if (selected_cpu_name[0])
32053 {
91d6fa6a 32054 char *q;
ee065d83 32055
91d6fa6a
NC		 32056 q = selected_cpu_name;
32057 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB		 32058 {
32059 int i;
5f4273c7 32060
91d6fa6a
NC		 32061 q += 4;
32062 for (i = 0; q[i]; i++)
32063 q[i] = TOUPPER (q[i]);
ee065d83 32064 }
91d6fa6a 32065 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 32066 }
62f3b8c8 32067
ee065d83 32068 /* Tag_CPU_arch. */
ee3c0378 32069 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 32070
62b3e311 32071 /* Tag_CPU_arch_profile. */
69239280
MGD		 32072 if (profile != '\0')
32073 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
62f3b8c8 32074
15afaa63 32075 /* Tag_DSP_extension. */
4d354d8b 32076 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
6c290d53 32077 aeabi_set_attribute_int (Tag_DSP_extension, 1);
15afaa63 32078
2c6b98ea 32079 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
ee065d83 32080 /* Tag_ARM_ISA_use. */
ee3c0378 32081 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
2c6b98ea 32082 || ARM_FEATURE_ZERO (flags_arch))
ee3c0378 32083 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 32084
ee065d83 32085 /* Tag_THUMB_ISA_use. */
ee3c0378 32086 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
2c6b98ea 32087 || ARM_FEATURE_ZERO (flags_arch))
4ed7ed8d
TP		 32088 {
32089 int thumb_isa_use;
32090
32091 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
16a1fa25 32092 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
4ed7ed8d
TP		 32093 thumb_isa_use = 3;
32094 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
32095 thumb_isa_use = 2;
32096 else
32097 thumb_isa_use = 1;
32098 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
32099 }
62f3b8c8 32100
ee065d83 32101 /* Tag_VFP_arch. */
a715796b
TG		 32102 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
32103 aeabi_set_attribute_int (Tag_VFP_arch,
32104 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
32105 ? 7 : 8);
bca38921 32106 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
62f3b8c8
PB		 32107 aeabi_set_attribute_int (Tag_VFP_arch,
32108 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
32109 ? 5 : 6);
32110 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
bca38921
MGD		 32111 {
32112 fp16_optional = 1;
32113 aeabi_set_attribute_int (Tag_VFP_arch, 3);
32114 }
ada65aa3 32115 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
bca38921
MGD		 32116 {
32117 aeabi_set_attribute_int (Tag_VFP_arch, 4);
32118 fp16_optional = 1;
32119 }
ee3c0378
AS		 32120 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
32121 aeabi_set_attribute_int (Tag_VFP_arch, 2);
32122 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
477330fc 32123 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
ee3c0378 32124 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 32125
4547cb56
NC		 32126 /* Tag_ABI_HardFP_use. */
32127 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
32128 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
32129 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
32130
ee065d83 32131 /* Tag_WMMX_arch. */
ee3c0378
AS		 32132 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
32133 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
32134 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
32135 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 32136
ee3c0378 32137 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
9411fd44
MW		 32138 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
32139 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
32140 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
bca38921
MGD		 32141 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
32142 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
32143 {
32144 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
32145 {
32146 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
32147 }
32148 else
32149 {
32150 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
32151 fp16_optional = 1;
32152 }
32153 }
fa94de6b 32154
a7ad558c
AV		 32155 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
32156 aeabi_set_attribute_int (Tag_MVE_arch, 2);
32157 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
32158 aeabi_set_attribute_int (Tag_MVE_arch, 1);
32159
ee3c0378 32160 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
bca38921 32161 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
ee3c0378 32162 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56 32163
69239280
MGD		 32164 /* Tag_DIV_use.
32165
32166 We set Tag_DIV_use to two when integer divide instructions have been used
32167 in ARM state, or when Thumb integer divide instructions have been used,
32168 but we have no architecture profile set, nor have we any ARM instructions.
32169
4ed7ed8d
TP		 32170 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32171 by the base architecture.
bca38921 32172
69239280 32173 For new architectures we will have to check these tests. */
031254f2 32174 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
4ed7ed8d
TP		 32175 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
32176 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
bca38921
MGD		 32177 aeabi_set_attribute_int (Tag_DIV_use, 0);
32178 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
32179 || (profile == '\0'
32180 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
32181 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
eea54501 32182 aeabi_set_attribute_int (Tag_DIV_use, 2);
60e5ef9f
MGD		 32183
32184 /* Tag_MP_extension_use. */
32185 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
32186 aeabi_set_attribute_int (Tag_MPextension_use, 1);
f4c65163
MGD		 32187
32188 /* Tag Virtualization_use. */
32189 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
90ec0d68
MGD		 32190 virt_sec |= 1;
32191 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
32192 virt_sec |= 2;
32193 if (virt_sec != 0)
32194 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
5312fe52
BW		 32195
32196 if (fp16_format != ARM_FP16_FORMAT_DEFAULT)
32197 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format, fp16_format);
ee065d83
PB		 32198}
32199
c168ce07
TP		 32200/* Post relaxation hook. Recompute ARM attributes now that relaxation is
32201 finished and free extension feature bits which will not be used anymore. */
0198d5e6 32202
c168ce07
TP		 32203void
32204arm_md_post_relax (void)
32205{
32206 aeabi_set_public_attributes ();
4d354d8b
TP		 32207 XDELETE (mcpu_ext_opt);
32208 mcpu_ext_opt = NULL;
32209 XDELETE (march_ext_opt);
32210 march_ext_opt = NULL;
c168ce07
TP		 32211}
32212
104d59d1 32213/* Add the default contents for the .ARM.attributes section. */
0198d5e6 32214
ee065d83
PB		 32215void
32216arm_md_end (void)
32217{
ee065d83
PB		 32218 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
32219 return;
32220
32221 aeabi_set_public_attributes ();
ee065d83 32222}
8463be01 32223#endif /* OBJ_ELF */
ee065d83 32224
ee065d83
PB		 32225/* Parse a .cpu directive. */
32226
32227static void
32228s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
32229{
e74cfd16 32230 const struct arm_cpu_option_table *opt;
ee065d83
PB		 32231 char *name;
32232 char saved_char;
32233
32234 name = input_line_pointer;
5f4273c7 32235 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 32236 input_line_pointer++;
32237 saved_char = *input_line_pointer;
32238 *input_line_pointer = 0;
32239
32240 /* Skip the first "all" entry. */
32241 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
32242 if (streq (opt->name, name))
32243 {
4d354d8b
TP		 32244 selected_arch = opt->value;
32245 selected_ext = opt->ext;
32246 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
ee065d83 32247 if (opt->canonical_name)
5f4273c7 32248 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 32249 else
32250 {
32251 int i;
32252 for (i = 0; opt->name[i]; i++)
32253 selected_cpu_name[i] = TOUPPER (opt->name[i]);
f3bad469 32254
ee065d83
PB		 32255 selected_cpu_name[i] = 0;
32256 }
4d354d8b
TP		 32257 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
32258
ee065d83
PB		 32259 *input_line_pointer = saved_char;
32260 demand_empty_rest_of_line ();
32261 return;
32262 }
32263 as_bad (_("unknown cpu `%s'"), name);
32264 *input_line_pointer = saved_char;
32265 ignore_rest_of_line ();
32266}
32267
ee065d83
PB		 32268/* Parse a .arch directive. */
32269
32270static void
32271s_arm_arch (int ignored ATTRIBUTE_UNUSED)
32272{
e74cfd16 32273 const struct arm_arch_option_table *opt;
ee065d83
PB		 32274 char saved_char;
32275 char *name;
32276
32277 name = input_line_pointer;
5f4273c7 32278 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 32279 input_line_pointer++;
32280 saved_char = *input_line_pointer;
32281 *input_line_pointer = 0;
32282
32283 /* Skip the first "all" entry. */
32284 for (opt = arm_archs + 1; opt->name != NULL; opt++)
32285 if (streq (opt->name, name))
32286 {
4d354d8b
TP		 32287 selected_arch = opt->value;
32288 selected_ext = arm_arch_none;
32289 selected_cpu = selected_arch;
5f4273c7 32290 strcpy (selected_cpu_name, opt->name);
4d354d8b 32291 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB		 32292 *input_line_pointer = saved_char;
32293 demand_empty_rest_of_line ();
32294 return;
32295 }
32296
32297 as_bad (_("unknown architecture `%s'\n"), name);
32298 *input_line_pointer = saved_char;
32299 ignore_rest_of_line ();
32300}
32301
7a1d4c38
PB		 32302/* Parse a .object_arch directive. */
32303
32304static void
32305s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
32306{
32307 const struct arm_arch_option_table *opt;
32308 char saved_char;
32309 char *name;
32310
32311 name = input_line_pointer;
5f4273c7 32312 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB		 32313 input_line_pointer++;
32314 saved_char = *input_line_pointer;
32315 *input_line_pointer = 0;
32316
32317 /* Skip the first "all" entry. */
32318 for (opt = arm_archs + 1; opt->name != NULL; opt++)
32319 if (streq (opt->name, name))
32320 {
4d354d8b 32321 selected_object_arch = opt->value;
7a1d4c38
PB		 32322 *input_line_pointer = saved_char;
32323 demand_empty_rest_of_line ();
32324 return;
32325 }
32326
32327 as_bad (_("unknown architecture `%s'\n"), name);
32328 *input_line_pointer = saved_char;
32329 ignore_rest_of_line ();
32330}
32331
69133863
MGD		 32332/* Parse a .arch_extension directive. */
32333
32334static void
32335s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
32336{
32337 const struct arm_option_extension_value_table *opt;
32338 char saved_char;
32339 char *name;
32340 int adding_value = 1;
32341
32342 name = input_line_pointer;
32343 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
32344 input_line_pointer++;
32345 saved_char = *input_line_pointer;
32346 *input_line_pointer = 0;
32347
32348 if (strlen (name) >= 2
32349 && strncmp (name, "no", 2) == 0)
32350 {
32351 adding_value = 0;
32352 name += 2;
32353 }
32354
32355 for (opt = arm_extensions; opt->name != NULL; opt++)
32356 if (streq (opt->name, name))
32357 {
d942732e
TP		 32358 int i, nb_allowed_archs =
32359 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
32360 for (i = 0; i < nb_allowed_archs; i++)
32361 {
32362 /* Empty entry. */
4d354d8b 32363 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
d942732e 32364 continue;
4d354d8b 32365 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
d942732e
TP		 32366 break;
32367 }
32368
32369 if (i == nb_allowed_archs)
69133863
MGD		 32370 {
32371 as_bad (_("architectural extension `%s' is not allowed for the "
32372 "current base architecture"), name);
32373 break;
32374 }
32375
32376 if (adding_value)
4d354d8b 32377 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
5a70a223 32378 opt->merge_value);
69133863 32379 else
4d354d8b 32380 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
69133863 32381
4d354d8b
TP		 32382 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
32383 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
69133863
MGD		 32384 *input_line_pointer = saved_char;
32385 demand_empty_rest_of_line ();
3d030cdb
TP		 32386 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32387 on this return so that duplicate extensions (extensions with the
32388 same name as a previous extension in the list) are not considered
32389 for command-line parsing. */
69133863
MGD		 32390 return;
32391 }
32392
32393 if (opt->name == NULL)
e673710a 32394 as_bad (_("unknown architecture extension `%s'\n"), name);
69133863
MGD		 32395
32396 *input_line_pointer = saved_char;
32397 ignore_rest_of_line ();
32398}
32399
ee065d83
PB		 32400/* Parse a .fpu directive. */
32401
32402static void
32403s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
32404{
69133863 32405 const struct arm_option_fpu_value_table *opt;
ee065d83
PB		 32406 char saved_char;
32407 char *name;
32408
32409 name = input_line_pointer;
5f4273c7 32410 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 32411 input_line_pointer++;
32412 saved_char = *input_line_pointer;
32413 *input_line_pointer = 0;
5f4273c7 32414
ee065d83
PB		 32415 for (opt = arm_fpus; opt->name != NULL; opt++)
32416 if (streq (opt->name, name))
32417 {
4d354d8b
TP		 32418 selected_fpu = opt->value;
32419#ifndef CPU_DEFAULT
32420 if (no_cpu_selected ())
32421 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
32422 else
32423#endif
32424 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB		 32425 *input_line_pointer = saved_char;
32426 demand_empty_rest_of_line ();
32427 return;
32428 }
32429
32430 as_bad (_("unknown floating point format `%s'\n"), name);
32431 *input_line_pointer = saved_char;
32432 ignore_rest_of_line ();
32433}
ee065d83 32434
794ba86a 32435/* Copy symbol information. */
f31fef98 32436
794ba86a
DJ		 32437void
32438arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
32439{
32440 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
32441}
e04befd0 32442
f31fef98 32443#ifdef OBJ_ELF
e04befd0
AS		 32444/* Given a symbolic attribute NAME, return the proper integer value.
32445 Returns -1 if the attribute is not known. */
f31fef98 32446
e04befd0
AS		 32447int
32448arm_convert_symbolic_attribute (const char *name)
32449{
f31fef98
NC		 32450 static const struct
32451 {
32452 const char * name;
32453 const int tag;
32454 }
32455 attribute_table[] =
32456 {
32457 /* When you modify this table you should
32458 also modify the list in doc/c-arm.texi. */
e04befd0 32459#define T(tag) {#tag, tag}
f31fef98
NC		 32460 T (Tag_CPU_raw_name),
32461 T (Tag_CPU_name),
32462 T (Tag_CPU_arch),
32463 T (Tag_CPU_arch_profile),
32464 T (Tag_ARM_ISA_use),
32465 T (Tag_THUMB_ISA_use),
75375b3e 32466 T (Tag_FP_arch),
f31fef98
NC		 32467 T (Tag_VFP_arch),
32468 T (Tag_WMMX_arch),
32469 T (Tag_Advanced_SIMD_arch),
32470 T (Tag_PCS_config),
32471 T (Tag_ABI_PCS_R9_use),
32472 T (Tag_ABI_PCS_RW_data),
32473 T (Tag_ABI_PCS_RO_data),
32474 T (Tag_ABI_PCS_GOT_use),
32475 T (Tag_ABI_PCS_wchar_t),
32476 T (Tag_ABI_FP_rounding),
32477 T (Tag_ABI_FP_denormal),
32478 T (Tag_ABI_FP_exceptions),
32479 T (Tag_ABI_FP_user_exceptions),
32480 T (Tag_ABI_FP_number_model),
75375b3e 32481 T (Tag_ABI_align_needed),
f31fef98 32482 T (Tag_ABI_align8_needed),
75375b3e 32483 T (Tag_ABI_align_preserved),
f31fef98
NC		 32484 T (Tag_ABI_align8_preserved),
32485 T (Tag_ABI_enum_size),
32486 T (Tag_ABI_HardFP_use),
32487 T (Tag_ABI_VFP_args),
32488 T (Tag_ABI_WMMX_args),
32489 T (Tag_ABI_optimization_goals),
32490 T (Tag_ABI_FP_optimization_goals),
32491 T (Tag_compatibility),
32492 T (Tag_CPU_unaligned_access),
75375b3e 32493 T (Tag_FP_HP_extension),
f31fef98
NC		 32494 T (Tag_VFP_HP_extension),
32495 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD		 32496 T (Tag_MPextension_use),
32497 T (Tag_DIV_use),
f31fef98
NC		 32498 T (Tag_nodefaults),
32499 T (Tag_also_compatible_with),
32500 T (Tag_conformance),
32501 T (Tag_T2EE_use),
32502 T (Tag_Virtualization_use),
15afaa63 32503 T (Tag_DSP_extension),
a7ad558c 32504 T (Tag_MVE_arch),
cd21e546 32505 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 32506#undef T
f31fef98 32507 };
e04befd0
AS		 32508 unsigned int i;
32509
32510 if (name == NULL)
32511 return -1;
32512
f31fef98 32513 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 32514 if (streq (name, attribute_table[i].name))
e04befd0
AS		 32515 return attribute_table[i].tag;
32516
32517 return -1;
32518}
267bf995 32519
93ef582d
NC		 32520/* Apply sym value for relocations only in the case that they are for
32521 local symbols in the same segment as the fixup and you have the
32522 respective architectural feature for blx and simple switches. */
0198d5e6 32523
267bf995 32524int
93ef582d 32525arm_apply_sym_value (struct fix * fixP, segT this_seg)
267bf995
RR		 32526{
32527 if (fixP->fx_addsy
32528 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
93ef582d
NC		 32529 /* PR 17444: If the local symbol is in a different section then a reloc
32530 will always be generated for it, so applying the symbol value now
32531 will result in a double offset being stored in the relocation. */
32532 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
34e77a92 32533 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
267bf995
RR		 32534 {
32535 switch (fixP->fx_r_type)
32536 {
32537 case BFD_RELOC_ARM_PCREL_BLX:
32538 case BFD_RELOC_THUMB_PCREL_BRANCH23:
32539 if (ARM_IS_FUNC (fixP->fx_addsy))
32540 return 1;
32541 break;
32542
32543 case BFD_RELOC_ARM_PCREL_CALL:
32544 case BFD_RELOC_THUMB_PCREL_BLX:
32545 if (THUMB_IS_FUNC (fixP->fx_addsy))
93ef582d 32546 return 1;
267bf995
RR		 32547 break;
32548
32549 default:
32550 break;
32551 }
32552
32553 }
32554 return 0;
32555}
f31fef98 32556#endif /* OBJ_ELF */
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