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c906108c 1/* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
0fd88904 2
6aba47ca 3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
0fb0cc75 4 2003, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
c906108c 5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
c5aa993b 11 (at your option) any later version.
c906108c 12
c5aa993b
JM
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b 18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS
20
21#include "defs.h"
615967cb 22#include "doublest.h"
c906108c 23#include "frame.h"
d2427a71
RH
24#include "frame-unwind.h"
25#include "frame-base.h"
baa490c4 26#include "dwarf2-frame.h"
c906108c
SS
27#include "inferior.h"
28#include "symtab.h"
29#include "value.h"
30#include "gdbcmd.h"
31#include "gdbcore.h"
32#include "dis-asm.h"
33#include "symfile.h"
34#include "objfiles.h"
35#include "gdb_string.h"
c5f0f3d0 36#include "linespec.h"
4e052eda 37#include "regcache.h"
615967cb 38#include "reggroups.h"
dc129d82 39#include "arch-utils.h"
4be87837 40#include "osabi.h"
fe898f56 41#include "block.h"
7d9b040b 42#include "infcall.h"
07ea644b 43#include "trad-frame.h"
dc129d82
JT
44
45#include "elf-bfd.h"
46
47#include "alpha-tdep.h"
48
c906108c 49\f
515921d7
JB
50/* Return the name of the REGNO register.
51
52 An empty name corresponds to a register number that used to
53 be used for a virtual register. That virtual register has
54 been removed, but the index is still reserved to maintain
55 compatibility with existing remote alpha targets. */
56
fa88f677 57static const char *
d93859e2 58alpha_register_name (struct gdbarch *gdbarch, int regno)
636a6dfc 59{
5ab84872 60 static const char * const register_names[] =
636a6dfc
JT
61 {
62 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
63 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
64 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
65 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
66 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
67 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
68 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
69 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr",
44d88583 70 "pc", "", "unique"
636a6dfc
JT
71 };
72
73 if (regno < 0)
5ab84872 74 return NULL;
e8d2d628 75 if (regno >= ARRAY_SIZE(register_names))
5ab84872
RH
76 return NULL;
77 return register_names[regno];
636a6dfc 78}
d734c450 79
dc129d82 80static int
64a3914f 81alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
d734c450 82{
515921d7 83 return (regno == ALPHA_ZERO_REGNUM
64a3914f 84 || strlen (alpha_register_name (gdbarch, regno)) == 0);
d734c450
JT
85}
86
dc129d82 87static int
64a3914f 88alpha_cannot_store_register (struct gdbarch *gdbarch, int regno)
d734c450 89{
515921d7 90 return (regno == ALPHA_ZERO_REGNUM
64a3914f 91 || strlen (alpha_register_name (gdbarch, regno)) == 0);
d734c450
JT
92}
93
dc129d82 94static struct type *
c483c494 95alpha_register_type (struct gdbarch *gdbarch, int regno)
0d056799 96{
72667056 97 if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM)
0dfff4cb 98 return builtin_type (gdbarch)->builtin_data_ptr;
72667056 99 if (regno == ALPHA_PC_REGNUM)
0dfff4cb 100 return builtin_type (gdbarch)->builtin_func_ptr;
72667056
RH
101
102 /* Don't need to worry about little vs big endian until
103 some jerk tries to port to alpha-unicosmk. */
b38b6be2 104 if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31)
27067745 105 return builtin_type (gdbarch)->builtin_double;
72667056 106
df4df182 107 return builtin_type (gdbarch)->builtin_int64;
0d056799 108}
f8453e34 109
615967cb
RH
110/* Is REGNUM a member of REGGROUP? */
111
112static int
113alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
114 struct reggroup *group)
115{
116 /* Filter out any registers eliminated, but whose regnum is
117 reserved for backward compatibility, e.g. the vfp. */
ec7cc0e8
UW
118 if (gdbarch_register_name (gdbarch, regnum) == NULL
119 || *gdbarch_register_name (gdbarch, regnum) == '\0')
615967cb
RH
120 return 0;
121
df4a182b
RH
122 if (group == all_reggroup)
123 return 1;
124
125 /* Zero should not be saved or restored. Technically it is a general
126 register (just as $f31 would be a float if we represented it), but
127 there's no point displaying it during "info regs", so leave it out
128 of all groups except for "all". */
129 if (regnum == ALPHA_ZERO_REGNUM)
130 return 0;
131
132 /* All other registers are saved and restored. */
133 if (group == save_reggroup || group == restore_reggroup)
615967cb
RH
134 return 1;
135
136 /* All other groups are non-overlapping. */
137
138 /* Since this is really a PALcode memory slot... */
139 if (regnum == ALPHA_UNIQUE_REGNUM)
140 return group == system_reggroup;
141
142 /* Force the FPCR to be considered part of the floating point state. */
143 if (regnum == ALPHA_FPCR_REGNUM)
144 return group == float_reggroup;
145
146 if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31)
147 return group == float_reggroup;
148 else
149 return group == general_reggroup;
150}
151
c483c494
RH
152/* The following represents exactly the conversion performed by
153 the LDS instruction. This applies to both single-precision
154 floating point and 32-bit integers. */
155
156static void
e17a4113 157alpha_lds (struct gdbarch *gdbarch, void *out, const void *in)
c483c494 158{
e17a4113
UW
159 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
160 ULONGEST mem = extract_unsigned_integer (in, 4, byte_order);
c483c494
RH
161 ULONGEST frac = (mem >> 0) & 0x7fffff;
162 ULONGEST sign = (mem >> 31) & 1;
163 ULONGEST exp_msb = (mem >> 30) & 1;
164 ULONGEST exp_low = (mem >> 23) & 0x7f;
165 ULONGEST exp, reg;
166
167 exp = (exp_msb << 10) | exp_low;
168 if (exp_msb)
169 {
170 if (exp_low == 0x7f)
171 exp = 0x7ff;
172 }
173 else
174 {
175 if (exp_low != 0x00)
176 exp |= 0x380;
177 }
178
179 reg = (sign << 63) | (exp << 52) | (frac << 29);
e17a4113 180 store_unsigned_integer (out, 8, byte_order, reg);
c483c494
RH
181}
182
183/* Similarly, this represents exactly the conversion performed by
184 the STS instruction. */
185
39efb398 186static void
e17a4113 187alpha_sts (struct gdbarch *gdbarch, void *out, const void *in)
c483c494 188{
e17a4113 189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c483c494
RH
190 ULONGEST reg, mem;
191
e17a4113 192 reg = extract_unsigned_integer (in, 8, byte_order);
c483c494 193 mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff);
e17a4113 194 store_unsigned_integer (out, 4, byte_order, mem);
c483c494
RH
195}
196
d2427a71
RH
197/* The alpha needs a conversion between register and memory format if the
198 register is a floating point register and memory format is float, as the
199 register format must be double or memory format is an integer with 4
200 bytes or less, as the representation of integers in floating point
201 registers is different. */
202
c483c494 203static int
0abe36f5 204alpha_convert_register_p (struct gdbarch *gdbarch, int regno, struct type *type)
14696584 205{
83acabca
DJ
206 return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31
207 && TYPE_LENGTH (type) != 8);
14696584
RH
208}
209
d2427a71 210static void
ff2e87ac 211alpha_register_to_value (struct frame_info *frame, int regnum,
5b819568 212 struct type *valtype, gdb_byte *out)
5868c862 213{
2a1ce6ec
MK
214 gdb_byte in[MAX_REGISTER_SIZE];
215
ff2e87ac 216 frame_register_read (frame, regnum, in);
c483c494 217 switch (TYPE_LENGTH (valtype))
d2427a71 218 {
c483c494 219 case 4:
e17a4113 220 alpha_sts (get_frame_arch (frame), out, in);
c483c494 221 break;
c483c494 222 default:
323e0a4a 223 error (_("Cannot retrieve value from floating point register"));
d2427a71 224 }
d2427a71 225}
5868c862 226
d2427a71 227static void
ff2e87ac 228alpha_value_to_register (struct frame_info *frame, int regnum,
5b819568 229 struct type *valtype, const gdb_byte *in)
d2427a71 230{
2a1ce6ec
MK
231 gdb_byte out[MAX_REGISTER_SIZE];
232
c483c494 233 switch (TYPE_LENGTH (valtype))
d2427a71 234 {
c483c494 235 case 4:
e17a4113 236 alpha_lds (get_frame_arch (frame), out, in);
c483c494 237 break;
c483c494 238 default:
323e0a4a 239 error (_("Cannot store value in floating point register"));
d2427a71 240 }
ff2e87ac 241 put_frame_register (frame, regnum, out);
5868c862
JT
242}
243
d2427a71
RH
244\f
245/* The alpha passes the first six arguments in the registers, the rest on
c88e30c0
RH
246 the stack. The register arguments are stored in ARG_REG_BUFFER, and
247 then moved into the register file; this simplifies the passing of a
248 large struct which extends from the registers to the stack, plus avoids
249 three ptrace invocations per word.
250
251 We don't bother tracking which register values should go in integer
252 regs or fp regs; we load the same values into both.
253
d2427a71
RH
254 If the called function is returning a structure, the address of the
255 structure to be returned is passed as a hidden first argument. */
c906108c 256
d2427a71 257static CORE_ADDR
7d9b040b 258alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
c88e30c0
RH
259 struct regcache *regcache, CORE_ADDR bp_addr,
260 int nargs, struct value **args, CORE_ADDR sp,
261 int struct_return, CORE_ADDR struct_addr)
c906108c 262{
e17a4113 263 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d2427a71
RH
264 int i;
265 int accumulate_size = struct_return ? 8 : 0;
d2427a71 266 struct alpha_arg
c906108c 267 {
2a1ce6ec 268 gdb_byte *contents;
d2427a71
RH
269 int len;
270 int offset;
271 };
c88e30c0
RH
272 struct alpha_arg *alpha_args
273 = (struct alpha_arg *) alloca (nargs * sizeof (struct alpha_arg));
52f0bd74 274 struct alpha_arg *m_arg;
2a1ce6ec 275 gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS];
d2427a71 276 int required_arg_regs;
7d9b040b 277 CORE_ADDR func_addr = find_function_addr (function, NULL);
c906108c 278
c88e30c0
RH
279 /* The ABI places the address of the called function in T12. */
280 regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr);
281
282 /* Set the return address register to point to the entry point
283 of the program, where a breakpoint lies in wait. */
284 regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr);
285
286 /* Lay out the arguments in memory. */
d2427a71
RH
287 for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++)
288 {
289 struct value *arg = args[i];
4991999e 290 struct type *arg_type = check_typedef (value_type (arg));
c88e30c0 291
d2427a71
RH
292 /* Cast argument to long if necessary as the compiler does it too. */
293 switch (TYPE_CODE (arg_type))
c906108c 294 {
d2427a71
RH
295 case TYPE_CODE_INT:
296 case TYPE_CODE_BOOL:
297 case TYPE_CODE_CHAR:
298 case TYPE_CODE_RANGE:
299 case TYPE_CODE_ENUM:
0ede8eca 300 if (TYPE_LENGTH (arg_type) == 4)
d2427a71 301 {
0ede8eca
RH
302 /* 32-bit values must be sign-extended to 64 bits
303 even if the base data type is unsigned. */
df4df182 304 arg_type = builtin_type (gdbarch)->builtin_int32;
0ede8eca
RH
305 arg = value_cast (arg_type, arg);
306 }
307 if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE)
308 {
df4df182 309 arg_type = builtin_type (gdbarch)->builtin_int64;
d2427a71
RH
310 arg = value_cast (arg_type, arg);
311 }
312 break;
7b5e1cb3 313
c88e30c0
RH
314 case TYPE_CODE_FLT:
315 /* "float" arguments loaded in registers must be passed in
316 register format, aka "double". */
317 if (accumulate_size < sizeof (arg_reg_buffer)
318 && TYPE_LENGTH (arg_type) == 4)
319 {
27067745 320 arg_type = builtin_type (gdbarch)->builtin_double;
c88e30c0
RH
321 arg = value_cast (arg_type, arg);
322 }
323 /* Tru64 5.1 has a 128-bit long double, and passes this by
324 invisible reference. No one else uses this data type. */
325 else if (TYPE_LENGTH (arg_type) == 16)
326 {
327 /* Allocate aligned storage. */
328 sp = (sp & -16) - 16;
329
330 /* Write the real data into the stack. */
0fd88904 331 write_memory (sp, value_contents (arg), 16);
c88e30c0
RH
332
333 /* Construct the indirection. */
334 arg_type = lookup_pointer_type (arg_type);
335 arg = value_from_pointer (arg_type, sp);
336 }
337 break;
7b5e1cb3
RH
338
339 case TYPE_CODE_COMPLEX:
340 /* ??? The ABI says that complex values are passed as two
341 separate scalar values. This distinction only matters
342 for complex float. However, GCC does not implement this. */
343
344 /* Tru64 5.1 has a 128-bit long double, and passes this by
345 invisible reference. */
346 if (TYPE_LENGTH (arg_type) == 32)
347 {
348 /* Allocate aligned storage. */
349 sp = (sp & -16) - 16;
350
351 /* Write the real data into the stack. */
0fd88904 352 write_memory (sp, value_contents (arg), 32);
7b5e1cb3
RH
353
354 /* Construct the indirection. */
355 arg_type = lookup_pointer_type (arg_type);
356 arg = value_from_pointer (arg_type, sp);
357 }
358 break;
359
d2427a71
RH
360 default:
361 break;
c906108c 362 }
d2427a71
RH
363 m_arg->len = TYPE_LENGTH (arg_type);
364 m_arg->offset = accumulate_size;
365 accumulate_size = (accumulate_size + m_arg->len + 7) & ~7;
0fd88904 366 m_arg->contents = value_contents_writeable (arg);
c906108c
SS
367 }
368
d2427a71
RH
369 /* Determine required argument register loads, loading an argument register
370 is expensive as it uses three ptrace calls. */
371 required_arg_regs = accumulate_size / 8;
372 if (required_arg_regs > ALPHA_NUM_ARG_REGS)
373 required_arg_regs = ALPHA_NUM_ARG_REGS;
c906108c 374
d2427a71 375 /* Make room for the arguments on the stack. */
c88e30c0
RH
376 if (accumulate_size < sizeof(arg_reg_buffer))
377 accumulate_size = 0;
378 else
379 accumulate_size -= sizeof(arg_reg_buffer);
d2427a71 380 sp -= accumulate_size;
c906108c 381
c88e30c0 382 /* Keep sp aligned to a multiple of 16 as the ABI requires. */
d2427a71 383 sp &= ~15;
c906108c 384
d2427a71
RH
385 /* `Push' arguments on the stack. */
386 for (i = nargs; m_arg--, --i >= 0;)
c906108c 387 {
2a1ce6ec 388 gdb_byte *contents = m_arg->contents;
c88e30c0
RH
389 int offset = m_arg->offset;
390 int len = m_arg->len;
391
392 /* Copy the bytes destined for registers into arg_reg_buffer. */
393 if (offset < sizeof(arg_reg_buffer))
394 {
395 if (offset + len <= sizeof(arg_reg_buffer))
396 {
397 memcpy (arg_reg_buffer + offset, contents, len);
398 continue;
399 }
400 else
401 {
402 int tlen = sizeof(arg_reg_buffer) - offset;
403 memcpy (arg_reg_buffer + offset, contents, tlen);
404 offset += tlen;
405 contents += tlen;
406 len -= tlen;
407 }
408 }
409
410 /* Everything else goes to the stack. */
411 write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len);
c906108c 412 }
c88e30c0 413 if (struct_return)
e17a4113
UW
414 store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE,
415 byte_order, struct_addr);
c906108c 416
d2427a71
RH
417 /* Load the argument registers. */
418 for (i = 0; i < required_arg_regs; i++)
419 {
09cc52fd
RH
420 regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i,
421 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
422 regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i,
423 arg_reg_buffer + i*ALPHA_REGISTER_SIZE);
d2427a71 424 }
c906108c 425
09cc52fd
RH
426 /* Finally, update the stack pointer. */
427 regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp);
428
c88e30c0 429 return sp;
c906108c
SS
430}
431
5ec2bb99
RH
432/* Extract from REGCACHE the value about to be returned from a function
433 and copy it into VALBUF. */
d2427a71 434
dc129d82 435static void
5ec2bb99 436alpha_extract_return_value (struct type *valtype, struct regcache *regcache,
5b819568 437 gdb_byte *valbuf)
140f9984 438{
e17a4113
UW
439 struct gdbarch *gdbarch = get_regcache_arch (regcache);
440 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
7b5e1cb3 441 int length = TYPE_LENGTH (valtype);
2a1ce6ec 442 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
5ec2bb99
RH
443 ULONGEST l;
444
445 switch (TYPE_CODE (valtype))
446 {
447 case TYPE_CODE_FLT:
7b5e1cb3 448 switch (length)
5ec2bb99
RH
449 {
450 case 4:
451 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer);
e17a4113 452 alpha_sts (gdbarch, valbuf, raw_buffer);
5ec2bb99
RH
453 break;
454
455 case 8:
456 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
457 break;
458
24064b5c
RH
459 case 16:
460 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
461 read_memory (l, valbuf, 16);
462 break;
463
5ec2bb99 464 default:
323e0a4a 465 internal_error (__FILE__, __LINE__, _("unknown floating point width"));
5ec2bb99
RH
466 }
467 break;
468
7b5e1cb3
RH
469 case TYPE_CODE_COMPLEX:
470 switch (length)
471 {
472 case 8:
473 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
474 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
475 break;
476
477 case 16:
478 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf);
2a1ce6ec 479 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
7b5e1cb3
RH
480 break;
481
482 case 32:
483 regcache_cooked_read_signed (regcache, ALPHA_V0_REGNUM, &l);
484 read_memory (l, valbuf, 32);
485 break;
486
487 default:
323e0a4a 488 internal_error (__FILE__, __LINE__, _("unknown floating point width"));
7b5e1cb3
RH
489 }
490 break;
491
5ec2bb99
RH
492 default:
493 /* Assume everything else degenerates to an integer. */
494 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l);
e17a4113 495 store_unsigned_integer (valbuf, length, byte_order, l);
5ec2bb99
RH
496 break;
497 }
140f9984
JT
498}
499
5ec2bb99
RH
500/* Insert the given value into REGCACHE as if it was being
501 returned by a function. */
0d056799 502
d2427a71 503static void
5ec2bb99 504alpha_store_return_value (struct type *valtype, struct regcache *regcache,
5b819568 505 const gdb_byte *valbuf)
c906108c 506{
df4df182 507 struct gdbarch *gdbarch = get_regcache_arch (regcache);
d2427a71 508 int length = TYPE_LENGTH (valtype);
2a1ce6ec 509 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
5ec2bb99 510 ULONGEST l;
d2427a71 511
5ec2bb99 512 switch (TYPE_CODE (valtype))
c906108c 513 {
5ec2bb99
RH
514 case TYPE_CODE_FLT:
515 switch (length)
516 {
517 case 4:
e17a4113 518 alpha_lds (gdbarch, raw_buffer, valbuf);
f75d70cc
RH
519 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer);
520 break;
5ec2bb99
RH
521
522 case 8:
523 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
524 break;
525
24064b5c
RH
526 case 16:
527 /* FIXME: 128-bit long doubles are returned like structures:
528 by writing into indirect storage provided by the caller
529 as the first argument. */
323e0a4a 530 error (_("Cannot set a 128-bit long double return value."));
24064b5c 531
5ec2bb99 532 default:
323e0a4a 533 internal_error (__FILE__, __LINE__, _("unknown floating point width"));
5ec2bb99
RH
534 }
535 break;
d2427a71 536
7b5e1cb3
RH
537 case TYPE_CODE_COMPLEX:
538 switch (length)
539 {
540 case 8:
541 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
542 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
543 break;
544
545 case 16:
546 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf);
2a1ce6ec 547 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8);
7b5e1cb3
RH
548 break;
549
550 case 32:
551 /* FIXME: 128-bit long doubles are returned like structures:
552 by writing into indirect storage provided by the caller
553 as the first argument. */
323e0a4a 554 error (_("Cannot set a 128-bit long double return value."));
7b5e1cb3
RH
555
556 default:
323e0a4a 557 internal_error (__FILE__, __LINE__, _("unknown floating point width"));
7b5e1cb3
RH
558 }
559 break;
560
5ec2bb99
RH
561 default:
562 /* Assume everything else degenerates to an integer. */
0ede8eca
RH
563 /* 32-bit values must be sign-extended to 64 bits
564 even if the base data type is unsigned. */
565 if (length == 4)
df4df182 566 valtype = builtin_type (gdbarch)->builtin_int32;
5ec2bb99
RH
567 l = unpack_long (valtype, valbuf);
568 regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l);
569 break;
570 }
c906108c
SS
571}
572
9823e921 573static enum return_value_convention
c055b101
CV
574alpha_return_value (struct gdbarch *gdbarch, struct type *func_type,
575 struct type *type, struct regcache *regcache,
576 gdb_byte *readbuf, const gdb_byte *writebuf)
9823e921
RH
577{
578 enum type_code code = TYPE_CODE (type);
579
580 if ((code == TYPE_CODE_STRUCT
581 || code == TYPE_CODE_UNION
582 || code == TYPE_CODE_ARRAY)
583 && gdbarch_tdep (gdbarch)->return_in_memory (type))
584 {
585 if (readbuf)
586 {
587 ULONGEST addr;
588 regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr);
589 read_memory (addr, readbuf, TYPE_LENGTH (type));
590 }
591
592 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
593 }
594
595 if (readbuf)
596 alpha_extract_return_value (type, regcache, readbuf);
597 if (writebuf)
598 alpha_store_return_value (type, regcache, writebuf);
599
600 return RETURN_VALUE_REGISTER_CONVENTION;
601}
602
603static int
604alpha_return_in_memory_always (struct type *type)
605{
606 return 1;
607}
d2427a71 608\f
2a1ce6ec 609static const gdb_byte *
67d57894 610alpha_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
c906108c 611{
2a1ce6ec 612 static const gdb_byte break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */
c906108c 613
2a1ce6ec
MK
614 *len = sizeof(break_insn);
615 return break_insn;
d2427a71 616}
c906108c 617
d2427a71
RH
618\f
619/* This returns the PC of the first insn after the prologue.
620 If we can't find the prologue, then return 0. */
c906108c 621
d2427a71
RH
622CORE_ADDR
623alpha_after_prologue (CORE_ADDR pc)
c906108c 624{
d2427a71
RH
625 struct symtab_and_line sal;
626 CORE_ADDR func_addr, func_end;
c906108c 627
d2427a71 628 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
c5aa993b 629 return 0;
c906108c 630
d2427a71
RH
631 sal = find_pc_line (func_addr, 0);
632 if (sal.end < func_end)
633 return sal.end;
c5aa993b 634
d2427a71
RH
635 /* The line after the prologue is after the end of the function. In this
636 case, tell the caller to find the prologue the hard way. */
637 return 0;
c906108c
SS
638}
639
d2427a71
RH
640/* Read an instruction from memory at PC, looking through breakpoints. */
641
642unsigned int
e17a4113 643alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 644{
e17a4113 645 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e8d2d628 646 gdb_byte buf[ALPHA_INSN_SIZE];
d2427a71 647 int status;
c5aa993b 648
8defab1a 649 status = target_read_memory (pc, buf, sizeof (buf));
d2427a71
RH
650 if (status)
651 memory_error (status, pc);
e17a4113 652 return extract_unsigned_integer (buf, sizeof (buf), byte_order);
d2427a71 653}
c5aa993b 654
d2427a71
RH
655/* To skip prologues, I use this predicate. Returns either PC itself
656 if the code at PC does not look like a function prologue; otherwise
657 returns an address that (if we're lucky) follows the prologue. If
658 LENIENT, then we must skip everything which is involved in setting
659 up the frame (it's OK to skip more, just so long as we don't skip
660 anything which might clobber the registers which are being saved. */
c906108c 661
d2427a71 662static CORE_ADDR
6093d2eb 663alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
d2427a71
RH
664{
665 unsigned long inst;
666 int offset;
667 CORE_ADDR post_prologue_pc;
e8d2d628 668 gdb_byte buf[ALPHA_INSN_SIZE];
c906108c 669
d2427a71
RH
670 /* Silently return the unaltered pc upon memory errors.
671 This could happen on OSF/1 if decode_line_1 tries to skip the
672 prologue for quickstarted shared library functions when the
673 shared library is not yet mapped in.
674 Reading target memory is slow over serial lines, so we perform
675 this check only if the target has shared libraries (which all
676 Alpha targets do). */
e8d2d628 677 if (target_read_memory (pc, buf, sizeof (buf)))
d2427a71 678 return pc;
c906108c 679
d2427a71
RH
680 /* See if we can determine the end of the prologue via the symbol table.
681 If so, then return either PC, or the PC after the prologue, whichever
682 is greater. */
c906108c 683
d2427a71
RH
684 post_prologue_pc = alpha_after_prologue (pc);
685 if (post_prologue_pc != 0)
686 return max (pc, post_prologue_pc);
c906108c 687
d2427a71
RH
688 /* Can't determine prologue from the symbol table, need to examine
689 instructions. */
dc1b0db2 690
d2427a71
RH
691 /* Skip the typical prologue instructions. These are the stack adjustment
692 instruction and the instructions that save registers on the stack
693 or in the gcc frame. */
e8d2d628 694 for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE)
d2427a71 695 {
e17a4113 696 inst = alpha_read_insn (gdbarch, pc + offset);
c906108c 697
d2427a71
RH
698 if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
699 continue;
700 if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */
701 continue;
702 if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
703 continue;
704 if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */
705 continue;
c906108c 706
d2427a71
RH
707 if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */
708 || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */
709 && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */
710 continue;
c906108c 711
d2427a71
RH
712 if (inst == 0x47de040f) /* bis sp,sp,fp */
713 continue;
714 if (inst == 0x47fe040f) /* bis zero,sp,fp */
715 continue;
c906108c 716
d2427a71 717 break;
c906108c 718 }
d2427a71
RH
719 return pc + offset;
720}
c906108c 721
d2427a71
RH
722\f
723/* Figure out where the longjmp will land.
724 We expect the first arg to be a pointer to the jmp_buf structure from
725 which we extract the PC (JB_PC) that we will land at. The PC is copied
726 into the "pc". This routine returns true on success. */
c906108c
SS
727
728static int
60ade65d 729alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
c906108c 730{
e17a4113
UW
731 struct gdbarch *gdbarch = get_frame_arch (frame);
732 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
733 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d2427a71 734 CORE_ADDR jb_addr;
2a1ce6ec 735 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE];
c906108c 736
60ade65d 737 jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM);
c906108c 738
d2427a71
RH
739 if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size),
740 raw_buffer, tdep->jb_elt_size))
c906108c 741 return 0;
d2427a71 742
e17a4113 743 *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order);
d2427a71 744 return 1;
c906108c
SS
745}
746
d2427a71
RH
747\f
748/* Frame unwinder for signal trampolines. We use alpha tdep bits that
749 describe the location and shape of the sigcontext structure. After
750 that, all registers are in memory, so it's easy. */
751/* ??? Shouldn't we be able to do this generically, rather than with
752 OSABI data specific to Alpha? */
753
754struct alpha_sigtramp_unwind_cache
c906108c 755{
d2427a71
RH
756 CORE_ADDR sigcontext_addr;
757};
c906108c 758
d2427a71 759static struct alpha_sigtramp_unwind_cache *
6834c9bb 760alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
d2427a71
RH
761 void **this_prologue_cache)
762{
763 struct alpha_sigtramp_unwind_cache *info;
764 struct gdbarch_tdep *tdep;
c906108c 765
d2427a71
RH
766 if (*this_prologue_cache)
767 return *this_prologue_cache;
c906108c 768
d2427a71
RH
769 info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache);
770 *this_prologue_cache = info;
c906108c 771
6834c9bb
JB
772 tdep = gdbarch_tdep (get_frame_arch (this_frame));
773 info->sigcontext_addr = tdep->sigcontext_addr (this_frame);
c906108c 774
d2427a71 775 return info;
c906108c
SS
776}
777
138e7be5
MK
778/* Return the address of REGNUM in a sigtramp frame. Since this is
779 all arithmetic, it doesn't seem worthwhile to cache it. */
c5aa993b 780
d2427a71 781static CORE_ADDR
be8626e0
MD
782alpha_sigtramp_register_address (struct gdbarch *gdbarch,
783 CORE_ADDR sigcontext_addr, int regnum)
d2427a71 784{
be8626e0 785 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
138e7be5
MK
786
787 if (regnum >= 0 && regnum < 32)
788 return sigcontext_addr + tdep->sc_regs_offset + regnum * 8;
789 else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32)
790 return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8;
791 else if (regnum == ALPHA_PC_REGNUM)
792 return sigcontext_addr + tdep->sc_pc_offset;
c5aa993b 793
d2427a71 794 return 0;
c906108c
SS
795}
796
d2427a71
RH
797/* Given a GDB frame, determine the address of the calling function's
798 frame. This will be used to create a new GDB frame struct. */
140f9984 799
dc129d82 800static void
6834c9bb 801alpha_sigtramp_frame_this_id (struct frame_info *this_frame,
d2427a71
RH
802 void **this_prologue_cache,
803 struct frame_id *this_id)
c906108c 804{
6834c9bb 805 struct gdbarch *gdbarch = get_frame_arch (this_frame);
be8626e0 806 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
d2427a71 807 struct alpha_sigtramp_unwind_cache *info
6834c9bb 808 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
d2427a71
RH
809 CORE_ADDR stack_addr, code_addr;
810
811 /* If the OSABI couldn't locate the sigcontext, give up. */
812 if (info->sigcontext_addr == 0)
813 return;
814
815 /* If we have dynamic signal trampolines, find their start.
816 If we do not, then we must assume there is a symbol record
817 that can provide the start address. */
d2427a71 818 if (tdep->dynamic_sigtramp_offset)
c906108c 819 {
d2427a71 820 int offset;
6834c9bb 821 code_addr = get_frame_pc (this_frame);
e17a4113 822 offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr);
d2427a71
RH
823 if (offset >= 0)
824 code_addr -= offset;
c906108c 825 else
d2427a71 826 code_addr = 0;
c906108c 827 }
d2427a71 828 else
6834c9bb 829 code_addr = get_frame_func (this_frame);
c906108c 830
d2427a71 831 /* The stack address is trivially read from the sigcontext. */
be8626e0 832 stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr,
d2427a71 833 ALPHA_SP_REGNUM);
6834c9bb 834 stack_addr = get_frame_memory_unsigned (this_frame, stack_addr,
b21fd293 835 ALPHA_REGISTER_SIZE);
c906108c 836
d2427a71 837 *this_id = frame_id_build (stack_addr, code_addr);
c906108c
SS
838}
839
d2427a71 840/* Retrieve the value of REGNUM in FRAME. Don't give up! */
c906108c 841
6834c9bb
JB
842static struct value *
843alpha_sigtramp_frame_prev_register (struct frame_info *this_frame,
844 void **this_prologue_cache, int regnum)
c906108c 845{
d2427a71 846 struct alpha_sigtramp_unwind_cache *info
6834c9bb 847 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache);
d2427a71 848 CORE_ADDR addr;
c906108c 849
d2427a71 850 if (info->sigcontext_addr != 0)
c906108c 851 {
d2427a71 852 /* All integer and fp registers are stored in memory. */
6834c9bb 853 addr = alpha_sigtramp_register_address (get_frame_arch (this_frame),
be8626e0 854 info->sigcontext_addr, regnum);
d2427a71 855 if (addr != 0)
6834c9bb 856 return frame_unwind_got_memory (this_frame, regnum, addr);
c906108c
SS
857 }
858
d2427a71
RH
859 /* This extra register may actually be in the sigcontext, but our
860 current description of it in alpha_sigtramp_frame_unwind_cache
861 doesn't include it. Too bad. Fall back on whatever's in the
862 outer frame. */
6834c9bb 863 return frame_unwind_got_register (this_frame, regnum, regnum);
d2427a71 864}
c906108c 865
6834c9bb
JB
866static int
867alpha_sigtramp_frame_sniffer (const struct frame_unwind *self,
868 struct frame_info *this_frame,
869 void **this_prologue_cache)
d2427a71 870{
6834c9bb
JB
871 struct gdbarch *gdbarch = get_frame_arch (this_frame);
872 CORE_ADDR pc = get_frame_pc (this_frame);
d2427a71 873 char *name;
c906108c 874
f2524b93
AC
875 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead
876 look at tramp-frame.h and other simplier per-architecture
877 sigtramp unwinders. */
878
879 /* We shouldn't even bother to try if the OSABI didn't register a
880 sigcontext_addr handler or pc_in_sigtramp hander. */
ec7cc0e8 881 if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL)
6834c9bb 882 return 0;
ec7cc0e8 883 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL)
6834c9bb 884 return 0;
c906108c 885
d2427a71
RH
886 /* Otherwise we should be in a signal frame. */
887 find_pc_partial_function (pc, &name, NULL, NULL);
e17a4113 888 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name))
6834c9bb 889 return 1;
c906108c 890
6834c9bb 891 return 0;
c906108c 892}
6834c9bb
JB
893
894static const struct frame_unwind alpha_sigtramp_frame_unwind = {
895 SIGTRAMP_FRAME,
896 alpha_sigtramp_frame_this_id,
897 alpha_sigtramp_frame_prev_register,
898 NULL,
899 alpha_sigtramp_frame_sniffer
900};
901
d2427a71 902\f
c906108c 903
d2427a71
RH
904/* Heuristic_proc_start may hunt through the text section for a long
905 time across a 2400 baud serial line. Allows the user to limit this
906 search. */
907static unsigned int heuristic_fence_post = 0;
c906108c 908
d2427a71
RH
909/* Attempt to locate the start of the function containing PC. We assume that
910 the previous function ends with an about_to_return insn. Not foolproof by
911 any means, since gcc is happy to put the epilogue in the middle of a
912 function. But we're guessing anyway... */
c906108c 913
d2427a71 914static CORE_ADDR
be8626e0 915alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc)
d2427a71 916{
be8626e0 917 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
d2427a71
RH
918 CORE_ADDR last_non_nop = pc;
919 CORE_ADDR fence = pc - heuristic_fence_post;
920 CORE_ADDR orig_pc = pc;
fbe586ae 921 CORE_ADDR func;
d6b48e9c 922 struct inferior *inf;
9e0b60a8 923
d2427a71
RH
924 if (pc == 0)
925 return 0;
9e0b60a8 926
fbe586ae
RH
927 /* First see if we can find the start of the function from minimal
928 symbol information. This can succeed with a binary that doesn't
929 have debug info, but hasn't been stripped. */
930 func = get_pc_function_start (pc);
931 if (func)
932 return func;
933
d2427a71
RH
934 if (heuristic_fence_post == UINT_MAX
935 || fence < tdep->vm_min_address)
936 fence = tdep->vm_min_address;
c906108c 937
d2427a71
RH
938 /* Search back for previous return; also stop at a 0, which might be
939 seen for instance before the start of a code section. Don't include
940 nops, since this usually indicates padding between functions. */
e8d2d628 941 for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE)
c906108c 942 {
e17a4113 943 unsigned int insn = alpha_read_insn (gdbarch, pc);
d2427a71 944 switch (insn)
c906108c 945 {
d2427a71
RH
946 case 0: /* invalid insn */
947 case 0x6bfa8001: /* ret $31,($26),1 */
948 return last_non_nop;
949
950 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */
951 case 0x47ff041f: /* nop: bis $31,$31,$31 */
952 break;
953
954 default:
955 last_non_nop = pc;
956 break;
c906108c 957 }
d2427a71 958 }
c906108c 959
d6b48e9c
PA
960 inf = current_inferior ();
961
d2427a71
RH
962 /* It's not clear to me why we reach this point when stopping quietly,
963 but with this test, at least we don't print out warnings for every
964 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */
d6b48e9c 965 if (inf->stop_soon == NO_STOP_QUIETLY)
d2427a71
RH
966 {
967 static int blurb_printed = 0;
c906108c 968
d2427a71 969 if (fence == tdep->vm_min_address)
323e0a4a 970 warning (_("Hit beginning of text section without finding \
5af949e3 971enclosing function for address %s"), paddress (gdbarch, orig_pc));
c906108c 972 else
323e0a4a 973 warning (_("Hit heuristic-fence-post without finding \
5af949e3 974enclosing function for address %s"), paddress (gdbarch, orig_pc));
c906108c 975
d2427a71
RH
976 if (!blurb_printed)
977 {
323e0a4a 978 printf_filtered (_("\
d2427a71
RH
979This warning occurs if you are debugging a function without any symbols\n\
980(for example, in a stripped executable). In that case, you may wish to\n\
981increase the size of the search with the `set heuristic-fence-post' command.\n\
982\n\
983Otherwise, you told GDB there was a function where there isn't one, or\n\
323e0a4a 984(more likely) you have encountered a bug in GDB.\n"));
d2427a71
RH
985 blurb_printed = 1;
986 }
987 }
c906108c 988
d2427a71
RH
989 return 0;
990}
c906108c 991
07ea644b
MD
992/* Fallback alpha frame unwinder. Uses instruction scanning and knows
993 something about the traditional layout of alpha stack frames. */
994
995struct alpha_heuristic_unwind_cache
996{
997 CORE_ADDR vfp;
998 CORE_ADDR start_pc;
999 struct trad_frame_saved_reg *saved_regs;
1000 int return_reg;
1001};
1002
fbe586ae 1003static struct alpha_heuristic_unwind_cache *
6834c9bb 1004alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame,
d2427a71
RH
1005 void **this_prologue_cache,
1006 CORE_ADDR start_pc)
1007{
6834c9bb 1008 struct gdbarch *gdbarch = get_frame_arch (this_frame);
d2427a71
RH
1009 struct alpha_heuristic_unwind_cache *info;
1010 ULONGEST val;
1011 CORE_ADDR limit_pc, cur_pc;
1012 int frame_reg, frame_size, return_reg, reg;
c906108c 1013
d2427a71
RH
1014 if (*this_prologue_cache)
1015 return *this_prologue_cache;
c906108c 1016
d2427a71
RH
1017 info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache);
1018 *this_prologue_cache = info;
6834c9bb 1019 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
c906108c 1020
6834c9bb 1021 limit_pc = get_frame_pc (this_frame);
d2427a71 1022 if (start_pc == 0)
be8626e0 1023 start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc);
d2427a71 1024 info->start_pc = start_pc;
c906108c 1025
d2427a71
RH
1026 frame_reg = ALPHA_SP_REGNUM;
1027 frame_size = 0;
1028 return_reg = -1;
c906108c 1029
d2427a71
RH
1030 /* If we've identified a likely place to start, do code scanning. */
1031 if (start_pc != 0)
c5aa993b 1032 {
d2427a71
RH
1033 /* Limit the forward search to 50 instructions. */
1034 if (start_pc + 200 < limit_pc)
1035 limit_pc = start_pc + 200;
c5aa993b 1036
e8d2d628 1037 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE)
d2427a71 1038 {
e17a4113 1039 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
c5aa993b 1040
d2427a71
RH
1041 if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
1042 {
1043 if (word & 0x8000)
1044 {
1045 /* Consider only the first stack allocation instruction
1046 to contain the static size of the frame. */
1047 if (frame_size == 0)
1048 frame_size = (-word) & 0xffff;
1049 }
1050 else
1051 {
1052 /* Exit loop if a positive stack adjustment is found, which
1053 usually means that the stack cleanup code in the function
1054 epilogue is reached. */
1055 break;
1056 }
1057 }
1058 else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1059 {
1060 reg = (word & 0x03e00000) >> 21;
1061
d15bfd3a
AC
1062 /* Ignore this instruction if we have already encountered
1063 an instruction saving the same register earlier in the
1064 function code. The current instruction does not tell
1065 us where the original value upon function entry is saved.
1066 All it says is that the function we are scanning reused
1067 that register for some computation of its own, and is now
1068 saving its result. */
07ea644b 1069 if (trad_frame_addr_p(info->saved_regs, reg))
d15bfd3a
AC
1070 continue;
1071
d2427a71
RH
1072 if (reg == 31)
1073 continue;
1074
1075 /* Do not compute the address where the register was saved yet,
1076 because we don't know yet if the offset will need to be
1077 relative to $sp or $fp (we can not compute the address
1078 relative to $sp if $sp is updated during the execution of
1079 the current subroutine, for instance when doing some alloca).
1080 So just store the offset for the moment, and compute the
1081 address later when we know whether this frame has a frame
1082 pointer or not. */
1083 /* Hack: temporarily add one, so that the offset is non-zero
1084 and we can tell which registers have save offsets below. */
07ea644b 1085 info->saved_regs[reg].addr = (word & 0xffff) + 1;
d2427a71
RH
1086
1087 /* Starting with OSF/1-3.2C, the system libraries are shipped
1088 without local symbols, but they still contain procedure
1089 descriptors without a symbol reference. GDB is currently
1090 unable to find these procedure descriptors and uses
1091 heuristic_proc_desc instead.
1092 As some low level compiler support routines (__div*, __add*)
1093 use a non-standard return address register, we have to
1094 add some heuristics to determine the return address register,
1095 or stepping over these routines will fail.
1096 Usually the return address register is the first register
1097 saved on the stack, but assembler optimization might
1098 rearrange the register saves.
1099 So we recognize only a few registers (t7, t9, ra) within
1100 the procedure prologue as valid return address registers.
1101 If we encounter a return instruction, we extract the
1102 the return address register from it.
1103
1104 FIXME: Rewriting GDB to access the procedure descriptors,
1105 e.g. via the minimal symbol table, might obviate this hack. */
1106 if (return_reg == -1
1107 && cur_pc < (start_pc + 80)
1108 && (reg == ALPHA_T7_REGNUM
1109 || reg == ALPHA_T9_REGNUM
1110 || reg == ALPHA_RA_REGNUM))
1111 return_reg = reg;
1112 }
1113 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1114 return_reg = (word >> 16) & 0x1f;
1115 else if (word == 0x47de040f) /* bis sp,sp,fp */
1116 frame_reg = ALPHA_GCC_FP_REGNUM;
1117 else if (word == 0x47fe040f) /* bis zero,sp,fp */
1118 frame_reg = ALPHA_GCC_FP_REGNUM;
1119 }
c5aa993b 1120
d2427a71
RH
1121 /* If we haven't found a valid return address register yet, keep
1122 searching in the procedure prologue. */
1123 if (return_reg == -1)
1124 {
1125 while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80))
1126 {
e17a4113 1127 unsigned int word = alpha_read_insn (gdbarch, cur_pc);
c5aa993b 1128
d2427a71
RH
1129 if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1130 {
1131 reg = (word & 0x03e00000) >> 21;
1132 if (reg == ALPHA_T7_REGNUM
1133 || reg == ALPHA_T9_REGNUM
1134 || reg == ALPHA_RA_REGNUM)
1135 {
1136 return_reg = reg;
1137 break;
1138 }
1139 }
1140 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1141 {
1142 return_reg = (word >> 16) & 0x1f;
1143 break;
1144 }
85b32d22 1145
e8d2d628 1146 cur_pc += ALPHA_INSN_SIZE;
d2427a71
RH
1147 }
1148 }
c906108c 1149 }
c906108c 1150
d2427a71
RH
1151 /* Failing that, do default to the customary RA. */
1152 if (return_reg == -1)
1153 return_reg = ALPHA_RA_REGNUM;
1154 info->return_reg = return_reg;
f8453e34 1155
6834c9bb 1156 val = get_frame_register_unsigned (this_frame, frame_reg);
d2427a71 1157 info->vfp = val + frame_size;
c906108c 1158
d2427a71
RH
1159 /* Convert offsets to absolute addresses. See above about adding
1160 one to the offsets to make all detected offsets non-zero. */
1161 for (reg = 0; reg < ALPHA_NUM_REGS; ++reg)
07ea644b
MD
1162 if (trad_frame_addr_p(info->saved_regs, reg))
1163 info->saved_regs[reg].addr += val - 1;
d2427a71 1164
bfd66dd9
JB
1165 /* The stack pointer of the previous frame is computed by popping
1166 the current stack frame. */
1167 if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM))
1168 trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp);
1169
d2427a71 1170 return info;
c906108c 1171}
c906108c 1172
d2427a71
RH
1173/* Given a GDB frame, determine the address of the calling function's
1174 frame. This will be used to create a new GDB frame struct. */
1175
fbe586ae 1176static void
6834c9bb
JB
1177alpha_heuristic_frame_this_id (struct frame_info *this_frame,
1178 void **this_prologue_cache,
1179 struct frame_id *this_id)
c906108c 1180{
d2427a71 1181 struct alpha_heuristic_unwind_cache *info
6834c9bb 1182 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
c906108c 1183
d2427a71 1184 *this_id = frame_id_build (info->vfp, info->start_pc);
c906108c
SS
1185}
1186
d2427a71
RH
1187/* Retrieve the value of REGNUM in FRAME. Don't give up! */
1188
6834c9bb
JB
1189static struct value *
1190alpha_heuristic_frame_prev_register (struct frame_info *this_frame,
1191 void **this_prologue_cache, int regnum)
c906108c 1192{
d2427a71 1193 struct alpha_heuristic_unwind_cache *info
6834c9bb 1194 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
d2427a71
RH
1195
1196 /* The PC of the previous frame is stored in the link register of
1197 the current frame. Frob regnum so that we pull the value from
1198 the correct place. */
1199 if (regnum == ALPHA_PC_REGNUM)
1200 regnum = info->return_reg;
1201
6834c9bb 1202 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
95b80706
JT
1203}
1204
d2427a71
RH
1205static const struct frame_unwind alpha_heuristic_frame_unwind = {
1206 NORMAL_FRAME,
1207 alpha_heuristic_frame_this_id,
6834c9bb
JB
1208 alpha_heuristic_frame_prev_register,
1209 NULL,
1210 default_frame_sniffer
d2427a71 1211};
c906108c 1212
fbe586ae 1213static CORE_ADDR
6834c9bb 1214alpha_heuristic_frame_base_address (struct frame_info *this_frame,
d2427a71 1215 void **this_prologue_cache)
c906108c 1216{
d2427a71 1217 struct alpha_heuristic_unwind_cache *info
6834c9bb 1218 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0);
c906108c 1219
d2427a71 1220 return info->vfp;
c906108c
SS
1221}
1222
d2427a71
RH
1223static const struct frame_base alpha_heuristic_frame_base = {
1224 &alpha_heuristic_frame_unwind,
1225 alpha_heuristic_frame_base_address,
1226 alpha_heuristic_frame_base_address,
1227 alpha_heuristic_frame_base_address
1228};
1229
c906108c 1230/* Just like reinit_frame_cache, but with the right arguments to be
d2427a71 1231 callable as an sfunc. Used by the "set heuristic-fence-post" command. */
c906108c
SS
1232
1233static void
fba45db2 1234reinit_frame_cache_sfunc (char *args, int from_tty, struct cmd_list_element *c)
c906108c
SS
1235{
1236 reinit_frame_cache ();
1237}
1238
d2427a71 1239\f
d2427a71
RH
1240/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1241 dummy frame. The frame ID's base needs to match the TOS value
1242 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1243 breakpoint. */
d734c450 1244
d2427a71 1245static struct frame_id
6834c9bb 1246alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
0d056799 1247{
d2427a71 1248 ULONGEST base;
6834c9bb
JB
1249 base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM);
1250 return frame_id_build (base, get_frame_pc (this_frame));
0d056799
JT
1251}
1252
dc129d82 1253static CORE_ADDR
d2427a71 1254alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
accc6d1f 1255{
d2427a71 1256 ULONGEST pc;
11411de3 1257 pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM);
d2427a71 1258 return pc;
accc6d1f
JT
1259}
1260
98a8e1e5
RH
1261\f
1262/* Helper routines for alpha*-nat.c files to move register sets to and
1263 from core files. The UNIQUE pointer is allowed to be NULL, as most
1264 targets don't supply this value in their core files. */
1265
1266void
390c1522
UW
1267alpha_supply_int_regs (struct regcache *regcache, int regno,
1268 const void *r0_r30, const void *pc, const void *unique)
98a8e1e5 1269{
2a1ce6ec 1270 const gdb_byte *regs = r0_r30;
98a8e1e5
RH
1271 int i;
1272
1273 for (i = 0; i < 31; ++i)
1274 if (regno == i || regno == -1)
390c1522 1275 regcache_raw_supply (regcache, i, regs + i * 8);
98a8e1e5
RH
1276
1277 if (regno == ALPHA_ZERO_REGNUM || regno == -1)
390c1522 1278 regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, NULL);
98a8e1e5
RH
1279
1280 if (regno == ALPHA_PC_REGNUM || regno == -1)
390c1522 1281 regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc);
98a8e1e5
RH
1282
1283 if (regno == ALPHA_UNIQUE_REGNUM || regno == -1)
390c1522 1284 regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique);
98a8e1e5
RH
1285}
1286
1287void
390c1522
UW
1288alpha_fill_int_regs (const struct regcache *regcache,
1289 int regno, void *r0_r30, void *pc, void *unique)
98a8e1e5 1290{
2a1ce6ec 1291 gdb_byte *regs = r0_r30;
98a8e1e5
RH
1292 int i;
1293
1294 for (i = 0; i < 31; ++i)
1295 if (regno == i || regno == -1)
390c1522 1296 regcache_raw_collect (regcache, i, regs + i * 8);
98a8e1e5
RH
1297
1298 if (regno == ALPHA_PC_REGNUM || regno == -1)
390c1522 1299 regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc);
98a8e1e5
RH
1300
1301 if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1))
390c1522 1302 regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique);
98a8e1e5
RH
1303}
1304
1305void
390c1522
UW
1306alpha_supply_fp_regs (struct regcache *regcache, int regno,
1307 const void *f0_f30, const void *fpcr)
98a8e1e5 1308{
2a1ce6ec 1309 const gdb_byte *regs = f0_f30;
98a8e1e5
RH
1310 int i;
1311
1312 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1313 if (regno == i || regno == -1)
390c1522 1314 regcache_raw_supply (regcache, i,
2a1ce6ec 1315 regs + (i - ALPHA_FP0_REGNUM) * 8);
98a8e1e5
RH
1316
1317 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
390c1522 1318 regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr);
98a8e1e5
RH
1319}
1320
1321void
390c1522
UW
1322alpha_fill_fp_regs (const struct regcache *regcache,
1323 int regno, void *f0_f30, void *fpcr)
98a8e1e5 1324{
2a1ce6ec 1325 gdb_byte *regs = f0_f30;
98a8e1e5
RH
1326 int i;
1327
1328 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i)
1329 if (regno == i || regno == -1)
390c1522 1330 regcache_raw_collect (regcache, i,
2a1ce6ec 1331 regs + (i - ALPHA_FP0_REGNUM) * 8);
98a8e1e5
RH
1332
1333 if (regno == ALPHA_FPCR_REGNUM || regno == -1)
390c1522 1334 regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr);
98a8e1e5
RH
1335}
1336
d2427a71 1337\f
0de94d4b
JB
1338
1339/* Return nonzero if the G_floating register value in REG is equal to
1340 zero for FP control instructions. */
1341
1342static int
1343fp_register_zero_p (LONGEST reg)
1344{
1345 /* Check that all bits except the sign bit are zero. */
1346 const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1;
1347
1348 return ((reg & zero_mask) == 0);
1349}
1350
1351/* Return the value of the sign bit for the G_floating register
1352 value held in REG. */
1353
1354static int
1355fp_register_sign_bit (LONGEST reg)
1356{
1357 const LONGEST sign_mask = (LONGEST) 1 << 63;
1358
1359 return ((reg & sign_mask) != 0);
1360}
1361
ec32e4be
JT
1362/* alpha_software_single_step() is called just before we want to resume
1363 the inferior, if we want to single-step it but there is no hardware
1364 or kernel single-step support (NetBSD on Alpha, for example). We find
e0cd558a 1365 the target of the coming instruction and breakpoint it. */
ec32e4be
JT
1366
1367static CORE_ADDR
0b1b3e42 1368alpha_next_pc (struct frame_info *frame, CORE_ADDR pc)
ec32e4be 1369{
e17a4113 1370 struct gdbarch *gdbarch = get_frame_arch (frame);
ec32e4be
JT
1371 unsigned int insn;
1372 unsigned int op;
551e4f2e 1373 int regno;
ec32e4be
JT
1374 int offset;
1375 LONGEST rav;
1376
e17a4113 1377 insn = alpha_read_insn (gdbarch, pc);
ec32e4be
JT
1378
1379 /* Opcode is top 6 bits. */
1380 op = (insn >> 26) & 0x3f;
1381
1382 if (op == 0x1a)
1383 {
1384 /* Jump format: target PC is:
1385 RB & ~3 */
0b1b3e42 1386 return (get_frame_register_unsigned (frame, (insn >> 16) & 0x1f) & ~3);
ec32e4be
JT
1387 }
1388
1389 if ((op & 0x30) == 0x30)
1390 {
1391 /* Branch format: target PC is:
1392 (new PC) + (4 * sext(displacement)) */
1393 if (op == 0x30 || /* BR */
1394 op == 0x34) /* BSR */
1395 {
1396 branch_taken:
1397 offset = (insn & 0x001fffff);
1398 if (offset & 0x00100000)
1399 offset |= 0xffe00000;
e8d2d628
MK
1400 offset *= ALPHA_INSN_SIZE;
1401 return (pc + ALPHA_INSN_SIZE + offset);
ec32e4be
JT
1402 }
1403
1404 /* Need to determine if branch is taken; read RA. */
551e4f2e
JB
1405 regno = (insn >> 21) & 0x1f;
1406 switch (op)
1407 {
1408 case 0x31: /* FBEQ */
1409 case 0x36: /* FBGE */
1410 case 0x37: /* FBGT */
1411 case 0x33: /* FBLE */
1412 case 0x32: /* FBLT */
1413 case 0x35: /* FBNE */
e17a4113 1414 regno += gdbarch_fp0_regnum (gdbarch);
551e4f2e
JB
1415 }
1416
0b1b3e42 1417 rav = get_frame_register_signed (frame, regno);
0de94d4b 1418
ec32e4be
JT
1419 switch (op)
1420 {
1421 case 0x38: /* BLBC */
1422 if ((rav & 1) == 0)
1423 goto branch_taken;
1424 break;
1425 case 0x3c: /* BLBS */
1426 if (rav & 1)
1427 goto branch_taken;
1428 break;
1429 case 0x39: /* BEQ */
1430 if (rav == 0)
1431 goto branch_taken;
1432 break;
1433 case 0x3d: /* BNE */
1434 if (rav != 0)
1435 goto branch_taken;
1436 break;
1437 case 0x3a: /* BLT */
1438 if (rav < 0)
1439 goto branch_taken;
1440 break;
1441 case 0x3b: /* BLE */
1442 if (rav <= 0)
1443 goto branch_taken;
1444 break;
1445 case 0x3f: /* BGT */
1446 if (rav > 0)
1447 goto branch_taken;
1448 break;
1449 case 0x3e: /* BGE */
1450 if (rav >= 0)
1451 goto branch_taken;
1452 break;
d2427a71 1453
0de94d4b
JB
1454 /* Floating point branches. */
1455
1456 case 0x31: /* FBEQ */
1457 if (fp_register_zero_p (rav))
1458 goto branch_taken;
1459 break;
1460 case 0x36: /* FBGE */
1461 if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav))
1462 goto branch_taken;
1463 break;
1464 case 0x37: /* FBGT */
1465 if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav))
1466 goto branch_taken;
1467 break;
1468 case 0x33: /* FBLE */
1469 if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav))
1470 goto branch_taken;
1471 break;
1472 case 0x32: /* FBLT */
1473 if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav))
1474 goto branch_taken;
1475 break;
1476 case 0x35: /* FBNE */
1477 if (! fp_register_zero_p (rav))
1478 goto branch_taken;
1479 break;
ec32e4be
JT
1480 }
1481 }
1482
1483 /* Not a branch or branch not taken; target PC is:
1484 pc + 4 */
e8d2d628 1485 return (pc + ALPHA_INSN_SIZE);
ec32e4be
JT
1486}
1487
e6590a1b 1488int
0b1b3e42 1489alpha_software_single_step (struct frame_info *frame)
ec32e4be 1490{
a6d9a66e 1491 struct gdbarch *gdbarch = get_frame_arch (frame);
e0cd558a 1492 CORE_ADDR pc, next_pc;
ec32e4be 1493
0b1b3e42
UW
1494 pc = get_frame_pc (frame);
1495 next_pc = alpha_next_pc (frame, pc);
ec32e4be 1496
a6d9a66e 1497 insert_single_step_breakpoint (gdbarch, next_pc);
e6590a1b 1498 return 1;
c906108c
SS
1499}
1500
dc129d82 1501\f
dc129d82
JT
1502/* Initialize the current architecture based on INFO. If possible, re-use an
1503 architecture from ARCHES, which is a list of architectures already created
1504 during this debugging session.
1505
1506 Called e.g. at program startup, when reading a core file, and when reading
1507 a binary file. */
1508
1509static struct gdbarch *
1510alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1511{
1512 struct gdbarch_tdep *tdep;
1513 struct gdbarch *gdbarch;
dc129d82
JT
1514
1515 /* Try to determine the ABI of the object we are loading. */
4be87837 1516 if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
dc129d82 1517 {
4be87837
DJ
1518 /* If it's an ECOFF file, assume it's OSF/1. */
1519 if (bfd_get_flavour (info.abfd) == bfd_target_ecoff_flavour)
aff87235 1520 info.osabi = GDB_OSABI_OSF1;
dc129d82
JT
1521 }
1522
1523 /* Find a candidate among extant architectures. */
4be87837
DJ
1524 arches = gdbarch_list_lookup_by_info (arches, &info);
1525 if (arches != NULL)
1526 return arches->gdbarch;
dc129d82
JT
1527
1528 tdep = xmalloc (sizeof (struct gdbarch_tdep));
1529 gdbarch = gdbarch_alloc (&info, tdep);
1530
d2427a71
RH
1531 /* Lowest text address. This is used by heuristic_proc_start()
1532 to decide when to stop looking. */
594706e6 1533 tdep->vm_min_address = (CORE_ADDR) 0x120000000LL;
d9b023cc 1534
36a6271d 1535 tdep->dynamic_sigtramp_offset = NULL;
5868c862 1536 tdep->sigcontext_addr = NULL;
138e7be5
MK
1537 tdep->sc_pc_offset = 2 * 8;
1538 tdep->sc_regs_offset = 4 * 8;
1539 tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8;
36a6271d 1540
accc6d1f
JT
1541 tdep->jb_pc = -1; /* longjmp support not enabled by default */
1542
9823e921
RH
1543 tdep->return_in_memory = alpha_return_in_memory_always;
1544
dc129d82
JT
1545 /* Type sizes */
1546 set_gdbarch_short_bit (gdbarch, 16);
1547 set_gdbarch_int_bit (gdbarch, 32);
1548 set_gdbarch_long_bit (gdbarch, 64);
1549 set_gdbarch_long_long_bit (gdbarch, 64);
1550 set_gdbarch_float_bit (gdbarch, 32);
1551 set_gdbarch_double_bit (gdbarch, 64);
1552 set_gdbarch_long_double_bit (gdbarch, 64);
1553 set_gdbarch_ptr_bit (gdbarch, 64);
1554
1555 /* Register info */
1556 set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS);
1557 set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM);
dc129d82
JT
1558 set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM);
1559 set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM);
1560
1561 set_gdbarch_register_name (gdbarch, alpha_register_name);
c483c494 1562 set_gdbarch_register_type (gdbarch, alpha_register_type);
dc129d82
JT
1563
1564 set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register);
1565 set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register);
1566
c483c494
RH
1567 set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p);
1568 set_gdbarch_register_to_value (gdbarch, alpha_register_to_value);
1569 set_gdbarch_value_to_register (gdbarch, alpha_value_to_register);
dc129d82 1570
615967cb
RH
1571 set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p);
1572
d2427a71 1573 /* Prologue heuristics. */
dc129d82
JT
1574 set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue);
1575
5ef165c2
RH
1576 /* Disassembler. */
1577 set_gdbarch_print_insn (gdbarch, print_insn_alpha);
1578
d2427a71 1579 /* Call info. */
dc129d82 1580
9823e921 1581 set_gdbarch_return_value (gdbarch, alpha_return_value);
dc129d82
JT
1582
1583 /* Settings for calling functions in the inferior. */
c88e30c0 1584 set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call);
d2427a71
RH
1585
1586 /* Methods for saving / extracting a dummy frame's ID. */
6834c9bb 1587 set_gdbarch_dummy_id (gdbarch, alpha_dummy_id);
d2427a71
RH
1588
1589 /* Return the unwound PC value. */
1590 set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc);
dc129d82
JT
1591
1592 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
36a6271d 1593 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
dc129d82 1594
95b80706 1595 set_gdbarch_breakpoint_from_pc (gdbarch, alpha_breakpoint_from_pc);
e8d2d628 1596 set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE);
9d519230 1597 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
95b80706 1598
44dffaac 1599 /* Hook in ABI-specific overrides, if they have been registered. */
4be87837 1600 gdbarch_init_osabi (info, gdbarch);
44dffaac 1601
accc6d1f
JT
1602 /* Now that we have tuned the configuration, set a few final things
1603 based on what the OS ABI has told us. */
1604
1605 if (tdep->jb_pc >= 0)
1606 set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target);
1607
6834c9bb
JB
1608 frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind);
1609 frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind);
dc129d82 1610
d2427a71 1611 frame_base_set_default (gdbarch, &alpha_heuristic_frame_base);
accc6d1f 1612
d2427a71 1613 return gdbarch;
dc129d82
JT
1614}
1615
baa490c4
RH
1616void
1617alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1618{
6834c9bb 1619 dwarf2_append_unwinders (gdbarch);
336d1bba 1620 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
baa490c4
RH
1621}
1622
a78f21af
AC
1623extern initialize_file_ftype _initialize_alpha_tdep; /* -Wmissing-prototypes */
1624
c906108c 1625void
fba45db2 1626_initialize_alpha_tdep (void)
c906108c
SS
1627{
1628 struct cmd_list_element *c;
1629
d2427a71 1630 gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL);
c906108c
SS
1631
1632 /* Let the user set the fence post for heuristic_proc_start. */
1633
1634 /* We really would like to have both "0" and "unlimited" work, but
1635 command.c doesn't deal with that. So make it a var_zinteger
1636 because the user can always use "999999" or some such for unlimited. */
edefbb7c
AC
1637 /* We need to throw away the frame cache when we set this, since it
1638 might change our ability to get backtraces. */
1639 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
7915a72c
AC
1640 &heuristic_fence_post, _("\
1641Set the distance searched for the start of a function."), _("\
1642Show the distance searched for the start of a function."), _("\
c906108c
SS
1643If you are debugging a stripped executable, GDB needs to search through the\n\
1644program for the start of a function. This command sets the distance of the\n\
323e0a4a 1645search. The only need to set it is when debugging a stripped executable."),
2c5b56ce 1646 reinit_frame_cache_sfunc,
7915a72c 1647 NULL, /* FIXME: i18n: The distance searched for the start of a function is \"%d\". */
edefbb7c 1648 &setlist, &showlist);
c906108c 1649}