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129ba616 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. |
129ba616 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
129ba616 KG |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8572ds board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
509c4c4c KG |
14 | #include "../board/freescale/common/ics307_clk.h" |
15 | ||
cb14e93b | 16 | #ifndef CONFIG_SYS_TEXT_BASE |
18025756 | 17 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
cb14e93b KG |
18 | #endif |
19 | ||
7a577fda KG |
20 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
21 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
22 | #endif | |
23 | ||
cb14e93b KG |
24 | #ifndef CONFIG_SYS_MONITOR_BASE |
25 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
26 | #endif | |
27 | ||
129ba616 KG |
28 | /* High Level Configuration Options */ |
29 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
30 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
129ba616 KG |
31 | #define CONFIG_MPC8572 1 |
32 | #define CONFIG_MPC8572DS 1 | |
33 | #define CONFIG_MP 1 /* support multiple processors */ | |
129ba616 | 34 | |
c51fc5d5 | 35 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
b38eaec5 RD |
36 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ |
37 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ | |
38 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ | |
129ba616 | 39 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
842033e6 | 40 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
129ba616 | 41 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 42 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
129ba616 KG |
43 | |
44 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
45 | ||
46 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
47 | #define CONFIG_ENV_OVERWRITE | |
48 | ||
509c4c4c KG |
49 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
50 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ | |
4ca06607 | 51 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
129ba616 KG |
52 | |
53 | /* | |
54 | * These can be toggled for performance analysis, otherwise use default. | |
55 | */ | |
56 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
57 | #define CONFIG_BTB /* toggle branch predition */ | |
129ba616 KG |
58 | |
59 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
60 | ||
18af1c5f KG |
61 | #ifdef CONFIG_PHYS_64BIT |
62 | #define CONFIG_ADDR_MAP 1 | |
63 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
64 | #endif | |
65 | ||
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
67 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
129ba616 KG |
68 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
69 | ||
cb14e93b KG |
70 | /* |
71 | * Config the L2 Cache as L2 SRAM | |
72 | */ | |
73 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
74 | #ifdef CONFIG_PHYS_64BIT | |
75 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
76 | #else | |
77 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
78 | #endif | |
79 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
80 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
81 | ||
e46fedfe TT |
82 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
83 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
129ba616 | 84 | |
8d22ddca | 85 | #if defined(CONFIG_NAND_SPL) |
e46fedfe | 86 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
cb14e93b KG |
87 | #endif |
88 | ||
129ba616 | 89 | /* DDR Setup */ |
f8523cb0 | 90 | #define CONFIG_VERY_BIG_RAM |
5614e71b | 91 | #define CONFIG_SYS_FSL_DDR2 |
129ba616 KG |
92 | #undef CONFIG_FSL_DDR_INTERACTIVE |
93 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
94 | #define CONFIG_DDR_SPD | |
129ba616 | 95 | |
d34897d3 | 96 | #define CONFIG_DDR_ECC |
9b0ad1b1 | 97 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
129ba616 KG |
98 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
99 | ||
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
101 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
129ba616 KG |
102 | |
103 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
104 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
105 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
106 | ||
107 | /* I2C addresses of SPD EEPROMs */ | |
6d0f6bcf | 108 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
129ba616 KG |
109 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
110 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ | |
111 | ||
112 | /* These are used when DDR doesn't use SPD. */ | |
dc889e86 DL |
113 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
114 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F | |
115 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
116 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
117 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
118 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 | |
119 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf | |
120 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 | |
6d0f6bcf | 121 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
dc889e86 | 122 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
6d0f6bcf | 123 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
dc889e86 DL |
124 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
125 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
6d0f6bcf | 126 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
dc889e86 DL |
127 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
128 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
6d0f6bcf JCPV |
129 | |
130 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
131 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
132 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
129ba616 | 133 | |
129ba616 KG |
134 | /* |
135 | * Make sure required options are set | |
136 | */ | |
137 | #ifndef CONFIG_SPD_EEPROM | |
138 | #error ("CONFIG_SPD_EEPROM is required") | |
139 | #endif | |
140 | ||
141 | #undef CONFIG_CLOCKS_IN_MHZ | |
142 | ||
143 | /* | |
144 | * Memory map | |
145 | * | |
146 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
147 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
148 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
149 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
150 | * | |
151 | * Localbus cacheable (TBD) | |
152 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
153 | * | |
154 | * Localbus non-cacheable | |
155 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
156 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
3cbd8231 | 157 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
129ba616 KG |
158 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
159 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
160 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
161 | */ | |
162 | ||
163 | /* | |
164 | * Local Bus Definitions | |
165 | */ | |
6d0f6bcf | 166 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
18af1c5f KG |
167 | #ifdef CONFIG_PHYS_64BIT |
168 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
169 | #else | |
c953ddfd | 170 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
18af1c5f | 171 | #endif |
129ba616 | 172 | |
cb14e93b | 173 | #define CONFIG_FLASH_BR_PRELIM \ |
7ee41107 | 174 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
cb14e93b | 175 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
129ba616 | 176 | |
c953ddfd KG |
177 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
178 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
129ba616 | 179 | |
18af1c5f | 180 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
6d0f6bcf | 181 | #define CONFIG_SYS_FLASH_QUIET_TEST |
129ba616 KG |
182 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
183 | ||
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
185 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
186 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
187 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
188 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
129ba616 | 189 | |
cb14e93b | 190 | #undef CONFIG_SYS_RAMBOOT |
129ba616 KG |
191 | |
192 | #define CONFIG_FLASH_CFI_DRIVER | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_FLASH_CFI |
194 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
195 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
129ba616 KG |
196 | |
197 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
198 | ||
558710b9 | 199 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
129ba616 KG |
200 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
201 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
18af1c5f KG |
202 | #ifdef CONFIG_PHYS_64BIT |
203 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
204 | #else | |
52b565f5 | 205 | #define PIXIS_BASE_PHYS PIXIS_BASE |
18af1c5f | 206 | #endif |
129ba616 | 207 | |
52b565f5 | 208 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
6d0f6bcf | 209 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
129ba616 KG |
210 | |
211 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
212 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
213 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
214 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
215 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
216 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
217 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
218 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
219 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
220 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
221 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
222 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
223 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
224 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
225 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
6bb5b412 KG |
226 | #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ |
227 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
228 | #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ | |
229 | #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ | |
230 | #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ | |
129ba616 KG |
231 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
232 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
233 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
234 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ | |
235 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ | |
236 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ | |
237 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ | |
238 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ | |
239 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ | |
240 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
241 | #define PIXIS_LED 0x25 /* LED Register */ | |
242 | ||
cb14e93b KG |
243 | #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ |
244 | ||
129ba616 KG |
245 | /* old pixis referenced names */ |
246 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
247 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 248 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
7e183cad LY |
249 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
250 | #define PIXIS_VSPEED2_TSEC2SER 0x4 | |
251 | #define PIXIS_VSPEED2_TSEC3SER 0x2 | |
252 | #define PIXIS_VSPEED2_TSEC4SER 0x1 | |
253 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
254 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 | |
255 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 | |
256 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 | |
257 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ | |
258 | | PIXIS_VSPEED2_TSEC2SER \ | |
259 | | PIXIS_VSPEED2_TSEC3SER \ | |
260 | | PIXIS_VSPEED2_TSEC4SER) | |
261 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ | |
262 | | PIXIS_VCFGEN1_TSEC2SER \ | |
263 | | PIXIS_VCFGEN1_TSEC3SER \ | |
264 | | PIXIS_VCFGEN1_TSEC4SER) | |
129ba616 | 265 | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
267 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
553f0982 | 268 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
129ba616 | 269 | |
25ddd1fb | 270 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 271 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
129ba616 | 272 | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
274 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
129ba616 | 275 | |
cb14e93b | 276 | #ifndef CONFIG_NAND_SPL |
c013b749 | 277 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
18af1c5f KG |
278 | #ifdef CONFIG_PHYS_64BIT |
279 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
280 | #else | |
c013b749 | 281 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
18af1c5f | 282 | #endif |
cb14e93b KG |
283 | #else |
284 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
285 | #ifdef CONFIG_PHYS_64BIT | |
286 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
287 | #else | |
288 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
289 | #endif | |
290 | #endif | |
291 | ||
c013b749 HW |
292 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
293 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
294 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
295 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
296 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
3cbd8231 WD |
297 | #define CONFIG_CMD_NAND 1 |
298 | #define CONFIG_NAND_FSL_ELBC 1 | |
c013b749 | 299 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
68ec9c85 PK |
300 | #define CONFIG_SYS_NAND_MAX_OOBFREE 5 |
301 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 | |
c013b749 | 302 | |
cb14e93b KG |
303 | /* NAND boot: 4K NAND loader config */ |
304 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
305 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
306 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
307 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
308 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
309 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
310 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
311 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
312 | ||
c013b749 | 313 | /* NAND flash config */ |
a3055c58 | 314 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
3cbd8231 WD |
315 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
316 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
317 | | BR_MS_FCM /* MSEL = FCM */ \ | |
318 | | BR_V) /* valid */ | |
a3055c58 | 319 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
3cbd8231 WD |
320 | | OR_FCM_PGS /* Large Page*/ \ |
321 | | OR_FCM_CSCT \ | |
322 | | OR_FCM_CST \ | |
323 | | OR_FCM_CHT \ | |
324 | | OR_FCM_SCY_1 \ | |
325 | | OR_FCM_TRLX \ | |
326 | | OR_FCM_EHTR) | |
c013b749 | 327 | |
cb14e93b KG |
328 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
329 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
330 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
331 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
7ee41107 | 332 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
3cbd8231 WD |
333 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
334 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
335 | | BR_MS_FCM /* MSEL = FCM */ \ | |
336 | | BR_V) /* valid */ | |
a3055c58 | 337 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
7ee41107 | 338 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ |
3cbd8231 WD |
339 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
340 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
341 | | BR_MS_FCM /* MSEL = FCM */ \ | |
342 | | BR_V) /* valid */ | |
a3055c58 | 343 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
c013b749 | 344 | |
7ee41107 | 345 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ |
3cbd8231 WD |
346 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
347 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
348 | | BR_MS_FCM /* MSEL = FCM */ \ | |
349 | | BR_V) /* valid */ | |
a3055c58 | 350 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
c013b749 | 351 | |
129ba616 KG |
352 | /* Serial Port - controlled on board with jumper J8 |
353 | * open - index 2 | |
354 | * shorted - index 1 | |
355 | */ | |
356 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_NS16550_SERIAL |
358 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
359 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
cb14e93b KG |
360 | #ifdef CONFIG_NAND_SPL |
361 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
362 | #endif | |
129ba616 | 363 | |
6d0f6bcf | 364 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
129ba616 KG |
365 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
366 | ||
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
368 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
129ba616 | 369 | |
129ba616 | 370 | /* I2C */ |
00f792e0 HS |
371 | #define CONFIG_SYS_I2C |
372 | #define CONFIG_SYS_I2C_FSL | |
373 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
374 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
375 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
376 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
377 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
378 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
379 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
6d0f6bcf | 380 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
129ba616 | 381 | |
445a7b38 HW |
382 | /* |
383 | * I2C2 EEPROM | |
384 | */ | |
385 | #define CONFIG_ID_EEPROM | |
386 | #ifdef CONFIG_ID_EEPROM | |
6d0f6bcf | 387 | #define CONFIG_SYS_I2C_EEPROM_NXID |
445a7b38 | 388 | #endif |
6d0f6bcf JCPV |
389 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
390 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
391 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
445a7b38 | 392 | |
129ba616 KG |
393 | /* |
394 | * General PCI | |
395 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
396 | */ | |
397 | ||
129ba616 | 398 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
18ea5551 | 399 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
5af0fdd8 | 400 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
18af1c5f | 401 | #ifdef CONFIG_PHYS_64BIT |
156984a3 | 402 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
18af1c5f KG |
403 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
404 | #else | |
ad97dce1 | 405 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
5af0fdd8 | 406 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
18af1c5f | 407 | #endif |
6d0f6bcf | 408 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 409 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
5f91ef6a | 410 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
18af1c5f KG |
411 | #ifdef CONFIG_PHYS_64BIT |
412 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
413 | #else | |
6d0f6bcf | 414 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
18af1c5f | 415 | #endif |
6d0f6bcf | 416 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
129ba616 KG |
417 | |
418 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
18ea5551 | 419 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
5af0fdd8 | 420 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
18af1c5f | 421 | #ifdef CONFIG_PHYS_64BIT |
156984a3 | 422 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
18af1c5f KG |
423 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
424 | #else | |
ad97dce1 | 425 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
5af0fdd8 | 426 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
18af1c5f | 427 | #endif |
6d0f6bcf | 428 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 429 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
5f91ef6a | 430 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
18af1c5f KG |
431 | #ifdef CONFIG_PHYS_64BIT |
432 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
433 | #else | |
6d0f6bcf | 434 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
18af1c5f | 435 | #endif |
6d0f6bcf | 436 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
129ba616 KG |
437 | |
438 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
18ea5551 | 439 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
5af0fdd8 | 440 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
18af1c5f | 441 | #ifdef CONFIG_PHYS_64BIT |
156984a3 | 442 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
18af1c5f KG |
443 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
444 | #else | |
ad97dce1 | 445 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
5af0fdd8 | 446 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
18af1c5f | 447 | #endif |
6d0f6bcf | 448 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 449 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
5f91ef6a | 450 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
18af1c5f KG |
451 | #ifdef CONFIG_PHYS_64BIT |
452 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
453 | #else | |
6d0f6bcf | 454 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
18af1c5f | 455 | #endif |
6d0f6bcf | 456 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
129ba616 KG |
457 | |
458 | #if defined(CONFIG_PCI) | |
459 | ||
460 | /*PCIE video card used*/ | |
aca5f018 | 461 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
129ba616 KG |
462 | |
463 | /* video */ | |
129ba616 KG |
464 | |
465 | #if defined(CONFIG_VIDEO) | |
466 | #define CONFIG_BIOSEMU | |
129ba616 KG |
467 | #define CONFIG_ATI_RADEON_FB |
468 | #define CONFIG_VIDEO_LOGO | |
6d0f6bcf | 469 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
129ba616 KG |
470 | #endif |
471 | ||
129ba616 KG |
472 | #undef CONFIG_EEPRO100 |
473 | #undef CONFIG_TULIP | |
129ba616 | 474 | |
129ba616 | 475 | #ifndef CONFIG_PCI_PNP |
5f91ef6a KG |
476 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
477 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
129ba616 KG |
478 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
479 | #endif | |
480 | ||
481 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
482 | #define CONFIG_DOS_PARTITION | |
483 | #define CONFIG_SCSI_AHCI | |
484 | ||
485 | #ifdef CONFIG_SCSI_AHCI | |
344ca0b4 | 486 | #define CONFIG_LIBATA |
129ba616 | 487 | #define CONFIG_SATA_ULI5288 |
6d0f6bcf JCPV |
488 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
489 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
490 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
491 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
129ba616 KG |
492 | #endif /* SCSI */ |
493 | ||
494 | #endif /* CONFIG_PCI */ | |
495 | ||
129ba616 KG |
496 | #if defined(CONFIG_TSEC_ENET) |
497 | ||
129ba616 KG |
498 | #define CONFIG_MII 1 /* MII PHY management */ |
499 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
500 | #define CONFIG_TSEC1 1 | |
501 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
502 | #define CONFIG_TSEC2 1 | |
503 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
504 | #define CONFIG_TSEC3 1 | |
505 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
506 | #define CONFIG_TSEC4 1 | |
507 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
508 | ||
7e183cad LY |
509 | #define CONFIG_PIXIS_SGMII_CMD |
510 | #define CONFIG_FSL_SGMII_RISER 1 | |
511 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
512 | ||
513 | #ifdef CONFIG_FSL_SGMII_RISER | |
514 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
515 | #endif | |
516 | ||
129ba616 KG |
517 | #define TSEC1_PHY_ADDR 0 |
518 | #define TSEC2_PHY_ADDR 1 | |
519 | #define TSEC3_PHY_ADDR 2 | |
520 | #define TSEC4_PHY_ADDR 3 | |
521 | ||
522 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
523 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
524 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
525 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
526 | ||
527 | #define TSEC1_PHYIDX 0 | |
528 | #define TSEC2_PHYIDX 0 | |
529 | #define TSEC3_PHYIDX 0 | |
530 | #define TSEC4_PHYIDX 0 | |
531 | ||
532 | #define CONFIG_ETHPRIME "eTSEC1" | |
533 | ||
534 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
535 | #endif /* CONFIG_TSEC_ENET */ | |
536 | ||
537 | /* | |
538 | * Environment | |
539 | */ | |
cb14e93b KG |
540 | |
541 | #if defined(CONFIG_SYS_RAMBOOT) | |
cb14e93b | 542 | |
129ba616 | 543 | #else |
cb14e93b KG |
544 | #define CONFIG_ENV_IS_IN_FLASH 1 |
545 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
546 | #define CONFIG_ENV_ADDR 0xfff80000 | |
547 | #else | |
548 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
549 | #endif | |
550 | #define CONFIG_ENV_SIZE 0x2000 | |
551 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
129ba616 | 552 | #endif |
129ba616 KG |
553 | |
554 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 555 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
129ba616 KG |
556 | |
557 | /* | |
558 | * Command line configuration. | |
559 | */ | |
67f94476 | 560 | #define CONFIG_CMD_ERRATA |
129ba616 | 561 | #define CONFIG_CMD_IRQ |
199e262e | 562 | #define CONFIG_CMD_REGINFO |
129ba616 KG |
563 | |
564 | #if defined(CONFIG_PCI) | |
565 | #define CONFIG_CMD_PCI | |
c649e3c9 | 566 | #define CONFIG_SCSI |
129ba616 KG |
567 | #endif |
568 | ||
863a3eac ZC |
569 | /* |
570 | * USB | |
571 | */ | |
572 | #define CONFIG_USB_EHCI | |
573 | ||
574 | #ifdef CONFIG_USB_EHCI | |
863a3eac ZC |
575 | #define CONFIG_USB_EHCI_PCI |
576 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
863a3eac ZC |
577 | #define CONFIG_PCI_EHCI_DEVICE 0 |
578 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 | |
579 | #endif | |
580 | ||
129ba616 KG |
581 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
582 | ||
583 | /* | |
584 | * Miscellaneous configurable options | |
585 | */ | |
6d0f6bcf | 586 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
587 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
588 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 589 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
129ba616 | 590 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 591 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
129ba616 | 592 | #else |
6d0f6bcf | 593 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
129ba616 | 594 | #endif |
6d0f6bcf JCPV |
595 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
596 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
597 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
129ba616 KG |
598 | |
599 | /* | |
600 | * For booting Linux, the board info and command line data | |
a832ac41 | 601 | * have to be in the first 64 MB of memory, since this is |
129ba616 KG |
602 | * the maximum mapped by the Linux kernel during initialization. |
603 | */ | |
a832ac41 KG |
604 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
605 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
129ba616 | 606 | |
129ba616 KG |
607 | #if defined(CONFIG_CMD_KGDB) |
608 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
129ba616 KG |
609 | #endif |
610 | ||
611 | /* | |
612 | * Environment Configuration | |
613 | */ | |
129ba616 KG |
614 | #if defined(CONFIG_TSEC_ENET) |
615 | #define CONFIG_HAS_ETH0 | |
129ba616 | 616 | #define CONFIG_HAS_ETH1 |
129ba616 | 617 | #define CONFIG_HAS_ETH2 |
129ba616 | 618 | #define CONFIG_HAS_ETH3 |
129ba616 KG |
619 | #endif |
620 | ||
621 | #define CONFIG_IPADDR 192.168.1.254 | |
622 | ||
623 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 624 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 625 | #define CONFIG_BOOTFILE "uImage" |
129ba616 KG |
626 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
627 | ||
628 | #define CONFIG_SERVERIP 192.168.1.1 | |
629 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
630 | #define CONFIG_NETMASK 255.255.255.0 | |
631 | ||
632 | /* default location for tftp and bootm */ | |
633 | #define CONFIG_LOADADDR 1000000 | |
634 | ||
129ba616 KG |
635 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
636 | ||
637 | #define CONFIG_BAUDRATE 115200 | |
638 | ||
639 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
238e1467 | 640 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ |
5368c55d MV |
641 | "netdev=eth0\0" \ |
642 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
643 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
644 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
645 | " +$filesize; " \ | |
646 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
647 | " +$filesize; " \ | |
648 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
649 | " $filesize; " \ | |
650 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
651 | " +$filesize; " \ | |
652 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
653 | " $filesize\0" \ | |
654 | "consoledev=ttyS0\0" \ | |
655 | "ramdiskaddr=2000000\0" \ | |
656 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ | |
b24a4f62 | 657 | "fdtaddr=1e00000\0" \ |
5368c55d MV |
658 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ |
659 | "bdev=sda3\0" | |
129ba616 KG |
660 | |
661 | #define CONFIG_HDBOOT \ | |
662 | "setenv bootargs root=/dev/$bdev rw " \ | |
663 | "console=$consoledev,$baudrate $othbootargs;" \ | |
664 | "tftp $loadaddr $bootfile;" \ | |
665 | "tftp $fdtaddr $fdtfile;" \ | |
666 | "bootm $loadaddr - $fdtaddr" | |
667 | ||
668 | #define CONFIG_NFSBOOTCOMMAND \ | |
669 | "setenv bootargs root=/dev/nfs rw " \ | |
670 | "nfsroot=$serverip:$rootpath " \ | |
671 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
672 | "console=$consoledev,$baudrate $othbootargs;" \ | |
673 | "tftp $loadaddr $bootfile;" \ | |
674 | "tftp $fdtaddr $fdtfile;" \ | |
675 | "bootm $loadaddr - $fdtaddr" | |
676 | ||
677 | #define CONFIG_RAMBOOTCOMMAND \ | |
678 | "setenv bootargs root=/dev/ram rw " \ | |
679 | "console=$consoledev,$baudrate $othbootargs;" \ | |
680 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
681 | "tftp $loadaddr $bootfile;" \ | |
682 | "tftp $fdtaddr $fdtfile;" \ | |
683 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
684 | ||
685 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
686 | ||
687 | #endif /* __CONFIG_H */ |