projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 129ba616 | 1 | /* |
| 7c57f3e8 | 2 | * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. |
| 129ba616 | 3 | * |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 129ba616 KG |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * mpc8572ds board configuration file | |
| 9 | * | |
| 10 | */ | |
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 509c4c4c KG |
14 | #include "../board/freescale/common/ics307_clk.h" |
| 15 | ||
| d24f2d32 | 16 | #ifdef CONFIG_36BIT |
| f9edcc10 KG |
17 | #define CONFIG_PHYS_64BIT |
| 18 | #endif | |
| 19 | ||
| cb14e93b KG |
20 | #ifdef CONFIG_NAND |
| 21 | #define CONFIG_NAND_U_BOOT | |
| 22 | #define CONFIG_RAMBOOT_NAND | |
| 23 | #ifdef CONFIG_NAND_SPL | |
| 24 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 | |
| 25 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ | |
| 26 | #else | |
| 00203c64 | 27 | #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds |
| cb14e93b KG |
28 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 |
| 29 | #endif /* CONFIG_NAND_SPL */ | |
| 30 | #endif | |
| 31 | ||
| 32 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 33 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
| 34 | #endif | |
| 35 | ||
| 7a577fda KG |
36 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 37 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 38 | #endif | |
| 39 | ||
| cb14e93b KG |
40 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 41 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 42 | #endif | |
| 43 | ||
| 129ba616 KG |
44 | /* High Level Configuration Options */ |
| 45 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 46 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 47 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 48 | #define CONFIG_MPC8572 1 | |
| 49 | #define CONFIG_MPC8572DS 1 | |
| 50 | #define CONFIG_MP 1 /* support multiple processors */ | |
| 129ba616 | 51 | |
| c51fc5d5 | 52 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| 129ba616 KG |
53 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 54 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
| 55 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 56 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
| 57 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 842033e6 | 58 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
| 129ba616 | 59 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 0151cbac | 60 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 129ba616 KG |
61 | |
| 62 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
| 63 | ||
| 64 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 65 | #define CONFIG_ENV_OVERWRITE | |
| 66 | ||
| 509c4c4c KG |
67 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| 68 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ | |
| 4ca06607 | 69 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| 129ba616 KG |
70 | |
| 71 | /* | |
| 72 | * These can be toggled for performance analysis, otherwise use default. | |
| 73 | */ | |
| 74 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 75 | #define CONFIG_BTB /* toggle branch predition */ | |
| 129ba616 KG |
76 | |
| 77 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 78 | ||
| 18af1c5f KG |
79 | #ifdef CONFIG_PHYS_64BIT |
| 80 | #define CONFIG_ADDR_MAP 1 | |
| 81 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 82 | #endif | |
| 83 | ||
| 6d0f6bcf JCPV |
84 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 85 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
| 129ba616 KG |
86 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 87 | ||
| cb14e93b KG |
88 | /* |
| 89 | * Config the L2 Cache as L2 SRAM | |
| 90 | */ | |
| 91 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 92 | #ifdef CONFIG_PHYS_64BIT | |
| 93 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
| 94 | #else | |
| 95 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 96 | #endif | |
| 97 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
| 98 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 99 | ||
| e46fedfe TT |
100 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 101 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 129ba616 | 102 | |
| 8d22ddca | 103 | #if defined(CONFIG_NAND_SPL) |
| e46fedfe | 104 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| cb14e93b KG |
105 | #endif |
| 106 | ||
| 129ba616 | 107 | /* DDR Setup */ |
| f8523cb0 | 108 | #define CONFIG_VERY_BIG_RAM |
| 129ba616 KG |
109 | #define CONFIG_FSL_DDR2 |
| 110 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 111 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 112 | #define CONFIG_DDR_SPD | |
| 129ba616 | 113 | |
| d34897d3 | 114 | #define CONFIG_DDR_ECC |
| 9b0ad1b1 | 115 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 129ba616 KG |
116 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 117 | ||
| 6d0f6bcf JCPV |
118 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 119 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 129ba616 KG |
120 | |
| 121 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 122 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 123 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 124 | ||
| 125 | /* I2C addresses of SPD EEPROMs */ | |
| 6d0f6bcf | 126 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
| 129ba616 KG |
127 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
| 128 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ | |
| 129 | ||
| 130 | /* These are used when DDR doesn't use SPD. */ | |
| dc889e86 DL |
131 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
| 132 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F | |
| 133 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
| 134 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
| 135 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 136 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 | |
| 137 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf | |
| 138 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 | |
| 6d0f6bcf | 139 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| dc889e86 | 140 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
| 6d0f6bcf | 141 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| dc889e86 DL |
142 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
| 143 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 6d0f6bcf | 144 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| dc889e86 DL |
145 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
| 146 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
| 6d0f6bcf JCPV |
147 | |
| 148 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 149 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 150 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
| 129ba616 | 151 | |
| 129ba616 KG |
152 | /* |
| 153 | * Make sure required options are set | |
| 154 | */ | |
| 155 | #ifndef CONFIG_SPD_EEPROM | |
| 156 | #error ("CONFIG_SPD_EEPROM is required") | |
| 157 | #endif | |
| 158 | ||
| 159 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 160 | ||
| 161 | /* | |
| 162 | * Memory map | |
| 163 | * | |
| 164 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 165 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
| 166 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
| 167 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
| 168 | * | |
| 169 | * Localbus cacheable (TBD) | |
| 170 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 171 | * | |
| 172 | * Localbus non-cacheable | |
| 173 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
| 174 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
| 3cbd8231 | 175 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| 129ba616 KG |
176 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 177 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 178 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 179 | */ | |
| 180 | ||
| 181 | /* | |
| 182 | * Local Bus Definitions | |
| 183 | */ | |
| 6d0f6bcf | 184 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| 18af1c5f KG |
185 | #ifdef CONFIG_PHYS_64BIT |
| 186 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
| 187 | #else | |
| c953ddfd | 188 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 18af1c5f | 189 | #endif |
| 129ba616 | 190 | |
| cb14e93b KG |
191 | |
| 192 | #define CONFIG_FLASH_BR_PRELIM \ | |
| 7ee41107 | 193 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
| cb14e93b | 194 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
| 129ba616 | 195 | |
| c953ddfd KG |
196 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| 197 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
| 129ba616 | 198 | |
| 18af1c5f | 199 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| 6d0f6bcf | 200 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 129ba616 KG |
201 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 202 | ||
| 6d0f6bcf JCPV |
203 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 204 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 205 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 206 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 207 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 129ba616 | 208 | |
| cb14e93b KG |
209 | #if defined(CONFIG_RAMBOOT_NAND) |
| 210 | #define CONFIG_SYS_RAMBOOT | |
| 211 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 212 | #else | |
| 213 | #undef CONFIG_SYS_RAMBOOT | |
| 214 | #endif | |
| 129ba616 KG |
215 | |
| 216 | #define CONFIG_FLASH_CFI_DRIVER | |
| 6d0f6bcf JCPV |
217 | #define CONFIG_SYS_FLASH_CFI |
| 218 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 219 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 129ba616 KG |
220 | |
| 221 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 222 | ||
| 558710b9 | 223 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
| 129ba616 KG |
224 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| 225 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
| 18af1c5f KG |
226 | #ifdef CONFIG_PHYS_64BIT |
| 227 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
| 228 | #else | |
| 52b565f5 | 229 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| 18af1c5f | 230 | #endif |
| 129ba616 | 231 | |
| 52b565f5 | 232 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| 6d0f6bcf | 233 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| 129ba616 KG |
234 | |
| 235 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
| 236 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 237 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 238 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
| 239 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 240 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
| 241 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
| 242 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 243 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
| 244 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 245 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
| 246 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 247 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 248 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
| 249 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 6bb5b412 KG |
250 | #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ |
| 251 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
| 252 | #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ | |
| 253 | #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ | |
| 254 | #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ | |
| 129ba616 KG |
255 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 256 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 257 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
| 258 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ | |
| 259 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ | |
| 260 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ | |
| 261 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ | |
| 262 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ | |
| 263 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ | |
| 264 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
| 265 | #define PIXIS_LED 0x25 /* LED Register */ | |
| 266 | ||
| cb14e93b KG |
267 | #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ |
| 268 | ||
| 129ba616 KG |
269 | /* old pixis referenced names */ |
| 270 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 271 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 272 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
| 7e183cad LY |
273 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
| 274 | #define PIXIS_VSPEED2_TSEC2SER 0x4 | |
| 275 | #define PIXIS_VSPEED2_TSEC3SER 0x2 | |
| 276 | #define PIXIS_VSPEED2_TSEC4SER 0x1 | |
| 277 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
| 278 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 | |
| 279 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 | |
| 280 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 | |
| 281 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ | |
| 282 | | PIXIS_VSPEED2_TSEC2SER \ | |
| 283 | | PIXIS_VSPEED2_TSEC3SER \ | |
| 284 | | PIXIS_VSPEED2_TSEC4SER) | |
| 285 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ | |
| 286 | | PIXIS_VCFGEN1_TSEC2SER \ | |
| 287 | | PIXIS_VCFGEN1_TSEC3SER \ | |
| 288 | | PIXIS_VCFGEN1_TSEC4SER) | |
| 129ba616 | 289 | |
| 6d0f6bcf JCPV |
290 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 291 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 553f0982 | 292 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| 129ba616 | 293 | |
| 25ddd1fb | 294 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 295 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 129ba616 | 296 | |
| 6d0f6bcf JCPV |
297 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 298 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 129ba616 | 299 | |
| cb14e93b | 300 | #ifndef CONFIG_NAND_SPL |
| c013b749 | 301 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 18af1c5f KG |
302 | #ifdef CONFIG_PHYS_64BIT |
| 303 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
| 304 | #else | |
| c013b749 | 305 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 18af1c5f | 306 | #endif |
| cb14e93b KG |
307 | #else |
| 308 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
| 309 | #ifdef CONFIG_PHYS_64BIT | |
| 310 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
| 311 | #else | |
| 312 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 313 | #endif | |
| 314 | #endif | |
| 315 | ||
| c013b749 HW |
316 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 317 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
| 318 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
| 319 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
| 320 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
| c013b749 | 321 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 3cbd8231 WD |
322 | #define CONFIG_CMD_NAND 1 |
| 323 | #define CONFIG_NAND_FSL_ELBC 1 | |
| c013b749 HW |
324 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 325 | ||
| cb14e93b KG |
326 | /* NAND boot: 4K NAND loader config */ |
| 327 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
| 328 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
| 329 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
| 330 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
| 331 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
| 332 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
| 333 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 334 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 335 | ||
| 336 | ||
| c013b749 | 337 | /* NAND flash config */ |
| a3055c58 | 338 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 3cbd8231 WD |
339 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 340 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 341 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 342 | | BR_V) /* valid */ | |
| a3055c58 | 343 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
| 3cbd8231 WD |
344 | | OR_FCM_PGS /* Large Page*/ \ |
| 345 | | OR_FCM_CSCT \ | |
| 346 | | OR_FCM_CST \ | |
| 347 | | OR_FCM_CHT \ | |
| 348 | | OR_FCM_SCY_1 \ | |
| 349 | | OR_FCM_TRLX \ | |
| 350 | | OR_FCM_EHTR) | |
| c013b749 | 351 | |
| cb14e93b | 352 | #ifdef CONFIG_RAMBOOT_NAND |
| a3055c58 MM |
353 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 354 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| cb14e93b KG |
355 | #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 356 | #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 357 | #else | |
| 358 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 359 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| a3055c58 MM |
360 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 361 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| cb14e93b | 362 | #endif |
| 7ee41107 | 363 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
| 3cbd8231 WD |
364 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 365 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 366 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 367 | | BR_V) /* valid */ | |
| a3055c58 | 368 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| 7ee41107 | 369 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ |
| 3cbd8231 WD |
370 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 371 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 372 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 373 | | BR_V) /* valid */ | |
| a3055c58 | 374 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| c013b749 | 375 | |
| 7ee41107 | 376 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ |
| 3cbd8231 WD |
377 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 378 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 379 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 380 | | BR_V) /* valid */ | |
| a3055c58 | 381 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| c013b749 HW |
382 | |
| 383 | ||
| 129ba616 KG |
384 | /* Serial Port - controlled on board with jumper J8 |
| 385 | * open - index 2 | |
| 386 | * shorted - index 1 | |
| 387 | */ | |
| 388 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
389 | #define CONFIG_SYS_NS16550 |
| 390 | #define CONFIG_SYS_NS16550_SERIAL | |
| 391 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 392 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| cb14e93b KG |
393 | #ifdef CONFIG_NAND_SPL |
| 394 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 395 | #endif | |
| 129ba616 | 396 | |
| 6d0f6bcf | 397 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 129ba616 KG |
398 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 399 | ||
| 6d0f6bcf JCPV |
400 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 401 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 129ba616 KG |
402 | |
| 403 | /* Use the HUSH parser */ | |
| 6d0f6bcf | 404 | #define CONFIG_SYS_HUSH_PARSER |
| 129ba616 KG |
405 | |
| 406 | /* | |
| 407 | * Pass open firmware flat tree | |
| 408 | */ | |
| 409 | #define CONFIG_OF_LIBFDT 1 | |
| 410 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 411 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 412 | ||
| 129ba616 KG |
413 | /* new uImage format support */ |
| 414 | #define CONFIG_FIT 1 | |
| 415 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
| 416 | ||
| 417 | /* I2C */ | |
| 00f792e0 HS |
418 | #define CONFIG_SYS_I2C |
| 419 | #define CONFIG_SYS_I2C_FSL | |
| 420 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 421 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 422 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 423 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 424 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 425 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 426 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
| 6d0f6bcf | 427 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 129ba616 | 428 | |
| 445a7b38 HW |
429 | /* |
| 430 | * I2C2 EEPROM | |
| 431 | */ | |
| 432 | #define CONFIG_ID_EEPROM | |
| 433 | #ifdef CONFIG_ID_EEPROM | |
| 6d0f6bcf | 434 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 445a7b38 | 435 | #endif |
| 6d0f6bcf JCPV |
436 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 437 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 438 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 445a7b38 | 439 | |
| 129ba616 KG |
440 | /* |
| 441 | * General PCI | |
| 442 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 443 | */ | |
| 444 | ||
| 129ba616 | 445 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
| 18ea5551 | 446 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
| 5af0fdd8 | 447 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| 18af1c5f | 448 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 449 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
450 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| 451 | #else | |
| ad97dce1 | 452 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| 5af0fdd8 | 453 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| 18af1c5f | 454 | #endif |
| 6d0f6bcf | 455 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 456 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| 5f91ef6a | 457 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 18af1c5f KG |
458 | #ifdef CONFIG_PHYS_64BIT |
| 459 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
| 460 | #else | |
| 6d0f6bcf | 461 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| 18af1c5f | 462 | #endif |
| 6d0f6bcf | 463 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
464 | |
| 465 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 18ea5551 | 466 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
| 5af0fdd8 | 467 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 18af1c5f | 468 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 469 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
470 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 471 | #else | |
| ad97dce1 | 472 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 5af0fdd8 | 473 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| 18af1c5f | 474 | #endif |
| 6d0f6bcf | 475 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 476 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 5f91ef6a | 477 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 18af1c5f KG |
478 | #ifdef CONFIG_PHYS_64BIT |
| 479 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 480 | #else | |
| 6d0f6bcf | 481 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| 18af1c5f | 482 | #endif |
| 6d0f6bcf | 483 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
484 | |
| 485 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 18ea5551 | 486 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
| 5af0fdd8 | 487 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| 18af1c5f | 488 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 489 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
490 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| 491 | #else | |
| ad97dce1 | 492 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| 5af0fdd8 | 493 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| 18af1c5f | 494 | #endif |
| 6d0f6bcf | 495 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 496 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| 5f91ef6a | 497 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 18af1c5f KG |
498 | #ifdef CONFIG_PHYS_64BIT |
| 499 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
| 500 | #else | |
| 6d0f6bcf | 501 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| 18af1c5f | 502 | #endif |
| 6d0f6bcf | 503 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
504 | |
| 505 | #if defined(CONFIG_PCI) | |
| 506 | ||
| 507 | /*PCIE video card used*/ | |
| aca5f018 | 508 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| 129ba616 KG |
509 | |
| 510 | /* video */ | |
| 511 | #define CONFIG_VIDEO | |
| 512 | ||
| 513 | #if defined(CONFIG_VIDEO) | |
| 514 | #define CONFIG_BIOSEMU | |
| 515 | #define CONFIG_CFB_CONSOLE | |
| 516 | #define CONFIG_VIDEO_SW_CURSOR | |
| 517 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 518 | #define CONFIG_ATI_RADEON_FB | |
| 519 | #define CONFIG_VIDEO_LOGO | |
| 520 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
| 6d0f6bcf | 521 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| 129ba616 KG |
522 | #endif |
| 523 | ||
| 129ba616 KG |
524 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 525 | ||
| 526 | #undef CONFIG_EEPRO100 | |
| 527 | #undef CONFIG_TULIP | |
| 528 | #undef CONFIG_RTL8139 | |
| 16855ec1 | 529 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
| 129ba616 | 530 | |
| 129ba616 | 531 | #ifndef CONFIG_PCI_PNP |
| 5f91ef6a KG |
532 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
| 533 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
| 129ba616 KG |
534 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 535 | #endif | |
| 536 | ||
| 537 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 538 | #define CONFIG_DOS_PARTITION | |
| 539 | #define CONFIG_SCSI_AHCI | |
| 540 | ||
| 541 | #ifdef CONFIG_SCSI_AHCI | |
| 542 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
543 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 544 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 545 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 546 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| 129ba616 KG |
547 | #endif /* SCSI */ |
| 548 | ||
| 549 | #endif /* CONFIG_PCI */ | |
| 550 | ||
| 551 | ||
| 552 | #if defined(CONFIG_TSEC_ENET) | |
| 553 | ||
| 129ba616 KG |
554 | #define CONFIG_MII 1 /* MII PHY management */ |
| 555 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 556 | #define CONFIG_TSEC1 1 | |
| 557 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 558 | #define CONFIG_TSEC2 1 | |
| 559 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 560 | #define CONFIG_TSEC3 1 | |
| 561 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 562 | #define CONFIG_TSEC4 1 | |
| 563 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| 564 | ||
| 7e183cad LY |
565 | #define CONFIG_PIXIS_SGMII_CMD |
| 566 | #define CONFIG_FSL_SGMII_RISER 1 | |
| 567 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
| 568 | ||
| 569 | #ifdef CONFIG_FSL_SGMII_RISER | |
| 570 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
| 571 | #endif | |
| 572 | ||
| 129ba616 KG |
573 | #define TSEC1_PHY_ADDR 0 |
| 574 | #define TSEC2_PHY_ADDR 1 | |
| 575 | #define TSEC3_PHY_ADDR 2 | |
| 576 | #define TSEC4_PHY_ADDR 3 | |
| 577 | ||
| 578 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 579 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 580 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 581 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 582 | ||
| 583 | #define TSEC1_PHYIDX 0 | |
| 584 | #define TSEC2_PHYIDX 0 | |
| 585 | #define TSEC3_PHYIDX 0 | |
| 586 | #define TSEC4_PHYIDX 0 | |
| 587 | ||
| 588 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 589 | ||
| 590 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 591 | #endif /* CONFIG_TSEC_ENET */ | |
| 592 | ||
| 593 | /* | |
| 594 | * Environment | |
| 595 | */ | |
| cb14e93b KG |
596 | |
| 597 | #if defined(CONFIG_SYS_RAMBOOT) | |
| 598 | #if defined(CONFIG_RAMBOOT_NAND) | |
| 599 | #define CONFIG_ENV_IS_IN_NAND 1 | |
| 600 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| 601 | #define CONFIG_ENV_OFFSET ((512 * 1024)\ | |
| 602 | + CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 603 | #endif | |
| 604 | ||
| 129ba616 | 605 | #else |
| cb14e93b KG |
606 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 607 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
| 608 | #define CONFIG_ENV_ADDR 0xfff80000 | |
| 609 | #else | |
| 610 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 611 | #endif | |
| 612 | #define CONFIG_ENV_SIZE 0x2000 | |
| 613 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 129ba616 | 614 | #endif |
| 129ba616 KG |
615 | |
| 616 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 617 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 129ba616 KG |
618 | |
| 619 | /* | |
| 620 | * Command line configuration. | |
| 621 | */ | |
| 622 | #include <config_cmd_default.h> | |
| 623 | ||
| 67f94476 | 624 | #define CONFIG_CMD_ERRATA |
| 129ba616 KG |
625 | #define CONFIG_CMD_IRQ |
| 626 | #define CONFIG_CMD_PING | |
| 627 | #define CONFIG_CMD_I2C | |
| 628 | #define CONFIG_CMD_MII | |
| 629 | #define CONFIG_CMD_ELF | |
| 1c9aa76b | 630 | #define CONFIG_CMD_SETEXPR |
| 199e262e | 631 | #define CONFIG_CMD_REGINFO |
| 129ba616 KG |
632 | |
| 633 | #if defined(CONFIG_PCI) | |
| 634 | #define CONFIG_CMD_PCI | |
| 129ba616 KG |
635 | #define CONFIG_CMD_NET |
| 636 | #define CONFIG_CMD_SCSI | |
| 637 | #define CONFIG_CMD_EXT2 | |
| 638 | #endif | |
| 639 | ||
| 863a3eac ZC |
640 | /* |
| 641 | * USB | |
| 642 | */ | |
| 643 | #define CONFIG_USB_EHCI | |
| 644 | ||
| 645 | #ifdef CONFIG_USB_EHCI | |
| 646 | #define CONFIG_CMD_USB | |
| 647 | #define CONFIG_USB_EHCI_PCI | |
| 648 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 649 | #define CONFIG_USB_STORAGE | |
| 650 | #define CONFIG_PCI_EHCI_DEVICE 0 | |
| 651 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 | |
| 652 | #endif | |
| 653 | ||
| 129ba616 KG |
654 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 655 | ||
| 656 | /* | |
| 657 | * Miscellaneous configurable options | |
| 658 | */ | |
| 6d0f6bcf | 659 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 5be58f5f KP |
660 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 661 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 6d0f6bcf JCPV |
662 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 663 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 129ba616 | 664 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 665 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 129ba616 | 666 | #else |
| 6d0f6bcf | 667 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 129ba616 | 668 | #endif |
| 6d0f6bcf JCPV |
669 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 670 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 671 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 672 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 129ba616 KG |
673 | |
| 674 | /* | |
| 675 | * For booting Linux, the board info and command line data | |
| a832ac41 | 676 | * have to be in the first 64 MB of memory, since this is |
| 129ba616 KG |
677 | * the maximum mapped by the Linux kernel during initialization. |
| 678 | */ | |
| a832ac41 KG |
679 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 680 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 129ba616 | 681 | |
| 129ba616 KG |
682 | #if defined(CONFIG_CMD_KGDB) |
| 683 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 684 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 685 | #endif | |
| 686 | ||
| 687 | /* | |
| 688 | * Environment Configuration | |
| 689 | */ | |
| 690 | ||
| 691 | /* The mac addresses for all ethernet interface */ | |
| 692 | #if defined(CONFIG_TSEC_ENET) | |
| 693 | #define CONFIG_HAS_ETH0 | |
| 694 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
| 695 | #define CONFIG_HAS_ETH1 | |
| 696 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
| 697 | #define CONFIG_HAS_ETH2 | |
| 698 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
| 699 | #define CONFIG_HAS_ETH3 | |
| 700 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
| 701 | #endif | |
| 702 | ||
| 703 | #define CONFIG_IPADDR 192.168.1.254 | |
| 704 | ||
| 705 | #define CONFIG_HOSTNAME unknown | |
| 8b3637c6 | 706 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 707 | #define CONFIG_BOOTFILE "uImage" |
| 129ba616 KG |
708 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 709 | ||
| 710 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 711 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 712 | #define CONFIG_NETMASK 255.255.255.0 | |
| 713 | ||
| 714 | /* default location for tftp and bootm */ | |
| 715 | #define CONFIG_LOADADDR 1000000 | |
| 716 | ||
| 717 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 718 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 719 | ||
| 720 | #define CONFIG_BAUDRATE 115200 | |
| 721 | ||
| 722 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 238e1467 | 723 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ |
| 5368c55d MV |
724 | "netdev=eth0\0" \ |
| 725 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 726 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 727 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 728 | " +$filesize; " \ | |
| 729 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 730 | " +$filesize; " \ | |
| 731 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 732 | " $filesize; " \ | |
| 733 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 734 | " +$filesize; " \ | |
| 735 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 736 | " $filesize\0" \ | |
| 737 | "consoledev=ttyS0\0" \ | |
| 738 | "ramdiskaddr=2000000\0" \ | |
| 739 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ | |
| 740 | "fdtaddr=c00000\0" \ | |
| 741 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ | |
| 742 | "bdev=sda3\0" | |
| 129ba616 KG |
743 | |
| 744 | #define CONFIG_HDBOOT \ | |
| 745 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 746 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 747 | "tftp $loadaddr $bootfile;" \ | |
| 748 | "tftp $fdtaddr $fdtfile;" \ | |
| 749 | "bootm $loadaddr - $fdtaddr" | |
| 750 | ||
| 751 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 752 | "setenv bootargs root=/dev/nfs rw " \ | |
| 753 | "nfsroot=$serverip:$rootpath " \ | |
| 754 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 755 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 756 | "tftp $loadaddr $bootfile;" \ | |
| 757 | "tftp $fdtaddr $fdtfile;" \ | |
| 758 | "bootm $loadaddr - $fdtaddr" | |
| 759 | ||
| 760 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 761 | "setenv bootargs root=/dev/ram rw " \ | |
| 762 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 763 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 764 | "tftp $loadaddr $bootfile;" \ | |
| 765 | "tftp $fdtaddr $fdtfile;" \ | |
| 766 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 767 | ||
| 768 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 769 | ||
| 770 | #endif /* __CONFIG_H */ |