[people/ms/u-boot.git] / include / configs / km / km_arm.h

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Prafulla Wadaskar <prafulla@marvell.com>
 *
 * (C) Copyright 2009
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2010-2011
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * for linking errors see
 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
 */

#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_MARVELL
#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
#define CONFIG_KW88F6281		/* SOC Name */
#define CONFIG_MACH_KM_KIRKWOOD		/* Machine type */

#define CONFIG_MACH_TYPE	MACH_TYPE_KM_KIRKWOOD

#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH

/* include common defines/options for all Keymile boards */
#include "keymile-common.h"

#define CONFIG_CMD_NAND

/* SPI NOR Flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		8100000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		8100000
#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#endif

/* Reserve 4 MB for malloc */
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#include "asm/arch/config.h"

#define CONFIG_SYS_TEXT_BASE	0x07d00000	/* code address before reloc */
#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */

/* pseudo-non volatile RAM [hex] */
#define CONFIG_KM_PNVRAM	0x80000
/* physical RAM MTD size [hex] */
#define CONFIG_KM_PHRAM		0x17F000

#define CONFIG_KM_CRAMFS_ADDR	0x2400000
#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 3098KBytes */
#define CONFIG_KM_FDT_ADDR	0x23E0000	/*  128KBytes */

/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
		"bootcountaddr=${bootcountaddr} ${mtdparts}"		\
		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"

#define CONFIG_KM_DEF_ENV_CPU						\
	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0"		\
	CONFIG_KM_UPDATE_UBOOT						\
	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
	"checkfdt="							\
		"if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; "	\
		"then true; else setenv cramfsloadfdt true; "		\
		"setenv boot bootm ${load_addr_r}; "			\
		"echo No FDT found, booting with the kernel "		\
		"appended one; fi\0"					\
	""

#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
#define CONFIG_MISC_INIT_R

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
#define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE

/*
 * Serial Port configuration
 * The following definitions let you select what serial you want to use
 * for your console driver.
 */

#define CONFIG_CONS_INDEX	1	/* Console on UART0 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
#define CONFIG_INITRD_TAG		/* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */

/*
 * Commands configuration
 */
#define CONFIG_CMD_MTDPARTS

/*
 * NAND Flash configuration
 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define BOOTFLASH_START		0x0

/* Kirkwood has two serial IF */
#if (CONFIG_CONS_INDEX == 2)
#define CONFIG_KM_CONSOLE_TTY	"ttyS1"
#else
#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
#endif

/*
 * Other required minimal configurations
 */
#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
#define CONFIG_NR_DRAM_BANKS	4
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */

/*
 * Ethernet Driver configuration
 */
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define CONFIG_MII		/* expose smi ove miiphy interface */
#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
#define CONFIG_PHY_BASE_ADR	0
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */

/*
 * UBI related stuff
 */
#define CONFIG_SYS_USE_UBI

/*
 * I2C related stuff
 */
#undef CONFIG_I2C_MVTWSI
#define CONFIG_SYS_I2C
#define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
#define CONFIG_SYS_I2C_INIT_BOARD

#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
#define CONFIG_SYS_NUM_I2C_BUSES	6
#define CONFIG_SYS_I2C_MAX_HOPS		1
#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
				}

#ifndef __ASSEMBLY__
#include <asm/arch/gpio.h>
extern void __set_direction(unsigned pin, int high);
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
#define KM_KIRKWOOD_SDA_PIN	8
#define KM_KIRKWOOD_SCL_PIN	9
#define KM_KIRKWOOD_SOFT_I2C_GPIOS	0x0300
#define KM_KIRKWOOD_ENV_WP	38

#define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
#define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
#define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
#define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
#define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
#endif

#define I2C_DELAY	udelay(1)
#define I2C_SOFT_DECLARATIONS

#define	CONFIG_SYS_I2C_SOFT_SLAVE	0x0
#define	CONFIG_SYS_I2C_SOFT_SPEED	100000

/* EEprom support 24C128, 24C256 valid for environment eeprom */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6 /* 64 Byte write page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2

/*
 *  Environment variables configurations
 */
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_ENV_IS_IN_SPI_FLASH  /* use SPI-Flash for environment vars */
#define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
#define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
#define CONFIG_ENV_SECT_SIZE		0x10000
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
					CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
#else
#define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
#define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_EEPROM_WREN
#define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
#define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
#define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
#endif

#define CONFIG_SYS_REDUNDAND_ENVIRONMENT


/* SPI bus claim MPP configuration */
#define CONFIG_SYS_KW_SPI_MPP	0x0

#define FLASH_GPIO_PIN			0x00010000
#define KM_FLASH_GPIO_PIN	16

#ifndef MTDIDS_DEFAULT
# define MTDIDS_DEFAULT		"nand0=orion_nand"
#endif /* MTDIDS_DEFAULT */

#ifndef MTDPARTS_DEFAULT
# define MTDPARTS_DEFAULT	"mtdparts="			\
	"orion_nand:"						\
		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
#endif /* MTDPARTS_DEFAULT */

#define	CONFIG_KM_UPDATE_UBOOT						\
	"update="							\
		"sf probe 0;sf erase 0 +${filesize};"			\
		"sf write ${load_addr_r} 0 ${filesize};\0"

#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_NEW_ENV						\
	"newenv=sf probe 0;"						\
		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
#else
#define CONFIG_KM_NEW_ENV						\
	"newenv=setenv addr 0x100000 && "				\
		"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; "  \
		"mw.b ${addr} 0 4 && "					\
		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
		" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && "	\
		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
#endif

#ifndef CONFIG_KM_BOARD_EXTRA_ENV
#define CONFIG_KM_BOARD_EXTRA_ENV       ""
#endif

/*
 * Default environment variables
 */
#define CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_KM_BOARD_EXTRA_ENV					\
	CONFIG_KM_DEF_ENV						\
	CONFIG_KM_NEW_ENV						\
	"arch=arm\0"							\
	""

#if !defined(CONFIG_MTD_NOR_FLASH)
#undef	CONFIG_FLASH_CFI_MTD
#undef	CONFIG_JFFS2_CMDLINE
#endif

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
/* Do early setups now in board_init_f() */

/*
 * resereved pram area at the end of memroy [hex]
 * 8Mbytes for switch + 4Kbytes for bootcount
 */
#define CONFIG_KM_RESERVED_PRAM 0x801000
/* address for the bootcount (taken from end of RAM) */
#define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
/* Use generic bootcount RAM driver */
#define CONFIG_BOOTCOUNT_RAM

/* enable POST tests */
#define CONFIG_POST	(CONFIG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_SKIP_ENV_FLAGS
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
#define CONFIG_CMD_DIAG

/* we do the whole PCIe FPGA config stuff here */

#endif /* _CONFIG_KM_ARM_H */
Commit	Line	Data
67fa8c25 HS	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Prafulla Wadaskar <prafulla@marvell.com>
	5	*
	6	* (C) Copyright 2009
	7	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	8	*
b11f53f3 HS	9	* (C) Copyright 2010-2011
	10	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
67fa8c25 HS	13	*/
67fa8c25 HS	14
b11f53f3 HS	15	/*
	16	* for linking errors see
	17	* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
	18	*/
67fa8c25 HS	19
	20	#ifndef _CONFIG_KM_ARM_H
	21	#define _CONFIG_KM_ARM_H
	22
	23	/*
	24	* High Level Configuration Options (easy to change)
	25	*/
	26	#define CONFIG_MARVELL
67fa8c25	27	#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
67fa8c25	28	#define CONFIG_KW88F6281 /* SOC Name */
802d9963	29	#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
67fa8c25	30
8620ca2a VL	31	#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
8620ca2a VL	32
dfeafde4 HB	33	#define CONFIG_NAND_ECC_BCH
	34	#define CONFIG_BCH
	35
67fa8c25 HS	36	/* include common defines/options for all Keymile boards */
67fa8c25 HS	37	#include "keymile-common.h"
de3ad13d	38
b5befd82	39	#define CONFIG_CMD_NAND
b5befd82	40
f46b4a1a VL	41	/* SPI NOR Flash default params, used by sf commands */
	42	#define CONFIG_SF_DEFAULT_SPEED 8100000
	43	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	44
8170aefc HB	45	#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
	46	#define CONFIG_ENV_SPI_BUS 0
	47	#define CONFIG_ENV_SPI_CS 0
05c8e81f	48	#define CONFIG_ENV_SPI_MAX_HZ 8100000
8170aefc HB	49	#define CONFIG_ENV_SPI_MODE SPI_MODE_3
	50	#endif
	51
ac5b00e0 VL	52	/* Reserve 4 MB for malloc */
	53	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	54
b5befd82 HB	55	#include "asm/arch/config.h"
b5befd82 HB	56
e5847b77	57	#define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */
de3ad13d HB	58	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
	59	#define CONFIG_SYS_MEMTEST_END 0x007fffff /(_8M -1) /
	60	#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
	61
	62	/* pseudo-non volatile RAM [hex] */
	63	#define CONFIG_KM_PNVRAM 0x80000
	64	/* physical RAM MTD size [hex] */
	65	#define CONFIG_KM_PHRAM 0x17F000
	66
	67	#define CONFIG_KM_CRAMFS_ADDR 0x2400000
7b2268b8 GF	68	#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */
7b2268b8 GF	69	#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */
de3ad13d	70
db0bb572 HB	71	/* architecture specific default bootargs */
db0bb572 HB	72	#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
66072a8c HB	73	"bootcountaddr=${bootcountaddr} ${mtdparts}" \
66072a8c HB	74	" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
db0bb572	75
de3ad13d	76	#define CONFIG_KM_DEF_ENV_CPU \
93ea89f0	77	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
af85f085	78	CONFIG_KM_UPDATE_UBOOT \
b1c2a7ae	79	"set_fdthigh=setenv fdt_high ${kernelmem}\0" \
c6d32dfd VL	80	"checkfdt=" \
	81	"if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \
	82	"then true; else setenv cramfsloadfdt true; " \
	83	"setenv boot bootm ${load_addr_r}; " \
	84	"echo No FDT found, booting with the kernel " \
	85	"appended one; fi\0" \
de3ad13d HB	86	""
de3ad13d HB	87
67fa8c25	88	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
67fa8c25 HS	89	#define CONFIG_MISC_INIT_R
	90
	91	/*
	92	* NS16550 Configuration
	93	*/
67fa8c25 HS	94	#define CONFIG_SYS_NS16550_SERIAL
	95	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	96	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
	97	#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
3d3c7096	98	#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
67fa8c25 HS	99
	100	/*
	101	* Serial Port configuration
	102	* The following definitions let you select what serial you want to use
	103	* for your console driver.
	104	*/
	105
	106	#define CONFIG_CONS_INDEX 1 /* Console on UART0 */
	107
	108	/*
	109	* For booting Linux, the board info and command line data
	110	* have to be in the first 8 MB of memory, since this is
	111	* the maximum mapped by the Linux kernel during initialization.
	112	*/
	113	#define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
	114	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	115	#define CONFIG_INITRD_TAG /* enable INITRD tag */
499b1a4d	116	#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
67fa8c25 HS	117
	118	/*
	119	* Commands configuration
	120	*/
67fa8c25	121	#define CONFIG_CMD_MTDPARTS
67fa8c25	122
67fa8c25 HS	123	/*
	124	* NAND Flash configuration
	125	*/
	126	#define CONFIG_SYS_MAX_NAND_DEVICE 1
67fa8c25 HS	127
	128	#define BOOTFLASH_START 0x0
	129
3d3c7096 HB	130	/* Kirkwood has two serial IF */
	131	#if (CONFIG_CONS_INDEX == 2)
	132	#define CONFIG_KM_CONSOLE_TTY "ttyS1"
	133	#else
67fa8c25	134	#define CONFIG_KM_CONSOLE_TTY "ttyS0"
3d3c7096	135	#endif
67fa8c25	136
67fa8c25 HS	137	/*
	138	* Other required minimal configurations
	139	*/
67fa8c25	140	#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
67fa8c25	141	#define CONFIG_NR_DRAM_BANKS 4
67fa8c25 HS	142	#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
	143
	144	/*
	145	* Ethernet Driver configuration
	146	*/
	147	#define CONFIG_NETCONSOLE /* include NetConsole support */
67fa8c25	148	#define CONFIG_MII /* expose smi ove miiphy interface */
d44265ad	149	#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
67fa8c25	150	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
d44265ad	151	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
67fa8c25 HS	152	#define CONFIG_PHY_BASE_ADR 0
67fa8c25 HS	153	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
99f6249a	154	#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
67fa8c25 HS	155
	156	/*
	157	* UBI related stuff
	158	*/
	159	#define CONFIG_SYS_USE_UBI
	160
	161	/*
	162	* I2C related stuff
	163	*/
ea818dbb HS	164	#undef CONFIG_I2C_MVTWSI
	165	#define CONFIG_SYS_I2C
	166	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
0a4f88b9	167	#define CONFIG_SYS_I2C_INIT_BOARD
ea818dbb	168
67fa8c25	169	#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
ea818dbb HS	170	#define CONFIG_SYS_NUM_I2C_BUSES 6
	171	#define CONFIG_SYS_I2C_MAX_HOPS 1
	172	#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
	173	{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
	174	{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
	175	{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
	176	{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
	177	{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
	178	}
	179
67fa8c25	180	#ifndef __ASSEMBLY__
ea385723	181	#include <asm/arch/gpio.h>
67fa8c25	182	extern void __set_direction(unsigned pin, int high);
499b1a4d HB	183	void set_sda(int state);
	184	void set_scl(int state);
	185	int get_sda(void);
	186	int get_scl(void);
44097e26 HS	187	#define KM_KIRKWOOD_SDA_PIN 8
44097e26 HS	188	#define KM_KIRKWOOD_SCL_PIN 9
c471d848	189	#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
44097e26 HS	190	#define KM_KIRKWOOD_ENV_WP 38
	191
	192	#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
	193	#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1)
	194	#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
	195	#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
	196	#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
67fa8c25 HS	197	#endif
67fa8c25 HS	198
9e9c6d7c	199	#define I2C_DELAY udelay(1)
67fa8c25 HS	200	#define I2C_SOFT_DECLARATIONS
67fa8c25 HS	201
ea818dbb HS	202	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0
ea818dbb HS	203	#define CONFIG_SYS_I2C_SOFT_SPEED 100000
67fa8c25	204
4daea6ff	205	/* EEprom support 24C128, 24C256 valid for environment eeprom */
4daea6ff SB	206	#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
	207	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
	208	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	209
67fa8c25 HS	210	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	211	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	212
331a30dc HS	213	/*
	214	* Environment variables configurations
	215	*/
8170aefc HB	216	#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
	217	#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */
	218	#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */
	219	#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */
	220	#define CONFIG_ENV_SECT_SIZE 0x10000
	221	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	222	CONFIG_ENV_SECT_SIZE)
	223	#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */
	224	#else
331a30dc HS	225	#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
	226	#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
	227	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	228	#define CONFIG_SYS_EEPROM_WREN
	229	#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
331a30dc	230	#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
716e4ffe	231	#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
331a30dc HS	232	#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
331a30dc HS	233	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
8170aefc HB	234	#endif
	235
	236	#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
331a30dc	237
331a30dc	238
0c25defc VL	239	/* SPI bus claim MPP configuration */
	240	#define CONFIG_SYS_KW_SPI_MPP 0x0
	241
331a30dc	242	#define FLASH_GPIO_PIN 0x00010000
0c25defc	243	#define KM_FLASH_GPIO_PIN 16
331a30dc	244
cf73639d AH	245	#ifndef MTDIDS_DEFAULT
	246	# define MTDIDS_DEFAULT "nand0=orion_nand"
	247	#endif /* MTDIDS_DEFAULT */
	248
	249	#ifndef MTDPARTS_DEFAULT
	250	# define MTDPARTS_DEFAULT "mtdparts=" \
	251	"orion_nand:" \
	252	"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
	253	#endif /* MTDPARTS_DEFAULT */
331a30dc	254
af85f085	255	#define CONFIG_KM_UPDATE_UBOOT \
331a30dc	256	"update=" \
0c25defc VL	257	"sf probe 0;sf erase 0 +${filesize};" \
0c25defc VL	258	"sf write ${load_addr_r} 0 ${filesize};\0"
331a30dc	259
8170aefc HB	260	#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
	261	#define CONFIG_KM_NEW_ENV \
	262	"newenv=sf probe 0;" \
93ea89f0 MV	263	"sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
93ea89f0 MV	264	__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
8170aefc HB	265	#else
8170aefc HB	266	#define CONFIG_KM_NEW_ENV \
ea616d4d	267	"newenv=setenv addr 0x100000 && " \
67bfae36 HB	268	"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \
67bfae36 HB	269	"mw.b ${addr} 0 4 && " \
93ea89f0 MV	270	"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
	271	" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \
	272	"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
	273	" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
8170aefc HB	274	#endif
8170aefc HB	275
56cde177 HB	276	#ifndef CONFIG_KM_BOARD_EXTRA_ENV
	277	#define CONFIG_KM_BOARD_EXTRA_ENV ""
	278	#endif
	279
8170aefc HB	280	/*
	281	* Default environment variables
	282	*/
	283	#define CONFIG_EXTRA_ENV_SETTINGS \
56cde177	284	CONFIG_KM_BOARD_EXTRA_ENV \
8170aefc HB	285	CONFIG_KM_DEF_ENV \
8170aefc HB	286	CONFIG_KM_NEW_ENV \
b648bfc2	287	"arch=arm\0" \
ea616d4d VL	288	""
ea616d4d VL	289
e856bdcf	290	#if !defined(CONFIG_MTD_NOR_FLASH)
67fa8c25 HS	291	#undef CONFIG_FLASH_CFI_MTD
	292	#undef CONFIG_JFFS2_CMDLINE
	293	#endif
	294
a784c01a	295	/* additions for new relocation code, must be added to all boards */
ab86f72c	296	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6b0ccc3b	297	/* Do early setups now in board_init_f() */
f1fef1d8 HS	298
	299	/*
	300	* resereved pram area at the end of memroy [hex]
	301	* 8Mbytes for switch + 4Kbytes for bootcount
	302	*/
	303	#define CONFIG_KM_RESERVED_PRAM 0x801000
a21b5d4b HB	304	/* address for the bootcount (taken from end of RAM) */
a21b5d4b HB	305	#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)
0044c42e SR	306	/* Use generic bootcount RAM driver */
0044c42e SR	307	#define CONFIG_BOOTCOUNT_RAM
f1fef1d8	308
9400f8fa VL	309	/* enable POST tests */
	310	#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
	311	#define CONFIG_POST_SKIP_ENV_FLAGS
	312	#define CONFIG_POST_EXTERNAL_WORD_FUNCS
	313	#define CONFIG_CMD_DIAG
	314
b37f7724	315	/* we do the whole PCIe FPGA config stuff here */
b37f7724	316
67fa8c25	317	#endif /* _CONFIG_KM_ARM_H */