]>
Commit | Line | Data |
---|---|---|
8449f287 ML |
1 | /* |
2 | * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> | |
3 | * | |
4 | * (C) Copyright 2004 | |
5 | * Texas Instruments. | |
6 | * Richard Woodruff <r-woodruff2@ti.com> | |
7 | * Kshitij Gupta <kshitij@ti.com> | |
8 | * | |
9 | * Configuration settings for the Freescale i.MX31 PDK board. | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
8449f287 ML |
12 | */ |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
86271115 | 17 | #include <asm/arch/imx-regs.h> |
38a8b3ea | 18 | |
8449f287 | 19 | /* High Level Configuration Options */ |
3fd968e9 | 20 | #define CONFIG_MX31 /* This is a mx31 */ |
8449f287 | 21 | |
e89f1f91 FE |
22 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
23 | #define CONFIG_SETUP_MEMORY_TAGS | |
24 | #define CONFIG_INITRD_TAG | |
8449f287 | 25 | |
9aa3c6a1 FE |
26 | #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS |
27 | ||
da962b71 | 28 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
da962b71 | 29 | #define CONFIG_SPL_MAX_SIZE 2048 |
da962b71 BT |
30 | |
31 | #define CONFIG_SPL_TEXT_BASE 0x87dc0000 | |
32 | #define CONFIG_SYS_TEXT_BASE 0x87e00000 | |
33 | ||
34 | #ifndef CONFIG_SPL_BUILD | |
8449f287 | 35 | #define CONFIG_SKIP_LOWLEVEL_INIT |
d08e5ca3 | 36 | #endif |
8449f287 ML |
37 | |
38 | /* | |
39 | * Size of malloc() pool | |
40 | */ | |
38a8b3ea | 41 | #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) |
8449f287 ML |
42 | |
43 | /* | |
44 | * Hardware drivers | |
45 | */ | |
46 | ||
e89f1f91 | 47 | #define CONFIG_MXC_UART |
40f6fffe | 48 | #define CONFIG_MXC_UART_BASE UART1_BASE |
6f2a4be9 | 49 | #define CONFIG_MXC_GPIO |
8449f287 | 50 | |
e89f1f91 FE |
51 | #define CONFIG_HARD_SPI |
52 | #define CONFIG_MXC_SPI | |
8449f287 | 53 | #define CONFIG_DEFAULT_SPI_BUS 1 |
9f481e95 | 54 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
8449f287 | 55 | |
877a438a | 56 | /* PMIC Controller */ |
be3b51aa ŁM |
57 | #define CONFIG_POWER |
58 | #define CONFIG_POWER_SPI | |
59 | #define CONFIG_POWER_FSL | |
dfe5e14f SB |
60 | #define CONFIG_FSL_PMIC_BUS 1 |
61 | #define CONFIG_FSL_PMIC_CS 2 | |
62 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
9f481e95 | 63 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
877a438a | 64 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 65 | #define CONFIG_RTC_MC13XXX |
8449f287 | 66 | |
8449f287 ML |
67 | /* allow to overwrite serial and ethaddr */ |
68 | #define CONFIG_ENV_OVERWRITE | |
69 | #define CONFIG_CONS_INDEX 1 | |
8449f287 | 70 | |
8449f287 ML |
71 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
72 | "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ | |
73 | "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ | |
74 | "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ | |
75 | "bootcmd=run bootcmd_net\0" \ | |
76 | "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ | |
38a8b3ea | 77 | "tftpboot 0x81000000 uImage-mx31; bootm\0" \ |
da962b71 | 78 | "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ |
38a8b3ea ML |
79 | "nand erase 0x0 0x40000; " \ |
80 | "nand write 0x81000000 0x0 0x40000\0" | |
8449f287 | 81 | |
8449f287 ML |
82 | /* |
83 | * Miscellaneous configurable options | |
84 | */ | |
85 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
8449f287 ML |
86 | |
87 | /* memtest works on */ | |
88 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
304e49e6 | 89 | #define CONFIG_SYS_MEMTEST_END 0x80010000 |
8449f287 ML |
90 | |
91 | /* default load address */ | |
92 | #define CONFIG_SYS_LOAD_ADDR 0x81000000 | |
93 | ||
e89f1f91 | 94 | #define CONFIG_CMDLINE_EDITING |
8449f287 | 95 | |
8449f287 ML |
96 | /*----------------------------------------------------------------------- |
97 | * Physical Memory Map | |
98 | */ | |
99 | #define CONFIG_NR_DRAM_BANKS 1 | |
100 | #define PHYS_SDRAM_1 CSD0_BASE | |
101 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
102 | ||
ed3df72d FE |
103 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
104 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
105 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
026ca659 FE |
106 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
107 | GENERATED_GBL_DATA_SIZE) | |
108 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
da962b71 | 109 | CONFIG_SYS_INIT_RAM_SIZE) |
ed3df72d | 110 | |
e856bdcf MY |
111 | /* |
112 | * environment organization | |
8449f287 | 113 | */ |
38a8b3ea ML |
114 | #define CONFIG_ENV_OFFSET 0x40000 |
115 | #define CONFIG_ENV_OFFSET_REDUND 0x60000 | |
116 | #define CONFIG_ENV_SIZE (128 * 1024) | |
8449f287 | 117 | |
38a8b3ea ML |
118 | /* |
119 | * NAND driver | |
120 | */ | |
38a8b3ea ML |
121 | #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR |
122 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
123 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
124 | #define CONFIG_MXC_NAND_HWECC | |
125 | #define CONFIG_SYS_NAND_LARGEPAGE | |
8449f287 | 126 | |
d08e5ca3 ML |
127 | /* NAND configuration for the NAND_SPL */ |
128 | ||
a187559e | 129 | /* Start copying real U-Boot from the second page */ |
da962b71 BT |
130 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
131 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 | |
d08e5ca3 | 132 | /* Load U-Boot to this address */ |
da962b71 | 133 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE |
d08e5ca3 ML |
134 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
135 | ||
136 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 | |
137 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
138 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
139 | #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) | |
140 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
141 | ||
d08e5ca3 ML |
142 | /* Configuration of lowlevel_init.S (clocks and SDRAM) */ |
143 | #define CCM_CCMR_SETUP 0x074B0BF5 | |
9e0081d5 BT |
144 | #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ |
145 | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ | |
146 | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ | |
147 | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) | |
148 | #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ | |
d08e5ca3 ML |
149 | PLL_MFN(12)) |
150 | ||
151 | #define ESDMISC_MDDR_SETUP 0x00000004 | |
152 | #define ESDMISC_MDDR_RESET_DL 0x0000000c | |
153 | #define ESDCFG0_MDDR_SETUP 0x006ac73a | |
154 | ||
155 | #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) | |
156 | #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ | |
157 | ESDCTL_DSIZ(2) | ESDCTL_BL(1)) | |
158 | #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) | |
159 | #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) | |
160 | #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) | |
161 | #define ESDCTL_RW ESDCTL_SETTINGS | |
162 | ||
8449f287 | 163 | #endif /* __CONFIG_H */ |