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252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
73cd51e5
AV		 358/* MVE opcodes. */
359
360struct mopcode32
361{
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368};
369
6b0dd094
AV		 370enum isa {
371 ANY,
372 T32,
373 ARM
374};
375
376
377/* Shared (between Arm and Thumb mode) opcode. */
378struct sopcode32
379{
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385};
386
6b5d3a4d
ZW		 387struct opcode16
388{
823d2571 389 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 391 const char *assembler; /* How to disassemble this insn. */
392};
b7693d02 393
8f06b2d8 394/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 395
2fbad815 396 %% %
4a5329c6 397
c22aaad1 398 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 399 %q print shifter argument
e2efe87d
MGD		 400 %u print condition code (unconditional in ARM mode,
401 UNPREDICTABLE if not AL in Thumb)
4a5329c6 402 %A print address for ldc/stc/ldf/stf instruction
16980d0b 403 %B print vstm/vldm register list
efd6b359 404 %C print vscclrm register list
4a5329c6 405 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 406 %J print register for VLDR instruction
407 %K print address for VLDR instruction
4a5329c6
ZW		 408 %F print the COUNT field of a LFM/SFM instruction.
409 %P print floating point precision in arithmetic insn
410 %Q print floating point precision in ldf/stf insn
411 %R print floating point rounding mode
412
33399f07 413 %<bitfield>c print as a condition code (for vsel)
4a5329c6 414 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 415 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
416 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 417 %<bitfield>d print the bitfield in decimal
16980d0b 418 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 419 %<bitfield>x print the bitfield in hex
420 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 421 %<bitfield>f print a floating point constant if >7 else a
422 floating point register
4a5329c6
ZW		 423 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
424 %<bitfield>g print as an iWMMXt 64-bit register
425 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 426 %<bitfield>D print as a NEON D register
427 %<bitfield>Q print as a NEON Q register
c28eeff2 428 %<bitfield>V print as a NEON D or Q register
6f1c2142 429 %<bitfield>E print a quarter-float immediate value
4a5329c6 430
16980d0b 431 %y<code> print a single precision VFP reg.
2fbad815 432 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 433 %z<code> print a double precision VFP reg
2fbad815 434 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 435
16980d0b
JB		 436 %<bitfield>'c print specified char iff bitfield is all ones
437 %<bitfield>`c print specified char iff bitfield is all zeroes
438 %<bitfield>?ab... select from array of values in big endian order
43e65147 439
2fbad815 440 %L print as an iWMMXt N/M width field.
4a5329c6 441 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 442 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 443 versions.
444 %i print 5-bit immediate in bits 8,3..0
445 (print "32" when 0)
fe56b6ce 446 %r print register offset address for wldt/wstr instruction. */
2fbad815 447
21d799b5 448enum opcode_sentinel_enum
05413229
NC		 449{
450 SENTINEL_IWMMXT_START = 1,
451 SENTINEL_IWMMXT_END,
452 SENTINEL_GENERIC_START
453} opcode_sentinels;
454
aefd8a40 455#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 456#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
457#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 458#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 459
8f06b2d8 460/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 461
6b0dd094 462static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 463{
2fbad815 464 /* XScale instructions. */
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 466 0x0e200010, 0x0fff0ff0,
467 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 469 0x0e280010, 0x0fff0ff0,
470 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 472 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 474 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 476 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 477
2fbad815 478 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 479 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 481 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 483 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 485 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 487 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 489 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 491 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 493 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 495 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 497 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 499 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 501 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 503 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 505 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 507 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 509 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 511 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 513 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 515 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 517 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 519 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 521 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 523 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 525 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 527 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 528 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 529 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 531 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 533 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 535 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 537 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 538 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 539 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 541 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 542 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 543 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 545 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 547 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 549 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 551 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 553 0x0e800120, 0x0f800ff0,
554 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 556 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 560 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 562 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 564 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 568 0x0e8000a0, 0x0f800ff0,
569 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 571 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 573 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 575 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 577 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 579 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 581 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 583 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 585 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 587 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 589 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 591 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 593 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 595 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 597 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 599 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 601 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 603 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 605 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 607 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 609 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 611 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 613 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 615 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 617 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 619 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 621 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 623 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 625 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 627 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 629 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 633 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 634
fe56b6ce 635 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 637 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 639 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 641 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 643 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 645 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 647 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 649 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 651 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 653 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 655 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 657 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 659 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 661 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 663 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 665 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 667 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 669 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 671 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 673 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 675 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 677 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 679 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 681 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 683 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 685 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 687 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 689 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 691 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 693 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 695 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 697 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 699 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 701 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 703 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 705 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 707 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 709 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 711 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 713 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 715 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 717 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 719 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 721 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 722
efd6b359
AV		 723 /* Armv8.1-M Mainline instructions. */
724 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
725 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
726 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
727 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
728
16a1fa25 729 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 730 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 731 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 732 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 733 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
734
fe56b6ce 735 /* Register load/store. */
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 737 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 739 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 741 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 743 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 745 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 747 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 749 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 751 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 753 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 755 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 757 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 759 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 761 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 763 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 765 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 767 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 768 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
769 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
770 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
771 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 772
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 774 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 776 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 778 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 780 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 781
fe56b6ce 782 /* Data transfer between ARM and NEON registers. */
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 784 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 786 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 788 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 790 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 792 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 794 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 796 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 798 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 799 /* Half-precision conversion instructions. */
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 801 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 803 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 805 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 807 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 808
fe56b6ce 809 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 811 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
ba6cd17f 812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 813 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 814 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
815 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 817 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 819 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 821 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 823 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 825 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 827 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
ba6cd17f
SD		 828 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
829 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
830 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
831 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
832 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
833 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
834 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
835 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 839 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
ba6cd17f 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 841 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 842 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
843 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 845 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 847 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 849 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 851 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 853 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 855 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
ba6cd17f
SD		 856 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
857 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
858 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
859 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
860 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
861 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
862 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
863 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 865 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 867 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 869 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 871 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 873 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 875 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 877 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 879 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 881 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 883 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 885 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 887 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 889 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 891 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 893 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 895 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 897 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 899 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 901 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 903 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 905 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 907 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 909 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 911 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 913 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 915 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 917 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 919 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 921 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 923 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 925 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 927 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 929 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 931 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 933 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 935 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 937 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 939 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 941 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 943 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 945 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 947 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 949 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 951 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 953 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 955 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 957 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 959 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 961 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 963 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 965 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 966 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 967 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 968
969 /* Cirrus coprocessor instructions. */
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 971 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 973 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 975 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 977 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 979 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 981 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 983 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 985 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 987 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 989 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 991 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 993 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 995 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 997 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 999 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1001 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1003 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1005 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1007 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1009 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1011 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1013 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1015 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1017 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1019 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1021 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1023 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1025 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1027 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1029 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1031 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1033 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1035 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1037 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1039 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1041 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1043 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1044 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1045 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1046 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1047 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1049 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1051 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1053 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1055 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1057 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1059 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1061 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1063 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1065 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1067 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1069 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1071 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1073 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1075 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1077 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1079 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1081 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1083 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1085 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1087 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1089 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1091 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1093 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1095 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1097 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1099 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1101 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1103 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1105 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1107 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1109 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1111 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1112 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1113 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1114 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1115 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1117 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1118 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1119 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1120 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1121 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1122 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1123 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1124 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1125 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1126 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1127 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1128 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1129 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1130 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1131 0x0e000600, 0x0ff00f10,
1132 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1134 0x0e100600, 0x0ff00f10,
1135 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1136 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1137 0x0e200600, 0x0ff00f10,
1138 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1140 0x0e300600, 0x0ff00f10,
1141 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1142
62f3b8c8 1143 /* VFP Fused multiply add instructions. */
6b0dd094 1144 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1145 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1146 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1147 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1148 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1149 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1150 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1151 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1152 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1153 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1154 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1155 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1156 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1157 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1158 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1159 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1160
33399f07 1161 /* FP v5. */
6b0dd094 1162 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1163 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1164 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1165 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1166 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1167 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1168 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1169 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1170 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1171 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1172 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1173 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1174 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1175 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1176 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1177 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1178 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1179 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1180 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1181 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1182 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1183 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1184 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1185 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1186
05413229 1187 /* Generic coprocessor instructions. */
6b0dd094
AV		 1188 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1189 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1190 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1191 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1192 0x0c500000, 0x0ff00000,
1193 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1195 0x0e000000, 0x0f000010,
1196 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1197 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1198 0x0e10f010, 0x0f10f010,
1199 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1201 0x0e100010, 0x0f100010,
1202 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1203 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1204 0x0e000010, 0x0f100010,
1205 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1207 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1209 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1210
05413229 1211 /* V6 coprocessor instructions. */
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1213 0xfc500000, 0xfff00000,
1214 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1215 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1216 0xfc400000, 0xfff00000,
1217 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1218
c28eeff2 1219 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1220 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1221 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1223 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1225 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1227 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1229 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1231 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1233 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1235 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1237 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1238 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1239 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1240
c604a79a 1241 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1242 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1243 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1244 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1245 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1246
dec41383 1247 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1249 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1251 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1253 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1255 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1257 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1259 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1261 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1263 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1264
05413229 1265 /* V5 coprocessor instructions. */
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1267 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1269 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1271 0xfe000000, 0xff000010,
1272 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1273 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1274 0xfe000010, 0xff100010,
1275 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1277 0xfe100010, 0xff100010,
1278 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1279
b0c11777
RL		 1280 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1281 cp_num: bit <11:8> == 0b1001.
1282 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1284 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1286 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1288 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1289 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1290 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1292 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1293 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1294 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1295 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1296 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1297 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1298 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1299 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1300 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1302 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1304 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1306 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1307 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1308 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1310 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1311 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1312 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1313 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1314 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1315 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1316 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1317 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1318 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1319 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1320 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1321 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1322 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1323 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1324 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1325 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1326 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1327 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1328 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1329 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1330 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1331 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1332 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1333 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1334 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1335 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1336 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1337 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1338 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1339 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1340 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1341 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1342 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1343 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1344 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1345 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1346 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1347 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1348 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1349 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1350 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1351 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1352 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1353
49e8a725 1354 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1355 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1356 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1357
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1359};
1360
16980d0b
JB		 1361/* Neon opcode table: This does not encode the top byte -- that is
1362 checked by the print_insn_neon routine, as it depends on whether we are
1363 doing thumb32 or arm32 disassembly. */
1364
1365/* print_insn_neon recognizes the following format control codes:
1366
1367 %% %
1368
c22aaad1 1369 %c print condition code
e2efe87d
MGD		 1370 %u print condition code (unconditional in ARM mode,
1371 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1372 %A print v{st,ld}[1234] operands
1373 %B print v{st,ld}[1234] any one operands
1374 %C print v{st,ld}[1234] single->all operands
1375 %D print scalar
1376 %E print vmov, vmvn, vorr, vbic encoded constant
1377 %F print vtbl,vtbx register list
1378
1379 %<bitfield>r print as an ARM register
1380 %<bitfield>d print the bitfield in decimal
1381 %<bitfield>e print the 2^N - bitfield in decimal
1382 %<bitfield>D print as a NEON D register
1383 %<bitfield>Q print as a NEON Q register
1384 %<bitfield>R print as a NEON D or Q register
1385 %<bitfield>Sn print byte scaled width limited by n
1386 %<bitfield>Tn print short scaled width limited by n
1387 %<bitfield>Un print long scaled width limited by n
43e65147 1388
16980d0b
JB		 1389 %<bitfield>'c print specified char iff bitfield is all ones
1390 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1391 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1392
1393static const struct opcode32 neon_opcodes[] =
1394{
fe56b6ce 1395 /* Extract. */
823d2571
TG		 1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2b00840, 0xffb00850,
1398 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2b00000, 0xffb00810,
1401 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1402
9743db03
AV		 1403 /* Data transfer between ARM and NEON registers. */
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1416
fe56b6ce 1417 /* Move data element to all lanes. */
823d2571
TG		 1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1424
fe56b6ce 1425 /* Table lookup. */
823d2571
TG		 1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1430
8e79c3df 1431 /* Half-precision conversions. */
823d2571
TG		 1432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1433 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1435 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1436
1437 /* NEON fused multiply add instructions. */
823d2571 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1439 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1441 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1443 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1445 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1446
fe56b6ce 1447 /* Two registers, miscellaneous. */
823d2571
TG		 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1449 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1451 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1453 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1455 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1456 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1457 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1458 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1459 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1460 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1461 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1462 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1463 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1464 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1465 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1467 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1469 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf3b20300, 0xffb30fd0,
1492 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1496 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1500 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1540 0xf3bb0600, 0xffbf0e10,
823d2571 1541 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1543 0xf3b70600, 0xffbf0e10,
1544 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1545
fe56b6ce 1546 /* Three registers of the same length. */
823d2571
TG		 1547 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1548 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1549 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1551 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1552 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1553 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1554 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1556 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1558 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1560 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1562 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1564 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1566 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1568 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1586 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1588 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1590 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1592 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1594 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1596 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1598 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1600 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1602 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1604 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1606 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1608 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1610 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1612 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1614 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1616 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1618 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1620 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1622 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1624 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1626 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1628 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1630 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1632 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1634 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1636 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1638 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1640 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1642 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1644 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1646 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1648 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1650 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1652 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1654 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1656 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf2000b00, 0xff800f10,
1665 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf2000b10, 0xff800f10,
1668 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf3000b00, 0xff800f10,
1677 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2000000, 0xfe800f10,
1680 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2000010, 0xfe800f10,
1683 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000100, 0xfe800f10,
1686 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf2000200, 0xfe800f10,
1689 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2000210, 0xfe800f10,
1692 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2000300, 0xfe800f10,
1695 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2000310, 0xfe800f10,
1698 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf2000400, 0xfe800f10,
1701 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2000410, 0xfe800f10,
1704 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2000500, 0xfe800f10,
1707 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2000510, 0xfe800f10,
1710 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2000600, 0xfe800f10,
1713 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2000610, 0xfe800f10,
1716 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2000700, 0xfe800f10,
1719 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2000710, 0xfe800f10,
1722 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf2000910, 0xfe800f10,
1725 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2000a00, 0xfe800f10,
1728 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2000a10, 0xfe800f10,
1731 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1733 0xf3000b10, 0xff800f10,
1734 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1736 0xf3000c10, 0xff800f10,
1737 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1738
fe56b6ce 1739 /* One register and an immediate value. */
823d2571
TG		 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1766
fe56b6ce 1767 /* Two registers and a shift amount. */
823d2571
TG		 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2880950, 0xfeb80fd0,
1780 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2900950, 0xfeb00fd0,
1803 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2a00950, 0xfea00fd0,
1848 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2a00e10, 0xfea00e90,
1887 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1889 0xf2a00c10, 0xfea00e90,
1890 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1891
fe56b6ce 1892 /* Three registers of different lengths. */
823d2571
TG		 1893 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1894 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf2800400, 0xff800f50,
1899 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2800600, 0xff800f50,
1902 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2800900, 0xff800f50,
1905 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf2800b00, 0xff800f50,
1908 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf2800d00, 0xff800f50,
1911 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf3800400, 0xff800f50,
1914 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf3800600, 0xff800f50,
1917 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf2800000, 0xfe800f50,
1920 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf2800100, 0xfe800f50,
1923 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2800200, 0xfe800f50,
1926 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2800300, 0xfe800f50,
1929 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf2800500, 0xfe800f50,
1932 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2800700, 0xfe800f50,
1935 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2800800, 0xfe800f50,
1938 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf2800a00, 0xfe800f50,
1941 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf2800c00, 0xfe800f50,
1944 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1945
fe56b6ce 1946 /* Two registers and a scalar. */
823d2571
TG		 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1950 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1951 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1952 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1958 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1959 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1960 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1966 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1967 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1968 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1978 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1979 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1980 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1984 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1985 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1986 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1990 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1991 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1992 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1994 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998 0xf2800240, 0xfe800f50,
1999 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2800640, 0xfe800f50,
2002 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf2800a40, 0xfe800f50,
2005 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2007 0xf2800e40, 0xff800f50,
2008 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2010 0xf2800f40, 0xff800f50,
2011 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2013 0xf3800e40, 0xff800f50,
2014 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2016 0xf3800f40, 0xff800f50,
2017 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2018 },
16980d0b 2019
fe56b6ce 2020 /* Element and structure load/store. */
823d2571
TG		 2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2024 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2026 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2032 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2038 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2044 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2048 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2050 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2054 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2056 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2059
2060 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2061};
2062
73cd51e5
AV		 2063/* mve opcode table. */
2064
2065/* print_insn_mve recognizes the following format control codes:
2066
2067 %% %
2068
ef1576a1
AV		 2069 %a print '+' or '-' or imm offset in vldr[bhwd] and
2070 vstr[bhwd]
9743db03 2071 %c print condition code
aef6d006
AV		 2072 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2073 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2074 %i print MVE predicate(s) for vpt and vpst
23d00a41 2075 %j print a 5-bit immediate from hw2[14:12,7:6]
bf0b396d 2076 %m print rounding mode for vcvt and vrint
143275ea 2077 %n print vector comparison code for predicated instruction
bf0b396d 2078 %s print size for various vcvt instructions
143275ea
AV		 2079 %v print vector predicate for instruction in predicated
2080 block
ef1576a1 2081 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2082 %w print writeback mode for MVE v{st,ld}[24]
2083 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2084 %E print vmov, vmvn, vorr, vbic encoded constant
2085 %N print generic index for vmov
14925797 2086 %T print bottom ('b') or top ('t') of source register
d3b63143 2087 %X print exchange field in vmla* instructions
04d54ace 2088
9743db03 2089 %<bitfield>r print as an ARM register
04d54ace 2090 %<bitfield>d print the bitfield in decimal
d3b63143 2091 %<bitfield>A print accumulate or not
e39c1607
SD		 2092 %<bitfield>c print bitfield as a condition code
2093 %<bitfield>C print bitfield as an inverted condition code
143275ea 2094 %<bitfield>Q print as a MVE Q register
c507f10b 2095 %<bitfield>F print as a MVE S register
143275ea
AV		 2096 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2097 UNPREDICTABLE
23d00a41
SD		 2098
2099 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2100 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2101 %<bitfield>I print carry flag or not
ef1576a1 2102 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2103 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2104 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2105 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2106 %<bitfield>o print rotate value for vcmul
1c8f2df8 2107 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2108 %<bitfield>x print the bitfield in hex.
1c8f2df8 2109 */
73cd51e5
AV		 2110
2111static const struct mopcode32 mve_opcodes[] =
2112{
143275ea
AV		 2113 /* MVE. */
2114
2115 {ARM_FEATURE_COPROC (FPU_MVE),
2116 MVE_VPST,
2117 0xfe310f4d, 0xffbf1fff,
2118 "vpst%i"
2119 },
2120
2121 /* Floating point VPT T1. */
2122 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2123 MVE_VPT_FP_T1,
2124 0xee310f00, 0xefb10f50,
2125 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2126 /* Floating point VPT T2. */
2127 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2128 MVE_VPT_FP_T2,
2129 0xee310f40, 0xefb10f50,
2130 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2131
2132 /* Vector VPT T1. */
2133 {ARM_FEATURE_COPROC (FPU_MVE),
2134 MVE_VPT_VEC_T1,
2135 0xfe010f00, 0xff811f51,
2136 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2137 /* Vector VPT T2. */
2138 {ARM_FEATURE_COPROC (FPU_MVE),
2139 MVE_VPT_VEC_T2,
2140 0xfe010f01, 0xff811f51,
2141 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2142 /* Vector VPT T3. */
2143 {ARM_FEATURE_COPROC (FPU_MVE),
2144 MVE_VPT_VEC_T3,
2145 0xfe011f00, 0xff811f50,
2146 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2147 /* Vector VPT T4. */
2148 {ARM_FEATURE_COPROC (FPU_MVE),
2149 MVE_VPT_VEC_T4,
2150 0xfe010f40, 0xff811f70,
2151 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2152 /* Vector VPT T5. */
2153 {ARM_FEATURE_COPROC (FPU_MVE),
2154 MVE_VPT_VEC_T5,
2155 0xfe010f60, 0xff811f70,
2156 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2157 /* Vector VPT T6. */
2158 {ARM_FEATURE_COPROC (FPU_MVE),
2159 MVE_VPT_VEC_T6,
2160 0xfe011f40, 0xff811f50,
2161 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2162
c507f10b
AV		 2163 /* Vector VBIC immediate. */
2164 {ARM_FEATURE_COPROC (FPU_MVE),
2165 MVE_VBIC_IMM,
2166 0xef800070, 0xefb81070,
2167 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2168
2169 /* Vector VBIC register. */
2170 {ARM_FEATURE_COPROC (FPU_MVE),
2171 MVE_VBIC_REG,
2172 0xef100150, 0xffb11f51,
2173 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2174
66dcaa5d
AV		 2175 /* Vector VABAV. */
2176 {ARM_FEATURE_COPROC (FPU_MVE),
2177 MVE_VABAV,
2178 0xee800f01, 0xefc10f51,
2179 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2180
2181 /* Vector VABD floating point. */
2182 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2183 MVE_VABD_FP,
2184 0xff200d40, 0xffa11f51,
2185 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2186
2187 /* Vector VABD. */
2188 {ARM_FEATURE_COPROC (FPU_MVE),
2189 MVE_VABD_VEC,
2190 0xef000740, 0xef811f51,
2191 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2192
2193 /* Vector VABS floating point. */
2194 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2195 MVE_VABS_FP,
2196 0xFFB10740, 0xFFB31FD1,
2197 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2198 /* Vector VABS. */
2199 {ARM_FEATURE_COPROC (FPU_MVE),
2200 MVE_VABS_VEC,
2201 0xffb10340, 0xffb31fd1,
2202 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2203
2204 /* Vector VADD floating point T1. */
2205 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2206 MVE_VADD_FP_T1,
2207 0xef000d40, 0xffa11f51,
2208 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2209 /* Vector VADD floating point T2. */
2210 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2211 MVE_VADD_FP_T2,
2212 0xee300f40, 0xefb11f70,
2213 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2214 /* Vector VADD T1. */
2215 {ARM_FEATURE_COPROC (FPU_MVE),
2216 MVE_VADD_VEC_T1,
2217 0xef000840, 0xff811f51,
2218 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2219 /* Vector VADD T2. */
2220 {ARM_FEATURE_COPROC (FPU_MVE),
2221 MVE_VADD_VEC_T2,
2222 0xee010f40, 0xff811f70,
2223 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2224
d3b63143
AV		 2225 /* Vector VADDLV. */
2226 {ARM_FEATURE_COPROC (FPU_MVE),
2227 MVE_VADDLV,
2228 0xee890f00, 0xef8f1fd1,
2229 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2230
2231 /* Vector VADDV. */
2232 {ARM_FEATURE_COPROC (FPU_MVE),
2233 MVE_VADDV,
2234 0xeef10f00, 0xeff31fd1,
2235 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2236
66dcaa5d
AV		 2237 /* Vector VADC. */
2238 {ARM_FEATURE_COPROC (FPU_MVE),
2239 MVE_VADC,
2240 0xee300f00, 0xffb10f51,
2241 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2242
e523f101
AV		 2243 /* Vector VAND. */
2244 {ARM_FEATURE_COPROC (FPU_MVE),
2245 MVE_VAND,
2246 0xef000150, 0xffb11f51,
2247 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2248
2249 /* Vector VBRSR register. */
2250 {ARM_FEATURE_COPROC (FPU_MVE),
2251 MVE_VBRSR,
2252 0xfe011e60, 0xff811f70,
2253 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2254
897b9bbc
AV		 2255 /* Vector VCADD floating point. */
2256 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2257 MVE_VCADD_FP,
2258 0xfc800840, 0xfea11f51,
2259 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2260
2261 /* Vector VCADD. */
2262 {ARM_FEATURE_COPROC (FPU_MVE),
2263 MVE_VCADD_VEC,
2264 0xfe000f00, 0xff810f51,
2265 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2266
e523f101
AV		 2267 /* Vector VCLS. */
2268 {ARM_FEATURE_COPROC (FPU_MVE),
2269 MVE_VCLS,
2270 0xffb00440, 0xffb31fd1,
2271 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2272
2273 /* Vector VCLZ. */
2274 {ARM_FEATURE_COPROC (FPU_MVE),
2275 MVE_VCLZ,
2276 0xffb004c0, 0xffb31fd1,
2277 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2278
897b9bbc
AV		 2279 /* Vector VCMLA. */
2280 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2281 MVE_VCMLA_FP,
2282 0xfc200840, 0xfe211f51,
2283 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2284
143275ea
AV		 2285 /* Vector VCMP floating point T1. */
2286 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2287 MVE_VCMP_FP_T1,
2288 0xee310f00, 0xeff1ef50,
2289 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2290
2291 /* Vector VCMP floating point T2. */
2292 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2293 MVE_VCMP_FP_T2,
2294 0xee310f40, 0xeff1ef50,
2295 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2296
2297 /* Vector VCMP T1. */
2298 {ARM_FEATURE_COPROC (FPU_MVE),
2299 MVE_VCMP_VEC_T1,
2300 0xfe010f00, 0xffc1ff51,
2301 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2302 /* Vector VCMP T2. */
2303 {ARM_FEATURE_COPROC (FPU_MVE),
2304 MVE_VCMP_VEC_T2,
2305 0xfe010f01, 0xffc1ff51,
2306 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2307 /* Vector VCMP T3. */
2308 {ARM_FEATURE_COPROC (FPU_MVE),
2309 MVE_VCMP_VEC_T3,
2310 0xfe011f00, 0xffc1ff50,
2311 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2312 /* Vector VCMP T4. */
2313 {ARM_FEATURE_COPROC (FPU_MVE),
2314 MVE_VCMP_VEC_T4,
2315 0xfe010f40, 0xffc1ff70,
2316 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2317 /* Vector VCMP T5. */
2318 {ARM_FEATURE_COPROC (FPU_MVE),
2319 MVE_VCMP_VEC_T5,
2320 0xfe010f60, 0xffc1ff70,
2321 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2322 /* Vector VCMP T6. */
2323 {ARM_FEATURE_COPROC (FPU_MVE),
2324 MVE_VCMP_VEC_T6,
2325 0xfe011f40, 0xffc1ff50,
2326 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2327
9743db03
AV		 2328 /* Vector VDUP. */
2329 {ARM_FEATURE_COPROC (FPU_MVE),
2330 MVE_VDUP,
2331 0xeea00b10, 0xffb10f5f,
2332 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2333
2334 /* Vector VEOR. */
2335 {ARM_FEATURE_COPROC (FPU_MVE),
2336 MVE_VEOR,
2337 0xff000150, 0xffd11f51,
2338 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2339
2340 /* Vector VFMA, vector * scalar. */
2341 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2342 MVE_VFMA_FP_SCALAR,
2343 0xee310e40, 0xefb11f70,
2344 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2345
2346 /* Vector VFMA floating point. */
2347 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2348 MVE_VFMA_FP,
2349 0xef000c50, 0xffa11f51,
2350 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2351
2352 /* Vector VFMS floating point. */
2353 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2354 MVE_VFMS_FP,
2355 0xef200c50, 0xffa11f51,
2356 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2357
2358 /* Vector VFMAS, vector * scalar. */
2359 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2360 MVE_VFMAS_FP_SCALAR,
2361 0xee311e40, 0xefb11f70,
2362 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2363
2364 /* Vector VHADD T1. */
2365 {ARM_FEATURE_COPROC (FPU_MVE),
2366 MVE_VHADD_T1,
2367 0xef000040, 0xef811f51,
2368 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2369
2370 /* Vector VHADD T2. */
2371 {ARM_FEATURE_COPROC (FPU_MVE),
2372 MVE_VHADD_T2,
2373 0xee000f40, 0xef811f70,
2374 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2375
2376 /* Vector VHSUB T1. */
2377 {ARM_FEATURE_COPROC (FPU_MVE),
2378 MVE_VHSUB_T1,
2379 0xef000240, 0xef811f51,
2380 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2381
2382 /* Vector VHSUB T2. */
2383 {ARM_FEATURE_COPROC (FPU_MVE),
2384 MVE_VHSUB_T2,
2385 0xee001f40, 0xef811f70,
2386 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2387
897b9bbc
AV		 2388 /* Vector VCMUL. */
2389 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2390 MVE_VCMUL_FP,
2391 0xee300e00, 0xefb10f50,
2392 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2393
e523f101
AV		 2394 /* Vector VCTP. */
2395 {ARM_FEATURE_COPROC (FPU_MVE),
2396 MVE_VCTP,
2397 0xf000e801, 0xffc0ffff,
2398 "vctp%v.%20-21s\t%16-19r"},
2399
9743db03
AV		 2400 /* Vector VDUP. */
2401 {ARM_FEATURE_COPROC (FPU_MVE),
2402 MVE_VDUP,
2403 0xeea00b10, 0xffb10f5f,
2404 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2405
2406 /* Vector VRHADD. */
2407 {ARM_FEATURE_COPROC (FPU_MVE),
2408 MVE_VRHADD,
2409 0xef000140, 0xef811f51,
2410 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2411
bf0b396d
AV		 2412 /* Vector VCVT. */
2413 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2414 MVE_VCVT_FP_FIX_VEC,
2415 0xef800c50, 0xef801cd1,
2416 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2417
2418 /* Vector VCVT. */
2419 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2420 MVE_VCVT_BETWEEN_FP_INT,
2421 0xffb30640, 0xffb31e51,
2422 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2423
2424 /* Vector VCVT between single and half-precision float, bottom half. */
2425 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2426 MVE_VCVT_FP_HALF_FP,
2427 0xee3f0e01, 0xefbf1fd1,
2428 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2429
2430 /* Vector VCVT between single and half-precision float, top half. */
2431 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2432 MVE_VCVT_FP_HALF_FP,
2433 0xee3f1e01, 0xefbf1fd1,
2434 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2435
2436 /* Vector VCVT. */
2437 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2438 MVE_VCVT_FROM_FP_TO_INT,
2439 0xffb30040, 0xffb31c51,
2440 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2441
1c8f2df8
AV		 2442 /* Vector VDDUP. */
2443 {ARM_FEATURE_COPROC (FPU_MVE),
2444 MVE_VDDUP,
2445 0xee011f6e, 0xff811f7e,
2446 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2447
2448 /* Vector VDWDUP. */
2449 {ARM_FEATURE_COPROC (FPU_MVE),
2450 MVE_VDWDUP,
2451 0xee011f60, 0xff811f70,
2452 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2453
897b9bbc
AV		 2454 /* Vector VHCADD. */
2455 {ARM_FEATURE_COPROC (FPU_MVE),
2456 MVE_VHCADD,
2457 0xee000f00, 0xff810f51,
2458 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2459
1c8f2df8
AV		 2460 /* Vector VIWDUP. */
2461 {ARM_FEATURE_COPROC (FPU_MVE),
2462 MVE_VIWDUP,
2463 0xee010f60, 0xff811f70,
2464 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2465
2466 /* Vector VIDUP. */
2467 {ARM_FEATURE_COPROC (FPU_MVE),
2468 MVE_VIDUP,
2469 0xee010f6e, 0xff811f7e,
2470 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2471
04d54ace
AV		 2472 /* Vector VLD2. */
2473 {ARM_FEATURE_COPROC (FPU_MVE),
2474 MVE_VLD2,
2475 0xfc901e00, 0xff901e5f,
2476 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2477
2478 /* Vector VLD4. */
2479 {ARM_FEATURE_COPROC (FPU_MVE),
2480 MVE_VLD4,
2481 0xfc901e01, 0xff901e1f,
2482 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2483
ef1576a1
AV		 2484 /* Vector VLDRB gather load. */
2485 {ARM_FEATURE_COPROC (FPU_MVE),
2486 MVE_VLDRB_GATHER_T1,
2487 0xec900e00, 0xefb01e50,
2488 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2489
2490 /* Vector VLDRH gather load. */
2491 {ARM_FEATURE_COPROC (FPU_MVE),
2492 MVE_VLDRH_GATHER_T2,
2493 0xec900e10, 0xefb01e50,
2494 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2495
2496 /* Vector VLDRW gather load. */
2497 {ARM_FEATURE_COPROC (FPU_MVE),
2498 MVE_VLDRW_GATHER_T3,
2499 0xfc900f40, 0xffb01fd0,
2500 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2501
2502 /* Vector VLDRD gather load. */
2503 {ARM_FEATURE_COPROC (FPU_MVE),
2504 MVE_VLDRD_GATHER_T4,
2505 0xec900fd0, 0xefb01fd0,
2506 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2507
2508 /* Vector VLDRW gather load. */
2509 {ARM_FEATURE_COPROC (FPU_MVE),
2510 MVE_VLDRW_GATHER_T5,
2511 0xfd101e00, 0xff111f00,
2512 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2513
2514 /* Vector VLDRD gather load, variant T6. */
2515 {ARM_FEATURE_COPROC (FPU_MVE),
2516 MVE_VLDRD_GATHER_T6,
2517 0xfd101f00, 0xff111f00,
2518 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2519
aef6d006
AV		 2520 /* Vector VLDRB. */
2521 {ARM_FEATURE_COPROC (FPU_MVE),
2522 MVE_VLDRB_T1,
2523 0xec100e00, 0xee581e00,
2524 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2525
2526 /* Vector VLDRH. */
2527 {ARM_FEATURE_COPROC (FPU_MVE),
2528 MVE_VLDRH_T2,
2529 0xec180e00, 0xee581e00,
2530 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2531
2532 /* Vector VLDRB unsigned, variant T5. */
2533 {ARM_FEATURE_COPROC (FPU_MVE),
2534 MVE_VLDRB_T5,
2535 0xec101e00, 0xfe101f80,
2536 "vldrb%v.u8\t%13-15,22Q, %d"},
2537
2538 /* Vector VLDRH unsigned, variant T6. */
2539 {ARM_FEATURE_COPROC (FPU_MVE),
2540 MVE_VLDRH_T6,
2541 0xec101e80, 0xfe101f80,
2542 "vldrh%v.u16\t%13-15,22Q, %d"},
2543
2544 /* Vector VLDRW unsigned, variant T7. */
2545 {ARM_FEATURE_COPROC (FPU_MVE),
2546 MVE_VLDRW_T7,
2547 0xec101f00, 0xfe101f80,
2548 "vldrw%v.u32\t%13-15,22Q, %d"},
2549
56858bea
AV		 2550 /* Vector VMAX. */
2551 {ARM_FEATURE_COPROC (FPU_MVE),
2552 MVE_VMAX,
2553 0xef000640, 0xef811f51,
2554 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2555
2556 /* Vector VMAXA. */
2557 {ARM_FEATURE_COPROC (FPU_MVE),
2558 MVE_VMAXA,
2559 0xee330e81, 0xffb31fd1,
2560 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2561
2562 /* Vector VMAXNM floating point. */
2563 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2564 MVE_VMAXNM_FP,
2565 0xff000f50, 0xffa11f51,
2566 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2567
2568 /* Vector VMAXNMA floating point. */
2569 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2570 MVE_VMAXNMA_FP,
2571 0xee3f0e81, 0xefbf1fd1,
2572 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2573
2574 /* Vector VMAXNMV floating point. */
2575 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2576 MVE_VMAXNMV_FP,
2577 0xeeee0f00, 0xefff0fd1,
2578 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2579
2580 /* Vector VMAXNMAV floating point. */
2581 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2582 MVE_VMAXNMAV_FP,
2583 0xeeec0f00, 0xefff0fd1,
2584 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2585
2586 /* Vector VMAXV. */
2587 {ARM_FEATURE_COPROC (FPU_MVE),
2588 MVE_VMAXV,
2589 0xeee20f00, 0xeff30fd1,
2590 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2591
2592 /* Vector VMAXAV. */
2593 {ARM_FEATURE_COPROC (FPU_MVE),
2594 MVE_VMAXAV,
2595 0xeee00f00, 0xfff30fd1,
2596 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2597
2598 /* Vector VMIN. */
2599 {ARM_FEATURE_COPROC (FPU_MVE),
2600 MVE_VMIN,
2601 0xef000650, 0xef811f51,
2602 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2603
2604 /* Vector VMINA. */
2605 {ARM_FEATURE_COPROC (FPU_MVE),
2606 MVE_VMINA,
2607 0xee331e81, 0xffb31fd1,
2608 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2609
2610 /* Vector VMINNM floating point. */
2611 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2612 MVE_VMINNM_FP,
2613 0xff200f50, 0xffa11f51,
2614 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2615
2616 /* Vector VMINNMA floating point. */
2617 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2618 MVE_VMINNMA_FP,
2619 0xee3f1e81, 0xefbf1fd1,
2620 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2621
2622 /* Vector VMINNMV floating point. */
2623 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2624 MVE_VMINNMV_FP,
2625 0xeeee0f80, 0xefff0fd1,
2626 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2627
2628 /* Vector VMINNMAV floating point. */
2629 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2630 MVE_VMINNMAV_FP,
2631 0xeeec0f80, 0xefff0fd1,
2632 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2633
2634 /* Vector VMINV. */
2635 {ARM_FEATURE_COPROC (FPU_MVE),
2636 MVE_VMINV,
2637 0xeee20f80, 0xeff30fd1,
2638 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2639
2640 /* Vector VMINAV. */
2641 {ARM_FEATURE_COPROC (FPU_MVE),
2642 MVE_VMINAV,
2643 0xeee00f80, 0xfff30fd1,
2644 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2645
2646 /* Vector VMLA. */
2647 {ARM_FEATURE_COPROC (FPU_MVE),
2648 MVE_VMLA,
2649 0xee010e40, 0xef811f70,
2650 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2651
d3b63143
AV		 2652 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2653 opcode aliasing. */
2654 {ARM_FEATURE_COPROC (FPU_MVE),
2655 MVE_VMLALDAV,
2656 0xee801e00, 0xef801f51,
2657 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2658
2659 {ARM_FEATURE_COPROC (FPU_MVE),
2660 MVE_VMLALDAV,
2661 0xee800e00, 0xef801f51,
2662 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2663
2664 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2665 {ARM_FEATURE_COPROC (FPU_MVE),
2666 MVE_VMLADAV_T1,
2667 0xeef00e00, 0xeff01f51,
2668 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2669
2670 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2671 {ARM_FEATURE_COPROC (FPU_MVE),
2672 MVE_VMLADAV_T2,
2673 0xeef00f00, 0xeff11f51,
2674 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2675
2676 /* Vector VMLADAV T1 variant. */
2677 {ARM_FEATURE_COPROC (FPU_MVE),
2678 MVE_VMLADAV_T1,
2679 0xeef01e00, 0xeff01f51,
2680 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2681
2682 /* Vector VMLADAV T2 variant. */
2683 {ARM_FEATURE_COPROC (FPU_MVE),
2684 MVE_VMLADAV_T2,
2685 0xeef01f00, 0xeff11f51,
2686 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2687
2688 /* Vector VMLAS. */
2689 {ARM_FEATURE_COPROC (FPU_MVE),
2690 MVE_VMLAS,
2691 0xee011e40, 0xef811f70,
2692 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2693
2694 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2695 opcode aliasing. */
2696 {ARM_FEATURE_COPROC (FPU_MVE),
2697 MVE_VRMLSLDAVH,
2698 0xfe800e01, 0xff810f51,
2699 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2700
2701 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2702 opcdoe aliasing. */
2703 {ARM_FEATURE_COPROC (FPU_MVE),
2704 MVE_VMLSLDAV,
2705 0xee800e01, 0xff800f51,
2706 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2707
2708 /* Vector VMLSDAV T1 Variant. */
2709 {ARM_FEATURE_COPROC (FPU_MVE),
2710 MVE_VMLSDAV_T1,
2711 0xeef00e01, 0xfff00f51,
2712 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2713
2714 /* Vector VMLSDAV T2 Variant. */
2715 {ARM_FEATURE_COPROC (FPU_MVE),
2716 MVE_VMLSDAV_T2,
2717 0xfef00e01, 0xfff10f51,
2718 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2719
c507f10b
AV		 2720 /* Vector VMOV between gpr and half precision register, op == 0. */
2721 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2722 MVE_VMOV_HFP_TO_GP,
2723 0xee000910, 0xfff00f7f,
2724 "vmov.f16\t%7,16-19F, %12-15r"},
2725
2726 /* Vector VMOV between gpr and half precision register, op == 1. */
2727 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2728 MVE_VMOV_HFP_TO_GP,
2729 0xee100910, 0xfff00f7f,
2730 "vmov.f16\t%12-15r, %7,16-19F"},
2731
2732 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2733 MVE_VMOV_GP_TO_VEC_LANE,
2734 0xee000b10, 0xff900f1f,
2735 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2736
2737 /* Vector VORR immediate to vector.
2738 NOTE: MVE_VORR_IMM must appear in the table
2739 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2740 {ARM_FEATURE_COPROC (FPU_MVE),
2741 MVE_VORR_IMM,
2742 0xef800050, 0xefb810f0,
2743 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2744
ed63aa17
AV		 2745 /* Vector VQSHL T2 Variant.
2746 NOTE: MVE_VQSHL_T2 must appear in the table before
2747 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2748 {ARM_FEATURE_COPROC (FPU_MVE),
2749 MVE_VQSHL_T2,
2750 0xef800750, 0xef801fd1,
2751 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2752
2753 /* Vector VQSHLU T3 Variant
2754 NOTE: MVE_VQSHL_T2 must appear in the table before
2755 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2756
2757 {ARM_FEATURE_COPROC (FPU_MVE),
2758 MVE_VQSHLU_T3,
2759 0xff800650, 0xff801fd1,
2760 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2761
2762 /* Vector VRSHR
2763 NOTE: MVE_VRSHR must appear in the table before
2764 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2765 {ARM_FEATURE_COPROC (FPU_MVE),
2766 MVE_VRSHR,
2767 0xef800250, 0xef801fd1,
2768 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2769
2770 /* Vector VSHL.
2771 NOTE: MVE_VSHL must appear in the table before
2772 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2773 {ARM_FEATURE_COPROC (FPU_MVE),
2774 MVE_VSHL_T1,
2775 0xef800550, 0xff801fd1,
2776 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2777
2778 /* Vector VSHR
2779 NOTE: MVE_VSHR must appear in the table before
2780 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2781 {ARM_FEATURE_COPROC (FPU_MVE),
2782 MVE_VSHR,
2783 0xef800050, 0xef801fd1,
2784 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2785
2786 /* Vector VSLI
2787 NOTE: MVE_VSLI must appear in the table before
2788 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2789 {ARM_FEATURE_COPROC (FPU_MVE),
2790 MVE_VSLI,
2791 0xff800550, 0xff801fd1,
2792 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2793
2794 /* Vector VSRI
2795 NOTE: MVE_VSRI must appear in the table before
2796 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2797 {ARM_FEATURE_COPROC (FPU_MVE),
2798 MVE_VSRI,
2799 0xff800450, 0xff801fd1,
2800 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2801
c507f10b
AV		 2802 /* Vector VMOV immediate to vector,
2803 cmode == 11x1 -> VMVN which is UNDEFINED
2804 for such a cmode. */
2805 {ARM_FEATURE_COPROC (FPU_MVE),
2806 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2807
2808 /* Vector VMOV immediate to vector. */
2809 {ARM_FEATURE_COPROC (FPU_MVE),
2810 MVE_VMOV_IMM_TO_VEC,
2811 0xef800050, 0xefb810d0,
2812 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2813
2814 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2815 {ARM_FEATURE_COPROC (FPU_MVE),
2816 MVE_VMOV2_VEC_LANE_TO_GP,
2817 0xec000f00, 0xffb01ff0,
2818 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2819
2820 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2821 {ARM_FEATURE_COPROC (FPU_MVE),
2822 MVE_VMOV2_VEC_LANE_TO_GP,
2823 0xec000f10, 0xffb01ff0,
2824 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2825
2826 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2827 {ARM_FEATURE_COPROC (FPU_MVE),
2828 MVE_VMOV2_GP_TO_VEC_LANE,
2829 0xec100f00, 0xffb01ff0,
2830 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2831
2832 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2833 {ARM_FEATURE_COPROC (FPU_MVE),
2834 MVE_VMOV2_GP_TO_VEC_LANE,
2835 0xec100f10, 0xffb01ff0,
2836 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2837
2838 /* Vector VMOV Vector lane to gpr. */
2839 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2840 MVE_VMOV_VEC_LANE_TO_GP,
2841 0xee100b10, 0xff100f1f,
2842 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2843
ed63aa17
AV		 2844 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2845 to instruction opcode aliasing. */
2846 {ARM_FEATURE_COPROC (FPU_MVE),
2847 MVE_VSHLL_T1,
2848 0xeea00f40, 0xefa00fd1,
2849 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2850
14925797
AV		 2851 /* Vector VMOVL long. */
2852 {ARM_FEATURE_COPROC (FPU_MVE),
2853 MVE_VMOVL,
2854 0xeea00f40, 0xefa70fd1,
2855 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2856
2857 /* Vector VMOV and narrow. */
2858 {ARM_FEATURE_COPROC (FPU_MVE),
2859 MVE_VMOVN,
2860 0xfe310e81, 0xffb30fd1,
2861 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2862
c507f10b
AV		 2863 /* Floating point move extract. */
2864 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2865 MVE_VMOVX,
2866 0xfeb00a40, 0xffbf0fd0,
2867 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2868
f49bb598
AV		 2869 /* Vector VMUL floating-point T1 variant. */
2870 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2871 MVE_VMUL_FP_T1,
2872 0xff000d50, 0xffa11f51,
2873 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2874
2875 /* Vector VMUL floating-point T2 variant. */
2876 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2877 MVE_VMUL_FP_T2,
2878 0xee310e60, 0xefb11f70,
2879 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2880
2881 /* Vector VMUL T1 variant. */
2882 {ARM_FEATURE_COPROC (FPU_MVE),
2883 MVE_VMUL_VEC_T1,
2884 0xef000950, 0xff811f51,
2885 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2886
2887 /* Vector VMUL T2 variant. */
2888 {ARM_FEATURE_COPROC (FPU_MVE),
2889 MVE_VMUL_VEC_T2,
2890 0xee011e60, 0xff811f70,
2891 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2892
2893 /* Vector VMULH. */
2894 {ARM_FEATURE_COPROC (FPU_MVE),
2895 MVE_VMULH,
2896 0xee010e01, 0xef811f51,
2897 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2898
2899 /* Vector VRMULH. */
2900 {ARM_FEATURE_COPROC (FPU_MVE),
2901 MVE_VRMULH,
2902 0xee011e01, 0xef811f51,
2903 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2904
14925797
AV		 2905 /* Vector VMULL integer. */
2906 {ARM_FEATURE_COPROC (FPU_MVE),
2907 MVE_VMULL_INT,
2908 0xee010e00, 0xef810f51,
2909 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2910
2911 /* Vector VMULL polynomial. */
2912 {ARM_FEATURE_COPROC (FPU_MVE),
2913 MVE_VMULL_POLY,
2914 0xee310e00, 0xefb10f51,
2915 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2916
c507f10b
AV		 2917 /* Vector VMVN immediate to vector. */
2918 {ARM_FEATURE_COPROC (FPU_MVE),
2919 MVE_VMVN_IMM,
2920 0xef800070, 0xefb810f0,
2921 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2922
2923 /* Vector VMVN register. */
2924 {ARM_FEATURE_COPROC (FPU_MVE),
2925 MVE_VMVN_REG,
2926 0xffb005c0, 0xffbf1fd1,
2927 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2928
f49bb598
AV		 2929 /* Vector VNEG floating point. */
2930 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2931 MVE_VNEG_FP,
2932 0xffb107c0, 0xffb31fd1,
2933 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2934
2935 /* Vector VNEG. */
2936 {ARM_FEATURE_COPROC (FPU_MVE),
2937 MVE_VNEG_VEC,
2938 0xffb103c0, 0xffb31fd1,
2939 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2940
c507f10b
AV		 2941 /* Vector VORN, vector bitwise or not. */
2942 {ARM_FEATURE_COPROC (FPU_MVE),
2943 MVE_VORN,
2944 0xef300150, 0xffb11f51,
2945 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2946
2947 /* Vector VORR register. */
2948 {ARM_FEATURE_COPROC (FPU_MVE),
2949 MVE_VORR_REG,
2950 0xef200150, 0xffb11f51,
2951 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2952
14925797
AV		 2953 /* Vector VQDMULL T1 variant. */
2954 {ARM_FEATURE_COPROC (FPU_MVE),
2955 MVE_VQDMULL_T1,
2956 0xee300f01, 0xefb10f51,
2957 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2958
14b456f2
AV		 2959 /* Vector VPNOT. */
2960 {ARM_FEATURE_COPROC (FPU_MVE),
2961 MVE_VPNOT,
2962 0xfe310f4d, 0xffffffff,
2963 "vpnot%v"},
2964
2965 /* Vector VPSEL. */
2966 {ARM_FEATURE_COPROC (FPU_MVE),
2967 MVE_VPSEL,
2968 0xfe310f01, 0xffb11f51,
2969 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2970
2971 /* Vector VQABS. */
2972 {ARM_FEATURE_COPROC (FPU_MVE),
2973 MVE_VQABS,
2974 0xffb00740, 0xffb31fd1,
2975 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2976
2977 /* Vector VQADD T1 variant. */
2978 {ARM_FEATURE_COPROC (FPU_MVE),
2979 MVE_VQADD_T1,
2980 0xef000050, 0xef811f51,
2981 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2982
2983 /* Vector VQADD T2 variant. */
2984 {ARM_FEATURE_COPROC (FPU_MVE),
2985 MVE_VQADD_T2,
2986 0xee000f60, 0xef811f70,
2987 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2988
14925797
AV		 2989 /* Vector VQDMULL T2 variant. */
2990 {ARM_FEATURE_COPROC (FPU_MVE),
2991 MVE_VQDMULL_T2,
2992 0xee300f60, 0xefb10f70,
2993 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2994
2995 /* Vector VQMOVN. */
2996 {ARM_FEATURE_COPROC (FPU_MVE),
2997 MVE_VQMOVN,
2998 0xee330e01, 0xefb30fd1,
2999 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3000
3001 /* Vector VQMOVUN. */
3002 {ARM_FEATURE_COPROC (FPU_MVE),
3003 MVE_VQMOVUN,
3004 0xee310e81, 0xffb30fd1,
3005 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3006
d3b63143
AV		 3007 /* Vector VQDMLADH. */
3008 {ARM_FEATURE_COPROC (FPU_MVE),
3009 MVE_VQDMLADH,
3010 0xee000e00, 0xff810f51,
3011 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3012
3013 /* Vector VQRDMLADH. */
3014 {ARM_FEATURE_COPROC (FPU_MVE),
3015 MVE_VQRDMLADH,
3016 0xee000e01, 0xff810f51,
3017 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3018
3019 /* Vector VQDMLAH. */
3020 {ARM_FEATURE_COPROC (FPU_MVE),
3021 MVE_VQDMLAH,
3022 0xee000e60, 0xef811f70,
3023 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3024
3025 /* Vector VQRDMLAH. */
3026 {ARM_FEATURE_COPROC (FPU_MVE),
3027 MVE_VQRDMLAH,
3028 0xee000e40, 0xef811f70,
3029 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3030
3031 /* Vector VQDMLASH. */
3032 {ARM_FEATURE_COPROC (FPU_MVE),
3033 MVE_VQDMLASH,
3034 0xee001e60, 0xef811f70,
3035 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3036
3037 /* Vector VQRDMLASH. */
3038 {ARM_FEATURE_COPROC (FPU_MVE),
3039 MVE_VQRDMLASH,
3040 0xee001e40, 0xef811f70,
3041 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3042
3043 /* Vector VQDMLSDH. */
3044 {ARM_FEATURE_COPROC (FPU_MVE),
3045 MVE_VQDMLSDH,
3046 0xfe000e00, 0xff810f51,
3047 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3048
3049 /* Vector VQRDMLSDH. */
3050 {ARM_FEATURE_COPROC (FPU_MVE),
3051 MVE_VQRDMLSDH,
3052 0xfe000e01, 0xff810f51,
3053 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3054
3055 /* Vector VQDMULH T1 variant. */
3056 {ARM_FEATURE_COPROC (FPU_MVE),
3057 MVE_VQDMULH_T1,
3058 0xef000b40, 0xff811f51,
3059 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3060
3061 /* Vector VQRDMULH T2 variant. */
3062 {ARM_FEATURE_COPROC (FPU_MVE),
3063 MVE_VQRDMULH_T2,
3064 0xff000b40, 0xff811f51,
3065 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3066
3067 /* Vector VQDMULH T3 variant. */
3068 {ARM_FEATURE_COPROC (FPU_MVE),
3069 MVE_VQDMULH_T3,
3070 0xee010e60, 0xff811f70,
3071 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3072
3073 /* Vector VQRDMULH T4 variant. */
3074 {ARM_FEATURE_COPROC (FPU_MVE),
3075 MVE_VQRDMULH_T4,
3076 0xfe010e60, 0xff811f70,
3077 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3078
14b456f2
AV		 3079 /* Vector VQNEG. */
3080 {ARM_FEATURE_COPROC (FPU_MVE),
3081 MVE_VQNEG,
3082 0xffb007c0, 0xffb31fd1,
3083 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3084
ed63aa17
AV		 3085 /* Vector VQRSHL T1 variant. */
3086 {ARM_FEATURE_COPROC (FPU_MVE),
3087 MVE_VQRSHL_T1,
3088 0xef000550, 0xef811f51,
3089 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3090
3091 /* Vector VQRSHL T2 variant. */
3092 {ARM_FEATURE_COPROC (FPU_MVE),
3093 MVE_VQRSHL_T2,
3094 0xee331ee0, 0xefb31ff0,
3095 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3096
3097 /* Vector VQRSHRN. */
3098 {ARM_FEATURE_COPROC (FPU_MVE),
3099 MVE_VQRSHRN,
3100 0xee800f41, 0xefa00fd1,
3101 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3102
3103 /* Vector VQRSHRUN. */
3104 {ARM_FEATURE_COPROC (FPU_MVE),
3105 MVE_VQRSHRUN,
3106 0xfe800fc0, 0xffa00fd1,
3107 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3108
3109 /* Vector VQSHL T1 Variant. */
3110 {ARM_FEATURE_COPROC (FPU_MVE),
3111 MVE_VQSHL_T1,
3112 0xee311ee0, 0xefb31ff0,
3113 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3114
3115 /* Vector VQSHL T4 Variant. */
3116 {ARM_FEATURE_COPROC (FPU_MVE),
3117 MVE_VQSHL_T4,
3118 0xef000450, 0xef811f51,
3119 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3120
3121 /* Vector VQSHRN. */
3122 {ARM_FEATURE_COPROC (FPU_MVE),
3123 MVE_VQSHRN,
3124 0xee800f40, 0xefa00fd1,
3125 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3126
3127 /* Vector VQSHRUN. */
3128 {ARM_FEATURE_COPROC (FPU_MVE),
3129 MVE_VQSHRUN,
3130 0xee800fc0, 0xffa00fd1,
3131 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3132
14b456f2
AV		 3133 /* Vector VQSUB T1 Variant. */
3134 {ARM_FEATURE_COPROC (FPU_MVE),
3135 MVE_VQSUB_T1,
3136 0xef000250, 0xef811f51,
3137 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3138
3139 /* Vector VQSUB T2 Variant. */
3140 {ARM_FEATURE_COPROC (FPU_MVE),
3141 MVE_VQSUB_T2,
3142 0xee001f60, 0xef811f70,
3143 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3144
3145 /* Vector VREV16. */
3146 {ARM_FEATURE_COPROC (FPU_MVE),
3147 MVE_VREV16,
3148 0xffb00140, 0xffb31fd1,
3149 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3150
3151 /* Vector VREV32. */
3152 {ARM_FEATURE_COPROC (FPU_MVE),
3153 MVE_VREV32,
3154 0xffb000c0, 0xffb31fd1,
3155 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3156
3157 /* Vector VREV64. */
3158 {ARM_FEATURE_COPROC (FPU_MVE),
3159 MVE_VREV64,
3160 0xffb00040, 0xffb31fd1,
3161 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3162
bf0b396d
AV		 3163 /* Vector VRINT floating point. */
3164 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3165 MVE_VRINT_FP,
3166 0xffb20440, 0xffb31c51,
3167 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3168
d3b63143
AV		 3169 /* Vector VRMLALDAVH. */
3170 {ARM_FEATURE_COPROC (FPU_MVE),
3171 MVE_VRMLALDAVH,
3172 0xee800f00, 0xef811f51,
3173 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3174
3175 /* Vector VRMLALDAVH. */
3176 {ARM_FEATURE_COPROC (FPU_MVE),
3177 MVE_VRMLALDAVH,
3178 0xee801f00, 0xef811f51,
3179 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3180
ed63aa17
AV		 3181 /* Vector VRSHL T1 Variant. */
3182 {ARM_FEATURE_COPROC (FPU_MVE),
3183 MVE_VRSHL_T1,
3184 0xef000540, 0xef811f51,
3185 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3186
3187 /* Vector VRSHL T2 Variant. */
3188 {ARM_FEATURE_COPROC (FPU_MVE),
3189 MVE_VRSHL_T2,
3190 0xee331e60, 0xefb31ff0,
3191 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3192
3193 /* Vector VRSHRN. */
3194 {ARM_FEATURE_COPROC (FPU_MVE),
3195 MVE_VRSHRN,
3196 0xfe800fc1, 0xffa00fd1,
3197 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3198
66dcaa5d
AV		 3199 /* Vector VSBC. */
3200 {ARM_FEATURE_COPROC (FPU_MVE),
3201 MVE_VSBC,
3202 0xfe300f00, 0xffb10f51,
3203 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3204
ed63aa17
AV		 3205 /* Vector VSHL T2 Variant. */
3206 {ARM_FEATURE_COPROC (FPU_MVE),
3207 MVE_VSHL_T2,
3208 0xee311e60, 0xefb31ff0,
3209 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3210
3211 /* Vector VSHL T3 Variant. */
3212 {ARM_FEATURE_COPROC (FPU_MVE),
3213 MVE_VSHL_T3,
3214 0xef000440, 0xef811f51,
3215 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3216
3217 /* Vector VSHLC. */
3218 {ARM_FEATURE_COPROC (FPU_MVE),
3219 MVE_VSHLC,
3220 0xeea00fc0, 0xffa01ff0,
3221 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3222
3223 /* Vector VSHLL T2 Variant. */
3224 {ARM_FEATURE_COPROC (FPU_MVE),
3225 MVE_VSHLL_T2,
3226 0xee310e01, 0xefb30fd1,
3227 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3228
3229 /* Vector VSHRN. */
3230 {ARM_FEATURE_COPROC (FPU_MVE),
3231 MVE_VSHRN,
3232 0xee800fc1, 0xffa00fd1,
3233 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3234
04d54ace
AV		 3235 /* Vector VST2 no writeback. */
3236 {ARM_FEATURE_COPROC (FPU_MVE),
3237 MVE_VST2,
3238 0xfc801e00, 0xffb01e5f,
3239 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3240
3241 /* Vector VST2 writeback. */
3242 {ARM_FEATURE_COPROC (FPU_MVE),
3243 MVE_VST2,
3244 0xfca01e00, 0xffb01e5f,
3245 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3246
3247 /* Vector VST4 no writeback. */
3248 {ARM_FEATURE_COPROC (FPU_MVE),
3249 MVE_VST4,
3250 0xfc801e01, 0xffb01e1f,
3251 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3252
3253 /* Vector VST4 writeback. */
3254 {ARM_FEATURE_COPROC (FPU_MVE),
3255 MVE_VST4,
3256 0xfca01e01, 0xffb01e1f,
3257 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3258
ef1576a1
AV		 3259 /* Vector VSTRB scatter store, T1 variant. */
3260 {ARM_FEATURE_COPROC (FPU_MVE),
3261 MVE_VSTRB_SCATTER_T1,
3262 0xec800e00, 0xffb01e50,
3263 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3264
3265 /* Vector VSTRH scatter store, T2 variant. */
3266 {ARM_FEATURE_COPROC (FPU_MVE),
3267 MVE_VSTRH_SCATTER_T2,
3268 0xec800e10, 0xffb01e50,
3269 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3270
3271 /* Vector VSTRW scatter store, T3 variant. */
3272 {ARM_FEATURE_COPROC (FPU_MVE),
3273 MVE_VSTRW_SCATTER_T3,
3274 0xec800e40, 0xffb01e50,
3275 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3276
3277 /* Vector VSTRD scatter store, T4 variant. */
3278 {ARM_FEATURE_COPROC (FPU_MVE),
3279 MVE_VSTRD_SCATTER_T4,
3280 0xec800fd0, 0xffb01fd0,
3281 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3282
3283 /* Vector VSTRW scatter store, T5 variant. */
3284 {ARM_FEATURE_COPROC (FPU_MVE),
3285 MVE_VSTRW_SCATTER_T5,
3286 0xfd001e00, 0xff111f00,
3287 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3288
3289 /* Vector VSTRD scatter store, T6 variant. */
3290 {ARM_FEATURE_COPROC (FPU_MVE),
3291 MVE_VSTRD_SCATTER_T6,
3292 0xfd001f00, 0xff111f00,
3293 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3294
aef6d006
AV		 3295 /* Vector VSTRB. */
3296 {ARM_FEATURE_COPROC (FPU_MVE),
3297 MVE_VSTRB_T1,
3298 0xec000e00, 0xfe581e00,
3299 "vstrb%v.%7-8s\t%13-15Q, %d"},
3300
3301 /* Vector VSTRH. */
3302 {ARM_FEATURE_COPROC (FPU_MVE),
3303 MVE_VSTRH_T2,
3304 0xec080e00, 0xfe581e00,
3305 "vstrh%v.%7-8s\t%13-15Q, %d"},
3306
3307 /* Vector VSTRB variant T5. */
3308 {ARM_FEATURE_COPROC (FPU_MVE),
3309 MVE_VSTRB_T5,
3310 0xec001e00, 0xfe101f80,
3311 "vstrb%v.8\t%13-15,22Q, %d"},
3312
3313 /* Vector VSTRH variant T6. */
3314 {ARM_FEATURE_COPROC (FPU_MVE),
3315 MVE_VSTRH_T6,
3316 0xec001e80, 0xfe101f80,
3317 "vstrh%v.16\t%13-15,22Q, %d"},
3318
3319 /* Vector VSTRW variant T7. */
3320 {ARM_FEATURE_COPROC (FPU_MVE),
3321 MVE_VSTRW_T7,
3322 0xec001f00, 0xfe101f80,
3323 "vstrw%v.32\t%13-15,22Q, %d"},
3324
66dcaa5d
AV		 3325 /* Vector VSUB floating point T1 variant. */
3326 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3327 MVE_VSUB_FP_T1,
3328 0xef200d40, 0xffa11f51,
3329 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3330
3331 /* Vector VSUB floating point T2 variant. */
3332 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3333 MVE_VSUB_FP_T2,
3334 0xee301f40, 0xefb11f70,
3335 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3336
3337 /* Vector VSUB T1 variant. */
3338 {ARM_FEATURE_COPROC (FPU_MVE),
3339 MVE_VSUB_VEC_T1,
3340 0xff000840, 0xff811f51,
3341 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3342
3343 /* Vector VSUB T2 variant. */
3344 {ARM_FEATURE_COPROC (FPU_MVE),
3345 MVE_VSUB_VEC_T2,
3346 0xee011f40, 0xff811f70,
3347 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3348
23d00a41
SD		 3349 {ARM_FEATURE_COPROC (FPU_MVE),
3350 MVE_ASRLI,
3351 0xea50012f, 0xfff1813f,
3352 "asrl%c\t%17-19l, %9-11h, %j"},
3353
3354 {ARM_FEATURE_COPROC (FPU_MVE),
3355 MVE_ASRL,
3356 0xea50012d, 0xfff101ff,
3357 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3358
3359 {ARM_FEATURE_COPROC (FPU_MVE),
3360 MVE_LSLLI,
3361 0xea50010f, 0xfff1813f,
3362 "lsll%c\t%17-19l, %9-11h, %j"},
3363
3364 {ARM_FEATURE_COPROC (FPU_MVE),
3365 MVE_LSLL,
3366 0xea50010d, 0xfff101ff,
3367 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3368
3369 {ARM_FEATURE_COPROC (FPU_MVE),
3370 MVE_LSRL,
3371 0xea50011f, 0xfff1813f,
3372 "lsrl%c\t%17-19l, %9-11h, %j"},
3373
3374 {ARM_FEATURE_COPROC (FPU_MVE),
3375 MVE_SQRSHRL,
3376 0xea51012d, 0xfff101ff,
3377 "sqrshrl%c\t%17-19l, %9-11h, %12-15S"},
3378
3379 {ARM_FEATURE_COPROC (FPU_MVE),
3380 MVE_SQRSHR,
3381 0xea500f2d, 0xfff00fff,
3382 "sqrshr%c\t%16-19S, %12-15S"},
3383
3384 {ARM_FEATURE_COPROC (FPU_MVE),
3385 MVE_SQSHLL,
3386 0xea51013f, 0xfff1813f,
3387 "sqshll%c\t%17-19l, %9-11h, %j"},
3388
3389 {ARM_FEATURE_COPROC (FPU_MVE),
3390 MVE_SQSHL,
3391 0xea500f3f, 0xfff08f3f,
3392 "sqshl%c\t%16-19S, %j"},
3393
3394 {ARM_FEATURE_COPROC (FPU_MVE),
3395 MVE_SRSHRL,
3396 0xea51012f, 0xfff1813f,
3397 "srshrl%c\t%17-19l, %9-11h, %j"},
3398
3399 {ARM_FEATURE_COPROC (FPU_MVE),
3400 MVE_SRSHR,
3401 0xea500f2f, 0xfff08f3f,
3402 "srshr%c\t%16-19S, %j"},
3403
3404 {ARM_FEATURE_COPROC (FPU_MVE),
3405 MVE_UQRSHLL,
3406 0xea51010d, 0xfff101ff,
3407 "uqrshll%c\t%17-19l, %9-11h, %12-15S"},
3408
3409 {ARM_FEATURE_COPROC (FPU_MVE),
3410 MVE_UQRSHL,
3411 0xea500f0d, 0xfff00fff,
3412 "uqrshl%c\t%16-19S, %12-15S"},
3413
3414 {ARM_FEATURE_COPROC (FPU_MVE),
3415 MVE_UQSHLL,
3416 0xea51010f, 0xfff1813f,
3417 "uqshll%c\t%17-19l, %9-11h, %j"},
3418
3419 {ARM_FEATURE_COPROC (FPU_MVE),
3420 MVE_UQSHL,
3421 0xea500f0f, 0xfff08f3f,
3422 "uqshl%c\t%16-19S, %j"},
3423
3424 {ARM_FEATURE_COPROC (FPU_MVE),
3425 MVE_URSHRL,
3426 0xea51011f, 0xfff1813f,
3427 "urshrl%c\t%17-19l, %9-11h, %j"},
3428
3429 {ARM_FEATURE_COPROC (FPU_MVE),
3430 MVE_URSHR,
3431 0xea500f1f, 0xfff08f3f,
3432 "urshr%c\t%16-19S, %j"},
3433
e39c1607
SD		 3434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3435 MVE_CSINC,
3436 0xea509000, 0xfff0f000,
3437 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3438
3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3440 MVE_CSINV,
3441 0xea50a000, 0xfff0f000,
3442 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3443
3444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3445 MVE_CSET,
3446 0xea5f900f, 0xfffff00f,
3447 "cset\t%8-11S, %4-7C"},
3448
3449 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3450 MVE_CSETM,
3451 0xea5fa00f, 0xfffff00f,
3452 "csetm\t%8-11S, %4-7C"},
3453
3454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3455 MVE_CSEL,
3456 0xea508000, 0xfff0f000,
3457 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3458
3459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3460 MVE_CSNEG,
3461 0xea50b000, 0xfff0f000,
3462 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3463
3464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3465 MVE_CINC,
3466 0xea509000, 0xfff0f000,
3467 "cinc\t%8-11S, %16-19Z, %4-7C"},
3468
3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3470 MVE_CINV,
3471 0xea50a000, 0xfff0f000,
3472 "cinv\t%8-11S, %16-19Z, %4-7C"},
3473
3474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3475 MVE_CNEG,
3476 0xea50b000, 0xfff0f000,
3477 "cneg\t%8-11S, %16-19Z, %4-7C"},
3478
143275ea
AV		 3479 {ARM_FEATURE_CORE_LOW (0),
3480 MVE_NONE,
3481 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3482};
3483
8f06b2d8
PB		 3484/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3485 ordered: they must be searched linearly from the top to obtain a correct
3486 match. */
3487
3488/* print_insn_arm recognizes the following format control codes:
3489
3490 %% %
3491
3492 %a print address for ldr/str instruction
3493 %s print address for ldr/str halfword/signextend instruction
c1e26897 3494 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3495 %b print branch destination
3496 %c print condition code (always bits 28-31)
3497 %m print register mask for ldm/stm instruction
3498 %o print operand2 (immediate or register + shift)
3499 %p print 'p' iff bits 12-15 are 15
3500 %t print 't' iff bit 21 set and bit 24 clear
3501 %B print arm BLX(1) destination
3502 %C print the PSR sub type.
62b3e311
PB		 3503 %U print barrier type.
3504 %P print address for pli instruction.
8f06b2d8
PB		 3505
3506 %<bitfield>r print as an ARM register
9eb6c0f1 3507 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3508 %<bitfield>R as %r but r15 is UNPREDICTABLE
3509 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3510 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3511 %<bitfield>d print the bitfield in decimal
43e65147 3512 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3513 %<bitfield>x print the bitfield in hex
3514 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3515
16980d0b
JB		 3516 %<bitfield>'c print specified char iff bitfield is all ones
3517 %<bitfield>`c print specified char iff bitfield is all zeroes
3518 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3519
8f06b2d8
PB		 3520 %e print arm SMI operand (bits 0..7,8..19).
3521 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3522 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3523 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3524
8f06b2d8
PB		 3525static const struct opcode32 arm_opcodes[] =
3526{
3527 /* ARM instructions. */
823d2571
TG		 3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3529 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3531 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3532
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3534 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3536 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3538 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3540 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3542 0x00800090, 0x0fa000f0,
3543 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3545 0x00a00090, 0x0fa000f0,
3546 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3547
105bde57 3548 /* V8.2 RAS extension instructions. */
4d1464f2 3549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3550 0xe320f010, 0xffffffff, "esb"},
3551
53c4b28b 3552 /* V8 instructions. */
823d2571
TG		 3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3554 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3555 /* Defined in V8 but is in NOP space so available to all arch. */
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3557 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3559 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3560 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3561 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3563 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3565 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3566 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3567 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3568 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3569 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3570 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3571 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3572 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3573 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3574 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3575 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3576 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3577 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3578 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3579 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3580 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3581 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3582 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3583 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3584 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3585 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3586 /* CRC32 instructions. */
823d2571
TG		 3587 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3588 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3589 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3590 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3591 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3592 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3593 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3594 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3595 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3596 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3597 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3598 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3599
ddfded2f
MW		 3600 /* Privileged Access Never extension instructions. */
3601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3602 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3603
90ec0d68 3604 /* Virtualization Extension instructions. */
823d2571
TG		 3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3607
eea54501 3608 /* Integer Divide Extension instructions. */
823d2571
TG		 3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3610 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3612 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3613
60e5ef9f 3614 /* MP Extension instructions. */
823d2571 3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3616
c597cc3d
SD		 3617 /* Speculation Barriers. */
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3621
62b3e311 3622 /* V7 instructions. */
823d2571
TG		 3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3631 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3632
c19d1205 3633 /* ARM V6T2 instructions. */
823d2571
TG		 3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3635 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3637 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3639 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3641 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3642
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3644 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3646 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3647
ff8646ee 3648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3649 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3650 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3651 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3653 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3655 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3656
f4c65163 3657 /* ARM Security extension instructions. */
823d2571
TG		 3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3659 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3660
8f06b2d8 3661 /* ARM V6K instructions. */
823d2571
TG		 3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3663 0xf57ff01f, 0xffffffff, "clrex"},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3665 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3667 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3669 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3671 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3673 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3675 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3676
7fadb25d
SD		 3677 /* ARMv8.5-A instructions. */
3678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3679
8f06b2d8 3680 /* ARM V6K NOP hints. */
823d2571
TG		 3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3682 0x0320f001, 0x0fffffff, "yield%c"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3684 0x0320f002, 0x0fffffff, "wfe%c"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3686 0x0320f003, 0x0fffffff, "wfi%c"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3688 0x0320f004, 0x0fffffff, "sev%c"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3690 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3691
fe56b6ce 3692 /* ARM V6 instructions. */
823d2571
TG		 3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3694 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3696 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3698 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3700 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3702 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3704 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3706 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3708 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3710 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3712 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3714 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3716 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3718 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3720 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3722 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3724 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3726 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3728 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3730 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3732 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3734 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3736 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3738 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3740 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3742 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3744 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3746 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3748 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3752 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3754 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3756 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3760 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3780 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3782 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3784 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3786 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3788 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3798 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3800 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3802 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3804 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3806 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3808 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3810 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3812 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3814 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3816 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3818 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3820 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3822 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3824 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3826 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3828 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3830 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3832 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3834 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3836 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3838 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3840 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3842 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3844 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3846 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3848 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3850 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3852 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3854 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3856 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3858 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3860 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3862 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3864 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3866 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3868 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3870 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3872 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3874 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3876 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3878 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3880 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3882 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3884 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3886 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3888 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3890 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3892 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3894 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3896 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3898 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3900 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3902 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3904 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3906 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3908 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3910 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3912 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3914 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3916 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3918 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3920 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3922 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3924 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3926 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3928 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3930 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3932 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3934 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3936 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3937
8f06b2d8 3938 /* V5J instruction. */
823d2571
TG		 3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3940 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3941
8f06b2d8 3942 /* V5 Instructions. */
823d2571
TG		 3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3944 0xe1200070, 0xfff000f0,
3945 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3947 0xfa000000, 0xfe000000, "blx\t%B"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3949 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3951 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3952
3953 /* V5E "El Segundo" Instructions. */
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3955 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3957 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3959 0xf450f000, 0xfc70f000, "pld\t%a"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3961 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3963 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3965 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3967 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3968
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3970 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3972 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3973
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3975 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3977 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3979 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3981 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3982
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3984 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3986 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3988 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3990 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3991
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3993 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3995 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3996
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3998 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4000 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4002 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4004 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4005
8f06b2d8 4006 /* ARM Instructions. */
823d2571
TG		 4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4008 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4009
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4011 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4013 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4015 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4017 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4019 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4021 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4022
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4024 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4026 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4028 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4030 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4031
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4033 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4035 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4037 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4039 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4040
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4042 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4044 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4046 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4047
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4049 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4051 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4053 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4054
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4058 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4060 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4061
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4063 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4065 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4067 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4068
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4075
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4077 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4079 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4081 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4082
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4086 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4088 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4089
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4093 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4095 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4096
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4098 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4100 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4102 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4103
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4107 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4109 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4110
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4112 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4114 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4116 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4117
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4119 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4121 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4123 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4124
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4131
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4133 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4135 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4137 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4138
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4140 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4142 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4144 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4153
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4155 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4160
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4162 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4164 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4167
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4169 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4172
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4175
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4180
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4204 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4206 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4208 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4210 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x092d0000, 0x0fff0000, "push%c\t%m"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4218 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4219
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4225 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4227 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4231 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4233 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4235 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4237 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4239 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4241 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4243 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4245 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4247 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4249 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4251 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4253 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4255 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4257 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4258
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4260 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4262 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4263
4264 /* The rest. */
4ab90a7a
AV		 4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4266 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4269 {ARM_FEATURE_CORE_LOW (0),
4270 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4271};
4272
4273/* print_insn_thumb16 recognizes the following format control codes:
4274
4275 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4276 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4277 %<bitfield>I print bitfield as a signed decimal
4278 (top bit of range being the sign bit)
4279 %N print Thumb register mask (with LR)
4280 %O print Thumb register mask (with PC)
4281 %M print Thumb register mask
4282 %b print CZB's 6-bit unsigned branch destination
4283 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4284 %c print the condition code
4285 %C print the condition code, or "s" if not conditional
4286 %x print warning if conditional an not at end of IT block"
4287 %X print "\t; unpredictable <IT:code>" if conditional
4288 %I print IT instruction suffix and operands
4547cb56 4289 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4290 %<bitfield>r print bitfield as an ARM register
4291 %<bitfield>d print bitfield as a decimal
4292 %<bitfield>H print (bitfield * 2) as a decimal
4293 %<bitfield>W print (bitfield * 4) as a decimal
4294 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4295 %<bitfield>B print Thumb branch destination (signed displacement)
4296 %<bitfield>c print bitfield as a condition code
4297 %<bitnum>'c print specified char iff bit is one
4298 %<bitnum>?ab print a if bit is one else print b. */
4299
4300static const struct opcode16 thumb_opcodes[] =
4301{
4302 /* Thumb instructions. */
4303
16a1fa25
TP		 4304 /* ARMv8-M Security Extensions instructions. */
4305 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4307
53c4b28b 4308 /* ARM V8 instructions. */
823d2571
TG		 4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4312
8f06b2d8 4313 /* ARM V6K no-argument instructions. */
823d2571
TG		 4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4320
4321 /* ARM V6T2 instructions. */
ff8646ee
TP		 4322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4323 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4325 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4327
4328 /* ARM V6. */
823d2571
TG		 4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4340
4341 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4343 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4344 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4346 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4347 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4349 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4350 /* Format 4. */
823d2571
TG		 4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4367 /* format 13 */
823d2571
TG		 4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4370 /* format 5 */
823d2571
TG		 4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4375 /* format 14 */
823d2571
TG		 4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4378 /* format 2 */
823d2571
TG		 4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4380 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4382 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4384 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4386 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4387 /* format 8 */
823d2571
TG		 4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4389 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4391 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4393 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4394 /* format 7 */
823d2571
TG		 4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4396 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4398 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4399 /* format 1 */
823d2571
TG		 4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4402 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4405 /* format 3 */
823d2571
TG		 4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4410 /* format 6 */
823d2571
TG		 4411 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4413 0x4800, 0xF800,
4414 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4415 /* format 9 */
823d2571
TG		 4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4417 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4419 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4421 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4423 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4424 /* format 10 */
823d2571
TG		 4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4426 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4428 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4429 /* format 11 */
823d2571
TG		 4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4431 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4433 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4434 /* format 12 */
823d2571
TG		 4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4436 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4438 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4439 /* format 15 */
823d2571
TG		 4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4442 /* format 17 */
823d2571 4443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4444 /* format 16 */
823d2571
TG		 4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4448 /* format 18 */
823d2571 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4450
4451 /* The E800 .. FFFF range is unconditionally redirected to the
4452 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4453 are processed via that table. Thus, we can never encounter a
4454 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4456 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4457};
4458
4459/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4460 We adopt the convention that hw1 is the high 16 bits of .value and
4461 .mask, hw2 the low 16 bits.
4462
4463 print_insn_thumb32 recognizes the following format control codes:
4464
4465 %% %
4466
4467 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4468 %M print a modified 12-bit immediate (same location)
4469 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4470 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4471 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4472 %S print a possibly-shifted Rm
4473
32a94698 4474 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4475 %a print the address of a plain load/store
4476 %w print the width and signedness of a core load/store
4477 %m print register mask for ldm/stm
4b5a202f 4478 %n print register mask for clrm
8f06b2d8
PB		 4479
4480 %E print the lsb and width fields of a bfc/bfi instruction
4481 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4482 %G print a fallback offset for Branch Future instructions
e5d6e09e 4483 %W print an offset for BF instruction
1caf72a5 4484 %Y print an offset for BFL instruction
1889da70 4485 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4486 %Q print an offset for Low Overhead Loop instructions
4487 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4488 %b print a conditional branch offset
4489 %B print an unconditional branch offset
4490 %s print the shift field of an SSAT instruction
4491 %R print the rotation field of an SXT instruction
62b3e311
PB		 4492 %U print barrier type.
4493 %P print address for pli instruction.
c22aaad1
PB		 4494 %c print the condition code
4495 %x print warning if conditional an not at end of IT block"
4496 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4497
4498 %<bitfield>d print bitfield in decimal
f0fba320 4499 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4500 %<bitfield>W print bitfield*4 in decimal
4501 %<bitfield>r print bitfield as an ARM register
dd5181d5 4502 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4503 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4504 %<bitfield>c print bitfield as a condition code
4505
16980d0b
JB		 4506 %<bitfield>'c print specified char iff bitfield is all ones
4507 %<bitfield>`c print specified char iff bitfield is all zeroes
4508 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4509
4510 With one exception at the bottom (done because BL and BLX(1) need
4511 to come dead last), this table was machine-sorted first in
4512 decreasing order of number of bits set in the mask, then in
4513 increasing numeric order of mask, then in increasing numeric order
4514 of opcode. This order is not the clearest for a human reader, but
4515 is guaranteed never to catch a special-case bit pattern with a more
4516 general mask, which is important, because this instruction encoding
4517 makes heavy use of special-case bit patterns. */
4518static const struct opcode32 thumb32_opcodes[] =
4519{
4b5a202f
AV		 4520 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4521 instructions. */
60f993ce 4522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4523 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4525 0xf02fc001, 0xfffff001, "le\t%P"},
4526 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4527 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4529 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4531 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4533 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4535 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4537 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4538
4389b29a
AV		 4539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4540 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4542 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4544 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4546 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4548 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4549
4b5a202f
AV		 4550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4551 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4552
16a1fa25
TP		 4553 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4556 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4558 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4560 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4562 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4563
105bde57 4564 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4566 0xf3af8010, 0xffffffff, "esb"},
4567
53c4b28b 4568 /* V8 instructions. */
823d2571
TG		 4569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4570 0xf3af8005, 0xffffffff, "sevl%c.w"},
4571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4572 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4574 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4576 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4578 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4580 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4582 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4584 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4586 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4588 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4590 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4592 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4594 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4596 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4598 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4600 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4601
dd5181d5 4602 /* CRC32 instructions. */
823d2571 4603 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4604 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 4605 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4606 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 4607 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4608 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 4609 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4610 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 4611 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4612 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 4613 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4614 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4615
c597cc3d
SD		 4616 /* Speculation Barriers. */
4617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4620
62b3e311 4621 /* V7 instructions. */
823d2571
TG		 4622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4630 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4632 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4633
90ec0d68 4634 /* Virtualization Extension instructions. */
823d2571 4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4636 /* We skip ERET as that is SUBS pc, lr, #0. */
4637
60e5ef9f 4638 /* MP Extension instructions. */
823d2571 4639 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4640
f4c65163 4641 /* Security extension instructions. */
823d2571 4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4643
7fadb25d
SD		 4644 /* ARMv8.5-A instructions. */
4645 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4646
8f06b2d8 4647 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4654 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4656
ff8646ee 4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4658 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4660 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4662 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4664 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4666 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4668 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4670 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4672 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4674 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4676 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4678 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4680 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4682 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4684 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4686 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4688 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4690 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4692 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4694 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4696 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4698 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4700 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4702 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4704 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4706 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4708 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4710 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4712 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4714 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4716 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4718 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4720 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4722 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4724 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4726 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4728 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4730 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4732 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4738 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4740 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4742 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4744 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4746 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4748 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4750 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4752 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4754 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4756 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4758 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4760 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4762 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4764 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4766 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4768 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4770 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4772 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4774 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4776 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4778 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4780 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4782 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4784 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4786 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4788 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4792 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4794 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4796 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4814 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4816 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4882 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xf810f000, 0xff70f000, "pld%c\t%a"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xfb100000, 0xfff000c0,
4915 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xfbc00080, 0xfff000c0,
4918 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4924 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4930 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4934 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4956 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xe9400000, 0xff500000,
4991 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4993 0xe9500000, 0xff500000,
4994 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xe8600000, 0xff700000,
4997 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4999 0xe8700000, 0xff700000,
5000 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5005
5006 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5015
8f06b2d8 5016 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5018 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5020 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5021
5022 /* Fallback. */
823d2571
TG		 5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5024 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5025 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5026};
ff4a8d2b 5027
8f06b2d8
PB		 5028static const char *const arm_conditional[] =
5029{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5030 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5031
5032static const char *const arm_fp_const[] =
5033{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5034
5035static const char *const arm_shift[] =
5036{"lsl", "lsr", "asr", "ror"};
5037
5038typedef struct
5039{
5040 const char *name;
5041 const char *description;
5042 const char *reg_names[16];
5043}
5044arm_regname;
5045
5046static const arm_regname regnames[] =
5047{
65b48a81 5048 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5049 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5050 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5051 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5052 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5053 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5054 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5055 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5056 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5057 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5058 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5059 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 5060 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5061 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 5062};
5063
5064static const char *const iwmmxt_wwnames[] =
5065{"b", "h", "w", "d"};
5066
5067static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5068{"b", "bus", "bc", "bss",
5069 "h", "hus", "hc", "hss",
5070 "w", "wus", "wc", "wss",
5071 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5072};
5073
5074static const char *const iwmmxt_regnames[] =
5075{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5076 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5077};
5078
5079static const char *const iwmmxt_cregnames[] =
5080{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5081 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5082};
5083
143275ea
AV		 5084static const char *const vec_condnames[] =
5085{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5086};
5087
5088static const char *const mve_predicatenames[] =
5089{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5090 "eee", "ee", "eet", "e", "ett", "et", "ete"
5091};
5092
5093/* Names for 2-bit size field for mve vector isntructions. */
5094static const char *const mve_vec_sizename[] =
5095 { "8", "16", "32", "64"};
5096
5097/* Indicates whether we are processing a then predicate,
5098 else predicate or none at all. */
5099enum vpt_pred_state
5100{
5101 PRED_NONE,
5102 PRED_THEN,
5103 PRED_ELSE
5104};
5105
5106/* Information used to process a vpt block and subsequent instructions. */
5107struct vpt_block
5108{
5109 /* Are we in a vpt block. */
5110 bfd_boolean in_vpt_block;
5111
5112 /* Next predicate state if in vpt block. */
5113 enum vpt_pred_state next_pred_state;
5114
5115 /* Mask from vpt/vpst instruction. */
5116 long predicate_mask;
5117
5118 /* Instruction number in vpt block. */
5119 long current_insn_num;
5120
5121 /* Number of instructions in vpt block.. */
5122 long num_pred_insn;
5123};
5124
5125static struct vpt_block vpt_block_state =
5126{
5127 FALSE,
5128 PRED_NONE,
5129 0,
5130 0,
5131 0
5132};
5133
8f06b2d8
PB		 5134/* Default to GCC register name set. */
5135static unsigned int regname_selected = 1;
5136
65b48a81 5137#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5138#define arm_regnames regnames[regname_selected].reg_names
5139
5140static bfd_boolean force_thumb = FALSE;
5141
c22aaad1
PB		 5142/* Current IT instruction state. This contains the same state as the IT
5143 bits in the CPSR. */
5144static unsigned int ifthen_state;
5145/* IT state for the next instruction. */
5146static unsigned int ifthen_next_state;
5147/* The address of the insn for which the IT state is valid. */
5148static bfd_vma ifthen_address;
5149#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5150/* Indicates that the current Conditional state is unconditional or outside
5151 an IT block. */
5152#define COND_UNCOND 16
c22aaad1 5153
8f06b2d8
PB		 5154\f
5155/* Functions. */
143275ea
AV		 5156/* Extract the predicate mask for a VPT or VPST instruction.
5157 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5158
5159static long
5160mve_extract_pred_mask (long given)
5161{
5162 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5163}
5164
5165/* Return the number of instructions in a MVE predicate block. */
5166static long
5167num_instructions_vpt_block (long given)
5168{
5169 long mask = mve_extract_pred_mask (given);
5170 if (mask == 0)
5171 return 0;
5172
5173 if (mask == 8)
5174 return 1;
5175
5176 if ((mask & 7) == 4)
5177 return 2;
5178
5179 if ((mask & 3) == 2)
5180 return 3;
5181
5182 if ((mask & 1) == 1)
5183 return 4;
5184
5185 return 0;
5186}
5187
5188static void
5189mark_outside_vpt_block (void)
5190{
5191 vpt_block_state.in_vpt_block = FALSE;
5192 vpt_block_state.next_pred_state = PRED_NONE;
5193 vpt_block_state.predicate_mask = 0;
5194 vpt_block_state.current_insn_num = 0;
5195 vpt_block_state.num_pred_insn = 0;
5196}
5197
5198static void
5199mark_inside_vpt_block (long given)
5200{
5201 vpt_block_state.in_vpt_block = TRUE;
5202 vpt_block_state.next_pred_state = PRED_THEN;
5203 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5204 vpt_block_state.current_insn_num = 0;
5205 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5206 assert (vpt_block_state.num_pred_insn >= 1);
5207}
5208
5209static enum vpt_pred_state
5210invert_next_predicate_state (enum vpt_pred_state astate)
5211{
5212 if (astate == PRED_THEN)
5213 return PRED_ELSE;
5214 else if (astate == PRED_ELSE)
5215 return PRED_THEN;
5216 else
5217 return PRED_NONE;
5218}
5219
5220static enum vpt_pred_state
5221update_next_predicate_state (void)
5222{
5223 long pred_mask = vpt_block_state.predicate_mask;
5224 long mask_for_insn = 0;
5225
5226 switch (vpt_block_state.current_insn_num)
5227 {
5228 case 1:
5229 mask_for_insn = 8;
5230 break;
5231
5232 case 2:
5233 mask_for_insn = 4;
5234 break;
5235
5236 case 3:
5237 mask_for_insn = 2;
5238 break;
5239
5240 case 4:
5241 return PRED_NONE;
5242 }
5243
5244 if (pred_mask & mask_for_insn)
5245 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5246 else
5247 return vpt_block_state.next_pred_state;
5248}
5249
5250static void
5251update_vpt_block_state (void)
5252{
5253 vpt_block_state.current_insn_num++;
5254 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5255 {
5256 /* No more instructions to process in vpt block. */
5257 mark_outside_vpt_block ();
5258 return;
5259 }
5260
5261 vpt_block_state.next_pred_state = update_next_predicate_state ();
5262}
8f06b2d8 5263
16980d0b
JB		 5264/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5265 Returns pointer to following character of the format string and
5266 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5267 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5268
5269static const char *
fe56b6ce
NC		 5270arm_decode_bitfield (const char *ptr,
5271 unsigned long insn,
5272 unsigned long *valuep,
5273 int *widthp)
16980d0b
JB		 5274{
5275 unsigned long value = 0;
5276 int width = 0;
43e65147
L		 5277
5278 do
16980d0b
JB		 5279 {
5280 int start, end;
5281 int bits;
5282
5283 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5284 start = start * 10 + *ptr - '0';
5285 if (*ptr == '-')
5286 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5287 end = end * 10 + *ptr - '0';
5288 else
5289 end = start;
5290 bits = end - start;
5291 if (bits < 0)
5292 abort ();
5293 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5294 width += bits + 1;
5295 }
5296 while (*ptr++ == ',');
5297 *valuep = value;
5298 if (widthp)
5299 *widthp = width;
5300 return ptr - 1;
5301}
5302
8f06b2d8 5303static void
37b37b2d 5304arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5305 bfd_boolean print_shift)
8f06b2d8
PB		 5306{
5307 func (stream, "%s", arm_regnames[given & 0xf]);
5308
5309 if ((given & 0xff0) != 0)
5310 {
5311 if ((given & 0x10) == 0)
5312 {
5313 int amount = (given & 0xf80) >> 7;
5314 int shift = (given & 0x60) >> 5;
5315
5316 if (amount == 0)
5317 {
5318 if (shift == 3)
5319 {
5320 func (stream, ", rrx");
5321 return;
5322 }
5323
5324 amount = 32;
5325 }
5326
37b37b2d
RE		 5327 if (print_shift)
5328 func (stream, ", %s #%d", arm_shift[shift], amount);
5329 else
5330 func (stream, ", #%d", amount);
8f06b2d8 5331 }
74bdfecf 5332 else if ((given & 0x80) == 0x80)
aefd8a40 5333 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5334 else if (print_shift)
8f06b2d8
PB		 5335 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5336 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5337 else
5338 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5339 }
5340}
5341
73cd51e5
AV		 5342/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5343
5344static bfd_boolean
5345is_mve_okay_in_it (enum mve_instructions matched_insn)
5346{
c507f10b
AV		 5347 switch (matched_insn)
5348 {
5349 case MVE_VMOV_GP_TO_VEC_LANE:
5350 case MVE_VMOV2_VEC_LANE_TO_GP:
5351 case MVE_VMOV2_GP_TO_VEC_LANE:
5352 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5353 case MVE_LSLL:
5354 case MVE_LSLLI:
5355 case MVE_LSRL:
5356 case MVE_ASRL:
5357 case MVE_ASRLI:
5358 case MVE_SQRSHRL:
5359 case MVE_SQRSHR:
5360 case MVE_UQRSHL:
5361 case MVE_UQRSHLL:
5362 case MVE_UQSHL:
5363 case MVE_UQSHLL:
5364 case MVE_URSHRL:
5365 case MVE_URSHR:
5366 case MVE_SRSHRL:
5367 case MVE_SRSHR:
5368 case MVE_SQSHLL:
5369 case MVE_SQSHL:
c507f10b
AV		 5370 return TRUE;
5371 default:
5372 return FALSE;
5373 }
73cd51e5
AV		 5374}
5375
5376static bfd_boolean
5377is_mve_architecture (struct disassemble_info *info)
5378{
5379 struct arm_private_data *private_data = info->private_data;
5380 arm_feature_set allowed_arches = private_data->features;
5381
5382 arm_feature_set arm_ext_v8_1m_main
5383 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5384
5385 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5386 && !ARM_CPU_IS_ANY (allowed_arches))
5387 return TRUE;
5388 else
5389 return FALSE;
5390}
5391
143275ea
AV		 5392static bfd_boolean
5393is_vpt_instruction (long given)
5394{
5395
5396 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5397 if ((given & 0x0040e000) == 0)
5398 return FALSE;
5399
5400 /* VPT floating point T1 variant. */
5401 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5402 /* VPT floating point T2 variant. */
5403 || ((given & 0xefb10f50) == 0xee310f40)
5404 /* VPT vector T1 variant. */
5405 || ((given & 0xff811f51) == 0xfe010f00)
5406 /* VPT vector T2 variant. */
5407 || ((given & 0xff811f51) == 0xfe010f01
5408 && ((given & 0x300000) != 0x300000))
5409 /* VPT vector T3 variant. */
5410 || ((given & 0xff811f50) == 0xfe011f00)
5411 /* VPT vector T4 variant. */
5412 || ((given & 0xff811f70) == 0xfe010f40)
5413 /* VPT vector T5 variant. */
5414 || ((given & 0xff811f70) == 0xfe010f60)
5415 /* VPT vector T6 variant. */
5416 || ((given & 0xff811f50) == 0xfe011f40)
5417 /* VPST vector T variant. */
5418 || ((given & 0xffbf1fff) == 0xfe310f4d))
5419 return TRUE;
5420 else
5421 return FALSE;
5422}
5423
73cd51e5
AV		 5424/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5425 and ending bitfield = END. END must be greater than START. */
5426
5427static unsigned long
5428arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5429{
5430 int bits = end - start;
5431
5432 if (bits < 0)
5433 abort ();
5434
5435 return ((given >> start) & ((2ul << bits) - 1));
5436}
5437
5438/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5439 START:END and START2:END2. END/END2 must be greater than
5440 START/START2. */
5441
5442static unsigned long
5443arm_decode_field_multiple (unsigned long given, unsigned int start,
5444 unsigned int end, unsigned int start2,
5445 unsigned int end2)
5446{
5447 int bits = end - start;
5448 int bits2 = end2 - start2;
5449 unsigned long value = 0;
5450 int width = 0;
5451
5452 if (bits2 < 0)
5453 abort ();
5454
5455 value = arm_decode_field (given, start, end);
5456 width += bits + 1;
5457
5458 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5459 return value;
5460}
5461
5462/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5463 This helps us decode instructions that change mnemonic depending on specific
5464 operand values/encodings. */
5465
5466static bfd_boolean
5467is_mve_encoding_conflict (unsigned long given,
5468 enum mve_instructions matched_insn)
5469{
143275ea
AV		 5470 switch (matched_insn)
5471 {
5472 case MVE_VPST:
5473 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5474 return TRUE;
5475 else
5476 return FALSE;
5477
5478 case MVE_VPT_FP_T1:
5479 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5480 return TRUE;
5481 if ((arm_decode_field (given, 12, 12) == 0)
5482 && (arm_decode_field (given, 0, 0) == 1))
5483 return TRUE;
5484 return FALSE;
5485
5486 case MVE_VPT_FP_T2:
5487 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5488 return TRUE;
5489 if (arm_decode_field (given, 0, 3) == 0xd)
5490 return TRUE;
5491 return FALSE;
5492
5493 case MVE_VPT_VEC_T1:
5494 case MVE_VPT_VEC_T2:
5495 case MVE_VPT_VEC_T3:
5496 case MVE_VPT_VEC_T4:
5497 case MVE_VPT_VEC_T5:
5498 case MVE_VPT_VEC_T6:
5499 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5500 return TRUE;
5501 if (arm_decode_field (given, 20, 21) == 3)
5502 return TRUE;
5503 return FALSE;
5504
5505 case MVE_VCMP_FP_T1:
5506 if ((arm_decode_field (given, 12, 12) == 0)
5507 && (arm_decode_field (given, 0, 0) == 1))
5508 return TRUE;
5509 else
5510 return FALSE;
5511
5512 case MVE_VCMP_FP_T2:
5513 if (arm_decode_field (given, 0, 3) == 0xd)
5514 return TRUE;
5515 else
5516 return FALSE;
5517
14b456f2
AV		 5518 case MVE_VQADD_T2:
5519 case MVE_VQSUB_T2:
f49bb598
AV		 5520 case MVE_VMUL_VEC_T2:
5521 case MVE_VMULH:
5522 case MVE_VRMULH:
56858bea
AV		 5523 case MVE_VMLA:
5524 case MVE_VMAX:
5525 case MVE_VMIN:
e523f101 5526 case MVE_VBRSR:
66dcaa5d
AV		 5527 case MVE_VADD_VEC_T2:
5528 case MVE_VSUB_VEC_T2:
5529 case MVE_VABAV:
ed63aa17
AV		 5530 case MVE_VQRSHL_T1:
5531 case MVE_VQSHL_T4:
5532 case MVE_VRSHL_T1:
5533 case MVE_VSHL_T3:
897b9bbc
AV		 5534 case MVE_VCADD_VEC:
5535 case MVE_VHCADD:
1c8f2df8
AV		 5536 case MVE_VDDUP:
5537 case MVE_VIDUP:
d3b63143
AV		 5538 case MVE_VQRDMLADH:
5539 case MVE_VQDMLAH:
5540 case MVE_VQRDMLAH:
5541 case MVE_VQDMLASH:
5542 case MVE_VQRDMLASH:
5543 case MVE_VQDMLSDH:
5544 case MVE_VQRDMLSDH:
5545 case MVE_VQDMULH_T3:
5546 case MVE_VQRDMULH_T4:
5547 case MVE_VQDMLADH:
5548 case MVE_VMLAS:
14925797 5549 case MVE_VMULL_INT:
9743db03
AV		 5550 case MVE_VHADD_T2:
5551 case MVE_VHSUB_T2:
143275ea
AV		 5552 case MVE_VCMP_VEC_T1:
5553 case MVE_VCMP_VEC_T2:
5554 case MVE_VCMP_VEC_T3:
5555 case MVE_VCMP_VEC_T4:
5556 case MVE_VCMP_VEC_T5:
5557 case MVE_VCMP_VEC_T6:
5558 if (arm_decode_field (given, 20, 21) == 3)
5559 return TRUE;
5560 else
5561 return FALSE;
5562
04d54ace
AV		 5563 case MVE_VLD2:
5564 case MVE_VLD4:
5565 case MVE_VST2:
5566 case MVE_VST4:
5567 if (arm_decode_field (given, 7, 8) == 3)
5568 return TRUE;
5569 else
5570 return FALSE;
5571
aef6d006
AV		 5572 case MVE_VSTRB_T1:
5573 case MVE_VSTRH_T2:
5574 if ((arm_decode_field (given, 24, 24) == 0)
5575 && (arm_decode_field (given, 21, 21) == 0))
5576 {
5577 return TRUE;
5578 }
5579 else if ((arm_decode_field (given, 7, 8) == 3))
5580 return TRUE;
5581 else
5582 return FALSE;
5583
5584 case MVE_VSTRB_T5:
5585 case MVE_VSTRH_T6:
5586 case MVE_VSTRW_T7:
5587 if ((arm_decode_field (given, 24, 24) == 0)
5588 && (arm_decode_field (given, 21, 21) == 0))
5589 {
5590 return TRUE;
5591 }
5592 else
5593 return FALSE;
5594
bf0b396d
AV		 5595 case MVE_VCVT_FP_FIX_VEC:
5596 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5597
c507f10b
AV		 5598 case MVE_VBIC_IMM:
5599 case MVE_VORR_IMM:
5600 {
5601 unsigned long cmode = arm_decode_field (given, 8, 11);
5602
5603 if ((cmode & 1) == 0)
5604 return TRUE;
5605 else if ((cmode & 0xc) == 0xc)
5606 return TRUE;
5607 else
5608 return FALSE;
5609 }
5610
5611 case MVE_VMVN_IMM:
5612 {
5613 unsigned long cmode = arm_decode_field (given, 8, 11);
5614
5615 if ((cmode & 9) == 1)
5616 return TRUE;
5617 else if ((cmode & 5) == 1)
5618 return TRUE;
5619 else if ((cmode & 0xe) == 0xe)
5620 return TRUE;
5621 else
5622 return FALSE;
5623 }
5624
5625 case MVE_VMOV_IMM_TO_VEC:
5626 if ((arm_decode_field (given, 5, 5) == 1)
5627 && (arm_decode_field (given, 8, 11) != 0xe))
5628 return TRUE;
5629 else
5630 return FALSE;
5631
14925797
AV		 5632 case MVE_VMOVL:
5633 {
5634 unsigned long size = arm_decode_field (given, 19, 20);
5635 if ((size == 0) || (size == 3))
5636 return TRUE;
5637 else
5638 return FALSE;
5639 }
5640
56858bea
AV		 5641 case MVE_VMAXA:
5642 case MVE_VMINA:
5643 case MVE_VMAXV:
5644 case MVE_VMAXAV:
5645 case MVE_VMINV:
5646 case MVE_VMINAV:
ed63aa17
AV		 5647 case MVE_VQRSHL_T2:
5648 case MVE_VQSHL_T1:
5649 case MVE_VRSHL_T2:
5650 case MVE_VSHL_T2:
5651 case MVE_VSHLL_T2:
d3b63143 5652 case MVE_VADDV:
14925797
AV		 5653 case MVE_VMOVN:
5654 case MVE_VQMOVUN:
5655 case MVE_VQMOVN:
5656 if (arm_decode_field (given, 18, 19) == 3)
5657 return TRUE;
5658 else
5659 return FALSE;
5660
d3b63143
AV		 5661 case MVE_VMLSLDAV:
5662 case MVE_VRMLSLDAVH:
5663 case MVE_VMLALDAV:
5664 case MVE_VADDLV:
5665 if (arm_decode_field (given, 20, 22) == 7)
5666 return TRUE;
5667 else
5668 return FALSE;
5669
5670 case MVE_VRMLALDAVH:
5671 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5672 return TRUE;
5673 else
5674 return FALSE;
5675
1c8f2df8
AV		 5676 case MVE_VDWDUP:
5677 case MVE_VIWDUP:
5678 if ((arm_decode_field (given, 20, 21) == 3)
5679 || (arm_decode_field (given, 1, 3) == 7))
5680 return TRUE;
5681 else
5682 return FALSE;
5683
ed63aa17
AV		 5684
5685 case MVE_VSHLL_T1:
5686 if (arm_decode_field (given, 16, 18) == 0)
5687 {
5688 unsigned long sz = arm_decode_field (given, 19, 20);
5689
5690 if ((sz == 1) || (sz == 2))
5691 return TRUE;
5692 else
5693 return FALSE;
5694 }
5695 else
5696 return FALSE;
5697
5698 case MVE_VQSHL_T2:
5699 case MVE_VQSHLU_T3:
5700 case MVE_VRSHR:
5701 case MVE_VSHL_T1:
5702 case MVE_VSHR:
5703 case MVE_VSLI:
5704 case MVE_VSRI:
5705 if (arm_decode_field (given, 19, 21) == 0)
5706 return TRUE;
5707 else
5708 return FALSE;
5709
e523f101
AV		 5710 case MVE_VCTP:
5711 if (arm_decode_field (given, 16, 19) == 0xf)
5712 return TRUE;
5713 else
5714 return FALSE;
5715
23d00a41
SD		 5716 case MVE_ASRLI:
5717 case MVE_ASRL:
5718 case MVE_LSLLI:
5719 case MVE_LSLL:
5720 case MVE_LSRL:
5721 case MVE_SQRSHRL:
5722 case MVE_SQSHLL:
5723 case MVE_SRSHRL:
5724 case MVE_UQRSHLL:
5725 case MVE_UQSHLL:
5726 case MVE_URSHRL:
5727 if (arm_decode_field (given, 9, 11) == 0x7)
5728 return TRUE;
5729 else
5730 return FALSE;
5731
e39c1607
SD		 5732 case MVE_CSINC:
5733 case MVE_CSINV:
5734 {
5735 unsigned long rm, rn;
5736 rm = arm_decode_field (given, 0, 3);
5737 rn = arm_decode_field (given, 16, 19);
5738 /* CSET/CSETM. */
5739 if (rm == 0xf && rn == 0xf)
5740 return TRUE;
5741 /* CINC/CINV. */
5742 else if (rn == rm && rn != 0xf)
5743 return TRUE;
5744 }
5745 /* Fall through. */
5746 case MVE_CSEL:
5747 case MVE_CSNEG:
5748 if (arm_decode_field (given, 0, 3) == 0xd)
5749 return TRUE;
5750 /* CNEG. */
5751 else if (matched_insn == MVE_CSNEG)
5752 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5753 return TRUE;
5754 return FALSE;
5755
143275ea 5756 default:
66dcaa5d
AV		 5757 case MVE_VADD_FP_T1:
5758 case MVE_VADD_FP_T2:
5759 case MVE_VADD_VEC_T1:
143275ea
AV		 5760 return FALSE;
5761
5762 }
73cd51e5
AV		 5763}
5764
aef6d006
AV		 5765static void
5766print_mve_vld_str_addr (struct disassemble_info *info,
5767 unsigned long given,
5768 enum mve_instructions matched_insn)
5769{
5770 void *stream = info->stream;
5771 fprintf_ftype func = info->fprintf_func;
5772
5773 unsigned long p, w, gpr, imm, add, mod_imm;
5774
5775 imm = arm_decode_field (given, 0, 6);
5776 mod_imm = imm;
5777
5778 switch (matched_insn)
5779 {
5780 case MVE_VLDRB_T1:
5781 case MVE_VSTRB_T1:
5782 gpr = arm_decode_field (given, 16, 18);
5783 break;
5784
5785 case MVE_VLDRH_T2:
5786 case MVE_VSTRH_T2:
5787 gpr = arm_decode_field (given, 16, 18);
5788 mod_imm = imm << 1;
5789 break;
5790
5791 case MVE_VLDRH_T6:
5792 case MVE_VSTRH_T6:
5793 gpr = arm_decode_field (given, 16, 19);
5794 mod_imm = imm << 1;
5795 break;
5796
5797 case MVE_VLDRW_T7:
5798 case MVE_VSTRW_T7:
5799 gpr = arm_decode_field (given, 16, 19);
5800 mod_imm = imm << 2;
5801 break;
5802
5803 case MVE_VLDRB_T5:
5804 case MVE_VSTRB_T5:
5805 gpr = arm_decode_field (given, 16, 19);
5806 break;
5807
5808 default:
5809 return;
5810 }
5811
5812 p = arm_decode_field (given, 24, 24);
5813 w = arm_decode_field (given, 21, 21);
5814
5815 add = arm_decode_field (given, 23, 23);
5816
5817 char * add_sub;
5818
5819 /* Don't print anything for '+' as it is implied. */
5820 if (add == 1)
5821 add_sub = "";
5822 else
5823 add_sub = "-";
5824
5825 if (p == 1)
5826 {
5827 /* Offset mode. */
5828 if (w == 0)
5829 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5830 /* Pre-indexed mode. */
5831 else
5832 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5833 }
5834 else if ((p == 0) && (w == 1))
5835 /* Post-index mode. */
5836 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5837}
5838
73cd51e5
AV		 5839/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5840 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5841 this encoding is undefined. */
5842
5843static bfd_boolean
5844is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5845 enum mve_undefined *undefined_code)
5846{
5847 *undefined_code = UNDEF_NONE;
5848
9743db03
AV		 5849 switch (matched_insn)
5850 {
5851 case MVE_VDUP:
5852 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5853 {
5854 *undefined_code = UNDEF_SIZE_3;
5855 return TRUE;
5856 }
5857 else
5858 return FALSE;
5859
14b456f2
AV		 5860 case MVE_VQADD_T1:
5861 case MVE_VQSUB_T1:
f49bb598 5862 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5863 case MVE_VABD_VEC:
5864 case MVE_VADD_VEC_T1:
5865 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5866 case MVE_VQDMULH_T1:
5867 case MVE_VQRDMULH_T2:
9743db03
AV		 5868 case MVE_VRHADD:
5869 case MVE_VHADD_T1:
5870 case MVE_VHSUB_T1:
5871 if (arm_decode_field (given, 20, 21) == 3)
5872 {
5873 *undefined_code = UNDEF_SIZE_3;
5874 return TRUE;
5875 }
5876 else
5877 return FALSE;
5878
aef6d006
AV		 5879 case MVE_VLDRB_T1:
5880 if (arm_decode_field (given, 7, 8) == 3)
5881 {
5882 *undefined_code = UNDEF_SIZE_3;
5883 return TRUE;
5884 }
5885 else
5886 return FALSE;
5887
5888 case MVE_VLDRH_T2:
5889 if (arm_decode_field (given, 7, 8) <= 1)
5890 {
5891 *undefined_code = UNDEF_SIZE_LE_1;
5892 return TRUE;
5893 }
5894 else
5895 return FALSE;
5896
5897 case MVE_VSTRB_T1:
5898 if ((arm_decode_field (given, 7, 8) == 0))
5899 {
5900 *undefined_code = UNDEF_SIZE_0;
5901 return TRUE;
5902 }
5903 else
5904 return FALSE;
5905
5906 case MVE_VSTRH_T2:
5907 if ((arm_decode_field (given, 7, 8) <= 1))
5908 {
5909 *undefined_code = UNDEF_SIZE_LE_1;
5910 return TRUE;
5911 }
5912 else
5913 return FALSE;
5914
ef1576a1
AV		 5915 case MVE_VLDRB_GATHER_T1:
5916 if (arm_decode_field (given, 7, 8) == 3)
5917 {
5918 *undefined_code = UNDEF_SIZE_3;
5919 return TRUE;
5920 }
5921 else if ((arm_decode_field (given, 28, 28) == 0)
5922 && (arm_decode_field (given, 7, 8) == 0))
5923 {
5924 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5925 return TRUE;
5926 }
5927 else
5928 return FALSE;
5929
5930 case MVE_VLDRH_GATHER_T2:
5931 if (arm_decode_field (given, 7, 8) == 3)
5932 {
5933 *undefined_code = UNDEF_SIZE_3;
5934 return TRUE;
5935 }
5936 else if ((arm_decode_field (given, 28, 28) == 0)
5937 && (arm_decode_field (given, 7, 8) == 1))
5938 {
5939 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5940 return TRUE;
5941 }
5942 else if (arm_decode_field (given, 7, 8) == 0)
5943 {
5944 *undefined_code = UNDEF_SIZE_0;
5945 return TRUE;
5946 }
5947 else
5948 return FALSE;
5949
5950 case MVE_VLDRW_GATHER_T3:
5951 if (arm_decode_field (given, 7, 8) != 2)
5952 {
5953 *undefined_code = UNDEF_SIZE_NOT_2;
5954 return TRUE;
5955 }
5956 else if (arm_decode_field (given, 28, 28) == 0)
5957 {
5958 *undefined_code = UNDEF_NOT_UNSIGNED;
5959 return TRUE;
5960 }
5961 else
5962 return FALSE;
5963
5964 case MVE_VLDRD_GATHER_T4:
5965 if (arm_decode_field (given, 7, 8) != 3)
5966 {
5967 *undefined_code = UNDEF_SIZE_NOT_3;
5968 return TRUE;
5969 }
5970 else if (arm_decode_field (given, 28, 28) == 0)
5971 {
5972 *undefined_code = UNDEF_NOT_UNSIGNED;
5973 return TRUE;
5974 }
5975 else
5976 return FALSE;
5977
5978 case MVE_VSTRB_SCATTER_T1:
5979 if (arm_decode_field (given, 7, 8) == 3)
5980 {
5981 *undefined_code = UNDEF_SIZE_3;
5982 return TRUE;
5983 }
5984 else
5985 return FALSE;
5986
5987 case MVE_VSTRH_SCATTER_T2:
5988 {
5989 unsigned long size = arm_decode_field (given, 7, 8);
5990 if (size == 3)
5991 {
5992 *undefined_code = UNDEF_SIZE_3;
5993 return TRUE;
5994 }
5995 else if (size == 0)
5996 {
5997 *undefined_code = UNDEF_SIZE_0;
5998 return TRUE;
5999 }
6000 else
6001 return FALSE;
6002 }
6003
6004 case MVE_VSTRW_SCATTER_T3:
6005 if (arm_decode_field (given, 7, 8) != 2)
6006 {
6007 *undefined_code = UNDEF_SIZE_NOT_2;
6008 return TRUE;
6009 }
6010 else
6011 return FALSE;
6012
6013 case MVE_VSTRD_SCATTER_T4:
6014 if (arm_decode_field (given, 7, 8) != 3)
6015 {
6016 *undefined_code = UNDEF_SIZE_NOT_3;
6017 return TRUE;
6018 }
6019 else
6020 return FALSE;
6021
bf0b396d
AV		 6022 case MVE_VCVT_FP_FIX_VEC:
6023 {
6024 unsigned long imm6 = arm_decode_field (given, 16, 21);
6025 if ((imm6 & 0x20) == 0)
6026 {
6027 *undefined_code = UNDEF_VCVT_IMM6;
6028 return TRUE;
6029 }
6030
6031 if ((arm_decode_field (given, 9, 9) == 0)
6032 && ((imm6 & 0x30) == 0x20))
6033 {
6034 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6035 return TRUE;
6036 }
6037
6038 return FALSE;
6039 }
6040
f49bb598 6041 case MVE_VNEG_FP:
66dcaa5d 6042 case MVE_VABS_FP:
bf0b396d
AV		 6043 case MVE_VCVT_BETWEEN_FP_INT:
6044 case MVE_VCVT_FROM_FP_TO_INT:
6045 {
6046 unsigned long size = arm_decode_field (given, 18, 19);
6047 if (size == 0)
6048 {
6049 *undefined_code = UNDEF_SIZE_0;
6050 return TRUE;
6051 }
6052 else if (size == 3)
6053 {
6054 *undefined_code = UNDEF_SIZE_3;
6055 return TRUE;
6056 }
6057 else
6058 return FALSE;
6059 }
6060
c507f10b
AV		 6061 case MVE_VMOV_VEC_LANE_TO_GP:
6062 {
6063 unsigned long op1 = arm_decode_field (given, 21, 22);
6064 unsigned long op2 = arm_decode_field (given, 5, 6);
6065 unsigned long u = arm_decode_field (given, 23, 23);
6066
6067 if ((op2 == 0) && (u == 1))
6068 {
6069 if ((op1 == 0) || (op1 == 1))
6070 {
6071 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6072 return TRUE;
6073 }
6074 else
6075 return FALSE;
6076 }
6077 else if (op2 == 2)
6078 {
6079 if ((op1 == 0) || (op1 == 1))
6080 {
6081 *undefined_code = UNDEF_BAD_OP1_OP2;
6082 return TRUE;
6083 }
6084 else
6085 return FALSE;
6086 }
6087
6088 return FALSE;
6089 }
6090
6091 case MVE_VMOV_GP_TO_VEC_LANE:
6092 if (arm_decode_field (given, 5, 6) == 2)
6093 {
6094 unsigned long op1 = arm_decode_field (given, 21, 22);
6095 if ((op1 == 0) || (op1 == 1))
6096 {
6097 *undefined_code = UNDEF_BAD_OP1_OP2;
6098 return TRUE;
6099 }
6100 else
6101 return FALSE;
6102 }
6103 else
6104 return FALSE;
6105
6106 case MVE_VMOV_IMM_TO_VEC:
6107 if (arm_decode_field (given, 5, 5) == 0)
6108 {
6109 unsigned long cmode = arm_decode_field (given, 8, 11);
6110
6111 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6112 {
6113 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6114 return TRUE;
6115 }
6116 else
6117 return FALSE;
6118 }
6119 else
6120 return FALSE;
6121
ed63aa17 6122 case MVE_VSHLL_T2:
14925797
AV		 6123 case MVE_VMOVN:
6124 if (arm_decode_field (given, 18, 19) == 2)
6125 {
6126 *undefined_code = UNDEF_SIZE_2;
6127 return TRUE;
6128 }
6129 else
6130 return FALSE;
6131
d3b63143
AV		 6132 case MVE_VRMLALDAVH:
6133 case MVE_VMLADAV_T1:
6134 case MVE_VMLADAV_T2:
6135 case MVE_VMLALDAV:
6136 if ((arm_decode_field (given, 28, 28) == 1)
6137 && (arm_decode_field (given, 12, 12) == 1))
6138 {
6139 *undefined_code = UNDEF_XCHG_UNS;
6140 return TRUE;
6141 }
6142 else
6143 return FALSE;
6144
ed63aa17
AV		 6145 case MVE_VQSHRN:
6146 case MVE_VQSHRUN:
6147 case MVE_VSHLL_T1:
6148 case MVE_VSHRN:
6149 {
6150 unsigned long sz = arm_decode_field (given, 19, 20);
6151 if (sz == 1)
6152 return FALSE;
6153 else if ((sz & 2) == 2)
6154 return FALSE;
6155 else
6156 {
6157 *undefined_code = UNDEF_SIZE;
6158 return TRUE;
6159 }
6160 }
6161 break;
6162
6163 case MVE_VQSHL_T2:
6164 case MVE_VQSHLU_T3:
6165 case MVE_VRSHR:
6166 case MVE_VSHL_T1:
6167 case MVE_VSHR:
6168 case MVE_VSLI:
6169 case MVE_VSRI:
6170 {
6171 unsigned long sz = arm_decode_field (given, 19, 21);
6172 if ((sz & 7) == 1)
6173 return FALSE;
6174 else if ((sz & 6) == 2)
6175 return FALSE;
6176 else if ((sz & 4) == 4)
6177 return FALSE;
6178 else
6179 {
6180 *undefined_code = UNDEF_SIZE;
6181 return TRUE;
6182 }
6183 }
6184
6185 case MVE_VQRSHRN:
6186 case MVE_VQRSHRUN:
6187 if (arm_decode_field (given, 19, 20) == 0)
6188 {
6189 *undefined_code = UNDEF_SIZE_0;
6190 return TRUE;
6191 }
6192 else
6193 return FALSE;
6194
66dcaa5d
AV		 6195 case MVE_VABS_VEC:
6196 if (arm_decode_field (given, 18, 19) == 3)
6197 {
6198 *undefined_code = UNDEF_SIZE_3;
6199 return TRUE;
6200 }
6201 else
6202 return FALSE;
6203
14b456f2
AV		 6204 case MVE_VQNEG:
6205 case MVE_VQABS:
f49bb598 6206 case MVE_VNEG_VEC:
e523f101
AV		 6207 case MVE_VCLS:
6208 case MVE_VCLZ:
6209 if (arm_decode_field (given, 18, 19) == 3)
6210 {
6211 *undefined_code = UNDEF_SIZE_3;
6212 return TRUE;
6213 }
6214 else
6215 return FALSE;
6216
14b456f2
AV		 6217 case MVE_VREV16:
6218 if (arm_decode_field (given, 18, 19) == 0)
6219 return FALSE;
6220 else
6221 {
6222 *undefined_code = UNDEF_SIZE_NOT_0;
6223 return TRUE;
6224 }
6225
6226 case MVE_VREV32:
6227 {
6228 unsigned long size = arm_decode_field (given, 18, 19);
6229 if ((size & 2) == 2)
6230 {
6231 *undefined_code = UNDEF_SIZE_2;
6232 return TRUE;
6233 }
6234 else
6235 return FALSE;
6236 }
6237
6238 case MVE_VREV64:
6239 if (arm_decode_field (given, 18, 19) != 3)
6240 return FALSE;
6241 else
6242 {
6243 *undefined_code = UNDEF_SIZE_3;
6244 return TRUE;
6245 }
6246
9743db03
AV		 6247 default:
6248 return FALSE;
6249 }
73cd51e5
AV		 6250}
6251
6252/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6253 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6254 why this encoding is unpredictable. */
6255
6256static bfd_boolean
6257is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6258 enum mve_unpredictable *unpredictable_code)
6259{
6260 *unpredictable_code = UNPRED_NONE;
6261
143275ea
AV		 6262 switch (matched_insn)
6263 {
6264 case MVE_VCMP_FP_T2:
6265 case MVE_VPT_FP_T2:
6266 if ((arm_decode_field (given, 12, 12) == 0)
6267 && (arm_decode_field (given, 5, 5) == 1))
6268 {
6269 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6270 return TRUE;
6271 }
6272 else
6273 return FALSE;
73cd51e5 6274
143275ea
AV		 6275 case MVE_VPT_VEC_T4:
6276 case MVE_VPT_VEC_T5:
6277 case MVE_VPT_VEC_T6:
6278 case MVE_VCMP_VEC_T4:
6279 case MVE_VCMP_VEC_T5:
6280 case MVE_VCMP_VEC_T6:
6281 if (arm_decode_field (given, 0, 3) == 0xd)
6282 {
6283 *unpredictable_code = UNPRED_R13;
6284 return TRUE;
6285 }
6286 else
6287 return FALSE;
c1e26897 6288
9743db03
AV		 6289 case MVE_VDUP:
6290 {
6291 unsigned long gpr = arm_decode_field (given, 12, 15);
6292 if (gpr == 0xd)
6293 {
6294 *unpredictable_code = UNPRED_R13;
6295 return TRUE;
6296 }
6297 else if (gpr == 0xf)
6298 {
6299 *unpredictable_code = UNPRED_R15;
6300 return TRUE;
6301 }
6302
6303 return FALSE;
6304 }
6305
14b456f2
AV		 6306 case MVE_VQADD_T2:
6307 case MVE_VQSUB_T2:
f49bb598
AV		 6308 case MVE_VMUL_FP_T2:
6309 case MVE_VMUL_VEC_T2:
56858bea 6310 case MVE_VMLA:
e523f101 6311 case MVE_VBRSR:
66dcaa5d
AV		 6312 case MVE_VADD_FP_T2:
6313 case MVE_VSUB_FP_T2:
6314 case MVE_VADD_VEC_T2:
6315 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6316 case MVE_VQRSHL_T2:
6317 case MVE_VQSHL_T1:
6318 case MVE_VRSHL_T2:
6319 case MVE_VSHL_T2:
6320 case MVE_VSHLC:
d3b63143
AV		 6321 case MVE_VQDMLAH:
6322 case MVE_VQRDMLAH:
6323 case MVE_VQDMLASH:
6324 case MVE_VQRDMLASH:
6325 case MVE_VQDMULH_T3:
6326 case MVE_VQRDMULH_T4:
6327 case MVE_VMLAS:
9743db03
AV		 6328 case MVE_VFMA_FP_SCALAR:
6329 case MVE_VFMAS_FP_SCALAR:
6330 case MVE_VHADD_T2:
6331 case MVE_VHSUB_T2:
6332 {
6333 unsigned long gpr = arm_decode_field (given, 0, 3);
6334 if (gpr == 0xd)
6335 {
6336 *unpredictable_code = UNPRED_R13;
6337 return TRUE;
6338 }
6339 else if (gpr == 0xf)
6340 {
6341 *unpredictable_code = UNPRED_R15;
6342 return TRUE;
6343 }
6344
6345 return FALSE;
6346 }
6347
04d54ace
AV		 6348 case MVE_VLD2:
6349 case MVE_VST2:
6350 {
6351 unsigned long rn = arm_decode_field (given, 16, 19);
6352
6353 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6354 {
6355 *unpredictable_code = UNPRED_R13_AND_WB;
6356 return TRUE;
6357 }
6358
6359 if (rn == 0xf)
6360 {
6361 *unpredictable_code = UNPRED_R15;
6362 return TRUE;
6363 }
6364
6365 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6366 {
6367 *unpredictable_code = UNPRED_Q_GT_6;
6368 return TRUE;
6369 }
6370 else
6371 return FALSE;
6372 }
6373
6374 case MVE_VLD4:
6375 case MVE_VST4:
6376 {
6377 unsigned long rn = arm_decode_field (given, 16, 19);
6378
6379 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6380 {
6381 *unpredictable_code = UNPRED_R13_AND_WB;
6382 return TRUE;
6383 }
6384
6385 if (rn == 0xf)
6386 {
6387 *unpredictable_code = UNPRED_R15;
6388 return TRUE;
6389 }
6390
6391 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6392 {
6393 *unpredictable_code = UNPRED_Q_GT_4;
6394 return TRUE;
6395 }
6396 else
6397 return FALSE;
6398 }
6399
aef6d006
AV		 6400 case MVE_VLDRB_T5:
6401 case MVE_VLDRH_T6:
6402 case MVE_VLDRW_T7:
6403 case MVE_VSTRB_T5:
6404 case MVE_VSTRH_T6:
6405 case MVE_VSTRW_T7:
6406 {
6407 unsigned long rn = arm_decode_field (given, 16, 19);
6408
6409 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6410 {
6411 *unpredictable_code = UNPRED_R13_AND_WB;
6412 return TRUE;
6413 }
6414 else if (rn == 0xf)
6415 {
6416 *unpredictable_code = UNPRED_R15;
6417 return TRUE;
6418 }
6419 else
6420 return FALSE;
6421 }
6422
ef1576a1
AV		 6423 case MVE_VLDRB_GATHER_T1:
6424 if (arm_decode_field (given, 0, 0) == 1)
6425 {
6426 *unpredictable_code = UNPRED_OS;
6427 return TRUE;
6428 }
6429
6430 /* fall through. */
6431 /* To handle common code with T2-T4 variants. */
6432 case MVE_VLDRH_GATHER_T2:
6433 case MVE_VLDRW_GATHER_T3:
6434 case MVE_VLDRD_GATHER_T4:
6435 {
6436 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6437 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6438
6439 if (qd == qm)
6440 {
6441 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6442 return TRUE;
6443 }
6444
6445 if (arm_decode_field (given, 16, 19) == 0xf)
6446 {
6447 *unpredictable_code = UNPRED_R15;
6448 return TRUE;
6449 }
6450
6451 return FALSE;
6452 }
6453
6454 case MVE_VLDRW_GATHER_T5:
6455 case MVE_VLDRD_GATHER_T6:
6456 {
6457 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6458 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6459
6460 if (qd == qm)
6461 {
6462 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6463 return TRUE;
6464 }
6465 else
6466 return FALSE;
6467 }
6468
6469 case MVE_VSTRB_SCATTER_T1:
6470 if (arm_decode_field (given, 16, 19) == 0xf)
6471 {
6472 *unpredictable_code = UNPRED_R15;
6473 return TRUE;
6474 }
6475 else if (arm_decode_field (given, 0, 0) == 1)
6476 {
6477 *unpredictable_code = UNPRED_OS;
6478 return TRUE;
6479 }
6480 else
6481 return FALSE;
6482
6483 case MVE_VSTRH_SCATTER_T2:
6484 case MVE_VSTRW_SCATTER_T3:
6485 case MVE_VSTRD_SCATTER_T4:
6486 if (arm_decode_field (given, 16, 19) == 0xf)
6487 {
6488 *unpredictable_code = UNPRED_R15;
6489 return TRUE;
6490 }
6491 else
6492 return FALSE;
6493
c507f10b
AV		 6494 case MVE_VMOV2_VEC_LANE_TO_GP:
6495 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6496 case MVE_VCVT_BETWEEN_FP_INT:
6497 case MVE_VCVT_FROM_FP_TO_INT:
6498 {
6499 unsigned long rt = arm_decode_field (given, 0, 3);
6500 unsigned long rt2 = arm_decode_field (given, 16, 19);
6501
6502 if ((rt == 0xd) || (rt2 == 0xd))
6503 {
6504 *unpredictable_code = UNPRED_R13;
6505 return TRUE;
6506 }
6507 else if ((rt == 0xf) || (rt2 == 0xf))
6508 {
6509 *unpredictable_code = UNPRED_R15;
6510 return TRUE;
6511 }
6512 else if (rt == rt2)
6513 {
6514 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6515 return TRUE;
6516 }
6517
6518 return FALSE;
6519 }
6520
56858bea
AV		 6521 case MVE_VMAXV:
6522 case MVE_VMAXAV:
6523 case MVE_VMAXNMV_FP:
6524 case MVE_VMAXNMAV_FP:
6525 case MVE_VMINNMV_FP:
6526 case MVE_VMINNMAV_FP:
6527 case MVE_VMINV:
6528 case MVE_VMINAV:
66dcaa5d 6529 case MVE_VABAV:
c507f10b
AV		 6530 case MVE_VMOV_HFP_TO_GP:
6531 case MVE_VMOV_GP_TO_VEC_LANE:
6532 case MVE_VMOV_VEC_LANE_TO_GP:
6533 {
6534 unsigned long rda = arm_decode_field (given, 12, 15);
6535 if (rda == 0xd)
6536 {
6537 *unpredictable_code = UNPRED_R13;
6538 return TRUE;
6539 }
6540 else if (rda == 0xf)
6541 {
6542 *unpredictable_code = UNPRED_R15;
6543 return TRUE;
6544 }
6545
6546 return FALSE;
6547 }
6548
d3b63143
AV		 6549 case MVE_VQRDMLADH:
6550 case MVE_VQDMLSDH:
6551 case MVE_VQRDMLSDH:
6552 case MVE_VQDMLADH:
14925797
AV		 6553 case MVE_VMULL_INT:
6554 {
6555 unsigned long Qd;
6556 unsigned long Qm;
6557 unsigned long Qn;
6558
6559 if (arm_decode_field (given, 20, 21) == 2)
6560 {
6561 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6562 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6563 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6564
6565 if ((Qd == Qn) || (Qd == Qm))
6566 {
6567 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6568 return TRUE;
6569 }
6570 else
6571 return FALSE;
6572 }
6573 else
6574 return FALSE;
6575 }
6576
897b9bbc 6577 case MVE_VCMUL_FP:
14925797
AV		 6578 case MVE_VQDMULL_T1:
6579 {
6580 unsigned long Qd;
6581 unsigned long Qm;
6582 unsigned long Qn;
6583
6584 if (arm_decode_field (given, 28, 28) == 1)
6585 {
6586 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6587 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6588 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6589
6590 if ((Qd == Qn) || (Qd == Qm))
6591 {
6592 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6593 return TRUE;
6594 }
6595 else
6596 return FALSE;
6597 }
6598 else
6599 return FALSE;
6600 }
6601
6602 case MVE_VQDMULL_T2:
6603 {
6604 unsigned long gpr = arm_decode_field (given, 0, 3);
6605 if (gpr == 0xd)
6606 {
6607 *unpredictable_code = UNPRED_R13;
6608 return TRUE;
6609 }
6610 else if (gpr == 0xf)
6611 {
6612 *unpredictable_code = UNPRED_R15;
6613 return TRUE;
6614 }
6615
6616 if (arm_decode_field (given, 28, 28) == 1)
6617 {
6618 unsigned long Qd
6619 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6620 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6621
a9d96ab9 6622 if (Qd == Qn)
14925797
AV		 6623 {
6624 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6625 return TRUE;
6626 }
6627 else
6628 return FALSE;
6629 }
6630
6631 return FALSE;
6632 }
6633
d3b63143
AV		 6634 case MVE_VMLSLDAV:
6635 case MVE_VRMLSLDAVH:
6636 case MVE_VMLALDAV:
6637 case MVE_VADDLV:
6638 if (arm_decode_field (given, 20, 22) == 6)
6639 {
6640 *unpredictable_code = UNPRED_R13;
6641 return TRUE;
6642 }
6643 else
6644 return FALSE;
6645
1c8f2df8
AV		 6646 case MVE_VDWDUP:
6647 case MVE_VIWDUP:
6648 if (arm_decode_field (given, 1, 3) == 6)
6649 {
6650 *unpredictable_code = UNPRED_R13;
6651 return TRUE;
6652 }
6653 else
6654 return FALSE;
6655
897b9bbc
AV		 6656 case MVE_VCADD_VEC:
6657 case MVE_VHCADD:
6658 {
6659 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6660 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6661 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6662 {
6663 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6664 return TRUE;
6665 }
6666 else
6667 return FALSE;
6668 }
6669
6670 case MVE_VCADD_FP:
6671 {
6672 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6673 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6674 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6675 {
6676 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6677 return TRUE;
6678 }
6679 else
6680 return FALSE;
6681 }
6682
6683 case MVE_VCMLA_FP:
6684 {
6685 unsigned long Qda;
6686 unsigned long Qm;
6687 unsigned long Qn;
6688
6689 if (arm_decode_field (given, 20, 20) == 1)
6690 {
6691 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6692 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6693 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6694
6695 if ((Qda == Qn) || (Qda == Qm))
6696 {
6697 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6698 return TRUE;
6699 }
6700 else
6701 return FALSE;
6702 }
6703 else
6704 return FALSE;
6705
6706 }
6707
e523f101
AV		 6708 case MVE_VCTP:
6709 if (arm_decode_field (given, 16, 19) == 0xd)
6710 {
6711 *unpredictable_code = UNPRED_R13;
6712 return TRUE;
6713 }
6714 else
6715 return FALSE;
6716
14b456f2
AV		 6717 case MVE_VREV64:
6718 {
6719 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6720 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6721
6722 if (qd == qm)
6723 {
6724 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6725 return TRUE;
6726 }
6727 else
6728 return FALSE;
6729 }
6730
23d00a41
SD		 6731 case MVE_LSLL:
6732 case MVE_LSLLI:
6733 case MVE_LSRL:
6734 case MVE_ASRL:
6735 case MVE_ASRLI:
6736 case MVE_UQSHLL:
6737 case MVE_UQRSHLL:
6738 case MVE_URSHRL:
6739 case MVE_SRSHRL:
6740 case MVE_SQSHLL:
6741 case MVE_SQRSHRL:
6742 {
6743 unsigned long gpr = arm_decode_field (given, 9, 11);
6744 gpr = ((gpr << 1) | 1);
6745 if (gpr == 0xd)
6746 {
6747 *unpredictable_code = UNPRED_R13;
6748 return TRUE;
6749 }
6750 else if (gpr == 0xf)
6751 {
6752 *unpredictable_code = UNPRED_R15;
6753 return TRUE;
6754 }
6755
6756 return FALSE;
6757 }
6758
143275ea
AV		 6759 default:
6760 return FALSE;
6761 }
6762}
c1e26897 6763
c507f10b
AV		 6764static void
6765print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6766{
6767 unsigned long op1 = arm_decode_field (given, 21, 22);
6768 unsigned long op2 = arm_decode_field (given, 5, 6);
6769 unsigned long h = arm_decode_field (given, 16, 16);
6770 unsigned long index, esize, targetBeat, idx;
6771 void *stream = info->stream;
6772 fprintf_ftype func = info->fprintf_func;
6773
6774 if ((op1 & 0x2) == 0x2)
6775 {
6776 index = op2;
6777 esize = 8;
6778 }
6779 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6780 {
6781 index = op2 >> 1;
6782 esize = 16;
6783 }
6784 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6785 {
6786 index = 0;
6787 esize = 32;
6788 }
6789 else
6790 {
6791 func (stream, "<undefined index>");
6792 return;
6793 }
6794
6795 targetBeat = (op1 & 0x1) | (h << 1);
6796 idx = index + targetBeat * (32/esize);
6797
6798 func (stream, "%lu", idx);
6799}
6800
6801/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6802 in length and integer of floating-point type. */
6803static void
6804print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6805 unsigned int ibit_loc, const struct mopcode32 *insn)
6806{
6807 int bits = 0;
6808 int cmode = (given >> 8) & 0xf;
6809 int op = (given >> 5) & 0x1;
6810 unsigned long value = 0, hival = 0;
6811 unsigned shift;
6812 int size = 0;
6813 int isfloat = 0;
6814 void *stream = info->stream;
6815 fprintf_ftype func = info->fprintf_func;
6816
6817 /* On Neon the 'i' bit is at bit 24, on mve it is
6818 at bit 28. */
6819 bits |= ((given >> ibit_loc) & 1) << 7;
6820 bits |= ((given >> 16) & 7) << 4;
6821 bits |= ((given >> 0) & 15) << 0;
6822
6823 if (cmode < 8)
6824 {
6825 shift = (cmode >> 1) & 3;
6826 value = (unsigned long) bits << (8 * shift);
6827 size = 32;
6828 }
6829 else if (cmode < 12)
6830 {
6831 shift = (cmode >> 1) & 1;
6832 value = (unsigned long) bits << (8 * shift);
6833 size = 16;
6834 }
6835 else if (cmode < 14)
6836 {
6837 shift = (cmode & 1) + 1;
6838 value = (unsigned long) bits << (8 * shift);
6839 value |= (1ul << (8 * shift)) - 1;
6840 size = 32;
6841 }
6842 else if (cmode == 14)
6843 {
6844 if (op)
6845 {
6846 /* Bit replication into bytes. */
6847 int ix;
6848 unsigned long mask;
6849
6850 value = 0;
6851 hival = 0;
6852 for (ix = 7; ix >= 0; ix--)
6853 {
6854 mask = ((bits >> ix) & 1) ? 0xff : 0;
6855 if (ix <= 3)
6856 value = (value << 8) | mask;
6857 else
6858 hival = (hival << 8) | mask;
6859 }
6860 size = 64;
6861 }
6862 else
6863 {
6864 /* Byte replication. */
6865 value = (unsigned long) bits;
6866 size = 8;
6867 }
6868 }
6869 else if (!op)
6870 {
6871 /* Floating point encoding. */
6872 int tmp;
6873
6874 value = (unsigned long) (bits & 0x7f) << 19;
6875 value |= (unsigned long) (bits & 0x80) << 24;
6876 tmp = bits & 0x40 ? 0x3c : 0x40;
6877 value |= (unsigned long) tmp << 24;
6878 size = 32;
6879 isfloat = 1;
6880 }
6881 else
6882 {
6883 func (stream, "<illegal constant %.8x:%x:%x>",
6884 bits, cmode, op);
6885 size = 32;
6886 return;
6887 }
6888
6889 // printU determines whether the immediate value should be printed as
6890 // unsigned.
6891 unsigned printU = 0;
6892 switch (insn->mve_op)
6893 {
6894 default:
6895 break;
6896 // We want this for instructions that don't have a 'signed' type
6897 case MVE_VBIC_IMM:
6898 case MVE_VORR_IMM:
6899 case MVE_VMVN_IMM:
6900 case MVE_VMOV_IMM_TO_VEC:
6901 printU = 1;
6902 break;
6903 }
6904 switch (size)
6905 {
6906 case 8:
6907 func (stream, "#%ld\t; 0x%.2lx", value, value);
6908 break;
6909
6910 case 16:
6911 func (stream,
6912 printU
6913 ? "#%lu\t; 0x%.4lx"
6914 : "#%ld\t; 0x%.4lx", value, value);
6915 break;
6916
6917 case 32:
6918 if (isfloat)
6919 {
6920 unsigned char valbytes[4];
6921 double fvalue;
6922
6923 /* Do this a byte at a time so we don't have to
6924 worry about the host's endianness. */
6925 valbytes[0] = value & 0xff;
6926 valbytes[1] = (value >> 8) & 0xff;
6927 valbytes[2] = (value >> 16) & 0xff;
6928 valbytes[3] = (value >> 24) & 0xff;
6929
6930 floatformat_to_double
6931 (& floatformat_ieee_single_little, valbytes,
6932 & fvalue);
6933
6934 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6935 value);
6936 }
6937 else
6938 func (stream,
6939 printU
6940 ? "#%lu\t; 0x%.8lx"
6941 : "#%ld\t; 0x%.8lx",
6942 (long) (((value & 0x80000000L) != 0)
6943 && !printU
6944 ? value | ~0xffffffffL : value),
6945 value);
6946 break;
6947
6948 case 64:
6949 func (stream, "#0x%.8lx%.8lx", hival, value);
6950 break;
6951
6952 default:
6953 abort ();
6954 }
6955
6956}
6957
73cd51e5
AV		 6958static void
6959print_mve_undefined (struct disassemble_info *info,
6960 enum mve_undefined undefined_code)
6961{
6962 void *stream = info->stream;
6963 fprintf_ftype func = info->fprintf_func;
6964
6965 func (stream, "\t\tundefined instruction: ");
6966
6967 switch (undefined_code)
6968 {
ed63aa17
AV		 6969 case UNDEF_SIZE:
6970 func (stream, "illegal size");
6971 break;
6972
aef6d006
AV		 6973 case UNDEF_SIZE_0:
6974 func (stream, "size equals zero");
6975 break;
6976
c507f10b
AV		 6977 case UNDEF_SIZE_2:
6978 func (stream, "size equals two");
6979 break;
6980
9743db03
AV		 6981 case UNDEF_SIZE_3:
6982 func (stream, "size equals three");
6983 break;
6984
aef6d006
AV		 6985 case UNDEF_SIZE_LE_1:
6986 func (stream, "size <= 1");
6987 break;
6988
14b456f2
AV		 6989 case UNDEF_SIZE_NOT_0:
6990 func (stream, "size not equal to 0");
6991 break;
6992
ef1576a1
AV		 6993 case UNDEF_SIZE_NOT_2:
6994 func (stream, "size not equal to 2");
6995 break;
6996
6997 case UNDEF_SIZE_NOT_3:
6998 func (stream, "size not equal to 3");
6999 break;
7000
7001 case UNDEF_NOT_UNS_SIZE_0:
7002 func (stream, "not unsigned and size = zero");
7003 break;
7004
7005 case UNDEF_NOT_UNS_SIZE_1:
7006 func (stream, "not unsigned and size = one");
7007 break;
7008
7009 case UNDEF_NOT_UNSIGNED:
7010 func (stream, "not unsigned");
7011 break;
7012
bf0b396d
AV		 7013 case UNDEF_VCVT_IMM6:
7014 func (stream, "invalid imm6");
7015 break;
7016
7017 case UNDEF_VCVT_FSI_IMM6:
7018 func (stream, "fsi = 0 and invalid imm6");
7019 break;
7020
c507f10b
AV		 7021 case UNDEF_BAD_OP1_OP2:
7022 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7023 break;
7024
7025 case UNDEF_BAD_U_OP1_OP2:
7026 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7027 break;
7028
7029 case UNDEF_OP_0_BAD_CMODE:
7030 func (stream, "op field equal 0 and bad cmode");
7031 break;
7032
d3b63143
AV		 7033 case UNDEF_XCHG_UNS:
7034 func (stream, "exchange and unsigned together");
7035 break;
7036
73cd51e5
AV		 7037 case UNDEF_NONE:
7038 break;
7039 }
7040
7041}
7042
7043static void
7044print_mve_unpredictable (struct disassemble_info *info,
7045 enum mve_unpredictable unpredict_code)
7046{
7047 void *stream = info->stream;
7048 fprintf_ftype func = info->fprintf_func;
7049
7050 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7051
7052 switch (unpredict_code)
7053 {
7054 case UNPRED_IT_BLOCK:
7055 func (stream, "mve instruction in it block");
7056 break;
7057
143275ea
AV		 7058 case UNPRED_FCA_0_FCB_1:
7059 func (stream, "condition bits, fca = 0 and fcb = 1");
7060 break;
7061
7062 case UNPRED_R13:
7063 func (stream, "use of r13 (sp)");
7064 break;
7065
9743db03
AV		 7066 case UNPRED_R15:
7067 func (stream, "use of r15 (pc)");
7068 break;
7069
04d54ace
AV		 7070 case UNPRED_Q_GT_4:
7071 func (stream, "start register block > r4");
7072 break;
7073
7074 case UNPRED_Q_GT_6:
7075 func (stream, "start register block > r6");
7076 break;
7077
7078 case UNPRED_R13_AND_WB:
7079 func (stream, "use of r13 and write back");
7080 break;
7081
ef1576a1
AV		 7082 case UNPRED_Q_REGS_EQUAL:
7083 func (stream,
7084 "same vector register used for destination and other operand");
7085 break;
7086
7087 case UNPRED_OS:
7088 func (stream, "use of offset scaled");
7089 break;
7090
bf0b396d
AV		 7091 case UNPRED_GP_REGS_EQUAL:
7092 func (stream, "same general-purpose register used for both operands");
7093 break;
7094
c507f10b
AV		 7095 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7096 func (stream, "use of identical q registers and size = 1");
7097 break;
7098
7099 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7100 func (stream, "use of identical q registers and size = 1");
7101 break;
7102
73cd51e5
AV		 7103 case UNPRED_NONE:
7104 break;
7105 }
7106}
7107
04d54ace
AV		 7108/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7109
7110static void
7111print_mve_register_blocks (struct disassemble_info *info,
7112 unsigned long given,
7113 enum mve_instructions matched_insn)
7114{
7115 void *stream = info->stream;
7116 fprintf_ftype func = info->fprintf_func;
7117
7118 unsigned long q_reg_start = arm_decode_field_multiple (given,
7119 13, 15,
7120 22, 22);
7121 switch (matched_insn)
7122 {
7123 case MVE_VLD2:
7124 case MVE_VST2:
7125 if (q_reg_start <= 6)
7126 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7127 else
7128 func (stream, "<illegal reg q%ld>", q_reg_start);
7129 break;
7130
7131 case MVE_VLD4:
7132 case MVE_VST4:
7133 if (q_reg_start <= 4)
7134 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7135 q_reg_start + 1, q_reg_start + 2,
7136 q_reg_start + 3);
7137 else
7138 func (stream, "<illegal reg q%ld>", q_reg_start);
7139 break;
7140
7141 default:
7142 break;
7143 }
7144}
7145
bf0b396d
AV		 7146static void
7147print_mve_rounding_mode (struct disassemble_info *info,
7148 unsigned long given,
7149 enum mve_instructions matched_insn)
7150{
7151 void *stream = info->stream;
7152 fprintf_ftype func = info->fprintf_func;
7153
7154 switch (matched_insn)
7155 {
7156 case MVE_VCVT_FROM_FP_TO_INT:
7157 {
7158 switch (arm_decode_field (given, 8, 9))
7159 {
7160 case 0:
7161 func (stream, "a");
7162 break;
7163
7164 case 1:
7165 func (stream, "n");
7166 break;
7167
7168 case 2:
7169 func (stream, "p");
7170 break;
7171
7172 case 3:
7173 func (stream, "m");
7174 break;
7175
7176 default:
7177 break;
7178 }
7179 }
7180 break;
7181
7182 case MVE_VRINT_FP:
7183 {
7184 switch (arm_decode_field (given, 7, 9))
7185 {
7186 case 0:
7187 func (stream, "n");
7188 break;
7189
7190 case 1:
7191 func (stream, "x");
7192 break;
7193
7194 case 2:
7195 func (stream, "a");
7196 break;
7197
7198 case 3:
7199 func (stream, "z");
7200 break;
7201
7202 case 5:
7203 func (stream, "m");
7204 break;
7205
7206 case 7:
7207 func (stream, "p");
7208
7209 case 4:
7210 case 6:
7211 default:
7212 break;
7213 }
7214 }
7215 break;
7216
7217 default:
7218 break;
7219 }
7220}
7221
7222static void
7223print_mve_vcvt_size (struct disassemble_info *info,
7224 unsigned long given,
7225 enum mve_instructions matched_insn)
7226{
7227 unsigned long mode = 0;
7228 void *stream = info->stream;
7229 fprintf_ftype func = info->fprintf_func;
7230
7231 switch (matched_insn)
7232 {
7233 case MVE_VCVT_FP_FIX_VEC:
7234 {
7235 mode = (((given & 0x200) >> 7)
7236 | ((given & 0x10000000) >> 27)
7237 | ((given & 0x100) >> 8));
7238
7239 switch (mode)
7240 {
7241 case 0:
7242 func (stream, "f16.s16");
7243 break;
7244
7245 case 1:
7246 func (stream, "s16.f16");
7247 break;
7248
7249 case 2:
7250 func (stream, "f16.u16");
7251 break;
7252
7253 case 3:
7254 func (stream, "u16.f16");
7255 break;
7256
7257 case 4:
7258 func (stream, "f32.s32");
7259 break;
7260
7261 case 5:
7262 func (stream, "s32.f32");
7263 break;
7264
7265 case 6:
7266 func (stream, "f32.u32");
7267 break;
7268
7269 case 7:
7270 func (stream, "u32.f32");
7271 break;
7272
7273 default:
7274 break;
7275 }
7276 break;
7277 }
7278 case MVE_VCVT_BETWEEN_FP_INT:
7279 {
7280 unsigned long size = arm_decode_field (given, 18, 19);
7281 unsigned long op = arm_decode_field (given, 7, 8);
7282
7283 if (size == 1)
7284 {
7285 switch (op)
7286 {
7287 case 0:
7288 func (stream, "f16.s16");
7289 break;
7290
7291 case 1:
7292 func (stream, "f16.u16");
7293 break;
7294
7295 case 2:
7296 func (stream, "s16.f16");
7297 break;
7298
7299 case 3:
7300 func (stream, "u16.f16");
7301 break;
7302
7303 default:
7304 break;
7305 }
7306 }
7307 else if (size == 2)
7308 {
7309 switch (op)
7310 {
7311 case 0:
7312 func (stream, "f32.s32");
7313 break;
7314
7315 case 1:
7316 func (stream, "f32.u32");
7317 break;
7318
7319 case 2:
7320 func (stream, "s32.f32");
7321 break;
7322
7323 case 3:
7324 func (stream, "u32.f32");
7325 break;
7326 }
7327 }
7328 }
7329 break;
7330
7331 case MVE_VCVT_FP_HALF_FP:
7332 {
7333 unsigned long op = arm_decode_field (given, 28, 28);
7334 if (op == 0)
7335 func (stream, "f16.f32");
7336 else if (op == 1)
7337 func (stream, "f32.f16");
7338 }
7339 break;
7340
7341 case MVE_VCVT_FROM_FP_TO_INT:
7342 {
7343 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7344
7345 switch (size)
7346 {
7347 case 2:
7348 func (stream, "s16.f16");
7349 break;
7350
7351 case 3:
7352 func (stream, "u16.f16");
7353 break;
7354
7355 case 4:
7356 func (stream, "s32.f32");
7357 break;
7358
7359 case 5:
7360 func (stream, "u32.f32");
7361 break;
7362
7363 default:
7364 break;
7365 }
7366 }
7367 break;
7368
7369 default:
7370 break;
7371 }
7372}
7373
897b9bbc
AV		 7374static void
7375print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7376 unsigned long rot_width)
7377{
7378 void *stream = info->stream;
7379 fprintf_ftype func = info->fprintf_func;
7380
7381 if (rot_width == 1)
7382 {
7383 switch (rot)
7384 {
7385 case 0:
7386 func (stream, "90");
7387 break;
7388 case 1:
7389 func (stream, "270");
7390 break;
7391 default:
7392 break;
7393 }
7394 }
7395 else if (rot_width == 2)
7396 {
7397 switch (rot)
7398 {
7399 case 0:
7400 func (stream, "0");
7401 break;
7402 case 1:
7403 func (stream, "90");
7404 break;
7405 case 2:
7406 func (stream, "180");
7407 break;
7408 case 3:
7409 func (stream, "270");
7410 break;
7411 default:
7412 break;
7413 }
7414 }
7415}
7416
143275ea
AV		 7417static void
7418print_instruction_predicate (struct disassemble_info *info)
7419{
7420 void *stream = info->stream;
7421 fprintf_ftype func = info->fprintf_func;
7422
7423 if (vpt_block_state.next_pred_state == PRED_THEN)
7424 func (stream, "t");
7425 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7426 func (stream, "e");
7427}
7428
7429static void
7430print_mve_size (struct disassemble_info *info,
7431 unsigned long size,
7432 enum mve_instructions matched_insn)
7433{
7434 void *stream = info->stream;
7435 fprintf_ftype func = info->fprintf_func;
7436
7437 switch (matched_insn)
7438 {
66dcaa5d
AV		 7439 case MVE_VABAV:
7440 case MVE_VABD_VEC:
7441 case MVE_VABS_FP:
7442 case MVE_VABS_VEC:
7443 case MVE_VADD_VEC_T1:
7444 case MVE_VADD_VEC_T2:
d3b63143 7445 case MVE_VADDV:
e523f101 7446 case MVE_VBRSR:
897b9bbc 7447 case MVE_VCADD_VEC:
e523f101
AV		 7448 case MVE_VCLS:
7449 case MVE_VCLZ:
143275ea
AV		 7450 case MVE_VCMP_VEC_T1:
7451 case MVE_VCMP_VEC_T2:
7452 case MVE_VCMP_VEC_T3:
7453 case MVE_VCMP_VEC_T4:
7454 case MVE_VCMP_VEC_T5:
7455 case MVE_VCMP_VEC_T6:
e523f101 7456 case MVE_VCTP:
1c8f2df8
AV		 7457 case MVE_VDDUP:
7458 case MVE_VDWDUP:
9743db03
AV		 7459 case MVE_VHADD_T1:
7460 case MVE_VHADD_T2:
897b9bbc 7461 case MVE_VHCADD:
9743db03
AV		 7462 case MVE_VHSUB_T1:
7463 case MVE_VHSUB_T2:
1c8f2df8
AV		 7464 case MVE_VIDUP:
7465 case MVE_VIWDUP:
04d54ace
AV		 7466 case MVE_VLD2:
7467 case MVE_VLD4:
ef1576a1
AV		 7468 case MVE_VLDRB_GATHER_T1:
7469 case MVE_VLDRH_GATHER_T2:
7470 case MVE_VLDRW_GATHER_T3:
7471 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7472 case MVE_VLDRB_T1:
7473 case MVE_VLDRH_T2:
56858bea
AV		 7474 case MVE_VMAX:
7475 case MVE_VMAXA:
7476 case MVE_VMAXV:
7477 case MVE_VMAXAV:
7478 case MVE_VMIN:
7479 case MVE_VMINA:
7480 case MVE_VMINV:
7481 case MVE_VMINAV:
7482 case MVE_VMLA:
d3b63143 7483 case MVE_VMLAS:
f49bb598
AV		 7484 case MVE_VMUL_VEC_T1:
7485 case MVE_VMUL_VEC_T2:
7486 case MVE_VMULH:
7487 case MVE_VRMULH:
7488 case MVE_VMULL_INT:
7489 case MVE_VNEG_FP:
7490 case MVE_VNEG_VEC:
143275ea
AV		 7491 case MVE_VPT_VEC_T1:
7492 case MVE_VPT_VEC_T2:
7493 case MVE_VPT_VEC_T3:
7494 case MVE_VPT_VEC_T4:
7495 case MVE_VPT_VEC_T5:
7496 case MVE_VPT_VEC_T6:
14b456f2
AV		 7497 case MVE_VQABS:
7498 case MVE_VQADD_T1:
7499 case MVE_VQADD_T2:
d3b63143
AV		 7500 case MVE_VQDMLADH:
7501 case MVE_VQRDMLADH:
7502 case MVE_VQDMLAH:
7503 case MVE_VQRDMLAH:
7504 case MVE_VQDMLASH:
7505 case MVE_VQRDMLASH:
7506 case MVE_VQDMLSDH:
7507 case MVE_VQRDMLSDH:
7508 case MVE_VQDMULH_T1:
7509 case MVE_VQRDMULH_T2:
7510 case MVE_VQDMULH_T3:
7511 case MVE_VQRDMULH_T4:
14b456f2 7512 case MVE_VQNEG:
ed63aa17
AV		 7513 case MVE_VQRSHL_T1:
7514 case MVE_VQRSHL_T2:
7515 case MVE_VQSHL_T1:
7516 case MVE_VQSHL_T4:
14b456f2
AV		 7517 case MVE_VQSUB_T1:
7518 case MVE_VQSUB_T2:
7519 case MVE_VREV32:
7520 case MVE_VREV64:
9743db03 7521 case MVE_VRHADD:
bf0b396d 7522 case MVE_VRINT_FP:
ed63aa17
AV		 7523 case MVE_VRSHL_T1:
7524 case MVE_VRSHL_T2:
7525 case MVE_VSHL_T2:
7526 case MVE_VSHL_T3:
7527 case MVE_VSHLL_T2:
04d54ace
AV		 7528 case MVE_VST2:
7529 case MVE_VST4:
ef1576a1
AV		 7530 case MVE_VSTRB_SCATTER_T1:
7531 case MVE_VSTRH_SCATTER_T2:
7532 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7533 case MVE_VSTRB_T1:
7534 case MVE_VSTRH_T2:
66dcaa5d
AV		 7535 case MVE_VSUB_VEC_T1:
7536 case MVE_VSUB_VEC_T2:
143275ea
AV		 7537 if (size <= 3)
7538 func (stream, "%s", mve_vec_sizename[size]);
7539 else
7540 func (stream, "<undef size>");
7541 break;
7542
66dcaa5d
AV		 7543 case MVE_VABD_FP:
7544 case MVE_VADD_FP_T1:
7545 case MVE_VADD_FP_T2:
7546 case MVE_VSUB_FP_T1:
7547 case MVE_VSUB_FP_T2:
143275ea
AV		 7548 case MVE_VCMP_FP_T1:
7549 case MVE_VCMP_FP_T2:
9743db03
AV		 7550 case MVE_VFMA_FP_SCALAR:
7551 case MVE_VFMA_FP:
7552 case MVE_VFMS_FP:
7553 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7554 case MVE_VMAXNM_FP:
7555 case MVE_VMAXNMA_FP:
7556 case MVE_VMAXNMV_FP:
7557 case MVE_VMAXNMAV_FP:
7558 case MVE_VMINNM_FP:
7559 case MVE_VMINNMA_FP:
7560 case MVE_VMINNMV_FP:
7561 case MVE_VMINNMAV_FP:
f49bb598
AV		 7562 case MVE_VMUL_FP_T1:
7563 case MVE_VMUL_FP_T2:
143275ea
AV		 7564 case MVE_VPT_FP_T1:
7565 case MVE_VPT_FP_T2:
7566 if (size == 0)
7567 func (stream, "32");
7568 else if (size == 1)
7569 func (stream, "16");
7570 break;
7571
897b9bbc
AV		 7572 case MVE_VCADD_FP:
7573 case MVE_VCMLA_FP:
7574 case MVE_VCMUL_FP:
d3b63143
AV		 7575 case MVE_VMLADAV_T1:
7576 case MVE_VMLALDAV:
7577 case MVE_VMLSDAV_T1:
7578 case MVE_VMLSLDAV:
14925797
AV		 7579 case MVE_VMOVN:
7580 case MVE_VQDMULL_T1:
7581 case MVE_VQDMULL_T2:
7582 case MVE_VQMOVN:
7583 case MVE_VQMOVUN:
7584 if (size == 0)
7585 func (stream, "16");
7586 else if (size == 1)
7587 func (stream, "32");
7588 break;
7589
7590 case MVE_VMOVL:
7591 if (size == 1)
7592 func (stream, "8");
7593 else if (size == 2)
7594 func (stream, "16");
7595 break;
7596
9743db03
AV		 7597 case MVE_VDUP:
7598 switch (size)
7599 {
7600 case 0:
7601 func (stream, "32");
7602 break;
7603 case 1:
7604 func (stream, "16");
7605 break;
7606 case 2:
7607 func (stream, "8");
7608 break;
7609 default:
7610 break;
7611 }
7612 break;
7613
c507f10b
AV		 7614 case MVE_VMOV_GP_TO_VEC_LANE:
7615 case MVE_VMOV_VEC_LANE_TO_GP:
7616 switch (size)
7617 {
7618 case 0: case 4:
7619 func (stream, "32");
7620 break;
7621
7622 case 1: case 3:
7623 case 5: case 7:
7624 func (stream, "16");
7625 break;
7626
7627 case 8: case 9: case 10: case 11:
7628 case 12: case 13: case 14: case 15:
7629 func (stream, "8");
7630 break;
7631
7632 default:
7633 break;
7634 }
7635 break;
7636
7637 case MVE_VMOV_IMM_TO_VEC:
7638 switch (size)
7639 {
7640 case 0: case 4: case 8:
7641 case 12: case 24: case 26:
7642 func (stream, "i32");
7643 break;
7644 case 16: case 20:
7645 func (stream, "i16");
7646 break;
7647 case 28:
7648 func (stream, "i8");
7649 break;
7650 case 29:
7651 func (stream, "i64");
7652 break;
7653 case 30:
7654 func (stream, "f32");
7655 break;
7656 default:
7657 break;
7658 }
7659 break;
7660
14925797
AV		 7661 case MVE_VMULL_POLY:
7662 if (size == 0)
7663 func (stream, "p8");
7664 else if (size == 1)
7665 func (stream, "p16");
7666 break;
7667
c507f10b
AV		 7668 case MVE_VMVN_IMM:
7669 switch (size)
7670 {
7671 case 0: case 2: case 4:
7672 case 6: case 12: case 13:
7673 func (stream, "32");
7674 break;
7675
7676 case 8: case 10:
7677 func (stream, "16");
7678 break;
7679
7680 default:
7681 break;
7682 }
7683 break;
7684
7685 case MVE_VBIC_IMM:
7686 case MVE_VORR_IMM:
7687 switch (size)
7688 {
7689 case 1: case 3:
7690 case 5: case 7:
7691 func (stream, "32");
7692 break;
7693
7694 case 9: case 11:
7695 func (stream, "16");
7696 break;
7697
7698 default:
7699 break;
7700 }
7701 break;
7702
ed63aa17
AV		 7703 case MVE_VQSHRN:
7704 case MVE_VQSHRUN:
7705 case MVE_VQRSHRN:
7706 case MVE_VQRSHRUN:
7707 case MVE_VRSHRN:
7708 case MVE_VSHRN:
7709 {
7710 switch (size)
7711 {
7712 case 1:
7713 func (stream, "16");
7714 break;
7715
7716 case 2: case 3:
7717 func (stream, "32");
7718 break;
7719
7720 default:
7721 break;
7722 }
7723 }
7724 break;
7725
7726 case MVE_VQSHL_T2:
7727 case MVE_VQSHLU_T3:
7728 case MVE_VRSHR:
7729 case MVE_VSHL_T1:
7730 case MVE_VSHLL_T1:
7731 case MVE_VSHR:
7732 case MVE_VSLI:
7733 case MVE_VSRI:
7734 {
7735 switch (size)
7736 {
7737 case 1:
7738 func (stream, "8");
7739 break;
7740
7741 case 2: case 3:
7742 func (stream, "16");
7743 break;
7744
7745 case 4: case 5: case 6: case 7:
7746 func (stream, "32");
7747 break;
7748
7749 default:
7750 break;
7751 }
7752 }
7753 break;
7754
143275ea
AV		 7755 default:
7756 break;
7757 }
7758}
7759
ed63aa17
AV		 7760static void
7761print_mve_shift_n (struct disassemble_info *info, long given,
7762 enum mve_instructions matched_insn)
7763{
7764 void *stream = info->stream;
7765 fprintf_ftype func = info->fprintf_func;
7766
7767 int startAt0
7768 = matched_insn == MVE_VQSHL_T2
7769 || matched_insn == MVE_VQSHLU_T3
7770 || matched_insn == MVE_VSHL_T1
7771 || matched_insn == MVE_VSHLL_T1
7772 || matched_insn == MVE_VSLI;
7773
7774 unsigned imm6 = (given & 0x3f0000) >> 16;
7775
7776 if (matched_insn == MVE_VSHLL_T1)
7777 imm6 &= 0x1f;
7778
7779 unsigned shiftAmount = 0;
7780 if ((imm6 & 0x20) != 0)
7781 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7782 else if ((imm6 & 0x10) != 0)
7783 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7784 else if ((imm6 & 0x08) != 0)
7785 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7786 else
7787 print_mve_undefined (info, UNDEF_SIZE_0);
7788
7789 func (stream, "%u", shiftAmount);
7790}
7791
143275ea
AV		 7792static void
7793print_vec_condition (struct disassemble_info *info, long given,
7794 enum mve_instructions matched_insn)
7795{
7796 void *stream = info->stream;
7797 fprintf_ftype func = info->fprintf_func;
7798 long vec_cond = 0;
7799
7800 switch (matched_insn)
7801 {
7802 case MVE_VPT_FP_T1:
7803 case MVE_VCMP_FP_T1:
7804 vec_cond = (((given & 0x1000) >> 10)
7805 | ((given & 1) << 1)
7806 | ((given & 0x0080) >> 7));
7807 func (stream, "%s",vec_condnames[vec_cond]);
7808 break;
7809
7810 case MVE_VPT_FP_T2:
7811 case MVE_VCMP_FP_T2:
7812 vec_cond = (((given & 0x1000) >> 10)
7813 | ((given & 0x0020) >> 4)
7814 | ((given & 0x0080) >> 7));
7815 func (stream, "%s",vec_condnames[vec_cond]);
7816 break;
7817
7818 case MVE_VPT_VEC_T1:
7819 case MVE_VCMP_VEC_T1:
7820 vec_cond = (given & 0x0080) >> 7;
7821 func (stream, "%s",vec_condnames[vec_cond]);
7822 break;
7823
7824 case MVE_VPT_VEC_T2:
7825 case MVE_VCMP_VEC_T2:
7826 vec_cond = 2 | ((given & 0x0080) >> 7);
7827 func (stream, "%s",vec_condnames[vec_cond]);
7828 break;
7829
7830 case MVE_VPT_VEC_T3:
7831 case MVE_VCMP_VEC_T3:
7832 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7833 func (stream, "%s",vec_condnames[vec_cond]);
7834 break;
7835
7836 case MVE_VPT_VEC_T4:
7837 case MVE_VCMP_VEC_T4:
7838 vec_cond = (given & 0x0080) >> 7;
7839 func (stream, "%s",vec_condnames[vec_cond]);
7840 break;
7841
7842 case MVE_VPT_VEC_T5:
7843 case MVE_VCMP_VEC_T5:
7844 vec_cond = 2 | ((given & 0x0080) >> 7);
7845 func (stream, "%s",vec_condnames[vec_cond]);
7846 break;
7847
7848 case MVE_VPT_VEC_T6:
7849 case MVE_VCMP_VEC_T6:
7850 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7851 func (stream, "%s",vec_condnames[vec_cond]);
7852 break;
7853
7854 case MVE_NONE:
7855 case MVE_VPST:
7856 default:
7857 break;
7858 }
7859}
7860
7861#define W_BIT 21
7862#define I_BIT 22
7863#define U_BIT 23
7864#define P_BIT 24
7865
7866#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7867#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7868#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7869#define PRE_BIT_SET (given & (1 << P_BIT))
7870
7871
8f06b2d8
PB		 7872/* Print one coprocessor instruction on INFO->STREAM.
7873 Return TRUE if the instuction matched, FALSE if this is not a
7874 recognised coprocessor instruction. */
7875
7876static bfd_boolean
fe56b6ce
NC		 7877print_insn_coprocessor (bfd_vma pc,
7878 struct disassemble_info *info,
7879 long given,
8f06b2d8
PB		 7880 bfd_boolean thumb)
7881{
6b0dd094 7882 const struct sopcode32 *insn;
8f06b2d8
PB		 7883 void *stream = info->stream;
7884 fprintf_ftype func = info->fprintf_func;
7885 unsigned long mask;
2edcd244 7886 unsigned long value = 0;
c22aaad1 7887 int cond;
8afc7bea 7888 int cp_num;
823d2571
TG		 7889 struct arm_private_data *private_data = info->private_data;
7890 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7891 arm_feature_set arm_ext_v8_1m_main =
7892 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7893
5b616bef 7894 allowed_arches = private_data->features;
8f06b2d8
PB		 7895
7896 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7897 {
ff4a8d2b
NC		 7898 unsigned long u_reg = 16;
7899 bfd_boolean is_unpredictable = FALSE;
05413229 7900 signed long value_in_comment = 0;
0313a2b8
NC		 7901 const char *c;
7902
823d2571 7903 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7904 switch (insn->value)
7905 {
7906 case SENTINEL_IWMMXT_START:
7907 if (info->mach != bfd_mach_arm_XScale
7908 && info->mach != bfd_mach_arm_iWMMXt
7909 && info->mach != bfd_mach_arm_iWMMXt2)
7910 do
7911 insn++;
823d2571
TG		 7912 while ((! ARM_FEATURE_ZERO (insn->arch))
7913 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7914 continue;
7915
7916 case SENTINEL_IWMMXT_END:
7917 continue;
7918
7919 case SENTINEL_GENERIC_START:
5b616bef 7920 allowed_arches = private_data->features;
05413229
NC		 7921 continue;
7922
7923 default:
7924 abort ();
7925 }
8f06b2d8
PB		 7926
7927 mask = insn->mask;
7928 value = insn->value;
8afc7bea
RL		 7929 cp_num = (given >> 8) & 0xf;
7930
8f06b2d8
PB		 7931 if (thumb)
7932 {
7933 /* The high 4 bits are 0xe for Arm conditional instructions, and
7934 0xe for arm unconditional instructions. The rest of the
7935 encoding is the same. */
7936 mask |= 0xf0000000;
7937 value |= 0xe0000000;
c22aaad1
PB		 7938 if (ifthen_state)
7939 cond = IFTHEN_COND;
7940 else
e2efe87d 7941 cond = COND_UNCOND;
8f06b2d8
PB		 7942 }
7943 else
7944 {
7945 /* Only match unconditional instuctions against unconditional
7946 patterns. */
7947 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 7948 {
7949 mask |= 0xf0000000;
e2efe87d 7950 cond = COND_UNCOND;
c22aaad1
PB		 7951 }
7952 else
7953 {
7954 cond = (given >> 28) & 0xf;
7955 if (cond == 0xe)
e2efe87d 7956 cond = COND_UNCOND;
c22aaad1 7957 }
8f06b2d8 7958 }
823d2571 7959
6b0dd094
AV		 7960 if ((insn->isa == T32 && !thumb)
7961 || (insn->isa == ARM && thumb))
7962 continue;
7963
0313a2b8
NC		 7964 if ((given & mask) != value)
7965 continue;
8f06b2d8 7966
823d2571 7967 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 7968 continue;
7969
8afc7bea
RL		 7970 if (insn->value == 0xfe000010 /* mcr2 */
7971 || insn->value == 0xfe100010 /* mrc2 */
7972 || insn->value == 0xfc100000 /* ldc2 */
7973 || insn->value == 0xfc000000) /* stc2 */
7974 {
b0c11777 7975 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7976 is_unpredictable = TRUE;
f08d8ce3
AV		 7977
7978 /* Armv8.1-M Mainline FP & MVE instructions. */
7979 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7980 && !ARM_CPU_IS_ANY (allowed_arches)
7981 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7982 continue;
7983
8afc7bea
RL		 7984 }
7985 else if (insn->value == 0x0e000000 /* cdp */
7986 || insn->value == 0xfe000000 /* cdp2 */
7987 || insn->value == 0x0e000010 /* mcr */
7988 || insn->value == 0x0e100010 /* mrc */
7989 || insn->value == 0x0c100000 /* ldc */
7990 || insn->value == 0x0c000000) /* stc */
7991 {
7992 /* Floating-point instructions. */
b0c11777 7993 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7994 continue;
32c36c3c
AV		 7995
7996 /* Armv8.1-M Mainline FP & MVE instructions. */
7997 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7998 && !ARM_CPU_IS_ANY (allowed_arches)
7999 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8000 continue;
8afc7bea 8001 }
aef6d006
AV		 8002 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8003 || insn->value == 0xec000f80) /* vstr (system register) */
8004 && arm_decode_field (given, 24, 24) == 0
8005 && arm_decode_field (given, 21, 21) == 0)
8006 /* If the P and W bits are both 0 then these encodings match the MVE
8007 VLDR and VSTR instructions, these are in a different table, so we
8008 don't let it match here. */
8009 continue;
8010
0313a2b8
NC		 8011 for (c = insn->assembler; *c; c++)
8012 {
8013 if (*c == '%')
8f06b2d8 8014 {
32c36c3c
AV		 8015 const char mod = *++c;
8016 switch (mod)
8f06b2d8 8017 {
0313a2b8
NC		 8018 case '%':
8019 func (stream, "%%");
8020 break;
8021
8022 case 'A':
32c36c3c 8023 case 'K':
05413229 8024 {
79862e45 8025 int rn = (given >> 16) & 0xf;
b0c11777 8026 bfd_vma offset = given & 0xff;
0313a2b8 8027
32c36c3c
AV		 8028 if (mod == 'K')
8029 offset = given & 0x7f;
8030
05413229 8031 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8032
79862e45
DJ		 8033 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8034 {
8035 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8036 if (cp_num == 9)
8037 /* vldr.16/vstr.16 will shift the address
8038 left by 1 bit only. */
8039 offset = offset * 2;
8040 else
8041 offset = offset * 4;
8042
79862e45
DJ		 8043 if (NEGATIVE_BIT_SET)
8044 offset = - offset;
8045 if (rn != 15)
8046 value_in_comment = offset;
8047 }
8048
c1e26897 8049 if (PRE_BIT_SET)
05413229
NC		 8050 {
8051 if (offset)
fe56b6ce 8052 func (stream, ", #%d]%s",
d908c8af 8053 (int) offset,
c1e26897 8054 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8055 else if (NEGATIVE_BIT_SET)
8056 func (stream, ", #-0]");
05413229
NC		 8057 else
8058 func (stream, "]");
8059 }
8060 else
8061 {
0313a2b8 8062 func (stream, "]");
8f06b2d8 8063
c1e26897 8064 if (WRITEBACK_BIT_SET)
05413229
NC		 8065 {
8066 if (offset)
d908c8af 8067 func (stream, ", #%d", (int) offset);
26d97720
NS		 8068 else if (NEGATIVE_BIT_SET)
8069 func (stream, ", #-0");
05413229
NC		 8070 }
8071 else
fe56b6ce 8072 {
26d97720
NS		 8073 func (stream, ", {%s%d}",
8074 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8075 (int) offset);
fe56b6ce
NC		 8076 value_in_comment = offset;
8077 }
05413229 8078 }
79862e45
DJ		 8079 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8080 {
8081 func (stream, "\t; ");
6844b2c2
MGD		 8082 /* For unaligned PCs, apply off-by-alignment
8083 correction. */
43e65147 8084 info->print_address_func (offset + pc
6844b2c2
MGD		 8085 + info->bytes_per_chunk * 2
8086 - (pc & 3),
dffaa15c 8087 info);
79862e45 8088 }
05413229 8089 }
0313a2b8 8090 break;
8f06b2d8 8091
0313a2b8
NC		 8092 case 'B':
8093 {
8094 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8095 int offset = (given >> 1) & 0x3f;
8096
8097 if (offset == 1)
8098 func (stream, "{d%d}", regno);
8099 else if (regno + offset > 32)
8100 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8101 else
8102 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8103 }
8104 break;
8f06b2d8 8105
efd6b359
AV		 8106 case 'C':
8107 {
8108 bfd_boolean single = ((given >> 8) & 1) == 0;
8109 char reg_prefix = single ? 's' : 'd';
8110 int Dreg = (given >> 22) & 0x1;
8111 int Vdreg = (given >> 12) & 0xf;
8112 int reg = single ? ((Vdreg << 1) | Dreg)
8113 : ((Dreg << 4) | Vdreg);
8114 int num = (given >> (single ? 0 : 1)) & 0x7f;
8115 int maxreg = single ? 31 : 15;
8116 int topreg = reg + num - 1;
8117
8118 if (!num)
8119 func (stream, "{VPR}");
8120 else if (num == 1)
8121 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8122 else if (topreg > maxreg)
8123 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8124 reg_prefix, reg, single ? topreg >> 1 : topreg);
8125 else
8126 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8127 reg_prefix, topreg);
8128 }
8129 break;
8130
e2efe87d
MGD		 8131 case 'u':
8132 if (cond != COND_UNCOND)
8133 is_unpredictable = TRUE;
8134
8135 /* Fall through. */
0313a2b8 8136 case 'c':
b0c11777
RL		 8137 if (cond != COND_UNCOND && cp_num == 9)
8138 is_unpredictable = TRUE;
8139
0313a2b8
NC		 8140 func (stream, "%s", arm_conditional[cond]);
8141 break;
8f06b2d8 8142
0313a2b8
NC		 8143 case 'I':
8144 /* Print a Cirrus/DSP shift immediate. */
8145 /* Immediates are 7bit signed ints with bits 0..3 in
8146 bits 0..3 of opcode and bits 4..6 in bits 5..7
8147 of opcode. */
8148 {
8149 int imm;
8f06b2d8 8150
0313a2b8 8151 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8152
0313a2b8
NC		 8153 /* Is ``imm'' a negative number? */
8154 if (imm & 0x40)
24b4cf66 8155 imm -= 0x80;
8f06b2d8 8156
0313a2b8
NC		 8157 func (stream, "%d", imm);
8158 }
8159
8160 break;
8f06b2d8 8161
32c36c3c
AV		 8162 case 'J':
8163 {
73cd51e5
AV		 8164 unsigned long regno
8165 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8166
8167 switch (regno)
8168 {
8169 case 0x1:
8170 func (stream, "FPSCR");
8171 break;
8172 case 0x2:
8173 func (stream, "FPSCR_nzcvqc");
8174 break;
8175 case 0xc:
8176 func (stream, "VPR");
8177 break;
8178 case 0xd:
8179 func (stream, "P0");
8180 break;
8181 case 0xe:
8182 func (stream, "FPCXTNS");
8183 break;
8184 case 0xf:
8185 func (stream, "FPCXTS");
8186 break;
8187 default:
73cd51e5 8188 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8189 break;
8190 }
8191 }
8192 break;
8193
0313a2b8
NC		 8194 case 'F':
8195 switch (given & 0x00408000)
8196 {
8197 case 0:
8198 func (stream, "4");
8199 break;
8200 case 0x8000:
8201 func (stream, "1");
8202 break;
8203 case 0x00400000:
8204 func (stream, "2");
8f06b2d8 8205 break;
0313a2b8
NC		 8206 default:
8207 func (stream, "3");
8208 }
8209 break;
8f06b2d8 8210
0313a2b8
NC		 8211 case 'P':
8212 switch (given & 0x00080080)
8213 {
8214 case 0:
8215 func (stream, "s");
8216 break;
8217 case 0x80:
8218 func (stream, "d");
8219 break;
8220 case 0x00080000:
8221 func (stream, "e");
8222 break;
8223 default:
8224 func (stream, _("<illegal precision>"));
8f06b2d8 8225 break;
0313a2b8
NC		 8226 }
8227 break;
8f06b2d8 8228
0313a2b8
NC		 8229 case 'Q':
8230 switch (given & 0x00408000)
8231 {
8232 case 0:
8233 func (stream, "s");
8f06b2d8 8234 break;
0313a2b8
NC		 8235 case 0x8000:
8236 func (stream, "d");
8f06b2d8 8237 break;
0313a2b8
NC		 8238 case 0x00400000:
8239 func (stream, "e");
8240 break;
8241 default:
8242 func (stream, "p");
8f06b2d8 8243 break;
0313a2b8
NC		 8244 }
8245 break;
8f06b2d8 8246
0313a2b8
NC		 8247 case 'R':
8248 switch (given & 0x60)
8249 {
8250 case 0:
8251 break;
8252 case 0x20:
8253 func (stream, "p");
8254 break;
8255 case 0x40:
8256 func (stream, "m");
8257 break;
8258 default:
8259 func (stream, "z");
8260 break;
8261 }
8262 break;
16980d0b 8263
0313a2b8
NC		 8264 case '0': case '1': case '2': case '3': case '4':
8265 case '5': case '6': case '7': case '8': case '9':
8266 {
8267 int width;
8f06b2d8 8268
0313a2b8 8269 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8270
0313a2b8
NC		 8271 switch (*c)
8272 {
ff4a8d2b
NC		 8273 case 'R':
8274 if (value == 15)
8275 is_unpredictable = TRUE;
8276 /* Fall through. */
0313a2b8 8277 case 'r':
ff4a8d2b
NC		 8278 if (c[1] == 'u')
8279 {
8280 /* Eat the 'u' character. */
8281 ++ c;
8282
8283 if (u_reg == value)
8284 is_unpredictable = TRUE;
8285 u_reg = value;
8286 }
0313a2b8
NC		 8287 func (stream, "%s", arm_regnames[value]);
8288 break;
c28eeff2
SN		 8289 case 'V':
8290 if (given & (1 << 6))
8291 goto Q;
8292 /* FALLTHROUGH */
0313a2b8
NC		 8293 case 'D':
8294 func (stream, "d%ld", value);
8295 break;
8296 case 'Q':
c28eeff2 8297 Q:
0313a2b8
NC		 8298 if (value & 1)
8299 func (stream, "<illegal reg q%ld.5>", value >> 1);
8300 else
8301 func (stream, "q%ld", value >> 1);
8302 break;
8303 case 'd':
8304 func (stream, "%ld", value);
05413229 8305 value_in_comment = value;
0313a2b8 8306 break;
6f1c2142
AM		 8307 case 'E':
8308 {
8309 /* Converts immediate 8 bit back to float value. */
8310 unsigned floatVal = (value & 0x80) << 24
8311 | (value & 0x3F) << 19
8312 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8313
8314 /* Quarter float have a maximum value of 31.0.
8315 Get floating point value multiplied by 1e7.
8316 The maximum value stays in limit of a 32-bit int. */
8317 unsigned decVal =
8318 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8319 (16 + (value & 0xF));
8320
8321 if (!(decVal % 1000000))
8322 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8323 floatVal, value & 0x80 ? '-' : ' ',
8324 decVal / 10000000,
8325 decVal % 10000000 / 1000000);
8326 else if (!(decVal % 10000))
8327 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8328 floatVal, value & 0x80 ? '-' : ' ',
8329 decVal / 10000000,
8330 decVal % 10000000 / 10000);
8331 else
8332 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8333 floatVal, value & 0x80 ? '-' : ' ',
8334 decVal / 10000000, decVal % 10000000);
8335 break;
8336 }
0313a2b8
NC		 8337 case 'k':
8338 {
8339 int from = (given & (1 << 7)) ? 32 : 16;
8340 func (stream, "%ld", from - value);
8341 }
8342 break;
8f06b2d8 8343
0313a2b8
NC		 8344 case 'f':
8345 if (value > 7)
8346 func (stream, "#%s", arm_fp_const[value & 7]);
8347 else
8348 func (stream, "f%ld", value);
8349 break;
4146fd53 8350
0313a2b8
NC		 8351 case 'w':
8352 if (width == 2)
8353 func (stream, "%s", iwmmxt_wwnames[value]);
8354 else
8355 func (stream, "%s", iwmmxt_wwssnames[value]);
8356 break;
4146fd53 8357
0313a2b8
NC		 8358 case 'g':
8359 func (stream, "%s", iwmmxt_regnames[value]);
8360 break;
8361 case 'G':
8362 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8363 break;
8f06b2d8 8364
0313a2b8 8365 case 'x':
d1aaab3c 8366 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8367 break;
8f06b2d8 8368
33399f07
MGD		 8369 case 'c':
8370 switch (value)
8371 {
8372 case 0:
8373 func (stream, "eq");
8374 break;
8375
8376 case 1:
8377 func (stream, "vs");
8378 break;
8379
8380 case 2:
8381 func (stream, "ge");
8382 break;
8383
8384 case 3:
8385 func (stream, "gt");
8386 break;
8387
8388 default:
8389 func (stream, "??");
8390 break;
8391 }
8392 break;
8393
0313a2b8
NC		 8394 case '`':
8395 c++;
8396 if (value == 0)
8397 func (stream, "%c", *c);
8398 break;
8399 case '\'':
8400 c++;
8401 if (value == ((1ul << width) - 1))
8402 func (stream, "%c", *c);
8403 break;
8404 case '?':
fe56b6ce 8405 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8406 c += 1 << width;
8407 break;
8408 default:
8409 abort ();
8410 }
dffaa15c
AM		 8411 }
8412 break;
0313a2b8 8413
dffaa15c
AM		 8414 case 'y':
8415 case 'z':
8416 {
8417 int single = *c++ == 'y';
8418 int regno;
8f06b2d8 8419
dffaa15c
AM		 8420 switch (*c)
8421 {
8422 case '4': /* Sm pair */
8423 case '0': /* Sm, Dm */
8424 regno = given & 0x0000000f;
8425 if (single)
8426 {
8427 regno <<= 1;
8428 regno += (given >> 5) & 1;
8429 }
8430 else
8431 regno += ((given >> 5) & 1) << 4;
8432 break;
8f06b2d8 8433
dffaa15c
AM		 8434 case '1': /* Sd, Dd */
8435 regno = (given >> 12) & 0x0000000f;
8436 if (single)
8437 {
8438 regno <<= 1;
8439 regno += (given >> 22) & 1;
8440 }
8441 else
8442 regno += ((given >> 22) & 1) << 4;
8443 break;
7df76b80 8444
dffaa15c
AM		 8445 case '2': /* Sn, Dn */
8446 regno = (given >> 16) & 0x0000000f;
8447 if (single)
8448 {
8449 regno <<= 1;
8450 regno += (given >> 7) & 1;
8451 }
8452 else
8453 regno += ((given >> 7) & 1) << 4;
8454 break;
a7f8487e 8455
dffaa15c
AM		 8456 case '3': /* List */
8457 func (stream, "{");
8458 regno = (given >> 12) & 0x0000000f;
8459 if (single)
8460 {
8461 regno <<= 1;
8462 regno += (given >> 22) & 1;
8463 }
8464 else
8465 regno += ((given >> 22) & 1) << 4;
8466 break;
a7f8487e 8467
dffaa15c
AM		 8468 default:
8469 abort ();
8470 }
0313a2b8 8471
dffaa15c 8472 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8473
dffaa15c
AM		 8474 if (*c == '3')
8475 {
8476 int count = given & 0xff;
b34976b6 8477
dffaa15c
AM		 8478 if (single == 0)
8479 count >>= 1;
0313a2b8 8480
dffaa15c
AM		 8481 if (--count)
8482 {
8483 func (stream, "-%c%d",
8484 single ? 's' : 'd',
8485 regno + count);
8486 }
0313a2b8 8487
dffaa15c 8488 func (stream, "}");
0313a2b8 8489 }
dffaa15c
AM		 8490 else if (*c == '4')
8491 func (stream, ", %c%d", single ? 's' : 'd',
8492 regno + 1);
8493 }
8494 break;
b34976b6 8495
dffaa15c
AM		 8496 case 'L':
8497 switch (given & 0x00400100)
0313a2b8 8498 {
dffaa15c
AM		 8499 case 0x00000000: func (stream, "b"); break;
8500 case 0x00400000: func (stream, "h"); break;
8501 case 0x00000100: func (stream, "w"); break;
8502 case 0x00400100: func (stream, "d"); break;
8503 default:
8504 break;
0313a2b8 8505 }
dffaa15c 8506 break;
2d447fca 8507
dffaa15c
AM		 8508 case 'Z':
8509 {
8510 /* given (20, 23) | given (0, 3) */
8511 value = ((given >> 16) & 0xf0) | (given & 0xf);
8512 func (stream, "%d", (int) value);
8513 }
8514 break;
0313a2b8 8515
dffaa15c
AM		 8516 case 'l':
8517 /* This is like the 'A' operator, except that if
8518 the width field "M" is zero, then the offset is
8519 *not* multiplied by four. */
8520 {
8521 int offset = given & 0xff;
8522 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8523
dffaa15c 8524 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8525
dffaa15c
AM		 8526 if (multiplier > 1)
8527 {
8528 value_in_comment = offset * multiplier;
8529 if (NEGATIVE_BIT_SET)
8530 value_in_comment = - value_in_comment;
8531 }
0313a2b8 8532
dffaa15c
AM		 8533 if (offset)
8534 {
8535 if (PRE_BIT_SET)
8536 func (stream, ", #%s%d]%s",
8537 NEGATIVE_BIT_SET ? "-" : "",
8538 offset * multiplier,
8539 WRITEBACK_BIT_SET ? "!" : "");
8540 else
8541 func (stream, "], #%s%d",
8542 NEGATIVE_BIT_SET ? "-" : "",
8543 offset * multiplier);
8544 }
8545 else
8546 func (stream, "]");
8547 }
8548 break;
2d447fca 8549
dffaa15c
AM		 8550 case 'r':
8551 {
8552 int imm4 = (given >> 4) & 0xf;
8553 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8554 int ubit = ! NEGATIVE_BIT_SET;
8555 const char *rm = arm_regnames [given & 0xf];
8556 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8557
dffaa15c
AM		 8558 switch (puw_bits)
8559 {
8560 case 1:
8561 case 3:
8562 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8563 if (imm4)
8564 func (stream, ", lsl #%d", imm4);
8565 break;
0313a2b8 8566
dffaa15c
AM		 8567 case 4:
8568 case 5:
8569 case 6:
8570 case 7:
8571 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8572 if (imm4 > 0)
8573 func (stream, ", lsl #%d", imm4);
8574 func (stream, "]");
8575 if (puw_bits == 5 || puw_bits == 7)
8576 func (stream, "!");
8577 break;
2d447fca 8578
dffaa15c
AM		 8579 default:
8580 func (stream, "INVALID");
8581 }
8582 }
8583 break;
0313a2b8 8584
dffaa15c
AM		 8585 case 'i':
8586 {
8587 long imm5;
8588 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8589 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8590 }
dffaa15c
AM		 8591 break;
8592
8593 default:
8594 abort ();
252b5132 8595 }
252b5132 8596 }
0313a2b8
NC		 8597 else
8598 func (stream, "%c", *c);
252b5132 8599 }
05413229
NC		 8600
8601 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8602 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8603
ff4a8d2b
NC		 8604 if (is_unpredictable)
8605 func (stream, UNPREDICTABLE_INSTRUCTION);
8606
0313a2b8 8607 return TRUE;
252b5132 8608 }
8f06b2d8 8609 return FALSE;
252b5132
RH		 8610}
8611
05413229
NC		 8612/* Decodes and prints ARM addressing modes. Returns the offset
8613 used in the address, if any, if it is worthwhile printing the
8614 offset as a hexadecimal value in a comment at the end of the
8615 line of disassembly. */
8616
8617static signed long
62b3e311
PB		 8618print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8619{
8620 void *stream = info->stream;
8621 fprintf_ftype func = info->fprintf_func;
f8b960bc 8622 bfd_vma offset = 0;
62b3e311
PB		 8623
8624 if (((given & 0x000f0000) == 0x000f0000)
8625 && ((given & 0x02000000) == 0))
8626 {
05413229 8627 offset = given & 0xfff;
62b3e311
PB		 8628
8629 func (stream, "[pc");
8630
c1e26897 8631 if (PRE_BIT_SET)
62b3e311 8632 {
26d97720
NS		 8633 /* Pre-indexed. Elide offset of positive zero when
8634 non-writeback. */
8635 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8636 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8637
8638 if (NEGATIVE_BIT_SET)
8639 offset = -offset;
62b3e311
PB		 8640
8641 offset += pc + 8;
8642
8643 /* Cope with the possibility of write-back
8644 being used. Probably a very dangerous thing
8645 for the programmer to do, but who are we to
8646 argue ? */
26d97720 8647 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8648 }
c1e26897 8649 else /* Post indexed. */
62b3e311 8650 {
d908c8af 8651 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8652
c1e26897 8653 /* Ie ignore the offset. */
62b3e311
PB		 8654 offset = pc + 8;
8655 }
8656
8657 func (stream, "\t; ");
8658 info->print_address_func (offset, info);
05413229 8659 offset = 0;
62b3e311
PB		 8660 }
8661 else
8662 {
8663 func (stream, "[%s",
8664 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8665
8666 if (PRE_BIT_SET)
62b3e311
PB		 8667 {
8668 if ((given & 0x02000000) == 0)
8669 {
26d97720 8670 /* Elide offset of positive zero when non-writeback. */
05413229 8671 offset = given & 0xfff;
26d97720 8672 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8673 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8674 }
8675 else
8676 {
26d97720 8677 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8678 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8679 }
8680
8681 func (stream, "]%s",
c1e26897 8682 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8683 }
8684 else
8685 {
8686 if ((given & 0x02000000) == 0)
8687 {
26d97720 8688 /* Always show offset. */
05413229 8689 offset = given & 0xfff;
26d97720 8690 func (stream, "], #%s%d",
d908c8af 8691 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8692 }
8693 else
8694 {
8695 func (stream, "], %s",
c1e26897 8696 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8697 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8698 }
8699 }
84919466
MR		 8700 if (NEGATIVE_BIT_SET)
8701 offset = -offset;
62b3e311 8702 }
05413229
NC		 8703
8704 return (signed long) offset;
62b3e311
PB		 8705}
8706
16980d0b
JB		 8707/* Print one neon instruction on INFO->STREAM.
8708 Return TRUE if the instuction matched, FALSE if this is not a
8709 recognised neon instruction. */
8710
8711static bfd_boolean
8712print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8713{
8714 const struct opcode32 *insn;
8715 void *stream = info->stream;
8716 fprintf_ftype func = info->fprintf_func;
8717
8718 if (thumb)
8719 {
8720 if ((given & 0xef000000) == 0xef000000)
8721 {
0313a2b8 8722 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8723 unsigned long bit28 = given & (1 << 28);
8724
8725 given &= 0x00ffffff;
8726 if (bit28)
8727 given |= 0xf3000000;
8728 else
8729 given |= 0xf2000000;
8730 }
8731 else if ((given & 0xff000000) == 0xf9000000)
8732 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 8733 /* vdup is also a valid neon instruction. */
8734 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8735 return FALSE;
8736 }
43e65147 8737
16980d0b
JB		 8738 for (insn = neon_opcodes; insn->assembler; insn++)
8739 {
8740 if ((given & insn->mask) == insn->value)
8741 {
05413229 8742 signed long value_in_comment = 0;
e2efe87d 8743 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 8744 const char *c;
8745
8746 for (c = insn->assembler; *c; c++)
8747 {
8748 if (*c == '%')
8749 {
8750 switch (*++c)
8751 {
8752 case '%':
8753 func (stream, "%%");
8754 break;
8755
e2efe87d
MGD		 8756 case 'u':
8757 if (thumb && ifthen_state)
8758 is_unpredictable = TRUE;
8759
8760 /* Fall through. */
c22aaad1
PB		 8761 case 'c':
8762 if (thumb && ifthen_state)
8763 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8764 break;
8765
16980d0b
JB		 8766 case 'A':
8767 {
43e65147 8768 static const unsigned char enc[16] =
16980d0b
JB		 8769 {
8770 0x4, 0x14, /* st4 0,1 */
8771 0x4, /* st1 2 */
8772 0x4, /* st2 3 */
8773 0x3, /* st3 4 */
8774 0x13, /* st3 5 */
8775 0x3, /* st1 6 */
8776 0x1, /* st1 7 */
8777 0x2, /* st2 8 */
8778 0x12, /* st2 9 */
8779 0x2, /* st1 10 */
8780 0, 0, 0, 0, 0
8781 };
8782 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8783 int rn = ((given >> 16) & 0xf);
8784 int rm = ((given >> 0) & 0xf);
8785 int align = ((given >> 4) & 0x3);
8786 int type = ((given >> 8) & 0xf);
8787 int n = enc[type] & 0xf;
8788 int stride = (enc[type] >> 4) + 1;
8789 int ix;
43e65147 8790
16980d0b
JB		 8791 func (stream, "{");
8792 if (stride > 1)
8793 for (ix = 0; ix != n; ix++)
8794 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8795 else if (n == 1)
8796 func (stream, "d%d", rd);
8797 else
8798 func (stream, "d%d-d%d", rd, rd + n - 1);
8799 func (stream, "}, [%s", arm_regnames[rn]);
8800 if (align)
8e560766 8801 func (stream, " :%d", 32 << align);
16980d0b
JB		 8802 func (stream, "]");
8803 if (rm == 0xd)
8804 func (stream, "!");
8805 else if (rm != 0xf)
8806 func (stream, ", %s", arm_regnames[rm]);
8807 }
8808 break;
43e65147 8809
16980d0b
JB		 8810 case 'B':
8811 {
8812 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8813 int rn = ((given >> 16) & 0xf);
8814 int rm = ((given >> 0) & 0xf);
8815 int idx_align = ((given >> 4) & 0xf);
8816 int align = 0;
8817 int size = ((given >> 10) & 0x3);
8818 int idx = idx_align >> (size + 1);
8819 int length = ((given >> 8) & 3) + 1;
8820 int stride = 1;
8821 int i;
8822
8823 if (length > 1 && size > 0)
8824 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 8825
16980d0b
JB		 8826 switch (length)
8827 {
8828 case 1:
8829 {
8830 int amask = (1 << size) - 1;
8831 if ((idx_align & (1 << size)) != 0)
8832 return FALSE;
8833 if (size > 0)
8834 {
8835 if ((idx_align & amask) == amask)
8836 align = 8 << size;
8837 else if ((idx_align & amask) != 0)
8838 return FALSE;
8839 }
8840 }
8841 break;
43e65147 8842
16980d0b
JB		 8843 case 2:
8844 if (size == 2 && (idx_align & 2) != 0)
8845 return FALSE;
8846 align = (idx_align & 1) ? 16 << size : 0;
8847 break;
43e65147 8848
16980d0b
JB		 8849 case 3:
8850 if ((size == 2 && (idx_align & 3) != 0)
8851 || (idx_align & 1) != 0)
8852 return FALSE;
8853 break;
43e65147 8854
16980d0b
JB		 8855 case 4:
8856 if (size == 2)
8857 {
8858 if ((idx_align & 3) == 3)
8859 return FALSE;
8860 align = (idx_align & 3) * 64;
8861 }
8862 else
8863 align = (idx_align & 1) ? 32 << size : 0;
8864 break;
43e65147 8865
16980d0b
JB		 8866 default:
8867 abort ();
8868 }
43e65147 8869
16980d0b
JB		 8870 func (stream, "{");
8871 for (i = 0; i < length; i++)
8872 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8873 rd + i * stride, idx);
8874 func (stream, "}, [%s", arm_regnames[rn]);
8875 if (align)
8e560766 8876 func (stream, " :%d", align);
16980d0b
JB		 8877 func (stream, "]");
8878 if (rm == 0xd)
8879 func (stream, "!");
8880 else if (rm != 0xf)
8881 func (stream, ", %s", arm_regnames[rm]);
8882 }
8883 break;
43e65147 8884
16980d0b
JB		 8885 case 'C':
8886 {
8887 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8888 int rn = ((given >> 16) & 0xf);
8889 int rm = ((given >> 0) & 0xf);
8890 int align = ((given >> 4) & 0x1);
8891 int size = ((given >> 6) & 0x3);
8892 int type = ((given >> 8) & 0x3);
8893 int n = type + 1;
8894 int stride = ((given >> 5) & 0x1);
8895 int ix;
43e65147 8896
16980d0b
JB		 8897 if (stride && (n == 1))
8898 n++;
8899 else
8900 stride++;
43e65147 8901
16980d0b
JB		 8902 func (stream, "{");
8903 if (stride > 1)
8904 for (ix = 0; ix != n; ix++)
8905 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8906 else if (n == 1)
8907 func (stream, "d%d[]", rd);
8908 else
8909 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8910 func (stream, "}, [%s", arm_regnames[rn]);
8911 if (align)
8912 {
91d6fa6a 8913 align = (8 * (type + 1)) << size;
16980d0b
JB		 8914 if (type == 3)
8915 align = (size > 1) ? align >> 1 : align;
8916 if (type == 2 || (type == 0 && !size))
8e560766 8917 func (stream, " :<bad align %d>", align);
16980d0b 8918 else
8e560766 8919 func (stream, " :%d", align);
16980d0b
JB		 8920 }
8921 func (stream, "]");
8922 if (rm == 0xd)
8923 func (stream, "!");
8924 else if (rm != 0xf)
8925 func (stream, ", %s", arm_regnames[rm]);
8926 }
8927 break;
43e65147 8928
16980d0b
JB		 8929 case 'D':
8930 {
8931 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8932 int size = (given >> 20) & 3;
8933 int reg = raw_reg & ((4 << size) - 1);
8934 int ix = raw_reg >> size >> 2;
43e65147 8935
16980d0b
JB		 8936 func (stream, "d%d[%d]", reg, ix);
8937 }
8938 break;
43e65147 8939
16980d0b 8940 case 'E':
fe56b6ce 8941 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 8942 {
8943 int bits = 0;
8944 int cmode = (given >> 8) & 0xf;
8945 int op = (given >> 5) & 0x1;
8946 unsigned long value = 0, hival = 0;
8947 unsigned shift;
8948 int size = 0;
0dbde4cf 8949 int isfloat = 0;
43e65147 8950
16980d0b
JB		 8951 bits |= ((given >> 24) & 1) << 7;
8952 bits |= ((given >> 16) & 7) << 4;
8953 bits |= ((given >> 0) & 15) << 0;
43e65147 8954
16980d0b
JB		 8955 if (cmode < 8)
8956 {
8957 shift = (cmode >> 1) & 3;
fe56b6ce 8958 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8959 size = 32;
8960 }
8961 else if (cmode < 12)
8962 {
8963 shift = (cmode >> 1) & 1;
fe56b6ce 8964 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8965 size = 16;
8966 }
8967 else if (cmode < 14)
8968 {
8969 shift = (cmode & 1) + 1;
fe56b6ce 8970 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8971 value |= (1ul << (8 * shift)) - 1;
8972 size = 32;
8973 }
8974 else if (cmode == 14)
8975 {
8976 if (op)
8977 {
fe56b6ce 8978 /* Bit replication into bytes. */
16980d0b
JB		 8979 int ix;
8980 unsigned long mask;
43e65147 8981
16980d0b
JB		 8982 value = 0;
8983 hival = 0;
8984 for (ix = 7; ix >= 0; ix--)
8985 {
8986 mask = ((bits >> ix) & 1) ? 0xff : 0;
8987 if (ix <= 3)
8988 value = (value << 8) | mask;
8989 else
8990 hival = (hival << 8) | mask;
8991 }
8992 size = 64;
8993 }
8994 else
8995 {
fe56b6ce
NC		 8996 /* Byte replication. */
8997 value = (unsigned long) bits;
16980d0b
JB		 8998 size = 8;
8999 }
9000 }
9001 else if (!op)
9002 {
fe56b6ce 9003 /* Floating point encoding. */
16980d0b 9004 int tmp;
43e65147 9005
fe56b6ce
NC		 9006 value = (unsigned long) (bits & 0x7f) << 19;
9007 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9008 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9009 value |= (unsigned long) tmp << 24;
16980d0b 9010 size = 32;
0dbde4cf 9011 isfloat = 1;
16980d0b
JB		 9012 }
9013 else
9014 {
9015 func (stream, "<illegal constant %.8x:%x:%x>",
9016 bits, cmode, op);
9017 size = 32;
9018 break;
9019 }
9020 switch (size)
9021 {
9022 case 8:
9023 func (stream, "#%ld\t; 0x%.2lx", value, value);
9024 break;
43e65147 9025
16980d0b
JB		 9026 case 16:
9027 func (stream, "#%ld\t; 0x%.4lx", value, value);
9028 break;
9029
9030 case 32:
0dbde4cf
JB		 9031 if (isfloat)
9032 {
9033 unsigned char valbytes[4];
9034 double fvalue;
43e65147 9035
0dbde4cf
JB		 9036 /* Do this a byte at a time so we don't have to
9037 worry about the host's endianness. */
9038 valbytes[0] = value & 0xff;
9039 valbytes[1] = (value >> 8) & 0xff;
9040 valbytes[2] = (value >> 16) & 0xff;
9041 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9042
9043 floatformat_to_double
c1e26897
NC		 9044 (& floatformat_ieee_single_little, valbytes,
9045 & fvalue);
43e65147 9046
0dbde4cf
JB		 9047 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9048 value);
9049 }
9050 else
4e9d3b81 9051 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9052 (long) (((value & 0x80000000L) != 0)
9d82ec38 9053 ? value | ~0xffffffffL : value),
c1e26897 9054 value);
16980d0b
JB		 9055 break;
9056
9057 case 64:
9058 func (stream, "#0x%.8lx%.8lx", hival, value);
9059 break;
43e65147 9060
16980d0b
JB		 9061 default:
9062 abort ();
9063 }
9064 }
9065 break;
43e65147 9066
16980d0b
JB		 9067 case 'F':
9068 {
9069 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9070 int num = (given >> 8) & 0x3;
43e65147 9071
16980d0b
JB		 9072 if (!num)
9073 func (stream, "{d%d}", regno);
9074 else if (num + regno >= 32)
9075 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9076 else
9077 func (stream, "{d%d-d%d}", regno, regno + num);
9078 }
9079 break;
7e8e6784 9080
16980d0b
JB		 9081
9082 case '0': case '1': case '2': case '3': case '4':
9083 case '5': case '6': case '7': case '8': case '9':
9084 {
9085 int width;
9086 unsigned long value;
9087
9088 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9089
16980d0b
JB		 9090 switch (*c)
9091 {
9092 case 'r':
9093 func (stream, "%s", arm_regnames[value]);
9094 break;
9095 case 'd':
9096 func (stream, "%ld", value);
05413229 9097 value_in_comment = value;
16980d0b
JB		 9098 break;
9099 case 'e':
9100 func (stream, "%ld", (1ul << width) - value);
9101 break;
43e65147 9102
16980d0b
JB		 9103 case 'S':
9104 case 'T':
9105 case 'U':
05413229 9106 /* Various width encodings. */
16980d0b
JB		 9107 {
9108 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9109 int limit;
9110 unsigned low, high;
9111
9112 c++;
9113 if (*c >= '0' && *c <= '9')
9114 limit = *c - '0';
9115 else if (*c >= 'a' && *c <= 'f')
9116 limit = *c - 'a' + 10;
9117 else
9118 abort ();
9119 low = limit >> 2;
9120 high = limit & 3;
9121
9122 if (value < low || value > high)
9123 func (stream, "<illegal width %d>", base << value);
9124 else
9125 func (stream, "%d", base << value);
9126 }
9127 break;
9128 case 'R':
9129 if (given & (1 << 6))
9130 goto Q;
9131 /* FALLTHROUGH */
9132 case 'D':
9133 func (stream, "d%ld", value);
9134 break;
9135 case 'Q':
9136 Q:
9137 if (value & 1)
9138 func (stream, "<illegal reg q%ld.5>", value >> 1);
9139 else
9140 func (stream, "q%ld", value >> 1);
9141 break;
43e65147 9142
16980d0b
JB		 9143 case '`':
9144 c++;
9145 if (value == 0)
9146 func (stream, "%c", *c);
9147 break;
9148 case '\'':
9149 c++;
9150 if (value == ((1ul << width) - 1))
9151 func (stream, "%c", *c);
9152 break;
9153 case '?':
fe56b6ce 9154 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9155 c += 1 << width;
9156 break;
9157 default:
9158 abort ();
9159 }
16980d0b 9160 }
dffaa15c
AM		 9161 break;
9162
9163 default:
9164 abort ();
16980d0b
JB		 9165 }
9166 }
9167 else
9168 func (stream, "%c", *c);
9169 }
05413229
NC		 9170
9171 if (value_in_comment > 32 || value_in_comment < -16)
9172 func (stream, "\t; 0x%lx", value_in_comment);
9173
e2efe87d
MGD		 9174 if (is_unpredictable)
9175 func (stream, UNPREDICTABLE_INSTRUCTION);
9176
16980d0b
JB		 9177 return TRUE;
9178 }
9179 }
9180 return FALSE;
9181}
9182
73cd51e5
AV		 9183/* Print one mve instruction on INFO->STREAM.
9184 Return TRUE if the instuction matched, FALSE if this is not a
9185 recognised mve instruction. */
9186
9187static bfd_boolean
9188print_insn_mve (struct disassemble_info *info, long given)
9189{
9190 const struct mopcode32 *insn;
9191 void *stream = info->stream;
9192 fprintf_ftype func = info->fprintf_func;
9193
9194 for (insn = mve_opcodes; insn->assembler; insn++)
9195 {
9196 if (((given & insn->mask) == insn->value)
9197 && !is_mve_encoding_conflict (given, insn->mve_op))
9198 {
9199 signed long value_in_comment = 0;
9200 bfd_boolean is_unpredictable = FALSE;
9201 bfd_boolean is_undefined = FALSE;
9202 const char *c;
9203 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9204 enum mve_undefined undefined_cond = UNDEF_NONE;
9205
9206 /* Most vector mve instruction are illegal in a it block.
9207 There are a few exceptions; check for them. */
9208 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9209 {
9210 is_unpredictable = TRUE;
9211 unpredictable_cond = UNPRED_IT_BLOCK;
9212 }
9213 else if (is_mve_unpredictable (given, insn->mve_op,
9214 &unpredictable_cond))
9215 is_unpredictable = TRUE;
9216
9217 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9218 is_undefined = TRUE;
9219
9220 for (c = insn->assembler; *c; c++)
9221 {
9222 if (*c == '%')
9223 {
9224 switch (*++c)
9225 {
9226 case '%':
9227 func (stream, "%%");
9228 break;
9229
ef1576a1
AV		 9230 case 'a':
9231 /* Don't print anything for '+' as it is implied. */
9232 if (arm_decode_field (given, 23, 23) == 0)
9233 func (stream, "-");
9234 break;
9235
143275ea
AV		 9236 case 'c':
9237 if (ifthen_state)
9238 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9239 break;
9240
aef6d006
AV		 9241 case 'd':
9242 print_mve_vld_str_addr (info, given, insn->mve_op);
9243 break;
9244
143275ea
AV		 9245 case 'i':
9246 {
9247 long mve_mask = mve_extract_pred_mask (given);
9248 func (stream, "%s", mve_predicatenames[mve_mask]);
9249 }
9250 break;
9251
23d00a41
SD		 9252 case 'j':
9253 {
9254 unsigned int imm5 = 0;
9255 imm5 |= arm_decode_field (given, 6, 7);
9256 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9257 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9258 }
9259 break;
9260
143275ea
AV		 9261 case 'n':
9262 print_vec_condition (info, given, insn->mve_op);
9263 break;
9264
ef1576a1
AV		 9265 case 'o':
9266 if (arm_decode_field (given, 0, 0) == 1)
9267 {
9268 unsigned long size
9269 = arm_decode_field (given, 4, 4)
9270 | (arm_decode_field (given, 6, 6) << 1);
9271
9272 func (stream, ", uxtw #%lu", size);
9273 }
9274 break;
9275
bf0b396d
AV		 9276 case 'm':
9277 print_mve_rounding_mode (info, given, insn->mve_op);
9278 break;
9279
9280 case 's':
9281 print_mve_vcvt_size (info, given, insn->mve_op);
9282 break;
9283
aef6d006
AV		 9284 case 'u':
9285 {
c507f10b
AV		 9286 unsigned long op1 = arm_decode_field (given, 21, 22);
9287
9288 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9289 {
9290 /* Check for signed. */
9291 if (arm_decode_field (given, 23, 23) == 0)
9292 {
9293 /* We don't print 's' for S32. */
9294 if ((arm_decode_field (given, 5, 6) == 0)
9295 && ((op1 == 0) || (op1 == 1)))
9296 ;
9297 else
9298 func (stream, "s");
9299 }
9300 else
9301 func (stream, "u");
9302 }
aef6d006 9303 else
c507f10b
AV		 9304 {
9305 if (arm_decode_field (given, 28, 28) == 0)
9306 func (stream, "s");
9307 else
9308 func (stream, "u");
9309 }
aef6d006 9310 }
ef1576a1 9311 break;
aef6d006 9312
143275ea
AV		 9313 case 'v':
9314 print_instruction_predicate (info);
9315 break;
9316
04d54ace
AV		 9317 case 'w':
9318 if (arm_decode_field (given, 21, 21) == 1)
9319 func (stream, "!");
9320 break;
9321
9322 case 'B':
9323 print_mve_register_blocks (info, given, insn->mve_op);
9324 break;
9325
c507f10b
AV		 9326 case 'E':
9327 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9328
9329 print_simd_imm8 (info, given, 28, insn);
9330 break;
9331
9332 case 'N':
9333 print_mve_vmov_index (info, given);
9334 break;
9335
14925797
AV		 9336 case 'T':
9337 if (arm_decode_field (given, 12, 12) == 0)
9338 func (stream, "b");
9339 else
9340 func (stream, "t");
9341 break;
9342
d3b63143
AV		 9343 case 'X':
9344 if (arm_decode_field (given, 12, 12) == 1)
9345 func (stream, "x");
9346 break;
9347
143275ea
AV		 9348 case '0': case '1': case '2': case '3': case '4':
9349 case '5': case '6': case '7': case '8': case '9':
9350 {
9351 int width;
9352 unsigned long value;
9353
9354 c = arm_decode_bitfield (c, given, &value, &width);
9355
9356 switch (*c)
9357 {
9358 case 'Z':
9359 if (value == 13)
9360 is_unpredictable = TRUE;
9361 else if (value == 15)
9362 func (stream, "zr");
9363 else
9364 func (stream, "%s", arm_regnames[value]);
9365 break;
23d00a41 9366
e39c1607
SD		 9367 case 'c':
9368 func (stream, "%s", arm_conditional[value]);
9369 break;
9370
9371 case 'C':
9372 value ^= 1;
9373 func (stream, "%s", arm_conditional[value]);
9374 break;
9375
23d00a41
SD		 9376 case 'S':
9377 if (value == 13 || value == 15)
9378 is_unpredictable = TRUE;
9379 else
9380 func (stream, "%s", arm_regnames[value]);
9381 break;
9382
143275ea
AV		 9383 case 's':
9384 print_mve_size (info,
9385 value,
9386 insn->mve_op);
9387 break;
66dcaa5d
AV		 9388 case 'I':
9389 if (value == 1)
9390 func (stream, "i");
9391 break;
d3b63143
AV		 9392 case 'A':
9393 if (value == 1)
9394 func (stream, "a");
9395 break;
1c8f2df8
AV		 9396 case 'h':
9397 {
9398 unsigned int odd_reg = (value << 1) | 1;
9399 func (stream, "%s", arm_regnames[odd_reg]);
9400 }
9401 break;
ef1576a1
AV		 9402 case 'i':
9403 {
9404 unsigned long imm
9405 = arm_decode_field (given, 0, 6);
9406 unsigned long mod_imm = imm;
9407
9408 switch (insn->mve_op)
9409 {
9410 case MVE_VLDRW_GATHER_T5:
9411 case MVE_VSTRW_SCATTER_T5:
9412 mod_imm = mod_imm << 2;
9413 break;
9414 case MVE_VSTRD_SCATTER_T6:
9415 case MVE_VLDRD_GATHER_T6:
9416 mod_imm = mod_imm << 3;
9417 break;
9418
9419 default:
9420 break;
9421 }
9422
9423 func (stream, "%lu", mod_imm);
9424 }
9425 break;
bf0b396d
AV		 9426 case 'k':
9427 func (stream, "%lu", 64 - value);
9428 break;
1c8f2df8
AV		 9429 case 'l':
9430 {
9431 unsigned int even_reg = value << 1;
9432 func (stream, "%s", arm_regnames[even_reg]);
9433 }
9434 break;
9435 case 'u':
9436 switch (value)
9437 {
9438 case 0:
9439 func (stream, "1");
9440 break;
9441 case 1:
9442 func (stream, "2");
9443 break;
9444 case 2:
9445 func (stream, "4");
9446 break;
9447 case 3:
9448 func (stream, "8");
9449 break;
9450 default:
9451 break;
9452 }
9453 break;
897b9bbc
AV		 9454 case 'o':
9455 print_mve_rotate (info, value, width);
9456 break;
9743db03
AV		 9457 case 'r':
9458 func (stream, "%s", arm_regnames[value]);
9459 break;
04d54ace 9460 case 'd':
ed63aa17
AV		 9461 if (insn->mve_op == MVE_VQSHL_T2
9462 || insn->mve_op == MVE_VQSHLU_T3
9463 || insn->mve_op == MVE_VRSHR
9464 || insn->mve_op == MVE_VRSHRN
9465 || insn->mve_op == MVE_VSHL_T1
9466 || insn->mve_op == MVE_VSHLL_T1
9467 || insn->mve_op == MVE_VSHR
9468 || insn->mve_op == MVE_VSHRN
9469 || insn->mve_op == MVE_VSLI
9470 || insn->mve_op == MVE_VSRI)
9471 print_mve_shift_n (info, given, insn->mve_op);
9472 else if (insn->mve_op == MVE_VSHLL_T2)
9473 {
9474 switch (value)
9475 {
9476 case 0x00:
9477 func (stream, "8");
9478 break;
9479 case 0x01:
9480 func (stream, "16");
9481 break;
9482 case 0x10:
9483 print_mve_undefined (info, UNDEF_SIZE_0);
9484 break;
9485 default:
9486 assert (0);
9487 break;
9488 }
9489 }
9490 else
9491 {
9492 if (insn->mve_op == MVE_VSHLC && value == 0)
9493 value = 32;
9494 func (stream, "%ld", value);
9495 value_in_comment = value;
9496 }
04d54ace 9497 break;
c507f10b
AV		 9498 case 'F':
9499 func (stream, "s%ld", value);
9500 break;
143275ea
AV		 9501 case 'Q':
9502 if (value & 0x8)
9503 func (stream, "<illegal reg q%ld.5>", value);
9504 else
9505 func (stream, "q%ld", value);
9506 break;
c507f10b
AV		 9507 case 'x':
9508 func (stream, "0x%08lx", value);
9509 break;
143275ea
AV		 9510 default:
9511 abort ();
9512 }
9513 break;
9514 default:
9515 abort ();
9516 }
73cd51e5
AV		 9517 }
9518 }
9519 else
9520 func (stream, "%c", *c);
9521 }
9522
9523 if (value_in_comment > 32 || value_in_comment < -16)
9524 func (stream, "\t; 0x%lx", value_in_comment);
9525
9526 if (is_unpredictable)
9527 print_mve_unpredictable (info, unpredictable_cond);
9528
9529 if (is_undefined)
9530 print_mve_undefined (info, undefined_cond);
9531
143275ea
AV		 9532 if ((vpt_block_state.in_vpt_block == FALSE)
9533 && !ifthen_state
9534 && (is_vpt_instruction (given) == TRUE))
9535 mark_inside_vpt_block (given);
9536 else if (vpt_block_state.in_vpt_block == TRUE)
9537 update_vpt_block_state ();
9538
73cd51e5
AV		 9539 return TRUE;
9540 }
9541 }
9542 return FALSE;
9543}
9544
9545
90ec0d68
MGD		 9546/* Return the name of a v7A special register. */
9547
43e65147 9548static const char *
90ec0d68
MGD		 9549banked_regname (unsigned reg)
9550{
9551 switch (reg)
9552 {
9553 case 15: return "CPSR";
43e65147 9554 case 32: return "R8_usr";
90ec0d68
MGD		 9555 case 33: return "R9_usr";
9556 case 34: return "R10_usr";
9557 case 35: return "R11_usr";
9558 case 36: return "R12_usr";
9559 case 37: return "SP_usr";
9560 case 38: return "LR_usr";
43e65147 9561 case 40: return "R8_fiq";
90ec0d68
MGD		 9562 case 41: return "R9_fiq";
9563 case 42: return "R10_fiq";
9564 case 43: return "R11_fiq";
9565 case 44: return "R12_fiq";
9566 case 45: return "SP_fiq";
9567 case 46: return "LR_fiq";
9568 case 48: return "LR_irq";
9569 case 49: return "SP_irq";
9570 case 50: return "LR_svc";
9571 case 51: return "SP_svc";
9572 case 52: return "LR_abt";
9573 case 53: return "SP_abt";
9574 case 54: return "LR_und";
9575 case 55: return "SP_und";
9576 case 60: return "LR_mon";
9577 case 61: return "SP_mon";
9578 case 62: return "ELR_hyp";
9579 case 63: return "SP_hyp";
9580 case 79: return "SPSR";
9581 case 110: return "SPSR_fiq";
9582 case 112: return "SPSR_irq";
9583 case 114: return "SPSR_svc";
9584 case 116: return "SPSR_abt";
9585 case 118: return "SPSR_und";
9586 case 124: return "SPSR_mon";
9587 case 126: return "SPSR_hyp";
9588 default: return NULL;
9589 }
9590}
9591
e797f7e0
MGD		 9592/* Return the name of the DMB/DSB option. */
9593static const char *
9594data_barrier_option (unsigned option)
9595{
9596 switch (option & 0xf)
9597 {
9598 case 0xf: return "sy";
9599 case 0xe: return "st";
9600 case 0xd: return "ld";
9601 case 0xb: return "ish";
9602 case 0xa: return "ishst";
9603 case 0x9: return "ishld";
9604 case 0x7: return "un";
9605 case 0x6: return "unst";
9606 case 0x5: return "nshld";
9607 case 0x3: return "osh";
9608 case 0x2: return "oshst";
9609 case 0x1: return "oshld";
9610 default: return NULL;
9611 }
9612}
9613
4a5329c6
ZW		 9614/* Print one ARM instruction from PC on INFO->STREAM. */
9615
9616static void
9617print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9618{
6b5d3a4d 9619 const struct opcode32 *insn;
6a51a8a8 9620 void *stream = info->stream;
6b5d3a4d 9621 fprintf_ftype func = info->fprintf_func;
b0e28b39 9622 struct arm_private_data *private_data = info->private_data;
252b5132 9623
16980d0b
JB		 9624 if (print_insn_coprocessor (pc, info, given, FALSE))
9625 return;
9626
9627 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9628 return;
9629
252b5132
RH		 9630 for (insn = arm_opcodes; insn->assembler; insn++)
9631 {
0313a2b8
NC		 9632 if ((given & insn->mask) != insn->value)
9633 continue;
823d2571
TG		 9634
9635 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9636 continue;
9637
9638 /* Special case: an instruction with all bits set in the condition field
9639 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9640 or by the catchall at the end of the table. */
9641 if ((given & 0xF0000000) != 0xF0000000
9642 || (insn->mask & 0xF0000000) == 0xF0000000
9643 || (insn->mask == 0 && insn->value == 0))
252b5132 9644 {
ff4a8d2b
NC		 9645 unsigned long u_reg = 16;
9646 unsigned long U_reg = 16;
ab8e2090 9647 bfd_boolean is_unpredictable = FALSE;
05413229 9648 signed long value_in_comment = 0;
6b5d3a4d 9649 const char *c;
b34976b6 9650
252b5132
RH		 9651 for (c = insn->assembler; *c; c++)
9652 {
9653 if (*c == '%')
9654 {
c1e26897
NC		 9655 bfd_boolean allow_unpredictable = FALSE;
9656
252b5132
RH		 9657 switch (*++c)
9658 {
9659 case '%':
9660 func (stream, "%%");
9661 break;
9662
9663 case 'a':
05413229 9664 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9665 break;
252b5132 9666
62b3e311
PB		 9667 case 'P':
9668 /* Set P address bit and use normal address
9669 printing routine. */
c1e26897 9670 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9671 break;
9672
c1e26897
NC		 9673 case 'S':
9674 allow_unpredictable = TRUE;
1a0670f3 9675 /* Fall through. */
252b5132
RH		 9676 case 's':
9677 if ((given & 0x004f0000) == 0x004f0000)
9678 {
58efb6c0 9679 /* PC relative with immediate offset. */
f8b960bc 9680 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9681
aefd8a40
NC		 9682 if (PRE_BIT_SET)
9683 {
26d97720
NS		 9684 /* Elide positive zero offset. */
9685 if (offset || NEGATIVE_BIT_SET)
9686 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9687 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9688 else
26d97720
NS		 9689 func (stream, "[pc]\t; ");
9690 if (NEGATIVE_BIT_SET)
9691 offset = -offset;
aefd8a40
NC		 9692 info->print_address_func (offset + pc + 8, info);
9693 }
9694 else
9695 {
26d97720
NS		 9696 /* Always show the offset. */
9697 func (stream, "[pc], #%s%d",
d908c8af 9698 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9699 if (! allow_unpredictable)
9700 is_unpredictable = TRUE;
aefd8a40 9701 }
252b5132
RH		 9702 }
9703 else
9704 {
fe56b6ce
NC		 9705 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9706
b34976b6 9707 func (stream, "[%s",
252b5132 9708 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9709
c1e26897 9710 if (PRE_BIT_SET)
252b5132 9711 {
c1e26897 9712 if (IMMEDIATE_BIT_SET)
252b5132 9713 {
26d97720
NS		 9714 /* Elide offset for non-writeback
9715 positive zero. */
9716 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9717 || offset)
9718 func (stream, ", #%s%d",
9719 NEGATIVE_BIT_SET ? "-" : "", offset);
9720
9721 if (NEGATIVE_BIT_SET)
9722 offset = -offset;
945ee430 9723
fe56b6ce 9724 value_in_comment = offset;
252b5132 9725 }
945ee430 9726 else
ff4a8d2b
NC		 9727 {
9728 /* Register Offset or Register Pre-Indexed. */
9729 func (stream, ", %s%s",
9730 NEGATIVE_BIT_SET ? "-" : "",
9731 arm_regnames[given & 0xf]);
9732
9733 /* Writing back to the register that is the source/
9734 destination of the load/store is unpredictable. */
9735 if (! allow_unpredictable
9736 && WRITEBACK_BIT_SET
9737 && ((given & 0xf) == ((given >> 12) & 0xf)))
9738 is_unpredictable = TRUE;
9739 }
252b5132 9740
b34976b6 9741 func (stream, "]%s",
c1e26897 9742 WRITEBACK_BIT_SET ? "!" : "");
252b5132 9743 }
945ee430 9744 else
252b5132 9745 {
c1e26897 9746 if (IMMEDIATE_BIT_SET)
252b5132 9747 {
945ee430 9748 /* Immediate Post-indexed. */
aefd8a40 9749 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 9750 func (stream, "], #%s%d",
9751 NEGATIVE_BIT_SET ? "-" : "", offset);
9752 if (NEGATIVE_BIT_SET)
9753 offset = -offset;
fe56b6ce 9754 value_in_comment = offset;
252b5132 9755 }
945ee430 9756 else
ff4a8d2b
NC		 9757 {
9758 /* Register Post-indexed. */
9759 func (stream, "], %s%s",
9760 NEGATIVE_BIT_SET ? "-" : "",
9761 arm_regnames[given & 0xf]);
9762
9763 /* Writing back to the register that is the source/
9764 destination of the load/store is unpredictable. */
9765 if (! allow_unpredictable
9766 && (given & 0xf) == ((given >> 12) & 0xf))
9767 is_unpredictable = TRUE;
9768 }
c1e26897 9769
07a28fab
NC		 9770 if (! allow_unpredictable)
9771 {
9772 /* Writeback is automatically implied by post- addressing.
9773 Setting the W bit is unnecessary and ARM specify it as
9774 being unpredictable. */
9775 if (WRITEBACK_BIT_SET
9776 /* Specifying the PC register as the post-indexed
9777 registers is also unpredictable. */
ab8e2090
NC		 9778 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9779 is_unpredictable = TRUE;
07a28fab 9780 }
252b5132
RH		 9781 }
9782 }
9783 break;
b34976b6 9784
252b5132 9785 case 'b':
6b5d3a4d 9786 {
f8b960bc 9787 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 9788 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 9789 }
252b5132
RH		 9790 break;
9791
9792 case 'c':
c22aaad1
PB		 9793 if (((given >> 28) & 0xf) != 0xe)
9794 func (stream, "%s",
9795 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 9796 break;
9797
9798 case 'm':
9799 {
9800 int started = 0;
9801 int reg;
9802
9803 func (stream, "{");
9804 for (reg = 0; reg < 16; reg++)
9805 if ((given & (1 << reg)) != 0)
9806 {
9807 if (started)
9808 func (stream, ", ");
9809 started = 1;
9810 func (stream, "%s", arm_regnames[reg]);
9811 }
9812 func (stream, "}");
ab8e2090
NC		 9813 if (! started)
9814 is_unpredictable = TRUE;
252b5132
RH		 9815 }
9816 break;
9817
37b37b2d 9818 case 'q':
78c66db8 9819 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 9820 break;
9821
252b5132
RH		 9822 case 'o':
9823 if ((given & 0x02000000) != 0)
9824 {
a415b1cd
JB		 9825 unsigned int rotate = (given & 0xf00) >> 7;
9826 unsigned int immed = (given & 0xff);
9827 unsigned int a, i;
9828
9829 a = (((immed << (32 - rotate))
9830 | (immed >> rotate)) & 0xffffffff);
9831 /* If there is another encoding with smaller rotate,
9832 the rotate should be specified directly. */
9833 for (i = 0; i < 32; i += 2)
9834 if ((a << i | a >> (32 - i)) <= 0xff)
9835 break;
9836
9837 if (i != rotate)
9838 func (stream, "#%d, %d", immed, rotate);
9839 else
9840 func (stream, "#%d", a);
9841 value_in_comment = a;
252b5132
RH		 9842 }
9843 else
78c66db8 9844 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 9845 break;
9846
9847 case 'p':
9848 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 9849 {
823d2571
TG		 9850 arm_feature_set arm_ext_v6 =
9851 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9852
aefd8a40
NC		 9853 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9854 mechanism for setting PSR flag bits. They are
9855 obsolete in V6 onwards. */
823d2571
TG		 9856 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9857 arm_ext_v6))
aefd8a40 9858 func (stream, "p");
4ab90a7a
AV		 9859 else
9860 is_unpredictable = TRUE;
aefd8a40 9861 }
252b5132
RH		 9862 break;
9863
9864 case 't':
9865 if ((given & 0x01200000) == 0x00200000)
9866 func (stream, "t");
9867 break;
9868
252b5132 9869 case 'A':
05413229
NC		 9870 {
9871 int offset = given & 0xff;
f02232aa 9872
05413229 9873 value_in_comment = offset * 4;
c1e26897 9874 if (NEGATIVE_BIT_SET)
05413229 9875 value_in_comment = - value_in_comment;
f02232aa 9876
05413229 9877 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9878
c1e26897 9879 if (PRE_BIT_SET)
05413229
NC		 9880 {
9881 if (offset)
fe56b6ce 9882 func (stream, ", #%d]%s",
d908c8af 9883 (int) value_in_comment,
c1e26897 9884 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9885 else
9886 func (stream, "]");
9887 }
9888 else
9889 {
9890 func (stream, "]");
f02232aa 9891
c1e26897 9892 if (WRITEBACK_BIT_SET)
05413229
NC		 9893 {
9894 if (offset)
d908c8af 9895 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9896 }
9897 else
fe56b6ce 9898 {
d908c8af 9899 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 9900 value_in_comment = offset;
9901 }
05413229
NC		 9902 }
9903 }
252b5132
RH		 9904 break;
9905
077b8428
NC		 9906 case 'B':
9907 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9908 {
9909 bfd_vma address;
9910 bfd_vma offset = 0;
b34976b6 9911
c1e26897 9912 if (! NEGATIVE_BIT_SET)
077b8428
NC		 9913 /* Is signed, hi bits should be ones. */
9914 offset = (-1) ^ 0x00ffffff;
9915
9916 /* Offset is (SignExtend(offset field)<<2). */
9917 offset += given & 0x00ffffff;
9918 offset <<= 2;
9919 address = offset + pc + 8;
b34976b6 9920
8f06b2d8
PB		 9921 if (given & 0x01000000)
9922 /* H bit allows addressing to 2-byte boundaries. */
9923 address += 2;
b1ee46c5 9924
8f06b2d8 9925 info->print_address_func (address, info);
b1ee46c5 9926 }
b1ee46c5
AH		 9927 break;
9928
252b5132 9929 case 'C':
90ec0d68
MGD		 9930 if ((given & 0x02000200) == 0x200)
9931 {
9932 const char * name;
9933 unsigned sysm = (given & 0x004f0000) >> 16;
9934
9935 sysm |= (given & 0x300) >> 4;
9936 name = banked_regname (sysm);
9937
9938 if (name != NULL)
9939 func (stream, "%s", name);
9940 else
d908c8af 9941 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 9942 }
9943 else
9944 {
43e65147 9945 func (stream, "%cPSR_",
90ec0d68
MGD		 9946 (given & 0x00400000) ? 'S' : 'C');
9947 if (given & 0x80000)
9948 func (stream, "f");
9949 if (given & 0x40000)
9950 func (stream, "s");
9951 if (given & 0x20000)
9952 func (stream, "x");
9953 if (given & 0x10000)
9954 func (stream, "c");
9955 }
252b5132
RH		 9956 break;
9957
62b3e311 9958 case 'U':
43e65147 9959 if ((given & 0xf0) == 0x60)
62b3e311 9960 {
52e7f43d
RE		 9961 switch (given & 0xf)
9962 {
9963 case 0xf: func (stream, "sy"); break;
9964 default:
9965 func (stream, "#%d", (int) given & 0xf);
9966 break;
9967 }
43e65147
L		 9968 }
9969 else
52e7f43d 9970 {
e797f7e0
MGD		 9971 const char * opt = data_barrier_option (given & 0xf);
9972 if (opt != NULL)
9973 func (stream, "%s", opt);
9974 else
52e7f43d 9975 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 9976 }
9977 break;
9978
b34976b6 9979 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 9980 case '5': case '6': case '7': case '8': case '9':
9981 {
16980d0b
JB		 9982 int width;
9983 unsigned long value;
252b5132 9984
16980d0b 9985 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9986
252b5132
RH		 9987 switch (*c)
9988 {
ab8e2090
NC		 9989 case 'R':
9990 if (value == 15)
9991 is_unpredictable = TRUE;
9992 /* Fall through. */
16980d0b 9993 case 'r':
9eb6c0f1
MGD		 9994 case 'T':
9995 /* We want register + 1 when decoding T. */
9996 if (*c == 'T')
9997 ++value;
9998
ff4a8d2b
NC		 9999 if (c[1] == 'u')
10000 {
10001 /* Eat the 'u' character. */
10002 ++ c;
10003
10004 if (u_reg == value)
10005 is_unpredictable = TRUE;
10006 u_reg = value;
10007 }
10008 if (c[1] == 'U')
10009 {
10010 /* Eat the 'U' character. */
10011 ++ c;
10012
10013 if (U_reg == value)
10014 is_unpredictable = TRUE;
10015 U_reg = value;
10016 }
16980d0b
JB		 10017 func (stream, "%s", arm_regnames[value]);
10018 break;
10019 case 'd':
10020 func (stream, "%ld", value);
05413229 10021 value_in_comment = value;
16980d0b
JB		 10022 break;
10023 case 'b':
10024 func (stream, "%ld", value * 8);
05413229 10025 value_in_comment = value * 8;
16980d0b
JB		 10026 break;
10027 case 'W':
10028 func (stream, "%ld", value + 1);
05413229 10029 value_in_comment = value + 1;
16980d0b
JB		 10030 break;
10031 case 'x':
10032 func (stream, "0x%08lx", value);
10033
10034 /* Some SWI instructions have special
10035 meanings. */
10036 if ((given & 0x0fffffff) == 0x0FF00000)
10037 func (stream, "\t; IMB");
10038 else if ((given & 0x0fffffff) == 0x0FF00001)
10039 func (stream, "\t; IMBRange");
10040 break;
10041 case 'X':
10042 func (stream, "%01lx", value & 0xf);
05413229 10043 value_in_comment = value;
252b5132
RH		 10044 break;
10045 case '`':
10046 c++;
16980d0b 10047 if (value == 0)
252b5132
RH		 10048 func (stream, "%c", *c);
10049 break;
10050 case '\'':
10051 c++;
16980d0b 10052 if (value == ((1ul << width) - 1))
252b5132
RH		 10053 func (stream, "%c", *c);
10054 break;
10055 case '?':
fe56b6ce 10056 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10057 c += 1 << width;
252b5132
RH		 10058 break;
10059 default:
10060 abort ();
10061 }
dffaa15c
AM		 10062 }
10063 break;
0dd132b6 10064
dffaa15c
AM		 10065 case 'e':
10066 {
10067 int imm;
0dd132b6 10068
dffaa15c
AM		 10069 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10070 func (stream, "%d", imm);
10071 value_in_comment = imm;
10072 }
10073 break;
fe56b6ce 10074
dffaa15c
AM		 10075 case 'E':
10076 /* LSB and WIDTH fields of BFI or BFC. The machine-
10077 language instruction encodes LSB and MSB. */
10078 {
10079 long msb = (given & 0x001f0000) >> 16;
10080 long lsb = (given & 0x00000f80) >> 7;
10081 long w = msb - lsb + 1;
0a003adc 10082
dffaa15c
AM		 10083 if (w > 0)
10084 func (stream, "#%lu, #%lu", lsb, w);
10085 else
10086 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10087 }
10088 break;
90ec0d68 10089
dffaa15c
AM		 10090 case 'R':
10091 /* Get the PSR/banked register name. */
10092 {
10093 const char * name;
10094 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10095
dffaa15c
AM		 10096 sysm |= (given & 0x300) >> 4;
10097 name = banked_regname (sysm);
90ec0d68 10098
dffaa15c
AM		 10099 if (name != NULL)
10100 func (stream, "%s", name);
10101 else
10102 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10103 }
10104 break;
fe56b6ce 10105
dffaa15c
AM		 10106 case 'V':
10107 /* 16-bit unsigned immediate from a MOVT or MOVW
10108 instruction, encoded in bits 0:11 and 15:19. */
10109 {
10110 long hi = (given & 0x000f0000) >> 4;
10111 long lo = (given & 0x00000fff);
10112 long imm16 = hi | lo;
0a003adc 10113
dffaa15c
AM		 10114 func (stream, "#%lu", imm16);
10115 value_in_comment = imm16;
252b5132 10116 }
dffaa15c
AM		 10117 break;
10118
10119 default:
10120 abort ();
252b5132
RH		 10121 }
10122 }
10123 else
10124 func (stream, "%c", *c);
10125 }
05413229
NC		 10126
10127 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10128 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10129
10130 if (is_unpredictable)
10131 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10132
4a5329c6 10133 return;
252b5132
RH		 10134 }
10135 }
0b347048
TC		 10136 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10137 return;
252b5132
RH		 10138}
10139
4a5329c6 10140/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10141
4a5329c6
ZW		 10142static void
10143print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10144{
6b5d3a4d 10145 const struct opcode16 *insn;
6a51a8a8
AM		 10146 void *stream = info->stream;
10147 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10148
10149 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10150 if ((given & insn->mask) == insn->value)
10151 {
05413229 10152 signed long value_in_comment = 0;
6b5d3a4d 10153 const char *c = insn->assembler;
05413229 10154
c19d1205
ZW		 10155 for (; *c; c++)
10156 {
10157 int domaskpc = 0;
10158 int domasklr = 0;
10159
10160 if (*c != '%')
10161 {
10162 func (stream, "%c", *c);
10163 continue;
10164 }
252b5132 10165
c19d1205
ZW		 10166 switch (*++c)
10167 {
10168 case '%':
10169 func (stream, "%%");
10170 break;
b34976b6 10171
c22aaad1
PB		 10172 case 'c':
10173 if (ifthen_state)
10174 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10175 break;
10176
10177 case 'C':
10178 if (ifthen_state)
10179 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10180 else
10181 func (stream, "s");
10182 break;
10183
10184 case 'I':
10185 {
10186 unsigned int tmp;
10187
10188 ifthen_next_state = given & 0xff;
10189 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10190 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10191 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10192 }
10193 break;
10194
10195 case 'x':
10196 if (ifthen_next_state)
10197 func (stream, "\t; unpredictable branch in IT block\n");
10198 break;
10199
10200 case 'X':
10201 if (ifthen_state)
10202 func (stream, "\t; unpredictable <IT:%s>",
10203 arm_conditional[IFTHEN_COND]);
10204 break;
10205
c19d1205
ZW		 10206 case 'S':
10207 {
10208 long reg;
10209
10210 reg = (given >> 3) & 0x7;
10211 if (given & (1 << 6))
10212 reg += 8;
4f3c3dbb 10213
c19d1205
ZW		 10214 func (stream, "%s", arm_regnames[reg]);
10215 }
10216 break;
baf0cc5e 10217
c19d1205 10218 case 'D':
4f3c3dbb 10219 {
c19d1205
ZW		 10220 long reg;
10221
10222 reg = given & 0x7;
10223 if (given & (1 << 7))
10224 reg += 8;
10225
10226 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10227 }
c19d1205
ZW		 10228 break;
10229
10230 case 'N':
10231 if (given & (1 << 8))
10232 domasklr = 1;
10233 /* Fall through. */
10234 case 'O':
10235 if (*c == 'O' && (given & (1 << 8)))
10236 domaskpc = 1;
10237 /* Fall through. */
10238 case 'M':
10239 {
10240 int started = 0;
10241 int reg;
10242
10243 func (stream, "{");
10244
10245 /* It would be nice if we could spot
10246 ranges, and generate the rS-rE format: */
10247 for (reg = 0; (reg < 8); reg++)
10248 if ((given & (1 << reg)) != 0)
10249 {
10250 if (started)
10251 func (stream, ", ");
10252 started = 1;
10253 func (stream, "%s", arm_regnames[reg]);
10254 }
10255
10256 if (domasklr)
10257 {
10258 if (started)
10259 func (stream, ", ");
10260 started = 1;
d908c8af 10261 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10262 }
10263
10264 if (domaskpc)
10265 {
10266 if (started)
10267 func (stream, ", ");
d908c8af 10268 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10269 }
10270
10271 func (stream, "}");
10272 }
10273 break;
10274
4547cb56
NC		 10275 case 'W':
10276 /* Print writeback indicator for a LDMIA. We are doing a
10277 writeback if the base register is not in the register
10278 mask. */
10279 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10280 func (stream, "!");
dffaa15c 10281 break;
4547cb56 10282
c19d1205
ZW		 10283 case 'b':
10284 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10285 {
10286 bfd_vma address = (pc + 4
10287 + ((given & 0x00f8) >> 2)
10288 + ((given & 0x0200) >> 3));
10289 info->print_address_func (address, info);
10290 }
10291 break;
10292
10293 case 's':
10294 /* Right shift immediate -- bits 6..10; 1-31 print
10295 as themselves, 0 prints as 32. */
10296 {
10297 long imm = (given & 0x07c0) >> 6;
10298 if (imm == 0)
10299 imm = 32;
0fd3a477 10300 func (stream, "#%ld", imm);
c19d1205
ZW		 10301 }
10302 break;
10303
10304 case '0': case '1': case '2': case '3': case '4':
10305 case '5': case '6': case '7': case '8': case '9':
10306 {
10307 int bitstart = *c++ - '0';
10308 int bitend = 0;
10309
10310 while (*c >= '0' && *c <= '9')
10311 bitstart = (bitstart * 10) + *c++ - '0';
10312
10313 switch (*c)
10314 {
10315 case '-':
10316 {
f8b960bc 10317 bfd_vma reg;
c19d1205
ZW		 10318
10319 c++;
10320 while (*c >= '0' && *c <= '9')
10321 bitend = (bitend * 10) + *c++ - '0';
10322 if (!bitend)
10323 abort ();
10324 reg = given >> bitstart;
10325 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10326
c19d1205
ZW		 10327 switch (*c)
10328 {
10329 case 'r':
10330 func (stream, "%s", arm_regnames[reg]);
10331 break;
10332
10333 case 'd':
d908c8af 10334 func (stream, "%ld", (long) reg);
05413229 10335 value_in_comment = reg;
c19d1205
ZW		 10336 break;
10337
10338 case 'H':
d908c8af 10339 func (stream, "%ld", (long) (reg << 1));
05413229 10340 value_in_comment = reg << 1;
c19d1205
ZW		 10341 break;
10342
10343 case 'W':
d908c8af 10344 func (stream, "%ld", (long) (reg << 2));
05413229 10345 value_in_comment = reg << 2;
c19d1205
ZW		 10346 break;
10347
10348 case 'a':
10349 /* PC-relative address -- the bottom two
10350 bits of the address are dropped
10351 before the calculation. */
10352 info->print_address_func
10353 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10354 value_in_comment = 0;
c19d1205
ZW		 10355 break;
10356
10357 case 'x':
d908c8af 10358 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10359 break;
10360
c19d1205
ZW		 10361 case 'B':
10362 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 10363 info->print_address_func (reg * 2 + pc + 4, info);
05413229 10364 value_in_comment = 0;
c19d1205
ZW		 10365 break;
10366
10367 case 'c':
c22aaad1 10368 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10369 break;
10370
10371 default:
10372 abort ();
10373 }
10374 }
10375 break;
10376
10377 case '\'':
10378 c++;
10379 if ((given & (1 << bitstart)) != 0)
10380 func (stream, "%c", *c);
10381 break;
10382
10383 case '?':
10384 ++c;
10385 if ((given & (1 << bitstart)) != 0)
10386 func (stream, "%c", *c++);
10387 else
10388 func (stream, "%c", *++c);
10389 break;
10390
10391 default:
10392 abort ();
10393 }
10394 }
10395 break;
10396
10397 default:
10398 abort ();
10399 }
10400 }
05413229
NC		 10401
10402 if (value_in_comment > 32 || value_in_comment < -16)
10403 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10404 return;
c19d1205
ZW		 10405 }
10406
10407 /* No match. */
0b347048
TC		 10408 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10409 return;
c19d1205
ZW		 10410}
10411
62b3e311 10412/* Return the name of an V7M special register. */
fe56b6ce 10413
62b3e311
PB		 10414static const char *
10415psr_name (int regno)
10416{
10417 switch (regno)
10418 {
1a336194
TP		 10419 case 0x0: return "APSR";
10420 case 0x1: return "IAPSR";
10421 case 0x2: return "EAPSR";
10422 case 0x3: return "PSR";
10423 case 0x5: return "IPSR";
10424 case 0x6: return "EPSR";
10425 case 0x7: return "IEPSR";
10426 case 0x8: return "MSP";
10427 case 0x9: return "PSP";
10428 case 0xa: return "MSPLIM";
10429 case 0xb: return "PSPLIM";
10430 case 0x10: return "PRIMASK";
10431 case 0x11: return "BASEPRI";
10432 case 0x12: return "BASEPRI_MAX";
10433 case 0x13: return "FAULTMASK";
10434 case 0x14: return "CONTROL";
16a1fa25
TP		 10435 case 0x88: return "MSP_NS";
10436 case 0x89: return "PSP_NS";
1a336194
TP		 10437 case 0x8a: return "MSPLIM_NS";
10438 case 0x8b: return "PSPLIM_NS";
10439 case 0x90: return "PRIMASK_NS";
10440 case 0x91: return "BASEPRI_NS";
10441 case 0x93: return "FAULTMASK_NS";
10442 case 0x94: return "CONTROL_NS";
10443 case 0x98: return "SP_NS";
62b3e311
PB		 10444 default: return "<unknown>";
10445 }
10446}
10447
4a5329c6
ZW		 10448/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10449
10450static void
10451print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10452{
6b5d3a4d 10453 const struct opcode32 *insn;
c19d1205
ZW		 10454 void *stream = info->stream;
10455 fprintf_ftype func = info->fprintf_func;
73cd51e5 10456 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10457
16980d0b
JB		 10458 if (print_insn_coprocessor (pc, info, given, TRUE))
10459 return;
10460
73cd51e5
AV		 10461 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10462 return;
10463
10464 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10465 return;
10466
c19d1205
ZW		 10467 for (insn = thumb32_opcodes; insn->assembler; insn++)
10468 if ((given & insn->mask) == insn->value)
10469 {
4b5a202f 10470 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10471 bfd_boolean is_unpredictable = FALSE;
05413229 10472 signed long value_in_comment = 0;
6b5d3a4d 10473 const char *c = insn->assembler;
05413229 10474
c19d1205
ZW		 10475 for (; *c; c++)
10476 {
10477 if (*c != '%')
10478 {
10479 func (stream, "%c", *c);
10480 continue;
10481 }
10482
10483 switch (*++c)
10484 {
10485 case '%':
10486 func (stream, "%%");
10487 break;
10488
c22aaad1
PB		 10489 case 'c':
10490 if (ifthen_state)
10491 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10492 break;
10493
10494 case 'x':
10495 if (ifthen_next_state)
10496 func (stream, "\t; unpredictable branch in IT block\n");
10497 break;
10498
10499 case 'X':
10500 if (ifthen_state)
10501 func (stream, "\t; unpredictable <IT:%s>",
10502 arm_conditional[IFTHEN_COND]);
10503 break;
10504
c19d1205
ZW		 10505 case 'I':
10506 {
10507 unsigned int imm12 = 0;
fe56b6ce 10508
c19d1205
ZW		 10509 imm12 |= (given & 0x000000ffu);
10510 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10511 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10512 func (stream, "#%u", imm12);
10513 value_in_comment = imm12;
c19d1205
ZW		 10514 }
10515 break;
10516
10517 case 'M':
10518 {
10519 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10520
c19d1205
ZW		 10521 bits |= (given & 0x000000ffu);
10522 bits |= (given & 0x00007000u) >> 4;
10523 bits |= (given & 0x04000000u) >> 15;
10524 imm8 = (bits & 0x0ff);
10525 mod = (bits & 0xf00) >> 8;
10526 switch (mod)
10527 {
10528 case 0: imm = imm8; break;
c1e26897
NC		 10529 case 1: imm = ((imm8 << 16) | imm8); break;
10530 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10531 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10532 default:
10533 mod = (bits & 0xf80) >> 7;
10534 imm8 = (bits & 0x07f) | 0x80;
10535 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10536 }
fe56b6ce
NC		 10537 func (stream, "#%u", imm);
10538 value_in_comment = imm;
c19d1205
ZW		 10539 }
10540 break;
43e65147 10541
c19d1205
ZW		 10542 case 'J':
10543 {
10544 unsigned int imm = 0;
fe56b6ce 10545
c19d1205
ZW		 10546 imm |= (given & 0x000000ffu);
10547 imm |= (given & 0x00007000u) >> 4;
10548 imm |= (given & 0x04000000u) >> 15;
10549 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10550 func (stream, "#%u", imm);
10551 value_in_comment = imm;
c19d1205
ZW		 10552 }
10553 break;
10554
10555 case 'K':
10556 {
10557 unsigned int imm = 0;
fe56b6ce 10558
c19d1205
ZW		 10559 imm |= (given & 0x000f0000u) >> 16;
10560 imm |= (given & 0x00000ff0u) >> 0;
10561 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10562 func (stream, "#%u", imm);
10563 value_in_comment = imm;
c19d1205
ZW		 10564 }
10565 break;
10566
74db7efb
NC		 10567 case 'H':
10568 {
10569 unsigned int imm = 0;
10570
10571 imm |= (given & 0x000f0000u) >> 4;
10572 imm |= (given & 0x00000fffu) >> 0;
10573 func (stream, "#%u", imm);
10574 value_in_comment = imm;
10575 }
10576 break;
10577
90ec0d68
MGD		 10578 case 'V':
10579 {
10580 unsigned int imm = 0;
10581
10582 imm |= (given & 0x00000fffu);
10583 imm |= (given & 0x000f0000u) >> 4;
10584 func (stream, "#%u", imm);
10585 value_in_comment = imm;
10586 }
10587 break;
10588
c19d1205
ZW		 10589 case 'S':
10590 {
10591 unsigned int reg = (given & 0x0000000fu);
10592 unsigned int stp = (given & 0x00000030u) >> 4;
10593 unsigned int imm = 0;
10594 imm |= (given & 0x000000c0u) >> 6;
10595 imm |= (given & 0x00007000u) >> 10;
10596
10597 func (stream, "%s", arm_regnames[reg]);
10598 switch (stp)
10599 {
10600 case 0:
10601 if (imm > 0)
10602 func (stream, ", lsl #%u", imm);
10603 break;
10604
10605 case 1:
10606 if (imm == 0)
10607 imm = 32;
10608 func (stream, ", lsr #%u", imm);
10609 break;
10610
10611 case 2:
10612 if (imm == 0)
10613 imm = 32;
10614 func (stream, ", asr #%u", imm);
10615 break;
10616
10617 case 3:
10618 if (imm == 0)
10619 func (stream, ", rrx");
10620 else
10621 func (stream, ", ror #%u", imm);
10622 }
10623 }
10624 break;
10625
10626 case 'a':
10627 {
10628 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 10629 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 10630 unsigned int op = (given & 0x00000f00) >> 8;
10631 unsigned int i12 = (given & 0x00000fff);
10632 unsigned int i8 = (given & 0x000000ff);
10633 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 10634 bfd_vma offset = 0;
c19d1205
ZW		 10635
10636 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 10637 if (U) /* 12-bit positive immediate offset. */
10638 {
10639 offset = i12;
10640 if (Rn != 15)
10641 value_in_comment = offset;
10642 }
10643 else if (Rn == 15) /* 12-bit negative immediate offset. */
10644 offset = - (int) i12;
10645 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 10646 {
10647 unsigned int Rm = (i8 & 0x0f);
10648 unsigned int sh = (i8 & 0x30) >> 4;
05413229 10649
c19d1205
ZW		 10650 func (stream, ", %s", arm_regnames[Rm]);
10651 if (sh)
10652 func (stream, ", lsl #%u", sh);
10653 func (stream, "]");
10654 break;
10655 }
10656 else switch (op)
10657 {
05413229 10658 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 10659 offset = i8;
10660 break;
10661
05413229 10662 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10663 offset = -i8;
10664 break;
10665
05413229 10666 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10667 offset = i8;
10668 writeback = TRUE;
10669 break;
10670
05413229 10671 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10672 offset = -i8;
10673 writeback = TRUE;
10674 break;
10675
05413229 10676 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10677 offset = i8;
10678 postind = TRUE;
10679 break;
10680
05413229 10681 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10682 offset = -i8;
10683 postind = TRUE;
10684 break;
10685
10686 default:
10687 func (stream, ", <undefined>]");
10688 goto skip;
10689 }
10690
10691 if (postind)
d908c8af 10692 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10693 else
10694 {
10695 if (offset)
d908c8af 10696 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 10697 func (stream, writeback ? "]!" : "]");
10698 }
10699
10700 if (Rn == 15)
10701 {
10702 func (stream, "\t; ");
10703 info->print_address_func (((pc + 4) & ~3) + offset, info);
10704 }
10705 }
10706 skip:
10707 break;
10708
10709 case 'A':
10710 {
c1e26897
NC		 10711 unsigned int U = ! NEGATIVE_BIT_SET;
10712 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 10713 unsigned int Rn = (given & 0x000f0000) >> 16;
10714 unsigned int off = (given & 0x000000ff);
10715
10716 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 10717
10718 if (PRE_BIT_SET)
c19d1205
ZW		 10719 {
10720 if (off || !U)
05413229
NC		 10721 {
10722 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 10723 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10724 }
c19d1205
ZW		 10725 func (stream, "]");
10726 if (W)
10727 func (stream, "!");
10728 }
10729 else
10730 {
10731 func (stream, "], ");
10732 if (W)
05413229
NC		 10733 {
10734 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 10735 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10736 }
c19d1205 10737 else
fe56b6ce
NC		 10738 {
10739 func (stream, "{%u}", off);
10740 value_in_comment = off;
10741 }
c19d1205
ZW		 10742 }
10743 }
10744 break;
10745
10746 case 'w':
10747 {
10748 unsigned int Sbit = (given & 0x01000000) >> 24;
10749 unsigned int type = (given & 0x00600000) >> 21;
05413229 10750
c19d1205
ZW		 10751 switch (type)
10752 {
10753 case 0: func (stream, Sbit ? "sb" : "b"); break;
10754 case 1: func (stream, Sbit ? "sh" : "h"); break;
10755 case 2:
10756 if (Sbit)
10757 func (stream, "??");
10758 break;
10759 case 3:
10760 func (stream, "??");
10761 break;
10762 }
10763 }
10764 break;
10765
4b5a202f
AV		 10766 case 'n':
10767 is_clrm = TRUE;
10768 /* Fall through. */
c19d1205
ZW		 10769 case 'm':
10770 {
10771 int started = 0;
10772 int reg;
10773
10774 func (stream, "{");
10775 for (reg = 0; reg < 16; reg++)
10776 if ((given & (1 << reg)) != 0)
10777 {
10778 if (started)
10779 func (stream, ", ");
10780 started = 1;
4b5a202f
AV		 10781 if (is_clrm && reg == 13)
10782 func (stream, "(invalid: %s)", arm_regnames[reg]);
10783 else if (is_clrm && reg == 15)
10784 func (stream, "%s", "APSR");
10785 else
10786 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 10787 }
10788 func (stream, "}");
10789 }
10790 break;
10791
10792 case 'E':
10793 {
10794 unsigned int msb = (given & 0x0000001f);
10795 unsigned int lsb = 0;
fe56b6ce 10796
c19d1205
ZW		 10797 lsb |= (given & 0x000000c0u) >> 6;
10798 lsb |= (given & 0x00007000u) >> 10;
10799 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10800 }
10801 break;
10802
10803 case 'F':
10804 {
10805 unsigned int width = (given & 0x0000001f) + 1;
10806 unsigned int lsb = 0;
fe56b6ce 10807
c19d1205
ZW		 10808 lsb |= (given & 0x000000c0u) >> 6;
10809 lsb |= (given & 0x00007000u) >> 10;
10810 func (stream, "#%u, #%u", lsb, width);
10811 }
10812 break;
10813
e12437dc
AV		 10814 case 'G':
10815 {
10816 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10817 func (stream, "%x", boff);
10818 }
10819 break;
10820
e5d6e09e
AV		 10821 case 'W':
10822 {
10823 unsigned int immA = (given & 0x001f0000u) >> 16;
10824 unsigned int immB = (given & 0x000007feu) >> 1;
10825 unsigned int immC = (given & 0x00000800u) >> 11;
10826 bfd_vma offset = 0;
10827
10828 offset |= immA << 12;
10829 offset |= immB << 2;
10830 offset |= immC << 1;
10831 /* Sign extend. */
10832 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10833
10834 info->print_address_func (pc + 4 + offset, info);
10835 }
10836 break;
10837
1caf72a5
AV		 10838 case 'Y':
10839 {
10840 unsigned int immA = (given & 0x007f0000u) >> 16;
10841 unsigned int immB = (given & 0x000007feu) >> 1;
10842 unsigned int immC = (given & 0x00000800u) >> 11;
10843 bfd_vma offset = 0;
10844
10845 offset |= immA << 12;
10846 offset |= immB << 2;
10847 offset |= immC << 1;
10848 /* Sign extend. */
10849 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10850
10851 info->print_address_func (pc + 4 + offset, info);
10852 }
10853 break;
10854
1889da70
AV		 10855 case 'Z':
10856 {
10857 unsigned int immA = (given & 0x00010000u) >> 16;
10858 unsigned int immB = (given & 0x000007feu) >> 1;
10859 unsigned int immC = (given & 0x00000800u) >> 11;
10860 bfd_vma offset = 0;
10861
10862 offset |= immA << 12;
10863 offset |= immB << 2;
10864 offset |= immC << 1;
10865 /* Sign extend. */
10866 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10867
10868 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 10869
10870 unsigned int T = (given & 0x00020000u) >> 17;
10871 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10872 unsigned int boffset = (T == 1) ? 4 : 2;
10873 func (stream, ", ");
10874 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10875 }
10876 break;
10877
60f993ce
AV		 10878 case 'Q':
10879 {
10880 unsigned int immh = (given & 0x000007feu) >> 1;
10881 unsigned int imml = (given & 0x00000800u) >> 11;
10882 bfd_vma imm32 = 0;
10883
10884 imm32 |= immh << 2;
10885 imm32 |= imml << 1;
10886
10887 info->print_address_func (pc + 4 + imm32, info);
10888 }
10889 break;
10890
10891 case 'P':
10892 {
10893 unsigned int immh = (given & 0x000007feu) >> 1;
10894 unsigned int imml = (given & 0x00000800u) >> 11;
10895 bfd_vma imm32 = 0;
10896
10897 imm32 |= immh << 2;
10898 imm32 |= imml << 1;
10899
10900 info->print_address_func (pc + 4 - imm32, info);
10901 }
10902 break;
10903
c19d1205
ZW		 10904 case 'b':
10905 {
10906 unsigned int S = (given & 0x04000000u) >> 26;
10907 unsigned int J1 = (given & 0x00002000u) >> 13;
10908 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 10909 bfd_vma offset = 0;
c19d1205
ZW		 10910
10911 offset |= !S << 20;
10912 offset |= J2 << 19;
10913 offset |= J1 << 18;
10914 offset |= (given & 0x003f0000) >> 4;
10915 offset |= (given & 0x000007ff) << 1;
10916 offset -= (1 << 20);
10917
10918 info->print_address_func (pc + 4 + offset, info);
10919 }
10920 break;
10921
10922 case 'B':
10923 {
10924 unsigned int S = (given & 0x04000000u) >> 26;
10925 unsigned int I1 = (given & 0x00002000u) >> 13;
10926 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 10927 bfd_vma offset = 0;
c19d1205
ZW		 10928
10929 offset |= !S << 24;
10930 offset |= !(I1 ^ S) << 23;
10931 offset |= !(I2 ^ S) << 22;
10932 offset |= (given & 0x03ff0000u) >> 4;
10933 offset |= (given & 0x000007ffu) << 1;
10934 offset -= (1 << 24);
36b0c57d 10935 offset += pc + 4;
c19d1205 10936
36b0c57d
PB		 10937 /* BLX target addresses are always word aligned. */
10938 if ((given & 0x00001000u) == 0)
10939 offset &= ~2u;
10940
10941 info->print_address_func (offset, info);
c19d1205
ZW		 10942 }
10943 break;
10944
10945 case 's':
10946 {
10947 unsigned int shift = 0;
fe56b6ce 10948
c19d1205
ZW		 10949 shift |= (given & 0x000000c0u) >> 6;
10950 shift |= (given & 0x00007000u) >> 10;
c1e26897 10951 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 10952 func (stream, ", asr #%u", shift);
10953 else if (shift)
10954 func (stream, ", lsl #%u", shift);
10955 /* else print nothing - lsl #0 */
10956 }
10957 break;
10958
10959 case 'R':
10960 {
10961 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 10962
c19d1205
ZW		 10963 if (rot)
10964 func (stream, ", ror #%u", rot * 8);
10965 }
10966 break;
10967
62b3e311 10968 case 'U':
43e65147 10969 if ((given & 0xf0) == 0x60)
62b3e311 10970 {
52e7f43d
RE		 10971 switch (given & 0xf)
10972 {
10973 case 0xf: func (stream, "sy"); break;
10974 default:
10975 func (stream, "#%d", (int) given & 0xf);
10976 break;
10977 }
62b3e311 10978 }
43e65147 10979 else
52e7f43d 10980 {
e797f7e0
MGD		 10981 const char * opt = data_barrier_option (given & 0xf);
10982 if (opt != NULL)
10983 func (stream, "%s", opt);
10984 else
10985 func (stream, "#%d", (int) given & 0xf);
52e7f43d 10986 }
62b3e311
PB		 10987 break;
10988
10989 case 'C':
10990 if ((given & 0xff) == 0)
10991 {
10992 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10993 if (given & 0x800)
10994 func (stream, "f");
10995 if (given & 0x400)
10996 func (stream, "s");
10997 if (given & 0x200)
10998 func (stream, "x");
10999 if (given & 0x100)
11000 func (stream, "c");
11001 }
90ec0d68
MGD		 11002 else if ((given & 0x20) == 0x20)
11003 {
11004 char const* name;
11005 unsigned sysm = (given & 0xf00) >> 8;
11006
11007 sysm |= (given & 0x30);
11008 sysm |= (given & 0x00100000) >> 14;
11009 name = banked_regname (sysm);
43e65147 11010
90ec0d68
MGD		 11011 if (name != NULL)
11012 func (stream, "%s", name);
11013 else
d908c8af 11014 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11015 }
62b3e311
PB		 11016 else
11017 {
d908c8af 11018 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11019 }
11020 break;
11021
11022 case 'D':
90ec0d68
MGD		 11023 if (((given & 0xff) == 0)
11024 || ((given & 0x20) == 0x20))
11025 {
11026 char const* name;
11027 unsigned sm = (given & 0xf0000) >> 16;
11028
11029 sm |= (given & 0x30);
11030 sm |= (given & 0x00100000) >> 14;
11031 name = banked_regname (sm);
11032
11033 if (name != NULL)
11034 func (stream, "%s", name);
11035 else
d908c8af 11036 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11037 }
62b3e311 11038 else
d908c8af 11039 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11040 break;
11041
c19d1205
ZW		 11042 case '0': case '1': case '2': case '3': case '4':
11043 case '5': case '6': case '7': case '8': case '9':
11044 {
16980d0b
JB		 11045 int width;
11046 unsigned long val;
c19d1205 11047
16980d0b 11048 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11049
c19d1205
ZW		 11050 switch (*c)
11051 {
d052b9b7
AV		 11052 case 's':
11053 if (val <= 3)
11054 func (stream, "%s", mve_vec_sizename[val]);
11055 else
11056 func (stream, "<undef size>");
11057 break;
11058
05413229
NC		 11059 case 'd':
11060 func (stream, "%lu", val);
11061 value_in_comment = val;
11062 break;
ff4a8d2b 11063
f0fba320
RL		 11064 case 'D':
11065 func (stream, "%lu", val + 1);
11066 value_in_comment = val + 1;
11067 break;
11068
05413229
NC		 11069 case 'W':
11070 func (stream, "%lu", val * 4);
11071 value_in_comment = val * 4;
11072 break;
ff4a8d2b 11073
f1c7f421
AV		 11074 case 'S':
11075 if (val == 13)
11076 is_unpredictable = TRUE;
11077 /* Fall through. */
ff4a8d2b
NC		 11078 case 'R':
11079 if (val == 15)
11080 is_unpredictable = TRUE;
11081 /* Fall through. */
11082 case 'r':
11083 func (stream, "%s", arm_regnames[val]);
11084 break;
c19d1205
ZW		 11085
11086 case 'c':
c22aaad1 11087 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11088 break;
11089
11090 case '\'':
c19d1205 11091 c++;
16980d0b
JB		 11092 if (val == ((1ul << width) - 1))
11093 func (stream, "%c", *c);
c19d1205 11094 break;
43e65147 11095
c19d1205 11096 case '`':
c19d1205 11097 c++;
16980d0b
JB		 11098 if (val == 0)
11099 func (stream, "%c", *c);
c19d1205
ZW		 11100 break;
11101
11102 case '?':
fe56b6ce 11103 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11104 c += 1 << width;
c19d1205 11105 break;
43e65147 11106
0bb027fd
RR		 11107 case 'x':
11108 func (stream, "0x%lx", val & 0xffffffffUL);
11109 break;
c19d1205
ZW		 11110
11111 default:
11112 abort ();
11113 }
11114 }
11115 break;
11116
32a94698
NC		 11117 case 'L':
11118 /* PR binutils/12534
11119 If we have a PC relative offset in an LDRD or STRD
11120 instructions then display the decoded address. */
11121 if (((given >> 16) & 0xf) == 0xf)
11122 {
11123 bfd_vma offset = (given & 0xff) * 4;
11124
11125 if ((given & (1 << 23)) == 0)
11126 offset = - offset;
11127 func (stream, "\t; ");
11128 info->print_address_func ((pc & ~3) + 4 + offset, info);
11129 }
11130 break;
11131
c19d1205
ZW		 11132 default:
11133 abort ();
11134 }
11135 }
05413229
NC		 11136
11137 if (value_in_comment > 32 || value_in_comment < -16)
11138 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11139
11140 if (is_unpredictable)
11141 func (stream, UNPREDICTABLE_INSTRUCTION);
11142
4a5329c6 11143 return;
c19d1205 11144 }
252b5132 11145
58efb6c0 11146 /* No match. */
0b347048
TC		 11147 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11148 return;
252b5132
RH		 11149}
11150
e821645d
DJ		 11151/* Print data bytes on INFO->STREAM. */
11152
11153static void
fe56b6ce
NC		 11154print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11155 struct disassemble_info *info,
e821645d
DJ		 11156 long given)
11157{
11158 switch (info->bytes_per_chunk)
11159 {
11160 case 1:
11161 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11162 break;
11163 case 2:
11164 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11165 break;
11166 case 4:
11167 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11168 break;
11169 default:
11170 abort ();
11171 }
11172}
11173
22a398e1 11174/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11175 being displayed in symbol relative addresses.
11176
11177 Also disallow private symbol, with __tagsym$$ prefix,
11178 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11179
11180bfd_boolean
11181arm_symbol_is_valid (asymbol * sym,
11182 struct disassemble_info * info ATTRIBUTE_UNUSED)
11183{
11184 const char * name;
43e65147 11185
22a398e1
NC		 11186 if (sym == NULL)
11187 return FALSE;
11188
11189 name = bfd_asymbol_name (sym);
11190
d8282f0e 11191 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11192}
11193
65b48a81 11194/* Parse the string of disassembler options. */
baf0cc5e 11195
65b48a81 11196static void
f995bbe8 11197parse_arm_disassembler_options (const char *options)
dd92f639 11198{
f995bbe8 11199 const char *opt;
b34976b6 11200
65b48a81 11201 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11202 {
65b48a81
PB		 11203 if (CONST_STRNEQ (opt, "reg-names-"))
11204 {
11205 unsigned int i;
11206 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11207 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11208 {
11209 regname_selected = i;
11210 break;
11211 }
b34976b6 11212
65b48a81 11213 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11214 /* xgettext: c-format */
11215 opcodes_error_handler (_("unrecognised register name set: %s"),
11216 opt);
65b48a81
PB		 11217 }
11218 else if (CONST_STRNEQ (opt, "force-thumb"))
11219 force_thumb = 1;
11220 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11221 force_thumb = 0;
11222 else
a6743a54
AM		 11223 /* xgettext: c-format */
11224 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11225 }
b34976b6 11226
dd92f639
NC		 11227 return;
11228}
11229
5bc5ae88
RL		 11230static bfd_boolean
11231mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11232 enum map_type *map_symbol);
11233
c22aaad1
PB		 11234/* Search back through the insn stream to determine if this instruction is
11235 conditionally executed. */
fe56b6ce 11236
c22aaad1 11237static void
fe56b6ce
NC		 11238find_ifthen_state (bfd_vma pc,
11239 struct disassemble_info *info,
c22aaad1
PB		 11240 bfd_boolean little)
11241{
11242 unsigned char b[2];
11243 unsigned int insn;
11244 int status;
11245 /* COUNT is twice the number of instructions seen. It will be odd if we
11246 just crossed an instruction boundary. */
11247 int count;
11248 int it_count;
11249 unsigned int seen_it;
11250 bfd_vma addr;
11251
11252 ifthen_address = pc;
11253 ifthen_state = 0;
11254
11255 addr = pc;
11256 count = 1;
11257 it_count = 0;
11258 seen_it = 0;
11259 /* Scan backwards looking for IT instructions, keeping track of where
11260 instruction boundaries are. We don't know if something is actually an
11261 IT instruction until we find a definite instruction boundary. */
11262 for (;;)
11263 {
fe56b6ce 11264 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11265 {
11266 /* A symbol must be on an instruction boundary, and will not
11267 be within an IT block. */
11268 if (seen_it && (count & 1))
11269 break;
11270
11271 return;
11272 }
11273 addr -= 2;
fe56b6ce 11274 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11275 if (status)
11276 return;
11277
11278 if (little)
11279 insn = (b[0]) | (b[1] << 8);
11280 else
11281 insn = (b[1]) | (b[0] << 8);
11282 if (seen_it)
11283 {
11284 if ((insn & 0xf800) < 0xe800)
11285 {
11286 /* Addr + 2 is an instruction boundary. See if this matches
11287 the expected boundary based on the position of the last
11288 IT candidate. */
11289 if (count & 1)
11290 break;
11291 seen_it = 0;
11292 }
11293 }
11294 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11295 {
5bc5ae88
RL		 11296 enum map_type type = MAP_ARM;
11297 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11298
11299 if (!found || (found && type == MAP_THUMB))
11300 {
11301 /* This could be an IT instruction. */
11302 seen_it = insn;
11303 it_count = count >> 1;
11304 }
c22aaad1
PB		 11305 }
11306 if ((insn & 0xf800) >= 0xe800)
11307 count++;
11308 else
11309 count = (count + 2) | 1;
11310 /* IT blocks contain at most 4 instructions. */
11311 if (count >= 8 && !seen_it)
11312 return;
11313 }
11314 /* We found an IT instruction. */
11315 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11316 if ((ifthen_state & 0xf) == 0)
11317 ifthen_state = 0;
11318}
11319
b0e28b39
DJ		 11320/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11321 mapping symbol. */
11322
11323static int
11324is_mapping_symbol (struct disassemble_info *info, int n,
11325 enum map_type *map_type)
11326{
11327 const char *name;
11328
11329 name = bfd_asymbol_name (info->symtab[n]);
11330 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11331 && (name[2] == 0 || name[2] == '.'))
11332 {
11333 *map_type = ((name[1] == 'a') ? MAP_ARM
11334 : (name[1] == 't') ? MAP_THUMB
11335 : MAP_DATA);
11336 return TRUE;
11337 }
11338
11339 return FALSE;
11340}
11341
11342/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11343 Returns nonzero if *MAP_TYPE was set. */
11344
11345static int
11346get_map_sym_type (struct disassemble_info *info,
11347 int n,
11348 enum map_type *map_type)
11349{
11350 /* If the symbol is in a different section, ignore it. */
11351 if (info->section != NULL && info->section != info->symtab[n]->section)
11352 return FALSE;
11353
11354 return is_mapping_symbol (info, n, map_type);
11355}
11356
11357/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11358 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11359
11360static int
fe56b6ce
NC		 11361get_sym_code_type (struct disassemble_info *info,
11362 int n,
e821645d 11363 enum map_type *map_type)
2087ad84
PB		 11364{
11365 elf_symbol_type *es;
11366 unsigned int type;
b0e28b39
DJ		 11367
11368 /* If the symbol is in a different section, ignore it. */
11369 if (info->section != NULL && info->section != info->symtab[n]->section)
11370 return FALSE;
2087ad84 11371
e821645d 11372 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11373 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11374
11375 /* If the symbol has function type then use that. */
34e77a92 11376 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11377 {
39d911fc
TP		 11378 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11379 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11380 *map_type = MAP_THUMB;
11381 else
11382 *map_type = MAP_ARM;
2087ad84
PB		 11383 return TRUE;
11384 }
11385
2087ad84
PB		 11386 return FALSE;
11387}
11388
5bc5ae88
RL		 11389/* Search the mapping symbol state for instruction at pc. This is only
11390 applicable for elf target.
11391
11392 There is an assumption Here, info->private_data contains the correct AND
11393 up-to-date information about current scan process. The information will be
11394 used to speed this search process.
11395
11396 Return TRUE if the mapping state can be determined, and map_symbol
11397 will be updated accordingly. Otherwise, return FALSE. */
11398
11399static bfd_boolean
11400mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11401 enum map_type *map_symbol)
11402{
796d6298
TC		 11403 bfd_vma addr, section_vma = 0;
11404 int n, last_sym = -1;
5bc5ae88 11405 bfd_boolean found = FALSE;
796d6298
TC		 11406 bfd_boolean can_use_search_opt_p = FALSE;
11407
11408 /* Default to DATA. A text section is required by the ABI to contain an
11409 INSN mapping symbol at the start. A data section has no such
11410 requirement, hence if no mapping symbol is found the section must
11411 contain only data. This however isn't very useful if the user has
11412 fully stripped the binaries. If this is the case use the section
11413 attributes to determine the default. If we have no section default to
11414 INSN as well, as we may be disassembling some raw bytes on a baremetal
11415 HEX file or similar. */
11416 enum map_type type = MAP_DATA;
11417 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11418 type = MAP_ARM;
5bc5ae88
RL		 11419 struct arm_private_data *private_data;
11420
796d6298 11421 if (info->private_data == NULL
5bc5ae88
RL		 11422 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11423 return FALSE;
11424
11425 private_data = info->private_data;
5bc5ae88 11426
796d6298
TC		 11427 /* First, look for mapping symbols. */
11428 if (info->symtab_size != 0)
11429 {
11430 if (pc <= private_data->last_mapping_addr)
11431 private_data->last_mapping_sym = -1;
11432
11433 /* Start scanning at the start of the function, or wherever
11434 we finished last time. */
11435 n = info->symtab_pos + 1;
11436
11437 /* If the last stop offset is different from the current one it means we
11438 are disassembling a different glob of bytes. As such the optimization
11439 would not be safe and we should start over. */
11440 can_use_search_opt_p
11441 = private_data->last_mapping_sym >= 0
11442 && info->stop_offset == private_data->last_stop_offset;
11443
11444 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11445 n = private_data->last_mapping_sym;
11446
11447 /* Look down while we haven't passed the location being disassembled.
11448 The reason for this is that there's no defined order between a symbol
11449 and an mapping symbol that may be at the same address. We may have to
11450 look at least one position ahead. */
11451 for (; n < info->symtab_size; n++)
11452 {
11453 addr = bfd_asymbol_value (info->symtab[n]);
11454 if (addr > pc)
11455 break;
11456 if (get_map_sym_type (info, n, &type))
11457 {
11458 last_sym = n;
11459 found = TRUE;
11460 }
11461 }
5bc5ae88 11462
796d6298
TC		 11463 if (!found)
11464 {
11465 n = info->symtab_pos;
11466 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11467 n = private_data->last_mapping_sym;
11468
11469 /* No mapping symbol found at this address. Look backwards
11470 for a preceeding one, but don't go pass the section start
11471 otherwise a data section with no mapping symbol can pick up
11472 a text mapping symbol of a preceeding section. The documentation
11473 says section can be NULL, in which case we will seek up all the
11474 way to the top. */
11475 if (info->section)
11476 section_vma = info->section->vma;
11477
11478 for (; n >= 0; n--)
11479 {
11480 addr = bfd_asymbol_value (info->symtab[n]);
11481 if (addr < section_vma)
11482 break;
11483
11484 if (get_map_sym_type (info, n, &type))
11485 {
11486 last_sym = n;
11487 found = TRUE;
11488 break;
11489 }
11490 }
11491 }
11492 }
11493
11494 /* If no mapping symbol was found, try looking up without a mapping
11495 symbol. This is done by walking up from the current PC to the nearest
11496 symbol. We don't actually have to loop here since symtab_pos will
11497 contain the nearest symbol already. */
11498 if (!found)
5bc5ae88 11499 {
796d6298
TC		 11500 n = info->symtab_pos;
11501 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11502 {
796d6298
TC		 11503 last_sym = n;
11504 found = TRUE;
5bc5ae88
RL		 11505 }
11506 }
11507
796d6298
TC		 11508 private_data->last_mapping_sym = last_sym;
11509 private_data->last_type = type;
11510 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11511
11512 *map_symbol = type;
11513 return found;
11514}
11515
0313a2b8
NC		 11516/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11517 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11518 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11519
11520 FIXME: This could more efficiently implemented as a constant array,
11521 although it would also be less robust. */
11522
11523static void
11524select_arm_features (unsigned long mach,
11525 arm_feature_set * features)
11526{
c0c468d5
TP		 11527 arm_feature_set arch_fset;
11528 const arm_feature_set fpu_any = FPU_ANY;
11529
1af1dd51
MW		 11530#undef ARM_SET_FEATURES
11531#define ARM_SET_FEATURES(FSET) \
11532 { \
11533 const arm_feature_set fset = FSET; \
c0c468d5 11534 arch_fset = fset; \
1af1dd51 11535 }
823d2571 11536
c0c468d5
TP		 11537 /* When several architecture versions share the same bfd_mach_arm_XXX value
11538 the most featureful is chosen. */
0313a2b8
NC		 11539 switch (mach)
11540 {
c0c468d5
TP		 11541 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11542 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11543 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11544 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11545 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11546 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11547 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11548 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11549 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11550 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11551 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11552 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11553 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11554 break;
c0c468d5
TP		 11555 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11556 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11557 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11558 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11559 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11560 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11561 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11562 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11563 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11564 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11565 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11566 case bfd_mach_arm_8:
11567 {
0632eeea
SD		 11568 /* Add bits for extensions that Armv8.5-A recognizes. */
11569 arm_feature_set armv8_5_ext_fset
11570 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11571 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11572 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 11573 break;
11574 }
11575 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11576 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11577 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 11578 case bfd_mach_arm_8_1M_MAIN:
11579 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11580 force_thumb = 1;
11581 break;
c0c468d5
TP		 11582 /* If the machine type is unknown allow all architecture types and all
11583 extensions. */
11584 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 11585 default:
11586 abort ();
11587 }
1af1dd51 11588#undef ARM_SET_FEATURES
c0c468d5
TP		 11589
11590 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11591 and thus on bfd_mach_arm_XXX value. Therefore for a given
11592 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11593 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 11594}
11595
11596
58efb6c0
NC		 11597/* NOTE: There are no checks in these routines that
11598 the relevant number of data bytes exist. */
baf0cc5e 11599
58efb6c0 11600static int
4a5329c6 11601print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 11602{
c19d1205
ZW		 11603 unsigned char b[4];
11604 long given;
11605 int status;
e821645d 11606 int is_thumb = FALSE;
b0e28b39 11607 int is_data = FALSE;
bd2e2557 11608 int little_code;
e821645d 11609 unsigned int size = 4;
4a5329c6 11610 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 11611 bfd_boolean found = FALSE;
b0e28b39 11612 struct arm_private_data *private_data;
58efb6c0 11613
dd92f639
NC		 11614 if (info->disassembler_options)
11615 {
65b48a81 11616 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 11617
58efb6c0 11618 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 11619 info->disassembler_options = NULL;
11620 }
b34976b6 11621
0313a2b8
NC		 11622 /* PR 10288: Control which instructions will be disassembled. */
11623 if (info->private_data == NULL)
11624 {
b0e28b39 11625 static struct arm_private_data private;
0313a2b8
NC		 11626
11627 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11628 /* If the user did not use the -m command line switch then default to
11629 disassembling all types of ARM instruction.
43e65147 11630
0313a2b8
NC		 11631 The info->mach value has to be ignored as this will be based on
11632 the default archictecture for the target and/or hints in the notes
11633 section, but it will never be greater than the current largest arm
11634 machine value (iWMMXt2), which is only equivalent to the V5TE
11635 architecture. ARM architectures have advanced beyond the machine
11636 value encoding, and these newer architectures would be ignored if
11637 the machine value was used.
11638
11639 Ie the -m switch is used to restrict which instructions will be
11640 disassembled. If it is necessary to use the -m switch to tell
11641 objdump that an ARM binary is being disassembled, eg because the
11642 input is a raw binary file, but it is also desired to disassemble
11643 all ARM instructions then use "-marm". This will select the
11644 "unknown" arm architecture which is compatible with any ARM
11645 instruction. */
11646 info->mach = bfd_mach_arm_unknown;
11647
11648 /* Compute the architecture bitmask from the machine number.
11649 Note: This assumes that the machine number will not change
11650 during disassembly.... */
b0e28b39 11651 select_arm_features (info->mach, & private.features);
0313a2b8 11652
1fbaefec
PB		 11653 private.last_mapping_sym = -1;
11654 private.last_mapping_addr = 0;
796d6298 11655 private.last_stop_offset = 0;
b0e28b39
DJ		 11656
11657 info->private_data = & private;
0313a2b8 11658 }
b0e28b39
DJ		 11659
11660 private_data = info->private_data;
11661
bd2e2557
SS		 11662 /* Decide if our code is going to be little-endian, despite what the
11663 function argument might say. */
11664 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11665
b0e28b39
DJ		 11666 /* For ELF, consult the symbol table to determine what kind of code
11667 or data we have. */
8977d4b2 11668 if (info->symtab_size != 0
e821645d
DJ		 11669 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11670 {
11671 bfd_vma addr;
796d6298 11672 int n;
e821645d 11673 int last_sym = -1;
b0e28b39 11674 enum map_type type = MAP_ARM;
e821645d 11675
796d6298
TC		 11676 found = mapping_symbol_for_insn (pc, info, &type);
11677 last_sym = private_data->last_mapping_sym;
e821645d 11678
1fbaefec
PB		 11679 is_thumb = (private_data->last_type == MAP_THUMB);
11680 is_data = (private_data->last_type == MAP_DATA);
b34976b6 11681
e821645d
DJ		 11682 /* Look a little bit ahead to see if we should print out
11683 two or four bytes of data. If there's a symbol,
11684 mapping or otherwise, after two bytes then don't
11685 print more. */
11686 if (is_data)
11687 {
11688 size = 4 - (pc & 3);
11689 for (n = last_sym + 1; n < info->symtab_size; n++)
11690 {
11691 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 11692 if (addr > pc
11693 && (info->section == NULL
11694 || info->section == info->symtab[n]->section))
e821645d
DJ		 11695 {
11696 if (addr - pc < size)
11697 size = addr - pc;
11698 break;
11699 }
11700 }
11701 /* If the next symbol is after three bytes, we need to
11702 print only part of the data, so that we can use either
11703 .byte or .short. */
11704 if (size == 3)
11705 size = (pc & 1) ? 1 : 2;
11706 }
11707 }
11708
11709 if (info->symbols != NULL)
252b5132 11710 {
5876e06d
NC		 11711 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11712 {
2f0ca46a 11713 coff_symbol_type * cs;
b34976b6 11714
5876e06d
NC		 11715 cs = coffsymbol (*info->symbols);
11716 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11717 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11718 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11719 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11720 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11721 }
e821645d
DJ		 11722 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11723 && !found)
5876e06d 11724 {
2087ad84
PB		 11725 /* If no mapping symbol has been found then fall back to the type
11726 of the function symbol. */
e821645d
DJ		 11727 elf_symbol_type * es;
11728 unsigned int type;
2087ad84 11729
e821645d
DJ		 11730 es = *(elf_symbol_type **)(info->symbols);
11731 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 11732
39d911fc
TP		 11733 is_thumb =
11734 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11735 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 11736 }
e49d43ff
TG		 11737 else if (bfd_asymbol_flavour (*info->symbols)
11738 == bfd_target_mach_o_flavour)
11739 {
11740 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11741
11742 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11743 }
5876e06d 11744 }
b34976b6 11745
e821645d
DJ		 11746 if (force_thumb)
11747 is_thumb = TRUE;
11748
b8f9ee44
CL		 11749 if (is_data)
11750 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11751 else
11752 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11753
c19d1205 11754 info->bytes_per_line = 4;
252b5132 11755
1316c8b3
NC		 11756 /* PR 10263: Disassemble data if requested to do so by the user. */
11757 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 11758 {
11759 int i;
11760
1316c8b3 11761 /* Size was already set above. */
e821645d
DJ		 11762 info->bytes_per_chunk = size;
11763 printer = print_insn_data;
11764
fe56b6ce 11765 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 11766 given = 0;
11767 if (little)
11768 for (i = size - 1; i >= 0; i--)
11769 given = b[i] | (given << 8);
11770 else
11771 for (i = 0; i < (int) size; i++)
11772 given = b[i] | (given << 8);
11773 }
11774 else if (!is_thumb)
252b5132 11775 {
c19d1205
ZW		 11776 /* In ARM mode endianness is a straightforward issue: the instruction
11777 is four bytes long and is either ordered 0123 or 3210. */
11778 printer = print_insn_arm;
11779 info->bytes_per_chunk = 4;
4a5329c6 11780 size = 4;
c19d1205 11781
0313a2b8 11782 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 11783 if (little_code)
c19d1205
ZW		 11784 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11785 else
11786 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 11787 }
58efb6c0 11788 else
252b5132 11789 {
c19d1205
ZW		 11790 /* In Thumb mode we have the additional wrinkle of two
11791 instruction lengths. Fortunately, the bits that determine
11792 the length of the current instruction are always to be found
11793 in the first two bytes. */
4a5329c6 11794 printer = print_insn_thumb16;
c19d1205 11795 info->bytes_per_chunk = 2;
4a5329c6
ZW		 11796 size = 2;
11797
fe56b6ce 11798 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 11799 if (little_code)
9a2ff3f5
AM		 11800 given = (b[0]) | (b[1] << 8);
11801 else
11802 given = (b[1]) | (b[0] << 8);
11803
c19d1205 11804 if (!status)
252b5132 11805 {
c19d1205
ZW		 11806 /* These bit patterns signal a four-byte Thumb
11807 instruction. */
11808 if ((given & 0xF800) == 0xF800
11809 || (given & 0xF800) == 0xF000
11810 || (given & 0xF800) == 0xE800)
252b5132 11811 {
0313a2b8 11812 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 11813 if (little_code)
c19d1205 11814 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 11815 else
c19d1205
ZW		 11816 given = (b[1]) | (b[0] << 8) | (given << 16);
11817
11818 printer = print_insn_thumb32;
4a5329c6 11819 size = 4;
252b5132 11820 }
252b5132 11821 }
c22aaad1
PB		 11822
11823 if (ifthen_address != pc)
0313a2b8 11824 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 11825
11826 if (ifthen_state)
11827 {
11828 if ((ifthen_state & 0xf) == 0x8)
11829 ifthen_next_state = 0;
11830 else
11831 ifthen_next_state = (ifthen_state & 0xe0)
11832 | ((ifthen_state & 0xf) << 1);
11833 }
252b5132 11834 }
b34976b6 11835
c19d1205
ZW		 11836 if (status)
11837 {
11838 info->memory_error_func (status, pc, info);
11839 return -1;
11840 }
6a56ec7e
NC		 11841 if (info->flags & INSN_HAS_RELOC)
11842 /* If the instruction has a reloc associated with it, then
11843 the offset field in the instruction will actually be the
11844 addend for the reloc. (We are using REL type relocs).
11845 In such cases, we can ignore the pc when computing
11846 addresses, since the addend is not currently pc-relative. */
11847 pc = 0;
b34976b6 11848
4a5329c6 11849 printer (pc, info, given);
c22aaad1
PB		 11850
11851 if (is_thumb)
11852 {
11853 ifthen_state = ifthen_next_state;
11854 ifthen_address += size;
11855 }
4a5329c6 11856 return size;
252b5132
RH		 11857}
11858
11859int
4a5329c6 11860print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 11861{
bd2e2557
SS		 11862 /* Detect BE8-ness and record it in the disassembler info. */
11863 if (info->flavour == bfd_target_elf_flavour
11864 && info->section != NULL
11865 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11866 info->endian_code = BFD_ENDIAN_LITTLE;
11867
b34976b6 11868 return print_insn (pc, info, FALSE);
58efb6c0 11869}
01c7f630 11870
58efb6c0 11871int
4a5329c6 11872print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11873{
b34976b6 11874 return print_insn (pc, info, TRUE);
58efb6c0 11875}
252b5132 11876
471b9d15 11877const disasm_options_and_args_t *
65b48a81
PB		 11878disassembler_options_arm (void)
11879{
471b9d15 11880 static disasm_options_and_args_t *opts_and_args;
65b48a81 11881
471b9d15 11882 if (opts_and_args == NULL)
65b48a81 11883 {
471b9d15 11884 disasm_options_t *opts;
65b48a81 11885 unsigned int i;
471b9d15
MR		 11886
11887 opts_and_args = XNEW (disasm_options_and_args_t);
11888 opts_and_args->args = NULL;
11889
11890 opts = &opts_and_args->options;
65b48a81
PB		 11891 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11892 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11893 opts->arg = NULL;
65b48a81
PB		 11894 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11895 {
11896 opts->name[i] = regnames[i].name;
11897 if (regnames[i].description != NULL)
11898 opts->description[i] = _(regnames[i].description);
11899 else
11900 opts->description[i] = NULL;
11901 }
11902 /* The array we return must be NULL terminated. */
11903 opts->name[i] = NULL;
11904 opts->description[i] = NULL;
11905 }
11906
471b9d15 11907 return opts_and_args;
65b48a81
PB		 11908}
11909
58efb6c0 11910void
4a5329c6 11911print_arm_disassembler_options (FILE *stream)
58efb6c0 11912{
65b48a81 11913 unsigned int i, max_len = 0;
58efb6c0
NC		 11914 fprintf (stream, _("\n\
11915The following ARM specific disassembler options are supported for use with\n\
11916the -M switch:\n"));
b34976b6 11917
65b48a81
PB		 11918 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11919 {
11920 unsigned int len = strlen (regnames[i].name);
11921 if (max_len < len)
11922 max_len = len;
11923 }
58efb6c0 11924
65b48a81
PB		 11925 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11926 fprintf (stream, " %s%*c %s\n",
11927 regnames[i].name,
11928 (int)(max_len - strlen (regnames[i].name)), ' ',
11929 _(regnames[i].description));
252b5132 11930}
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