]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/arm-dis.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
New Romanian translation for ld
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
d87bef3a 2 Copyright (C) 1994-2023 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
1fbaefec
PB		 42/* Cached mapping symbol state. */
43enum map_type
44{
45 MAP_ARM,
46 MAP_THUMB,
47 MAP_DATA
48};
49
b0e28b39
DJ		 50struct arm_private_data
51{
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features;
54
1fbaefec
PB		 55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type;
57
58 /* Tracking symbol table information */
59 int last_mapping_sym;
796d6298
TC		 60
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset;
1fbaefec 63 bfd_vma last_mapping_addr;
b0e28b39
DJ		 64};
65
73cd51e5
AV		 66enum mve_instructions
67{
143275ea
AV		 68 MVE_VPST,
69 MVE_VPT_FP_T1,
70 MVE_VPT_FP_T2,
71 MVE_VPT_VEC_T1,
72 MVE_VPT_VEC_T2,
73 MVE_VPT_VEC_T3,
74 MVE_VPT_VEC_T4,
75 MVE_VPT_VEC_T5,
76 MVE_VPT_VEC_T6,
77 MVE_VCMP_FP_T1,
78 MVE_VCMP_FP_T2,
79 MVE_VCMP_VEC_T1,
80 MVE_VCMP_VEC_T2,
81 MVE_VCMP_VEC_T3,
82 MVE_VCMP_VEC_T4,
83 MVE_VCMP_VEC_T5,
84 MVE_VCMP_VEC_T6,
9743db03
AV		 85 MVE_VDUP,
86 MVE_VEOR,
87 MVE_VFMAS_FP_SCALAR,
88 MVE_VFMA_FP_SCALAR,
89 MVE_VFMA_FP,
90 MVE_VFMS_FP,
91 MVE_VHADD_T1,
92 MVE_VHADD_T2,
93 MVE_VHSUB_T1,
94 MVE_VHSUB_T2,
95 MVE_VRHADD,
04d54ace
AV		 96 MVE_VLD2,
97 MVE_VLD4,
98 MVE_VST2,
99 MVE_VST4,
aef6d006
AV		 100 MVE_VLDRB_T1,
101 MVE_VLDRH_T2,
102 MVE_VLDRB_T5,
103 MVE_VLDRH_T6,
104 MVE_VLDRW_T7,
105 MVE_VSTRB_T1,
106 MVE_VSTRH_T2,
107 MVE_VSTRB_T5,
108 MVE_VSTRH_T6,
109 MVE_VSTRW_T7,
ef1576a1
AV		 110 MVE_VLDRB_GATHER_T1,
111 MVE_VLDRH_GATHER_T2,
112 MVE_VLDRW_GATHER_T3,
113 MVE_VLDRD_GATHER_T4,
114 MVE_VLDRW_GATHER_T5,
115 MVE_VLDRD_GATHER_T6,
116 MVE_VSTRB_SCATTER_T1,
117 MVE_VSTRH_SCATTER_T2,
118 MVE_VSTRW_SCATTER_T3,
119 MVE_VSTRD_SCATTER_T4,
120 MVE_VSTRW_SCATTER_T5,
121 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 122 MVE_VCVT_FP_FIX_VEC,
123 MVE_VCVT_BETWEEN_FP_INT,
124 MVE_VCVT_FP_HALF_FP,
125 MVE_VCVT_FROM_FP_TO_INT,
126 MVE_VRINT_FP,
c507f10b
AV		 127 MVE_VMOV_HFP_TO_GP,
128 MVE_VMOV_GP_TO_VEC_LANE,
129 MVE_VMOV_IMM_TO_VEC,
130 MVE_VMOV_VEC_TO_VEC,
131 MVE_VMOV2_VEC_LANE_TO_GP,
132 MVE_VMOV2_GP_TO_VEC_LANE,
133 MVE_VMOV_VEC_LANE_TO_GP,
134 MVE_VMVN_IMM,
135 MVE_VMVN_REG,
136 MVE_VORR_IMM,
137 MVE_VORR_REG,
138 MVE_VORN,
139 MVE_VBIC_IMM,
140 MVE_VBIC_REG,
141 MVE_VMOVX,
14925797
AV		 142 MVE_VMOVL,
143 MVE_VMOVN,
144 MVE_VMULL_INT,
145 MVE_VMULL_POLY,
146 MVE_VQDMULL_T1,
147 MVE_VQDMULL_T2,
148 MVE_VQMOVN,
149 MVE_VQMOVUN,
d3b63143
AV		 150 MVE_VADDV,
151 MVE_VMLADAV_T1,
152 MVE_VMLADAV_T2,
153 MVE_VMLALDAV,
154 MVE_VMLAS,
155 MVE_VADDLV,
156 MVE_VMLSDAV_T1,
157 MVE_VMLSDAV_T2,
158 MVE_VMLSLDAV,
159 MVE_VRMLALDAVH,
160 MVE_VRMLSLDAVH,
161 MVE_VQDMLADH,
162 MVE_VQRDMLADH,
163 MVE_VQDMLAH,
164 MVE_VQRDMLAH,
165 MVE_VQDMLASH,
166 MVE_VQRDMLASH,
167 MVE_VQDMLSDH,
168 MVE_VQRDMLSDH,
169 MVE_VQDMULH_T1,
170 MVE_VQRDMULH_T2,
171 MVE_VQDMULH_T3,
172 MVE_VQRDMULH_T4,
1c8f2df8
AV		 173 MVE_VDDUP,
174 MVE_VDWDUP,
175 MVE_VIWDUP,
176 MVE_VIDUP,
897b9bbc
AV		 177 MVE_VCADD_FP,
178 MVE_VCADD_VEC,
179 MVE_VHCADD,
180 MVE_VCMLA_FP,
181 MVE_VCMUL_FP,
ed63aa17
AV		 182 MVE_VQRSHL_T1,
183 MVE_VQRSHL_T2,
184 MVE_VQRSHRN,
185 MVE_VQRSHRUN,
186 MVE_VQSHL_T1,
187 MVE_VQSHL_T2,
188 MVE_VQSHLU_T3,
189 MVE_VQSHL_T4,
190 MVE_VQSHRN,
191 MVE_VQSHRUN,
192 MVE_VRSHL_T1,
193 MVE_VRSHL_T2,
194 MVE_VRSHR,
195 MVE_VRSHRN,
196 MVE_VSHL_T1,
197 MVE_VSHL_T2,
198 MVE_VSHL_T3,
199 MVE_VSHLC,
200 MVE_VSHLL_T1,
201 MVE_VSHLL_T2,
202 MVE_VSHR,
203 MVE_VSHRN,
204 MVE_VSLI,
205 MVE_VSRI,
66dcaa5d
AV		 206 MVE_VADC,
207 MVE_VABAV,
208 MVE_VABD_FP,
209 MVE_VABD_VEC,
210 MVE_VABS_FP,
211 MVE_VABS_VEC,
212 MVE_VADD_FP_T1,
213 MVE_VADD_FP_T2,
214 MVE_VADD_VEC_T1,
215 MVE_VADD_VEC_T2,
216 MVE_VSBC,
217 MVE_VSUB_FP_T1,
218 MVE_VSUB_FP_T2,
219 MVE_VSUB_VEC_T1,
220 MVE_VSUB_VEC_T2,
e523f101
AV		 221 MVE_VAND,
222 MVE_VBRSR,
223 MVE_VCLS,
224 MVE_VCLZ,
225 MVE_VCTP,
56858bea
AV		 226 MVE_VMAX,
227 MVE_VMAXA,
228 MVE_VMAXNM_FP,
229 MVE_VMAXNMA_FP,
230 MVE_VMAXNMV_FP,
231 MVE_VMAXNMAV_FP,
232 MVE_VMAXV,
233 MVE_VMAXAV,
234 MVE_VMIN,
235 MVE_VMINA,
236 MVE_VMINNM_FP,
237 MVE_VMINNMA_FP,
238 MVE_VMINNMV_FP,
239 MVE_VMINNMAV_FP,
240 MVE_VMINV,
241 MVE_VMINAV,
242 MVE_VMLA,
f49bb598
AV		 243 MVE_VMUL_FP_T1,
244 MVE_VMUL_FP_T2,
245 MVE_VMUL_VEC_T1,
246 MVE_VMUL_VEC_T2,
247 MVE_VMULH,
248 MVE_VRMULH,
249 MVE_VNEG_FP,
250 MVE_VNEG_VEC,
14b456f2
AV		 251 MVE_VPNOT,
252 MVE_VPSEL,
253 MVE_VQABS,
254 MVE_VQADD_T1,
255 MVE_VQADD_T2,
256 MVE_VQSUB_T1,
257 MVE_VQSUB_T2,
258 MVE_VQNEG,
259 MVE_VREV16,
260 MVE_VREV32,
261 MVE_VREV64,
23d00a41
SD		 262 MVE_LSLL,
263 MVE_LSLLI,
264 MVE_LSRL,
265 MVE_ASRL,
266 MVE_ASRLI,
267 MVE_SQRSHRL,
268 MVE_SQRSHR,
269 MVE_UQRSHL,
270 MVE_UQRSHLL,
271 MVE_UQSHL,
272 MVE_UQSHLL,
273 MVE_URSHRL,
274 MVE_URSHR,
275 MVE_SRSHRL,
276 MVE_SRSHR,
277 MVE_SQSHLL,
278 MVE_SQSHL,
e39c1607
SD		 279 MVE_CINC,
280 MVE_CINV,
281 MVE_CNEG,
282 MVE_CSINC,
283 MVE_CSINV,
284 MVE_CSET,
285 MVE_CSETM,
286 MVE_CSNEG,
287 MVE_CSEL,
73cd51e5
AV		 288 MVE_NONE
289};
290
291enum mve_unpredictable
292{
293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
294 */
143275ea
AV		 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
296 fcB = 1 (vpt). */
297 UNPRED_R13, /* Unpredictable because r13 (sp) or
298 r15 (sp) used. */
9743db03 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 300 UNPRED_Q_GT_4, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
305 and WB bit = 1. */
ef1576a1
AV		 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
307 equal. */
308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
310 same. */
c507f10b
AV		 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
312 size = 1. */
313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
314 size = 2. */
73cd51e5
AV		 315 UNPRED_NONE /* No unpredictable behavior. */
316};
317
318enum mve_undefined
319{
ed63aa17 320 UNDEF_SIZE, /* undefined size. */
bf0b396d 321 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 322 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 323 UNDEF_SIZE_3, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
329 size == 0. */
330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
331 size == 1. */
332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
336 op1 == (0 or 1). */
337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
340 in {0xx1, x0x1}. */
d3b63143 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 342 UNDEF_NONE /* no undefined behavior. */
343};
344
6b5d3a4d
ZW		 345struct opcode32
346{
823d2571
TG		 347 arm_feature_set arch; /* Architecture defining this insn. */
348 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 350 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 351};
352
4934a27c
MM		 353struct cdeopcode32
354{
355 arm_feature_set arch; /* Architecture defining this insn. */
356 uint8_t coproc_shift; /* coproc is this far into op. */
357 uint16_t coproc_mask; /* Length of coproc field in op. */
358 unsigned long value; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask; /* Recognise insn if (op & mask) == value. */
360 const char * assembler; /* How to disassemble this insn. */
361};
362
73cd51e5
AV		 363/* MVE opcodes. */
364
365struct mopcode32
366{
367 arm_feature_set arch; /* Architecture defining this insn. */
368 enum mve_instructions mve_op; /* Specific mve instruction for faster
369 decoding. */
370 unsigned long value; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask; /* Recognise insn if (op & mask) == value. */
372 const char * assembler; /* How to disassemble this insn. */
373};
374
6b0dd094
AV		 375enum isa {
376 ANY,
377 T32,
378 ARM
379};
380
381
382/* Shared (between Arm and Thumb mode) opcode. */
383struct sopcode32
384{
385 enum isa isa; /* Execution mode instruction availability. */
386 arm_feature_set arch; /* Architecture defining this insn. */
387 unsigned long value; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask; /* Recognise insn if (op & mask) == value. */
389 const char * assembler; /* How to disassemble this insn. */
390};
391
6b5d3a4d
ZW		 392struct opcode16
393{
823d2571 394 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 396 const char *assembler; /* How to disassemble this insn. */
397};
b7693d02 398
8f06b2d8 399/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 400
2fbad815 401 %% %
4a5329c6 402
c22aaad1 403 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 404 %b print condition code allowing cp_num == 9
37b37b2d 405 %q print shifter argument
e2efe87d
MGD		 406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
4a5329c6 408 %A print address for ldc/stc/ldf/stf instruction
16980d0b 409 %B print vstm/vldm register list
efd6b359 410 %C print vscclrm register list
4a5329c6 411 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 412 %J print register for VLDR instruction
413 %K print address for VLDR instruction
4a5329c6
ZW		 414 %F print the COUNT field of a LFM/SFM instruction.
415 %P print floating point precision in arithmetic insn
416 %Q print floating point precision in ldf/stf insn
417 %R print floating point rounding mode
418
33399f07 419 %<bitfield>c print as a condition code (for vsel)
4a5329c6 420 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
422 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 423 %<bitfield>d print the bitfield in decimal
16980d0b 424 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 425 %<bitfield>x print the bitfield in hex
426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 427 %<bitfield>f print a floating point constant if >7 else a
428 floating point register
4a5329c6
ZW		 429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
430 %<bitfield>g print as an iWMMXt 64-bit register
431 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 432 %<bitfield>D print as a NEON D register
433 %<bitfield>Q print as a NEON Q register
c28eeff2 434 %<bitfield>V print as a NEON D or Q register
6f1c2142 435 %<bitfield>E print a quarter-float immediate value
4a5329c6 436
16980d0b 437 %y<code> print a single precision VFP reg.
2fbad815 438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 439 %z<code> print a double precision VFP reg
2fbad815 440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 441
16980d0b
JB		 442 %<bitfield>'c print specified char iff bitfield is all ones
443 %<bitfield>`c print specified char iff bitfield is all zeroes
444 %<bitfield>?ab... select from array of values in big endian order
43e65147 445
2fbad815 446 %L print as an iWMMXt N/M width field.
4a5329c6 447 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 448 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 449 versions.
450 %i print 5-bit immediate in bits 8,3..0
451 (print "32" when 0)
fe56b6ce 452 %r print register offset address for wldt/wstr instruction. */
2fbad815 453
21d799b5 454enum opcode_sentinel_enum
05413229
NC		 455{
456 SENTINEL_IWMMXT_START = 1,
457 SENTINEL_IWMMXT_END,
458 SENTINEL_GENERIC_START
459} opcode_sentinels;
460
8cb6e175
AB		 461#define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x"
462#define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x"
463#define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x"
464#define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>"
05413229 465
8f06b2d8 466/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 467
4934a27c
MM		 468/* print_insn_cde recognizes the following format control codes:
469
470 %% %
471
472 %a print 'a' iff bit 28 is 1
473 %p print bits 8-10 as coprocessor
474 %<bitfield>d print as decimal
475 %<bitfield>r print as an ARM register
476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
477 %<bitfield>T print as an ARM register + 1
478 %<bitfield>R as %r but r13 is UNPREDICTABLE
479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
480 %j print immediate taken from bits (16..21,7,0..5)
481 %k print immediate taken from bits (20..21,7,0..5).
482 %l print immediate taken from bits (20..22,7,4..5). */
483
484/* At the moment there is only one valid position for the coprocessor number,
485 and hence that's encoded in the macro below. */
486#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487 { ARCH, 8, 7, VALUE, MASK, ASM }
488static const struct cdeopcode32 cde_opcodes[] =
489{
490 /* Custom Datapath Extension instructions. */
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492 0xee000000, 0xefc00840,
6576bffe 493 "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495 0xee000040, 0xefc00840,
6576bffe 496 "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 497
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499 0xee400000, 0xefc00840,
6576bffe 500 "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502 0xee400040, 0xefc00840,
6576bffe 503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 504
505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506 0xee800000, 0xef800840,
6576bffe 507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c
MM		 508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509 0xee800040, 0xef800840,
6576bffe 510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c 511
5aae9ae9
MM		 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513 0xec200000, 0xeeb00840,
6576bffe 514 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
5aae9ae9
MM		 515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516 0xec200040, 0xeeb00840,
6576bffe 517 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
5aae9ae9
MM		 518
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520 0xec300000, 0xeeb00840,
6576bffe 521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
5aae9ae9
MM		 522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523 0xec300040, 0xeeb00840,
6576bffe 524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
5aae9ae9
MM		 525
526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527 0xec800000, 0xee800840,
6576bffe 528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
5aae9ae9
MM		 529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530 0xec800040, 0xee800840,
6576bffe 531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
5aae9ae9 532
4934a27c
MM		 533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535};
536
6b0dd094 537static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 538{
2fbad815 539 /* XScale instructions. */
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 541 0x0e200010, 0x0fff0ff0,
6576bffe 542 "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0x0e280010, 0x0fff0ff0,
6576bffe 545 "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 549 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
05413229 552
2fbad815 553 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 554 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 628 0x0e800120, 0x0f800ff0,
629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 643 0x0e8000a0, 0x0f800ff0,
644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 707 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 708 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 709
fe56b6ce 710 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 797
efd6b359
AV		 798 /* Armv8.1-M Mainline instructions. */
799 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
16a1fa25 804 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 805 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 807 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
fe56b6ce 810 /* Register load/store. */
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 843 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 847
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
16980d0b 856
fe56b6ce 857 /* Data transfer between ARM and NEON registers. */
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
8e79c3df 874 /* Half-precision conversion instructions. */
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 883
fe56b6ce 884 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 886 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
2da2eaf4 887 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 888 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
ba6cd17f 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 890 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 892 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 894 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 896 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 898 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 900 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 902 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
2da2eaf4 903 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 904 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
2da2eaf4 905 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 906 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
ba6cd17f 907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 908 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
ba6cd17f 909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 910 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 914 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
2da2eaf4 915 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
ba6cd17f 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
2da2eaf4 931 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
2da2eaf4 933 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
ba6cd17f 935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
ba6cd17f 937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 1043
1044 /* Cirrus coprocessor instructions. */
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1046 0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1048 0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1050 0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1052 0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1054 0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1056 0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1058 0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1060 0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1062 0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1064 0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1066 0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1068 0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1070 0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1072 0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1074 0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1076 0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1078 0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1080 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1082 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1084 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1086 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1088 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1090 0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1092 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1094 0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1096 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1098 0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1100 0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1102 0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1104 0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1106 0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1108 0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1110 0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1112 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1114 0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1116 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1118 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
6b0dd094 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1120 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
6b0dd094 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1122 0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1124 0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1126 0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1128 0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1130 0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1132 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1134 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1135 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1136 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1138 0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1140 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1141 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1142 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1143 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1144 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1145 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1146 0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
6b0dd094 1147 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1148 0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
6b0dd094 1149 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1150 0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
6b0dd094 1151 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1152 0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
6b0dd094 1153 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1154 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1155 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1156 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1157 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1158 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1160 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1161 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1162 0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1163 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1164 0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1165 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1166 0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1167 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1168 0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1169 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1170 0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1171 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1172 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1173 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1174 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1175 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1176 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1177 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1178 0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1179 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1180 0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1181 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1182 0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1183 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1184 0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1185 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1186 0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1187 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1188 0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1189 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1190 0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1191 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1192 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1193 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1194 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1195 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1196 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1197 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1198 0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1199 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1200 0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1201 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1202 0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1203 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1204 0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1205 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1206 0x0e000600, 0x0ff00f10,
6576bffe 1207 "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1209 0x0e100600, 0x0ff00f10,
6576bffe 1210 "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1211 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1212 0x0e200600, 0x0ff00f10,
6576bffe 1213 "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1214 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1215 0x0e300600, 0x0ff00f10,
6576bffe 1216 "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
2fbad815 1217
62f3b8c8 1218 /* VFP Fused multiply add instructions. */
6b0dd094 1219 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1220 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1221 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1222 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1223 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1224 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1225 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1226 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1227 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1228 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1229 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1230 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1231 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1232 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1233 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1234 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1235
33399f07 1236 /* FP v5. */
6b0dd094 1237 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1238 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1239 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1240 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1241 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1242 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1243 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1244 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1245 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1246 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1247 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1248 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1249 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1250 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1251 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1252 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1253 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1254 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1255 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1256 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1257 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1258 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1259 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1260 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1261
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1263 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1265 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1267 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1269 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1271 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1273 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1275 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1277 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
6b0dd094 1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1279 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
6b0dd094 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1281 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
6b0dd094 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1283 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
c28eeff2 1284
aab2c27d
MM		 1285 /* BFloat16 instructions. */
1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
c604a79a 1289 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1290 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1291 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1292 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
6576bffe 1293 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
c604a79a 1294
dec41383 1295 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1297 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1299 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1301 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1303 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1305 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1307 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1309 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
6b0dd094 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1311 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
dec41383 1312
b0c11777
RL		 1313 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314 cp_num: bit <11:8> == 0b1001.
1315 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1316 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1317 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1318 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1319 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1320 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1321 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1322 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1323 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
6b0dd094 1324 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1325 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1326 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1327 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1328 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1329 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1330 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1331 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1332 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1333 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1334 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1335 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1336 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1337 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1338 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1339 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1340 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1341 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1342 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1343 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1344 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1345 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1346 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1347 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1348 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1349 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1350 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1351 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1352 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1353 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1354 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1355 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1356 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1357 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1359 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1360 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1361 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1362 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1363 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1364 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1365 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 1366 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1367 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1368 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1369 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1370 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1371 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1372 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1373 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1374 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1375 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1376 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1377 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1378 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1379 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1380 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1381 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1382 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1383 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1384 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1385 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
49e8a725 1387 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1388 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1389 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
6b0dd094 1391 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1392};
1393
33593eaf
MM		 1394/* Generic coprocessor instructions. These are only matched if a more specific
1395 SIMD or co-processor instruction does not match first. */
1396
1397static const struct sopcode32 generic_coprocessor_opcodes[] =
1398{
1399 /* Generic coprocessor instructions. */
1400 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
6576bffe 1401 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
33593eaf
MM		 1402 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403 0x0c500000, 0x0ff00000,
6576bffe 1404 "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406 0x0e000000, 0x0f000010,
6576bffe 1407 "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1408 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409 0x0e10f010, 0x0f10f010,
6576bffe 1410 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1411 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412 0x0e100010, 0x0f100010,
6576bffe 1413 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1414 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415 0x0e000010, 0x0f100010,
6576bffe 1416 "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf 1417 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1418 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1420 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1421
1422 /* V6 coprocessor instructions. */
1423 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424 0xfc500000, 0xfff00000,
6576bffe 1425 "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1426 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427 0xfc400000, 0xfff00000,
6576bffe 1428 "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
33593eaf
MM		 1429
1430 /* V5 coprocessor instructions. */
1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1432 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1433 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1434 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1435 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436 0xfe000000, 0xff000010,
6576bffe 1437 "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439 0xfe000010, 0xff100010,
6576bffe 1440 "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1441 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442 0xfe100010, 0xff100010,
6576bffe 1443 "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1444
1445 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446};
1447
16980d0b
JB		 1448/* Neon opcode table: This does not encode the top byte -- that is
1449 checked by the print_insn_neon routine, as it depends on whether we are
1450 doing thumb32 or arm32 disassembly. */
1451
1452/* print_insn_neon recognizes the following format control codes:
1453
1454 %% %
1455
c22aaad1 1456 %c print condition code
e2efe87d
MGD		 1457 %u print condition code (unconditional in ARM mode,
1458 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1459 %A print v{st,ld}[1234] operands
1460 %B print v{st,ld}[1234] any one operands
1461 %C print v{st,ld}[1234] single->all operands
1462 %D print scalar
1463 %E print vmov, vmvn, vorr, vbic encoded constant
1464 %F print vtbl,vtbx register list
1465
1466 %<bitfield>r print as an ARM register
1467 %<bitfield>d print the bitfield in decimal
1468 %<bitfield>e print the 2^N - bitfield in decimal
1469 %<bitfield>D print as a NEON D register
1470 %<bitfield>Q print as a NEON Q register
1471 %<bitfield>R print as a NEON D or Q register
1472 %<bitfield>Sn print byte scaled width limited by n
1473 %<bitfield>Tn print short scaled width limited by n
1474 %<bitfield>Un print long scaled width limited by n
43e65147 1475
16980d0b
JB		 1476 %<bitfield>'c print specified char iff bitfield is all ones
1477 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1478 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1479
1480static const struct opcode32 neon_opcodes[] =
1481{
fe56b6ce 1482 /* Extract. */
823d2571
TG		 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2b00840, 0xffb00850,
6576bffe 1485 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
823d2571
TG		 1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2b00000, 0xffb00810,
6576bffe 1488 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
16980d0b 1489
9743db03
AV		 1490 /* Data transfer between ARM and NEON registers. */
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1492 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1494 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1496 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1498 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1500 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1502 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1503
fe56b6ce 1504 /* Move data element to all lanes. */
823d2571 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1506 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
823d2571 1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1508 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
823d2571 1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1510 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
16980d0b 1511
fe56b6ce 1512 /* Table lookup. */
823d2571
TG		 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
8e79c3df 1518 /* Half-precision conversions. */
823d2571
TG		 1519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1523
1524 /* NEON fused multiply add instructions. */
823d2571 1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1526 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1530 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1533
aab2c27d
MM		 1534 /* BFloat16 instructions. */
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1538 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
aab2c27d
MM		 1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1546 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
aab2c27d 1547
616ce08e
MM		 1548 /* Matrix Multiply instructions. */
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1558 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1560 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1561
fe56b6ce 1562 /* Two registers, miscellaneous. */
823d2571
TG		 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1571 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf3b20300, 0xffb30fd0,
6576bffe 1607 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
823d2571
TG		 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1637 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1639 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1641 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1643 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1645 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571
TG		 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1655 0xf3bb0600, 0xffbf0e10,
823d2571 1656 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658 0xf3b70600, 0xffbf0e10,
1659 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1660
fe56b6ce 1661 /* Three registers of the same length. */
823d2571
TG		 1662 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1677 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1681 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1701 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1705 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1709 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1713 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1717 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1721 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1725 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1729 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1733 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1737 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1741 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1745 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1749 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1753 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1757 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1761 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1765 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1769 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2000b00, 0xff800f10,
1780 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2000b10, 0xff800f10,
1783 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf3000b00, 0xff800f10,
1792 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2000000, 0xfe800f10,
1795 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2000010, 0xfe800f10,
1798 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2000100, 0xfe800f10,
1801 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2000200, 0xfe800f10,
1804 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2000210, 0xfe800f10,
1807 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2000300, 0xfe800f10,
1810 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2000310, 0xfe800f10,
1813 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2000400, 0xfe800f10,
1816 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2000410, 0xfe800f10,
1819 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2000500, 0xfe800f10,
1822 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824 0xf2000510, 0xfe800f10,
1825 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2000600, 0xfe800f10,
1828 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf2000610, 0xfe800f10,
1831 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2000700, 0xfe800f10,
1834 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2000710, 0xfe800f10,
1837 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2000910, 0xfe800f10,
1840 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2000a00, 0xfe800f10,
1843 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2000a10, 0xfe800f10,
1846 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848 0xf3000b10, 0xff800f10,
1849 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851 0xf3000c10, 0xff800f10,
1852 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1853
fe56b6ce 1854 /* One register and an immediate value. */
823d2571
TG		 1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1881
fe56b6ce 1882 /* Two registers and a shift amount. */
823d2571 1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1884 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1886 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1888 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1890 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1892 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571
TG		 1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf2880950, 0xfeb80fd0,
6576bffe 1895 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1897 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
823d2571 1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1899 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1901 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1903 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1905 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1907 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1909 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1911 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1913 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1915 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571
TG		 1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf2900950, 0xfeb00fd0,
6576bffe 1918 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1920 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
823d2571 1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1922 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1924 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1926 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1928 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1930 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1932 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1934 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1936 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1938 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1940 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1942 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1944 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
823d2571 1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1946 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1948 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1950 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1952 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1954 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1956 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1958 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1960 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571
TG		 1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2a00950, 0xfea00fd0,
6576bffe 1963 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1965 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1967 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1969 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1971 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1973 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1975 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1977 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1979 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1981 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1983 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1985 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1987 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1989 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1991 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1993 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1995 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1997 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1999 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571
TG		 2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2a00e10, 0xfea00e90,
6576bffe 2002 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
cc933301
JW		 2003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004 0xf2a00c10, 0xfea00e90,
6576bffe 2005 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
16980d0b 2006
fe56b6ce 2007 /* Three registers of different lengths. */
823d2571
TG		 2008 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013 0xf2800400, 0xff800f50,
2014 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016 0xf2800600, 0xff800f50,
2017 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019 0xf2800900, 0xff800f50,
2020 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf2800b00, 0xff800f50,
2023 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025 0xf2800d00, 0xff800f50,
2026 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf3800400, 0xff800f50,
2029 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031 0xf3800600, 0xff800f50,
2032 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf2800000, 0xfe800f50,
2035 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037 0xf2800100, 0xfe800f50,
2038 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf2800200, 0xfe800f50,
2041 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043 0xf2800300, 0xfe800f50,
2044 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf2800500, 0xfe800f50,
2047 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049 0xf2800700, 0xfe800f50,
2050 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf2800800, 0xfe800f50,
2053 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055 0xf2800a00, 0xfe800f50,
2056 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf2800c00, 0xfe800f50,
2059 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 2060
fe56b6ce 2061 /* Two registers and a scalar. */
823d2571
TG		 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2065 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2073 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2081 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2093 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2099 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2105 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113 0xf2800240, 0xfe800f50,
2114 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116 0xf2800640, 0xfe800f50,
2117 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119 0xf2800a40, 0xfe800f50,
2120 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122 0xf2800e40, 0xff800f50,
2123 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125 0xf2800f40, 0xff800f50,
2126 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128 0xf3800e40, 0xff800f50,
2129 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131 0xf3800f40, 0xff800f50,
2132 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133 },
16980d0b 2134
fe56b6ce 2135 /* Element and structure load/store. */
823d2571
TG		 2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2176};
2177
73cd51e5
AV		 2178/* mve opcode table. */
2179
2180/* print_insn_mve recognizes the following format control codes:
2181
2182 %% %
2183
ef1576a1
AV		 2184 %a print '+' or '-' or imm offset in vldr[bhwd] and
2185 vstr[bhwd]
9743db03 2186 %c print condition code
aef6d006
AV		 2187 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2188 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2189 %i print MVE predicate(s) for vpt and vpst
23d00a41 2190 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2191 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2192 %m print rounding mode for vcvt and vrint
143275ea 2193 %n print vector comparison code for predicated instruction
bf0b396d 2194 %s print size for various vcvt instructions
143275ea
AV		 2195 %v print vector predicate for instruction in predicated
2196 block
ef1576a1 2197 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2198 %w print writeback mode for MVE v{st,ld}[24]
2199 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2200 %E print vmov, vmvn, vorr, vbic encoded constant
2201 %N print generic index for vmov
14925797 2202 %T print bottom ('b') or top ('t') of source register
d3b63143 2203 %X print exchange field in vmla* instructions
04d54ace 2204
9743db03 2205 %<bitfield>r print as an ARM register
04d54ace 2206 %<bitfield>d print the bitfield in decimal
d3b63143 2207 %<bitfield>A print accumulate or not
e39c1607
SD		 2208 %<bitfield>c print bitfield as a condition code
2209 %<bitfield>C print bitfield as an inverted condition code
143275ea 2210 %<bitfield>Q print as a MVE Q register
c507f10b 2211 %<bitfield>F print as a MVE S register
143275ea
AV		 2212 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2213 UNPREDICTABLE
23d00a41
SD		 2214
2215 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2216 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2217 %<bitfield>I print carry flag or not
ef1576a1 2218 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2219 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2220 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2221 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2222 %<bitfield>o print rotate value for vcmul
1c8f2df8 2223 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2224 %<bitfield>x print the bitfield in hex.
1c8f2df8 2225 */
73cd51e5
AV		 2226
2227static const struct mopcode32 mve_opcodes[] =
2228{
143275ea
AV		 2229 /* MVE. */
2230
2da2eaf4 2231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2232 MVE_VPST,
2233 0xfe310f4d, 0xffbf1fff,
2234 "vpst%i"
2235 },
2236
2237 /* Floating point VPT T1. */
2da2eaf4 2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2239 MVE_VPT_FP_T1,
2240 0xee310f00, 0xefb10f50,
2241 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Floating point VPT T2. */
2da2eaf4 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2244 MVE_VPT_FP_T2,
2245 0xee310f40, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248 /* Vector VPT T1. */
2da2eaf4 2249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2250 MVE_VPT_VEC_T1,
2251 0xfe010f00, 0xff811f51,
2252 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253 /* Vector VPT T2. */
2da2eaf4 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2255 MVE_VPT_VEC_T2,
2256 0xfe010f01, 0xff811f51,
2257 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T3. */
2da2eaf4 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2260 MVE_VPT_VEC_T3,
2261 0xfe011f00, 0xff811f50,
2262 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T4. */
2da2eaf4 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2265 MVE_VPT_VEC_T4,
2266 0xfe010f40, 0xff811f70,
2267 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268 /* Vector VPT T5. */
2da2eaf4 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2270 MVE_VPT_VEC_T5,
2271 0xfe010f60, 0xff811f70,
2272 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T6. */
2da2eaf4 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2275 MVE_VPT_VEC_T6,
2276 0xfe011f40, 0xff811f50,
2277 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
c507f10b 2279 /* Vector VBIC immediate. */
2da2eaf4 2280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2281 MVE_VBIC_IMM,
2282 0xef800070, 0xefb81070,
2283 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285 /* Vector VBIC register. */
2da2eaf4 2286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2287 MVE_VBIC_REG,
2288 0xef100150, 0xffb11f51,
2289 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
66dcaa5d 2291 /* Vector VABAV. */
2da2eaf4 2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2293 MVE_VABAV,
2294 0xee800f01, 0xefc10f51,
2295 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297 /* Vector VABD floating point. */
2da2eaf4 2298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2299 MVE_VABD_FP,
2300 0xff200d40, 0xffa11f51,
2301 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303 /* Vector VABD. */
2da2eaf4 2304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2305 MVE_VABD_VEC,
2306 0xef000740, 0xef811f51,
2307 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309 /* Vector VABS floating point. */
2da2eaf4 2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2311 MVE_VABS_FP,
2312 0xFFB10740, 0xFFB31FD1,
2313 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314 /* Vector VABS. */
2da2eaf4 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2316 MVE_VABS_VEC,
2317 0xffb10340, 0xffb31fd1,
2318 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320 /* Vector VADD floating point T1. */
2da2eaf4 2321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2322 MVE_VADD_FP_T1,
2323 0xef000d40, 0xffa11f51,
2324 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325 /* Vector VADD floating point T2. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2327 MVE_VADD_FP_T2,
2328 0xee300f40, 0xefb11f70,
2329 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330 /* Vector VADD T1. */
2da2eaf4 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2332 MVE_VADD_VEC_T1,
2333 0xef000840, 0xff811f51,
2334 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335 /* Vector VADD T2. */
2da2eaf4 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2337 MVE_VADD_VEC_T2,
2338 0xee010f40, 0xff811f70,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
d3b63143 2341 /* Vector VADDLV. */
2da2eaf4 2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2343 MVE_VADDLV,
2344 0xee890f00, 0xef8f1fd1,
2345 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347 /* Vector VADDV. */
2da2eaf4 2348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2349 MVE_VADDV,
2350 0xeef10f00, 0xeff31fd1,
2351 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
66dcaa5d 2353 /* Vector VADC. */
2da2eaf4 2354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2355 MVE_VADC,
2356 0xee300f00, 0xffb10f51,
2357 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
e523f101 2359 /* Vector VAND. */
2da2eaf4 2360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2361 MVE_VAND,
2362 0xef000150, 0xffb11f51,
2363 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365 /* Vector VBRSR register. */
2da2eaf4 2366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2367 MVE_VBRSR,
2368 0xfe011e60, 0xff811f70,
2369 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
897b9bbc 2371 /* Vector VCADD floating point. */
2da2eaf4 2372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2373 MVE_VCADD_FP,
2374 0xfc800840, 0xfea11f51,
6576bffe 2375 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
897b9bbc
AV		 2376
2377 /* Vector VCADD. */
2da2eaf4 2378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2379 MVE_VCADD_VEC,
2380 0xfe000f00, 0xff810f51,
6576bffe 2381 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2382
e523f101 2383 /* Vector VCLS. */
2da2eaf4 2384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2385 MVE_VCLS,
2386 0xffb00440, 0xffb31fd1,
2387 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389 /* Vector VCLZ. */
2da2eaf4 2390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2391 MVE_VCLZ,
2392 0xffb004c0, 0xffb31fd1,
2393 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
897b9bbc 2395 /* Vector VCMLA. */
2da2eaf4 2396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2397 MVE_VCMLA_FP,
2398 0xfc200840, 0xfe211f51,
6576bffe 2399 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
897b9bbc 2400
143275ea 2401 /* Vector VCMP floating point T1. */
2da2eaf4 2402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2403 MVE_VCMP_FP_T1,
2404 0xee310f00, 0xeff1ef50,
2405 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407 /* Vector VCMP floating point T2. */
2da2eaf4 2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2409 MVE_VCMP_FP_T2,
2410 0xee310f40, 0xeff1ef50,
2411 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413 /* Vector VCMP T1. */
2da2eaf4 2414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2415 MVE_VCMP_VEC_T1,
2416 0xfe010f00, 0xffc1ff51,
2417 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418 /* Vector VCMP T2. */
2da2eaf4 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2420 MVE_VCMP_VEC_T2,
2421 0xfe010f01, 0xffc1ff51,
2422 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T3. */
2da2eaf4 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2425 MVE_VCMP_VEC_T3,
2426 0xfe011f00, 0xffc1ff50,
2427 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T4. */
2da2eaf4 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2430 MVE_VCMP_VEC_T4,
2431 0xfe010f40, 0xffc1ff70,
2432 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433 /* Vector VCMP T5. */
2da2eaf4 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2435 MVE_VCMP_VEC_T5,
2436 0xfe010f60, 0xffc1ff70,
2437 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T6. */
2da2eaf4 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2440 MVE_VCMP_VEC_T6,
2441 0xfe011f40, 0xffc1ff50,
2442 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
9743db03 2444 /* Vector VDUP. */
2da2eaf4 2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2446 MVE_VDUP,
2447 0xeea00b10, 0xffb10f5f,
2448 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450 /* Vector VEOR. */
2da2eaf4 2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2452 MVE_VEOR,
2453 0xff000150, 0xffd11f51,
2454 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456 /* Vector VFMA, vector * scalar. */
2da2eaf4 2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2458 MVE_VFMA_FP_SCALAR,
2459 0xee310e40, 0xefb11f70,
2460 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462 /* Vector VFMA floating point. */
2da2eaf4 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2464 MVE_VFMA_FP,
2465 0xef000c50, 0xffa11f51,
2466 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468 /* Vector VFMS floating point. */
2da2eaf4 2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2470 MVE_VFMS_FP,
2471 0xef200c50, 0xffa11f51,
2472 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2476 MVE_VFMAS_FP_SCALAR,
2477 0xee311e40, 0xefb11f70,
2478 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480 /* Vector VHADD T1. */
2da2eaf4 2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2482 MVE_VHADD_T1,
2483 0xef000040, 0xef811f51,
2484 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486 /* Vector VHADD T2. */
2da2eaf4 2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2488 MVE_VHADD_T2,
2489 0xee000f40, 0xef811f70,
2490 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492 /* Vector VHSUB T1. */
2da2eaf4 2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2494 MVE_VHSUB_T1,
2495 0xef000240, 0xef811f51,
2496 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498 /* Vector VHSUB T2. */
2da2eaf4 2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2500 MVE_VHSUB_T2,
2501 0xee001f40, 0xef811f70,
2502 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
897b9bbc 2504 /* Vector VCMUL. */
2da2eaf4 2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2506 MVE_VCMUL_FP,
2507 0xee300e00, 0xefb10f50,
6576bffe 2508 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
897b9bbc 2509
e523f101 2510 /* Vector VCTP. */
2da2eaf4 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2512 MVE_VCTP,
2513 0xf000e801, 0xffc0ffff,
2514 "vctp%v.%20-21s\t%16-19r"},
2515
9743db03 2516 /* Vector VDUP. */
2da2eaf4 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2518 MVE_VDUP,
2519 0xeea00b10, 0xffb10f5f,
2520 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522 /* Vector VRHADD. */
2da2eaf4 2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2524 MVE_VRHADD,
2525 0xef000140, 0xef811f51,
2526 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
bf0b396d 2528 /* Vector VCVT. */
2da2eaf4 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2530 MVE_VCVT_FP_FIX_VEC,
2531 0xef800c50, 0xef801cd1,
6576bffe 2532 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
bf0b396d
AV		 2533
2534 /* Vector VCVT. */
2da2eaf4 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2536 MVE_VCVT_BETWEEN_FP_INT,
2537 0xffb30640, 0xffb31e51,
2538 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2542 MVE_VCVT_FP_HALF_FP,
2543 0xee3f0e01, 0xefbf1fd1,
2544 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2548 MVE_VCVT_FP_HALF_FP,
2549 0xee3f1e01, 0xefbf1fd1,
2550 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552 /* Vector VCVT. */
2da2eaf4 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2554 MVE_VCVT_FROM_FP_TO_INT,
2555 0xffb30040, 0xffb31c51,
2556 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
1c8f2df8 2558 /* Vector VDDUP. */
2da2eaf4 2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2560 MVE_VDDUP,
2561 0xee011f6e, 0xff811f7e,
6576bffe 2562 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8
AV		 2563
2564 /* Vector VDWDUP. */
2da2eaf4 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2566 MVE_VDWDUP,
2567 0xee011f60, 0xff811f70,
6576bffe 2568 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8 2569
897b9bbc 2570 /* Vector VHCADD. */
2da2eaf4 2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2572 MVE_VHCADD,
2573 0xee000f00, 0xff810f51,
6576bffe 2574 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2575
1c8f2df8 2576 /* Vector VIWDUP. */
2da2eaf4 2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2578 MVE_VIWDUP,
2579 0xee010f60, 0xff811f70,
6576bffe 2580 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8
AV		 2581
2582 /* Vector VIDUP. */
2da2eaf4 2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2584 MVE_VIDUP,
2585 0xee010f6e, 0xff811f7e,
6576bffe 2586 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8 2587
04d54ace 2588 /* Vector VLD2. */
2da2eaf4 2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2590 MVE_VLD2,
2591 0xfc901e00, 0xff901e5f,
2592 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594 /* Vector VLD4. */
2da2eaf4 2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2596 MVE_VLD4,
2597 0xfc901e01, 0xff901e1f,
2598 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
ef1576a1 2600 /* Vector VLDRB gather load. */
2da2eaf4 2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2602 MVE_VLDRB_GATHER_T1,
2603 0xec900e00, 0xefb01e50,
2604 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606 /* Vector VLDRH gather load. */
2da2eaf4 2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2608 MVE_VLDRH_GATHER_T2,
2609 0xec900e10, 0xefb01e50,
2610 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612 /* Vector VLDRW gather load. */
2da2eaf4 2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2614 MVE_VLDRW_GATHER_T3,
2615 0xfc900f40, 0xffb01fd0,
2616 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618 /* Vector VLDRD gather load. */
2da2eaf4 2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2620 MVE_VLDRD_GATHER_T4,
2621 0xec900fd0, 0xefb01fd0,
2622 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624 /* Vector VLDRW gather load. */
2da2eaf4 2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2626 MVE_VLDRW_GATHER_T5,
2627 0xfd101e00, 0xff111f00,
6576bffe 2628 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 2629
2630 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2632 MVE_VLDRD_GATHER_T6,
2633 0xfd101f00, 0xff111f00,
6576bffe 2634 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 2635
aef6d006 2636 /* Vector VLDRB. */
2da2eaf4 2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2638 MVE_VLDRB_T1,
2639 0xec100e00, 0xee581e00,
2640 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642 /* Vector VLDRH. */
2da2eaf4 2643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2644 MVE_VLDRH_T2,
2645 0xec180e00, 0xee581e00,
2646 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2650 MVE_VLDRB_T5,
2651 0xec101e00, 0xfe101f80,
2652 "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2656 MVE_VLDRH_T6,
2657 0xec101e80, 0xfe101f80,
2658 "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2662 MVE_VLDRW_T7,
2663 0xec101f00, 0xfe101f80,
2664 "vldrw%v.u32\t%13-15,22Q, %d"},
2665
56858bea 2666 /* Vector VMAX. */
2da2eaf4 2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2668 MVE_VMAX,
2669 0xef000640, 0xef811f51,
2670 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672 /* Vector VMAXA. */
2da2eaf4 2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2674 MVE_VMAXA,
2675 0xee330e81, 0xffb31fd1,
2676 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678 /* Vector VMAXNM floating point. */
2da2eaf4 2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2680 MVE_VMAXNM_FP,
2681 0xff000f50, 0xffa11f51,
2682 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684 /* Vector VMAXNMA floating point. */
2da2eaf4 2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2686 MVE_VMAXNMA_FP,
2687 0xee3f0e81, 0xefbf1fd1,
2688 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690 /* Vector VMAXNMV floating point. */
2da2eaf4 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2692 MVE_VMAXNMV_FP,
2693 0xeeee0f00, 0xefff0fd1,
2694 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696 /* Vector VMAXNMAV floating point. */
2da2eaf4 2697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2698 MVE_VMAXNMAV_FP,
2699 0xeeec0f00, 0xefff0fd1,
2700 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702 /* Vector VMAXV. */
2da2eaf4 2703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2704 MVE_VMAXV,
2705 0xeee20f00, 0xeff30fd1,
2706 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708 /* Vector VMAXAV. */
2da2eaf4 2709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2710 MVE_VMAXAV,
2711 0xeee00f00, 0xfff30fd1,
2712 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714 /* Vector VMIN. */
2da2eaf4 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2716 MVE_VMIN,
2717 0xef000650, 0xef811f51,
2718 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720 /* Vector VMINA. */
2da2eaf4 2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2722 MVE_VMINA,
2723 0xee331e81, 0xffb31fd1,
2724 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726 /* Vector VMINNM floating point. */
2da2eaf4 2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2728 MVE_VMINNM_FP,
2729 0xff200f50, 0xffa11f51,
2730 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732 /* Vector VMINNMA floating point. */
2da2eaf4 2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2734 MVE_VMINNMA_FP,
2735 0xee3f1e81, 0xefbf1fd1,
2736 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738 /* Vector VMINNMV floating point. */
2da2eaf4 2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2740 MVE_VMINNMV_FP,
2741 0xeeee0f80, 0xefff0fd1,
2742 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744 /* Vector VMINNMAV floating point. */
2da2eaf4 2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2746 MVE_VMINNMAV_FP,
2747 0xeeec0f80, 0xefff0fd1,
2748 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750 /* Vector VMINV. */
2da2eaf4 2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2752 MVE_VMINV,
2753 0xeee20f80, 0xeff30fd1,
2754 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756 /* Vector VMINAV. */
2da2eaf4 2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2758 MVE_VMINAV,
2759 0xeee00f80, 0xfff30fd1,
2760 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762 /* Vector VMLA. */
2da2eaf4 2763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2764 MVE_VMLA,
2765 0xee010e40, 0xef811f70,
2766 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2767
d3b63143
AV		 2768 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2769 opcode aliasing. */
2da2eaf4 2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2771 MVE_VMLALDAV,
2772 0xee801e00, 0xef801f51,
2773 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2da2eaf4 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2776 MVE_VMLALDAV,
2777 0xee800e00, 0xef801f51,
2778 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2782 MVE_VMLADAV_T1,
2783 0xeef00e00, 0xeff01f51,
2784 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2788 MVE_VMLADAV_T2,
2789 0xeef00f00, 0xeff11f51,
2790 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792 /* Vector VMLADAV T1 variant. */
2da2eaf4 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2794 MVE_VMLADAV_T1,
2795 0xeef01e00, 0xeff01f51,
2796 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798 /* Vector VMLADAV T2 variant. */
2da2eaf4 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2800 MVE_VMLADAV_T2,
2801 0xeef01f00, 0xeff11f51,
2802 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804 /* Vector VMLAS. */
2da2eaf4 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2806 MVE_VMLAS,
2807 0xee011e40, 0xef811f70,
2808 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2811 opcode aliasing. */
2da2eaf4 2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2813 MVE_VRMLSLDAVH,
2814 0xfe800e01, 0xff810f51,
2815 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2818 opcdoe aliasing. */
2da2eaf4 2819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2820 MVE_VMLSLDAV,
2821 0xee800e01, 0xff800f51,
2822 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2826 MVE_VMLSDAV_T1,
2827 0xeef00e01, 0xfff00f51,
2828 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2832 MVE_VMLSDAV_T2,
2833 0xfef00e01, 0xfff10f51,
2834 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
c507f10b 2836 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2838 MVE_VMOV_HFP_TO_GP,
2839 0xee000910, 0xfff00f7f,
2840 "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2844 MVE_VMOV_HFP_TO_GP,
2845 0xee100910, 0xfff00f7f,
2846 "vmov.f16\t%12-15r, %7,16-19F"},
2847
2da2eaf4 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2849 MVE_VMOV_GP_TO_VEC_LANE,
2850 0xee000b10, 0xff900f1f,
6576bffe 2851 "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
c507f10b
AV		 2852
2853 /* Vector VORR immediate to vector.
2854 NOTE: MVE_VORR_IMM must appear in the table
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2857 MVE_VORR_IMM,
2858 0xef800050, 0xefb810f0,
2859 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
ed63aa17
AV		 2861 /* Vector VQSHL T2 Variant.
2862 NOTE: MVE_VQSHL_T2 must appear in the table before
2863 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2865 MVE_VQSHL_T2,
2866 0xef800750, 0xef801fd1,
6576bffe 2867 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2868
2869 /* Vector VQSHLU T3 Variant
2870 NOTE: MVE_VQSHL_T2 must appear in the table before
2871 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2872
2da2eaf4 2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2874 MVE_VQSHLU_T3,
2875 0xff800650, 0xff801fd1,
6576bffe 2876 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2877
2878 /* Vector VRSHR
2879 NOTE: MVE_VRSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2882 MVE_VRSHR,
2883 0xef800250, 0xef801fd1,
6576bffe 2884 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2885
2886 /* Vector VSHL.
2887 NOTE: MVE_VSHL must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2890 MVE_VSHL_T1,
2891 0xef800550, 0xff801fd1,
6576bffe 2892 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2893
2894 /* Vector VSHR
2895 NOTE: MVE_VSHR must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2898 MVE_VSHR,
2899 0xef800050, 0xef801fd1,
6576bffe 2900 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2901
2902 /* Vector VSLI
2903 NOTE: MVE_VSLI must appear in the table before
2904 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2906 MVE_VSLI,
2907 0xff800550, 0xff801fd1,
6576bffe 2908 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2909
2910 /* Vector VSRI
2911 NOTE: MVE_VSRI must appear in the table before
2912 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2914 MVE_VSRI,
2915 0xff800450, 0xff801fd1,
6576bffe 2916 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2917
c507f10b 2918 /* Vector VMOV immediate to vector,
ce760a76 2919 undefinded for cmode == 1111 */
2da2eaf4 2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2921 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923 /* Vector VMOV immediate to vector,
2924 cmode == 1101 */
2da2eaf4 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2926 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2928
2929 /* Vector VMOV immediate to vector. */
2da2eaf4 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2931 MVE_VMOV_IMM_TO_VEC,
2932 0xef800050, 0xefb810d0,
2933 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2937 MVE_VMOV2_VEC_LANE_TO_GP,
2938 0xec000f00, 0xffb01ff0,
6576bffe 2939 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
c507f10b
AV		 2940
2941 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2943 MVE_VMOV2_VEC_LANE_TO_GP,
2944 0xec000f10, 0xffb01ff0,
6576bffe 2945 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
c507f10b
AV		 2946
2947 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2949 MVE_VMOV2_GP_TO_VEC_LANE,
2950 0xec100f00, 0xffb01ff0,
6576bffe 2951 "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
c507f10b
AV		 2952
2953 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2955 MVE_VMOV2_GP_TO_VEC_LANE,
2956 0xec100f10, 0xffb01ff0,
6576bffe 2957 "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
c507f10b
AV		 2958
2959 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2961 MVE_VMOV_VEC_LANE_TO_GP,
2962 0xee100b10, 0xff100f1f,
6576bffe 2963 "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
c507f10b 2964
ed63aa17
AV		 2965 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2966 to instruction opcode aliasing. */
2da2eaf4 2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2968 MVE_VSHLL_T1,
2969 0xeea00f40, 0xefa00fd1,
6576bffe 2970 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2971
14925797 2972 /* Vector VMOVL long. */
2da2eaf4 2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2974 MVE_VMOVL,
2975 0xeea00f40, 0xefa70fd1,
2976 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978 /* Vector VMOV and narrow. */
2da2eaf4 2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2980 MVE_VMOVN,
2981 0xfe310e81, 0xffb30fd1,
2982 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
c507f10b 2984 /* Floating point move extract. */
2da2eaf4 2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2986 MVE_VMOVX,
2987 0xfeb00a40, 0xffbf0fd0,
2988 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
f49bb598 2990 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2992 MVE_VMUL_FP_T1,
2993 0xff000d50, 0xffa11f51,
2994 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 2997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2998 MVE_VMUL_FP_T2,
2999 0xee310e60, 0xefb11f70,
3000 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002 /* Vector VMUL T1 variant. */
2da2eaf4 3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3004 MVE_VMUL_VEC_T1,
3005 0xef000950, 0xff811f51,
3006 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008 /* Vector VMUL T2 variant. */
2da2eaf4 3009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3010 MVE_VMUL_VEC_T2,
3011 0xee011e60, 0xff811f70,
3012 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014 /* Vector VMULH. */
2da2eaf4 3015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3016 MVE_VMULH,
3017 0xee010e01, 0xef811f51,
3018 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020 /* Vector VRMULH. */
2da2eaf4 3021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3022 MVE_VRMULH,
3023 0xee011e01, 0xef811f51,
3024 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
14925797 3026 /* Vector VMULL integer. */
2da2eaf4 3027 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3028 MVE_VMULL_INT,
3029 0xee010e00, 0xef810f51,
3030 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032 /* Vector VMULL polynomial. */
2da2eaf4 3033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3034 MVE_VMULL_POLY,
3035 0xee310e00, 0xefb10f51,
3036 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
c507f10b 3038 /* Vector VMVN immediate to vector. */
2da2eaf4 3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3040 MVE_VMVN_IMM,
3041 0xef800070, 0xefb810f0,
3042 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044 /* Vector VMVN register. */
2da2eaf4 3045 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3046 MVE_VMVN_REG,
3047 0xffb005c0, 0xffbf1fd1,
3048 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
f49bb598 3050 /* Vector VNEG floating point. */
2da2eaf4 3051 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3052 MVE_VNEG_FP,
3053 0xffb107c0, 0xffb31fd1,
3054 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056 /* Vector VNEG. */
2da2eaf4 3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3058 MVE_VNEG_VEC,
3059 0xffb103c0, 0xffb31fd1,
3060 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
c507f10b 3062 /* Vector VORN, vector bitwise or not. */
2da2eaf4 3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3064 MVE_VORN,
3065 0xef300150, 0xffb11f51,
3066 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068 /* Vector VORR register. */
2da2eaf4 3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3070 MVE_VORR_REG,
3071 0xef200150, 0xffb11f51,
3072 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
c4a23bf8
SP		 3074 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077 array. */
3078
2da2eaf4 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 3080 MVE_VMOV_VEC_TO_VEC,
3081 0xef200150, 0xffb11f51,
3082 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
14925797 3084 /* Vector VQDMULL T1 variant. */
2da2eaf4 3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3086 MVE_VQDMULL_T1,
3087 0xee300f01, 0xefb10f51,
3088 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
14b456f2 3090 /* Vector VPNOT. */
2da2eaf4 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3092 MVE_VPNOT,
3093 0xfe310f4d, 0xffffffff,
3094 "vpnot%v"},
3095
3096 /* Vector VPSEL. */
2da2eaf4 3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3098 MVE_VPSEL,
3099 0xfe310f01, 0xffb11f51,
3100 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102 /* Vector VQABS. */
2da2eaf4 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3104 MVE_VQABS,
3105 0xffb00740, 0xffb31fd1,
3106 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108 /* Vector VQADD T1 variant. */
2da2eaf4 3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3110 MVE_VQADD_T1,
3111 0xef000050, 0xef811f51,
3112 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114 /* Vector VQADD T2 variant. */
2da2eaf4 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3116 MVE_VQADD_T2,
3117 0xee000f60, 0xef811f70,
3118 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
14925797 3120 /* Vector VQDMULL T2 variant. */
2da2eaf4 3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3122 MVE_VQDMULL_T2,
3123 0xee300f60, 0xefb10f70,
3124 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126 /* Vector VQMOVN. */
2da2eaf4 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3128 MVE_VQMOVN,
3129 0xee330e01, 0xefb30fd1,
3130 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132 /* Vector VQMOVUN. */
2da2eaf4 3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3134 MVE_VQMOVUN,
3135 0xee310e81, 0xffb30fd1,
3136 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
d3b63143 3138 /* Vector VQDMLADH. */
2da2eaf4 3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3140 MVE_VQDMLADH,
3141 0xee000e00, 0xff810f51,
3142 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144 /* Vector VQRDMLADH. */
2da2eaf4 3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3146 MVE_VQRDMLADH,
3147 0xee000e01, 0xff810f51,
3148 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150 /* Vector VQDMLAH. */
2da2eaf4 3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3152 MVE_VQDMLAH,
23d188c7 3153 0xee000e60, 0xff811f70,
d3b63143
AV		 3154 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156 /* Vector VQRDMLAH. */
2da2eaf4 3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3158 MVE_VQRDMLAH,
23d188c7 3159 0xee000e40, 0xff811f70,
d3b63143
AV		 3160 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162 /* Vector VQDMLASH. */
2da2eaf4 3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3164 MVE_VQDMLASH,
23d188c7 3165 0xee001e60, 0xff811f70,
d3b63143
AV		 3166 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168 /* Vector VQRDMLASH. */
2da2eaf4 3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3170 MVE_VQRDMLASH,
23d188c7 3171 0xee001e40, 0xff811f70,
d3b63143
AV		 3172 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174 /* Vector VQDMLSDH. */
2da2eaf4 3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3176 MVE_VQDMLSDH,
3177 0xfe000e00, 0xff810f51,
3178 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180 /* Vector VQRDMLSDH. */
2da2eaf4 3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3182 MVE_VQRDMLSDH,
3183 0xfe000e01, 0xff810f51,
3184 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186 /* Vector VQDMULH T1 variant. */
2da2eaf4 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3188 MVE_VQDMULH_T1,
3189 0xef000b40, 0xff811f51,
3190 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3194 MVE_VQRDMULH_T2,
3195 0xff000b40, 0xff811f51,
3196 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198 /* Vector VQDMULH T3 variant. */
2da2eaf4 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3200 MVE_VQDMULH_T3,
3201 0xee010e60, 0xff811f70,
3202 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3206 MVE_VQRDMULH_T4,
3207 0xfe010e60, 0xff811f70,
3208 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
14b456f2 3210 /* Vector VQNEG. */
2da2eaf4 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3212 MVE_VQNEG,
3213 0xffb007c0, 0xffb31fd1,
3214 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
ed63aa17 3216 /* Vector VQRSHL T1 variant. */
2da2eaf4 3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3218 MVE_VQRSHL_T1,
3219 0xef000550, 0xef811f51,
3220 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222 /* Vector VQRSHL T2 variant. */
2da2eaf4 3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3224 MVE_VQRSHL_T2,
3225 0xee331ee0, 0xefb31ff0,
3226 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228 /* Vector VQRSHRN. */
2da2eaf4 3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3230 MVE_VQRSHRN,
3231 0xee800f41, 0xefa00fd1,
6576bffe 3232 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3233
3234 /* Vector VQRSHRUN. */
2da2eaf4 3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3236 MVE_VQRSHRUN,
3237 0xfe800fc0, 0xffa00fd1,
6576bffe 3238 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3239
3240 /* Vector VQSHL T1 Variant. */
2da2eaf4 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3242 MVE_VQSHL_T1,
3243 0xee311ee0, 0xefb31ff0,
3244 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246 /* Vector VQSHL T4 Variant. */
2da2eaf4 3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3248 MVE_VQSHL_T4,
3249 0xef000450, 0xef811f51,
3250 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252 /* Vector VQSHRN. */
2da2eaf4 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3254 MVE_VQSHRN,
3255 0xee800f40, 0xefa00fd1,
6576bffe 3256 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3257
3258 /* Vector VQSHRUN. */
2da2eaf4 3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3260 MVE_VQSHRUN,
3261 0xee800fc0, 0xffa00fd1,
6576bffe 3262 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3263
14b456f2 3264 /* Vector VQSUB T1 Variant. */
2da2eaf4 3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3266 MVE_VQSUB_T1,
3267 0xef000250, 0xef811f51,
3268 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270 /* Vector VQSUB T2 Variant. */
2da2eaf4 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3272 MVE_VQSUB_T2,
3273 0xee001f60, 0xef811f70,
3274 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276 /* Vector VREV16. */
2da2eaf4 3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3278 MVE_VREV16,
3279 0xffb00140, 0xffb31fd1,
3280 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282 /* Vector VREV32. */
2da2eaf4 3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3284 MVE_VREV32,
3285 0xffb000c0, 0xffb31fd1,
3286 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288 /* Vector VREV64. */
2da2eaf4 3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3290 MVE_VREV64,
3291 0xffb00040, 0xffb31fd1,
3292 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
bf0b396d 3294 /* Vector VRINT floating point. */
2da2eaf4 3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3296 MVE_VRINT_FP,
3297 0xffb20440, 0xffb31c51,
3298 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
d3b63143 3300 /* Vector VRMLALDAVH. */
2da2eaf4 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3302 MVE_VRMLALDAVH,
3303 0xee800f00, 0xef811f51,
3304 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306 /* Vector VRMLALDAVH. */
2da2eaf4 3307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3308 MVE_VRMLALDAVH,
3309 0xee801f00, 0xef811f51,
3310 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
ed63aa17 3312 /* Vector VRSHL T1 Variant. */
2da2eaf4 3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3314 MVE_VRSHL_T1,
3315 0xef000540, 0xef811f51,
3316 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318 /* Vector VRSHL T2 Variant. */
2da2eaf4 3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3320 MVE_VRSHL_T2,
3321 0xee331e60, 0xefb31ff0,
3322 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324 /* Vector VRSHRN. */
2da2eaf4 3325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3326 MVE_VRSHRN,
3327 0xfe800fc1, 0xffa00fd1,
6576bffe 3328 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3329
66dcaa5d 3330 /* Vector VSBC. */
2da2eaf4 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3332 MVE_VSBC,
3333 0xfe300f00, 0xffb10f51,
3334 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
ed63aa17 3336 /* Vector VSHL T2 Variant. */
2da2eaf4 3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3338 MVE_VSHL_T2,
3339 0xee311e60, 0xefb31ff0,
3340 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342 /* Vector VSHL T3 Variant. */
2da2eaf4 3343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3344 MVE_VSHL_T3,
3345 0xef000440, 0xef811f51,
3346 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348 /* Vector VSHLC. */
2da2eaf4 3349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3350 MVE_VSHLC,
3351 0xeea00fc0, 0xffa01ff0,
6576bffe 3352 "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
ed63aa17
AV		 3353
3354 /* Vector VSHLL T2 Variant. */
2da2eaf4 3355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3356 MVE_VSHLL_T2,
3357 0xee310e01, 0xefb30fd1,
6576bffe 3358 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
ed63aa17
AV		 3359
3360 /* Vector VSHRN. */
2da2eaf4 3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3362 MVE_VSHRN,
3363 0xee800fc1, 0xffa00fd1,
6576bffe 3364 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3365
04d54ace 3366 /* Vector VST2 no writeback. */
2da2eaf4 3367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3368 MVE_VST2,
3369 0xfc801e00, 0xffb01e5f,
3370 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372 /* Vector VST2 writeback. */
2da2eaf4 3373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3374 MVE_VST2,
3375 0xfca01e00, 0xffb01e5f,
3376 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378 /* Vector VST4 no writeback. */
2da2eaf4 3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3380 MVE_VST4,
3381 0xfc801e01, 0xffb01e1f,
3382 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384 /* Vector VST4 writeback. */
2da2eaf4 3385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3386 MVE_VST4,
3387 0xfca01e01, 0xffb01e1f,
3388 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
ef1576a1 3390 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3392 MVE_VSTRB_SCATTER_T1,
3393 0xec800e00, 0xffb01e50,
3394 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3398 MVE_VSTRH_SCATTER_T2,
3399 0xec800e10, 0xffb01e50,
3400 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3404 MVE_VSTRW_SCATTER_T3,
3405 0xec800e40, 0xffb01e50,
3406 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3410 MVE_VSTRD_SCATTER_T4,
3411 0xec800fd0, 0xffb01fd0,
3412 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3416 MVE_VSTRW_SCATTER_T5,
3417 0xfd001e00, 0xff111f00,
6576bffe 3418 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 3419
3420 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3422 MVE_VSTRD_SCATTER_T6,
3423 0xfd001f00, 0xff111f00,
6576bffe 3424 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 3425
aef6d006 3426 /* Vector VSTRB. */
2da2eaf4 3427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3428 MVE_VSTRB_T1,
3429 0xec000e00, 0xfe581e00,
3430 "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432 /* Vector VSTRH. */
2da2eaf4 3433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3434 MVE_VSTRH_T2,
3435 0xec080e00, 0xfe581e00,
3436 "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438 /* Vector VSTRB variant T5. */
2da2eaf4 3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3440 MVE_VSTRB_T5,
3441 0xec001e00, 0xfe101f80,
3442 "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444 /* Vector VSTRH variant T6. */
2da2eaf4 3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3446 MVE_VSTRH_T6,
3447 0xec001e80, 0xfe101f80,
3448 "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450 /* Vector VSTRW variant T7. */
2da2eaf4 3451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3452 MVE_VSTRW_T7,
3453 0xec001f00, 0xfe101f80,
3454 "vstrw%v.32\t%13-15,22Q, %d"},
3455
66dcaa5d 3456 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3458 MVE_VSUB_FP_T1,
3459 0xef200d40, 0xffa11f51,
3460 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3464 MVE_VSUB_FP_T2,
3465 0xee301f40, 0xefb11f70,
3466 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468 /* Vector VSUB T1 variant. */
2da2eaf4 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3470 MVE_VSUB_VEC_T1,
3471 0xff000840, 0xff811f51,
3472 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474 /* Vector VSUB T2 variant. */
2da2eaf4 3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3476 MVE_VSUB_VEC_T2,
3477 0xee011f40, 0xff811f70,
3478 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
2da2eaf4 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3481 MVE_ASRLI,
3482 0xea50012f, 0xfff1813f,
3483 "asrl%c\t%17-19l, %9-11h, %j"},
3484
2da2eaf4 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3486 MVE_ASRL,
3487 0xea50012d, 0xfff101ff,
3488 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
2da2eaf4 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3491 MVE_LSLLI,
3492 0xea50010f, 0xfff1813f,
3493 "lsll%c\t%17-19l, %9-11h, %j"},
3494
2da2eaf4 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3496 MVE_LSLL,
3497 0xea50010d, 0xfff101ff,
3498 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
2da2eaf4 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3501 MVE_LSRL,
3502 0xea50011f, 0xfff1813f,
3503 "lsrl%c\t%17-19l, %9-11h, %j"},
3504
2da2eaf4 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3506 MVE_SQRSHRL,
08132bdd
SP		 3507 0xea51012d, 0xfff1017f,
3508 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3509
2da2eaf4 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3511 MVE_SQRSHR,
3512 0xea500f2d, 0xfff00fff,
3513 "sqrshr%c\t%16-19S, %12-15S"},
3514
2da2eaf4 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3516 MVE_SQSHLL,
3517 0xea51013f, 0xfff1813f,
3518 "sqshll%c\t%17-19l, %9-11h, %j"},
3519
2da2eaf4 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3521 MVE_SQSHL,
3522 0xea500f3f, 0xfff08f3f,
3523 "sqshl%c\t%16-19S, %j"},
3524
2da2eaf4 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3526 MVE_SRSHRL,
3527 0xea51012f, 0xfff1813f,
3528 "srshrl%c\t%17-19l, %9-11h, %j"},
3529
2da2eaf4 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3531 MVE_SRSHR,
3532 0xea500f2f, 0xfff08f3f,
3533 "srshr%c\t%16-19S, %j"},
3534
2da2eaf4 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3536 MVE_UQRSHLL,
08132bdd
SP		 3537 0xea51010d, 0xfff1017f,
3538 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3539
2da2eaf4 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3541 MVE_UQRSHL,
3542 0xea500f0d, 0xfff00fff,
3543 "uqrshl%c\t%16-19S, %12-15S"},
3544
2da2eaf4 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3546 MVE_UQSHLL,
3547 0xea51010f, 0xfff1813f,
3548 "uqshll%c\t%17-19l, %9-11h, %j"},
3549
2da2eaf4 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3551 MVE_UQSHL,
3552 0xea500f0f, 0xfff08f3f,
3553 "uqshl%c\t%16-19S, %j"},
3554
2da2eaf4 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3556 MVE_URSHRL,
3557 0xea51011f, 0xfff1813f,
3558 "urshrl%c\t%17-19l, %9-11h, %j"},
3559
2da2eaf4 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3561 MVE_URSHR,
3562 0xea500f1f, 0xfff08f3f,
3563 "urshr%c\t%16-19S, %j"},
3564
e39c1607
SD		 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566 MVE_CSINC,
3567 0xea509000, 0xfff0f000,
3568 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571 MVE_CSINV,
3572 0xea50a000, 0xfff0f000,
3573 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576 MVE_CSET,
3577 0xea5f900f, 0xfffff00f,
3578 "cset\t%8-11S, %4-7C"},
3579
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581 MVE_CSETM,
3582 0xea5fa00f, 0xfffff00f,
3583 "csetm\t%8-11S, %4-7C"},
3584
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586 MVE_CSEL,
3587 0xea508000, 0xfff0f000,
3588 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591 MVE_CSNEG,
3592 0xea50b000, 0xfff0f000,
3593 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596 MVE_CINC,
3597 0xea509000, 0xfff0f000,
3598 "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601 MVE_CINV,
3602 0xea50a000, 0xfff0f000,
3603 "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606 MVE_CNEG,
3607 0xea50b000, 0xfff0f000,
3608 "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
143275ea
AV		 3610 {ARM_FEATURE_CORE_LOW (0),
3611 MVE_NONE,
3612 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3613};
3614
8f06b2d8
PB		 3615/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3616 ordered: they must be searched linearly from the top to obtain a correct
3617 match. */
3618
3619/* print_insn_arm recognizes the following format control codes:
3620
3621 %% %
3622
3623 %a print address for ldr/str instruction
3624 %s print address for ldr/str halfword/signextend instruction
c1e26897 3625 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3626 %b print branch destination
3627 %c print condition code (always bits 28-31)
3628 %m print register mask for ldm/stm instruction
3629 %o print operand2 (immediate or register + shift)
3630 %p print 'p' iff bits 12-15 are 15
3631 %t print 't' iff bit 21 set and bit 24 clear
3632 %B print arm BLX(1) destination
3633 %C print the PSR sub type.
62b3e311
PB		 3634 %U print barrier type.
3635 %P print address for pli instruction.
8f06b2d8
PB		 3636
3637 %<bitfield>r print as an ARM register
9eb6c0f1 3638 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3639 %<bitfield>R as %r but r15 is UNPREDICTABLE
3640 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3642 %<bitfield>d print the bitfield in decimal
43e65147 3643 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3644 %<bitfield>x print the bitfield in hex
3645 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3646
16980d0b
JB		 3647 %<bitfield>'c print specified char iff bitfield is all ones
3648 %<bitfield>`c print specified char iff bitfield is all zeroes
3649 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3650
8f06b2d8
PB		 3651 %e print arm SMI operand (bits 0..7,8..19).
3652 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3653 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3654 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3655
8f06b2d8
PB		 3656static const struct opcode32 arm_opcodes[] =
3657{
3658 /* ARM instructions. */
823d2571 3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 3660 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
823d2571 3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3662 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
823d2571
TG		 3663
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673 0x00800090, 0x0fa000f0,
3674 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676 0x00a00090, 0x0fa000f0,
3677 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3678
105bde57 3679 /* V8.2 RAS extension instructions. */
4d1464f2 3680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3681 0xe320f010, 0xffffffff, "esb"},
3682
26417f19
AC		 3683 /* V8-R instructions. */
3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685 0xf57ff04c, 0xffffffff, "dfb"},
3686
53c4b28b 3687 /* V8 instructions. */
823d2571
TG		 3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3690 /* Defined in V8 but is in NOP space so available to all arch. */
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3692 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
4ed7ed8d 3693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3694 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3696 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3701 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3702 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3703 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3704 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3705 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3706 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3707 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3708 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3709 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3710 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3711 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3712 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3713 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3714 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3716 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3717 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3718 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3719 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3720 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3721 /* CRC32 instructions. */
8b301fbb 3722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3723 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3725 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3727 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3729 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3731 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3733 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3734
ddfded2f
MW		 3735 /* Privileged Access Never extension instructions. */
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
6576bffe 3737 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
ddfded2f 3738
90ec0d68 3739 /* Virtualization Extension instructions. */
823d2571
TG		 3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3742
eea54501 3743 /* Integer Divide Extension instructions. */
823d2571
TG		 3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3748
60e5ef9f 3749 /* MP Extension instructions. */
823d2571 3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3751
c597cc3d
SD		 3752 /* Speculation Barriers. */
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
62b3e311 3757 /* V7 instructions. */
823d2571 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
6576bffe 3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a 3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 3766 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
62b3e311 3767
c19d1205 3768 /* ARM V6T2 instructions. */
823d2571
TG		 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
ff8646ee 3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3784 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3786 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 3790 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
885fc257 3791
f4c65163 3792 /* ARM Security extension instructions. */
823d2571
TG		 3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3795
8f06b2d8 3796 /* ARM V6K instructions. */
823d2571
TG		 3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798 0xf57ff01f, 0xffffffff, "clrex"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3811
7fadb25d
SD		 3812 /* ARMv8.5-A instructions. */
3813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
8f06b2d8 3815 /* ARM V6K NOP hints. */
823d2571
TG		 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817 0x0320f001, 0x0fffffff, "yield%c"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819 0x0320f002, 0x0fffffff, "wfe%c"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821 0x0320f003, 0x0fffffff, "wfi%c"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823 0x0320f004, 0x0fffffff, "sev%c"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
6576bffe 3825 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
c19d1205 3826
fe56b6ce 3827 /* ARM V6 instructions. */
823d2571 3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3829 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
823d2571 3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3831 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3833 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
823d2571 3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3835 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3837 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
823d2571
TG		 3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3841 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3843 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
823d2571 3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3845 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3847 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
823d2571
TG		 3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3931 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3933 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3935 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3939 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3941 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3943 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3947 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3949 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3951 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3955 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3957 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3959 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3963 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3965 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3967 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3971 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3973 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3975 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3979 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3981 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3983 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3987 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3989 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3991 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3995 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3997 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3999 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4003 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4005 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4007 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4011 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4013 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4015 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
823d2571
TG		 4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4019 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4021 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4023 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4027 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
823d2571
TG		 4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4047 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4049 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
823d2571 4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4051 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4053 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4055 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
823d2571
TG		 4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4065 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
823d2571 4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4067 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4069 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4071 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
c19d1205 4072
8f06b2d8 4073 /* V5J instruction. */
823d2571
TG		 4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 4076
8f06b2d8 4077 /* V5 Instructions. */
823d2571
TG		 4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079 0xe1200070, 0xfff000f0,
6576bffe 4080 "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
823d2571
TG		 4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082 0xfa000000, 0xfe000000, "blx\t%B"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088 /* V5E "El Segundo" Instructions. */
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094 0xf450f000, 0xfc70f000, "pld\t%a"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4140
8f06b2d8 4141 /* ARM Instructions. */
823d2571 4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 4143 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
823d2571
TG		 4144
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4247 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4249 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4251 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4252
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 4306 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
823d2571
TG		 4307
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349 0x092d0000, 0x0fff0000, "push%c\t%m"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4398
4399 /* The rest. */
4ab90a7a 4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 4401 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404 {ARM_FEATURE_CORE_LOW (0),
4405 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4406};
4407
4408/* print_insn_thumb16 recognizes the following format control codes:
4409
4410 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4411 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4412 %<bitfield>I print bitfield as a signed decimal
4413 (top bit of range being the sign bit)
4414 %N print Thumb register mask (with LR)
4415 %O print Thumb register mask (with PC)
4416 %M print Thumb register mask
4417 %b print CZB's 6-bit unsigned branch destination
4418 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4419 %c print the condition code
4420 %C print the condition code, or "s" if not conditional
4421 %x print warning if conditional an not at end of IT block"
8cb6e175 4422 %X print "\t@ unpredictable <IT:code>" if conditional
c22aaad1 4423 %I print IT instruction suffix and operands
4547cb56 4424 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4425 %<bitfield>r print bitfield as an ARM register
4426 %<bitfield>d print bitfield as a decimal
4427 %<bitfield>H print (bitfield * 2) as a decimal
4428 %<bitfield>W print (bitfield * 4) as a decimal
4429 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4430 %<bitfield>B print Thumb branch destination (signed displacement)
4431 %<bitfield>c print bitfield as a condition code
4432 %<bitnum>'c print specified char iff bit is one
4433 %<bitnum>?ab print a if bit is one else print b. */
4434
4435static const struct opcode16 thumb_opcodes[] =
4436{
4437 /* Thumb instructions. */
4438
16a1fa25
TP		 4439 /* ARMv8-M Security Extensions instructions. */
4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4442
53c4b28b 4443 /* ARM V8 instructions. */
823d2571
TG		 4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
6576bffe 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
53c4b28b 4447
8f06b2d8 4448 /* ARM V6K no-argument instructions. */
823d2571
TG		 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4455
4456 /* ARM V6T2 instructions. */
ff8646ee
TP		 4457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4462
4463 /* ARM V6. */
6576bffe
AB		 4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
823d2571
TG		 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
6576bffe 4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
823d2571
TG		 4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4475
4476 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4479 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4482 /* ARM V4T ISA (Thumb v1). */
823d2571 4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
8cb6e175 4484 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
8f06b2d8 4485 /* Format 4. */
823d2571
TG		 4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4502 /* format 13 */
6576bffe
AB		 4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
8f06b2d8 4505 /* format 5 */
823d2571
TG		 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4510 /* format 14 */
823d2571
TG		 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4513 /* format 2 */
823d2571
TG		 4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4519 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
823d2571 4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4521 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
8f06b2d8 4522 /* format 8 */
823d2571
TG		 4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4529 /* format 7 */
823d2571
TG		 4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4534 /* format 1 */
823d2571
TG		 4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4537 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
823d2571
TG		 4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4540 /* format 3 */
6576bffe
AB		 4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
8f06b2d8 4545 /* format 6 */
823d2571
TG		 4546 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548 0x4800, 0xF800,
6576bffe 4549 "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
8f06b2d8 4550 /* format 9 */
823d2571 4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4552 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4554 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4556 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
823d2571 4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4558 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
8f06b2d8 4559 /* format 10 */
823d2571 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4561 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
823d2571 4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4563 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
8f06b2d8 4564 /* format 11 */
823d2571 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4566 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
823d2571 4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4568 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
8f06b2d8 4569 /* format 12 */
823d2571 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4571 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
823d2571 4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4573 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
8f06b2d8 4574 /* format 15 */
823d2571
TG		 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4577 /* format 17 */
823d2571 4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4579 /* format 16 */
6576bffe 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
823d2571
TG		 4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4583 /* format 18 */
823d2571 4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4585
4586 /* The E800 .. FFFF range is unconditionally redirected to the
4587 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588 are processed via that table. Thus, we can never encounter a
4589 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4592};
4593
4594/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595 We adopt the convention that hw1 is the high 16 bits of .value and
4596 .mask, hw2 the low 16 bits.
4597
4598 print_insn_thumb32 recognizes the following format control codes:
4599
4600 %% %
4601
4602 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603 %M print a modified 12-bit immediate (same location)
4604 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4606 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4607 %S print a possibly-shifted Rm
4608
32a94698 4609 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4610 %a print the address of a plain load/store
4611 %w print the width and signedness of a core load/store
4612 %m print register mask for ldm/stm
4b5a202f 4613 %n print register mask for clrm
8f06b2d8
PB		 4614
4615 %E print the lsb and width fields of a bfc/bfi instruction
4616 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4617 %G print a fallback offset for Branch Future instructions
e5d6e09e 4618 %W print an offset for BF instruction
1caf72a5 4619 %Y print an offset for BFL instruction
1889da70 4620 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4621 %Q print an offset for Low Overhead Loop instructions
4622 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4623 %b print a conditional branch offset
4624 %B print an unconditional branch offset
4625 %s print the shift field of an SSAT instruction
4626 %R print the rotation field of an SXT instruction
62b3e311
PB		 4627 %U print barrier type.
4628 %P print address for pli instruction.
c22aaad1
PB		 4629 %c print the condition code
4630 %x print warning if conditional an not at end of IT block"
8cb6e175 4631 %X print "\t@ unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4632
4633 %<bitfield>d print bitfield in decimal
f0fba320 4634 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4635 %<bitfield>W print bitfield*4 in decimal
4636 %<bitfield>r print bitfield as an ARM register
dd5181d5 4637 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4638 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4639 %<bitfield>c print bitfield as a condition code
4640
16980d0b
JB		 4641 %<bitfield>'c print specified char iff bitfield is all ones
4642 %<bitfield>`c print specified char iff bitfield is all zeroes
4643 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4644
4645 With one exception at the bottom (done because BL and BLX(1) need
4646 to come dead last), this table was machine-sorted first in
4647 decreasing order of number of bits set in the mask, then in
4648 increasing numeric order of mask, then in increasing numeric order
4649 of opcode. This order is not the clearest for a human reader, but
4650 is guaranteed never to catch a special-case bit pattern with a more
4651 general mask, which is important, because this instruction encoding
4652 makes heavy use of special-case bit patterns. */
4653static const struct opcode32 thumb32_opcodes[] =
4654{
3751264c
AC		 4655 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4656 Identification Extension. */
e43ca2cb 4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4658 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
be05908c
AC		 4659 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4660 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
3751264c
AC		 4661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4662 0xf3af800f, 0xffffffff, "bti"},
e07352fa
AC		 4663 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4664 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
ce537a7d 4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4666 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
f1e1d7f3 4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4668 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
5c43020d
AC		 4669 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4670 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
3751264c 4671
4b5a202f
AV		 4672 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4673 instructions. */
60f993ce 4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4675 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677 0xf02fc001, 0xfffff001, "le\t%P"},
4678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4679 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
d052b9b7 4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4681 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
d052b9b7 4682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4683 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4685 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4687 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
d052b9b7 4688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4689 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
60f993ce 4690
4389b29a
AV		 4691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4692 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4694 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4696 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4698 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d 4699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4700 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4389b29a 4701
4b5a202f
AV		 4702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4703 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4704
16a1fa25
TP		 4705 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4708 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4710 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4712 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4713 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4714 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4715
105bde57 4716 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4717 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4718 0xf3af8010, 0xffffffff, "esb"},
4719
53c4b28b 4720 /* V8 instructions. */
823d2571
TG		 4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722 0xf3af8005, 0xffffffff, "sevl%c.w"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4738 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4740 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4742 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4744 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4746 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4748 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4750 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4752 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4753
26417f19
AC		 4754 /* V8-R instructions. */
4755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4756 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4757
dd5181d5 4758 /* CRC32 instructions. */
8b301fbb 4759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4760 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4762 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4764 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4766 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4768 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4769 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4770 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4771
c597cc3d
SD		 4772 /* Speculation Barriers. */
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4776
62b3e311 4777 /* V7 instructions. */
823d2571 4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
6576bffe 4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4786 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4788 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4789
90ec0d68 4790 /* Virtualization Extension instructions. */
823d2571 4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4792 /* We skip ERET as that is SUBS pc, lr, #0. */
4793
60e5ef9f 4794 /* MP Extension instructions. */
823d2571 4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4796
f4c65163 4797 /* Security extension instructions. */
823d2571 4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4799
7fadb25d
SD		 4800 /* ARMv8.5-A instructions. */
4801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4802
8f06b2d8 4803 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4810 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
823d2571
TG		 4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4812
ff8646ee 4813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4814 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4816 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571 4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4818 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571
TG		 4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4828 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
823d2571
TG		 4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4832 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
823d2571 4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4834 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4836 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4838 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
823d2571
TG		 4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4842 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4844 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4846 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4848 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571
TG		 4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4862 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4970 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4972 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
823d2571 4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4974 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
823d2571
TG		 4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 5037 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 5038 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044 0xf810f000, 0xff70f000, "pld%c\t%a"},
5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5060 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5062 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5068 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5070 0xfb100000, 0xfff000c0,
5071 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5073 0xfbc00080, 0xfff000c0,
5074 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5076 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5078 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 5080 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
823d2571 5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 5082 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
823d2571
TG		 5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5084 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5086 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5088 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5089 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5090 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5092 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5100 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5102 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5110 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 5112 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5128 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5130 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5134 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5136 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5140 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5142 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5144 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5146 0xe9400000, 0xff500000,
6576bffe 5147 "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 5148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5149 0xe9500000, 0xff500000,
6576bffe 5150 "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 5151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5152 0xe8600000, 0xff700000,
6576bffe 5153 "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 5154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5155 0xe8700000, 0xff700000,
6576bffe 5156 "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 5157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5158 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5160 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5161
5162 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5164 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5166 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5168 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5170 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5171
8f06b2d8 5172 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5174 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5176 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5177
5178 /* Fallback. */
823d2571
TG		 5179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5180 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5181 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5182};
ff4a8d2b 5183
8f06b2d8
PB		 5184static const char *const arm_conditional[] =
5185{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5186 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5187
5188static const char *const arm_fp_const[] =
5189{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5190
5191static const char *const arm_shift[] =
5192{"lsl", "lsr", "asr", "ror"};
5193
5194typedef struct
5195{
5196 const char *name;
5197 const char *description;
5198 const char *reg_names[16];
5199}
5200arm_regname;
5201
5202static const arm_regname regnames[] =
5203{
65b48a81 5204 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5205 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5206 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5207 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5208 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5209 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5210 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5211 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5212 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5213 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5214 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5215 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5216 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5217 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5218 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5219};
5220
5221static const char *const iwmmxt_wwnames[] =
5222{"b", "h", "w", "d"};
5223
5224static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5225{"b", "bus", "bc", "bss",
5226 "h", "hus", "hc", "hss",
5227 "w", "wus", "wc", "wss",
5228 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5229};
5230
5231static const char *const iwmmxt_regnames[] =
5232{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5233 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5234};
5235
5236static const char *const iwmmxt_cregnames[] =
5237{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5238 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5239};
5240
143275ea
AV		 5241static const char *const vec_condnames[] =
5242{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5243};
5244
5245static const char *const mve_predicatenames[] =
5246{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5247 "eee", "ee", "eet", "e", "ett", "et", "ete"
5248};
5249
5250/* Names for 2-bit size field for mve vector isntructions. */
5251static const char *const mve_vec_sizename[] =
5252 { "8", "16", "32", "64"};
5253
5254/* Indicates whether we are processing a then predicate,
5255 else predicate or none at all. */
5256enum vpt_pred_state
5257{
5258 PRED_NONE,
5259 PRED_THEN,
5260 PRED_ELSE
5261};
5262
5263/* Information used to process a vpt block and subsequent instructions. */
5264struct vpt_block
5265{
5266 /* Are we in a vpt block. */
78933a4a 5267 bool in_vpt_block;
143275ea
AV		 5268
5269 /* Next predicate state if in vpt block. */
5270 enum vpt_pred_state next_pred_state;
5271
5272 /* Mask from vpt/vpst instruction. */
5273 long predicate_mask;
5274
5275 /* Instruction number in vpt block. */
5276 long current_insn_num;
5277
5278 /* Number of instructions in vpt block.. */
5279 long num_pred_insn;
5280};
5281
5282static struct vpt_block vpt_block_state =
5283{
78933a4a 5284 false,
143275ea
AV		 5285 PRED_NONE,
5286 0,
5287 0,
5288 0
5289};
5290
8f06b2d8
PB		 5291/* Default to GCC register name set. */
5292static unsigned int regname_selected = 1;
5293
65b48a81 5294#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5295#define arm_regnames regnames[regname_selected].reg_names
5296
78933a4a 5297static bool force_thumb = false;
4934a27c 5298static uint16_t cde_coprocs = 0;
8f06b2d8 5299
c22aaad1
PB		 5300/* Current IT instruction state. This contains the same state as the IT
5301 bits in the CPSR. */
5302static unsigned int ifthen_state;
5303/* IT state for the next instruction. */
5304static unsigned int ifthen_next_state;
5305/* The address of the insn for which the IT state is valid. */
5306static bfd_vma ifthen_address;
5307#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5308/* Indicates that the current Conditional state is unconditional or outside
5309 an IT block. */
5310#define COND_UNCOND 16
c22aaad1 5311
8f06b2d8
PB		 5312\f
5313/* Functions. */
143275ea
AV		 5314/* Extract the predicate mask for a VPT or VPST instruction.
5315 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5316
5317static long
5318mve_extract_pred_mask (long given)
5319{
5320 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5321}
5322
5323/* Return the number of instructions in a MVE predicate block. */
5324static long
5325num_instructions_vpt_block (long given)
5326{
5327 long mask = mve_extract_pred_mask (given);
5328 if (mask == 0)
5329 return 0;
5330
5331 if (mask == 8)
5332 return 1;
5333
5334 if ((mask & 7) == 4)
5335 return 2;
5336
5337 if ((mask & 3) == 2)
5338 return 3;
5339
5340 if ((mask & 1) == 1)
5341 return 4;
5342
5343 return 0;
5344}
5345
5346static void
5347mark_outside_vpt_block (void)
5348{
78933a4a 5349 vpt_block_state.in_vpt_block = false;
143275ea
AV		 5350 vpt_block_state.next_pred_state = PRED_NONE;
5351 vpt_block_state.predicate_mask = 0;
5352 vpt_block_state.current_insn_num = 0;
5353 vpt_block_state.num_pred_insn = 0;
5354}
5355
5356static void
5357mark_inside_vpt_block (long given)
5358{
78933a4a 5359 vpt_block_state.in_vpt_block = true;
143275ea
AV		 5360 vpt_block_state.next_pred_state = PRED_THEN;
5361 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5362 vpt_block_state.current_insn_num = 0;
5363 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5364 assert (vpt_block_state.num_pred_insn >= 1);
5365}
5366
5367static enum vpt_pred_state
5368invert_next_predicate_state (enum vpt_pred_state astate)
5369{
5370 if (astate == PRED_THEN)
5371 return PRED_ELSE;
5372 else if (astate == PRED_ELSE)
5373 return PRED_THEN;
5374 else
5375 return PRED_NONE;
5376}
5377
5378static enum vpt_pred_state
5379update_next_predicate_state (void)
5380{
5381 long pred_mask = vpt_block_state.predicate_mask;
5382 long mask_for_insn = 0;
5383
5384 switch (vpt_block_state.current_insn_num)
5385 {
5386 case 1:
5387 mask_for_insn = 8;
5388 break;
5389
5390 case 2:
5391 mask_for_insn = 4;
5392 break;
5393
5394 case 3:
5395 mask_for_insn = 2;
5396 break;
5397
5398 case 4:
5399 return PRED_NONE;
5400 }
5401
5402 if (pred_mask & mask_for_insn)
5403 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5404 else
5405 return vpt_block_state.next_pred_state;
5406}
5407
5408static void
5409update_vpt_block_state (void)
5410{
5411 vpt_block_state.current_insn_num++;
5412 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5413 {
5414 /* No more instructions to process in vpt block. */
5415 mark_outside_vpt_block ();
5416 return;
5417 }
5418
5419 vpt_block_state.next_pred_state = update_next_predicate_state ();
5420}
8f06b2d8 5421
16980d0b
JB		 5422/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5423 Returns pointer to following character of the format string and
5424 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5425 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5426
5427static const char *
fe56b6ce
NC		 5428arm_decode_bitfield (const char *ptr,
5429 unsigned long insn,
5430 unsigned long *valuep,
5431 int *widthp)
16980d0b
JB		 5432{
5433 unsigned long value = 0;
5434 int width = 0;
43e65147
L		 5435
5436 do
16980d0b
JB		 5437 {
5438 int start, end;
5439 int bits;
5440
5441 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5442 start = start * 10 + *ptr - '0';
5443 if (*ptr == '-')
5444 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5445 end = end * 10 + *ptr - '0';
5446 else
5447 end = start;
5448 bits = end - start;
5449 if (bits < 0)
5450 abort ();
5451 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5452 width += bits + 1;
5453 }
5454 while (*ptr++ == ',');
5455 *valuep = value;
5456 if (widthp)
5457 *widthp = width;
5458 return ptr - 1;
5459}
5460
8f06b2d8 5461static void
6576bffe 5462arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
78933a4a 5463 bool print_shift)
8f06b2d8 5464{
6576bffe 5465 func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
8f06b2d8
PB		 5466
5467 if ((given & 0xff0) != 0)
5468 {
5469 if ((given & 0x10) == 0)
5470 {
5471 int amount = (given & 0xf80) >> 7;
5472 int shift = (given & 0x60) >> 5;
5473
5474 if (amount == 0)
5475 {
5476 if (shift == 3)
5477 {
6576bffe
AB		 5478 func (stream, dis_style_text, ", ");
5479 func (stream, dis_style_sub_mnemonic, "rrx");
8f06b2d8
PB		 5480 return;
5481 }
5482
5483 amount = 32;
5484 }
5485
37b37b2d 5486 if (print_shift)
6576bffe
AB		 5487 {
5488 func (stream, dis_style_text, ", ");
5489 func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5490 func (stream, dis_style_immediate, "#%d", amount);
5491 }
37b37b2d 5492 else
6576bffe
AB		 5493 {
5494 func (stream, dis_style_text, ", ");
5495 func (stream, dis_style_immediate, "#%d", amount);
5496 }
8f06b2d8 5497 }
74bdfecf 5498 else if ((given & 0x80) == 0x80)
6576bffe
AB		 5499 func (stream, dis_style_comment_start,
5500 "\t@ <illegal shifter operand>");
37b37b2d 5501 else if (print_shift)
6576bffe
AB		 5502 {
5503 func (stream, dis_style_text, ", ");
5504 func (stream, dis_style_sub_mnemonic, "%s ",
5505 arm_shift[(given & 0x60) >> 5]);
5506 func (stream, dis_style_register, "%s",
5507 arm_regnames[(given & 0xf00) >> 8]);
5508 }
37b37b2d 5509 else
6576bffe
AB		 5510 {
5511 func (stream, dis_style_text, ", ");
5512 func (stream, dis_style_register, "%s",
5513 arm_regnames[(given & 0xf00) >> 8]);
5514 }
8f06b2d8
PB		 5515 }
5516}
5517
73cd51e5
AV		 5518/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5519
78933a4a 5520static bool
73cd51e5
AV		 5521is_mve_okay_in_it (enum mve_instructions matched_insn)
5522{
c507f10b
AV		 5523 switch (matched_insn)
5524 {
5525 case MVE_VMOV_GP_TO_VEC_LANE:
5526 case MVE_VMOV2_VEC_LANE_TO_GP:
5527 case MVE_VMOV2_GP_TO_VEC_LANE:
5528 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5529 case MVE_LSLL:
5530 case MVE_LSLLI:
5531 case MVE_LSRL:
5532 case MVE_ASRL:
5533 case MVE_ASRLI:
5534 case MVE_SQRSHRL:
5535 case MVE_SQRSHR:
5536 case MVE_UQRSHL:
5537 case MVE_UQRSHLL:
5538 case MVE_UQSHL:
5539 case MVE_UQSHLL:
5540 case MVE_URSHRL:
5541 case MVE_URSHR:
5542 case MVE_SRSHRL:
5543 case MVE_SRSHR:
5544 case MVE_SQSHLL:
5545 case MVE_SQSHL:
78933a4a 5546 return true;
c507f10b 5547 default:
78933a4a 5548 return false;
c507f10b 5549 }
73cd51e5
AV		 5550}
5551
78933a4a 5552static bool
73cd51e5
AV		 5553is_mve_architecture (struct disassemble_info *info)
5554{
5555 struct arm_private_data *private_data = info->private_data;
5556 arm_feature_set allowed_arches = private_data->features;
5557
5558 arm_feature_set arm_ext_v8_1m_main
5559 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5560
5561 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5562 && !ARM_CPU_IS_ANY (allowed_arches))
78933a4a 5563 return true;
73cd51e5 5564 else
78933a4a 5565 return false;
73cd51e5
AV		 5566}
5567
78933a4a 5568static bool
143275ea
AV		 5569is_vpt_instruction (long given)
5570{
5571
5572 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5573 if ((given & 0x0040e000) == 0)
78933a4a 5574 return false;
143275ea
AV		 5575
5576 /* VPT floating point T1 variant. */
5577 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5578 /* VPT floating point T2 variant. */
5579 || ((given & 0xefb10f50) == 0xee310f40)
5580 /* VPT vector T1 variant. */
5581 || ((given & 0xff811f51) == 0xfe010f00)
5582 /* VPT vector T2 variant. */
5583 || ((given & 0xff811f51) == 0xfe010f01
5584 && ((given & 0x300000) != 0x300000))
5585 /* VPT vector T3 variant. */
5586 || ((given & 0xff811f50) == 0xfe011f00)
5587 /* VPT vector T4 variant. */
5588 || ((given & 0xff811f70) == 0xfe010f40)
5589 /* VPT vector T5 variant. */
5590 || ((given & 0xff811f70) == 0xfe010f60)
5591 /* VPT vector T6 variant. */
5592 || ((given & 0xff811f50) == 0xfe011f40)
5593 /* VPST vector T variant. */
5594 || ((given & 0xffbf1fff) == 0xfe310f4d))
78933a4a 5595 return true;
143275ea 5596 else
78933a4a 5597 return false;
143275ea
AV		 5598}
5599
73cd51e5
AV		 5600/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5601 and ending bitfield = END. END must be greater than START. */
5602
5603static unsigned long
5604arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5605{
5606 int bits = end - start;
5607
5608 if (bits < 0)
5609 abort ();
5610
5611 return ((given >> start) & ((2ul << bits) - 1));
5612}
5613
5614/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5615 START:END and START2:END2. END/END2 must be greater than
5616 START/START2. */
5617
5618static unsigned long
5619arm_decode_field_multiple (unsigned long given, unsigned int start,
5620 unsigned int end, unsigned int start2,
5621 unsigned int end2)
5622{
5623 int bits = end - start;
5624 int bits2 = end2 - start2;
5625 unsigned long value = 0;
5626 int width = 0;
5627
5628 if (bits2 < 0)
5629 abort ();
5630
5631 value = arm_decode_field (given, start, end);
5632 width += bits + 1;
5633
5634 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5635 return value;
5636}
5637
5638/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5639 This helps us decode instructions that change mnemonic depending on specific
5640 operand values/encodings. */
5641
78933a4a 5642static bool
73cd51e5
AV		 5643is_mve_encoding_conflict (unsigned long given,
5644 enum mve_instructions matched_insn)
5645{
143275ea
AV		 5646 switch (matched_insn)
5647 {
5648 case MVE_VPST:
5649 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5650 return true;
143275ea 5651 else
78933a4a 5652 return false;
143275ea
AV		 5653
5654 case MVE_VPT_FP_T1:
5655 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5656 return true;
143275ea
AV		 5657 if ((arm_decode_field (given, 12, 12) == 0)
5658 && (arm_decode_field (given, 0, 0) == 1))
78933a4a
AM		 5659 return true;
5660 return false;
143275ea
AV		 5661
5662 case MVE_VPT_FP_T2:
5663 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5664 return true;
143275ea 5665 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a
AM		 5666 return true;
5667 return false;
143275ea
AV		 5668
5669 case MVE_VPT_VEC_T1:
5670 case MVE_VPT_VEC_T2:
5671 case MVE_VPT_VEC_T3:
5672 case MVE_VPT_VEC_T4:
5673 case MVE_VPT_VEC_T5:
5674 case MVE_VPT_VEC_T6:
5675 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5676 return true;
143275ea 5677 if (arm_decode_field (given, 20, 21) == 3)
78933a4a
AM		 5678 return true;
5679 return false;
143275ea
AV		 5680
5681 case MVE_VCMP_FP_T1:
5682 if ((arm_decode_field (given, 12, 12) == 0)
5683 && (arm_decode_field (given, 0, 0) == 1))
78933a4a 5684 return true;
143275ea 5685 else
78933a4a 5686 return false;
143275ea
AV		 5687
5688 case MVE_VCMP_FP_T2:
5689 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5690 return true;
143275ea 5691 else
78933a4a 5692 return false;
143275ea 5693
14b456f2
AV		 5694 case MVE_VQADD_T2:
5695 case MVE_VQSUB_T2:
f49bb598
AV		 5696 case MVE_VMUL_VEC_T2:
5697 case MVE_VMULH:
5698 case MVE_VRMULH:
56858bea
AV		 5699 case MVE_VMLA:
5700 case MVE_VMAX:
5701 case MVE_VMIN:
e523f101 5702 case MVE_VBRSR:
66dcaa5d
AV		 5703 case MVE_VADD_VEC_T2:
5704 case MVE_VSUB_VEC_T2:
5705 case MVE_VABAV:
ed63aa17
AV		 5706 case MVE_VQRSHL_T1:
5707 case MVE_VQSHL_T4:
5708 case MVE_VRSHL_T1:
5709 case MVE_VSHL_T3:
897b9bbc
AV		 5710 case MVE_VCADD_VEC:
5711 case MVE_VHCADD:
1c8f2df8
AV		 5712 case MVE_VDDUP:
5713 case MVE_VIDUP:
d3b63143
AV		 5714 case MVE_VQRDMLADH:
5715 case MVE_VQDMLAH:
5716 case MVE_VQRDMLAH:
5717 case MVE_VQDMLASH:
5718 case MVE_VQRDMLASH:
5719 case MVE_VQDMLSDH:
5720 case MVE_VQRDMLSDH:
5721 case MVE_VQDMULH_T3:
5722 case MVE_VQRDMULH_T4:
5723 case MVE_VQDMLADH:
5724 case MVE_VMLAS:
14925797 5725 case MVE_VMULL_INT:
9743db03
AV		 5726 case MVE_VHADD_T2:
5727 case MVE_VHSUB_T2:
143275ea
AV		 5728 case MVE_VCMP_VEC_T1:
5729 case MVE_VCMP_VEC_T2:
5730 case MVE_VCMP_VEC_T3:
5731 case MVE_VCMP_VEC_T4:
5732 case MVE_VCMP_VEC_T5:
5733 case MVE_VCMP_VEC_T6:
5734 if (arm_decode_field (given, 20, 21) == 3)
78933a4a 5735 return true;
143275ea 5736 else
78933a4a 5737 return false;
143275ea 5738
04d54ace
AV		 5739 case MVE_VLD2:
5740 case MVE_VLD4:
5741 case MVE_VST2:
5742 case MVE_VST4:
5743 if (arm_decode_field (given, 7, 8) == 3)
78933a4a 5744 return true;
04d54ace 5745 else
78933a4a 5746 return false;
04d54ace 5747
aef6d006
AV		 5748 case MVE_VSTRB_T1:
5749 case MVE_VSTRH_T2:
5750 if ((arm_decode_field (given, 24, 24) == 0)
5751 && (arm_decode_field (given, 21, 21) == 0))
5752 {
78933a4a 5753 return true;
aef6d006
AV		 5754 }
5755 else if ((arm_decode_field (given, 7, 8) == 3))
78933a4a 5756 return true;
aef6d006 5757 else
78933a4a 5758 return false;
aef6d006 5759
e683cb41
AC		 5760 case MVE_VLDRB_T1:
5761 case MVE_VLDRH_T2:
5762 case MVE_VLDRW_T7:
aef6d006
AV		 5763 case MVE_VSTRB_T5:
5764 case MVE_VSTRH_T6:
5765 case MVE_VSTRW_T7:
5766 if ((arm_decode_field (given, 24, 24) == 0)
5767 && (arm_decode_field (given, 21, 21) == 0))
5768 {
78933a4a 5769 return true;
aef6d006
AV		 5770 }
5771 else
78933a4a 5772 return false;
aef6d006 5773
bf0b396d
AV		 5774 case MVE_VCVT_FP_FIX_VEC:
5775 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5776
c507f10b
AV		 5777 case MVE_VBIC_IMM:
5778 case MVE_VORR_IMM:
5779 {
5780 unsigned long cmode = arm_decode_field (given, 8, 11);
5781
5782 if ((cmode & 1) == 0)
78933a4a 5783 return true;
c507f10b 5784 else if ((cmode & 0xc) == 0xc)
78933a4a 5785 return true;
c507f10b 5786 else
78933a4a 5787 return false;
c507f10b
AV		 5788 }
5789
5790 case MVE_VMVN_IMM:
5791 {
5792 unsigned long cmode = arm_decode_field (given, 8, 11);
5793
ce760a76 5794 if (cmode == 0xe)
78933a4a 5795 return true;
ce760a76 5796 else if ((cmode & 0x9) == 1)
78933a4a 5797 return true;
ce760a76 5798 else if ((cmode & 0xd) == 9)
78933a4a 5799 return true;
c507f10b 5800 else
78933a4a 5801 return false;
c507f10b
AV		 5802 }
5803
5804 case MVE_VMOV_IMM_TO_VEC:
5805 if ((arm_decode_field (given, 5, 5) == 1)
5806 && (arm_decode_field (given, 8, 11) != 0xe))
78933a4a 5807 return true;
c507f10b 5808 else
78933a4a 5809 return false;
c507f10b 5810
14925797
AV		 5811 case MVE_VMOVL:
5812 {
5813 unsigned long size = arm_decode_field (given, 19, 20);
5814 if ((size == 0) || (size == 3))
78933a4a 5815 return true;
14925797 5816 else
78933a4a 5817 return false;
14925797
AV		 5818 }
5819
56858bea
AV		 5820 case MVE_VMAXA:
5821 case MVE_VMINA:
5822 case MVE_VMAXV:
5823 case MVE_VMAXAV:
5824 case MVE_VMINV:
5825 case MVE_VMINAV:
ed63aa17
AV		 5826 case MVE_VQRSHL_T2:
5827 case MVE_VQSHL_T1:
5828 case MVE_VRSHL_T2:
5829 case MVE_VSHL_T2:
5830 case MVE_VSHLL_T2:
d3b63143 5831 case MVE_VADDV:
14925797
AV		 5832 case MVE_VMOVN:
5833 case MVE_VQMOVUN:
5834 case MVE_VQMOVN:
5835 if (arm_decode_field (given, 18, 19) == 3)
78933a4a 5836 return true;
14925797 5837 else
78933a4a 5838 return false;
14925797 5839
d3b63143
AV		 5840 case MVE_VMLSLDAV:
5841 case MVE_VRMLSLDAVH:
5842 case MVE_VMLALDAV:
5843 case MVE_VADDLV:
5844 if (arm_decode_field (given, 20, 22) == 7)
78933a4a 5845 return true;
d3b63143 5846 else
78933a4a 5847 return false;
d3b63143
AV		 5848
5849 case MVE_VRMLALDAVH:
5850 if ((arm_decode_field (given, 20, 22) & 6) == 6)
78933a4a 5851 return true;
d3b63143 5852 else
78933a4a 5853 return false;
d3b63143 5854
1c8f2df8
AV		 5855 case MVE_VDWDUP:
5856 case MVE_VIWDUP:
5857 if ((arm_decode_field (given, 20, 21) == 3)
5858 || (arm_decode_field (given, 1, 3) == 7))
78933a4a 5859 return true;
1c8f2df8 5860 else
78933a4a 5861 return false;
1c8f2df8 5862
ed63aa17
AV		 5863
5864 case MVE_VSHLL_T1:
5865 if (arm_decode_field (given, 16, 18) == 0)
5866 {
5867 unsigned long sz = arm_decode_field (given, 19, 20);
5868
5869 if ((sz == 1) || (sz == 2))
78933a4a 5870 return true;
ed63aa17 5871 else
78933a4a 5872 return false;
ed63aa17
AV		 5873 }
5874 else
78933a4a 5875 return false;
ed63aa17
AV		 5876
5877 case MVE_VQSHL_T2:
5878 case MVE_VQSHLU_T3:
5879 case MVE_VRSHR:
5880 case MVE_VSHL_T1:
5881 case MVE_VSHR:
5882 case MVE_VSLI:
5883 case MVE_VSRI:
5884 if (arm_decode_field (given, 19, 21) == 0)
78933a4a 5885 return true;
ed63aa17 5886 else
78933a4a 5887 return false;
ed63aa17 5888
e523f101
AV		 5889 case MVE_VCTP:
5890 if (arm_decode_field (given, 16, 19) == 0xf)
78933a4a 5891 return true;
e523f101 5892 else
78933a4a 5893 return false;
e523f101 5894
23d00a41
SD		 5895 case MVE_ASRLI:
5896 case MVE_ASRL:
5897 case MVE_LSLLI:
5898 case MVE_LSLL:
5899 case MVE_LSRL:
5900 case MVE_SQRSHRL:
5901 case MVE_SQSHLL:
5902 case MVE_SRSHRL:
5903 case MVE_UQRSHLL:
5904 case MVE_UQSHLL:
5905 case MVE_URSHRL:
5906 if (arm_decode_field (given, 9, 11) == 0x7)
78933a4a 5907 return true;
23d00a41 5908 else
78933a4a 5909 return false;
23d00a41 5910
e39c1607
SD		 5911 case MVE_CSINC:
5912 case MVE_CSINV:
5913 {
5914 unsigned long rm, rn;
5915 rm = arm_decode_field (given, 0, 3);
5916 rn = arm_decode_field (given, 16, 19);
5917 /* CSET/CSETM. */
5918 if (rm == 0xf && rn == 0xf)
78933a4a 5919 return true;
e39c1607
SD		 5920 /* CINC/CINV. */
5921 else if (rn == rm && rn != 0xf)
78933a4a 5922 return true;
e39c1607
SD		 5923 }
5924 /* Fall through. */
5925 case MVE_CSEL:
5926 case MVE_CSNEG:
5927 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5928 return true;
e39c1607
SD		 5929 /* CNEG. */
5930 else if (matched_insn == MVE_CSNEG)
5931 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
78933a4a
AM		 5932 return true;
5933 return false;
e39c1607 5934
143275ea 5935 default:
66dcaa5d
AV		 5936 case MVE_VADD_FP_T1:
5937 case MVE_VADD_FP_T2:
5938 case MVE_VADD_VEC_T1:
78933a4a 5939 return false;
143275ea
AV		 5940
5941 }
73cd51e5
AV		 5942}
5943
aef6d006
AV		 5944static void
5945print_mve_vld_str_addr (struct disassemble_info *info,
5946 unsigned long given,
5947 enum mve_instructions matched_insn)
5948{
5949 void *stream = info->stream;
6576bffe 5950 fprintf_styled_ftype func = info->fprintf_styled_func;
aef6d006
AV		 5951
5952 unsigned long p, w, gpr, imm, add, mod_imm;
5953
5954 imm = arm_decode_field (given, 0, 6);
5955 mod_imm = imm;
5956
5957 switch (matched_insn)
5958 {
5959 case MVE_VLDRB_T1:
5960 case MVE_VSTRB_T1:
5961 gpr = arm_decode_field (given, 16, 18);
5962 break;
5963
5964 case MVE_VLDRH_T2:
5965 case MVE_VSTRH_T2:
5966 gpr = arm_decode_field (given, 16, 18);
5967 mod_imm = imm << 1;
5968 break;
5969
5970 case MVE_VLDRH_T6:
5971 case MVE_VSTRH_T6:
5972 gpr = arm_decode_field (given, 16, 19);
5973 mod_imm = imm << 1;
5974 break;
5975
5976 case MVE_VLDRW_T7:
5977 case MVE_VSTRW_T7:
5978 gpr = arm_decode_field (given, 16, 19);
5979 mod_imm = imm << 2;
5980 break;
5981
5982 case MVE_VLDRB_T5:
5983 case MVE_VSTRB_T5:
5984 gpr = arm_decode_field (given, 16, 19);
5985 break;
5986
5987 default:
5988 return;
5989 }
5990
5991 p = arm_decode_field (given, 24, 24);
5992 w = arm_decode_field (given, 21, 21);
5993
5994 add = arm_decode_field (given, 23, 23);
5995
5996 char * add_sub;
5997
5998 /* Don't print anything for '+' as it is implied. */
5999 if (add == 1)
6000 add_sub = "";
6001 else
6002 add_sub = "-";
6003
6576bffe 6004 func (stream, dis_style_text, "[");
4575eafb 6005 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
aef6d006
AV		 6006 if (p == 1)
6007 {
6576bffe
AB		 6008 func (stream, dis_style_text, ", ");
6009 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
aef6d006
AV		 6010 /* Offset mode. */
6011 if (w == 0)
6576bffe 6012 func (stream, dis_style_text, "]");
aef6d006
AV		 6013 /* Pre-indexed mode. */
6014 else
6576bffe 6015 func (stream, dis_style_text, "]!");
aef6d006
AV		 6016 }
6017 else if ((p == 0) && (w == 1))
6576bffe
AB		 6018 {
6019 /* Post-index mode. */
6020 func (stream, dis_style_text, "], ");
6021 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
6022 }
aef6d006
AV		 6023}
6024
73cd51e5
AV		 6025/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
6026 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
6027 this encoding is undefined. */
6028
78933a4a 6029static bool
73cd51e5
AV		 6030is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
6031 enum mve_undefined *undefined_code)
6032{
6033 *undefined_code = UNDEF_NONE;
6034
9743db03
AV		 6035 switch (matched_insn)
6036 {
6037 case MVE_VDUP:
6038 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
6039 {
6040 *undefined_code = UNDEF_SIZE_3;
78933a4a 6041 return true;
9743db03
AV		 6042 }
6043 else
78933a4a 6044 return false;
9743db03 6045
14b456f2
AV		 6046 case MVE_VQADD_T1:
6047 case MVE_VQSUB_T1:
f49bb598 6048 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 6049 case MVE_VABD_VEC:
6050 case MVE_VADD_VEC_T1:
6051 case MVE_VSUB_VEC_T1:
d3b63143
AV		 6052 case MVE_VQDMULH_T1:
6053 case MVE_VQRDMULH_T2:
9743db03
AV		 6054 case MVE_VRHADD:
6055 case MVE_VHADD_T1:
6056 case MVE_VHSUB_T1:
6057 if (arm_decode_field (given, 20, 21) == 3)
6058 {
6059 *undefined_code = UNDEF_SIZE_3;
78933a4a 6060 return true;
9743db03
AV		 6061 }
6062 else
78933a4a 6063 return false;
9743db03 6064
aef6d006
AV		 6065 case MVE_VLDRB_T1:
6066 if (arm_decode_field (given, 7, 8) == 3)
6067 {
6068 *undefined_code = UNDEF_SIZE_3;
78933a4a 6069 return true;
aef6d006
AV		 6070 }
6071 else
78933a4a 6072 return false;
aef6d006
AV		 6073
6074 case MVE_VLDRH_T2:
6075 if (arm_decode_field (given, 7, 8) <= 1)
6076 {
6077 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6078 return true;
aef6d006
AV		 6079 }
6080 else
78933a4a 6081 return false;
aef6d006
AV		 6082
6083 case MVE_VSTRB_T1:
6084 if ((arm_decode_field (given, 7, 8) == 0))
6085 {
6086 *undefined_code = UNDEF_SIZE_0;
78933a4a 6087 return true;
aef6d006
AV		 6088 }
6089 else
78933a4a 6090 return false;
aef6d006
AV		 6091
6092 case MVE_VSTRH_T2:
6093 if ((arm_decode_field (given, 7, 8) <= 1))
6094 {
6095 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6096 return true;
aef6d006
AV		 6097 }
6098 else
78933a4a 6099 return false;
aef6d006 6100
ef1576a1
AV		 6101 case MVE_VLDRB_GATHER_T1:
6102 if (arm_decode_field (given, 7, 8) == 3)
6103 {
6104 *undefined_code = UNDEF_SIZE_3;
78933a4a 6105 return true;
ef1576a1
AV		 6106 }
6107 else if ((arm_decode_field (given, 28, 28) == 0)
6108 && (arm_decode_field (given, 7, 8) == 0))
6109 {
6110 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
78933a4a 6111 return true;
ef1576a1
AV		 6112 }
6113 else
78933a4a 6114 return false;
ef1576a1
AV		 6115
6116 case MVE_VLDRH_GATHER_T2:
6117 if (arm_decode_field (given, 7, 8) == 3)
6118 {
6119 *undefined_code = UNDEF_SIZE_3;
78933a4a 6120 return true;
ef1576a1
AV		 6121 }
6122 else if ((arm_decode_field (given, 28, 28) == 0)
6123 && (arm_decode_field (given, 7, 8) == 1))
6124 {
6125 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
78933a4a 6126 return true;
ef1576a1
AV		 6127 }
6128 else if (arm_decode_field (given, 7, 8) == 0)
6129 {
6130 *undefined_code = UNDEF_SIZE_0;
78933a4a 6131 return true;
ef1576a1
AV		 6132 }
6133 else
78933a4a 6134 return false;
ef1576a1
AV		 6135
6136 case MVE_VLDRW_GATHER_T3:
6137 if (arm_decode_field (given, 7, 8) != 2)
6138 {
6139 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6140 return true;
ef1576a1
AV		 6141 }
6142 else if (arm_decode_field (given, 28, 28) == 0)
6143 {
6144 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6145 return true;
ef1576a1
AV		 6146 }
6147 else
78933a4a 6148 return false;
ef1576a1
AV		 6149
6150 case MVE_VLDRD_GATHER_T4:
6151 if (arm_decode_field (given, 7, 8) != 3)
6152 {
6153 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6154 return true;
ef1576a1
AV		 6155 }
6156 else if (arm_decode_field (given, 28, 28) == 0)
6157 {
6158 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6159 return true;
ef1576a1
AV		 6160 }
6161 else
78933a4a 6162 return false;
ef1576a1
AV		 6163
6164 case MVE_VSTRB_SCATTER_T1:
6165 if (arm_decode_field (given, 7, 8) == 3)
6166 {
6167 *undefined_code = UNDEF_SIZE_3;
78933a4a 6168 return true;
ef1576a1
AV		 6169 }
6170 else
78933a4a 6171 return false;
ef1576a1
AV		 6172
6173 case MVE_VSTRH_SCATTER_T2:
6174 {
6175 unsigned long size = arm_decode_field (given, 7, 8);
6176 if (size == 3)
6177 {
6178 *undefined_code = UNDEF_SIZE_3;
78933a4a 6179 return true;
ef1576a1
AV		 6180 }
6181 else if (size == 0)
6182 {
6183 *undefined_code = UNDEF_SIZE_0;
78933a4a 6184 return true;
ef1576a1
AV		 6185 }
6186 else
78933a4a 6187 return false;
ef1576a1
AV		 6188 }
6189
6190 case MVE_VSTRW_SCATTER_T3:
6191 if (arm_decode_field (given, 7, 8) != 2)
6192 {
6193 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6194 return true;
ef1576a1
AV		 6195 }
6196 else
78933a4a 6197 return false;
ef1576a1
AV		 6198
6199 case MVE_VSTRD_SCATTER_T4:
6200 if (arm_decode_field (given, 7, 8) != 3)
6201 {
6202 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6203 return true;
ef1576a1
AV		 6204 }
6205 else
78933a4a 6206 return false;
ef1576a1 6207
bf0b396d
AV		 6208 case MVE_VCVT_FP_FIX_VEC:
6209 {
6210 unsigned long imm6 = arm_decode_field (given, 16, 21);
6211 if ((imm6 & 0x20) == 0)
6212 {
6213 *undefined_code = UNDEF_VCVT_IMM6;
78933a4a 6214 return true;
bf0b396d
AV		 6215 }
6216
6217 if ((arm_decode_field (given, 9, 9) == 0)
6218 && ((imm6 & 0x30) == 0x20))
6219 {
6220 *undefined_code = UNDEF_VCVT_FSI_IMM6;
78933a4a 6221 return true;
bf0b396d
AV		 6222 }
6223
78933a4a 6224 return false;
bf0b396d
AV		 6225 }
6226
f49bb598 6227 case MVE_VNEG_FP:
66dcaa5d 6228 case MVE_VABS_FP:
bf0b396d
AV		 6229 case MVE_VCVT_BETWEEN_FP_INT:
6230 case MVE_VCVT_FROM_FP_TO_INT:
6231 {
6232 unsigned long size = arm_decode_field (given, 18, 19);
6233 if (size == 0)
6234 {
6235 *undefined_code = UNDEF_SIZE_0;
78933a4a 6236 return true;
bf0b396d
AV		 6237 }
6238 else if (size == 3)
6239 {
6240 *undefined_code = UNDEF_SIZE_3;
78933a4a 6241 return true;
bf0b396d
AV		 6242 }
6243 else
78933a4a 6244 return false;
bf0b396d
AV		 6245 }
6246
c507f10b
AV		 6247 case MVE_VMOV_VEC_LANE_TO_GP:
6248 {
6249 unsigned long op1 = arm_decode_field (given, 21, 22);
6250 unsigned long op2 = arm_decode_field (given, 5, 6);
6251 unsigned long u = arm_decode_field (given, 23, 23);
6252
6253 if ((op2 == 0) && (u == 1))
6254 {
6255 if ((op1 == 0) || (op1 == 1))
6256 {
6257 *undefined_code = UNDEF_BAD_U_OP1_OP2;
78933a4a 6258 return true;
c507f10b
AV		 6259 }
6260 else
78933a4a 6261 return false;
c507f10b
AV		 6262 }
6263 else if (op2 == 2)
6264 {
6265 if ((op1 == 0) || (op1 == 1))
6266 {
6267 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6268 return true;
c507f10b
AV		 6269 }
6270 else
78933a4a 6271 return false;
c507f10b
AV		 6272 }
6273
78933a4a 6274 return false;
c507f10b
AV		 6275 }
6276
6277 case MVE_VMOV_GP_TO_VEC_LANE:
6278 if (arm_decode_field (given, 5, 6) == 2)
6279 {
6280 unsigned long op1 = arm_decode_field (given, 21, 22);
6281 if ((op1 == 0) || (op1 == 1))
6282 {
6283 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6284 return true;
c507f10b
AV		 6285 }
6286 else
78933a4a 6287 return false;
c507f10b
AV		 6288 }
6289 else
78933a4a 6290 return false;
c507f10b 6291
c4a23bf8
SP		 6292 case MVE_VMOV_VEC_TO_VEC:
6293 if ((arm_decode_field (given, 5, 5) == 1)
6294 || (arm_decode_field (given, 22, 22) == 1))
78933a4a
AM		 6295 return true;
6296 return false;
c4a23bf8 6297
c507f10b
AV		 6298 case MVE_VMOV_IMM_TO_VEC:
6299 if (arm_decode_field (given, 5, 5) == 0)
6300 {
6301 unsigned long cmode = arm_decode_field (given, 8, 11);
6302
6303 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6304 {
6305 *undefined_code = UNDEF_OP_0_BAD_CMODE;
78933a4a 6306 return true;
c507f10b
AV		 6307 }
6308 else
78933a4a 6309 return false;
c507f10b
AV		 6310 }
6311 else
78933a4a 6312 return false;
c507f10b 6313
ed63aa17 6314 case MVE_VSHLL_T2:
14925797
AV		 6315 case MVE_VMOVN:
6316 if (arm_decode_field (given, 18, 19) == 2)
6317 {
6318 *undefined_code = UNDEF_SIZE_2;
78933a4a 6319 return true;
14925797
AV		 6320 }
6321 else
78933a4a 6322 return false;
14925797 6323
d3b63143
AV		 6324 case MVE_VRMLALDAVH:
6325 case MVE_VMLADAV_T1:
6326 case MVE_VMLADAV_T2:
6327 case MVE_VMLALDAV:
6328 if ((arm_decode_field (given, 28, 28) == 1)
6329 && (arm_decode_field (given, 12, 12) == 1))
6330 {
6331 *undefined_code = UNDEF_XCHG_UNS;
78933a4a 6332 return true;
d3b63143
AV		 6333 }
6334 else
78933a4a 6335 return false;
d3b63143 6336
ed63aa17
AV		 6337 case MVE_VQSHRN:
6338 case MVE_VQSHRUN:
6339 case MVE_VSHLL_T1:
6340 case MVE_VSHRN:
6341 {
6342 unsigned long sz = arm_decode_field (given, 19, 20);
6343 if (sz == 1)
78933a4a 6344 return false;
ed63aa17 6345 else if ((sz & 2) == 2)
78933a4a 6346 return false;
ed63aa17
AV		 6347 else
6348 {
6349 *undefined_code = UNDEF_SIZE;
78933a4a 6350 return true;
ed63aa17
AV		 6351 }
6352 }
6353 break;
6354
6355 case MVE_VQSHL_T2:
6356 case MVE_VQSHLU_T3:
6357 case MVE_VRSHR:
6358 case MVE_VSHL_T1:
6359 case MVE_VSHR:
6360 case MVE_VSLI:
6361 case MVE_VSRI:
6362 {
6363 unsigned long sz = arm_decode_field (given, 19, 21);
6364 if ((sz & 7) == 1)
78933a4a 6365 return false;
ed63aa17 6366 else if ((sz & 6) == 2)
78933a4a 6367 return false;
ed63aa17 6368 else if ((sz & 4) == 4)
78933a4a 6369 return false;
ed63aa17
AV		 6370 else
6371 {
6372 *undefined_code = UNDEF_SIZE;
78933a4a 6373 return true;
ed63aa17
AV		 6374 }
6375 }
6376
6377 case MVE_VQRSHRN:
6378 case MVE_VQRSHRUN:
6379 if (arm_decode_field (given, 19, 20) == 0)
6380 {
6381 *undefined_code = UNDEF_SIZE_0;
78933a4a 6382 return true;
ed63aa17
AV		 6383 }
6384 else
78933a4a 6385 return false;
ed63aa17 6386
66dcaa5d
AV		 6387 case MVE_VABS_VEC:
6388 if (arm_decode_field (given, 18, 19) == 3)
6389 {
6390 *undefined_code = UNDEF_SIZE_3;
78933a4a 6391 return true;
66dcaa5d
AV		 6392 }
6393 else
78933a4a 6394 return false;
66dcaa5d 6395
14b456f2
AV		 6396 case MVE_VQNEG:
6397 case MVE_VQABS:
f49bb598 6398 case MVE_VNEG_VEC:
e523f101
AV		 6399 case MVE_VCLS:
6400 case MVE_VCLZ:
6401 if (arm_decode_field (given, 18, 19) == 3)
6402 {
6403 *undefined_code = UNDEF_SIZE_3;
78933a4a 6404 return true;
e523f101
AV		 6405 }
6406 else
78933a4a 6407 return false;
e523f101 6408
14b456f2
AV		 6409 case MVE_VREV16:
6410 if (arm_decode_field (given, 18, 19) == 0)
78933a4a 6411 return false;
14b456f2
AV		 6412 else
6413 {
6414 *undefined_code = UNDEF_SIZE_NOT_0;
78933a4a 6415 return true;
14b456f2
AV		 6416 }
6417
6418 case MVE_VREV32:
6419 {
6420 unsigned long size = arm_decode_field (given, 18, 19);
6421 if ((size & 2) == 2)
6422 {
6423 *undefined_code = UNDEF_SIZE_2;
78933a4a 6424 return true;
14b456f2
AV		 6425 }
6426 else
78933a4a 6427 return false;
14b456f2
AV		 6428 }
6429
6430 case MVE_VREV64:
6431 if (arm_decode_field (given, 18, 19) != 3)
78933a4a 6432 return false;
14b456f2
AV		 6433 else
6434 {
6435 *undefined_code = UNDEF_SIZE_3;
78933a4a 6436 return true;
14b456f2
AV		 6437 }
6438
9743db03 6439 default:
78933a4a 6440 return false;
9743db03 6441 }
73cd51e5
AV		 6442}
6443
6444/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6445 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6446 why this encoding is unpredictable. */
6447
78933a4a 6448static bool
73cd51e5
AV		 6449is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6450 enum mve_unpredictable *unpredictable_code)
6451{
6452 *unpredictable_code = UNPRED_NONE;
6453
143275ea
AV		 6454 switch (matched_insn)
6455 {
6456 case MVE_VCMP_FP_T2:
6457 case MVE_VPT_FP_T2:
6458 if ((arm_decode_field (given, 12, 12) == 0)
6459 && (arm_decode_field (given, 5, 5) == 1))
6460 {
6461 *unpredictable_code = UNPRED_FCA_0_FCB_1;
78933a4a 6462 return true;
143275ea
AV		 6463 }
6464 else
78933a4a 6465 return false;
73cd51e5 6466
143275ea
AV		 6467 case MVE_VPT_VEC_T4:
6468 case MVE_VPT_VEC_T5:
6469 case MVE_VPT_VEC_T6:
6470 case MVE_VCMP_VEC_T4:
6471 case MVE_VCMP_VEC_T5:
6472 case MVE_VCMP_VEC_T6:
6473 if (arm_decode_field (given, 0, 3) == 0xd)
6474 {
6475 *unpredictable_code = UNPRED_R13;
78933a4a 6476 return true;
143275ea
AV		 6477 }
6478 else
78933a4a 6479 return false;
c1e26897 6480
9743db03
AV		 6481 case MVE_VDUP:
6482 {
6483 unsigned long gpr = arm_decode_field (given, 12, 15);
6484 if (gpr == 0xd)
6485 {
6486 *unpredictable_code = UNPRED_R13;
78933a4a 6487 return true;
9743db03
AV		 6488 }
6489 else if (gpr == 0xf)
6490 {
6491 *unpredictable_code = UNPRED_R15;
78933a4a 6492 return true;
9743db03
AV		 6493 }
6494
78933a4a 6495 return false;
9743db03
AV		 6496 }
6497
14b456f2
AV		 6498 case MVE_VQADD_T2:
6499 case MVE_VQSUB_T2:
f49bb598
AV		 6500 case MVE_VMUL_FP_T2:
6501 case MVE_VMUL_VEC_T2:
56858bea 6502 case MVE_VMLA:
e523f101 6503 case MVE_VBRSR:
66dcaa5d
AV		 6504 case MVE_VADD_FP_T2:
6505 case MVE_VSUB_FP_T2:
6506 case MVE_VADD_VEC_T2:
6507 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6508 case MVE_VQRSHL_T2:
6509 case MVE_VQSHL_T1:
6510 case MVE_VRSHL_T2:
6511 case MVE_VSHL_T2:
6512 case MVE_VSHLC:
d3b63143
AV		 6513 case MVE_VQDMLAH:
6514 case MVE_VQRDMLAH:
6515 case MVE_VQDMLASH:
6516 case MVE_VQRDMLASH:
6517 case MVE_VQDMULH_T3:
6518 case MVE_VQRDMULH_T4:
6519 case MVE_VMLAS:
9743db03
AV		 6520 case MVE_VFMA_FP_SCALAR:
6521 case MVE_VFMAS_FP_SCALAR:
6522 case MVE_VHADD_T2:
6523 case MVE_VHSUB_T2:
6524 {
6525 unsigned long gpr = arm_decode_field (given, 0, 3);
6526 if (gpr == 0xd)
6527 {
6528 *unpredictable_code = UNPRED_R13;
78933a4a 6529 return true;
9743db03
AV		 6530 }
6531 else if (gpr == 0xf)
6532 {
6533 *unpredictable_code = UNPRED_R15;
78933a4a 6534 return true;
9743db03
AV		 6535 }
6536
78933a4a 6537 return false;
9743db03
AV		 6538 }
6539
04d54ace
AV		 6540 case MVE_VLD2:
6541 case MVE_VST2:
6542 {
6543 unsigned long rn = arm_decode_field (given, 16, 19);
6544
6545 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6546 {
6547 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6548 return true;
04d54ace
AV		 6549 }
6550
6551 if (rn == 0xf)
6552 {
6553 *unpredictable_code = UNPRED_R15;
78933a4a 6554 return true;
04d54ace
AV		 6555 }
6556
6557 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6558 {
6559 *unpredictable_code = UNPRED_Q_GT_6;
78933a4a 6560 return true;
04d54ace
AV		 6561 }
6562 else
78933a4a 6563 return false;
04d54ace
AV		 6564 }
6565
6566 case MVE_VLD4:
6567 case MVE_VST4:
6568 {
6569 unsigned long rn = arm_decode_field (given, 16, 19);
6570
6571 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6572 {
6573 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6574 return true;
04d54ace
AV		 6575 }
6576
6577 if (rn == 0xf)
6578 {
6579 *unpredictable_code = UNPRED_R15;
78933a4a 6580 return true;
04d54ace
AV		 6581 }
6582
6583 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6584 {
6585 *unpredictable_code = UNPRED_Q_GT_4;
78933a4a 6586 return true;
04d54ace
AV		 6587 }
6588 else
78933a4a 6589 return false;
04d54ace
AV		 6590 }
6591
aef6d006
AV		 6592 case MVE_VLDRB_T5:
6593 case MVE_VLDRH_T6:
6594 case MVE_VLDRW_T7:
6595 case MVE_VSTRB_T5:
6596 case MVE_VSTRH_T6:
6597 case MVE_VSTRW_T7:
6598 {
6599 unsigned long rn = arm_decode_field (given, 16, 19);
6600
6601 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6602 {
6603 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6604 return true;
aef6d006
AV		 6605 }
6606 else if (rn == 0xf)
6607 {
6608 *unpredictable_code = UNPRED_R15;
78933a4a 6609 return true;
aef6d006
AV		 6610 }
6611 else
78933a4a 6612 return false;
aef6d006
AV		 6613 }
6614
ef1576a1
AV		 6615 case MVE_VLDRB_GATHER_T1:
6616 if (arm_decode_field (given, 0, 0) == 1)
6617 {
6618 *unpredictable_code = UNPRED_OS;
78933a4a 6619 return true;
ef1576a1
AV		 6620 }
6621
6622 /* fall through. */
6623 /* To handle common code with T2-T4 variants. */
6624 case MVE_VLDRH_GATHER_T2:
6625 case MVE_VLDRW_GATHER_T3:
6626 case MVE_VLDRD_GATHER_T4:
6627 {
6628 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6629 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6630
6631 if (qd == qm)
6632 {
6633 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6634 return true;
ef1576a1
AV		 6635 }
6636
6637 if (arm_decode_field (given, 16, 19) == 0xf)
6638 {
6639 *unpredictable_code = UNPRED_R15;
78933a4a 6640 return true;
ef1576a1
AV		 6641 }
6642
78933a4a 6643 return false;
ef1576a1
AV		 6644 }
6645
6646 case MVE_VLDRW_GATHER_T5:
6647 case MVE_VLDRD_GATHER_T6:
6648 {
6649 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6650 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6651
6652 if (qd == qm)
6653 {
6654 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6655 return true;
ef1576a1
AV		 6656 }
6657 else
78933a4a 6658 return false;
ef1576a1
AV		 6659 }
6660
6661 case MVE_VSTRB_SCATTER_T1:
6662 if (arm_decode_field (given, 16, 19) == 0xf)
6663 {
6664 *unpredictable_code = UNPRED_R15;
78933a4a 6665 return true;
ef1576a1
AV		 6666 }
6667 else if (arm_decode_field (given, 0, 0) == 1)
6668 {
6669 *unpredictable_code = UNPRED_OS;
78933a4a 6670 return true;
ef1576a1
AV		 6671 }
6672 else
78933a4a 6673 return false;
ef1576a1
AV		 6674
6675 case MVE_VSTRH_SCATTER_T2:
6676 case MVE_VSTRW_SCATTER_T3:
6677 case MVE_VSTRD_SCATTER_T4:
6678 if (arm_decode_field (given, 16, 19) == 0xf)
6679 {
6680 *unpredictable_code = UNPRED_R15;
78933a4a 6681 return true;
ef1576a1
AV		 6682 }
6683 else
78933a4a 6684 return false;
ef1576a1 6685
c507f10b
AV		 6686 case MVE_VMOV2_VEC_LANE_TO_GP:
6687 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6688 case MVE_VCVT_BETWEEN_FP_INT:
6689 case MVE_VCVT_FROM_FP_TO_INT:
6690 {
6691 unsigned long rt = arm_decode_field (given, 0, 3);
6692 unsigned long rt2 = arm_decode_field (given, 16, 19);
6693
6694 if ((rt == 0xd) || (rt2 == 0xd))
6695 {
6696 *unpredictable_code = UNPRED_R13;
78933a4a 6697 return true;
bf0b396d
AV		 6698 }
6699 else if ((rt == 0xf) || (rt2 == 0xf))
6700 {
6701 *unpredictable_code = UNPRED_R15;
78933a4a 6702 return true;
bf0b396d 6703 }
e683cb41 6704 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
bf0b396d
AV		 6705 {
6706 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
78933a4a 6707 return true;
bf0b396d
AV		 6708 }
6709
78933a4a 6710 return false;
bf0b396d
AV		 6711 }
6712
56858bea
AV		 6713 case MVE_VMAXV:
6714 case MVE_VMAXAV:
6715 case MVE_VMAXNMV_FP:
6716 case MVE_VMAXNMAV_FP:
6717 case MVE_VMINNMV_FP:
6718 case MVE_VMINNMAV_FP:
6719 case MVE_VMINV:
6720 case MVE_VMINAV:
66dcaa5d 6721 case MVE_VABAV:
c507f10b
AV		 6722 case MVE_VMOV_HFP_TO_GP:
6723 case MVE_VMOV_GP_TO_VEC_LANE:
6724 case MVE_VMOV_VEC_LANE_TO_GP:
6725 {
6726 unsigned long rda = arm_decode_field (given, 12, 15);
6727 if (rda == 0xd)
6728 {
6729 *unpredictable_code = UNPRED_R13;
78933a4a 6730 return true;
c507f10b
AV		 6731 }
6732 else if (rda == 0xf)
6733 {
6734 *unpredictable_code = UNPRED_R15;
78933a4a 6735 return true;
c507f10b
AV		 6736 }
6737
78933a4a 6738 return false;
c507f10b
AV		 6739 }
6740
14925797
AV		 6741 case MVE_VMULL_INT:
6742 {
6743 unsigned long Qd;
6744 unsigned long Qm;
6745 unsigned long Qn;
6746
6747 if (arm_decode_field (given, 20, 21) == 2)
6748 {
6749 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6750 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6751 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6752
6753 if ((Qd == Qn) || (Qd == Qm))
6754 {
6755 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6756 return true;
14925797
AV		 6757 }
6758 else
78933a4a 6759 return false;
14925797
AV		 6760 }
6761 else
78933a4a 6762 return false;
14925797
AV		 6763 }
6764
897b9bbc 6765 case MVE_VCMUL_FP:
14925797
AV		 6766 case MVE_VQDMULL_T1:
6767 {
6768 unsigned long Qd;
6769 unsigned long Qm;
6770 unsigned long Qn;
6771
6772 if (arm_decode_field (given, 28, 28) == 1)
6773 {
6774 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6775 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6776 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6777
6778 if ((Qd == Qn) || (Qd == Qm))
6779 {
6780 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6781 return true;
14925797
AV		 6782 }
6783 else
78933a4a 6784 return false;
14925797
AV		 6785 }
6786 else
78933a4a 6787 return false;
14925797
AV		 6788 }
6789
6790 case MVE_VQDMULL_T2:
6791 {
6792 unsigned long gpr = arm_decode_field (given, 0, 3);
6793 if (gpr == 0xd)
6794 {
6795 *unpredictable_code = UNPRED_R13;
78933a4a 6796 return true;
14925797
AV		 6797 }
6798 else if (gpr == 0xf)
6799 {
6800 *unpredictable_code = UNPRED_R15;
78933a4a 6801 return true;
14925797
AV		 6802 }
6803
6804 if (arm_decode_field (given, 28, 28) == 1)
6805 {
6806 unsigned long Qd
6807 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6808 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6809
a9d96ab9 6810 if (Qd == Qn)
14925797
AV		 6811 {
6812 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6813 return true;
14925797
AV		 6814 }
6815 else
78933a4a 6816 return false;
14925797
AV		 6817 }
6818
78933a4a 6819 return false;
14925797
AV		 6820 }
6821
d3b63143
AV		 6822 case MVE_VMLSLDAV:
6823 case MVE_VRMLSLDAVH:
6824 case MVE_VMLALDAV:
6825 case MVE_VADDLV:
6826 if (arm_decode_field (given, 20, 22) == 6)
6827 {
6828 *unpredictable_code = UNPRED_R13;
78933a4a 6829 return true;
d3b63143
AV		 6830 }
6831 else
78933a4a 6832 return false;
d3b63143 6833
1c8f2df8
AV		 6834 case MVE_VDWDUP:
6835 case MVE_VIWDUP:
6836 if (arm_decode_field (given, 1, 3) == 6)
6837 {
6838 *unpredictable_code = UNPRED_R13;
78933a4a 6839 return true;
1c8f2df8
AV		 6840 }
6841 else
78933a4a 6842 return false;
1c8f2df8 6843
897b9bbc
AV		 6844 case MVE_VCADD_VEC:
6845 case MVE_VHCADD:
6846 {
6847 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6848 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6849 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6850 {
6851 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6852 return true;
897b9bbc
AV		 6853 }
6854 else
78933a4a 6855 return false;
897b9bbc
AV		 6856 }
6857
6858 case MVE_VCADD_FP:
6859 {
6860 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6861 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6862 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6863 {
6864 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6865 return true;
897b9bbc
AV		 6866 }
6867 else
78933a4a 6868 return false;
897b9bbc
AV		 6869 }
6870
6871 case MVE_VCMLA_FP:
6872 {
6873 unsigned long Qda;
6874 unsigned long Qm;
6875 unsigned long Qn;
6876
6877 if (arm_decode_field (given, 20, 20) == 1)
6878 {
6879 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6880 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6881 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6882
6883 if ((Qda == Qn) || (Qda == Qm))
6884 {
6885 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6886 return true;
897b9bbc
AV		 6887 }
6888 else
78933a4a 6889 return false;
897b9bbc
AV		 6890 }
6891 else
78933a4a 6892 return false;
897b9bbc
AV		 6893
6894 }
6895
e523f101
AV		 6896 case MVE_VCTP:
6897 if (arm_decode_field (given, 16, 19) == 0xd)
6898 {
6899 *unpredictable_code = UNPRED_R13;
78933a4a 6900 return true;
e523f101
AV		 6901 }
6902 else
78933a4a 6903 return false;
e523f101 6904
14b456f2
AV		 6905 case MVE_VREV64:
6906 {
6907 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6908 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6909
6910 if (qd == qm)
6911 {
6912 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6913 return true;
14b456f2
AV		 6914 }
6915 else
78933a4a 6916 return false;
14b456f2
AV		 6917 }
6918
23d00a41
SD		 6919 case MVE_LSLL:
6920 case MVE_LSLLI:
6921 case MVE_LSRL:
6922 case MVE_ASRL:
6923 case MVE_ASRLI:
6924 case MVE_UQSHLL:
6925 case MVE_UQRSHLL:
6926 case MVE_URSHRL:
6927 case MVE_SRSHRL:
6928 case MVE_SQSHLL:
6929 case MVE_SQRSHRL:
6930 {
6931 unsigned long gpr = arm_decode_field (given, 9, 11);
6932 gpr = ((gpr << 1) | 1);
6933 if (gpr == 0xd)
6934 {
6935 *unpredictable_code = UNPRED_R13;
78933a4a 6936 return true;
23d00a41
SD		 6937 }
6938 else if (gpr == 0xf)
6939 {
6940 *unpredictable_code = UNPRED_R15;
78933a4a 6941 return true;
23d00a41
SD		 6942 }
6943
78933a4a 6944 return false;
23d00a41
SD		 6945 }
6946
143275ea 6947 default:
78933a4a 6948 return false;
143275ea
AV		 6949 }
6950}
c1e26897 6951
c507f10b
AV		 6952static void
6953print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6954{
6955 unsigned long op1 = arm_decode_field (given, 21, 22);
6956 unsigned long op2 = arm_decode_field (given, 5, 6);
6957 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6958 unsigned long index_operand, esize, targetBeat, idx;
c507f10b 6959 void *stream = info->stream;
6576bffe 6960 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 6961
6962 if ((op1 & 0x2) == 0x2)
6963 {
43dd7626 6964 index_operand = op2;
c507f10b
AV		 6965 esize = 8;
6966 }
6967 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6968 {
43dd7626 6969 index_operand = op2 >> 1;
c507f10b
AV		 6970 esize = 16;
6971 }
6972 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6973 {
43dd7626 6974 index_operand = 0;
c507f10b
AV		 6975 esize = 32;
6976 }
6977 else
6978 {
6576bffe 6979 func (stream, dis_style_text, "<undefined index>");
c507f10b
AV		 6980 return;
6981 }
6982
6983 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6984 idx = index_operand + targetBeat * (32/esize);
c507f10b 6985
6576bffe 6986 func (stream, dis_style_immediate, "%lu", idx);
c507f10b
AV		 6987}
6988
6989/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6990 in length and integer of floating-point type. */
6991static void
6992print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6993 unsigned int ibit_loc, const struct mopcode32 *insn)
6994{
6995 int bits = 0;
6996 int cmode = (given >> 8) & 0xf;
6997 int op = (given >> 5) & 0x1;
6998 unsigned long value = 0, hival = 0;
6999 unsigned shift;
7000 int size = 0;
7001 int isfloat = 0;
7002 void *stream = info->stream;
6576bffe 7003 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 7004
7005 /* On Neon the 'i' bit is at bit 24, on mve it is
7006 at bit 28. */
7007 bits |= ((given >> ibit_loc) & 1) << 7;
7008 bits |= ((given >> 16) & 7) << 4;
7009 bits |= ((given >> 0) & 15) << 0;
7010
7011 if (cmode < 8)
7012 {
7013 shift = (cmode >> 1) & 3;
7014 value = (unsigned long) bits << (8 * shift);
7015 size = 32;
7016 }
7017 else if (cmode < 12)
7018 {
7019 shift = (cmode >> 1) & 1;
7020 value = (unsigned long) bits << (8 * shift);
7021 size = 16;
7022 }
7023 else if (cmode < 14)
7024 {
7025 shift = (cmode & 1) + 1;
7026 value = (unsigned long) bits << (8 * shift);
7027 value |= (1ul << (8 * shift)) - 1;
7028 size = 32;
7029 }
7030 else if (cmode == 14)
7031 {
7032 if (op)
7033 {
7034 /* Bit replication into bytes. */
7035 int ix;
7036 unsigned long mask;
7037
7038 value = 0;
7039 hival = 0;
7040 for (ix = 7; ix >= 0; ix--)
7041 {
7042 mask = ((bits >> ix) & 1) ? 0xff : 0;
7043 if (ix <= 3)
7044 value = (value << 8) | mask;
7045 else
7046 hival = (hival << 8) | mask;
7047 }
7048 size = 64;
7049 }
7050 else
7051 {
7052 /* Byte replication. */
7053 value = (unsigned long) bits;
7054 size = 8;
7055 }
7056 }
7057 else if (!op)
7058 {
7059 /* Floating point encoding. */
7060 int tmp;
7061
7062 value = (unsigned long) (bits & 0x7f) << 19;
7063 value |= (unsigned long) (bits & 0x80) << 24;
7064 tmp = bits & 0x40 ? 0x3c : 0x40;
7065 value |= (unsigned long) tmp << 24;
7066 size = 32;
7067 isfloat = 1;
7068 }
7069 else
7070 {
6576bffe 7071 func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
c507f10b
AV		 7072 bits, cmode, op);
7073 size = 32;
7074 return;
7075 }
7076
279edac5
AM		 7077 /* printU determines whether the immediate value should be printed as
7078 unsigned. */
c507f10b
AV		 7079 unsigned printU = 0;
7080 switch (insn->mve_op)
7081 {
7082 default:
7083 break;
279edac5 7084 /* We want this for instructions that don't have a 'signed' type. */
c507f10b
AV		 7085 case MVE_VBIC_IMM:
7086 case MVE_VORR_IMM:
7087 case MVE_VMVN_IMM:
7088 case MVE_VMOV_IMM_TO_VEC:
7089 printU = 1;
7090 break;
7091 }
7092 switch (size)
7093 {
7094 case 8:
6576bffe
AB		 7095 func (stream, dis_style_immediate, "#%ld", value);
7096 func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
c507f10b
AV		 7097 break;
7098
7099 case 16:
6576bffe
AB		 7100 func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
7101 func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
c507f10b
AV		 7102 break;
7103
7104 case 32:
7105 if (isfloat)
7106 {
7107 unsigned char valbytes[4];
7108 double fvalue;
7109
7110 /* Do this a byte at a time so we don't have to
7111 worry about the host's endianness. */
7112 valbytes[0] = value & 0xff;
7113 valbytes[1] = (value >> 8) & 0xff;
7114 valbytes[2] = (value >> 16) & 0xff;
7115 valbytes[3] = (value >> 24) & 0xff;
7116
7117 floatformat_to_double
7118 (& floatformat_ieee_single_little, valbytes,
7119 & fvalue);
7120
6576bffe
AB		 7121 func (stream, dis_style_immediate, "#%.7g", fvalue);
7122 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
c507f10b
AV		 7123 }
7124 else
6576bffe
AB		 7125 {
7126 func (stream, dis_style_immediate,
7127 printU ? "#%lu" : "#%ld",
7128 (long) (((value & 0x80000000L) != 0)
7129 && !printU
7130 ? value | ~0xffffffffL : value));
7131 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
7132 }
c507f10b
AV		 7133 break;
7134
7135 case 64:
6576bffe 7136 func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
c507f10b
AV		 7137 break;
7138
7139 default:
7140 abort ();
7141 }
7142
7143}
7144
73cd51e5
AV		 7145static void
7146print_mve_undefined (struct disassemble_info *info,
7147 enum mve_undefined undefined_code)
7148{
7149 void *stream = info->stream;
6576bffe 7150 fprintf_styled_ftype func = info->fprintf_styled_func;
d8521074
AB		 7151 /* Initialize REASON to avoid compiler warning about uninitialized
7152 usage, though such usage should be impossible. */
7153 const char *reason = "??";
73cd51e5
AV		 7154
7155 switch (undefined_code)
7156 {
ed63aa17 7157 case UNDEF_SIZE:
6576bffe 7158 reason = "illegal size";
ed63aa17
AV		 7159 break;
7160
aef6d006 7161 case UNDEF_SIZE_0:
6576bffe 7162 reason = "size equals zero";
aef6d006
AV		 7163 break;
7164
c507f10b 7165 case UNDEF_SIZE_2:
6576bffe 7166 reason = "size equals two";
c507f10b
AV		 7167 break;
7168
9743db03 7169 case UNDEF_SIZE_3:
6576bffe 7170 reason = "size equals three";
9743db03
AV		 7171 break;
7172
aef6d006 7173 case UNDEF_SIZE_LE_1:
6576bffe 7174 reason = "size <= 1";
aef6d006
AV		 7175 break;
7176
14b456f2 7177 case UNDEF_SIZE_NOT_0:
6576bffe 7178 reason = "size not equal to 0";
14b456f2
AV		 7179 break;
7180
ef1576a1 7181 case UNDEF_SIZE_NOT_2:
6576bffe 7182 reason = "size not equal to 2";
ef1576a1
AV		 7183 break;
7184
7185 case UNDEF_SIZE_NOT_3:
6576bffe 7186 reason = "size not equal to 3";
ef1576a1
AV		 7187 break;
7188
7189 case UNDEF_NOT_UNS_SIZE_0:
6576bffe 7190 reason = "not unsigned and size = zero";
ef1576a1
AV		 7191 break;
7192
7193 case UNDEF_NOT_UNS_SIZE_1:
6576bffe 7194 reason = "not unsigned and size = one";
ef1576a1
AV		 7195 break;
7196
7197 case UNDEF_NOT_UNSIGNED:
6576bffe 7198 reason = "not unsigned";
ef1576a1
AV		 7199 break;
7200
bf0b396d 7201 case UNDEF_VCVT_IMM6:
6576bffe 7202 reason = "invalid imm6";
bf0b396d
AV		 7203 break;
7204
7205 case UNDEF_VCVT_FSI_IMM6:
6576bffe 7206 reason = "fsi = 0 and invalid imm6";
bf0b396d
AV		 7207 break;
7208
c507f10b 7209 case UNDEF_BAD_OP1_OP2:
6576bffe 7210 reason = "bad size with op2 = 2 and op1 = 0 or 1";
c507f10b
AV		 7211 break;
7212
7213 case UNDEF_BAD_U_OP1_OP2:
6576bffe 7214 reason = "unsigned with op2 = 0 and op1 = 0 or 1";
c507f10b
AV		 7215 break;
7216
7217 case UNDEF_OP_0_BAD_CMODE:
6576bffe 7218 reason = "op field equal 0 and bad cmode";
c507f10b
AV		 7219 break;
7220
d3b63143 7221 case UNDEF_XCHG_UNS:
6576bffe 7222 reason = "exchange and unsigned together";
d3b63143
AV		 7223 break;
7224
73cd51e5 7225 case UNDEF_NONE:
6576bffe 7226 reason = "";
73cd51e5
AV		 7227 break;
7228 }
7229
6576bffe 7230 func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
73cd51e5
AV		 7231}
7232
7233static void
7234print_mve_unpredictable (struct disassemble_info *info,
7235 enum mve_unpredictable unpredict_code)
7236{
7237 void *stream = info->stream;
6576bffe 7238 fprintf_styled_ftype func = info->fprintf_styled_func;
2df82cd4
AB		 7239 /* Initialize REASON to avoid compiler warning about uninitialized
7240 usage, though such usage should be impossible. */
7241 const char *reason = "??";
73cd51e5
AV		 7242
7243 switch (unpredict_code)
7244 {
7245 case UNPRED_IT_BLOCK:
6576bffe 7246 reason = "mve instruction in it block";
73cd51e5
AV		 7247 break;
7248
143275ea 7249 case UNPRED_FCA_0_FCB_1:
6576bffe 7250 reason = "condition bits, fca = 0 and fcb = 1";
143275ea
AV		 7251 break;
7252
7253 case UNPRED_R13:
6576bffe 7254 reason = "use of r13 (sp)";
143275ea
AV		 7255 break;
7256
9743db03 7257 case UNPRED_R15:
6576bffe 7258 reason = "use of r15 (pc)";
9743db03
AV		 7259 break;
7260
04d54ace 7261 case UNPRED_Q_GT_4:
6576bffe 7262 reason = "start register block > r4";
04d54ace
AV		 7263 break;
7264
7265 case UNPRED_Q_GT_6:
6576bffe 7266 reason = "start register block > r6";
04d54ace
AV		 7267 break;
7268
7269 case UNPRED_R13_AND_WB:
6576bffe 7270 reason = "use of r13 and write back";
04d54ace
AV		 7271 break;
7272
ef1576a1 7273 case UNPRED_Q_REGS_EQUAL:
6576bffe 7274 reason = "same vector register used for destination and other operand";
ef1576a1
AV		 7275 break;
7276
7277 case UNPRED_OS:
6576bffe 7278 reason = "use of offset scaled";
ef1576a1
AV		 7279 break;
7280
bf0b396d 7281 case UNPRED_GP_REGS_EQUAL:
6576bffe 7282 reason = "same general-purpose register used for both operands";
bf0b396d
AV		 7283 break;
7284
c507f10b 7285 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6576bffe 7286 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7287 break;
7288
7289 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6576bffe 7290 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7291 break;
7292
73cd51e5 7293 case UNPRED_NONE:
6576bffe 7294 reason = "";
73cd51e5
AV		 7295 break;
7296 }
6576bffe
AB		 7297
7298 func (stream, dis_style_comment_start, "%s: %s",
7299 UNPREDICTABLE_INSTRUCTION, reason);
73cd51e5
AV		 7300}
7301
04d54ace
AV		 7302/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7303
7304static void
7305print_mve_register_blocks (struct disassemble_info *info,
7306 unsigned long given,
7307 enum mve_instructions matched_insn)
7308{
7309 void *stream = info->stream;
6576bffe 7310 fprintf_styled_ftype func = info->fprintf_styled_func;
04d54ace
AV		 7311
7312 unsigned long q_reg_start = arm_decode_field_multiple (given,
7313 13, 15,
7314 22, 22);
7315 switch (matched_insn)
7316 {
7317 case MVE_VLD2:
7318 case MVE_VST2:
7319 if (q_reg_start <= 6)
6576bffe
AB		 7320 {
7321 func (stream, dis_style_text, "{");
7322 func (stream, dis_style_register, "q%ld", q_reg_start);
7323 func (stream, dis_style_text, ", ");
7324 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7325 func (stream, dis_style_text, "}");
7326 }
04d54ace 7327 else
6576bffe 7328 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7329 break;
7330
7331 case MVE_VLD4:
7332 case MVE_VST4:
7333 if (q_reg_start <= 4)
6576bffe
AB		 7334 {
7335 func (stream, dis_style_text, "{");
7336 func (stream, dis_style_register, "q%ld", q_reg_start);
7337 func (stream, dis_style_text, ", ");
7338 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7339 func (stream, dis_style_text, ", ");
7340 func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7341 func (stream, dis_style_text, ", ");
7342 func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7343 func (stream, dis_style_text, "}");
7344 }
04d54ace 7345 else
6576bffe 7346 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7347 break;
7348
7349 default:
7350 break;
7351 }
7352}
7353
bf0b396d
AV		 7354static void
7355print_mve_rounding_mode (struct disassemble_info *info,
7356 unsigned long given,
7357 enum mve_instructions matched_insn)
7358{
7359 void *stream = info->stream;
6576bffe 7360 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7361
7362 switch (matched_insn)
7363 {
7364 case MVE_VCVT_FROM_FP_TO_INT:
7365 {
7366 switch (arm_decode_field (given, 8, 9))
7367 {
7368 case 0:
6576bffe 7369 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7370 break;
7371
7372 case 1:
6576bffe 7373 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7374 break;
7375
7376 case 2:
6576bffe 7377 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7378 break;
7379
7380 case 3:
6576bffe 7381 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7382 break;
7383
7384 default:
7385 break;
7386 }
7387 }
7388 break;
7389
7390 case MVE_VRINT_FP:
7391 {
7392 switch (arm_decode_field (given, 7, 9))
7393 {
7394 case 0:
6576bffe 7395 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7396 break;
7397
7398 case 1:
6576bffe 7399 func (stream, dis_style_mnemonic, "x");
bf0b396d
AV		 7400 break;
7401
7402 case 2:
6576bffe 7403 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7404 break;
7405
7406 case 3:
6576bffe 7407 func (stream, dis_style_mnemonic, "z");
bf0b396d
AV		 7408 break;
7409
7410 case 5:
6576bffe 7411 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7412 break;
7413
7414 case 7:
6576bffe 7415 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7416
7417 case 4:
7418 case 6:
7419 default:
7420 break;
7421 }
7422 }
7423 break;
7424
7425 default:
7426 break;
7427 }
7428}
7429
7430static void
7431print_mve_vcvt_size (struct disassemble_info *info,
7432 unsigned long given,
7433 enum mve_instructions matched_insn)
7434{
7435 unsigned long mode = 0;
7436 void *stream = info->stream;
6576bffe 7437 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7438
7439 switch (matched_insn)
7440 {
7441 case MVE_VCVT_FP_FIX_VEC:
7442 {
7443 mode = (((given & 0x200) >> 7)
7444 | ((given & 0x10000000) >> 27)
7445 | ((given & 0x100) >> 8));
7446
7447 switch (mode)
7448 {
7449 case 0:
6576bffe 7450 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7451 break;
7452
7453 case 1:
6576bffe 7454 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7455 break;
7456
7457 case 2:
6576bffe 7458 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7459 break;
7460
7461 case 3:
6576bffe 7462 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7463 break;
7464
7465 case 4:
6576bffe 7466 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7467 break;
7468
7469 case 5:
6576bffe 7470 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7471 break;
7472
7473 case 6:
6576bffe 7474 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7475 break;
7476
7477 case 7:
6576bffe 7478 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7479 break;
7480
7481 default:
7482 break;
7483 }
7484 break;
7485 }
7486 case MVE_VCVT_BETWEEN_FP_INT:
7487 {
7488 unsigned long size = arm_decode_field (given, 18, 19);
7489 unsigned long op = arm_decode_field (given, 7, 8);
7490
7491 if (size == 1)
7492 {
7493 switch (op)
7494 {
7495 case 0:
6576bffe 7496 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7497 break;
7498
7499 case 1:
6576bffe 7500 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7501 break;
7502
7503 case 2:
6576bffe 7504 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7505 break;
7506
7507 case 3:
6576bffe 7508 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7509 break;
7510
7511 default:
7512 break;
7513 }
7514 }
7515 else if (size == 2)
7516 {
7517 switch (op)
7518 {
7519 case 0:
6576bffe 7520 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7521 break;
7522
7523 case 1:
6576bffe 7524 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7525 break;
7526
7527 case 2:
6576bffe 7528 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7529 break;
7530
7531 case 3:
6576bffe 7532 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7533 break;
7534 }
7535 }
7536 }
7537 break;
7538
7539 case MVE_VCVT_FP_HALF_FP:
7540 {
7541 unsigned long op = arm_decode_field (given, 28, 28);
7542 if (op == 0)
6576bffe 7543 func (stream, dis_style_mnemonic, "f16.f32");
bf0b396d 7544 else if (op == 1)
6576bffe 7545 func (stream, dis_style_mnemonic, "f32.f16");
bf0b396d
AV		 7546 }
7547 break;
7548
7549 case MVE_VCVT_FROM_FP_TO_INT:
7550 {
7551 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7552
7553 switch (size)
7554 {
7555 case 2:
6576bffe 7556 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7557 break;
7558
7559 case 3:
6576bffe 7560 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7561 break;
7562
7563 case 4:
6576bffe 7564 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7565 break;
7566
7567 case 5:
6576bffe 7568 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7569 break;
7570
7571 default:
7572 break;
7573 }
7574 }
7575 break;
7576
7577 default:
7578 break;
7579 }
7580}
7581
897b9bbc
AV		 7582static void
7583print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7584 unsigned long rot_width)
7585{
7586 void *stream = info->stream;
6576bffe 7587 fprintf_styled_ftype func = info->fprintf_styled_func;
897b9bbc
AV		 7588
7589 if (rot_width == 1)
7590 {
7591 switch (rot)
7592 {
7593 case 0:
6576bffe 7594 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7595 break;
7596 case 1:
6576bffe 7597 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7598 break;
7599 default:
7600 break;
7601 }
7602 }
7603 else if (rot_width == 2)
7604 {
7605 switch (rot)
7606 {
7607 case 0:
6576bffe 7608 func (stream, dis_style_immediate, "0");
897b9bbc
AV		 7609 break;
7610 case 1:
6576bffe 7611 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7612 break;
7613 case 2:
6576bffe 7614 func (stream, dis_style_immediate, "180");
897b9bbc
AV		 7615 break;
7616 case 3:
6576bffe 7617 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7618 break;
7619 default:
7620 break;
7621 }
7622 }
7623}
7624
143275ea
AV		 7625static void
7626print_instruction_predicate (struct disassemble_info *info)
7627{
7628 void *stream = info->stream;
6576bffe 7629 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7630
7631 if (vpt_block_state.next_pred_state == PRED_THEN)
6576bffe 7632 func (stream, dis_style_mnemonic, "t");
143275ea 7633 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6576bffe 7634 func (stream, dis_style_mnemonic, "e");
143275ea
AV		 7635}
7636
7637static void
7638print_mve_size (struct disassemble_info *info,
7639 unsigned long size,
7640 enum mve_instructions matched_insn)
7641{
7642 void *stream = info->stream;
6576bffe 7643 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7644
7645 switch (matched_insn)
7646 {
66dcaa5d
AV		 7647 case MVE_VABAV:
7648 case MVE_VABD_VEC:
7649 case MVE_VABS_FP:
7650 case MVE_VABS_VEC:
7651 case MVE_VADD_VEC_T1:
7652 case MVE_VADD_VEC_T2:
d3b63143 7653 case MVE_VADDV:
e523f101 7654 case MVE_VBRSR:
897b9bbc 7655 case MVE_VCADD_VEC:
e523f101
AV		 7656 case MVE_VCLS:
7657 case MVE_VCLZ:
143275ea
AV		 7658 case MVE_VCMP_VEC_T1:
7659 case MVE_VCMP_VEC_T2:
7660 case MVE_VCMP_VEC_T3:
7661 case MVE_VCMP_VEC_T4:
7662 case MVE_VCMP_VEC_T5:
7663 case MVE_VCMP_VEC_T6:
e523f101 7664 case MVE_VCTP:
1c8f2df8
AV		 7665 case MVE_VDDUP:
7666 case MVE_VDWDUP:
9743db03
AV		 7667 case MVE_VHADD_T1:
7668 case MVE_VHADD_T2:
897b9bbc 7669 case MVE_VHCADD:
9743db03
AV		 7670 case MVE_VHSUB_T1:
7671 case MVE_VHSUB_T2:
1c8f2df8
AV		 7672 case MVE_VIDUP:
7673 case MVE_VIWDUP:
04d54ace
AV		 7674 case MVE_VLD2:
7675 case MVE_VLD4:
ef1576a1
AV		 7676 case MVE_VLDRB_GATHER_T1:
7677 case MVE_VLDRH_GATHER_T2:
7678 case MVE_VLDRW_GATHER_T3:
7679 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7680 case MVE_VLDRB_T1:
7681 case MVE_VLDRH_T2:
56858bea
AV		 7682 case MVE_VMAX:
7683 case MVE_VMAXA:
7684 case MVE_VMAXV:
7685 case MVE_VMAXAV:
7686 case MVE_VMIN:
7687 case MVE_VMINA:
7688 case MVE_VMINV:
7689 case MVE_VMINAV:
7690 case MVE_VMLA:
d3b63143 7691 case MVE_VMLAS:
f49bb598
AV		 7692 case MVE_VMUL_VEC_T1:
7693 case MVE_VMUL_VEC_T2:
7694 case MVE_VMULH:
7695 case MVE_VRMULH:
7696 case MVE_VMULL_INT:
7697 case MVE_VNEG_FP:
7698 case MVE_VNEG_VEC:
143275ea
AV		 7699 case MVE_VPT_VEC_T1:
7700 case MVE_VPT_VEC_T2:
7701 case MVE_VPT_VEC_T3:
7702 case MVE_VPT_VEC_T4:
7703 case MVE_VPT_VEC_T5:
7704 case MVE_VPT_VEC_T6:
14b456f2
AV		 7705 case MVE_VQABS:
7706 case MVE_VQADD_T1:
7707 case MVE_VQADD_T2:
d3b63143
AV		 7708 case MVE_VQDMLADH:
7709 case MVE_VQRDMLADH:
7710 case MVE_VQDMLAH:
7711 case MVE_VQRDMLAH:
7712 case MVE_VQDMLASH:
7713 case MVE_VQRDMLASH:
7714 case MVE_VQDMLSDH:
7715 case MVE_VQRDMLSDH:
7716 case MVE_VQDMULH_T1:
7717 case MVE_VQRDMULH_T2:
7718 case MVE_VQDMULH_T3:
7719 case MVE_VQRDMULH_T4:
14b456f2 7720 case MVE_VQNEG:
ed63aa17
AV		 7721 case MVE_VQRSHL_T1:
7722 case MVE_VQRSHL_T2:
7723 case MVE_VQSHL_T1:
7724 case MVE_VQSHL_T4:
14b456f2
AV		 7725 case MVE_VQSUB_T1:
7726 case MVE_VQSUB_T2:
7727 case MVE_VREV32:
7728 case MVE_VREV64:
9743db03 7729 case MVE_VRHADD:
bf0b396d 7730 case MVE_VRINT_FP:
ed63aa17
AV		 7731 case MVE_VRSHL_T1:
7732 case MVE_VRSHL_T2:
7733 case MVE_VSHL_T2:
7734 case MVE_VSHL_T3:
7735 case MVE_VSHLL_T2:
04d54ace
AV		 7736 case MVE_VST2:
7737 case MVE_VST4:
ef1576a1
AV		 7738 case MVE_VSTRB_SCATTER_T1:
7739 case MVE_VSTRH_SCATTER_T2:
7740 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7741 case MVE_VSTRB_T1:
7742 case MVE_VSTRH_T2:
66dcaa5d
AV		 7743 case MVE_VSUB_VEC_T1:
7744 case MVE_VSUB_VEC_T2:
143275ea 7745 if (size <= 3)
6576bffe 7746 func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
143275ea 7747 else
6576bffe 7748 func (stream, dis_style_text, "<undef size>");
143275ea
AV		 7749 break;
7750
66dcaa5d
AV		 7751 case MVE_VABD_FP:
7752 case MVE_VADD_FP_T1:
7753 case MVE_VADD_FP_T2:
7754 case MVE_VSUB_FP_T1:
7755 case MVE_VSUB_FP_T2:
143275ea
AV		 7756 case MVE_VCMP_FP_T1:
7757 case MVE_VCMP_FP_T2:
9743db03
AV		 7758 case MVE_VFMA_FP_SCALAR:
7759 case MVE_VFMA_FP:
7760 case MVE_VFMS_FP:
7761 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7762 case MVE_VMAXNM_FP:
7763 case MVE_VMAXNMA_FP:
7764 case MVE_VMAXNMV_FP:
7765 case MVE_VMAXNMAV_FP:
7766 case MVE_VMINNM_FP:
7767 case MVE_VMINNMA_FP:
7768 case MVE_VMINNMV_FP:
7769 case MVE_VMINNMAV_FP:
f49bb598
AV		 7770 case MVE_VMUL_FP_T1:
7771 case MVE_VMUL_FP_T2:
143275ea
AV		 7772 case MVE_VPT_FP_T1:
7773 case MVE_VPT_FP_T2:
7774 if (size == 0)
6576bffe 7775 func (stream, dis_style_mnemonic, "32");
143275ea 7776 else if (size == 1)
6576bffe 7777 func (stream, dis_style_mnemonic, "16");
143275ea
AV		 7778 break;
7779
897b9bbc
AV		 7780 case MVE_VCADD_FP:
7781 case MVE_VCMLA_FP:
7782 case MVE_VCMUL_FP:
d3b63143
AV		 7783 case MVE_VMLADAV_T1:
7784 case MVE_VMLALDAV:
7785 case MVE_VMLSDAV_T1:
7786 case MVE_VMLSLDAV:
14925797
AV		 7787 case MVE_VMOVN:
7788 case MVE_VQDMULL_T1:
7789 case MVE_VQDMULL_T2:
7790 case MVE_VQMOVN:
7791 case MVE_VQMOVUN:
7792 if (size == 0)
6576bffe 7793 func (stream, dis_style_mnemonic, "16");
14925797 7794 else if (size == 1)
6576bffe 7795 func (stream, dis_style_mnemonic, "32");
14925797
AV		 7796 break;
7797
7798 case MVE_VMOVL:
7799 if (size == 1)
6576bffe 7800 func (stream, dis_style_mnemonic, "8");
14925797 7801 else if (size == 2)
6576bffe 7802 func (stream, dis_style_mnemonic, "16");
14925797
AV		 7803 break;
7804
9743db03
AV		 7805 case MVE_VDUP:
7806 switch (size)
7807 {
7808 case 0:
6576bffe 7809 func (stream, dis_style_mnemonic, "32");
9743db03
AV		 7810 break;
7811 case 1:
6576bffe 7812 func (stream, dis_style_mnemonic, "16");
9743db03
AV		 7813 break;
7814 case 2:
6576bffe 7815 func (stream, dis_style_mnemonic, "8");
9743db03
AV		 7816 break;
7817 default:
7818 break;
7819 }
7820 break;
7821
c507f10b
AV		 7822 case MVE_VMOV_GP_TO_VEC_LANE:
7823 case MVE_VMOV_VEC_LANE_TO_GP:
7824 switch (size)
7825 {
7826 case 0: case 4:
6576bffe 7827 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7828 break;
7829
7830 case 1: case 3:
7831 case 5: case 7:
6576bffe 7832 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7833 break;
7834
7835 case 8: case 9: case 10: case 11:
7836 case 12: case 13: case 14: case 15:
6576bffe 7837 func (stream, dis_style_mnemonic, "8");
c507f10b
AV		 7838 break;
7839
7840 default:
7841 break;
7842 }
7843 break;
7844
7845 case MVE_VMOV_IMM_TO_VEC:
7846 switch (size)
7847 {
7848 case 0: case 4: case 8:
7849 case 12: case 24: case 26:
6576bffe 7850 func (stream, dis_style_mnemonic, "i32");
c507f10b
AV		 7851 break;
7852 case 16: case 20:
6576bffe 7853 func (stream, dis_style_mnemonic, "i16");
c507f10b
AV		 7854 break;
7855 case 28:
6576bffe 7856 func (stream, dis_style_mnemonic, "i8");
c507f10b
AV		 7857 break;
7858 case 29:
6576bffe 7859 func (stream, dis_style_mnemonic, "i64");
c507f10b
AV		 7860 break;
7861 case 30:
6576bffe 7862 func (stream, dis_style_mnemonic, "f32");
c507f10b
AV		 7863 break;
7864 default:
7865 break;
7866 }
7867 break;
7868
14925797
AV		 7869 case MVE_VMULL_POLY:
7870 if (size == 0)
6576bffe 7871 func (stream, dis_style_mnemonic, "p8");
14925797 7872 else if (size == 1)
6576bffe 7873 func (stream, dis_style_mnemonic, "p16");
14925797
AV		 7874 break;
7875
c507f10b
AV		 7876 case MVE_VMVN_IMM:
7877 switch (size)
7878 {
7879 case 0: case 2: case 4:
7880 case 6: case 12: case 13:
6576bffe 7881 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7882 break;
7883
7884 case 8: case 10:
6576bffe 7885 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7886 break;
7887
7888 default:
7889 break;
7890 }
7891 break;
7892
7893 case MVE_VBIC_IMM:
7894 case MVE_VORR_IMM:
7895 switch (size)
7896 {
7897 case 1: case 3:
7898 case 5: case 7:
6576bffe 7899 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7900 break;
7901
7902 case 9: case 11:
6576bffe 7903 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7904 break;
7905
7906 default:
7907 break;
7908 }
7909 break;
7910
ed63aa17
AV		 7911 case MVE_VQSHRN:
7912 case MVE_VQSHRUN:
7913 case MVE_VQRSHRN:
7914 case MVE_VQRSHRUN:
7915 case MVE_VRSHRN:
7916 case MVE_VSHRN:
7917 {
7918 switch (size)
7919 {
7920 case 1:
6576bffe 7921 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7922 break;
7923
7924 case 2: case 3:
6576bffe 7925 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7926 break;
7927
7928 default:
7929 break;
7930 }
7931 }
7932 break;
7933
7934 case MVE_VQSHL_T2:
7935 case MVE_VQSHLU_T3:
7936 case MVE_VRSHR:
7937 case MVE_VSHL_T1:
7938 case MVE_VSHLL_T1:
7939 case MVE_VSHR:
7940 case MVE_VSLI:
7941 case MVE_VSRI:
7942 {
7943 switch (size)
7944 {
7945 case 1:
6576bffe 7946 func (stream, dis_style_mnemonic, "8");
ed63aa17
AV		 7947 break;
7948
7949 case 2: case 3:
6576bffe 7950 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7951 break;
7952
7953 case 4: case 5: case 6: case 7:
6576bffe 7954 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7955 break;
7956
7957 default:
7958 break;
7959 }
7960 }
7961 break;
7962
143275ea
AV		 7963 default:
7964 break;
7965 }
7966}
7967
ed63aa17
AV		 7968static void
7969print_mve_shift_n (struct disassemble_info *info, long given,
7970 enum mve_instructions matched_insn)
7971{
7972 void *stream = info->stream;
6576bffe 7973 fprintf_styled_ftype func = info->fprintf_styled_func;
ed63aa17
AV		 7974
7975 int startAt0
7976 = matched_insn == MVE_VQSHL_T2
7977 || matched_insn == MVE_VQSHLU_T3
7978 || matched_insn == MVE_VSHL_T1
7979 || matched_insn == MVE_VSHLL_T1
7980 || matched_insn == MVE_VSLI;
7981
7982 unsigned imm6 = (given & 0x3f0000) >> 16;
7983
7984 if (matched_insn == MVE_VSHLL_T1)
7985 imm6 &= 0x1f;
7986
7987 unsigned shiftAmount = 0;
7988 if ((imm6 & 0x20) != 0)
7989 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7990 else if ((imm6 & 0x10) != 0)
7991 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7992 else if ((imm6 & 0x08) != 0)
7993 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7994 else
7995 print_mve_undefined (info, UNDEF_SIZE_0);
7996
6576bffe 7997 func (stream, dis_style_immediate, "%u", shiftAmount);
ed63aa17
AV		 7998}
7999
143275ea
AV		 8000static void
8001print_vec_condition (struct disassemble_info *info, long given,
8002 enum mve_instructions matched_insn)
8003{
8004 void *stream = info->stream;
6576bffe 8005 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 8006 long vec_cond = 0;
8007
8008 switch (matched_insn)
8009 {
8010 case MVE_VPT_FP_T1:
8011 case MVE_VCMP_FP_T1:
8012 vec_cond = (((given & 0x1000) >> 10)
8013 | ((given & 1) << 1)
8014 | ((given & 0x0080) >> 7));
6576bffe 8015 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8016 break;
8017
8018 case MVE_VPT_FP_T2:
8019 case MVE_VCMP_FP_T2:
8020 vec_cond = (((given & 0x1000) >> 10)
8021 | ((given & 0x0020) >> 4)
8022 | ((given & 0x0080) >> 7));
6576bffe 8023 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8024 break;
8025
8026 case MVE_VPT_VEC_T1:
8027 case MVE_VCMP_VEC_T1:
8028 vec_cond = (given & 0x0080) >> 7;
6576bffe 8029 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8030 break;
8031
8032 case MVE_VPT_VEC_T2:
8033 case MVE_VCMP_VEC_T2:
8034 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 8035 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8036 break;
8037
8038 case MVE_VPT_VEC_T3:
8039 case MVE_VCMP_VEC_T3:
8040 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6576bffe 8041 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8042 break;
8043
8044 case MVE_VPT_VEC_T4:
8045 case MVE_VCMP_VEC_T4:
8046 vec_cond = (given & 0x0080) >> 7;
6576bffe 8047 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8048 break;
8049
8050 case MVE_VPT_VEC_T5:
8051 case MVE_VCMP_VEC_T5:
8052 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 8053 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8054 break;
8055
8056 case MVE_VPT_VEC_T6:
8057 case MVE_VCMP_VEC_T6:
8058 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6576bffe 8059 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8060 break;
8061
8062 case MVE_NONE:
8063 case MVE_VPST:
8064 default:
8065 break;
8066 }
8067}
8068
8069#define W_BIT 21
8070#define I_BIT 22
8071#define U_BIT 23
8072#define P_BIT 24
8073
8074#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8075#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8076#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8077#define PRE_BIT_SET (given & (1 << P_BIT))
8078
6576bffe
AB		 8079/* The assembler string for an instruction can include %{X:...%} patterns,
8080 where the 'X' is one of the characters understood by this function.
8081
8082 This function takes the X character, and returns a new style. This new
8083 style will be used by the caller to temporarily change the current base
8084 style. */
8085
8086static enum disassembler_style
8087decode_base_style (const char x)
8088{
8089 switch (x)
8090 {
8091 case 'A': return dis_style_address;
8092 case 'B': return dis_style_sub_mnemonic;
8093 case 'C': return dis_style_comment_start;
8094 case 'D': return dis_style_assembler_directive;
8095 case 'I': return dis_style_immediate;
8096 case 'M': return dis_style_mnemonic;
8097 case 'O': return dis_style_address_offset;
8098 case 'R': return dis_style_register;
8099 case 'S': return dis_style_symbol;
8100 case 'T': return dis_style_text;
8101 default:
8102 abort ();
8103 }
8104}
143275ea 8105
8f06b2d8
PB		 8106/* Print one coprocessor instruction on INFO->STREAM.
8107 Return TRUE if the instuction matched, FALSE if this is not a
8108 recognised coprocessor instruction. */
8109
78933a4a 8110static bool
33593eaf
MM		 8111print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8112 bfd_vma pc,
8113 struct disassemble_info *info,
8114 long given,
78933a4a 8115 bool thumb)
8f06b2d8 8116{
6b0dd094 8117 const struct sopcode32 *insn;
8f06b2d8 8118 void *stream = info->stream;
6576bffe 8119 fprintf_styled_ftype func = info->fprintf_styled_func;
8f06b2d8 8120 unsigned long mask;
2edcd244 8121 unsigned long value = 0;
c22aaad1 8122 int cond;
8afc7bea 8123 int cp_num;
823d2571
TG		 8124 struct arm_private_data *private_data = info->private_data;
8125 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 8126 arm_feature_set arm_ext_v8_1m_main =
8127 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
6576bffe
AB		 8128 enum disassembler_style base_style = dis_style_mnemonic;
8129 enum disassembler_style old_base_style = base_style;
823d2571 8130
5b616bef 8131 allowed_arches = private_data->features;
8f06b2d8 8132
33593eaf 8133 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 8134 {
ff4a8d2b 8135 unsigned long u_reg = 16;
78933a4a 8136 bool is_unpredictable = false;
05413229 8137 signed long value_in_comment = 0;
0313a2b8
NC		 8138 const char *c;
8139
823d2571 8140 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 8141 switch (insn->value)
8142 {
8143 case SENTINEL_IWMMXT_START:
8144 if (info->mach != bfd_mach_arm_XScale
8145 && info->mach != bfd_mach_arm_iWMMXt
8146 && info->mach != bfd_mach_arm_iWMMXt2)
8147 do
8148 insn++;
823d2571
TG		 8149 while ((! ARM_FEATURE_ZERO (insn->arch))
8150 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8151 continue;
8152
8153 case SENTINEL_IWMMXT_END:
8154 continue;
8155
8156 case SENTINEL_GENERIC_START:
5b616bef 8157 allowed_arches = private_data->features;
05413229
NC		 8158 continue;
8159
8160 default:
8161 abort ();
8162 }
8f06b2d8
PB		 8163
8164 mask = insn->mask;
8165 value = insn->value;
8afc7bea
RL		 8166 cp_num = (given >> 8) & 0xf;
8167
8f06b2d8
PB		 8168 if (thumb)
8169 {
8170 /* The high 4 bits are 0xe for Arm conditional instructions, and
8171 0xe for arm unconditional instructions. The rest of the
8172 encoding is the same. */
8173 mask |= 0xf0000000;
8174 value |= 0xe0000000;
c22aaad1
PB		 8175 if (ifthen_state)
8176 cond = IFTHEN_COND;
8177 else
e2efe87d 8178 cond = COND_UNCOND;
8f06b2d8
PB		 8179 }
8180 else
8181 {
8182 /* Only match unconditional instuctions against unconditional
8183 patterns. */
8184 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8185 {
8186 mask |= 0xf0000000;
e2efe87d 8187 cond = COND_UNCOND;
c22aaad1
PB		 8188 }
8189 else
8190 {
8191 cond = (given >> 28) & 0xf;
8192 if (cond == 0xe)
e2efe87d 8193 cond = COND_UNCOND;
c22aaad1 8194 }
8f06b2d8 8195 }
823d2571 8196
6b0dd094
AV		 8197 if ((insn->isa == T32 && !thumb)
8198 || (insn->isa == ARM && thumb))
8199 continue;
8200
0313a2b8
NC		 8201 if ((given & mask) != value)
8202 continue;
8f06b2d8 8203
823d2571 8204 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8205 continue;
8206
8afc7bea
RL		 8207 if (insn->value == 0xfe000010 /* mcr2 */
8208 || insn->value == 0xfe100010 /* mrc2 */
8209 || insn->value == 0xfc100000 /* ldc2 */
8210 || insn->value == 0xfc000000) /* stc2 */
8211 {
b0c11777 8212 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
78933a4a 8213 is_unpredictable = true;
f08d8ce3
AV		 8214
8215 /* Armv8.1-M Mainline FP & MVE instructions. */
8216 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8217 && !ARM_CPU_IS_ANY (allowed_arches)
8218 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8219 continue;
8220
8afc7bea
RL		 8221 }
8222 else if (insn->value == 0x0e000000 /* cdp */
8223 || insn->value == 0xfe000000 /* cdp2 */
8224 || insn->value == 0x0e000010 /* mcr */
8225 || insn->value == 0x0e100010 /* mrc */
8226 || insn->value == 0x0c100000 /* ldc */
8227 || insn->value == 0x0c000000) /* stc */
8228 {
8229 /* Floating-point instructions. */
b0c11777 8230 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8231 continue;
32c36c3c
AV		 8232
8233 /* Armv8.1-M Mainline FP & MVE instructions. */
8234 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8235 && !ARM_CPU_IS_ANY (allowed_arches)
8236 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8237 continue;
8afc7bea 8238 }
aef6d006
AV		 8239 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8240 || insn->value == 0xec000f80) /* vstr (system register) */
8241 && arm_decode_field (given, 24, 24) == 0
8242 && arm_decode_field (given, 21, 21) == 0)
8243 /* If the P and W bits are both 0 then these encodings match the MVE
8244 VLDR and VSTR instructions, these are in a different table, so we
8245 don't let it match here. */
8246 continue;
8247
0313a2b8
NC		 8248 for (c = insn->assembler; *c; c++)
8249 {
8250 if (*c == '%')
8f06b2d8 8251 {
32c36c3c 8252 const char mod = *++c;
6576bffe 8253
32c36c3c 8254 switch (mod)
8f06b2d8 8255 {
6576bffe
AB		 8256 case '{':
8257 ++c;
8258 if (*c == '\0')
8259 abort ();
8260 old_base_style = base_style;
8261 base_style = decode_base_style (*c);
8262 ++c;
8263 if (*c != ':')
8264 abort ();
8265 break;
8266
8267 case '}':
8268 base_style = old_base_style;
8269 break;
8270
0313a2b8 8271 case '%':
6576bffe 8272 func (stream, base_style, "%%");
0313a2b8
NC		 8273 break;
8274
8275 case 'A':
32c36c3c 8276 case 'K':
05413229 8277 {
79862e45 8278 int rn = (given >> 16) & 0xf;
b0c11777 8279 bfd_vma offset = given & 0xff;
0313a2b8 8280
32c36c3c
AV		 8281 if (mod == 'K')
8282 offset = given & 0x7f;
8283
6576bffe
AB		 8284 func (stream, dis_style_text, "[");
8285 func (stream, dis_style_register, "%s",
8286 arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8287
79862e45
DJ		 8288 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8289 {
8290 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8291 if (cp_num == 9)
8292 /* vldr.16/vstr.16 will shift the address
8293 left by 1 bit only. */
8294 offset = offset * 2;
8295 else
8296 offset = offset * 4;
8297
79862e45
DJ		 8298 if (NEGATIVE_BIT_SET)
8299 offset = - offset;
8300 if (rn != 15)
8301 value_in_comment = offset;
8302 }
8303
c1e26897 8304 if (PRE_BIT_SET)
05413229
NC		 8305 {
8306 if (offset)
6576bffe
AB		 8307 {
8308 func (stream, dis_style_text, ", ");
8309 func (stream, dis_style_immediate, "#%d",
8310 (int) offset);
8311 func (stream, dis_style_text, "]%s",
8312 WRITEBACK_BIT_SET ? "!" : "");
8313 }
26d97720 8314 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8315 {
8316 func (stream, dis_style_text, ", ");
8317 func (stream, dis_style_immediate, "#-0");
8318 func (stream, dis_style_text, "]");
8319 }
05413229 8320 else
6576bffe 8321 func (stream, dis_style_text, "]");
05413229
NC		 8322 }
8323 else
8324 {
6576bffe 8325 func (stream, dis_style_text, "]");
8f06b2d8 8326
c1e26897 8327 if (WRITEBACK_BIT_SET)
05413229
NC		 8328 {
8329 if (offset)
6576bffe
AB		 8330 {
8331 func (stream, dis_style_text, ", ");
8332 func (stream, dis_style_immediate,
8333 "#%d", (int) offset);
8334 }
26d97720 8335 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8336 {
8337 func (stream, dis_style_text, ", ");
8338 func (stream, dis_style_immediate, "#-0");
8339 }
05413229
NC		 8340 }
8341 else
fe56b6ce 8342 {
6576bffe
AB		 8343 func (stream, dis_style_text, ", {");
8344 func (stream, dis_style_immediate, "%s%d",
26d97720 8345 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8346 (int) offset);
6576bffe 8347 func (stream, dis_style_text, "}");
fe56b6ce
NC		 8348 value_in_comment = offset;
8349 }
05413229 8350 }
79862e45
DJ		 8351 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8352 {
6576bffe 8353 func (stream, dis_style_comment_start, "\t@ ");
6844b2c2
MGD		 8354 /* For unaligned PCs, apply off-by-alignment
8355 correction. */
43e65147 8356 info->print_address_func (offset + pc
6844b2c2
MGD		 8357 + info->bytes_per_chunk * 2
8358 - (pc & 3),
dffaa15c 8359 info);
79862e45 8360 }
05413229 8361 }
0313a2b8 8362 break;
8f06b2d8 8363
0313a2b8
NC		 8364 case 'B':
8365 {
8366 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8367 int offset = (given >> 1) & 0x3f;
8368
6576bffe 8369 func (stream, dis_style_text, "{");
0313a2b8 8370 if (offset == 1)
6576bffe 8371 func (stream, dis_style_register, "d%d", regno);
0313a2b8 8372 else if (regno + offset > 32)
6576bffe
AB		 8373 {
8374 func (stream, dis_style_register, "d%d", regno);
8375 func (stream, dis_style_text, "-<overflow reg d%d>",
8376 regno + offset - 1);
8377 }
0313a2b8 8378 else
6576bffe
AB		 8379 {
8380 func (stream, dis_style_register, "d%d", regno);
8381 func (stream, dis_style_text, "-");
8382 func (stream, dis_style_register, "d%d",
8383 regno + offset - 1);
8384 }
8385 func (stream, dis_style_text, "}");
0313a2b8
NC		 8386 }
8387 break;
8f06b2d8 8388
efd6b359
AV		 8389 case 'C':
8390 {
78933a4a 8391 bool single = ((given >> 8) & 1) == 0;
efd6b359
AV		 8392 char reg_prefix = single ? 's' : 'd';
8393 int Dreg = (given >> 22) & 0x1;
8394 int Vdreg = (given >> 12) & 0xf;
8395 int reg = single ? ((Vdreg << 1) | Dreg)
8396 : ((Dreg << 4) | Vdreg);
8397 int num = (given >> (single ? 0 : 1)) & 0x7f;
8398 int maxreg = single ? 31 : 15;
8399 int topreg = reg + num - 1;
8400
6576bffe 8401 func (stream, dis_style_text, "{");
efd6b359 8402 if (!num)
6576bffe
AB		 8403 {
8404 /* Nothing. */
8405 }
efd6b359 8406 else if (num == 1)
6576bffe
AB		 8407 {
8408 func (stream, dis_style_register,
8409 "%c%d", reg_prefix, reg);
8410 func (stream, dis_style_text, ", ");
8411 }
efd6b359 8412 else if (topreg > maxreg)
6576bffe
AB		 8413 {
8414 func (stream, dis_style_register, "%c%d",
8415 reg_prefix, reg);
8416 func (stream, dis_style_text, "-<overflow reg d%d, ",
8417 single ? topreg >> 1 : topreg);
8418 }
efd6b359 8419 else
6576bffe
AB		 8420 {
8421 func (stream, dis_style_register,
8422 "%c%d", reg_prefix, reg);
8423 func (stream, dis_style_text, "-");
8424 func (stream, dis_style_register, "%c%d",
8425 reg_prefix, topreg);
8426 func (stream, dis_style_text, ", ");
8427 }
8428 func (stream, dis_style_register, "VPR");
8429 func (stream, dis_style_text, "}");
efd6b359
AV		 8430 }
8431 break;
8432
e2efe87d
MGD		 8433 case 'u':
8434 if (cond != COND_UNCOND)
78933a4a 8435 is_unpredictable = true;
e2efe87d
MGD		 8436
8437 /* Fall through. */
0313a2b8 8438 case 'c':
b0c11777 8439 if (cond != COND_UNCOND && cp_num == 9)
78933a4a 8440 is_unpredictable = true;
b0c11777 8441
aab2c27d
MM		 8442 /* Fall through. */
8443 case 'b':
6576bffe
AB		 8444 func (stream, dis_style_mnemonic, "%s",
8445 arm_conditional[cond]);
0313a2b8 8446 break;
8f06b2d8 8447
0313a2b8
NC		 8448 case 'I':
8449 /* Print a Cirrus/DSP shift immediate. */
8450 /* Immediates are 7bit signed ints with bits 0..3 in
8451 bits 0..3 of opcode and bits 4..6 in bits 5..7
8452 of opcode. */
8453 {
8454 int imm;
8f06b2d8 8455
0313a2b8 8456 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8457
0313a2b8
NC		 8458 /* Is ``imm'' a negative number? */
8459 if (imm & 0x40)
24b4cf66 8460 imm -= 0x80;
8f06b2d8 8461
6576bffe 8462 func (stream, dis_style_immediate, "%d", imm);
0313a2b8
NC		 8463 }
8464
8465 break;
8f06b2d8 8466
32c36c3c
AV		 8467 case 'J':
8468 {
73cd51e5
AV		 8469 unsigned long regno
8470 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8471
8472 switch (regno)
8473 {
8474 case 0x1:
6576bffe 8475 func (stream, dis_style_register, "FPSCR");
32c36c3c
AV		 8476 break;
8477 case 0x2:
6576bffe 8478 func (stream, dis_style_register, "FPSCR_nzcvqc");
32c36c3c
AV		 8479 break;
8480 case 0xc:
6576bffe 8481 func (stream, dis_style_register, "VPR");
32c36c3c
AV		 8482 break;
8483 case 0xd:
6576bffe 8484 func (stream, dis_style_register, "P0");
32c36c3c
AV		 8485 break;
8486 case 0xe:
6576bffe 8487 func (stream, dis_style_register, "FPCXTNS");
32c36c3c
AV		 8488 break;
8489 case 0xf:
6576bffe 8490 func (stream, dis_style_register, "FPCXTS");
32c36c3c
AV		 8491 break;
8492 default:
6576bffe
AB		 8493 func (stream, dis_style_text, "<invalid reg %lu>",
8494 regno);
32c36c3c
AV		 8495 break;
8496 }
8497 }
8498 break;
8499
0313a2b8
NC		 8500 case 'F':
8501 switch (given & 0x00408000)
8502 {
8503 case 0:
6576bffe 8504 func (stream, dis_style_immediate, "4");
0313a2b8
NC		 8505 break;
8506 case 0x8000:
6576bffe 8507 func (stream, dis_style_immediate, "1");
0313a2b8
NC		 8508 break;
8509 case 0x00400000:
6576bffe 8510 func (stream, dis_style_immediate, "2");
8f06b2d8 8511 break;
0313a2b8 8512 default:
6576bffe 8513 func (stream, dis_style_immediate, "3");
0313a2b8
NC		 8514 }
8515 break;
8f06b2d8 8516
0313a2b8
NC		 8517 case 'P':
8518 switch (given & 0x00080080)
8519 {
8520 case 0:
6576bffe 8521 func (stream, dis_style_mnemonic, "s");
0313a2b8
NC		 8522 break;
8523 case 0x80:
6576bffe 8524 func (stream, dis_style_mnemonic, "d");
0313a2b8
NC		 8525 break;
8526 case 0x00080000:
6576bffe 8527 func (stream, dis_style_mnemonic, "e");
0313a2b8
NC		 8528 break;
8529 default:
6576bffe 8530 func (stream, dis_style_text, _("<illegal precision>"));
8f06b2d8 8531 break;
0313a2b8
NC		 8532 }
8533 break;
8f06b2d8 8534
0313a2b8
NC		 8535 case 'Q':
8536 switch (given & 0x00408000)
8537 {
8538 case 0:
6576bffe 8539 func (stream, dis_style_mnemonic, "s");
8f06b2d8 8540 break;
0313a2b8 8541 case 0x8000:
6576bffe 8542 func (stream, dis_style_mnemonic, "d");
8f06b2d8 8543 break;
0313a2b8 8544 case 0x00400000:
6576bffe 8545 func (stream, dis_style_mnemonic, "e");
0313a2b8
NC		 8546 break;
8547 default:
6576bffe 8548 func (stream, dis_style_mnemonic, "p");
8f06b2d8 8549 break;
0313a2b8
NC		 8550 }
8551 break;
8f06b2d8 8552
0313a2b8
NC		 8553 case 'R':
8554 switch (given & 0x60)
8555 {
8556 case 0:
8557 break;
8558 case 0x20:
6576bffe 8559 func (stream, dis_style_mnemonic, "p");
0313a2b8
NC		 8560 break;
8561 case 0x40:
6576bffe 8562 func (stream, dis_style_mnemonic, "m");
0313a2b8
NC		 8563 break;
8564 default:
6576bffe 8565 func (stream, dis_style_mnemonic, "z");
0313a2b8
NC		 8566 break;
8567 }
8568 break;
16980d0b 8569
0313a2b8
NC		 8570 case '0': case '1': case '2': case '3': case '4':
8571 case '5': case '6': case '7': case '8': case '9':
8572 {
8573 int width;
8f06b2d8 8574
0313a2b8 8575 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8576
0313a2b8
NC		 8577 switch (*c)
8578 {
ff4a8d2b
NC		 8579 case 'R':
8580 if (value == 15)
78933a4a 8581 is_unpredictable = true;
ff4a8d2b 8582 /* Fall through. */
0313a2b8 8583 case 'r':
ff4a8d2b
NC		 8584 if (c[1] == 'u')
8585 {
8586 /* Eat the 'u' character. */
8587 ++ c;
8588
8589 if (u_reg == value)
78933a4a 8590 is_unpredictable = true;
ff4a8d2b
NC		 8591 u_reg = value;
8592 }
4575eafb
AB		 8593 func (stream, dis_style_register, "%s",
8594 arm_regnames[value]);
0313a2b8 8595 break;
c28eeff2
SN		 8596 case 'V':
8597 if (given & (1 << 6))
8598 goto Q;
8599 /* FALLTHROUGH */
0313a2b8 8600 case 'D':
6576bffe 8601 func (stream, dis_style_register, "d%ld", value);
0313a2b8
NC		 8602 break;
8603 case 'Q':
c28eeff2 8604 Q:
0313a2b8 8605 if (value & 1)
6576bffe
AB		 8606 func (stream, dis_style_text,
8607 "<illegal reg q%ld.5>", value >> 1);
0313a2b8 8608 else
6576bffe
AB		 8609 func (stream, dis_style_register,
8610 "q%ld", value >> 1);
0313a2b8
NC		 8611 break;
8612 case 'd':
6576bffe 8613 func (stream, base_style, "%ld", value);
05413229 8614 value_in_comment = value;
0313a2b8 8615 break;
6f1c2142
AM		 8616 case 'E':
8617 {
8618 /* Converts immediate 8 bit back to float value. */
8619 unsigned floatVal = (value & 0x80) << 24
8620 | (value & 0x3F) << 19
8621 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8622
8623 /* Quarter float have a maximum value of 31.0.
8624 Get floating point value multiplied by 1e7.
8625 The maximum value stays in limit of a 32-bit int. */
8626 unsigned decVal =
8627 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8628 (16 + (value & 0xF));
8629
8630 if (!(decVal % 1000000))
6576bffe
AB		 8631 {
8632 func (stream, dis_style_immediate, "%ld", value);
8633 func (stream, dis_style_comment_start,
8634 "\t@ 0x%08x %c%u.%01u",
8635 floatVal, value & 0x80 ? '-' : ' ',
8636 decVal / 10000000,
8637 decVal % 10000000 / 1000000);
8638 }
6f1c2142 8639 else if (!(decVal % 10000))
6576bffe
AB		 8640 {
8641 func (stream, dis_style_immediate, "%ld", value);
8642 func (stream, dis_style_comment_start,
8643 "\t@ 0x%08x %c%u.%03u",
8644 floatVal, value & 0x80 ? '-' : ' ',
8645 decVal / 10000000,
8646 decVal % 10000000 / 10000);
8647 }
6f1c2142 8648 else
6576bffe
AB		 8649 {
8650 func (stream, dis_style_immediate, "%ld", value);
8651 func (stream, dis_style_comment_start,
8652 "\t@ 0x%08x %c%u.%07u",
8653 floatVal, value & 0x80 ? '-' : ' ',
8654 decVal / 10000000, decVal % 10000000);
8655 }
6f1c2142
AM		 8656 break;
8657 }
0313a2b8
NC		 8658 case 'k':
8659 {
8660 int from = (given & (1 << 7)) ? 32 : 16;
6576bffe
AB		 8661 func (stream, dis_style_immediate, "%ld",
8662 from - value);
0313a2b8
NC		 8663 }
8664 break;
8f06b2d8 8665
0313a2b8
NC		 8666 case 'f':
8667 if (value > 7)
6576bffe
AB		 8668 func (stream, dis_style_immediate, "#%s",
8669 arm_fp_const[value & 7]);
0313a2b8 8670 else
6576bffe 8671 func (stream, dis_style_register, "f%ld", value);
0313a2b8 8672 break;
4146fd53 8673
0313a2b8
NC		 8674 case 'w':
8675 if (width == 2)
6576bffe
AB		 8676 func (stream, dis_style_mnemonic, "%s",
8677 iwmmxt_wwnames[value]);
0313a2b8 8678 else
6576bffe
AB		 8679 func (stream, dis_style_mnemonic, "%s",
8680 iwmmxt_wwssnames[value]);
0313a2b8 8681 break;
4146fd53 8682
0313a2b8 8683 case 'g':
6576bffe
AB		 8684 func (stream, dis_style_register, "%s",
8685 iwmmxt_regnames[value]);
0313a2b8
NC		 8686 break;
8687 case 'G':
6576bffe
AB		 8688 func (stream, dis_style_register, "%s",
8689 iwmmxt_cregnames[value]);
16980d0b 8690 break;
8f06b2d8 8691
0313a2b8 8692 case 'x':
6576bffe
AB		 8693 func (stream, dis_style_immediate, "0x%lx",
8694 (value & 0xffffffffUL));
0313a2b8 8695 break;
8f06b2d8 8696
33399f07
MGD		 8697 case 'c':
8698 switch (value)
8699 {
8700 case 0:
6576bffe 8701 func (stream, dis_style_mnemonic, "eq");
33399f07
MGD		 8702 break;
8703
8704 case 1:
6576bffe 8705 func (stream, dis_style_mnemonic, "vs");
33399f07
MGD		 8706 break;
8707
8708 case 2:
6576bffe 8709 func (stream, dis_style_mnemonic, "ge");
33399f07
MGD		 8710 break;
8711
8712 case 3:
6576bffe 8713 func (stream, dis_style_mnemonic, "gt");
33399f07
MGD		 8714 break;
8715
8716 default:
6576bffe 8717 func (stream, dis_style_text, "??");
33399f07
MGD		 8718 break;
8719 }
8720 break;
8721
0313a2b8
NC		 8722 case '`':
8723 c++;
8724 if (value == 0)
6576bffe 8725 func (stream, dis_style_mnemonic, "%c", *c);
0313a2b8
NC		 8726 break;
8727 case '\'':
8728 c++;
8729 if (value == ((1ul << width) - 1))
6576bffe 8730 func (stream, base_style, "%c", *c);
0313a2b8
NC		 8731 break;
8732 case '?':
6576bffe
AB		 8733 func (stream, base_style, "%c",
8734 c[(1 << width) - (int) value]);
0313a2b8
NC		 8735 c += 1 << width;
8736 break;
8737 default:
8738 abort ();
8739 }
dffaa15c
AM		 8740 }
8741 break;
0313a2b8 8742
dffaa15c
AM		 8743 case 'y':
8744 case 'z':
8745 {
8746 int single = *c++ == 'y';
8747 int regno;
8f06b2d8 8748
dffaa15c
AM		 8749 switch (*c)
8750 {
8751 case '4': /* Sm pair */
8752 case '0': /* Sm, Dm */
8753 regno = given & 0x0000000f;
8754 if (single)
8755 {
8756 regno <<= 1;
8757 regno += (given >> 5) & 1;
8758 }
8759 else
8760 regno += ((given >> 5) & 1) << 4;
8761 break;
8f06b2d8 8762
dffaa15c
AM		 8763 case '1': /* Sd, Dd */
8764 regno = (given >> 12) & 0x0000000f;
8765 if (single)
8766 {
8767 regno <<= 1;
8768 regno += (given >> 22) & 1;
8769 }
8770 else
8771 regno += ((given >> 22) & 1) << 4;
8772 break;
7df76b80 8773
dffaa15c
AM		 8774 case '2': /* Sn, Dn */
8775 regno = (given >> 16) & 0x0000000f;
8776 if (single)
8777 {
8778 regno <<= 1;
8779 regno += (given >> 7) & 1;
8780 }
8781 else
8782 regno += ((given >> 7) & 1) << 4;
8783 break;
a7f8487e 8784
dffaa15c 8785 case '3': /* List */
6576bffe 8786 func (stream, dis_style_text, "{");
dffaa15c
AM		 8787 regno = (given >> 12) & 0x0000000f;
8788 if (single)
8789 {
8790 regno <<= 1;
8791 regno += (given >> 22) & 1;
8792 }
8793 else
8794 regno += ((given >> 22) & 1) << 4;
8795 break;
a7f8487e 8796
dffaa15c
AM		 8797 default:
8798 abort ();
8799 }
0313a2b8 8800
6576bffe
AB		 8801 func (stream, dis_style_register, "%c%d",
8802 single ? 's' : 'd', regno);
a7f8487e 8803
dffaa15c
AM		 8804 if (*c == '3')
8805 {
8806 int count = given & 0xff;
b34976b6 8807
dffaa15c
AM		 8808 if (single == 0)
8809 count >>= 1;
0313a2b8 8810
dffaa15c
AM		 8811 if (--count)
8812 {
6576bffe
AB		 8813 func (stream, dis_style_text, "-");
8814 func (stream, dis_style_register, "%c%d",
dffaa15c
AM		 8815 single ? 's' : 'd',
8816 regno + count);
8817 }
0313a2b8 8818
6576bffe 8819 func (stream, dis_style_text, "}");
0313a2b8 8820 }
dffaa15c 8821 else if (*c == '4')
6576bffe
AB		 8822 {
8823 func (stream, dis_style_text, ", ");
8824 func (stream, dis_style_register, "%c%d",
8825 single ? 's' : 'd', regno + 1);
8826 }
dffaa15c
AM		 8827 }
8828 break;
b34976b6 8829
dffaa15c
AM		 8830 case 'L':
8831 switch (given & 0x00400100)
0313a2b8 8832 {
6576bffe
AB		 8833 case 0x00000000:
8834 func (stream, dis_style_mnemonic, "b");
8835 break;
8836 case 0x00400000:
8837 func (stream, dis_style_mnemonic, "h");
8838 break;
8839 case 0x00000100:
8840 func (stream, dis_style_mnemonic, "w");
8841 break;
8842 case 0x00400100:
8843 func (stream, dis_style_mnemonic, "d");
8844 break;
dffaa15c
AM		 8845 default:
8846 break;
0313a2b8 8847 }
dffaa15c 8848 break;
2d447fca 8849
dffaa15c
AM		 8850 case 'Z':
8851 {
8852 /* given (20, 23) | given (0, 3) */
8853 value = ((given >> 16) & 0xf0) | (given & 0xf);
6576bffe 8854 func (stream, dis_style_immediate, "%d", (int) value);
dffaa15c
AM		 8855 }
8856 break;
0313a2b8 8857
dffaa15c
AM		 8858 case 'l':
8859 /* This is like the 'A' operator, except that if
8860 the width field "M" is zero, then the offset is
8861 *not* multiplied by four. */
8862 {
8863 int offset = given & 0xff;
8864 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8865
6576bffe
AB		 8866 func (stream, dis_style_text, "[");
8867 func (stream, dis_style_register, "%s",
8868 arm_regnames [(given >> 16) & 0xf]);
05413229 8869
dffaa15c
AM		 8870 if (multiplier > 1)
8871 {
8872 value_in_comment = offset * multiplier;
8873 if (NEGATIVE_BIT_SET)
8874 value_in_comment = - value_in_comment;
8875 }
0313a2b8 8876
dffaa15c
AM		 8877 if (offset)
8878 {
8879 if (PRE_BIT_SET)
6576bffe
AB		 8880 {
8881 func (stream, dis_style_text, ", ");
8882 func (stream, dis_style_immediate, "#%s%d",
8883 NEGATIVE_BIT_SET ? "-" : "",
8884 offset * multiplier);
8885 func (stream, dis_style_text, "]%s",
8886 WRITEBACK_BIT_SET ? "!" : "");
8887 }
dffaa15c 8888 else
6576bffe
AB		 8889 {
8890 func (stream, dis_style_text, "], ");
8891 func (stream, dis_style_immediate, "#%s%d",
8892 NEGATIVE_BIT_SET ? "-" : "",
8893 offset * multiplier);
8894 }
dffaa15c
AM		 8895 }
8896 else
6576bffe 8897 func (stream, dis_style_text, "]");
dffaa15c
AM		 8898 }
8899 break;
2d447fca 8900
dffaa15c
AM		 8901 case 'r':
8902 {
8903 int imm4 = (given >> 4) & 0xf;
8904 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8905 int ubit = ! NEGATIVE_BIT_SET;
8906 const char *rm = arm_regnames [given & 0xf];
8907 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8908
dffaa15c
AM		 8909 switch (puw_bits)
8910 {
8911 case 1:
8912 case 3:
6576bffe
AB		 8913 func (stream, dis_style_text, "[");
8914 func (stream, dis_style_register, "%s", rn);
8915 func (stream, dis_style_text, "], ");
8916 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8917 func (stream, dis_style_register, "%s", rm);
dffaa15c 8918 if (imm4)
6576bffe
AB		 8919 {
8920 func (stream, dis_style_text, ", ");
8921 func (stream, dis_style_sub_mnemonic, "lsl ");
8922 func (stream, dis_style_immediate, "#%d", imm4);
8923 }
dffaa15c 8924 break;
0313a2b8 8925
dffaa15c
AM		 8926 case 4:
8927 case 5:
8928 case 6:
8929 case 7:
6576bffe
AB		 8930 func (stream, dis_style_text, "[");
8931 func (stream, dis_style_register, "%s", rn);
8932 func (stream, dis_style_text, ", ");
8933 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8934 func (stream, dis_style_register, "%s", rm);
dffaa15c 8935 if (imm4 > 0)
6576bffe
AB		 8936 {
8937 func (stream, dis_style_text, ", ");
8938 func (stream, dis_style_sub_mnemonic, "lsl ");
8939 func (stream, dis_style_immediate, "#%d", imm4);
8940 }
8941 func (stream, dis_style_text, "]");
dffaa15c 8942 if (puw_bits == 5 || puw_bits == 7)
6576bffe 8943 func (stream, dis_style_text, "!");
dffaa15c 8944 break;
2d447fca 8945
dffaa15c 8946 default:
6576bffe 8947 func (stream, dis_style_text, "INVALID");
dffaa15c
AM		 8948 }
8949 }
8950 break;
0313a2b8 8951
dffaa15c
AM		 8952 case 'i':
8953 {
8954 long imm5;
8955 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
6576bffe
AB		 8956 func (stream, dis_style_immediate, "%ld",
8957 (imm5 == 0) ? 32 : imm5);
0313a2b8 8958 }
dffaa15c
AM		 8959 break;
8960
8961 default:
8962 abort ();
252b5132 8963 }
252b5132 8964 }
0313a2b8 8965 else
6576bffe
AB		 8966 {
8967 if (*c == '@')
8968 base_style = dis_style_comment_start;
8969
8970 if (*c == '\t')
8971 base_style = dis_style_text;
8972
8973 func (stream, base_style, "%c", *c);
8974 }
252b5132 8975 }
05413229
NC		 8976
8977 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 8978 func (stream, dis_style_comment_start, "\t@ 0x%lx",
8979 (value_in_comment & 0xffffffffUL));
05413229 8980
ff4a8d2b 8981 if (is_unpredictable)
6576bffe 8982 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 8983
78933a4a 8984 return true;
252b5132 8985 }
78933a4a 8986 return false;
252b5132
RH		 8987}
8988
78933a4a 8989static bool
33593eaf
MM		 8990print_insn_coprocessor (bfd_vma pc,
8991 struct disassemble_info *info,
8992 long given,
78933a4a 8993 bool thumb)
33593eaf
MM		 8994{
8995 return print_insn_coprocessor_1 (coprocessor_opcodes,
8996 pc, info, given, thumb);
8997}
8998
78933a4a 8999static bool
33593eaf
MM		 9000print_insn_generic_coprocessor (bfd_vma pc,
9001 struct disassemble_info *info,
9002 long given,
78933a4a 9003 bool thumb)
33593eaf
MM		 9004{
9005 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
9006 pc, info, given, thumb);
9007}
9008
05413229
NC		 9009/* Decodes and prints ARM addressing modes. Returns the offset
9010 used in the address, if any, if it is worthwhile printing the
9011 offset as a hexadecimal value in a comment at the end of the
9012 line of disassembly. */
9013
9014static signed long
62b3e311
PB		 9015print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
9016{
9017 void *stream = info->stream;
6576bffe 9018 fprintf_styled_ftype func = info->fprintf_styled_func;
f8b960bc 9019 bfd_vma offset = 0;
62b3e311
PB		 9020
9021 if (((given & 0x000f0000) == 0x000f0000)
9022 && ((given & 0x02000000) == 0))
9023 {
05413229 9024 offset = given & 0xfff;
62b3e311 9025
6576bffe
AB		 9026 func (stream, dis_style_text, "[");
9027 func (stream, dis_style_register, "pc");
62b3e311 9028
c1e26897 9029 if (PRE_BIT_SET)
62b3e311 9030 {
26d97720
NS		 9031 /* Pre-indexed. Elide offset of positive zero when
9032 non-writeback. */
9033 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 9034 {
9035 func (stream, dis_style_text, ", ");
9036 func (stream, dis_style_immediate, "#%s%d",
9037 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9038 }
26d97720
NS		 9039
9040 if (NEGATIVE_BIT_SET)
9041 offset = -offset;
62b3e311
PB		 9042
9043 offset += pc + 8;
9044
9045 /* Cope with the possibility of write-back
9046 being used. Probably a very dangerous thing
9047 for the programmer to do, but who are we to
9048 argue ? */
6576bffe 9049 func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 9050 }
c1e26897 9051 else /* Post indexed. */
62b3e311 9052 {
6576bffe
AB		 9053 func (stream, dis_style_text, "], ");
9054 func (stream, dis_style_immediate, "#%s%d",
9055 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 9056
c1e26897 9057 /* Ie ignore the offset. */
62b3e311
PB		 9058 offset = pc + 8;
9059 }
9060
6576bffe 9061 func (stream, dis_style_comment_start, "\t@ ");
62b3e311 9062 info->print_address_func (offset, info);
05413229 9063 offset = 0;
62b3e311
PB		 9064 }
9065 else
9066 {
6576bffe
AB		 9067 func (stream, dis_style_text, "[");
9068 func (stream, dis_style_register, "%s",
62b3e311 9069 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 9070
9071 if (PRE_BIT_SET)
62b3e311
PB		 9072 {
9073 if ((given & 0x02000000) == 0)
9074 {
26d97720 9075 /* Elide offset of positive zero when non-writeback. */
05413229 9076 offset = given & 0xfff;
26d97720 9077 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 9078 {
9079 func (stream, dis_style_text, ", ");
9080 func (stream, dis_style_immediate, "#%s%d",
9081 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9082 }
62b3e311
PB		 9083 }
9084 else
9085 {
6576bffe
AB		 9086 func (stream, dis_style_text, ", %s",
9087 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 9088 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 9089 }
9090
6576bffe 9091 func (stream, dis_style_text, "]%s",
c1e26897 9092 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 9093 }
9094 else
9095 {
9096 if ((given & 0x02000000) == 0)
9097 {
26d97720 9098 /* Always show offset. */
05413229 9099 offset = given & 0xfff;
6576bffe
AB		 9100 func (stream, dis_style_text, "], ");
9101 func (stream, dis_style_immediate, "#%s%d",
d908c8af 9102 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 9103 }
9104 else
9105 {
6576bffe 9106 func (stream, dis_style_text, "], %s",
c1e26897 9107 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 9108 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 9109 }
9110 }
84919466
MR		 9111 if (NEGATIVE_BIT_SET)
9112 offset = -offset;
62b3e311 9113 }
05413229
NC		 9114
9115 return (signed long) offset;
62b3e311
PB		 9116}
9117
4934a27c
MM		 9118
9119/* Print one cde instruction on INFO->STREAM.
9120 Return TRUE if the instuction matched, FALSE if this is not a
9121 recognised cde instruction. */
78933a4a
AM		 9122static bool
9123print_insn_cde (struct disassemble_info *info, long given, bool thumb)
4934a27c
MM		 9124{
9125 const struct cdeopcode32 *insn;
9126 void *stream = info->stream;
6576bffe
AB		 9127 fprintf_styled_ftype func = info->fprintf_styled_func;
9128 enum disassembler_style base_style = dis_style_mnemonic;
9129 enum disassembler_style old_base_style = base_style;
4934a27c
MM		 9130
9131 if (thumb)
9132 {
9133 /* Manually extract the coprocessor code from a known point.
9134 This position is the same across all CDE instructions. */
9135 for (insn = cde_opcodes; insn->assembler; insn++)
9136 {
9137 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
9138 uint16_t coproc_mask = 1 << coproc;
9139 if (! (coproc_mask & cde_coprocs))
9140 continue;
9141
9142 if ((given & insn->mask) == insn->value)
9143 {
78933a4a 9144 bool is_unpredictable = false;
4934a27c
MM		 9145 const char *c;
9146
9147 for (c = insn->assembler; *c; c++)
9148 {
9149 if (*c == '%')
9150 {
9151 switch (*++c)
9152 {
6576bffe
AB		 9153 case '{':
9154 ++c;
9155 if (*c == '\0')
9156 abort ();
9157 old_base_style = base_style;
9158 base_style = decode_base_style (*c);
9159 ++c;
9160 if (*c != ':')
9161 abort ();
9162 break;
9163
9164 case '}':
9165 base_style = old_base_style;
9166 break;
9167
4934a27c 9168 case '%':
6576bffe 9169 func (stream, base_style, "%%");
4934a27c
MM		 9170 break;
9171
9172 case '0': case '1': case '2': case '3': case '4':
9173 case '5': case '6': case '7': case '8': case '9':
9174 {
9175 int width;
9176 unsigned long value;
9177
9178 c = arm_decode_bitfield (c, given, &value, &width);
9179
9180 switch (*c)
9181 {
9182 case 'S':
9183 if (value > 10)
78933a4a 9184 is_unpredictable = true;
4934a27c
MM		 9185 /* Fall through. */
9186 case 'R':
9187 if (value == 13)
78933a4a 9188 is_unpredictable = true;
4934a27c
MM		 9189 /* Fall through. */
9190 case 'r':
6576bffe
AB		 9191 func (stream, dis_style_register, "%s",
9192 arm_regnames[value]);
4934a27c
MM		 9193 break;
9194
9195 case 'n':
9196 if (value == 15)
6576bffe 9197 func (stream, dis_style_register, "%s", "APSR_nzcv");
4934a27c 9198 else
6576bffe
AB		 9199 func (stream, dis_style_register, "%s",
9200 arm_regnames[value]);
4934a27c
MM		 9201 break;
9202
9203 case 'T':
6576bffe
AB		 9204 func (stream, dis_style_register, "%s",
9205 arm_regnames[(value + 1) & 15]);
4934a27c
MM		 9206 break;
9207
9208 case 'd':
6576bffe 9209 func (stream, dis_style_immediate, "%ld", value);
4934a27c
MM		 9210 break;
9211
5aae9ae9
MM		 9212 case 'V':
9213 if (given & (1 << 6))
6576bffe 9214 func (stream, dis_style_register, "q%ld", value >> 1);
5aae9ae9 9215 else if (given & (1 << 24))
6576bffe 9216 func (stream, dis_style_register, "d%ld", value);
5aae9ae9
MM		 9217 else
9218 {
9219 /* Encoding for S register is different than for D and
9220 Q registers. S registers are encoded using the top
9221 single bit in position 22 as the lowest bit of the
9222 register number, while for Q and D it represents the
9223 highest bit of the register number. */
9224 uint8_t top_bit = (value >> 4) & 1;
9225 uint8_t tmp = (value << 1) & 0x1e;
9226 uint8_t res = tmp | top_bit;
6576bffe 9227 func (stream, dis_style_register, "s%u", res);
5aae9ae9
MM		 9228 }
9229 break;
9230
4934a27c
MM		 9231 default:
9232 abort ();
9233 }
9234 }
9235 break;
9236
9237 case 'p':
9238 {
9239 uint8_t proc_number = (given >> 8) & 0x7;
6576bffe 9240 func (stream, dis_style_register, "p%u", proc_number);
4934a27c
MM		 9241 break;
9242 }
9243
9244 case 'a':
9245 {
9246 uint8_t a_offset = 28;
9247 if (given & (1 << a_offset))
6576bffe 9248 func (stream, dis_style_mnemonic, "a");
4934a27c
MM		 9249 break;
9250 }
9251 default:
9252 abort ();
9253 }
9254 }
9255 else
6576bffe
AB		 9256 {
9257 if (*c == '@')
9258 base_style = dis_style_comment_start;
9259 if (*c == '\t')
9260 base_style = dis_style_text;
9261
9262 func (stream, base_style, "%c", *c);
9263 }
4934a27c
MM		 9264 }
9265
9266 if (is_unpredictable)
6576bffe 9267 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
4934a27c 9268
78933a4a 9269 return true;
4934a27c
MM		 9270 }
9271 }
78933a4a 9272 return false;
4934a27c
MM		 9273 }
9274 else
78933a4a 9275 return false;
4934a27c
MM		 9276}
9277
9278
16980d0b
JB		 9279/* Print one neon instruction on INFO->STREAM.
9280 Return TRUE if the instuction matched, FALSE if this is not a
9281 recognised neon instruction. */
9282
78933a4a
AM		 9283static bool
9284print_insn_neon (struct disassemble_info *info, long given, bool thumb)
16980d0b
JB		 9285{
9286 const struct opcode32 *insn;
9287 void *stream = info->stream;
6576bffe
AB		 9288 fprintf_styled_ftype func = info->fprintf_styled_func;
9289 enum disassembler_style base_style = dis_style_mnemonic;
9290 enum disassembler_style old_base_style = base_style;
16980d0b
JB		 9291
9292 if (thumb)
9293 {
9294 if ((given & 0xef000000) == 0xef000000)
9295 {
0313a2b8 9296 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 9297 unsigned long bit28 = given & (1 << 28);
9298
9299 given &= 0x00ffffff;
9300 if (bit28)
9301 given |= 0xf3000000;
9302 else
9303 given |= 0xf2000000;
9304 }
9305 else if ((given & 0xff000000) == 0xf9000000)
9306 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 9307 /* BFloat16 neon instructions without special top byte handling. */
9308 else if ((given & 0xff000000) == 0xfe000000
9309 || (given & 0xff000000) == 0xfc000000)
9310 ;
9743db03 9311 /* vdup is also a valid neon instruction. */
e409955d 9312 else if ((given & 0xff900f5f) != 0xee800b10)
78933a4a 9313 return false;
16980d0b 9314 }
43e65147 9315
16980d0b
JB		 9316 for (insn = neon_opcodes; insn->assembler; insn++)
9317 {
e409955d
FS		 9318 unsigned long cond_mask = insn->mask;
9319 unsigned long cond_value = insn->value;
9320 int cond;
9321
9322 if (thumb)
9323 {
9324 if ((cond_mask & 0xf0000000) == 0) {
9325 /* For the entries in neon_opcodes, an opcode mask/value with
9326 the high 4 bits equal to 0 indicates a conditional
9327 instruction. For thumb however, we need to include those
9328 bits in the instruction matching. */
9329 cond_mask |= 0xf0000000;
9330 /* Furthermore, the thumb encoding of a conditional instruction
9331 will have the high 4 bits equal to 0xe. */
9332 cond_value |= 0xe0000000;
9333 }
9334 if (ifthen_state)
9335 cond = IFTHEN_COND;
9336 else
9337 cond = COND_UNCOND;
9338 }
9339 else
9340 {
9341 if ((given & 0xf0000000) == 0xf0000000)
9342 {
9343 /* If the instruction is unconditional, update the mask to only
9344 match against unconditional opcode values. */
9345 cond_mask |= 0xf0000000;
9346 cond = COND_UNCOND;
9347 }
9348 else
9349 {
9350 cond = (given >> 28) & 0xf;
9351 if (cond == 0xe)
9352 cond = COND_UNCOND;
9353 }
9354 }
9355
9356 if ((given & cond_mask) == cond_value)
16980d0b 9357 {
05413229 9358 signed long value_in_comment = 0;
78933a4a 9359 bool is_unpredictable = false;
16980d0b
JB		 9360 const char *c;
9361
9362 for (c = insn->assembler; *c; c++)
9363 {
9364 if (*c == '%')
9365 {
9366 switch (*++c)
9367 {
6576bffe
AB		 9368 case '{':
9369 ++c;
9370 if (*c == '\0')
9371 abort ();
9372 old_base_style = base_style;
9373 base_style = decode_base_style (*c);
9374 ++c;
9375 if (*c != ':')
9376 abort ();
9377 break;
9378
9379 case '}':
9380 base_style = old_base_style;
9381 break;
9382
16980d0b 9383 case '%':
6576bffe 9384 func (stream, base_style, "%%");
16980d0b
JB		 9385 break;
9386
e2efe87d
MGD		 9387 case 'u':
9388 if (thumb && ifthen_state)
78933a4a 9389 is_unpredictable = true;
e2efe87d
MGD		 9390
9391 /* Fall through. */
c22aaad1 9392 case 'c':
6576bffe
AB		 9393 func (stream, dis_style_mnemonic, "%s",
9394 arm_conditional[cond]);
c22aaad1
PB		 9395 break;
9396
16980d0b
JB		 9397 case 'A':
9398 {
43e65147 9399 static const unsigned char enc[16] =
16980d0b
JB		 9400 {
9401 0x4, 0x14, /* st4 0,1 */
9402 0x4, /* st1 2 */
9403 0x4, /* st2 3 */
9404 0x3, /* st3 4 */
9405 0x13, /* st3 5 */
9406 0x3, /* st1 6 */
9407 0x1, /* st1 7 */
9408 0x2, /* st2 8 */
9409 0x12, /* st2 9 */
9410 0x2, /* st1 10 */
9411 0, 0, 0, 0, 0
9412 };
9413 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9414 int rn = ((given >> 16) & 0xf);
9415 int rm = ((given >> 0) & 0xf);
9416 int align = ((given >> 4) & 0x3);
9417 int type = ((given >> 8) & 0xf);
9418 int n = enc[type] & 0xf;
9419 int stride = (enc[type] >> 4) + 1;
9420 int ix;
43e65147 9421
6576bffe 9422 func (stream, dis_style_text, "{");
16980d0b
JB		 9423 if (stride > 1)
9424 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9425 {
9426 if (ix > 0)
9427 func (stream, dis_style_text, ",");
9428 func (stream, dis_style_register, "d%d",
9429 rd + ix * stride);
9430 }
16980d0b 9431 else if (n == 1)
6576bffe 9432 func (stream, dis_style_register, "d%d", rd);
16980d0b 9433 else
6576bffe
AB		 9434 {
9435 func (stream, dis_style_register, "d%d", rd);
9436 func (stream, dis_style_text, "-");
9437 func (stream, dis_style_register, "d%d",
9438 rd + n - 1);
9439 }
9440 func (stream, dis_style_text, "}, [");
9441 func (stream, dis_style_register, "%s",
9442 arm_regnames[rn]);
16980d0b 9443 if (align)
6576bffe
AB		 9444 {
9445 func (stream, dis_style_text, " :");
9446 func (stream, dis_style_immediate, "%d",
9447 32 << align);
9448 }
9449 func (stream, dis_style_text, "]");
16980d0b 9450 if (rm == 0xd)
6576bffe 9451 func (stream, dis_style_text, "!");
16980d0b 9452 else if (rm != 0xf)
6576bffe
AB		 9453 {
9454 func (stream, dis_style_text, ", ");
9455 func (stream, dis_style_register, "%s",
9456 arm_regnames[rm]);
9457 }
16980d0b
JB		 9458 }
9459 break;
43e65147 9460
16980d0b
JB		 9461 case 'B':
9462 {
9463 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9464 int rn = ((given >> 16) & 0xf);
9465 int rm = ((given >> 0) & 0xf);
9466 int idx_align = ((given >> 4) & 0xf);
9467 int align = 0;
9468 int size = ((given >> 10) & 0x3);
9469 int idx = idx_align >> (size + 1);
9470 int length = ((given >> 8) & 3) + 1;
9471 int stride = 1;
9472 int i;
9473
9474 if (length > 1 && size > 0)
9475 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9476
16980d0b
JB		 9477 switch (length)
9478 {
9479 case 1:
9480 {
9481 int amask = (1 << size) - 1;
9482 if ((idx_align & (1 << size)) != 0)
78933a4a 9483 return false;
16980d0b
JB		 9484 if (size > 0)
9485 {
9486 if ((idx_align & amask) == amask)
9487 align = 8 << size;
9488 else if ((idx_align & amask) != 0)
78933a4a 9489 return false;
16980d0b
JB		 9490 }
9491 }
9492 break;
43e65147 9493
16980d0b
JB		 9494 case 2:
9495 if (size == 2 && (idx_align & 2) != 0)
78933a4a 9496 return false;
16980d0b
JB		 9497 align = (idx_align & 1) ? 16 << size : 0;
9498 break;
43e65147 9499
16980d0b
JB		 9500 case 3:
9501 if ((size == 2 && (idx_align & 3) != 0)
9502 || (idx_align & 1) != 0)
78933a4a 9503 return false;
16980d0b 9504 break;
43e65147 9505
16980d0b
JB		 9506 case 4:
9507 if (size == 2)
9508 {
9509 if ((idx_align & 3) == 3)
78933a4a 9510 return false;
16980d0b
JB		 9511 align = (idx_align & 3) * 64;
9512 }
9513 else
9514 align = (idx_align & 1) ? 32 << size : 0;
9515 break;
43e65147 9516
16980d0b
JB		 9517 default:
9518 abort ();
9519 }
43e65147 9520
6576bffe 9521 func (stream, dis_style_text, "{");
16980d0b 9522 for (i = 0; i < length; i++)
6576bffe
AB		 9523 {
9524 if (i > 0)
9525 func (stream, dis_style_text, ",");
9526 func (stream, dis_style_register, "d%d[%d]",
9527 rd + i * stride, idx);
9528 }
9529 func (stream, dis_style_text, "}, [");
9530 func (stream, dis_style_register, "%s",
9531 arm_regnames[rn]);
16980d0b 9532 if (align)
6576bffe
AB		 9533 {
9534 func (stream, dis_style_text, " :");
9535 func (stream, dis_style_immediate, "%d", align);
9536 }
9537 func (stream, dis_style_text, "]");
16980d0b 9538 if (rm == 0xd)
6576bffe 9539 func (stream, dis_style_text, "!");
16980d0b 9540 else if (rm != 0xf)
6576bffe
AB		 9541 {
9542 func (stream, dis_style_text, ", ");
9543 func (stream, dis_style_register, "%s",
9544 arm_regnames[rm]);
9545 }
16980d0b
JB		 9546 }
9547 break;
43e65147 9548
16980d0b
JB		 9549 case 'C':
9550 {
9551 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9552 int rn = ((given >> 16) & 0xf);
9553 int rm = ((given >> 0) & 0xf);
9554 int align = ((given >> 4) & 0x1);
9555 int size = ((given >> 6) & 0x3);
9556 int type = ((given >> 8) & 0x3);
9557 int n = type + 1;
9558 int stride = ((given >> 5) & 0x1);
9559 int ix;
43e65147 9560
16980d0b
JB		 9561 if (stride && (n == 1))
9562 n++;
9563 else
9564 stride++;
43e65147 9565
6576bffe 9566 func (stream, dis_style_text, "{");
16980d0b
JB		 9567 if (stride > 1)
9568 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9569 {
9570 if (ix > 0)
9571 func (stream, dis_style_text, ",");
9572 func (stream, dis_style_register, "d%d[]",
9573 rd + ix * stride);
9574 }
16980d0b 9575 else if (n == 1)
6576bffe 9576 func (stream, dis_style_register, "d%d[]", rd);
16980d0b 9577 else
6576bffe
AB		 9578 {
9579 func (stream, dis_style_register, "d%d[]", rd);
9580 func (stream, dis_style_text, "-");
9581 func (stream, dis_style_register, "d%d[]",
9582 rd + n - 1);
9583 }
9584 func (stream, dis_style_text, "}, [");
9585 func (stream, dis_style_register, "%s",
9586 arm_regnames[rn]);
16980d0b
JB		 9587 if (align)
9588 {
91d6fa6a 9589 align = (8 * (type + 1)) << size;
16980d0b
JB		 9590 if (type == 3)
9591 align = (size > 1) ? align >> 1 : align;
9592 if (type == 2 || (type == 0 && !size))
6576bffe
AB		 9593 func (stream, dis_style_text,
9594 " :<bad align %d>", align);
16980d0b 9595 else
6576bffe
AB		 9596 {
9597 func (stream, dis_style_text, " :");
9598 func (stream, dis_style_immediate,
9599 "%d", align);
9600 }
16980d0b 9601 }
6576bffe 9602 func (stream, dis_style_text, "]");
16980d0b 9603 if (rm == 0xd)
6576bffe 9604 func (stream, dis_style_text, "!");
16980d0b 9605 else if (rm != 0xf)
6576bffe
AB		 9606 {
9607 func (stream, dis_style_text, ", ");
9608 func (stream, dis_style_register, "%s",
9609 arm_regnames[rm]);
9610 }
16980d0b
JB		 9611 }
9612 break;
43e65147 9613
16980d0b
JB		 9614 case 'D':
9615 {
9616 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9617 int size = (given >> 20) & 3;
9618 int reg = raw_reg & ((4 << size) - 1);
9619 int ix = raw_reg >> size >> 2;
43e65147 9620
6576bffe 9621 func (stream, dis_style_register, "d%d[%d]", reg, ix);
16980d0b
JB		 9622 }
9623 break;
43e65147 9624
16980d0b 9625 case 'E':
fe56b6ce 9626 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9627 {
9628 int bits = 0;
9629 int cmode = (given >> 8) & 0xf;
9630 int op = (given >> 5) & 0x1;
9631 unsigned long value = 0, hival = 0;
9632 unsigned shift;
9633 int size = 0;
0dbde4cf 9634 int isfloat = 0;
43e65147 9635
16980d0b
JB		 9636 bits |= ((given >> 24) & 1) << 7;
9637 bits |= ((given >> 16) & 7) << 4;
9638 bits |= ((given >> 0) & 15) << 0;
43e65147 9639
16980d0b
JB		 9640 if (cmode < 8)
9641 {
9642 shift = (cmode >> 1) & 3;
fe56b6ce 9643 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9644 size = 32;
9645 }
9646 else if (cmode < 12)
9647 {
9648 shift = (cmode >> 1) & 1;
fe56b6ce 9649 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9650 size = 16;
9651 }
9652 else if (cmode < 14)
9653 {
9654 shift = (cmode & 1) + 1;
fe56b6ce 9655 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9656 value |= (1ul << (8 * shift)) - 1;
9657 size = 32;
9658 }
9659 else if (cmode == 14)
9660 {
9661 if (op)
9662 {
fe56b6ce 9663 /* Bit replication into bytes. */
16980d0b
JB		 9664 int ix;
9665 unsigned long mask;
43e65147 9666
16980d0b
JB		 9667 value = 0;
9668 hival = 0;
9669 for (ix = 7; ix >= 0; ix--)
9670 {
9671 mask = ((bits >> ix) & 1) ? 0xff : 0;
9672 if (ix <= 3)
9673 value = (value << 8) | mask;
9674 else
9675 hival = (hival << 8) | mask;
9676 }
9677 size = 64;
9678 }
9679 else
9680 {
fe56b6ce
NC		 9681 /* Byte replication. */
9682 value = (unsigned long) bits;
16980d0b
JB		 9683 size = 8;
9684 }
9685 }
9686 else if (!op)
9687 {
fe56b6ce 9688 /* Floating point encoding. */
16980d0b 9689 int tmp;
43e65147 9690
fe56b6ce
NC		 9691 value = (unsigned long) (bits & 0x7f) << 19;
9692 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9693 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9694 value |= (unsigned long) tmp << 24;
16980d0b 9695 size = 32;
0dbde4cf 9696 isfloat = 1;
16980d0b
JB		 9697 }
9698 else
9699 {
6576bffe
AB		 9700 func (stream, dis_style_text,
9701 "<illegal constant %.8x:%x:%x>",
16980d0b
JB		 9702 bits, cmode, op);
9703 size = 32;
9704 break;
9705 }
9706 switch (size)
9707 {
9708 case 8:
6576bffe
AB		 9709 func (stream, dis_style_immediate, "#%ld", value);
9710 func (stream, dis_style_comment_start,
9711 "\t@ 0x%.2lx", value);
16980d0b 9712 break;
43e65147 9713
16980d0b 9714 case 16:
6576bffe
AB		 9715 func (stream, dis_style_immediate, "#%ld", value);
9716 func (stream, dis_style_comment_start,
9717 "\t@ 0x%.4lx", value);
16980d0b
JB		 9718 break;
9719
9720 case 32:
0dbde4cf
JB		 9721 if (isfloat)
9722 {
9723 unsigned char valbytes[4];
9724 double fvalue;
43e65147 9725
0dbde4cf
JB		 9726 /* Do this a byte at a time so we don't have to
9727 worry about the host's endianness. */
9728 valbytes[0] = value & 0xff;
9729 valbytes[1] = (value >> 8) & 0xff;
9730 valbytes[2] = (value >> 16) & 0xff;
9731 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9732
9733 floatformat_to_double
c1e26897
NC		 9734 (& floatformat_ieee_single_little, valbytes,
9735 & fvalue);
43e65147 9736
6576bffe
AB		 9737 func (stream, dis_style_immediate,
9738 "#%.7g", fvalue);
9739 func (stream, dis_style_comment_start,
9740 "\t@ 0x%.8lx", value);
0dbde4cf
JB		 9741 }
9742 else
6576bffe
AB		 9743 {
9744 func (stream, dis_style_immediate, "#%ld",
9745 (long) (((value & 0x80000000L) != 0)
9746 ? value | ~0xffffffffL : value));
9747 func (stream, dis_style_comment_start,
9748 "\t@ 0x%.8lx", value);
9749 }
16980d0b
JB		 9750 break;
9751
9752 case 64:
6576bffe
AB		 9753 func (stream, dis_style_immediate,
9754 "#0x%.8lx%.8lx", hival, value);
16980d0b 9755 break;
43e65147 9756
16980d0b
JB		 9757 default:
9758 abort ();
9759 }
9760 }
9761 break;
43e65147 9762
16980d0b
JB		 9763 case 'F':
9764 {
9765 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9766 int num = (given >> 8) & 0x3;
43e65147 9767
6576bffe 9768 func (stream, dis_style_text, "{");
16980d0b 9769 if (!num)
6576bffe 9770 func (stream, dis_style_register, "d%d", regno);
16980d0b 9771 else if (num + regno >= 32)
6576bffe
AB		 9772 {
9773 func (stream, dis_style_register, "d%d", regno);
9774 func (stream, dis_style_text, "-<overflow reg d%d",
9775 regno + num);
9776 }
16980d0b 9777 else
6576bffe
AB		 9778 {
9779 func (stream, dis_style_register, "d%d", regno);
9780 func (stream, dis_style_text, "-");
9781 func (stream, dis_style_register, "d%d",
9782 regno + num);
9783 }
9784 func (stream, dis_style_text, "}");
16980d0b
JB		 9785 }
9786 break;
7e8e6784 9787
16980d0b
JB		 9788
9789 case '0': case '1': case '2': case '3': case '4':
9790 case '5': case '6': case '7': case '8': case '9':
9791 {
9792 int width;
9793 unsigned long value;
9794
9795 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9796
16980d0b
JB		 9797 switch (*c)
9798 {
9799 case 'r':
6576bffe
AB		 9800 func (stream, dis_style_register, "%s",
9801 arm_regnames[value]);
16980d0b
JB		 9802 break;
9803 case 'd':
6576bffe 9804 func (stream, base_style, "%ld", value);
05413229 9805 value_in_comment = value;
16980d0b
JB		 9806 break;
9807 case 'e':
6576bffe
AB		 9808 func (stream, dis_style_immediate, "%ld",
9809 (1ul << width) - value);
16980d0b 9810 break;
43e65147 9811
16980d0b
JB		 9812 case 'S':
9813 case 'T':
9814 case 'U':
05413229 9815 /* Various width encodings. */
16980d0b
JB		 9816 {
9817 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9818 int limit;
9819 unsigned low, high;
9820
9821 c++;
9822 if (*c >= '0' && *c <= '9')
9823 limit = *c - '0';
9824 else if (*c >= 'a' && *c <= 'f')
9825 limit = *c - 'a' + 10;
9826 else
9827 abort ();
9828 low = limit >> 2;
9829 high = limit & 3;
9830
9831 if (value < low || value > high)
6576bffe
AB		 9832 func (stream, dis_style_text,
9833 "<illegal width %d>", base << value);
16980d0b 9834 else
6576bffe
AB		 9835 func (stream, base_style, "%d",
9836 base << value);
16980d0b
JB		 9837 }
9838 break;
9839 case 'R':
9840 if (given & (1 << 6))
9841 goto Q;
9842 /* FALLTHROUGH */
9843 case 'D':
6576bffe 9844 func (stream, dis_style_register, "d%ld", value);
16980d0b
JB		 9845 break;
9846 case 'Q':
9847 Q:
9848 if (value & 1)
6576bffe
AB		 9849 func (stream, dis_style_text,
9850 "<illegal reg q%ld.5>", value >> 1);
16980d0b 9851 else
6576bffe
AB		 9852 func (stream, dis_style_register,
9853 "q%ld", value >> 1);
16980d0b 9854 break;
43e65147 9855
16980d0b
JB		 9856 case '`':
9857 c++;
9858 if (value == 0)
6576bffe 9859 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9860 break;
9861 case '\'':
9862 c++;
9863 if (value == ((1ul << width) - 1))
6576bffe 9864 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9865 break;
9866 case '?':
6576bffe
AB		 9867 func (stream, dis_style_mnemonic, "%c",
9868 c[(1 << width) - (int) value]);
16980d0b
JB		 9869 c += 1 << width;
9870 break;
9871 default:
9872 abort ();
9873 }
16980d0b 9874 }
dffaa15c
AM		 9875 break;
9876
9877 default:
9878 abort ();
16980d0b
JB		 9879 }
9880 }
9881 else
6576bffe
AB		 9882 {
9883 if (*c == '@')
9884 base_style = dis_style_comment_start;
9885
9886 if (*c == '\t')
9887 base_style = dis_style_text;
9888
9889 func (stream, base_style, "%c", *c);
9890
9891 }
16980d0b 9892 }
05413229
NC		 9893
9894 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 9895 func (stream, dis_style_comment_start, "\t@ 0x%lx",
9896 value_in_comment);
05413229 9897
e2efe87d 9898 if (is_unpredictable)
6576bffe 9899 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
e2efe87d 9900
78933a4a 9901 return true;
16980d0b
JB		 9902 }
9903 }
78933a4a 9904 return false;
16980d0b
JB		 9905}
9906
73cd51e5
AV		 9907/* Print one mve instruction on INFO->STREAM.
9908 Return TRUE if the instuction matched, FALSE if this is not a
9909 recognised mve instruction. */
9910
78933a4a 9911static bool
73cd51e5
AV		 9912print_insn_mve (struct disassemble_info *info, long given)
9913{
9914 const struct mopcode32 *insn;
9915 void *stream = info->stream;
6576bffe
AB		 9916 fprintf_styled_ftype func = info->fprintf_styled_func;
9917 enum disassembler_style base_style = dis_style_mnemonic;
9918 enum disassembler_style old_base_style = base_style;
73cd51e5
AV		 9919
9920 for (insn = mve_opcodes; insn->assembler; insn++)
9921 {
9922 if (((given & insn->mask) == insn->value)
9923 && !is_mve_encoding_conflict (given, insn->mve_op))
9924 {
9925 signed long value_in_comment = 0;
78933a4a
AM		 9926 bool is_unpredictable = false;
9927 bool is_undefined = false;
73cd51e5
AV		 9928 const char *c;
9929 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9930 enum mve_undefined undefined_cond = UNDEF_NONE;
9931
9932 /* Most vector mve instruction are illegal in a it block.
9933 There are a few exceptions; check for them. */
9934 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9935 {
78933a4a 9936 is_unpredictable = true;
73cd51e5
AV		 9937 unpredictable_cond = UNPRED_IT_BLOCK;
9938 }
9939 else if (is_mve_unpredictable (given, insn->mve_op,
9940 &unpredictable_cond))
78933a4a 9941 is_unpredictable = true;
73cd51e5
AV		 9942
9943 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
78933a4a 9944 is_undefined = true;
73cd51e5 9945
c4a23bf8
SP		 9946 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9947 i.e "VMOV Qd, Qm". */
9948 if ((insn->mve_op == MVE_VORR_REG)
9949 && (arm_decode_field (given, 1, 3)
9950 == arm_decode_field (given, 17, 19)))
9951 continue;
9952
73cd51e5
AV		 9953 for (c = insn->assembler; *c; c++)
9954 {
9955 if (*c == '%')
9956 {
9957 switch (*++c)
9958 {
6576bffe
AB		 9959 case '{':
9960 ++c;
9961 if (*c == '\0')
9962 abort ();
9963 old_base_style = base_style;
9964 base_style = decode_base_style (*c);
9965 ++c;
9966 if (*c != ':')
9967 abort ();
9968 break;
9969
9970 case '}':
9971 base_style = old_base_style;
9972 break;
9973
73cd51e5 9974 case '%':
6576bffe 9975 func (stream, base_style, "%%");
73cd51e5
AV		 9976 break;
9977
ef1576a1
AV		 9978 case 'a':
9979 /* Don't print anything for '+' as it is implied. */
9980 if (arm_decode_field (given, 23, 23) == 0)
6576bffe 9981 func (stream, dis_style_immediate, "-");
ef1576a1
AV		 9982 break;
9983
143275ea
AV		 9984 case 'c':
9985 if (ifthen_state)
6576bffe
AB		 9986 func (stream, dis_style_mnemonic, "%s",
9987 arm_conditional[IFTHEN_COND]);
143275ea
AV		 9988 break;
9989
aef6d006
AV		 9990 case 'd':
9991 print_mve_vld_str_addr (info, given, insn->mve_op);
9992 break;
9993
143275ea
AV		 9994 case 'i':
9995 {
9996 long mve_mask = mve_extract_pred_mask (given);
6576bffe
AB		 9997 func (stream, dis_style_mnemonic, "%s",
9998 mve_predicatenames[mve_mask]);
143275ea
AV		 9999 }
10000 break;
10001
23d00a41
SD		 10002 case 'j':
10003 {
10004 unsigned int imm5 = 0;
10005 imm5 |= arm_decode_field (given, 6, 7);
10006 imm5 |= (arm_decode_field (given, 12, 14) << 2);
6576bffe
AB		 10007 func (stream, dis_style_immediate, "#%u",
10008 (imm5 == 0) ? 32 : imm5);
23d00a41
SD		 10009 }
10010 break;
10011
08132bdd 10012 case 'k':
6576bffe 10013 func (stream, dis_style_immediate, "#%u",
08132bdd
SP		 10014 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
10015 break;
10016
143275ea
AV		 10017 case 'n':
10018 print_vec_condition (info, given, insn->mve_op);
10019 break;
10020
ef1576a1
AV		 10021 case 'o':
10022 if (arm_decode_field (given, 0, 0) == 1)
10023 {
10024 unsigned long size
10025 = arm_decode_field (given, 4, 4)
10026 | (arm_decode_field (given, 6, 6) << 1);
10027
6576bffe
AB		 10028 func (stream, dis_style_text, ", ");
10029 func (stream, dis_style_sub_mnemonic, "uxtw ");
10030 func (stream, dis_style_immediate, "#%lu", size);
ef1576a1
AV		 10031 }
10032 break;
10033
bf0b396d
AV		 10034 case 'm':
10035 print_mve_rounding_mode (info, given, insn->mve_op);
10036 break;
10037
10038 case 's':
10039 print_mve_vcvt_size (info, given, insn->mve_op);
10040 break;
10041
aef6d006
AV		 10042 case 'u':
10043 {
c507f10b
AV		 10044 unsigned long op1 = arm_decode_field (given, 21, 22);
10045
10046 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
10047 {
10048 /* Check for signed. */
10049 if (arm_decode_field (given, 23, 23) == 0)
10050 {
10051 /* We don't print 's' for S32. */
10052 if ((arm_decode_field (given, 5, 6) == 0)
10053 && ((op1 == 0) || (op1 == 1)))
10054 ;
10055 else
6576bffe 10056 func (stream, dis_style_mnemonic, "s");
c507f10b
AV		 10057 }
10058 else
6576bffe 10059 func (stream, dis_style_mnemonic, "u");
c507f10b 10060 }
aef6d006 10061 else
c507f10b
AV		 10062 {
10063 if (arm_decode_field (given, 28, 28) == 0)
6576bffe 10064 func (stream, dis_style_mnemonic, "s");
c507f10b 10065 else
6576bffe 10066 func (stream, dis_style_mnemonic, "u");
c507f10b 10067 }
aef6d006 10068 }
ef1576a1 10069 break;
aef6d006 10070
143275ea
AV		 10071 case 'v':
10072 print_instruction_predicate (info);
10073 break;
10074
04d54ace
AV		 10075 case 'w':
10076 if (arm_decode_field (given, 21, 21) == 1)
6576bffe 10077 func (stream, dis_style_text, "!");
04d54ace
AV		 10078 break;
10079
10080 case 'B':
10081 print_mve_register_blocks (info, given, insn->mve_op);
10082 break;
10083
c507f10b
AV		 10084 case 'E':
10085 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
10086
10087 print_simd_imm8 (info, given, 28, insn);
10088 break;
10089
10090 case 'N':
10091 print_mve_vmov_index (info, given);
10092 break;
10093
14925797
AV		 10094 case 'T':
10095 if (arm_decode_field (given, 12, 12) == 0)
6576bffe 10096 func (stream, dis_style_mnemonic, "b");
14925797 10097 else
6576bffe 10098 func (stream, dis_style_mnemonic, "t");
14925797
AV		 10099 break;
10100
d3b63143
AV		 10101 case 'X':
10102 if (arm_decode_field (given, 12, 12) == 1)
6576bffe 10103 func (stream, dis_style_mnemonic, "x");
d3b63143
AV		 10104 break;
10105
143275ea
AV		 10106 case '0': case '1': case '2': case '3': case '4':
10107 case '5': case '6': case '7': case '8': case '9':
10108 {
10109 int width;
10110 unsigned long value;
10111
10112 c = arm_decode_bitfield (c, given, &value, &width);
10113
10114 switch (*c)
10115 {
10116 case 'Z':
10117 if (value == 13)
78933a4a 10118 is_unpredictable = true;
143275ea 10119 else if (value == 15)
6576bffe 10120 func (stream, dis_style_register, "zr");
143275ea 10121 else
6576bffe
AB		 10122 func (stream, dis_style_register, "%s",
10123 arm_regnames[value]);
143275ea 10124 break;
23d00a41 10125
e39c1607 10126 case 'c':
6576bffe
AB		 10127 func (stream, dis_style_sub_mnemonic, "%s",
10128 arm_conditional[value]);
e39c1607
SD		 10129 break;
10130
10131 case 'C':
10132 value ^= 1;
6576bffe
AB		 10133 func (stream, dis_style_sub_mnemonic, "%s",
10134 arm_conditional[value]);
e39c1607
SD		 10135 break;
10136
23d00a41
SD		 10137 case 'S':
10138 if (value == 13 || value == 15)
78933a4a 10139 is_unpredictable = true;
23d00a41 10140 else
6576bffe
AB		 10141 func (stream, dis_style_register, "%s",
10142 arm_regnames[value]);
23d00a41
SD		 10143 break;
10144
143275ea
AV		 10145 case 's':
10146 print_mve_size (info,
10147 value,
10148 insn->mve_op);
10149 break;
66dcaa5d
AV		 10150 case 'I':
10151 if (value == 1)
6576bffe 10152 func (stream, dis_style_mnemonic, "i");
66dcaa5d 10153 break;
d3b63143
AV		 10154 case 'A':
10155 if (value == 1)
6576bffe 10156 func (stream, dis_style_mnemonic, "a");
d3b63143 10157 break;
1c8f2df8
AV		 10158 case 'h':
10159 {
10160 unsigned int odd_reg = (value << 1) | 1;
6576bffe
AB		 10161 func (stream, dis_style_register, "%s",
10162 arm_regnames[odd_reg]);
1c8f2df8
AV		 10163 }
10164 break;
ef1576a1
AV		 10165 case 'i':
10166 {
10167 unsigned long imm
10168 = arm_decode_field (given, 0, 6);
10169 unsigned long mod_imm = imm;
10170
10171 switch (insn->mve_op)
10172 {
10173 case MVE_VLDRW_GATHER_T5:
10174 case MVE_VSTRW_SCATTER_T5:
10175 mod_imm = mod_imm << 2;
10176 break;
10177 case MVE_VSTRD_SCATTER_T6:
10178 case MVE_VLDRD_GATHER_T6:
10179 mod_imm = mod_imm << 3;
10180 break;
10181
10182 default:
10183 break;
10184 }
10185
6576bffe
AB		 10186 func (stream, dis_style_immediate, "%lu",
10187 mod_imm);
ef1576a1
AV		 10188 }
10189 break;
bf0b396d 10190 case 'k':
6576bffe
AB		 10191 func (stream, dis_style_immediate, "%lu",
10192 64 - value);
bf0b396d 10193 break;
1c8f2df8
AV		 10194 case 'l':
10195 {
10196 unsigned int even_reg = value << 1;
6576bffe
AB		 10197 func (stream, dis_style_register, "%s",
10198 arm_regnames[even_reg]);
1c8f2df8
AV		 10199 }
10200 break;
10201 case 'u':
10202 switch (value)
10203 {
10204 case 0:
6576bffe 10205 func (stream, dis_style_immediate, "1");
1c8f2df8
AV		 10206 break;
10207 case 1:
6576bffe 10208 func (stream, dis_style_immediate, "2");
1c8f2df8
AV		 10209 break;
10210 case 2:
6576bffe 10211 func (stream, dis_style_immediate, "4");
1c8f2df8
AV		 10212 break;
10213 case 3:
6576bffe 10214 func (stream, dis_style_immediate, "8");
1c8f2df8
AV		 10215 break;
10216 default:
10217 break;
10218 }
10219 break;
897b9bbc
AV		 10220 case 'o':
10221 print_mve_rotate (info, value, width);
10222 break;
9743db03 10223 case 'r':
6576bffe
AB		 10224 func (stream, dis_style_register, "%s",
10225 arm_regnames[value]);
9743db03 10226 break;
04d54ace 10227 case 'd':
ed63aa17
AV		 10228 if (insn->mve_op == MVE_VQSHL_T2
10229 || insn->mve_op == MVE_VQSHLU_T3
10230 || insn->mve_op == MVE_VRSHR
10231 || insn->mve_op == MVE_VRSHRN
10232 || insn->mve_op == MVE_VSHL_T1
10233 || insn->mve_op == MVE_VSHLL_T1
10234 || insn->mve_op == MVE_VSHR
10235 || insn->mve_op == MVE_VSHRN
10236 || insn->mve_op == MVE_VSLI
10237 || insn->mve_op == MVE_VSRI)
10238 print_mve_shift_n (info, given, insn->mve_op);
10239 else if (insn->mve_op == MVE_VSHLL_T2)
10240 {
10241 switch (value)
10242 {
10243 case 0x00:
6576bffe 10244 func (stream, dis_style_immediate, "8");
ed63aa17
AV		 10245 break;
10246 case 0x01:
6576bffe 10247 func (stream, dis_style_immediate, "16");
ed63aa17
AV		 10248 break;
10249 case 0x10:
10250 print_mve_undefined (info, UNDEF_SIZE_0);
10251 break;
10252 default:
10253 assert (0);
10254 break;
10255 }
10256 }
10257 else
10258 {
10259 if (insn->mve_op == MVE_VSHLC && value == 0)
10260 value = 32;
6576bffe 10261 func (stream, base_style, "%ld", value);
ed63aa17
AV		 10262 value_in_comment = value;
10263 }
04d54ace 10264 break;
c507f10b 10265 case 'F':
6576bffe 10266 func (stream, dis_style_register, "s%ld", value);
c507f10b 10267 break;
143275ea
AV		 10268 case 'Q':
10269 if (value & 0x8)
6576bffe
AB		 10270 func (stream, dis_style_text,
10271 "<illegal reg q%ld.5>", value);
143275ea 10272 else
6576bffe 10273 func (stream, dis_style_register, "q%ld", value);
143275ea 10274 break;
c507f10b 10275 case 'x':
6576bffe
AB		 10276 func (stream, dis_style_immediate,
10277 "0x%08lx", value);
c507f10b 10278 break;
143275ea
AV		 10279 default:
10280 abort ();
10281 }
10282 break;
10283 default:
10284 abort ();
10285 }
73cd51e5
AV		 10286 }
10287 }
10288 else
6576bffe
AB		 10289 {
10290 if (*c == '@')
10291 base_style = dis_style_comment_start;
10292
10293 if (*c == '\t')
10294 base_style = dis_style_text;
10295
10296 func (stream, base_style, "%c", *c);
10297 }
73cd51e5
AV		 10298 }
10299
10300 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 10301 func (stream, dis_style_comment_start, "\t@ 0x%lx",
10302 value_in_comment);
73cd51e5
AV		 10303
10304 if (is_unpredictable)
10305 print_mve_unpredictable (info, unpredictable_cond);
10306
10307 if (is_undefined)
10308 print_mve_undefined (info, undefined_cond);
10309
63b4cc53 10310 if (!vpt_block_state.in_vpt_block
143275ea 10311 && !ifthen_state
63b4cc53 10312 && is_vpt_instruction (given))
143275ea 10313 mark_inside_vpt_block (given);
63b4cc53 10314 else if (vpt_block_state.in_vpt_block)
143275ea
AV		 10315 update_vpt_block_state ();
10316
78933a4a 10317 return true;
73cd51e5
AV		 10318 }
10319 }
78933a4a 10320 return false;
73cd51e5
AV		 10321}
10322
10323
90ec0d68
MGD		 10324/* Return the name of a v7A special register. */
10325
43e65147 10326static const char *
90ec0d68
MGD		 10327banked_regname (unsigned reg)
10328{
10329 switch (reg)
10330 {
10331 case 15: return "CPSR";
43e65147 10332 case 32: return "R8_usr";
90ec0d68
MGD		 10333 case 33: return "R9_usr";
10334 case 34: return "R10_usr";
10335 case 35: return "R11_usr";
10336 case 36: return "R12_usr";
10337 case 37: return "SP_usr";
10338 case 38: return "LR_usr";
43e65147 10339 case 40: return "R8_fiq";
90ec0d68
MGD		 10340 case 41: return "R9_fiq";
10341 case 42: return "R10_fiq";
10342 case 43: return "R11_fiq";
10343 case 44: return "R12_fiq";
10344 case 45: return "SP_fiq";
10345 case 46: return "LR_fiq";
10346 case 48: return "LR_irq";
10347 case 49: return "SP_irq";
10348 case 50: return "LR_svc";
10349 case 51: return "SP_svc";
10350 case 52: return "LR_abt";
10351 case 53: return "SP_abt";
10352 case 54: return "LR_und";
10353 case 55: return "SP_und";
10354 case 60: return "LR_mon";
10355 case 61: return "SP_mon";
10356 case 62: return "ELR_hyp";
10357 case 63: return "SP_hyp";
10358 case 79: return "SPSR";
10359 case 110: return "SPSR_fiq";
10360 case 112: return "SPSR_irq";
10361 case 114: return "SPSR_svc";
10362 case 116: return "SPSR_abt";
10363 case 118: return "SPSR_und";
10364 case 124: return "SPSR_mon";
10365 case 126: return "SPSR_hyp";
10366 default: return NULL;
10367 }
10368}
10369
e797f7e0
MGD		 10370/* Return the name of the DMB/DSB option. */
10371static const char *
10372data_barrier_option (unsigned option)
10373{
10374 switch (option & 0xf)
10375 {
10376 case 0xf: return "sy";
10377 case 0xe: return "st";
10378 case 0xd: return "ld";
10379 case 0xb: return "ish";
10380 case 0xa: return "ishst";
10381 case 0x9: return "ishld";
10382 case 0x7: return "un";
10383 case 0x6: return "unst";
10384 case 0x5: return "nshld";
10385 case 0x3: return "osh";
10386 case 0x2: return "oshst";
10387 case 0x1: return "oshld";
10388 default: return NULL;
10389 }
10390}
10391
4a5329c6
ZW		 10392/* Print one ARM instruction from PC on INFO->STREAM. */
10393
10394static void
10395print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10396{
6b5d3a4d 10397 const struct opcode32 *insn;
6a51a8a8 10398 void *stream = info->stream;
6576bffe 10399 fprintf_styled_ftype func = info->fprintf_styled_func;
b0e28b39 10400 struct arm_private_data *private_data = info->private_data;
6576bffe
AB		 10401 enum disassembler_style base_style = dis_style_mnemonic;
10402 enum disassembler_style old_base_style = base_style;
252b5132 10403
78933a4a 10404 if (print_insn_coprocessor (pc, info, given, false))
16980d0b
JB		 10405 return;
10406
78933a4a 10407 if (print_insn_neon (info, given, false))
8f06b2d8
PB		 10408 return;
10409
78933a4a 10410 if (print_insn_generic_coprocessor (pc, info, given, false))
33593eaf
MM		 10411 return;
10412
252b5132
RH		 10413 for (insn = arm_opcodes; insn->assembler; insn++)
10414 {
0313a2b8
NC		 10415 if ((given & insn->mask) != insn->value)
10416 continue;
823d2571
TG		 10417
10418 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 10419 continue;
10420
10421 /* Special case: an instruction with all bits set in the condition field
10422 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10423 or by the catchall at the end of the table. */
10424 if ((given & 0xF0000000) != 0xF0000000
10425 || (insn->mask & 0xF0000000) == 0xF0000000
10426 || (insn->mask == 0 && insn->value == 0))
252b5132 10427 {
ff4a8d2b
NC		 10428 unsigned long u_reg = 16;
10429 unsigned long U_reg = 16;
78933a4a 10430 bool is_unpredictable = false;
05413229 10431 signed long value_in_comment = 0;
6b5d3a4d 10432 const char *c;
b34976b6 10433
252b5132
RH		 10434 for (c = insn->assembler; *c; c++)
10435 {
10436 if (*c == '%')
10437 {
78933a4a 10438 bool allow_unpredictable = false;
c1e26897 10439
252b5132
RH		 10440 switch (*++c)
10441 {
6576bffe
AB		 10442 case '{':
10443 ++c;
10444 if (*c == '\0')
10445 abort ();
10446 old_base_style = base_style;
10447 base_style = decode_base_style (*c);
10448 ++c;
10449 if (*c != ':')
10450 abort ();
10451 break;
10452
10453 case '}':
10454 base_style = old_base_style;
10455 break;
10456
252b5132 10457 case '%':
6576bffe 10458 func (stream, base_style, "%%");
252b5132
RH		 10459 break;
10460
10461 case 'a':
05413229 10462 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10463 break;
252b5132 10464
62b3e311
PB		 10465 case 'P':
10466 /* Set P address bit and use normal address
10467 printing routine. */
c1e26897 10468 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10469 break;
10470
c1e26897 10471 case 'S':
78933a4a 10472 allow_unpredictable = true;
1a0670f3 10473 /* Fall through. */
252b5132
RH		 10474 case 's':
10475 if ((given & 0x004f0000) == 0x004f0000)
10476 {
58efb6c0 10477 /* PC relative with immediate offset. */
f8b960bc 10478 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10479
aefd8a40
NC		 10480 if (PRE_BIT_SET)
10481 {
26d97720
NS		 10482 /* Elide positive zero offset. */
10483 if (offset || NEGATIVE_BIT_SET)
6576bffe
AB		 10484 {
10485 func (stream, dis_style_text, "[");
10486 func (stream, dis_style_register, "pc");
10487 func (stream, dis_style_text, ", ");
10488 func (stream, dis_style_immediate, "#%s%d",
10489 (NEGATIVE_BIT_SET ? "-" : ""),
10490 (int) offset);
10491 func (stream, dis_style_text, "]");
10492 }
945ee430 10493 else
6576bffe
AB		 10494 {
10495 func (stream, dis_style_text, "[");
10496 func (stream, dis_style_register, "pc");
10497 func (stream, dis_style_text, "]");
10498 }
26d97720
NS		 10499 if (NEGATIVE_BIT_SET)
10500 offset = -offset;
6576bffe 10501 func (stream, dis_style_comment_start, "\t@ ");
aefd8a40
NC		 10502 info->print_address_func (offset + pc + 8, info);
10503 }
10504 else
10505 {
26d97720 10506 /* Always show the offset. */
6576bffe
AB		 10507 func (stream, dis_style_text, "[");
10508 func (stream, dis_style_register, "pc");
10509 func (stream, dis_style_text, "], ");
10510 func (stream, dis_style_immediate, "#%s%d",
d908c8af 10511 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b 10512 if (! allow_unpredictable)
78933a4a 10513 is_unpredictable = true;
aefd8a40 10514 }
252b5132
RH		 10515 }
10516 else
10517 {
fe56b6ce
NC		 10518 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10519
6576bffe
AB		 10520 func (stream, dis_style_text, "[");
10521 func (stream, dis_style_register, "%s",
252b5132 10522 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10523
c1e26897 10524 if (PRE_BIT_SET)
252b5132 10525 {
c1e26897 10526 if (IMMEDIATE_BIT_SET)
252b5132 10527 {
26d97720
NS		 10528 /* Elide offset for non-writeback
10529 positive zero. */
10530 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10531 || offset)
6576bffe
AB		 10532 {
10533 func (stream, dis_style_text, ", ");
10534 func (stream, dis_style_immediate,
10535 "#%s%d",
10536 (NEGATIVE_BIT_SET ? "-" : ""),
10537 offset);
10538 }
26d97720
NS		 10539
10540 if (NEGATIVE_BIT_SET)
10541 offset = -offset;
945ee430 10542
fe56b6ce 10543 value_in_comment = offset;
252b5132 10544 }
945ee430 10545 else
ff4a8d2b
NC		 10546 {
10547 /* Register Offset or Register Pre-Indexed. */
6576bffe
AB		 10548 func (stream, dis_style_text, ", %s",
10549 NEGATIVE_BIT_SET ? "-" : "");
10550 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10551 arm_regnames[given & 0xf]);
10552
10553 /* Writing back to the register that is the source/
10554 destination of the load/store is unpredictable. */
10555 if (! allow_unpredictable
10556 && WRITEBACK_BIT_SET
10557 && ((given & 0xf) == ((given >> 12) & 0xf)))
78933a4a 10558 is_unpredictable = true;
ff4a8d2b 10559 }
252b5132 10560
6576bffe 10561 func (stream, dis_style_text, "]%s",
c1e26897 10562 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10563 }
945ee430 10564 else
252b5132 10565 {
c1e26897 10566 if (IMMEDIATE_BIT_SET)
252b5132 10567 {
945ee430 10568 /* Immediate Post-indexed. */
aefd8a40 10569 /* PR 10924: Offset must be printed, even if it is zero. */
6576bffe
AB		 10570 func (stream, dis_style_text, "], ");
10571 func (stream, dis_style_immediate, "#%s%d",
26d97720
NS		 10572 NEGATIVE_BIT_SET ? "-" : "", offset);
10573 if (NEGATIVE_BIT_SET)
10574 offset = -offset;
fe56b6ce 10575 value_in_comment = offset;
252b5132 10576 }
945ee430 10577 else
ff4a8d2b
NC		 10578 {
10579 /* Register Post-indexed. */
6576bffe
AB		 10580 func (stream, dis_style_text, "], %s",
10581 NEGATIVE_BIT_SET ? "-" : "");
10582 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10583 arm_regnames[given & 0xf]);
10584
10585 /* Writing back to the register that is the source/
10586 destination of the load/store is unpredictable. */
10587 if (! allow_unpredictable
10588 && (given & 0xf) == ((given >> 12) & 0xf))
78933a4a 10589 is_unpredictable = true;
ff4a8d2b 10590 }
c1e26897 10591
07a28fab
NC		 10592 if (! allow_unpredictable)
10593 {
10594 /* Writeback is automatically implied by post- addressing.
10595 Setting the W bit is unnecessary and ARM specify it as
10596 being unpredictable. */
10597 if (WRITEBACK_BIT_SET
10598 /* Specifying the PC register as the post-indexed
10599 registers is also unpredictable. */
ab8e2090 10600 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
78933a4a 10601 is_unpredictable = true;
07a28fab 10602 }
252b5132
RH		 10603 }
10604 }
10605 break;
b34976b6 10606
252b5132 10607 case 'b':
6b5d3a4d 10608 {
f8b960bc 10609 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10610 bfd_vma target = disp * 4 + pc + 8;
10611 info->print_address_func (target, info);
10612
10613 /* Fill in instruction information. */
10614 info->insn_info_valid = 1;
10615 info->insn_type = dis_branch;
10616 info->target = target;
6b5d3a4d 10617 }
252b5132
RH		 10618 break;
10619
10620 case 'c':
c22aaad1 10621 if (((given >> 28) & 0xf) != 0xe)
6576bffe 10622 func (stream, dis_style_mnemonic, "%s",
c22aaad1 10623 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10624 break;
10625
10626 case 'm':
10627 {
10628 int started = 0;
10629 int reg;
10630
6576bffe 10631 func (stream, dis_style_text, "{");
252b5132
RH		 10632 for (reg = 0; reg < 16; reg++)
10633 if ((given & (1 << reg)) != 0)
10634 {
10635 if (started)
6576bffe 10636 func (stream, dis_style_text, ", ");
252b5132 10637 started = 1;
6576bffe
AB		 10638 func (stream, dis_style_register, "%s",
10639 arm_regnames[reg]);
252b5132 10640 }
6576bffe 10641 func (stream, dis_style_text, "}");
ab8e2090 10642 if (! started)
78933a4a 10643 is_unpredictable = true;
252b5132
RH		 10644 }
10645 break;
10646
37b37b2d 10647 case 'q':
78933a4a 10648 arm_decode_shift (given, func, stream, false);
37b37b2d
RE		 10649 break;
10650
252b5132
RH		 10651 case 'o':
10652 if ((given & 0x02000000) != 0)
10653 {
a415b1cd
JB		 10654 unsigned int rotate = (given & 0xf00) >> 7;
10655 unsigned int immed = (given & 0xff);
10656 unsigned int a, i;
10657
ebd1c6d1
AM		 10658 a = (immed << ((32 - rotate) & 31)
10659 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10660 /* If there is another encoding with smaller rotate,
10661 the rotate should be specified directly. */
10662 for (i = 0; i < 32; i += 2)
ebd1c6d1 10663 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10664 break;
10665
10666 if (i != rotate)
6576bffe
AB		 10667 {
10668 func (stream, dis_style_immediate, "#%d", immed);
10669 func (stream, dis_style_text, ", ");
10670 func (stream, dis_style_immediate, "%d", rotate);
10671 }
a415b1cd 10672 else
6576bffe 10673 func (stream, dis_style_immediate, "#%d", a);
a415b1cd 10674 value_in_comment = a;
252b5132
RH		 10675 }
10676 else
78933a4a 10677 arm_decode_shift (given, func, stream, true);
252b5132
RH		 10678 break;
10679
10680 case 'p':
10681 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10682 {
823d2571
TG		 10683 arm_feature_set arm_ext_v6 =
10684 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10685
aefd8a40
NC		 10686 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10687 mechanism for setting PSR flag bits. They are
10688 obsolete in V6 onwards. */
823d2571
TG		 10689 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10690 arm_ext_v6))
6576bffe 10691 func (stream, dis_style_mnemonic, "p");
4ab90a7a 10692 else
78933a4a 10693 is_unpredictable = true;
aefd8a40 10694 }
252b5132
RH		 10695 break;
10696
10697 case 't':
10698 if ((given & 0x01200000) == 0x00200000)
6576bffe 10699 func (stream, dis_style_mnemonic, "t");
252b5132
RH		 10700 break;
10701
252b5132 10702 case 'A':
05413229
NC		 10703 {
10704 int offset = given & 0xff;
f02232aa 10705
05413229 10706 value_in_comment = offset * 4;
c1e26897 10707 if (NEGATIVE_BIT_SET)
05413229 10708 value_in_comment = - value_in_comment;
f02232aa 10709
6576bffe
AB		 10710 func (stream, dis_style_text, "[%s",
10711 arm_regnames [(given >> 16) & 0xf]);
f02232aa 10712
c1e26897 10713 if (PRE_BIT_SET)
05413229
NC		 10714 {
10715 if (offset)
6576bffe 10716 func (stream, dis_style_text, ", #%d]%s",
d908c8af 10717 (int) value_in_comment,
c1e26897 10718 WRITEBACK_BIT_SET ? "!" : "");
05413229 10719 else
6576bffe 10720 func (stream, dis_style_text, "]");
05413229
NC		 10721 }
10722 else
10723 {
6576bffe 10724 func (stream, dis_style_text, "]");
f02232aa 10725
c1e26897 10726 if (WRITEBACK_BIT_SET)
05413229
NC		 10727 {
10728 if (offset)
6576bffe
AB		 10729 func (stream, dis_style_text,
10730 ", #%d", (int) value_in_comment);
05413229
NC		 10731 }
10732 else
fe56b6ce 10733 {
6576bffe
AB		 10734 func (stream, dis_style_text,
10735 ", {%d}", (int) offset);
fe56b6ce
NC		 10736 value_in_comment = offset;
10737 }
05413229
NC		 10738 }
10739 }
252b5132
RH		 10740 break;
10741
077b8428
NC		 10742 case 'B':
10743 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10744 {
10745 bfd_vma address;
10746 bfd_vma offset = 0;
b34976b6 10747
c1e26897 10748 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10749 /* Is signed, hi bits should be ones. */
10750 offset = (-1) ^ 0x00ffffff;
10751
10752 /* Offset is (SignExtend(offset field)<<2). */
10753 offset += given & 0x00ffffff;
10754 offset <<= 2;
10755 address = offset + pc + 8;
b34976b6 10756
8f06b2d8
PB		 10757 if (given & 0x01000000)
10758 /* H bit allows addressing to 2-byte boundaries. */
10759 address += 2;
b1ee46c5 10760
8f06b2d8 10761 info->print_address_func (address, info);
1d67fe3b
TT		 10762
10763 /* Fill in instruction information. */
10764 info->insn_info_valid = 1;
10765 info->insn_type = dis_branch;
10766 info->target = address;
b1ee46c5 10767 }
b1ee46c5
AH		 10768 break;
10769
252b5132 10770 case 'C':
90ec0d68
MGD		 10771 if ((given & 0x02000200) == 0x200)
10772 {
10773 const char * name;
10774 unsigned sysm = (given & 0x004f0000) >> 16;
10775
10776 sysm |= (given & 0x300) >> 4;
10777 name = banked_regname (sysm);
10778
10779 if (name != NULL)
6576bffe 10780 func (stream, dis_style_register, "%s", name);
90ec0d68 10781 else
6576bffe
AB		 10782 func (stream, dis_style_text,
10783 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10784 }
10785 else
10786 {
6576bffe 10787 func (stream, dis_style_register, "%cPSR_",
90ec0d68 10788 (given & 0x00400000) ? 'S' : 'C');
6576bffe 10789
90ec0d68 10790 if (given & 0x80000)
6576bffe 10791 func (stream, dis_style_register, "f");
90ec0d68 10792 if (given & 0x40000)
6576bffe 10793 func (stream, dis_style_register, "s");
90ec0d68 10794 if (given & 0x20000)
6576bffe 10795 func (stream, dis_style_register, "x");
90ec0d68 10796 if (given & 0x10000)
6576bffe 10797 func (stream, dis_style_register, "c");
90ec0d68 10798 }
252b5132
RH		 10799 break;
10800
62b3e311 10801 case 'U':
43e65147 10802 if ((given & 0xf0) == 0x60)
62b3e311 10803 {
52e7f43d
RE		 10804 switch (given & 0xf)
10805 {
6576bffe
AB		 10806 case 0xf:
10807 func (stream, dis_style_sub_mnemonic, "sy");
10808 break;
52e7f43d 10809 default:
6576bffe
AB		 10810 func (stream, dis_style_immediate, "#%d",
10811 (int) given & 0xf);
52e7f43d
RE		 10812 break;
10813 }
43e65147
L		 10814 }
10815 else
52e7f43d 10816 {
e797f7e0
MGD		 10817 const char * opt = data_barrier_option (given & 0xf);
10818 if (opt != NULL)
6576bffe 10819 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 10820 else
6576bffe
AB		 10821 func (stream, dis_style_immediate,
10822 "#%d", (int) given & 0xf);
62b3e311
PB		 10823 }
10824 break;
10825
b34976b6 10826 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10827 case '5': case '6': case '7': case '8': case '9':
10828 {
16980d0b
JB		 10829 int width;
10830 unsigned long value;
252b5132 10831
16980d0b 10832 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10833
252b5132
RH		 10834 switch (*c)
10835 {
ab8e2090
NC		 10836 case 'R':
10837 if (value == 15)
78933a4a 10838 is_unpredictable = true;
ab8e2090 10839 /* Fall through. */
16980d0b 10840 case 'r':
9eb6c0f1
MGD		 10841 case 'T':
10842 /* We want register + 1 when decoding T. */
10843 if (*c == 'T')
2bddb71a 10844 value = (value + 1) & 0xf;
9eb6c0f1 10845
ff4a8d2b
NC		 10846 if (c[1] == 'u')
10847 {
10848 /* Eat the 'u' character. */
10849 ++ c;
10850
10851 if (u_reg == value)
78933a4a 10852 is_unpredictable = true;
ff4a8d2b
NC		 10853 u_reg = value;
10854 }
10855 if (c[1] == 'U')
10856 {
10857 /* Eat the 'U' character. */
10858 ++ c;
10859
10860 if (U_reg == value)
78933a4a 10861 is_unpredictable = true;
ff4a8d2b
NC		 10862 U_reg = value;
10863 }
6576bffe
AB		 10864 func (stream, dis_style_register, "%s",
10865 arm_regnames[value]);
16980d0b
JB		 10866 break;
10867 case 'd':
6576bffe 10868 func (stream, base_style, "%ld", value);
05413229 10869 value_in_comment = value;
16980d0b
JB		 10870 break;
10871 case 'b':
6576bffe
AB		 10872 func (stream, dis_style_immediate,
10873 "%ld", value * 8);
05413229 10874 value_in_comment = value * 8;
16980d0b
JB		 10875 break;
10876 case 'W':
6576bffe
AB		 10877 func (stream, dis_style_immediate,
10878 "%ld", value + 1);
05413229 10879 value_in_comment = value + 1;
16980d0b
JB		 10880 break;
10881 case 'x':
6576bffe
AB		 10882 func (stream, dis_style_immediate,
10883 "0x%08lx", value);
16980d0b
JB		 10884
10885 /* Some SWI instructions have special
10886 meanings. */
10887 if ((given & 0x0fffffff) == 0x0FF00000)
6576bffe
AB		 10888 func (stream, dis_style_comment_start,
10889 "\t@ IMB");
16980d0b 10890 else if ((given & 0x0fffffff) == 0x0FF00001)
6576bffe
AB		 10891 func (stream, dis_style_comment_start,
10892 "\t@ IMBRange");
16980d0b
JB		 10893 break;
10894 case 'X':
6576bffe
AB		 10895 func (stream, dis_style_immediate,
10896 "%01lx", value & 0xf);
05413229 10897 value_in_comment = value;
252b5132
RH		 10898 break;
10899 case '`':
10900 c++;
16980d0b 10901 if (value == 0)
6576bffe 10902 func (stream, dis_style_text, "%c", *c);
252b5132
RH		 10903 break;
10904 case '\'':
10905 c++;
16980d0b 10906 if (value == ((1ul << width) - 1))
6576bffe 10907 func (stream, base_style, "%c", *c);
252b5132
RH		 10908 break;
10909 case '?':
6576bffe
AB		 10910 func (stream, base_style, "%c",
10911 c[(1 << width) - (int) value]);
16980d0b 10912 c += 1 << width;
252b5132
RH		 10913 break;
10914 default:
10915 abort ();
10916 }
dffaa15c
AM		 10917 }
10918 break;
0dd132b6 10919
dffaa15c
AM		 10920 case 'e':
10921 {
10922 int imm;
0dd132b6 10923
dffaa15c 10924 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
6576bffe 10925 func (stream, dis_style_immediate, "%d", imm);
dffaa15c
AM		 10926 value_in_comment = imm;
10927 }
10928 break;
fe56b6ce 10929
dffaa15c
AM		 10930 case 'E':
10931 /* LSB and WIDTH fields of BFI or BFC. The machine-
10932 language instruction encodes LSB and MSB. */
10933 {
10934 long msb = (given & 0x001f0000) >> 16;
10935 long lsb = (given & 0x00000f80) >> 7;
10936 long w = msb - lsb + 1;
0a003adc 10937
dffaa15c 10938 if (w > 0)
6576bffe
AB		 10939 {
10940 func (stream, dis_style_immediate, "#%lu", lsb);
10941 func (stream, dis_style_text, ", ");
10942 func (stream, dis_style_immediate, "#%lu", w);
10943 }
dffaa15c 10944 else
6576bffe
AB		 10945 func (stream, dis_style_text,
10946 "(invalid: %lu:%lu)", lsb, msb);
dffaa15c
AM		 10947 }
10948 break;
90ec0d68 10949
dffaa15c
AM		 10950 case 'R':
10951 /* Get the PSR/banked register name. */
10952 {
10953 const char * name;
10954 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10955
dffaa15c
AM		 10956 sysm |= (given & 0x300) >> 4;
10957 name = banked_regname (sysm);
90ec0d68 10958
dffaa15c 10959 if (name != NULL)
6576bffe 10960 func (stream, dis_style_register, "%s", name);
dffaa15c 10961 else
6576bffe
AB		 10962 func (stream, dis_style_text,
10963 "(UNDEF: %lu)", (unsigned long) sysm);
dffaa15c
AM		 10964 }
10965 break;
fe56b6ce 10966
dffaa15c
AM		 10967 case 'V':
10968 /* 16-bit unsigned immediate from a MOVT or MOVW
10969 instruction, encoded in bits 0:11 and 15:19. */
10970 {
10971 long hi = (given & 0x000f0000) >> 4;
10972 long lo = (given & 0x00000fff);
10973 long imm16 = hi | lo;
0a003adc 10974
6576bffe 10975 func (stream, dis_style_immediate, "#%lu", imm16);
dffaa15c 10976 value_in_comment = imm16;
252b5132 10977 }
dffaa15c
AM		 10978 break;
10979
10980 default:
10981 abort ();
252b5132
RH		 10982 }
10983 }
10984 else
6576bffe
AB		 10985 {
10986
10987 if (*c == '@')
10988 base_style = dis_style_comment_start;
10989
10990 if (*c == '\t')
10991 base_style = dis_style_text;
10992
10993 func (stream, base_style, "%c", *c);
10994 }
252b5132 10995 }
05413229
NC		 10996
10997 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 10998 func (stream, dis_style_comment_start, "\t@ 0x%lx",
10999 (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 11000
11001 if (is_unpredictable)
6576bffe 11002 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 11003
4a5329c6 11004 return;
252b5132
RH		 11005 }
11006 }
6576bffe
AB		 11007 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
11008 (unsigned) given);
0b347048 11009 return;
252b5132
RH		 11010}
11011
4a5329c6 11012/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 11013
4a5329c6
ZW		 11014static void
11015print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 11016{
6b5d3a4d 11017 const struct opcode16 *insn;
6a51a8a8 11018 void *stream = info->stream;
6576bffe
AB		 11019 fprintf_styled_ftype func = info->fprintf_styled_func;
11020 enum disassembler_style base_style = dis_style_mnemonic;
11021 enum disassembler_style old_base_style = base_style;
252b5132
RH		 11022
11023 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 11024 if ((given & insn->mask) == insn->value)
11025 {
05413229 11026 signed long value_in_comment = 0;
6b5d3a4d 11027 const char *c = insn->assembler;
05413229 11028
c19d1205
ZW		 11029 for (; *c; c++)
11030 {
11031 int domaskpc = 0;
11032 int domasklr = 0;
11033
11034 if (*c != '%')
11035 {
6576bffe
AB		 11036 if (*c == '@')
11037 base_style = dis_style_comment_start;
11038
11039 if (*c == '\t')
11040 base_style = dis_style_text;
11041
11042 func (stream, base_style, "%c", *c);
11043
c19d1205
ZW		 11044 continue;
11045 }
252b5132 11046
c19d1205
ZW		 11047 switch (*++c)
11048 {
6576bffe
AB		 11049 case '{':
11050 ++c;
11051 if (*c == '\0')
11052 abort ();
11053 old_base_style = base_style;
11054 base_style = decode_base_style (*c);
11055 ++c;
11056 if (*c != ':')
11057 abort ();
11058 break;
11059
11060 case '}':
11061 base_style = old_base_style;
11062 break;
11063
c19d1205 11064 case '%':
6576bffe 11065 func (stream, base_style, "%%");
c19d1205 11066 break;
b34976b6 11067
c22aaad1
PB		 11068 case 'c':
11069 if (ifthen_state)
6576bffe
AB		 11070 func (stream, dis_style_mnemonic, "%s",
11071 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 11072 break;
11073
11074 case 'C':
11075 if (ifthen_state)
6576bffe
AB		 11076 func (stream, dis_style_mnemonic, "%s",
11077 arm_conditional[IFTHEN_COND]);
c22aaad1 11078 else
6576bffe 11079 func (stream, dis_style_mnemonic, "s");
c22aaad1
PB		 11080 break;
11081
11082 case 'I':
11083 {
11084 unsigned int tmp;
11085
11086 ifthen_next_state = given & 0xff;
11087 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
6576bffe
AB		 11088 func (stream, dis_style_mnemonic,
11089 ((given ^ tmp) & 0x10) ? "e" : "t");
11090 func (stream, dis_style_text, "\t");
11091 func (stream, dis_style_sub_mnemonic, "%s",
11092 arm_conditional[(given >> 4) & 0xf]);
c22aaad1
PB		 11093 }
11094 break;
11095
11096 case 'x':
11097 if (ifthen_next_state)
6576bffe
AB		 11098 func (stream, dis_style_comment_start,
11099 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 11100 break;
11101
11102 case 'X':
11103 if (ifthen_state)
6576bffe
AB		 11104 func (stream, dis_style_comment_start,
11105 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 11106 arm_conditional[IFTHEN_COND]);
11107 break;
11108
c19d1205
ZW		 11109 case 'S':
11110 {
11111 long reg;
11112
11113 reg = (given >> 3) & 0x7;
11114 if (given & (1 << 6))
11115 reg += 8;
4f3c3dbb 11116
6576bffe 11117 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 11118 }
11119 break;
baf0cc5e 11120
c19d1205 11121 case 'D':
4f3c3dbb 11122 {
c19d1205
ZW		 11123 long reg;
11124
11125 reg = given & 0x7;
11126 if (given & (1 << 7))
11127 reg += 8;
11128
6576bffe 11129 func (stream, dis_style_register, "%s", arm_regnames[reg]);
4f3c3dbb 11130 }
c19d1205
ZW		 11131 break;
11132
11133 case 'N':
11134 if (given & (1 << 8))
11135 domasklr = 1;
11136 /* Fall through. */
11137 case 'O':
11138 if (*c == 'O' && (given & (1 << 8)))
11139 domaskpc = 1;
11140 /* Fall through. */
11141 case 'M':
11142 {
11143 int started = 0;
11144 int reg;
11145
6576bffe 11146 func (stream, dis_style_text, "{");
c19d1205
ZW		 11147
11148 /* It would be nice if we could spot
11149 ranges, and generate the rS-rE format: */
11150 for (reg = 0; (reg < 8); reg++)
11151 if ((given & (1 << reg)) != 0)
11152 {
11153 if (started)
6576bffe 11154 func (stream, dis_style_text, ", ");
c19d1205 11155 started = 1;
6576bffe
AB		 11156 func (stream, dis_style_register, "%s",
11157 arm_regnames[reg]);
c19d1205
ZW		 11158 }
11159
11160 if (domasklr)
11161 {
11162 if (started)
6576bffe 11163 func (stream, dis_style_text, ", ");
c19d1205 11164 started = 1;
6576bffe
AB		 11165 func (stream, dis_style_register, "%s",
11166 arm_regnames[14] /* "lr" */);
c19d1205
ZW		 11167 }
11168
11169 if (domaskpc)
11170 {
11171 if (started)
6576bffe
AB		 11172 func (stream, dis_style_text, ", ");
11173 func (stream, dis_style_register, "%s",
11174 arm_regnames[15] /* "pc" */);
c19d1205
ZW		 11175 }
11176
6576bffe 11177 func (stream, dis_style_text, "}");
c19d1205
ZW		 11178 }
11179 break;
11180
4547cb56
NC		 11181 case 'W':
11182 /* Print writeback indicator for a LDMIA. We are doing a
11183 writeback if the base register is not in the register
11184 mask. */
11185 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
6576bffe 11186 func (stream, dis_style_text, "!");
dffaa15c 11187 break;
4547cb56 11188
c19d1205
ZW		 11189 case 'b':
11190 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
11191 {
11192 bfd_vma address = (pc + 4
11193 + ((given & 0x00f8) >> 2)
11194 + ((given & 0x0200) >> 3));
11195 info->print_address_func (address, info);
1d67fe3b
TT		 11196
11197 /* Fill in instruction information. */
11198 info->insn_info_valid = 1;
11199 info->insn_type = dis_branch;
11200 info->target = address;
c19d1205
ZW		 11201 }
11202 break;
11203
11204 case 's':
11205 /* Right shift immediate -- bits 6..10; 1-31 print
11206 as themselves, 0 prints as 32. */
11207 {
11208 long imm = (given & 0x07c0) >> 6;
11209 if (imm == 0)
11210 imm = 32;
6576bffe 11211 func (stream, dis_style_immediate, "#%ld", imm);
c19d1205
ZW		 11212 }
11213 break;
11214
11215 case '0': case '1': case '2': case '3': case '4':
11216 case '5': case '6': case '7': case '8': case '9':
11217 {
11218 int bitstart = *c++ - '0';
11219 int bitend = 0;
11220
11221 while (*c >= '0' && *c <= '9')
11222 bitstart = (bitstart * 10) + *c++ - '0';
11223
11224 switch (*c)
11225 {
11226 case '-':
11227 {
f8b960bc 11228 bfd_vma reg;
c19d1205
ZW		 11229
11230 c++;
11231 while (*c >= '0' && *c <= '9')
11232 bitend = (bitend * 10) + *c++ - '0';
11233 if (!bitend)
11234 abort ();
11235 reg = given >> bitstart;
459cde81 11236 reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
ff4a8d2b 11237
c19d1205
ZW		 11238 switch (*c)
11239 {
11240 case 'r':
6576bffe
AB		 11241 func (stream, dis_style_register, "%s",
11242 arm_regnames[reg]);
c19d1205
ZW		 11243 break;
11244
11245 case 'd':
6576bffe
AB		 11246 func (stream, dis_style_immediate, "%ld",
11247 (long) reg);
05413229 11248 value_in_comment = reg;
c19d1205
ZW		 11249 break;
11250
11251 case 'H':
6576bffe
AB		 11252 func (stream, dis_style_immediate, "%ld",
11253 (long) (reg << 1));
05413229 11254 value_in_comment = reg << 1;
c19d1205
ZW		 11255 break;
11256
11257 case 'W':
6576bffe
AB		 11258 func (stream, dis_style_immediate, "%ld",
11259 (long) (reg << 2));
05413229 11260 value_in_comment = reg << 2;
c19d1205
ZW		 11261 break;
11262
11263 case 'a':
11264 /* PC-relative address -- the bottom two
11265 bits of the address are dropped
11266 before the calculation. */
11267 info->print_address_func
11268 (((pc + 4) & ~3) + (reg << 2), info);
05413229 11269 value_in_comment = 0;
c19d1205
ZW		 11270 break;
11271
11272 case 'x':
6576bffe
AB		 11273 func (stream, dis_style_immediate, "0x%04lx",
11274 (long) reg);
c19d1205
ZW		 11275 break;
11276
c19d1205
ZW		 11277 case 'B':
11278 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 11279 bfd_vma target = reg * 2 + pc + 4;
11280 info->print_address_func (target, info);
05413229 11281 value_in_comment = 0;
1d67fe3b
TT		 11282
11283 /* Fill in instruction information. */
11284 info->insn_info_valid = 1;
11285 info->insn_type = dis_branch;
11286 info->target = target;
c19d1205
ZW		 11287 break;
11288
11289 case 'c':
6576bffe
AB		 11290 func (stream, dis_style_mnemonic, "%s",
11291 arm_conditional [reg]);
c19d1205
ZW		 11292 break;
11293
11294 default:
11295 abort ();
11296 }
11297 }
11298 break;
11299
11300 case '\'':
11301 c++;
11302 if ((given & (1 << bitstart)) != 0)
6576bffe 11303 func (stream, base_style, "%c", *c);
c19d1205
ZW		 11304 break;
11305
11306 case '?':
11307 ++c;
11308 if ((given & (1 << bitstart)) != 0)
6576bffe 11309 func (stream, base_style, "%c", *c++);
c19d1205 11310 else
6576bffe 11311 func (stream, base_style, "%c", *++c);
c19d1205
ZW		 11312 break;
11313
11314 default:
11315 abort ();
11316 }
11317 }
11318 break;
11319
11320 default:
11321 abort ();
11322 }
11323 }
05413229
NC		 11324
11325 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 11326 func (stream, dis_style_comment_start,
11327 "\t@ 0x%lx", value_in_comment);
4a5329c6 11328 return;
c19d1205
ZW		 11329 }
11330
11331 /* No match. */
6576bffe
AB		 11332 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
11333 (unsigned) given);
0b347048 11334 return;
c19d1205
ZW		 11335}
11336
62b3e311 11337/* Return the name of an V7M special register. */
fe56b6ce 11338
62b3e311
PB		 11339static const char *
11340psr_name (int regno)
11341{
11342 switch (regno)
11343 {
1a336194
TP		 11344 case 0x0: return "APSR";
11345 case 0x1: return "IAPSR";
11346 case 0x2: return "EAPSR";
11347 case 0x3: return "PSR";
11348 case 0x5: return "IPSR";
11349 case 0x6: return "EPSR";
11350 case 0x7: return "IEPSR";
11351 case 0x8: return "MSP";
11352 case 0x9: return "PSP";
11353 case 0xa: return "MSPLIM";
11354 case 0xb: return "PSPLIM";
11355 case 0x10: return "PRIMASK";
11356 case 0x11: return "BASEPRI";
11357 case 0x12: return "BASEPRI_MAX";
11358 case 0x13: return "FAULTMASK";
11359 case 0x14: return "CONTROL";
16a1fa25
TP		 11360 case 0x88: return "MSP_NS";
11361 case 0x89: return "PSP_NS";
1a336194
TP		 11362 case 0x8a: return "MSPLIM_NS";
11363 case 0x8b: return "PSPLIM_NS";
11364 case 0x90: return "PRIMASK_NS";
11365 case 0x91: return "BASEPRI_NS";
11366 case 0x93: return "FAULTMASK_NS";
11367 case 0x94: return "CONTROL_NS";
11368 case 0x98: return "SP_NS";
62b3e311
PB		 11369 default: return "<unknown>";
11370 }
11371}
11372
4a5329c6
ZW		 11373/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
11374
11375static void
11376print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 11377{
6b5d3a4d 11378 const struct opcode32 *insn;
c19d1205 11379 void *stream = info->stream;
6576bffe 11380 fprintf_styled_ftype func = info->fprintf_styled_func;
78933a4a 11381 bool is_mve = is_mve_architecture (info);
6576bffe
AB		 11382 enum disassembler_style base_style = dis_style_mnemonic;
11383 enum disassembler_style old_base_style = base_style;
c19d1205 11384
78933a4a 11385 if (print_insn_coprocessor (pc, info, given, true))
16980d0b
JB		 11386 return;
11387
78933a4a 11388 if (!is_mve && print_insn_neon (info, given, true))
73cd51e5
AV		 11389 return;
11390
11391 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 11392 return;
11393
78933a4a 11394 if (print_insn_cde (info, given, true))
4934a27c
MM		 11395 return;
11396
78933a4a 11397 if (print_insn_generic_coprocessor (pc, info, given, true))
33593eaf
MM		 11398 return;
11399
c19d1205
ZW		 11400 for (insn = thumb32_opcodes; insn->assembler; insn++)
11401 if ((given & insn->mask) == insn->value)
11402 {
78933a4a
AM		 11403 bool is_clrm = false;
11404 bool is_unpredictable = false;
05413229 11405 signed long value_in_comment = 0;
6b5d3a4d 11406 const char *c = insn->assembler;
05413229 11407
c19d1205
ZW		 11408 for (; *c; c++)
11409 {
11410 if (*c != '%')
11411 {
6576bffe
AB		 11412 if (*c == '@')
11413 base_style = dis_style_comment_start;
11414 if (*c == '\t')
11415 base_style = dis_style_text;
11416 func (stream, base_style, "%c", *c);
c19d1205
ZW		 11417 continue;
11418 }
11419
11420 switch (*++c)
11421 {
6576bffe
AB		 11422 case '{':
11423 ++c;
11424 if (*c == '\0')
11425 abort ();
11426 old_base_style = base_style;
11427 base_style = decode_base_style (*c);
11428 ++c;
11429 if (*c != ':')
11430 abort ();
11431 break;
11432
11433 case '}':
11434 base_style = old_base_style;
11435 break;
11436
c19d1205 11437 case '%':
6576bffe 11438 func (stream, base_style, "%%");
c19d1205
ZW		 11439 break;
11440
c22aaad1
PB		 11441 case 'c':
11442 if (ifthen_state)
6576bffe
AB		 11443 func (stream, dis_style_mnemonic, "%s",
11444 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 11445 break;
11446
11447 case 'x':
11448 if (ifthen_next_state)
6576bffe
AB		 11449 func (stream, dis_style_comment_start,
11450 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 11451 break;
11452
11453 case 'X':
11454 if (ifthen_state)
6576bffe
AB		 11455 func (stream, dis_style_comment_start,
11456 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 11457 arm_conditional[IFTHEN_COND]);
11458 break;
11459
c19d1205
ZW		 11460 case 'I':
11461 {
11462 unsigned int imm12 = 0;
fe56b6ce 11463
c19d1205
ZW		 11464 imm12 |= (given & 0x000000ffu);
11465 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 11466 imm12 |= (given & 0x04000000u) >> 15;
6576bffe 11467 func (stream, dis_style_immediate, "#%u", imm12);
fe56b6ce 11468 value_in_comment = imm12;
c19d1205
ZW		 11469 }
11470 break;
11471
11472 case 'M':
11473 {
11474 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 11475
c19d1205
ZW		 11476 bits |= (given & 0x000000ffu);
11477 bits |= (given & 0x00007000u) >> 4;
11478 bits |= (given & 0x04000000u) >> 15;
11479 imm8 = (bits & 0x0ff);
11480 mod = (bits & 0xf00) >> 8;
11481 switch (mod)
11482 {
11483 case 0: imm = imm8; break;
c1e26897
NC		 11484 case 1: imm = ((imm8 << 16) | imm8); break;
11485 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11486 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 11487 default:
11488 mod = (bits & 0xf80) >> 7;
11489 imm8 = (bits & 0x07f) | 0x80;
11490 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11491 }
6576bffe 11492 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11493 value_in_comment = imm;
c19d1205
ZW		 11494 }
11495 break;
43e65147 11496
c19d1205
ZW		 11497 case 'J':
11498 {
11499 unsigned int imm = 0;
fe56b6ce 11500
c19d1205
ZW		 11501 imm |= (given & 0x000000ffu);
11502 imm |= (given & 0x00007000u) >> 4;
11503 imm |= (given & 0x04000000u) >> 15;
11504 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11505 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11506 value_in_comment = imm;
c19d1205
ZW		 11507 }
11508 break;
11509
11510 case 'K':
11511 {
11512 unsigned int imm = 0;
fe56b6ce 11513
c19d1205
ZW		 11514 imm |= (given & 0x000f0000u) >> 16;
11515 imm |= (given & 0x00000ff0u) >> 0;
11516 imm |= (given & 0x0000000fu) << 12;
6576bffe 11517 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11518 value_in_comment = imm;
c19d1205
ZW		 11519 }
11520 break;
11521
74db7efb
NC		 11522 case 'H':
11523 {
11524 unsigned int imm = 0;
11525
11526 imm |= (given & 0x000f0000u) >> 4;
11527 imm |= (given & 0x00000fffu) >> 0;
6576bffe 11528 func (stream, dis_style_immediate, "#%u", imm);
74db7efb
NC		 11529 value_in_comment = imm;
11530 }
11531 break;
11532
90ec0d68
MGD		 11533 case 'V':
11534 {
11535 unsigned int imm = 0;
11536
11537 imm |= (given & 0x00000fffu);
11538 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11539 func (stream, dis_style_immediate, "#%u", imm);
90ec0d68
MGD		 11540 value_in_comment = imm;
11541 }
11542 break;
11543
c19d1205
ZW		 11544 case 'S':
11545 {
11546 unsigned int reg = (given & 0x0000000fu);
11547 unsigned int stp = (given & 0x00000030u) >> 4;
11548 unsigned int imm = 0;
11549 imm |= (given & 0x000000c0u) >> 6;
11550 imm |= (given & 0x00007000u) >> 10;
11551
6576bffe 11552 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 11553 switch (stp)
11554 {
11555 case 0:
11556 if (imm > 0)
6576bffe
AB		 11557 {
11558 func (stream, dis_style_text, ", ");
11559 func (stream, dis_style_sub_mnemonic, "lsl ");
11560 func (stream, dis_style_immediate, "#%u", imm);
11561 }
c19d1205
ZW		 11562 break;
11563
11564 case 1:
11565 if (imm == 0)
11566 imm = 32;
6576bffe
AB		 11567 func (stream, dis_style_text, ", ");
11568 func (stream, dis_style_sub_mnemonic, "lsr ");
11569 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11570 break;
11571
11572 case 2:
11573 if (imm == 0)
11574 imm = 32;
6576bffe
AB		 11575 func (stream, dis_style_text, ", ");
11576 func (stream, dis_style_sub_mnemonic, "asr ");
11577 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11578 break;
11579
11580 case 3:
11581 if (imm == 0)
6576bffe
AB		 11582 {
11583 func (stream, dis_style_text, ", ");
11584 func (stream, dis_style_sub_mnemonic, "rrx");
11585 }
c19d1205 11586 else
6576bffe
AB		 11587 {
11588 func (stream, dis_style_text, ", ");
11589 func (stream, dis_style_sub_mnemonic, "ror ");
11590 func (stream, dis_style_immediate, "#%u", imm);
11591 }
c19d1205
ZW		 11592 }
11593 }
11594 break;
11595
11596 case 'a':
11597 {
11598 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11599 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11600 unsigned int op = (given & 0x00000f00) >> 8;
11601 unsigned int i12 = (given & 0x00000fff);
11602 unsigned int i8 = (given & 0x000000ff);
78933a4a 11603 bool writeback = false, postind = false;
f8b960bc 11604 bfd_vma offset = 0;
c19d1205 11605
6576bffe
AB		 11606 func (stream, dis_style_text, "[");
11607 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
05413229
NC		 11608 if (U) /* 12-bit positive immediate offset. */
11609 {
11610 offset = i12;
11611 if (Rn != 15)
11612 value_in_comment = offset;
11613 }
11614 else if (Rn == 15) /* 12-bit negative immediate offset. */
11615 offset = - (int) i12;
11616 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11617 {
11618 unsigned int Rm = (i8 & 0x0f);
11619 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11620
6576bffe
AB		 11621 func (stream, dis_style_text, ", ");
11622 func (stream, dis_style_register, "%s",
11623 arm_regnames[Rm]);
c19d1205 11624 if (sh)
6576bffe
AB		 11625 {
11626 func (stream, dis_style_text, ", ");
11627 func (stream, dis_style_sub_mnemonic, "lsl ");
11628 func (stream, dis_style_immediate, "#%u", sh);
11629 }
11630 func (stream, dis_style_text, "]");
c19d1205
ZW		 11631 break;
11632 }
11633 else switch (op)
11634 {
05413229 11635 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11636 offset = i8;
11637 break;
11638
05413229 11639 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11640 offset = -i8;
11641 break;
11642
05413229 11643 case 0xF: /* 8-bit + preindex with wb. */
c19d1205 11644 offset = i8;
78933a4a 11645 writeback = true;
c19d1205
ZW		 11646 break;
11647
05413229 11648 case 0xD: /* 8-bit - preindex with wb. */
c19d1205 11649 offset = -i8;
78933a4a 11650 writeback = true;
c19d1205
ZW		 11651 break;
11652
05413229 11653 case 0xB: /* 8-bit + postindex. */
c19d1205 11654 offset = i8;
78933a4a 11655 postind = true;
c19d1205
ZW		 11656 break;
11657
05413229 11658 case 0x9: /* 8-bit - postindex. */
c19d1205 11659 offset = -i8;
78933a4a 11660 postind = true;
c19d1205
ZW		 11661 break;
11662
11663 default:
6576bffe 11664 func (stream, dis_style_text, ", <undefined>]");
c19d1205
ZW		 11665 goto skip;
11666 }
11667
11668 if (postind)
6576bffe
AB		 11669 {
11670 func (stream, dis_style_text, "], ");
11671 func (stream, dis_style_immediate, "#%d", (int) offset);
11672 }
c19d1205
ZW		 11673 else
11674 {
11675 if (offset)
6576bffe
AB		 11676 {
11677 func (stream, dis_style_text, ", ");
11678 func (stream, dis_style_immediate, "#%d",
11679 (int) offset);
11680 }
11681 func (stream, dis_style_text, writeback ? "]!" : "]");
c19d1205
ZW		 11682 }
11683
11684 if (Rn == 15)
11685 {
6576bffe 11686 func (stream, dis_style_comment_start, "\t@ ");
c19d1205
ZW		 11687 info->print_address_func (((pc + 4) & ~3) + offset, info);
11688 }
11689 }
11690 skip:
11691 break;
11692
11693 case 'A':
11694 {
c1e26897
NC		 11695 unsigned int U = ! NEGATIVE_BIT_SET;
11696 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11697 unsigned int Rn = (given & 0x000f0000) >> 16;
11698 unsigned int off = (given & 0x000000ff);
11699
6576bffe
AB		 11700 func (stream, dis_style_text, "[");
11701 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
c1e26897
NC		 11702
11703 if (PRE_BIT_SET)
c19d1205
ZW		 11704 {
11705 if (off || !U)
05413229 11706 {
6576bffe
AB		 11707 func (stream, dis_style_text, ", ");
11708 func (stream, dis_style_immediate, "#%c%u",
11709 U ? '+' : '-', off * 4);
fe50e98c 11710 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11711 }
6576bffe 11712 func (stream, dis_style_text, "]");
c19d1205 11713 if (W)
6576bffe 11714 func (stream, dis_style_text, "!");
c19d1205
ZW		 11715 }
11716 else
11717 {
6576bffe 11718 func (stream, dis_style_text, "], ");
c19d1205 11719 if (W)
05413229 11720 {
6576bffe
AB		 11721 func (stream, dis_style_immediate, "#%c%u",
11722 U ? '+' : '-', off * 4);
fe50e98c 11723 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11724 }
c19d1205 11725 else
fe56b6ce 11726 {
6576bffe
AB		 11727 func (stream, dis_style_text, "{");
11728 func (stream, dis_style_immediate, "%u", off);
11729 func (stream, dis_style_text, "}");
fe56b6ce
NC		 11730 value_in_comment = off;
11731 }
c19d1205
ZW		 11732 }
11733 }
11734 break;
11735
11736 case 'w':
11737 {
11738 unsigned int Sbit = (given & 0x01000000) >> 24;
11739 unsigned int type = (given & 0x00600000) >> 21;
05413229 11740
c19d1205
ZW		 11741 switch (type)
11742 {
6576bffe
AB		 11743 case 0:
11744 func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11745 break;
11746 case 1:
11747 func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11748 break;
c19d1205
ZW		 11749 case 2:
11750 if (Sbit)
6576bffe 11751 func (stream, dis_style_text, "??");
c19d1205
ZW		 11752 break;
11753 case 3:
6576bffe 11754 func (stream, dis_style_text, "??");
c19d1205
ZW		 11755 break;
11756 }
11757 }
11758 break;
11759
4b5a202f 11760 case 'n':
78933a4a 11761 is_clrm = true;
4b5a202f 11762 /* Fall through. */
c19d1205
ZW		 11763 case 'm':
11764 {
11765 int started = 0;
11766 int reg;
11767
6576bffe 11768 func (stream, dis_style_text, "{");
c19d1205
ZW		 11769 for (reg = 0; reg < 16; reg++)
11770 if ((given & (1 << reg)) != 0)
11771 {
11772 if (started)
6576bffe 11773 func (stream, dis_style_text, ", ");
c19d1205 11774 started = 1;
4b5a202f 11775 if (is_clrm && reg == 13)
6576bffe
AB		 11776 func (stream, dis_style_text, "(invalid: %s)",
11777 arm_regnames[reg]);
4b5a202f 11778 else if (is_clrm && reg == 15)
6576bffe 11779 func (stream, dis_style_register, "%s", "APSR");
4b5a202f 11780 else
6576bffe
AB		 11781 func (stream, dis_style_register, "%s",
11782 arm_regnames[reg]);
c19d1205 11783 }
6576bffe 11784 func (stream, dis_style_text, "}");
c19d1205
ZW		 11785 }
11786 break;
11787
11788 case 'E':
11789 {
11790 unsigned int msb = (given & 0x0000001f);
11791 unsigned int lsb = 0;
fe56b6ce 11792
c19d1205
ZW		 11793 lsb |= (given & 0x000000c0u) >> 6;
11794 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11795 func (stream, dis_style_immediate, "#%u", lsb);
11796 func (stream, dis_style_text, ", ");
11797 func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
c19d1205
ZW		 11798 }
11799 break;
11800
11801 case 'F':
11802 {
11803 unsigned int width = (given & 0x0000001f) + 1;
11804 unsigned int lsb = 0;
fe56b6ce 11805
c19d1205
ZW		 11806 lsb |= (given & 0x000000c0u) >> 6;
11807 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11808 func (stream, dis_style_immediate, "#%u", lsb);
11809 func (stream, dis_style_text, ", ");
11810 func (stream, dis_style_immediate, "#%u", width);
c19d1205
ZW		 11811 }
11812 break;
11813
e12437dc
AV		 11814 case 'G':
11815 {
11816 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
6576bffe 11817 func (stream, dis_style_immediate, "%x", boff);
e12437dc
AV		 11818 }
11819 break;
11820
e5d6e09e
AV		 11821 case 'W':
11822 {
11823 unsigned int immA = (given & 0x001f0000u) >> 16;
11824 unsigned int immB = (given & 0x000007feu) >> 1;
11825 unsigned int immC = (given & 0x00000800u) >> 11;
11826 bfd_vma offset = 0;
11827
11828 offset |= immA << 12;
11829 offset |= immB << 2;
11830 offset |= immC << 1;
11831 /* Sign extend. */
11832 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11833
11834 info->print_address_func (pc + 4 + offset, info);
11835 }
11836 break;
11837
1caf72a5
AV		 11838 case 'Y':
11839 {
11840 unsigned int immA = (given & 0x007f0000u) >> 16;
11841 unsigned int immB = (given & 0x000007feu) >> 1;
11842 unsigned int immC = (given & 0x00000800u) >> 11;
11843 bfd_vma offset = 0;
11844
11845 offset |= immA << 12;
11846 offset |= immB << 2;
11847 offset |= immC << 1;
11848 /* Sign extend. */
11849 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11850
11851 info->print_address_func (pc + 4 + offset, info);
11852 }
11853 break;
11854
1889da70
AV		 11855 case 'Z':
11856 {
11857 unsigned int immA = (given & 0x00010000u) >> 16;
11858 unsigned int immB = (given & 0x000007feu) >> 1;
11859 unsigned int immC = (given & 0x00000800u) >> 11;
11860 bfd_vma offset = 0;
11861
11862 offset |= immA << 12;
11863 offset |= immB << 2;
11864 offset |= immC << 1;
11865 /* Sign extend. */
11866 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11867
11868 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11869
11870 unsigned int T = (given & 0x00020000u) >> 17;
11871 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11872 unsigned int boffset = (T == 1) ? 4 : 2;
6576bffe
AB		 11873 func (stream, dis_style_text, ", ");
11874 func (stream, dis_style_immediate, "%x",
11875 endoffset + boffset);
1889da70
AV		 11876 }
11877 break;
11878
60f993ce
AV		 11879 case 'Q':
11880 {
11881 unsigned int immh = (given & 0x000007feu) >> 1;
11882 unsigned int imml = (given & 0x00000800u) >> 11;
11883 bfd_vma imm32 = 0;
11884
11885 imm32 |= immh << 2;
11886 imm32 |= imml << 1;
11887
11888 info->print_address_func (pc + 4 + imm32, info);
11889 }
11890 break;
11891
11892 case 'P':
11893 {
11894 unsigned int immh = (given & 0x000007feu) >> 1;
11895 unsigned int imml = (given & 0x00000800u) >> 11;
11896 bfd_vma imm32 = 0;
11897
11898 imm32 |= immh << 2;
11899 imm32 |= imml << 1;
11900
11901 info->print_address_func (pc + 4 - imm32, info);
11902 }
11903 break;
11904
c19d1205
ZW		 11905 case 'b':
11906 {
11907 unsigned int S = (given & 0x04000000u) >> 26;
11908 unsigned int J1 = (given & 0x00002000u) >> 13;
11909 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11910 bfd_vma offset = 0;
c19d1205
ZW		 11911
11912 offset |= !S << 20;
11913 offset |= J2 << 19;
11914 offset |= J1 << 18;
11915 offset |= (given & 0x003f0000) >> 4;
11916 offset |= (given & 0x000007ff) << 1;
11917 offset -= (1 << 20);
11918
1d67fe3b
TT		 11919 bfd_vma target = pc + 4 + offset;
11920 info->print_address_func (target, info);
11921
11922 /* Fill in instruction information. */
11923 info->insn_info_valid = 1;
11924 info->insn_type = dis_branch;
11925 info->target = target;
c19d1205
ZW		 11926 }
11927 break;
11928
11929 case 'B':
11930 {
11931 unsigned int S = (given & 0x04000000u) >> 26;
11932 unsigned int I1 = (given & 0x00002000u) >> 13;
11933 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11934 bfd_vma offset = 0;
c19d1205
ZW		 11935
11936 offset |= !S << 24;
11937 offset |= !(I1 ^ S) << 23;
11938 offset |= !(I2 ^ S) << 22;
11939 offset |= (given & 0x03ff0000u) >> 4;
11940 offset |= (given & 0x000007ffu) << 1;
11941 offset -= (1 << 24);
36b0c57d 11942 offset += pc + 4;
c19d1205 11943
36b0c57d
PB		 11944 /* BLX target addresses are always word aligned. */
11945 if ((given & 0x00001000u) == 0)
11946 offset &= ~2u;
11947
11948 info->print_address_func (offset, info);
1d67fe3b
TT		 11949
11950 /* Fill in instruction information. */
11951 info->insn_info_valid = 1;
11952 info->insn_type = dis_branch;
11953 info->target = offset;
c19d1205
ZW		 11954 }
11955 break;
11956
11957 case 's':
11958 {
11959 unsigned int shift = 0;
fe56b6ce 11960
c19d1205
ZW		 11961 shift |= (given & 0x000000c0u) >> 6;
11962 shift |= (given & 0x00007000u) >> 10;
c1e26897 11963 if (WRITEBACK_BIT_SET)
6576bffe
AB		 11964 {
11965 func (stream, dis_style_text, ", ");
11966 func (stream, dis_style_sub_mnemonic, "asr ");
11967 func (stream, dis_style_immediate, "#%u", shift);
11968 }
c19d1205 11969 else if (shift)
6576bffe
AB		 11970 {
11971 func (stream, dis_style_text, ", ");
11972 func (stream, dis_style_sub_mnemonic, "lsl ");
11973 func (stream, dis_style_immediate, "#%u", shift);
11974 }
c19d1205
ZW		 11975 /* else print nothing - lsl #0 */
11976 }
11977 break;
11978
11979 case 'R':
11980 {
11981 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11982
c19d1205 11983 if (rot)
6576bffe
AB		 11984 {
11985 func (stream, dis_style_text, ", ");
11986 func (stream, dis_style_sub_mnemonic, "ror ");
11987 func (stream, dis_style_immediate, "#%u", rot * 8);
11988 }
c19d1205
ZW		 11989 }
11990 break;
11991
62b3e311 11992 case 'U':
43e65147 11993 if ((given & 0xf0) == 0x60)
62b3e311 11994 {
52e7f43d
RE		 11995 switch (given & 0xf)
11996 {
6576bffe
AB		 11997 case 0xf:
11998 func (stream, dis_style_sub_mnemonic, "sy");
11999 break;
12000 default:
12001 func (stream, dis_style_immediate, "#%d",
12002 (int) given & 0xf);
12003 break;
52e7f43d 12004 }
62b3e311 12005 }
43e65147 12006 else
52e7f43d 12007 {
e797f7e0
MGD		 12008 const char * opt = data_barrier_option (given & 0xf);
12009 if (opt != NULL)
6576bffe 12010 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 12011 else
6576bffe
AB		 12012 func (stream, dis_style_immediate, "#%d",
12013 (int) given & 0xf);
52e7f43d 12014 }
62b3e311
PB		 12015 break;
12016
12017 case 'C':
12018 if ((given & 0xff) == 0)
12019 {
6576bffe
AB		 12020 func (stream, dis_style_register, "%cPSR_",
12021 (given & 0x100000) ? 'S' : 'C');
12022
62b3e311 12023 if (given & 0x800)
6576bffe 12024 func (stream, dis_style_register, "f");
62b3e311 12025 if (given & 0x400)
6576bffe 12026 func (stream, dis_style_register, "s");
62b3e311 12027 if (given & 0x200)
6576bffe 12028 func (stream, dis_style_register, "x");
62b3e311 12029 if (given & 0x100)
6576bffe 12030 func (stream, dis_style_register, "c");
62b3e311 12031 }
90ec0d68
MGD		 12032 else if ((given & 0x20) == 0x20)
12033 {
12034 char const* name;
12035 unsigned sysm = (given & 0xf00) >> 8;
12036
12037 sysm |= (given & 0x30);
12038 sysm |= (given & 0x00100000) >> 14;
12039 name = banked_regname (sysm);
43e65147 12040
90ec0d68 12041 if (name != NULL)
6576bffe 12042 func (stream, dis_style_register, "%s", name);
90ec0d68 12043 else
6576bffe
AB		 12044 func (stream, dis_style_text,
12045 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 12046 }
62b3e311
PB		 12047 else
12048 {
6576bffe
AB		 12049 func (stream, dis_style_register, "%s",
12050 psr_name (given & 0xff));
62b3e311
PB		 12051 }
12052 break;
12053
12054 case 'D':
90ec0d68
MGD		 12055 if (((given & 0xff) == 0)
12056 || ((given & 0x20) == 0x20))
12057 {
12058 char const* name;
12059 unsigned sm = (given & 0xf0000) >> 16;
12060
12061 sm |= (given & 0x30);
12062 sm |= (given & 0x00100000) >> 14;
12063 name = banked_regname (sm);
12064
12065 if (name != NULL)
6576bffe 12066 func (stream, dis_style_register, "%s", name);
90ec0d68 12067 else
6576bffe
AB		 12068 func (stream, dis_style_text,
12069 "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 12070 }
62b3e311 12071 else
6576bffe
AB		 12072 func (stream, dis_style_register, "%s",
12073 psr_name (given & 0xff));
62b3e311
PB		 12074 break;
12075
c19d1205
ZW		 12076 case '0': case '1': case '2': case '3': case '4':
12077 case '5': case '6': case '7': case '8': case '9':
12078 {
16980d0b
JB		 12079 int width;
12080 unsigned long val;
c19d1205 12081
16980d0b 12082 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 12083
c19d1205
ZW		 12084 switch (*c)
12085 {
d052b9b7
AV		 12086 case 's':
12087 if (val <= 3)
6576bffe
AB		 12088 func (stream, dis_style_mnemonic, "%s",
12089 mve_vec_sizename[val]);
d052b9b7 12090 else
6576bffe 12091 func (stream, dis_style_text, "<undef size>");
d052b9b7
AV		 12092 break;
12093
05413229 12094 case 'd':
6576bffe 12095 func (stream, base_style, "%lu", val);
05413229
NC		 12096 value_in_comment = val;
12097 break;
ff4a8d2b 12098
f0fba320 12099 case 'D':
6576bffe 12100 func (stream, dis_style_immediate, "%lu", val + 1);
f0fba320
RL		 12101 value_in_comment = val + 1;
12102 break;
12103
05413229 12104 case 'W':
6576bffe 12105 func (stream, dis_style_immediate, "%lu", val * 4);
05413229
NC		 12106 value_in_comment = val * 4;
12107 break;
ff4a8d2b 12108
f1c7f421
AV		 12109 case 'S':
12110 if (val == 13)
78933a4a 12111 is_unpredictable = true;
f1c7f421 12112 /* Fall through. */
ff4a8d2b
NC		 12113 case 'R':
12114 if (val == 15)
78933a4a 12115 is_unpredictable = true;
ff4a8d2b
NC		 12116 /* Fall through. */
12117 case 'r':
6576bffe
AB		 12118 func (stream, dis_style_register, "%s",
12119 arm_regnames[val]);
ff4a8d2b 12120 break;
c19d1205
ZW		 12121
12122 case 'c':
6576bffe 12123 func (stream, base_style, "%s", arm_conditional[val]);
c19d1205
ZW		 12124 break;
12125
12126 case '\'':
c19d1205 12127 c++;
16980d0b 12128 if (val == ((1ul << width) - 1))
6576bffe 12129 func (stream, base_style, "%c", *c);
c19d1205 12130 break;
43e65147 12131
c19d1205 12132 case '`':
c19d1205 12133 c++;
16980d0b 12134 if (val == 0)
6576bffe 12135 func (stream, dis_style_immediate, "%c", *c);
c19d1205
ZW		 12136 break;
12137
12138 case '?':
6576bffe
AB		 12139 func (stream, dis_style_mnemonic, "%c",
12140 c[(1 << width) - (int) val]);
16980d0b 12141 c += 1 << width;
c19d1205 12142 break;
43e65147 12143
0bb027fd 12144 case 'x':
6576bffe
AB		 12145 func (stream, dis_style_immediate, "0x%lx",
12146 val & 0xffffffffUL);
0bb027fd 12147 break;
c19d1205
ZW		 12148
12149 default:
12150 abort ();
12151 }
12152 }
12153 break;
12154
32a94698
NC		 12155 case 'L':
12156 /* PR binutils/12534
12157 If we have a PC relative offset in an LDRD or STRD
12158 instructions then display the decoded address. */
12159 if (((given >> 16) & 0xf) == 0xf)
12160 {
12161 bfd_vma offset = (given & 0xff) * 4;
12162
12163 if ((given & (1 << 23)) == 0)
12164 offset = - offset;
6576bffe 12165 func (stream, dis_style_comment_start, "\t@ ");
32a94698
NC		 12166 info->print_address_func ((pc & ~3) + 4 + offset, info);
12167 }
12168 break;
12169
c19d1205
ZW		 12170 default:
12171 abort ();
12172 }
12173 }
05413229
NC		 12174
12175 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 12176 func (stream, dis_style_comment_start, "\t@ 0x%lx",
12177 value_in_comment);
ff4a8d2b
NC		 12178
12179 if (is_unpredictable)
6576bffe 12180 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 12181
4a5329c6 12182 return;
c19d1205 12183 }
252b5132 12184
58efb6c0 12185 /* No match. */
6576bffe
AB		 12186 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
12187 (unsigned) given);
0b347048 12188 return;
252b5132
RH		 12189}
12190
e821645d
DJ		 12191/* Print data bytes on INFO->STREAM. */
12192
12193static void
fe56b6ce
NC		 12194print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
12195 struct disassemble_info *info,
e821645d
DJ		 12196 long given)
12197{
6576bffe
AB		 12198 fprintf_styled_ftype func = info->fprintf_styled_func;
12199
e821645d
DJ		 12200 switch (info->bytes_per_chunk)
12201 {
12202 case 1:
6576bffe
AB		 12203 func (info->stream, dis_style_assembler_directive, ".byte");
12204 func (info->stream, dis_style_text, "\t");
12205 func (info->stream, dis_style_immediate, "0x%02lx", given);
e821645d
DJ		 12206 break;
12207 case 2:
6576bffe
AB		 12208 func (info->stream, dis_style_assembler_directive, ".short");
12209 func (info->stream, dis_style_text, "\t");
12210 func (info->stream, dis_style_immediate, "0x%04lx", given);
e821645d
DJ		 12211 break;
12212 case 4:
6576bffe
AB		 12213 func (info->stream, dis_style_assembler_directive, ".word");
12214 func (info->stream, dis_style_text, "\t");
12215 func (info->stream, dis_style_immediate, "0x%08lx", given);
e821645d
DJ		 12216 break;
12217 default:
12218 abort ();
12219 }
12220}
12221
22a398e1 12222/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 12223 being displayed in symbol relative addresses.
12224
12225 Also disallow private symbol, with __tagsym$$ prefix,
12226 from ARM RVCT toolchain being displayed. */
22a398e1 12227
78933a4a 12228bool
22a398e1
NC		 12229arm_symbol_is_valid (asymbol * sym,
12230 struct disassemble_info * info ATTRIBUTE_UNUSED)
12231{
12232 const char * name;
43e65147 12233
22a398e1 12234 if (sym == NULL)
78933a4a 12235 return false;
22a398e1
NC		 12236
12237 name = bfd_asymbol_name (sym);
12238
d8282f0e 12239 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 12240}
12241
65b48a81 12242/* Parse the string of disassembler options. */
baf0cc5e 12243
65b48a81 12244static void
f995bbe8 12245parse_arm_disassembler_options (const char *options)
dd92f639 12246{
f995bbe8 12247 const char *opt;
b34976b6 12248
cad152f2 12249 force_thumb = false;
65b48a81 12250 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 12251 {
08dedd66 12252 if (startswith (opt, "reg-names-"))
65b48a81
PB		 12253 {
12254 unsigned int i;
12255 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12256 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
12257 {
12258 regname_selected = i;
12259 break;
12260 }
b34976b6 12261
65b48a81 12262 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 12263 /* xgettext: c-format */
12264 opcodes_error_handler (_("unrecognised register name set: %s"),
12265 opt);
65b48a81 12266 }
08dedd66 12267 else if (startswith (opt, "force-thumb"))
65b48a81 12268 force_thumb = 1;
08dedd66 12269 else if (startswith (opt, "no-force-thumb"))
65b48a81 12270 force_thumb = 0;
08dedd66 12271 else if (startswith (opt, "coproc"))
4934a27c
MM		 12272 {
12273 const char *procptr = opt + sizeof ("coproc") - 1;
12274 char *endptr;
12275 uint8_t coproc_number = strtol (procptr, &endptr, 10);
12276 if (endptr != procptr + 1 || coproc_number > 7)
12277 {
12278 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
12279 opt);
12280 continue;
12281 }
12282 if (*endptr != '=')
12283 {
12284 opcodes_error_handler (_("coproc must have an argument: %s"),
12285 opt);
12286 continue;
12287 }
12288 endptr += 1;
08dedd66 12289 if (startswith (endptr, "generic"))
4934a27c 12290 cde_coprocs &= ~(1 << coproc_number);
08dedd66
ML		 12291 else if (startswith (endptr, "cde")
12292 || startswith (endptr, "CDE"))
4934a27c
MM		 12293 cde_coprocs |= (1 << coproc_number);
12294 else
12295 {
12296 opcodes_error_handler (
12297 _("coprocN argument takes options \"generic\","
12298 " \"cde\", or \"CDE\": %s"), opt);
12299 }
12300 }
65b48a81 12301 else
a6743a54
AM		 12302 /* xgettext: c-format */
12303 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 12304 }
b34976b6 12305
dd92f639
NC		 12306 return;
12307}
12308
78933a4a 12309static bool
5bc5ae88
RL		 12310mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12311 enum map_type *map_symbol);
12312
c22aaad1
PB		 12313/* Search back through the insn stream to determine if this instruction is
12314 conditionally executed. */
fe56b6ce 12315
c22aaad1 12316static void
fe56b6ce
NC		 12317find_ifthen_state (bfd_vma pc,
12318 struct disassemble_info *info,
78933a4a 12319 bool little)
c22aaad1
PB		 12320{
12321 unsigned char b[2];
12322 unsigned int insn;
12323 int status;
12324 /* COUNT is twice the number of instructions seen. It will be odd if we
12325 just crossed an instruction boundary. */
12326 int count;
12327 int it_count;
12328 unsigned int seen_it;
12329 bfd_vma addr;
12330
12331 ifthen_address = pc;
12332 ifthen_state = 0;
12333
12334 addr = pc;
12335 count = 1;
12336 it_count = 0;
12337 seen_it = 0;
12338 /* Scan backwards looking for IT instructions, keeping track of where
12339 instruction boundaries are. We don't know if something is actually an
12340 IT instruction until we find a definite instruction boundary. */
12341 for (;;)
12342 {
fe56b6ce 12343 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 12344 {
12345 /* A symbol must be on an instruction boundary, and will not
12346 be within an IT block. */
12347 if (seen_it && (count & 1))
12348 break;
12349
12350 return;
12351 }
12352 addr -= 2;
fe56b6ce 12353 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 12354 if (status)
12355 return;
12356
12357 if (little)
12358 insn = (b[0]) | (b[1] << 8);
12359 else
12360 insn = (b[1]) | (b[0] << 8);
12361 if (seen_it)
12362 {
12363 if ((insn & 0xf800) < 0xe800)
12364 {
12365 /* Addr + 2 is an instruction boundary. See if this matches
12366 the expected boundary based on the position of the last
12367 IT candidate. */
12368 if (count & 1)
12369 break;
12370 seen_it = 0;
12371 }
12372 }
12373 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12374 {
5bc5ae88 12375 enum map_type type = MAP_ARM;
78933a4a 12376 bool found = mapping_symbol_for_insn (addr, info, &type);
5bc5ae88
RL		 12377
12378 if (!found || (found && type == MAP_THUMB))
12379 {
12380 /* This could be an IT instruction. */
12381 seen_it = insn;
12382 it_count = count >> 1;
12383 }
c22aaad1
PB		 12384 }
12385 if ((insn & 0xf800) >= 0xe800)
12386 count++;
12387 else
12388 count = (count + 2) | 1;
12389 /* IT blocks contain at most 4 instructions. */
12390 if (count >= 8 && !seen_it)
12391 return;
12392 }
12393 /* We found an IT instruction. */
12394 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12395 if ((ifthen_state & 0xf) == 0)
12396 ifthen_state = 0;
12397}
12398
b0e28b39
DJ		 12399/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12400 mapping symbol. */
12401
12402static int
77186045
NC		 12403is_mapping_symbol (struct disassemble_info *info,
12404 int n,
b0e28b39
DJ		 12405 enum map_type *map_type)
12406{
77186045 12407 const char *name = bfd_asymbol_name (info->symtab[n]);
b0e28b39 12408
77186045
NC		 12409 if (name[0] == '$'
12410 && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
b0e28b39
DJ		 12411 && (name[2] == 0 || name[2] == '.'))
12412 {
12413 *map_type = ((name[1] == 'a') ? MAP_ARM
12414 : (name[1] == 't') ? MAP_THUMB
12415 : MAP_DATA);
78933a4a 12416 return true;
b0e28b39
DJ		 12417 }
12418
78933a4a 12419 return false;
b0e28b39
DJ		 12420}
12421
12422/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12423 Returns nonzero if *MAP_TYPE was set. */
12424
12425static int
12426get_map_sym_type (struct disassemble_info *info,
12427 int n,
12428 enum map_type *map_type)
12429{
12430 /* If the symbol is in a different section, ignore it. */
12431 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12432 return false;
b0e28b39
DJ		 12433
12434 return is_mapping_symbol (info, n, map_type);
12435}
12436
12437/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 12438 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 12439
12440static int
fe56b6ce
NC		 12441get_sym_code_type (struct disassemble_info *info,
12442 int n,
e821645d 12443 enum map_type *map_type)
2087ad84
PB		 12444{
12445 elf_symbol_type *es;
12446 unsigned int type;
77186045 12447 asymbol * sym;
b0e28b39
DJ		 12448
12449 /* If the symbol is in a different section, ignore it. */
12450 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12451 return false;
2087ad84 12452
77186045
NC		 12453 /* PR 30230: Reject non-ELF symbols, eg synthetic ones. */
12454 sym = info->symtab[n];
12455 if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12456 return false;
12457
12458 es = (elf_symbol_type *) sym;
2087ad84
PB		 12459 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12460
12461 /* If the symbol has function type then use that. */
34e77a92 12462 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 12463 {
39d911fc
TP		 12464 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12465 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 12466 *map_type = MAP_THUMB;
12467 else
12468 *map_type = MAP_ARM;
78933a4a 12469 return true;
2087ad84
PB		 12470 }
12471
78933a4a 12472 return false;
2087ad84
PB		 12473}
12474
5bc5ae88
RL		 12475/* Search the mapping symbol state for instruction at pc. This is only
12476 applicable for elf target.
12477
12478 There is an assumption Here, info->private_data contains the correct AND
12479 up-to-date information about current scan process. The information will be
12480 used to speed this search process.
12481
12482 Return TRUE if the mapping state can be determined, and map_symbol
12483 will be updated accordingly. Otherwise, return FALSE. */
12484
78933a4a 12485static bool
5bc5ae88
RL		 12486mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12487 enum map_type *map_symbol)
12488{
796d6298
TC		 12489 bfd_vma addr, section_vma = 0;
12490 int n, last_sym = -1;
78933a4a
AM		 12491 bool found = false;
12492 bool can_use_search_opt_p = false;
796d6298 12493
76a95fac
LM		 12494 /* Sanity check. */
12495 if (info == NULL)
12496 return false;
12497
796d6298
TC		 12498 /* Default to DATA. A text section is required by the ABI to contain an
12499 INSN mapping symbol at the start. A data section has no such
12500 requirement, hence if no mapping symbol is found the section must
12501 contain only data. This however isn't very useful if the user has
12502 fully stripped the binaries. If this is the case use the section
12503 attributes to determine the default. If we have no section default to
12504 INSN as well, as we may be disassembling some raw bytes on a baremetal
12505 HEX file or similar. */
12506 enum map_type type = MAP_DATA;
12507 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12508 type = MAP_ARM;
5bc5ae88
RL		 12509 struct arm_private_data *private_data;
12510
76a95fac 12511 if (info->private_data == NULL || info->symtab == NULL
4eeb0013 12512 || info->symtab_size == 0
5bc5ae88 12513 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
78933a4a 12514 return false;
5bc5ae88
RL		 12515
12516 private_data = info->private_data;
5bc5ae88 12517
796d6298 12518 /* First, look for mapping symbols. */
4eeb0013
AM		 12519 if (pc <= private_data->last_mapping_addr)
12520 private_data->last_mapping_sym = -1;
12521
12522 /* Start scanning at the start of the function, or wherever
12523 we finished last time. */
12524 n = info->symtab_pos + 1;
12525
12526 /* If the last stop offset is different from the current one it means we
12527 are disassembling a different glob of bytes. As such the optimization
12528 would not be safe and we should start over. */
12529 can_use_search_opt_p
12530 = (private_data->last_mapping_sym >= 0
12531 && info->stop_offset == private_data->last_stop_offset);
12532
12533 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12534 n = private_data->last_mapping_sym;
12535
12536 /* Look down while we haven't passed the location being disassembled.
12537 The reason for this is that there's no defined order between a symbol
12538 and an mapping symbol that may be at the same address. We may have to
12539 look at least one position ahead. */
12540 for (; n < info->symtab_size; n++)
12541 {
12542 addr = bfd_asymbol_value (info->symtab[n]);
12543 if (addr > pc)
12544 break;
12545 if (get_map_sym_type (info, n, &type))
12546 {
12547 last_sym = n;
12548 found = true;
12549 }
12550 }
5bc5ae88 12551
4eeb0013
AM		 12552 if (!found)
12553 {
12554 n = info->symtab_pos;
12555 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12556 n = private_data->last_mapping_sym;
12557
12558 /* No mapping symbol found at this address. Look backwards
12559 for a preceeding one, but don't go pass the section start
12560 otherwise a data section with no mapping symbol can pick up
12561 a text mapping symbol of a preceeding section. The documentation
12562 says section can be NULL, in which case we will seek up all the
12563 way to the top. */
12564 if (info->section)
12565 section_vma = info->section->vma;
12566
12567 for (; n >= 0; n--)
12568 {
12569 addr = bfd_asymbol_value (info->symtab[n]);
12570 if (addr < section_vma)
12571 break;
796d6298 12572
4eeb0013
AM		 12573 if (get_map_sym_type (info, n, &type))
12574 {
12575 last_sym = n;
12576 found = true;
12577 break;
12578 }
12579 }
12580 }
796d6298
TC		 12581
12582 /* If no mapping symbol was found, try looking up without a mapping
12583 symbol. This is done by walking up from the current PC to the nearest
12584 symbol. We don't actually have to loop here since symtab_pos will
12585 contain the nearest symbol already. */
12586 if (!found)
5bc5ae88 12587 {
796d6298
TC		 12588 n = info->symtab_pos;
12589 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 12590 {
796d6298 12591 last_sym = n;
78933a4a 12592 found = true;
5bc5ae88
RL		 12593 }
12594 }
12595
796d6298
TC		 12596 private_data->last_mapping_sym = last_sym;
12597 private_data->last_type = type;
12598 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 12599
12600 *map_symbol = type;
12601 return found;
12602}
12603
0313a2b8
NC		 12604/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12605 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 12606 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 12607
12608 FIXME: This could more efficiently implemented as a constant array,
12609 although it would also be less robust. */
12610
12611static void
12612select_arm_features (unsigned long mach,
12613 arm_feature_set * features)
12614{
c0c468d5
TP		 12615 arm_feature_set arch_fset;
12616 const arm_feature_set fpu_any = FPU_ANY;
12617
1af1dd51
MW		 12618#undef ARM_SET_FEATURES
12619#define ARM_SET_FEATURES(FSET) \
12620 { \
12621 const arm_feature_set fset = FSET; \
c0c468d5 12622 arch_fset = fset; \
1af1dd51 12623 }
823d2571 12624
c0c468d5
TP		 12625 /* When several architecture versions share the same bfd_mach_arm_XXX value
12626 the most featureful is chosen. */
0313a2b8
NC		 12627 switch (mach)
12628 {
c0c468d5
TP		 12629 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
12630 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12631 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
12632 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12633 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
12634 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12635 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
12636 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12637 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12638 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 12639 case bfd_mach_arm_ep9312:
c0c468d5
TP		 12640 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
12641 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 12642 break;
c0c468d5
TP		 12643 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12644 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12645 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12646 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
12647 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12648 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12649 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12650 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12651 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12652 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12653 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12654 case bfd_mach_arm_8:
12655 {
aab2c27d
MM		 12656 /* Add bits for extensions that Armv8.6-A recognizes. */
12657 arm_feature_set armv8_6_ext_fset
0632eeea 12658 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 12659 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12660 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 12661 break;
12662 }
12663 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12664 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12665 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12666 case bfd_mach_arm_8_1M_MAIN:
12667 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12668 arm_feature_set mve_all
12669 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12670 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12671 force_thumb = 1;
12672 break;
3197e593 12673 case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
c0c468d5 12674 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12675 extensions, with the exception of MVE as that clashes with NEON. */
12676 case bfd_mach_arm_unknown:
3197e593 12677 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
2da2eaf4 12678 break;
0313a2b8
NC		 12679 default:
12680 abort ();
12681 }
1af1dd51 12682#undef ARM_SET_FEATURES
c0c468d5
TP		 12683
12684 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12685 and thus on bfd_mach_arm_XXX value. Therefore for a given
12686 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12687 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12688}
12689
12690
58efb6c0
NC		 12691/* NOTE: There are no checks in these routines that
12692 the relevant number of data bytes exist. */
baf0cc5e 12693
58efb6c0 12694static int
78933a4a 12695print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
252b5132 12696{
c19d1205 12697 unsigned char b[4];
2480b6fa 12698 unsigned long given;
78933a4a
AM		 12699 int status;
12700 int is_thumb = false;
12701 int is_data = false;
12702 int little_code;
e821645d 12703 unsigned int size = 4;
78933a4a
AM		 12704 void (*printer) (bfd_vma, struct disassemble_info *, long);
12705 bool found = false;
b0e28b39 12706 struct arm_private_data *private_data;
58efb6c0 12707
1d67fe3b
TT		 12708 /* Clear instruction information field. */
12709 info->insn_info_valid = 0;
12710 info->branch_delay_insns = 0;
12711 info->data_size = 0;
12712 info->insn_type = dis_noninsn;
12713 info->target = 0;
12714 info->target2 = 0;
12715
dd92f639
NC		 12716 if (info->disassembler_options)
12717 {
65b48a81 12718 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12719
58efb6c0 12720 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12721 info->disassembler_options = NULL;
12722 }
b34976b6 12723
0313a2b8
NC		 12724 /* PR 10288: Control which instructions will be disassembled. */
12725 if (info->private_data == NULL)
12726 {
b0e28b39 12727 static struct arm_private_data private;
0313a2b8
NC		 12728
12729 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12730 /* If the user did not use the -m command line switch then default to
12731 disassembling all types of ARM instruction.
43e65147 12732
0313a2b8
NC		 12733 The info->mach value has to be ignored as this will be based on
12734 the default archictecture for the target and/or hints in the notes
12735 section, but it will never be greater than the current largest arm
12736 machine value (iWMMXt2), which is only equivalent to the V5TE
12737 architecture. ARM architectures have advanced beyond the machine
12738 value encoding, and these newer architectures would be ignored if
12739 the machine value was used.
12740
12741 Ie the -m switch is used to restrict which instructions will be
12742 disassembled. If it is necessary to use the -m switch to tell
12743 objdump that an ARM binary is being disassembled, eg because the
12744 input is a raw binary file, but it is also desired to disassemble
12745 all ARM instructions then use "-marm". This will select the
12746 "unknown" arm architecture which is compatible with any ARM
12747 instruction. */
12748 info->mach = bfd_mach_arm_unknown;
12749
12750 /* Compute the architecture bitmask from the machine number.
12751 Note: This assumes that the machine number will not change
12752 during disassembly.... */
b0e28b39 12753 select_arm_features (info->mach, & private.features);
0313a2b8 12754
1fbaefec
PB		 12755 private.last_mapping_sym = -1;
12756 private.last_mapping_addr = 0;
796d6298 12757 private.last_stop_offset = 0;
b0e28b39
DJ		 12758
12759 info->private_data = & private;
0313a2b8 12760 }
b0e28b39
DJ		 12761
12762 private_data = info->private_data;
12763
bd2e2557
SS		 12764 /* Decide if our code is going to be little-endian, despite what the
12765 function argument might say. */
12766 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12767
b0e28b39
DJ		 12768 /* For ELF, consult the symbol table to determine what kind of code
12769 or data we have. */
8977d4b2 12770 if (info->symtab_size != 0
e821645d
DJ		 12771 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12772 {
12773 bfd_vma addr;
796d6298 12774 int n;
e821645d 12775 int last_sym = -1;
b0e28b39 12776 enum map_type type = MAP_ARM;
e821645d 12777
796d6298
TC		 12778 found = mapping_symbol_for_insn (pc, info, &type);
12779 last_sym = private_data->last_mapping_sym;
e821645d 12780
1fbaefec
PB		 12781 is_thumb = (private_data->last_type == MAP_THUMB);
12782 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12783
e821645d
DJ		 12784 /* Look a little bit ahead to see if we should print out
12785 two or four bytes of data. If there's a symbol,
12786 mapping or otherwise, after two bytes then don't
12787 print more. */
12788 if (is_data)
12789 {
12790 size = 4 - (pc & 3);
12791 for (n = last_sym + 1; n < info->symtab_size; n++)
12792 {
12793 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12794 if (addr > pc
12795 && (info->section == NULL
12796 || info->section == info->symtab[n]->section))
e821645d
DJ		 12797 {
12798 if (addr - pc < size)
12799 size = addr - pc;
12800 break;
12801 }
12802 }
12803 /* If the next symbol is after three bytes, we need to
12804 print only part of the data, so that we can use either
12805 .byte or .short. */
12806 if (size == 3)
12807 size = (pc & 1) ? 1 : 2;
12808 }
12809 }
12810
12811 if (info->symbols != NULL)
252b5132 12812 {
5876e06d
NC		 12813 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12814 {
2f0ca46a 12815 coff_symbol_type * cs;
b34976b6 12816
5876e06d
NC		 12817 cs = coffsymbol (*info->symbols);
12818 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12819 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12820 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12821 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12822 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12823 }
e821645d
DJ		 12824 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12825 && !found)
5876e06d 12826 {
2087ad84
PB		 12827 /* If no mapping symbol has been found then fall back to the type
12828 of the function symbol. */
e821645d
DJ		 12829 elf_symbol_type * es;
12830 unsigned int type;
2087ad84 12831
e821645d
DJ		 12832 es = *(elf_symbol_type **)(info->symbols);
12833 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12834
39d911fc
TP		 12835 is_thumb =
12836 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12837 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12838 }
e49d43ff
TG		 12839 else if (bfd_asymbol_flavour (*info->symbols)
12840 == bfd_target_mach_o_flavour)
12841 {
12842 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12843
12844 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12845 }
5876e06d 12846 }
b34976b6 12847
e821645d 12848 if (force_thumb)
78933a4a 12849 is_thumb = true;
e821645d 12850
b8f9ee44
CL		 12851 if (is_data)
12852 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12853 else
12854 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12855
c19d1205 12856 info->bytes_per_line = 4;
252b5132 12857
1316c8b3
NC		 12858 /* PR 10263: Disassemble data if requested to do so by the user. */
12859 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12860 {
12861 int i;
12862
1316c8b3 12863 /* Size was already set above. */
e821645d
DJ		 12864 info->bytes_per_chunk = size;
12865 printer = print_insn_data;
12866
fe56b6ce 12867 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12868 given = 0;
12869 if (little)
12870 for (i = size - 1; i >= 0; i--)
12871 given = b[i] | (given << 8);
12872 else
12873 for (i = 0; i < (int) size; i++)
12874 given = b[i] | (given << 8);
12875 }
12876 else if (!is_thumb)
252b5132 12877 {
c19d1205
ZW		 12878 /* In ARM mode endianness is a straightforward issue: the instruction
12879 is four bytes long and is either ordered 0123 or 3210. */
12880 printer = print_insn_arm;
12881 info->bytes_per_chunk = 4;
4a5329c6 12882 size = 4;
c19d1205 12883
0313a2b8 12884 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12885 if (little_code)
2480b6fa 12886 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12887 else
2480b6fa 12888 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12889 }
58efb6c0 12890 else
252b5132 12891 {
c19d1205
ZW		 12892 /* In Thumb mode we have the additional wrinkle of two
12893 instruction lengths. Fortunately, the bits that determine
12894 the length of the current instruction are always to be found
12895 in the first two bytes. */
4a5329c6 12896 printer = print_insn_thumb16;
c19d1205 12897 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12898 size = 2;
12899
fe56b6ce 12900 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12901 if (little_code)
9a2ff3f5
AM		 12902 given = (b[0]) | (b[1] << 8);
12903 else
12904 given = (b[1]) | (b[0] << 8);
12905
c19d1205 12906 if (!status)
252b5132 12907 {
c19d1205
ZW		 12908 /* These bit patterns signal a four-byte Thumb
12909 instruction. */
12910 if ((given & 0xF800) == 0xF800
12911 || (given & 0xF800) == 0xF000
12912 || (given & 0xF800) == 0xE800)
252b5132 12913 {
0313a2b8 12914 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12915 if (little_code)
c19d1205 12916 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12917 else
c19d1205
ZW		 12918 given = (b[1]) | (b[0] << 8) | (given << 16);
12919
12920 printer = print_insn_thumb32;
4a5329c6 12921 size = 4;
252b5132 12922 }
252b5132 12923 }
c22aaad1
PB		 12924
12925 if (ifthen_address != pc)
0313a2b8 12926 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12927
12928 if (ifthen_state)
12929 {
12930 if ((ifthen_state & 0xf) == 0x8)
12931 ifthen_next_state = 0;
12932 else
12933 ifthen_next_state = (ifthen_state & 0xe0)
12934 | ((ifthen_state & 0xf) << 1);
12935 }
252b5132 12936 }
b34976b6 12937
c19d1205
ZW		 12938 if (status)
12939 {
12940 info->memory_error_func (status, pc, info);
12941 return -1;
12942 }
6a56ec7e
NC		 12943 if (info->flags & INSN_HAS_RELOC)
12944 /* If the instruction has a reloc associated with it, then
12945 the offset field in the instruction will actually be the
12946 addend for the reloc. (We are using REL type relocs).
12947 In such cases, we can ignore the pc when computing
12948 addresses, since the addend is not currently pc-relative. */
12949 pc = 0;
b34976b6 12950
4a5329c6 12951 printer (pc, info, given);
c22aaad1
PB		 12952
12953 if (is_thumb)
12954 {
12955 ifthen_state = ifthen_next_state;
12956 ifthen_address += size;
12957 }
4a5329c6 12958 return size;
252b5132
RH		 12959}
12960
12961int
4a5329c6 12962print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12963{
bd2e2557
SS		 12964 /* Detect BE8-ness and record it in the disassembler info. */
12965 if (info->flavour == bfd_target_elf_flavour
12966 && info->section != NULL
12967 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12968 info->endian_code = BFD_ENDIAN_LITTLE;
12969
78933a4a 12970 return print_insn (pc, info, false);
58efb6c0 12971}
01c7f630 12972
58efb6c0 12973int
4a5329c6 12974print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12975{
78933a4a 12976 return print_insn (pc, info, true);
58efb6c0 12977}
252b5132 12978
471b9d15 12979const disasm_options_and_args_t *
65b48a81
PB		 12980disassembler_options_arm (void)
12981{
471b9d15 12982 static disasm_options_and_args_t *opts_and_args;
65b48a81 12983
471b9d15 12984 if (opts_and_args == NULL)
65b48a81 12985 {
471b9d15 12986 disasm_options_t *opts;
65b48a81 12987 unsigned int i;
471b9d15
MR		 12988
12989 opts_and_args = XNEW (disasm_options_and_args_t);
12990 opts_and_args->args = NULL;
12991
12992 opts = &opts_and_args->options;
65b48a81
PB		 12993 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12994 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12995 opts->arg = NULL;
65b48a81
PB		 12996 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12997 {
12998 opts->name[i] = regnames[i].name;
12999 if (regnames[i].description != NULL)
13000 opts->description[i] = _(regnames[i].description);
13001 else
13002 opts->description[i] = NULL;
13003 }
13004 /* The array we return must be NULL terminated. */
13005 opts->name[i] = NULL;
13006 opts->description[i] = NULL;
13007 }
13008
471b9d15 13009 return opts_and_args;
65b48a81
PB		 13010}
13011
58efb6c0 13012void
4a5329c6 13013print_arm_disassembler_options (FILE *stream)
58efb6c0 13014{
65b48a81 13015 unsigned int i, max_len = 0;
58efb6c0
NC		 13016 fprintf (stream, _("\n\
13017The following ARM specific disassembler options are supported for use with\n\
13018the -M switch:\n"));
b34976b6 13019
65b48a81
PB		 13020 for (i = 0; i < NUM_ARM_OPTIONS; i++)
13021 {
13022 unsigned int len = strlen (regnames[i].name);
13023 if (max_len < len)
13024 max_len = len;
13025 }
58efb6c0 13026
65b48a81
PB		 13027 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
13028 fprintf (stream, " %s%*c %s\n",
13029 regnames[i].name,
13030 (int)(max_len - strlen (regnames[i].name)), ' ',
13031 _(regnames[i].description));
252b5132 13032}
A mirror of the official binutils-gdb repository