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MIPS/gas: Reject $0 as source register for DAUI instruction
[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
73cd51e5
AV		 267 MVE_NONE
268};
269
270enum mve_unpredictable
271{
272 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
273 */
143275ea
AV		 274 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
275 fcB = 1 (vpt). */
276 UNPRED_R13, /* Unpredictable because r13 (sp) or
277 r15 (sp) used. */
9743db03 278 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 279 UNPRED_Q_GT_4, /* Unpredictable because
280 vec reg start > 4 (vld4/st4). */
281 UNPRED_Q_GT_6, /* Unpredictable because
282 vec reg start > 6 (vld2/st2). */
283 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
284 and WB bit = 1. */
ef1576a1
AV		 285 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
286 equal. */
287 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 288 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
289 same. */
c507f10b
AV		 290 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
291 size = 1. */
292 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
293 size = 2. */
73cd51e5
AV		 294 UNPRED_NONE /* No unpredictable behavior. */
295};
296
297enum mve_undefined
298{
ed63aa17 299 UNDEF_SIZE, /* undefined size. */
bf0b396d 300 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 301 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 302 UNDEF_SIZE_3, /* undefined because size == 3. */
303 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 304 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 305 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
306 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
307 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
308 size == 0. */
309 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
310 size == 1. */
311 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 312 UNDEF_VCVT_IMM6, /* imm6 < 32. */
313 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 314 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
315 op1 == (0 or 1). */
316 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
317 op2 == 0 and op1 == (0 or 1). */
318 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
319 in {0xx1, x0x1}. */
d3b63143 320 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 321 UNDEF_NONE /* no undefined behavior. */
322};
323
6b5d3a4d
ZW		 324struct opcode32
325{
823d2571
TG		 326 arm_feature_set arch; /* Architecture defining this insn. */
327 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 328 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 329 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 330};
331
73cd51e5
AV		 332/* MVE opcodes. */
333
334struct mopcode32
335{
336 arm_feature_set arch; /* Architecture defining this insn. */
337 enum mve_instructions mve_op; /* Specific mve instruction for faster
338 decoding. */
339 unsigned long value; /* If arch is 0 then value is a sentinel. */
340 unsigned long mask; /* Recognise insn if (op & mask) == value. */
341 const char * assembler; /* How to disassemble this insn. */
342};
343
6b0dd094
AV		 344enum isa {
345 ANY,
346 T32,
347 ARM
348};
349
350
351/* Shared (between Arm and Thumb mode) opcode. */
352struct sopcode32
353{
354 enum isa isa; /* Execution mode instruction availability. */
355 arm_feature_set arch; /* Architecture defining this insn. */
356 unsigned long value; /* If arch is 0 then value is a sentinel. */
357 unsigned long mask; /* Recognise insn if (op & mask) == value. */
358 const char * assembler; /* How to disassemble this insn. */
359};
360
6b5d3a4d
ZW		 361struct opcode16
362{
823d2571 363 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 364 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 365 const char *assembler; /* How to disassemble this insn. */
366};
b7693d02 367
8f06b2d8 368/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 369
2fbad815 370 %% %
4a5329c6 371
c22aaad1 372 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 373 %q print shifter argument
e2efe87d
MGD		 374 %u print condition code (unconditional in ARM mode,
375 UNPREDICTABLE if not AL in Thumb)
4a5329c6 376 %A print address for ldc/stc/ldf/stf instruction
16980d0b 377 %B print vstm/vldm register list
efd6b359 378 %C print vscclrm register list
4a5329c6 379 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 380 %J print register for VLDR instruction
381 %K print address for VLDR instruction
4a5329c6
ZW		 382 %F print the COUNT field of a LFM/SFM instruction.
383 %P print floating point precision in arithmetic insn
384 %Q print floating point precision in ldf/stf insn
385 %R print floating point rounding mode
386
33399f07 387 %<bitfield>c print as a condition code (for vsel)
4a5329c6 388 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 389 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
390 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 391 %<bitfield>d print the bitfield in decimal
16980d0b 392 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 393 %<bitfield>x print the bitfield in hex
394 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 395 %<bitfield>f print a floating point constant if >7 else a
396 floating point register
4a5329c6
ZW		 397 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
398 %<bitfield>g print as an iWMMXt 64-bit register
399 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 400 %<bitfield>D print as a NEON D register
401 %<bitfield>Q print as a NEON Q register
c28eeff2 402 %<bitfield>V print as a NEON D or Q register
6f1c2142 403 %<bitfield>E print a quarter-float immediate value
4a5329c6 404
16980d0b 405 %y<code> print a single precision VFP reg.
2fbad815 406 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 407 %z<code> print a double precision VFP reg
2fbad815 408 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 409
16980d0b
JB		 410 %<bitfield>'c print specified char iff bitfield is all ones
411 %<bitfield>`c print specified char iff bitfield is all zeroes
412 %<bitfield>?ab... select from array of values in big endian order
43e65147 413
2fbad815 414 %L print as an iWMMXt N/M width field.
4a5329c6 415 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 416 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 417 versions.
418 %i print 5-bit immediate in bits 8,3..0
419 (print "32" when 0)
fe56b6ce 420 %r print register offset address for wldt/wstr instruction. */
2fbad815 421
21d799b5 422enum opcode_sentinel_enum
05413229
NC		 423{
424 SENTINEL_IWMMXT_START = 1,
425 SENTINEL_IWMMXT_END,
426 SENTINEL_GENERIC_START
427} opcode_sentinels;
428
aefd8a40 429#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 430#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
431#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 432#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 433
8f06b2d8 434/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 435
6b0dd094 436static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 437{
2fbad815 438 /* XScale instructions. */
6b0dd094 439 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 440 0x0e200010, 0x0fff0ff0,
441 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 442 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 443 0x0e280010, 0x0fff0ff0,
444 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 445 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 446 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 447 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 448 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 449 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 450 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 451
2fbad815 452 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 453 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
454 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 455 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 456 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 457 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 458 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 459 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 460 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 461 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 462 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 463 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 464 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 465 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 467 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 469 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 470 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 471 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 473 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 475 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 477 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 478 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 479 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 481 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 483 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 485 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 487 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 489 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 491 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 493 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 495 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 497 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 499 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 501 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 503 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 505 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 507 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 509 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 511 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 513 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 515 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 517 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 519 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 521 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 523 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 525 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 527 0x0e800120, 0x0f800ff0,
528 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 530 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 532 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 534 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 536 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 538 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 540 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 542 0x0e8000a0, 0x0f800ff0,
543 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 545 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 547 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 549 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 551 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 553 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 554 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 555 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 557 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 559 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 561 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 563 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 565 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 567 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 569 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 571 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 573 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 575 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 577 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 579 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 581 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 583 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 585 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 587 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 589 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 591 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 593 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 595 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 597 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 599 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 601 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 603 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 605 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 606 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 607 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 608
fe56b6ce 609 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 611 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 613 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 615 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 617 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 619 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 621 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 623 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 625 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 627 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 629 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 631 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 633 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 635 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 637 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 639 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 641 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 643 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 645 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 647 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 649 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 651 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 653 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 655 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 657 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 659 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 661 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 663 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 665 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 667 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 669 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 671 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 673 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 675 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 677 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 679 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 681 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 683 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 685 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 687 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 689 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 691 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 693 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 695 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 696
efd6b359
AV		 697 /* Armv8.1-M Mainline instructions. */
698 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
699 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
700 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
701 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
702
16a1fa25 703 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 704 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 705 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 706 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 707 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
708
fe56b6ce 709 /* Register load/store. */
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 711 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 713 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 715 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 717 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 719 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 721 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 723 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 725 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 727 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 729 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 731 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 733 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 735 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 737 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 739 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 741 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 742 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
743 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
744 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
745 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 746
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 748 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 750 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 752 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 754 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 755
fe56b6ce 756 /* Data transfer between ARM and NEON registers. */
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 758 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 760 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 762 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 764 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 766 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 768 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 770 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 772 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 773 /* Half-precision conversion instructions. */
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 775 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 777 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 779 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 781 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 782
fe56b6ce 783 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 785 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 787 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 789 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 791 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 793 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 795 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 797 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 799 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 801 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 803 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 805 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 807 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 808 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 809 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 811 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 813 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 814 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 815 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 817 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 819 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 821 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 823 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 825 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 827 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 829 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 831 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 833 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 835 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 839 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 841 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 843 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 845 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 847 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 849 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 851 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 853 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 855 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 856 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 857 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 859 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 861 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 863 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 865 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 867 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 869 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 871 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 873 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 875 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 877 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 879 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 881 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 883 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 885 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 887 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 889 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 891 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 893 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 895 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 897 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 899 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 901 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 903 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 905 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 907 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 909 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 911 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 913 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 915 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 917 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 919 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 921 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 922
923 /* Cirrus coprocessor instructions. */
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 925 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 927 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 929 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 931 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 933 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 935 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 937 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 939 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 940 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 941 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 942 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 943 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 945 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 947 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 949 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 951 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 953 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 955 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 957 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 959 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 961 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 963 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 965 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 966 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 967 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 968 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 969 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 971 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 973 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 975 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 977 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 979 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 981 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 983 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 985 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 987 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 989 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 991 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 993 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 995 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 997 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 999 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1001 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1003 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1005 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1007 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1009 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1011 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1013 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1015 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1017 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1019 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1021 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1023 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1025 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1027 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1029 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1031 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1033 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1035 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1037 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1039 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1041 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1043 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1044 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1045 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1046 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1047 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1049 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1051 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1053 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1055 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1057 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1059 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1061 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1063 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1065 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1067 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1069 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1071 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1073 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1075 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1077 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1079 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1081 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1083 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1085 0x0e000600, 0x0ff00f10,
1086 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1088 0x0e100600, 0x0ff00f10,
1089 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1091 0x0e200600, 0x0ff00f10,
1092 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1094 0x0e300600, 0x0ff00f10,
1095 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1096
62f3b8c8 1097 /* VFP Fused multiply add instructions. */
6b0dd094 1098 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1099 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1100 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1101 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1102 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1103 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1104 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1105 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1106 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1107 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1108 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1109 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1110 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1111 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1112 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1113 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1114
33399f07 1115 /* FP v5. */
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1117 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1118 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1119 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1120 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1121 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1122 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1123 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1124 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1125 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1126 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1127 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1128 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1129 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1130 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1131 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1132 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1133 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1134 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1135 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1136 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1137 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1138 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1139 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1140
05413229 1141 /* Generic coprocessor instructions. */
6b0dd094
AV		 1142 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1143 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1144 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1145 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1146 0x0c500000, 0x0ff00000,
1147 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1148 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1149 0x0e000000, 0x0f000010,
1150 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1151 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1152 0x0e10f010, 0x0f10f010,
1153 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1154 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1155 0x0e100010, 0x0f100010,
1156 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1157 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1158 0x0e000010, 0x0f100010,
1159 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1160 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1161 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1162 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1163 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1164
05413229 1165 /* V6 coprocessor instructions. */
6b0dd094 1166 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1167 0xfc500000, 0xfff00000,
1168 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1169 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1170 0xfc400000, 0xfff00000,
1171 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1172
c28eeff2 1173 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1174 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1175 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1176 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1177 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1178 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1179 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1181 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1183 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1185 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1187 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1189 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1191 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1193 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1194
c604a79a 1195 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1196 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1197 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1198 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1199 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1200
dec41383 1201 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1203 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1205 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1207 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1209 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1211 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1213 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1215 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1216 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1217 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1218
05413229 1219 /* V5 coprocessor instructions. */
6b0dd094 1220 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1221 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1223 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1225 0xfe000000, 0xff000010,
1226 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1227 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1228 0xfe000010, 0xff100010,
1229 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1231 0xfe100010, 0xff100010,
1232 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1233
b0c11777
RL		 1234 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1235 cp_num: bit <11:8> == 0b1001.
1236 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1237 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1238 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1239 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1240 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1241 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1242 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1243 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1244 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1245 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1246 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1247 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1248 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1249 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1250 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1251 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1252 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1253 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1254 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1255 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1256 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1257 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1258 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1259 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1260 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1261 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1262 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1263 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1264 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1265 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1266 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1267 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1268 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1269 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1270 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1271 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1272 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1273 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1274 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1275 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1276 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1277 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1278 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1279 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1280 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1281 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1282 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1284 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1286 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1288 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1289 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1290 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1292 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1293 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1294 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1295 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1296 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1297 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1298 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1299 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1300 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1302 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1304 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1306 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1307
49e8a725 1308 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1310 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1311
6b0dd094 1312 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1313};
1314
16980d0b
JB		 1315/* Neon opcode table: This does not encode the top byte -- that is
1316 checked by the print_insn_neon routine, as it depends on whether we are
1317 doing thumb32 or arm32 disassembly. */
1318
1319/* print_insn_neon recognizes the following format control codes:
1320
1321 %% %
1322
c22aaad1 1323 %c print condition code
e2efe87d
MGD		 1324 %u print condition code (unconditional in ARM mode,
1325 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1326 %A print v{st,ld}[1234] operands
1327 %B print v{st,ld}[1234] any one operands
1328 %C print v{st,ld}[1234] single->all operands
1329 %D print scalar
1330 %E print vmov, vmvn, vorr, vbic encoded constant
1331 %F print vtbl,vtbx register list
1332
1333 %<bitfield>r print as an ARM register
1334 %<bitfield>d print the bitfield in decimal
1335 %<bitfield>e print the 2^N - bitfield in decimal
1336 %<bitfield>D print as a NEON D register
1337 %<bitfield>Q print as a NEON Q register
1338 %<bitfield>R print as a NEON D or Q register
1339 %<bitfield>Sn print byte scaled width limited by n
1340 %<bitfield>Tn print short scaled width limited by n
1341 %<bitfield>Un print long scaled width limited by n
43e65147 1342
16980d0b
JB		 1343 %<bitfield>'c print specified char iff bitfield is all ones
1344 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1345 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1346
1347static const struct opcode32 neon_opcodes[] =
1348{
fe56b6ce 1349 /* Extract. */
823d2571
TG		 1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2b00840, 0xffb00850,
1352 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2b00000, 0xffb00810,
1355 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1356
9743db03
AV		 1357 /* Data transfer between ARM and NEON registers. */
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1370
fe56b6ce 1371 /* Move data element to all lanes. */
823d2571
TG		 1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1378
fe56b6ce 1379 /* Table lookup. */
823d2571
TG		 1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1384
8e79c3df 1385 /* Half-precision conversions. */
823d2571
TG		 1386 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1387 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1388 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1389 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1390
1391 /* NEON fused multiply add instructions. */
823d2571 1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1393 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1395 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1397 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1399 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1400
fe56b6ce 1401 /* Two registers, miscellaneous. */
823d2571
TG		 1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1403 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1404 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1405 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1407 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1409 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1410 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1411 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1412 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1413 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1414 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1415 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1416 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1417 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1418 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1419 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1420 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1421 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1422 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1423 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf3b20300, 0xffb30fd0,
1446 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1449 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1450 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1454 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1494 0xf3bb0600, 0xffbf0e10,
823d2571 1495 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1497 0xf3b70600, 0xffbf0e10,
1498 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1499
fe56b6ce 1500 /* Three registers of the same length. */
823d2571
TG		 1501 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1502 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1503 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1504 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1505 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1506 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1507 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1508 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1509 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1510 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1511 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1512 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1513 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1514 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1516 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1518 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1520 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1522 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1540 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1542 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1544 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1546 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1548 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1550 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1552 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1554 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1556 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1558 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1560 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1562 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1564 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1568 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1572 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1574 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1576 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1578 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1580 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1582 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1584 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1586 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1588 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1590 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1592 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1594 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1596 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1597 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1598 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1600 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1602 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1604 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1606 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1608 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1610 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2000b00, 0xff800f10,
1619 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2000b10, 0xff800f10,
1622 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3000b00, 0xff800f10,
1631 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf2000000, 0xfe800f10,
1634 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf2000010, 0xfe800f10,
1637 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639 0xf2000100, 0xfe800f10,
1640 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2000200, 0xfe800f10,
1643 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf2000210, 0xfe800f10,
1646 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf2000300, 0xfe800f10,
1649 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf2000310, 0xfe800f10,
1652 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2000400, 0xfe800f10,
1655 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf2000410, 0xfe800f10,
1658 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2000500, 0xfe800f10,
1661 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663 0xf2000510, 0xfe800f10,
1664 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf2000600, 0xfe800f10,
1667 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf2000610, 0xfe800f10,
1670 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2000700, 0xfe800f10,
1673 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf2000710, 0xfe800f10,
1676 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf2000910, 0xfe800f10,
1679 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2000a00, 0xfe800f10,
1682 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf2000a10, 0xfe800f10,
1685 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1687 0xf3000b10, 0xff800f10,
1688 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1690 0xf3000c10, 0xff800f10,
1691 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1692
fe56b6ce 1693 /* One register and an immediate value. */
823d2571
TG		 1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1720
fe56b6ce 1721 /* Two registers and a shift amount. */
823d2571
TG		 1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1731 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733 0xf2880950, 0xfeb80fd0,
1734 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1752 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1754 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756 0xf2900950, 0xfeb00fd0,
1757 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf2a00950, 0xfea00fd0,
1802 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1826 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1832 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1838 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2a00e10, 0xfea00e90,
1841 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1843 0xf2a00c10, 0xfea00e90,
1844 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1845
fe56b6ce 1846 /* Three registers of different lengths. */
823d2571
TG		 1847 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1848 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf2800400, 0xff800f50,
1853 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855 0xf2800600, 0xff800f50,
1856 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2800900, 0xff800f50,
1859 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf2800b00, 0xff800f50,
1862 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800d00, 0xff800f50,
1865 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf3800400, 0xff800f50,
1868 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf3800600, 0xff800f50,
1871 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf2800000, 0xfe800f50,
1874 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800100, 0xfe800f50,
1877 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf2800200, 0xfe800f50,
1880 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2800300, 0xfe800f50,
1883 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf2800500, 0xfe800f50,
1886 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf2800700, 0xfe800f50,
1889 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf2800800, 0xfe800f50,
1892 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf2800a00, 0xfe800f50,
1895 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf2800c00, 0xfe800f50,
1898 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1899
fe56b6ce 1900 /* Two registers and a scalar. */
823d2571
TG		 1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1904 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1905 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1906 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1912 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1913 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1914 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1920 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1921 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1922 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1932 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1933 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1934 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1938 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1939 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1940 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1944 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1945 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1946 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952 0xf2800240, 0xfe800f50,
1953 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf2800640, 0xfe800f50,
1956 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf2800a40, 0xfe800f50,
1959 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1961 0xf2800e40, 0xff800f50,
1962 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1964 0xf2800f40, 0xff800f50,
1965 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1967 0xf3800e40, 0xff800f50,
1968 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1970 0xf3800f40, 0xff800f50,
1971 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1972 },
16980d0b 1973
fe56b6ce 1974 /* Element and structure load/store. */
823d2571
TG		 1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1980 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1986 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1990 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1992 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1994 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2000 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2002 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2006 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2008 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2010 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2012 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2013
2014 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2015};
2016
73cd51e5
AV		 2017/* mve opcode table. */
2018
2019/* print_insn_mve recognizes the following format control codes:
2020
2021 %% %
2022
ef1576a1
AV		 2023 %a print '+' or '-' or imm offset in vldr[bhwd] and
2024 vstr[bhwd]
9743db03 2025 %c print condition code
aef6d006
AV		 2026 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2027 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2028 %i print MVE predicate(s) for vpt and vpst
bf0b396d 2029 %m print rounding mode for vcvt and vrint
143275ea 2030 %n print vector comparison code for predicated instruction
bf0b396d 2031 %s print size for various vcvt instructions
143275ea
AV		 2032 %v print vector predicate for instruction in predicated
2033 block
ef1576a1 2034 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2035 %w print writeback mode for MVE v{st,ld}[24]
2036 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2037 %E print vmov, vmvn, vorr, vbic encoded constant
2038 %N print generic index for vmov
14925797 2039 %T print bottom ('b') or top ('t') of source register
d3b63143 2040 %X print exchange field in vmla* instructions
04d54ace 2041
9743db03 2042 %<bitfield>r print as an ARM register
04d54ace 2043 %<bitfield>d print the bitfield in decimal
d3b63143 2044 %<bitfield>A print accumulate or not
143275ea 2045 %<bitfield>Q print as a MVE Q register
c507f10b 2046 %<bitfield>F print as a MVE S register
143275ea
AV		 2047 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2048 UNPREDICTABLE
2049 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2050 %<bitfield>I print carry flag or not
ef1576a1 2051 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2052 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2053 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2054 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2055 %<bitfield>o print rotate value for vcmul
1c8f2df8 2056 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2057 %<bitfield>x print the bitfield in hex.
1c8f2df8 2058 */
73cd51e5
AV		 2059
2060static const struct mopcode32 mve_opcodes[] =
2061{
143275ea
AV		 2062 /* MVE. */
2063
2064 {ARM_FEATURE_COPROC (FPU_MVE),
2065 MVE_VPST,
2066 0xfe310f4d, 0xffbf1fff,
2067 "vpst%i"
2068 },
2069
2070 /* Floating point VPT T1. */
2071 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2072 MVE_VPT_FP_T1,
2073 0xee310f00, 0xefb10f50,
2074 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2075 /* Floating point VPT T2. */
2076 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2077 MVE_VPT_FP_T2,
2078 0xee310f40, 0xefb10f50,
2079 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2080
2081 /* Vector VPT T1. */
2082 {ARM_FEATURE_COPROC (FPU_MVE),
2083 MVE_VPT_VEC_T1,
2084 0xfe010f00, 0xff811f51,
2085 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2086 /* Vector VPT T2. */
2087 {ARM_FEATURE_COPROC (FPU_MVE),
2088 MVE_VPT_VEC_T2,
2089 0xfe010f01, 0xff811f51,
2090 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2091 /* Vector VPT T3. */
2092 {ARM_FEATURE_COPROC (FPU_MVE),
2093 MVE_VPT_VEC_T3,
2094 0xfe011f00, 0xff811f50,
2095 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2096 /* Vector VPT T4. */
2097 {ARM_FEATURE_COPROC (FPU_MVE),
2098 MVE_VPT_VEC_T4,
2099 0xfe010f40, 0xff811f70,
2100 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2101 /* Vector VPT T5. */
2102 {ARM_FEATURE_COPROC (FPU_MVE),
2103 MVE_VPT_VEC_T5,
2104 0xfe010f60, 0xff811f70,
2105 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2106 /* Vector VPT T6. */
2107 {ARM_FEATURE_COPROC (FPU_MVE),
2108 MVE_VPT_VEC_T6,
2109 0xfe011f40, 0xff811f50,
2110 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2111
c507f10b
AV		 2112 /* Vector VBIC immediate. */
2113 {ARM_FEATURE_COPROC (FPU_MVE),
2114 MVE_VBIC_IMM,
2115 0xef800070, 0xefb81070,
2116 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2117
2118 /* Vector VBIC register. */
2119 {ARM_FEATURE_COPROC (FPU_MVE),
2120 MVE_VBIC_REG,
2121 0xef100150, 0xffb11f51,
2122 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2123
66dcaa5d
AV		 2124 /* Vector VABAV. */
2125 {ARM_FEATURE_COPROC (FPU_MVE),
2126 MVE_VABAV,
2127 0xee800f01, 0xefc10f51,
2128 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2129
2130 /* Vector VABD floating point. */
2131 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2132 MVE_VABD_FP,
2133 0xff200d40, 0xffa11f51,
2134 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2135
2136 /* Vector VABD. */
2137 {ARM_FEATURE_COPROC (FPU_MVE),
2138 MVE_VABD_VEC,
2139 0xef000740, 0xef811f51,
2140 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2141
2142 /* Vector VABS floating point. */
2143 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2144 MVE_VABS_FP,
2145 0xFFB10740, 0xFFB31FD1,
2146 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2147 /* Vector VABS. */
2148 {ARM_FEATURE_COPROC (FPU_MVE),
2149 MVE_VABS_VEC,
2150 0xffb10340, 0xffb31fd1,
2151 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2152
2153 /* Vector VADD floating point T1. */
2154 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2155 MVE_VADD_FP_T1,
2156 0xef000d40, 0xffa11f51,
2157 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2158 /* Vector VADD floating point T2. */
2159 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2160 MVE_VADD_FP_T2,
2161 0xee300f40, 0xefb11f70,
2162 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2163 /* Vector VADD T1. */
2164 {ARM_FEATURE_COPROC (FPU_MVE),
2165 MVE_VADD_VEC_T1,
2166 0xef000840, 0xff811f51,
2167 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2168 /* Vector VADD T2. */
2169 {ARM_FEATURE_COPROC (FPU_MVE),
2170 MVE_VADD_VEC_T2,
2171 0xee010f40, 0xff811f70,
2172 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2173
d3b63143
AV		 2174 /* Vector VADDLV. */
2175 {ARM_FEATURE_COPROC (FPU_MVE),
2176 MVE_VADDLV,
2177 0xee890f00, 0xef8f1fd1,
2178 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2179
2180 /* Vector VADDV. */
2181 {ARM_FEATURE_COPROC (FPU_MVE),
2182 MVE_VADDV,
2183 0xeef10f00, 0xeff31fd1,
2184 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2185
66dcaa5d
AV		 2186 /* Vector VADC. */
2187 {ARM_FEATURE_COPROC (FPU_MVE),
2188 MVE_VADC,
2189 0xee300f00, 0xffb10f51,
2190 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2191
e523f101
AV		 2192 /* Vector VAND. */
2193 {ARM_FEATURE_COPROC (FPU_MVE),
2194 MVE_VAND,
2195 0xef000150, 0xffb11f51,
2196 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2197
2198 /* Vector VBRSR register. */
2199 {ARM_FEATURE_COPROC (FPU_MVE),
2200 MVE_VBRSR,
2201 0xfe011e60, 0xff811f70,
2202 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2203
897b9bbc
AV		 2204 /* Vector VCADD floating point. */
2205 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2206 MVE_VCADD_FP,
2207 0xfc800840, 0xfea11f51,
2208 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2209
2210 /* Vector VCADD. */
2211 {ARM_FEATURE_COPROC (FPU_MVE),
2212 MVE_VCADD_VEC,
2213 0xfe000f00, 0xff810f51,
2214 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2215
e523f101
AV		 2216 /* Vector VCLS. */
2217 {ARM_FEATURE_COPROC (FPU_MVE),
2218 MVE_VCLS,
2219 0xffb00440, 0xffb31fd1,
2220 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2221
2222 /* Vector VCLZ. */
2223 {ARM_FEATURE_COPROC (FPU_MVE),
2224 MVE_VCLZ,
2225 0xffb004c0, 0xffb31fd1,
2226 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2227
897b9bbc
AV		 2228 /* Vector VCMLA. */
2229 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2230 MVE_VCMLA_FP,
2231 0xfc200840, 0xfe211f51,
2232 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2233
143275ea
AV		 2234 /* Vector VCMP floating point T1. */
2235 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2236 MVE_VCMP_FP_T1,
2237 0xee310f00, 0xeff1ef50,
2238 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2239
2240 /* Vector VCMP floating point T2. */
2241 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2242 MVE_VCMP_FP_T2,
2243 0xee310f40, 0xeff1ef50,
2244 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2245
2246 /* Vector VCMP T1. */
2247 {ARM_FEATURE_COPROC (FPU_MVE),
2248 MVE_VCMP_VEC_T1,
2249 0xfe010f00, 0xffc1ff51,
2250 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2251 /* Vector VCMP T2. */
2252 {ARM_FEATURE_COPROC (FPU_MVE),
2253 MVE_VCMP_VEC_T2,
2254 0xfe010f01, 0xffc1ff51,
2255 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2256 /* Vector VCMP T3. */
2257 {ARM_FEATURE_COPROC (FPU_MVE),
2258 MVE_VCMP_VEC_T3,
2259 0xfe011f00, 0xffc1ff50,
2260 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2261 /* Vector VCMP T4. */
2262 {ARM_FEATURE_COPROC (FPU_MVE),
2263 MVE_VCMP_VEC_T4,
2264 0xfe010f40, 0xffc1ff70,
2265 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2266 /* Vector VCMP T5. */
2267 {ARM_FEATURE_COPROC (FPU_MVE),
2268 MVE_VCMP_VEC_T5,
2269 0xfe010f60, 0xffc1ff70,
2270 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2271 /* Vector VCMP T6. */
2272 {ARM_FEATURE_COPROC (FPU_MVE),
2273 MVE_VCMP_VEC_T6,
2274 0xfe011f40, 0xffc1ff50,
2275 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2276
9743db03
AV		 2277 /* Vector VDUP. */
2278 {ARM_FEATURE_COPROC (FPU_MVE),
2279 MVE_VDUP,
2280 0xeea00b10, 0xffb10f5f,
2281 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2282
2283 /* Vector VEOR. */
2284 {ARM_FEATURE_COPROC (FPU_MVE),
2285 MVE_VEOR,
2286 0xff000150, 0xffd11f51,
2287 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2288
2289 /* Vector VFMA, vector * scalar. */
2290 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2291 MVE_VFMA_FP_SCALAR,
2292 0xee310e40, 0xefb11f70,
2293 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2294
2295 /* Vector VFMA floating point. */
2296 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2297 MVE_VFMA_FP,
2298 0xef000c50, 0xffa11f51,
2299 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2300
2301 /* Vector VFMS floating point. */
2302 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2303 MVE_VFMS_FP,
2304 0xef200c50, 0xffa11f51,
2305 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2306
2307 /* Vector VFMAS, vector * scalar. */
2308 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2309 MVE_VFMAS_FP_SCALAR,
2310 0xee311e40, 0xefb11f70,
2311 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2312
2313 /* Vector VHADD T1. */
2314 {ARM_FEATURE_COPROC (FPU_MVE),
2315 MVE_VHADD_T1,
2316 0xef000040, 0xef811f51,
2317 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2318
2319 /* Vector VHADD T2. */
2320 {ARM_FEATURE_COPROC (FPU_MVE),
2321 MVE_VHADD_T2,
2322 0xee000f40, 0xef811f70,
2323 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2324
2325 /* Vector VHSUB T1. */
2326 {ARM_FEATURE_COPROC (FPU_MVE),
2327 MVE_VHSUB_T1,
2328 0xef000240, 0xef811f51,
2329 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2330
2331 /* Vector VHSUB T2. */
2332 {ARM_FEATURE_COPROC (FPU_MVE),
2333 MVE_VHSUB_T2,
2334 0xee001f40, 0xef811f70,
2335 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2336
897b9bbc
AV		 2337 /* Vector VCMUL. */
2338 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2339 MVE_VCMUL_FP,
2340 0xee300e00, 0xefb10f50,
2341 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2342
e523f101
AV		 2343 /* Vector VCTP. */
2344 {ARM_FEATURE_COPROC (FPU_MVE),
2345 MVE_VCTP,
2346 0xf000e801, 0xffc0ffff,
2347 "vctp%v.%20-21s\t%16-19r"},
2348
9743db03
AV		 2349 /* Vector VDUP. */
2350 {ARM_FEATURE_COPROC (FPU_MVE),
2351 MVE_VDUP,
2352 0xeea00b10, 0xffb10f5f,
2353 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2354
2355 /* Vector VRHADD. */
2356 {ARM_FEATURE_COPROC (FPU_MVE),
2357 MVE_VRHADD,
2358 0xef000140, 0xef811f51,
2359 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2360
bf0b396d
AV		 2361 /* Vector VCVT. */
2362 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2363 MVE_VCVT_FP_FIX_VEC,
2364 0xef800c50, 0xef801cd1,
2365 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2366
2367 /* Vector VCVT. */
2368 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2369 MVE_VCVT_BETWEEN_FP_INT,
2370 0xffb30640, 0xffb31e51,
2371 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2372
2373 /* Vector VCVT between single and half-precision float, bottom half. */
2374 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2375 MVE_VCVT_FP_HALF_FP,
2376 0xee3f0e01, 0xefbf1fd1,
2377 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2378
2379 /* Vector VCVT between single and half-precision float, top half. */
2380 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2381 MVE_VCVT_FP_HALF_FP,
2382 0xee3f1e01, 0xefbf1fd1,
2383 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2384
2385 /* Vector VCVT. */
2386 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2387 MVE_VCVT_FROM_FP_TO_INT,
2388 0xffb30040, 0xffb31c51,
2389 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2390
1c8f2df8
AV		 2391 /* Vector VDDUP. */
2392 {ARM_FEATURE_COPROC (FPU_MVE),
2393 MVE_VDDUP,
2394 0xee011f6e, 0xff811f7e,
2395 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2396
2397 /* Vector VDWDUP. */
2398 {ARM_FEATURE_COPROC (FPU_MVE),
2399 MVE_VDWDUP,
2400 0xee011f60, 0xff811f70,
2401 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2402
897b9bbc
AV		 2403 /* Vector VHCADD. */
2404 {ARM_FEATURE_COPROC (FPU_MVE),
2405 MVE_VHCADD,
2406 0xee000f00, 0xff810f51,
2407 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2408
1c8f2df8
AV		 2409 /* Vector VIWDUP. */
2410 {ARM_FEATURE_COPROC (FPU_MVE),
2411 MVE_VIWDUP,
2412 0xee010f60, 0xff811f70,
2413 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2414
2415 /* Vector VIDUP. */
2416 {ARM_FEATURE_COPROC (FPU_MVE),
2417 MVE_VIDUP,
2418 0xee010f6e, 0xff811f7e,
2419 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2420
04d54ace
AV		 2421 /* Vector VLD2. */
2422 {ARM_FEATURE_COPROC (FPU_MVE),
2423 MVE_VLD2,
2424 0xfc901e00, 0xff901e5f,
2425 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2426
2427 /* Vector VLD4. */
2428 {ARM_FEATURE_COPROC (FPU_MVE),
2429 MVE_VLD4,
2430 0xfc901e01, 0xff901e1f,
2431 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2432
ef1576a1
AV		 2433 /* Vector VLDRB gather load. */
2434 {ARM_FEATURE_COPROC (FPU_MVE),
2435 MVE_VLDRB_GATHER_T1,
2436 0xec900e00, 0xefb01e50,
2437 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2438
2439 /* Vector VLDRH gather load. */
2440 {ARM_FEATURE_COPROC (FPU_MVE),
2441 MVE_VLDRH_GATHER_T2,
2442 0xec900e10, 0xefb01e50,
2443 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2444
2445 /* Vector VLDRW gather load. */
2446 {ARM_FEATURE_COPROC (FPU_MVE),
2447 MVE_VLDRW_GATHER_T3,
2448 0xfc900f40, 0xffb01fd0,
2449 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2450
2451 /* Vector VLDRD gather load. */
2452 {ARM_FEATURE_COPROC (FPU_MVE),
2453 MVE_VLDRD_GATHER_T4,
2454 0xec900fd0, 0xefb01fd0,
2455 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2456
2457 /* Vector VLDRW gather load. */
2458 {ARM_FEATURE_COPROC (FPU_MVE),
2459 MVE_VLDRW_GATHER_T5,
2460 0xfd101e00, 0xff111f00,
2461 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2462
2463 /* Vector VLDRD gather load, variant T6. */
2464 {ARM_FEATURE_COPROC (FPU_MVE),
2465 MVE_VLDRD_GATHER_T6,
2466 0xfd101f00, 0xff111f00,
2467 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2468
aef6d006
AV		 2469 /* Vector VLDRB. */
2470 {ARM_FEATURE_COPROC (FPU_MVE),
2471 MVE_VLDRB_T1,
2472 0xec100e00, 0xee581e00,
2473 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2474
2475 /* Vector VLDRH. */
2476 {ARM_FEATURE_COPROC (FPU_MVE),
2477 MVE_VLDRH_T2,
2478 0xec180e00, 0xee581e00,
2479 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2480
2481 /* Vector VLDRB unsigned, variant T5. */
2482 {ARM_FEATURE_COPROC (FPU_MVE),
2483 MVE_VLDRB_T5,
2484 0xec101e00, 0xfe101f80,
2485 "vldrb%v.u8\t%13-15,22Q, %d"},
2486
2487 /* Vector VLDRH unsigned, variant T6. */
2488 {ARM_FEATURE_COPROC (FPU_MVE),
2489 MVE_VLDRH_T6,
2490 0xec101e80, 0xfe101f80,
2491 "vldrh%v.u16\t%13-15,22Q, %d"},
2492
2493 /* Vector VLDRW unsigned, variant T7. */
2494 {ARM_FEATURE_COPROC (FPU_MVE),
2495 MVE_VLDRW_T7,
2496 0xec101f00, 0xfe101f80,
2497 "vldrw%v.u32\t%13-15,22Q, %d"},
2498
56858bea
AV		 2499 /* Vector VMAX. */
2500 {ARM_FEATURE_COPROC (FPU_MVE),
2501 MVE_VMAX,
2502 0xef000640, 0xef811f51,
2503 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2504
2505 /* Vector VMAXA. */
2506 {ARM_FEATURE_COPROC (FPU_MVE),
2507 MVE_VMAXA,
2508 0xee330e81, 0xffb31fd1,
2509 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2510
2511 /* Vector VMAXNM floating point. */
2512 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2513 MVE_VMAXNM_FP,
2514 0xff000f50, 0xffa11f51,
2515 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2516
2517 /* Vector VMAXNMA floating point. */
2518 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2519 MVE_VMAXNMA_FP,
2520 0xee3f0e81, 0xefbf1fd1,
2521 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2522
2523 /* Vector VMAXNMV floating point. */
2524 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2525 MVE_VMAXNMV_FP,
2526 0xeeee0f00, 0xefff0fd1,
2527 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2528
2529 /* Vector VMAXNMAV floating point. */
2530 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2531 MVE_VMAXNMAV_FP,
2532 0xeeec0f00, 0xefff0fd1,
2533 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2534
2535 /* Vector VMAXV. */
2536 {ARM_FEATURE_COPROC (FPU_MVE),
2537 MVE_VMAXV,
2538 0xeee20f00, 0xeff30fd1,
2539 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2540
2541 /* Vector VMAXAV. */
2542 {ARM_FEATURE_COPROC (FPU_MVE),
2543 MVE_VMAXAV,
2544 0xeee00f00, 0xfff30fd1,
2545 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2546
2547 /* Vector VMIN. */
2548 {ARM_FEATURE_COPROC (FPU_MVE),
2549 MVE_VMIN,
2550 0xef000650, 0xef811f51,
2551 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2552
2553 /* Vector VMINA. */
2554 {ARM_FEATURE_COPROC (FPU_MVE),
2555 MVE_VMINA,
2556 0xee331e81, 0xffb31fd1,
2557 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2558
2559 /* Vector VMINNM floating point. */
2560 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2561 MVE_VMINNM_FP,
2562 0xff200f50, 0xffa11f51,
2563 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2564
2565 /* Vector VMINNMA floating point. */
2566 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2567 MVE_VMINNMA_FP,
2568 0xee3f1e81, 0xefbf1fd1,
2569 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2570
2571 /* Vector VMINNMV floating point. */
2572 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2573 MVE_VMINNMV_FP,
2574 0xeeee0f80, 0xefff0fd1,
2575 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2576
2577 /* Vector VMINNMAV floating point. */
2578 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2579 MVE_VMINNMAV_FP,
2580 0xeeec0f80, 0xefff0fd1,
2581 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2582
2583 /* Vector VMINV. */
2584 {ARM_FEATURE_COPROC (FPU_MVE),
2585 MVE_VMINV,
2586 0xeee20f80, 0xeff30fd1,
2587 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2588
2589 /* Vector VMINAV. */
2590 {ARM_FEATURE_COPROC (FPU_MVE),
2591 MVE_VMINAV,
2592 0xeee00f80, 0xfff30fd1,
2593 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2594
2595 /* Vector VMLA. */
2596 {ARM_FEATURE_COPROC (FPU_MVE),
2597 MVE_VMLA,
2598 0xee010e40, 0xef811f70,
2599 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2600
d3b63143
AV		 2601 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2602 opcode aliasing. */
2603 {ARM_FEATURE_COPROC (FPU_MVE),
2604 MVE_VMLALDAV,
2605 0xee801e00, 0xef801f51,
2606 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2607
2608 {ARM_FEATURE_COPROC (FPU_MVE),
2609 MVE_VMLALDAV,
2610 0xee800e00, 0xef801f51,
2611 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2612
2613 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2614 {ARM_FEATURE_COPROC (FPU_MVE),
2615 MVE_VMLADAV_T1,
2616 0xeef00e00, 0xeff01f51,
2617 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2618
2619 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2620 {ARM_FEATURE_COPROC (FPU_MVE),
2621 MVE_VMLADAV_T2,
2622 0xeef00f00, 0xeff11f51,
2623 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2624
2625 /* Vector VMLADAV T1 variant. */
2626 {ARM_FEATURE_COPROC (FPU_MVE),
2627 MVE_VMLADAV_T1,
2628 0xeef01e00, 0xeff01f51,
2629 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2630
2631 /* Vector VMLADAV T2 variant. */
2632 {ARM_FEATURE_COPROC (FPU_MVE),
2633 MVE_VMLADAV_T2,
2634 0xeef01f00, 0xeff11f51,
2635 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2636
2637 /* Vector VMLAS. */
2638 {ARM_FEATURE_COPROC (FPU_MVE),
2639 MVE_VMLAS,
2640 0xee011e40, 0xef811f70,
2641 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2642
2643 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2644 opcode aliasing. */
2645 {ARM_FEATURE_COPROC (FPU_MVE),
2646 MVE_VRMLSLDAVH,
2647 0xfe800e01, 0xff810f51,
2648 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2649
2650 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2651 opcdoe aliasing. */
2652 {ARM_FEATURE_COPROC (FPU_MVE),
2653 MVE_VMLSLDAV,
2654 0xee800e01, 0xff800f51,
2655 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2656
2657 /* Vector VMLSDAV T1 Variant. */
2658 {ARM_FEATURE_COPROC (FPU_MVE),
2659 MVE_VMLSDAV_T1,
2660 0xeef00e01, 0xfff00f51,
2661 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2662
2663 /* Vector VMLSDAV T2 Variant. */
2664 {ARM_FEATURE_COPROC (FPU_MVE),
2665 MVE_VMLSDAV_T2,
2666 0xfef00e01, 0xfff10f51,
2667 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2668
c507f10b
AV		 2669 /* Vector VMOV between gpr and half precision register, op == 0. */
2670 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2671 MVE_VMOV_HFP_TO_GP,
2672 0xee000910, 0xfff00f7f,
2673 "vmov.f16\t%7,16-19F, %12-15r"},
2674
2675 /* Vector VMOV between gpr and half precision register, op == 1. */
2676 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2677 MVE_VMOV_HFP_TO_GP,
2678 0xee100910, 0xfff00f7f,
2679 "vmov.f16\t%12-15r, %7,16-19F"},
2680
2681 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2682 MVE_VMOV_GP_TO_VEC_LANE,
2683 0xee000b10, 0xff900f1f,
2684 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2685
2686 /* Vector VORR immediate to vector.
2687 NOTE: MVE_VORR_IMM must appear in the table
2688 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2689 {ARM_FEATURE_COPROC (FPU_MVE),
2690 MVE_VORR_IMM,
2691 0xef800050, 0xefb810f0,
2692 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2693
ed63aa17
AV		 2694 /* Vector VQSHL T2 Variant.
2695 NOTE: MVE_VQSHL_T2 must appear in the table before
2696 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2697 {ARM_FEATURE_COPROC (FPU_MVE),
2698 MVE_VQSHL_T2,
2699 0xef800750, 0xef801fd1,
2700 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2701
2702 /* Vector VQSHLU T3 Variant
2703 NOTE: MVE_VQSHL_T2 must appear in the table before
2704 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2705
2706 {ARM_FEATURE_COPROC (FPU_MVE),
2707 MVE_VQSHLU_T3,
2708 0xff800650, 0xff801fd1,
2709 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2710
2711 /* Vector VRSHR
2712 NOTE: MVE_VRSHR must appear in the table before
2713 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2714 {ARM_FEATURE_COPROC (FPU_MVE),
2715 MVE_VRSHR,
2716 0xef800250, 0xef801fd1,
2717 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2718
2719 /* Vector VSHL.
2720 NOTE: MVE_VSHL must appear in the table before
2721 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2722 {ARM_FEATURE_COPROC (FPU_MVE),
2723 MVE_VSHL_T1,
2724 0xef800550, 0xff801fd1,
2725 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2726
2727 /* Vector VSHR
2728 NOTE: MVE_VSHR must appear in the table before
2729 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2730 {ARM_FEATURE_COPROC (FPU_MVE),
2731 MVE_VSHR,
2732 0xef800050, 0xef801fd1,
2733 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2734
2735 /* Vector VSLI
2736 NOTE: MVE_VSLI must appear in the table before
2737 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2738 {ARM_FEATURE_COPROC (FPU_MVE),
2739 MVE_VSLI,
2740 0xff800550, 0xff801fd1,
2741 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2742
2743 /* Vector VSRI
2744 NOTE: MVE_VSRI must appear in the table before
2745 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2746 {ARM_FEATURE_COPROC (FPU_MVE),
2747 MVE_VSRI,
2748 0xff800450, 0xff801fd1,
2749 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2750
c507f10b
AV		 2751 /* Vector VMOV immediate to vector,
2752 cmode == 11x1 -> VMVN which is UNDEFINED
2753 for such a cmode. */
2754 {ARM_FEATURE_COPROC (FPU_MVE),
2755 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2756
2757 /* Vector VMOV immediate to vector. */
2758 {ARM_FEATURE_COPROC (FPU_MVE),
2759 MVE_VMOV_IMM_TO_VEC,
2760 0xef800050, 0xefb810d0,
2761 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2762
2763 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2764 {ARM_FEATURE_COPROC (FPU_MVE),
2765 MVE_VMOV2_VEC_LANE_TO_GP,
2766 0xec000f00, 0xffb01ff0,
2767 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2768
2769 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2770 {ARM_FEATURE_COPROC (FPU_MVE),
2771 MVE_VMOV2_VEC_LANE_TO_GP,
2772 0xec000f10, 0xffb01ff0,
2773 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2774
2775 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2776 {ARM_FEATURE_COPROC (FPU_MVE),
2777 MVE_VMOV2_GP_TO_VEC_LANE,
2778 0xec100f00, 0xffb01ff0,
2779 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2780
2781 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2782 {ARM_FEATURE_COPROC (FPU_MVE),
2783 MVE_VMOV2_GP_TO_VEC_LANE,
2784 0xec100f10, 0xffb01ff0,
2785 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2786
2787 /* Vector VMOV Vector lane to gpr. */
2788 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2789 MVE_VMOV_VEC_LANE_TO_GP,
2790 0xee100b10, 0xff100f1f,
2791 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2792
ed63aa17
AV		 2793 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2794 to instruction opcode aliasing. */
2795 {ARM_FEATURE_COPROC (FPU_MVE),
2796 MVE_VSHLL_T1,
2797 0xeea00f40, 0xefa00fd1,
2798 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2799
14925797
AV		 2800 /* Vector VMOVL long. */
2801 {ARM_FEATURE_COPROC (FPU_MVE),
2802 MVE_VMOVL,
2803 0xeea00f40, 0xefa70fd1,
2804 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2805
2806 /* Vector VMOV and narrow. */
2807 {ARM_FEATURE_COPROC (FPU_MVE),
2808 MVE_VMOVN,
2809 0xfe310e81, 0xffb30fd1,
2810 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2811
c507f10b
AV		 2812 /* Floating point move extract. */
2813 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2814 MVE_VMOVX,
2815 0xfeb00a40, 0xffbf0fd0,
2816 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2817
f49bb598
AV		 2818 /* Vector VMUL floating-point T1 variant. */
2819 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2820 MVE_VMUL_FP_T1,
2821 0xff000d50, 0xffa11f51,
2822 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2823
2824 /* Vector VMUL floating-point T2 variant. */
2825 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2826 MVE_VMUL_FP_T2,
2827 0xee310e60, 0xefb11f70,
2828 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2829
2830 /* Vector VMUL T1 variant. */
2831 {ARM_FEATURE_COPROC (FPU_MVE),
2832 MVE_VMUL_VEC_T1,
2833 0xef000950, 0xff811f51,
2834 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2835
2836 /* Vector VMUL T2 variant. */
2837 {ARM_FEATURE_COPROC (FPU_MVE),
2838 MVE_VMUL_VEC_T2,
2839 0xee011e60, 0xff811f70,
2840 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2841
2842 /* Vector VMULH. */
2843 {ARM_FEATURE_COPROC (FPU_MVE),
2844 MVE_VMULH,
2845 0xee010e01, 0xef811f51,
2846 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2847
2848 /* Vector VRMULH. */
2849 {ARM_FEATURE_COPROC (FPU_MVE),
2850 MVE_VRMULH,
2851 0xee011e01, 0xef811f51,
2852 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2853
14925797
AV		 2854 /* Vector VMULL integer. */
2855 {ARM_FEATURE_COPROC (FPU_MVE),
2856 MVE_VMULL_INT,
2857 0xee010e00, 0xef810f51,
2858 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2859
2860 /* Vector VMULL polynomial. */
2861 {ARM_FEATURE_COPROC (FPU_MVE),
2862 MVE_VMULL_POLY,
2863 0xee310e00, 0xefb10f51,
2864 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2865
c507f10b
AV		 2866 /* Vector VMVN immediate to vector. */
2867 {ARM_FEATURE_COPROC (FPU_MVE),
2868 MVE_VMVN_IMM,
2869 0xef800070, 0xefb810f0,
2870 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2871
2872 /* Vector VMVN register. */
2873 {ARM_FEATURE_COPROC (FPU_MVE),
2874 MVE_VMVN_REG,
2875 0xffb005c0, 0xffbf1fd1,
2876 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2877
f49bb598
AV		 2878 /* Vector VNEG floating point. */
2879 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2880 MVE_VNEG_FP,
2881 0xffb107c0, 0xffb31fd1,
2882 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2883
2884 /* Vector VNEG. */
2885 {ARM_FEATURE_COPROC (FPU_MVE),
2886 MVE_VNEG_VEC,
2887 0xffb103c0, 0xffb31fd1,
2888 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2889
c507f10b
AV		 2890 /* Vector VORN, vector bitwise or not. */
2891 {ARM_FEATURE_COPROC (FPU_MVE),
2892 MVE_VORN,
2893 0xef300150, 0xffb11f51,
2894 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2895
2896 /* Vector VORR register. */
2897 {ARM_FEATURE_COPROC (FPU_MVE),
2898 MVE_VORR_REG,
2899 0xef200150, 0xffb11f51,
2900 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2901
14925797
AV		 2902 /* Vector VQDMULL T1 variant. */
2903 {ARM_FEATURE_COPROC (FPU_MVE),
2904 MVE_VQDMULL_T1,
2905 0xee300f01, 0xefb10f51,
2906 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2907
14b456f2
AV		 2908 /* Vector VPNOT. */
2909 {ARM_FEATURE_COPROC (FPU_MVE),
2910 MVE_VPNOT,
2911 0xfe310f4d, 0xffffffff,
2912 "vpnot%v"},
2913
2914 /* Vector VPSEL. */
2915 {ARM_FEATURE_COPROC (FPU_MVE),
2916 MVE_VPSEL,
2917 0xfe310f01, 0xffb11f51,
2918 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2919
2920 /* Vector VQABS. */
2921 {ARM_FEATURE_COPROC (FPU_MVE),
2922 MVE_VQABS,
2923 0xffb00740, 0xffb31fd1,
2924 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2925
2926 /* Vector VQADD T1 variant. */
2927 {ARM_FEATURE_COPROC (FPU_MVE),
2928 MVE_VQADD_T1,
2929 0xef000050, 0xef811f51,
2930 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2931
2932 /* Vector VQADD T2 variant. */
2933 {ARM_FEATURE_COPROC (FPU_MVE),
2934 MVE_VQADD_T2,
2935 0xee000f60, 0xef811f70,
2936 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2937
14925797
AV		 2938 /* Vector VQDMULL T2 variant. */
2939 {ARM_FEATURE_COPROC (FPU_MVE),
2940 MVE_VQDMULL_T2,
2941 0xee300f60, 0xefb10f70,
2942 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2943
2944 /* Vector VQMOVN. */
2945 {ARM_FEATURE_COPROC (FPU_MVE),
2946 MVE_VQMOVN,
2947 0xee330e01, 0xefb30fd1,
2948 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2949
2950 /* Vector VQMOVUN. */
2951 {ARM_FEATURE_COPROC (FPU_MVE),
2952 MVE_VQMOVUN,
2953 0xee310e81, 0xffb30fd1,
2954 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2955
d3b63143
AV		 2956 /* Vector VQDMLADH. */
2957 {ARM_FEATURE_COPROC (FPU_MVE),
2958 MVE_VQDMLADH,
2959 0xee000e00, 0xff810f51,
2960 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2961
2962 /* Vector VQRDMLADH. */
2963 {ARM_FEATURE_COPROC (FPU_MVE),
2964 MVE_VQRDMLADH,
2965 0xee000e01, 0xff810f51,
2966 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2967
2968 /* Vector VQDMLAH. */
2969 {ARM_FEATURE_COPROC (FPU_MVE),
2970 MVE_VQDMLAH,
2971 0xee000e60, 0xef811f70,
2972 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2973
2974 /* Vector VQRDMLAH. */
2975 {ARM_FEATURE_COPROC (FPU_MVE),
2976 MVE_VQRDMLAH,
2977 0xee000e40, 0xef811f70,
2978 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2979
2980 /* Vector VQDMLASH. */
2981 {ARM_FEATURE_COPROC (FPU_MVE),
2982 MVE_VQDMLASH,
2983 0xee001e60, 0xef811f70,
2984 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2985
2986 /* Vector VQRDMLASH. */
2987 {ARM_FEATURE_COPROC (FPU_MVE),
2988 MVE_VQRDMLASH,
2989 0xee001e40, 0xef811f70,
2990 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2991
2992 /* Vector VQDMLSDH. */
2993 {ARM_FEATURE_COPROC (FPU_MVE),
2994 MVE_VQDMLSDH,
2995 0xfe000e00, 0xff810f51,
2996 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2997
2998 /* Vector VQRDMLSDH. */
2999 {ARM_FEATURE_COPROC (FPU_MVE),
3000 MVE_VQRDMLSDH,
3001 0xfe000e01, 0xff810f51,
3002 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3003
3004 /* Vector VQDMULH T1 variant. */
3005 {ARM_FEATURE_COPROC (FPU_MVE),
3006 MVE_VQDMULH_T1,
3007 0xef000b40, 0xff811f51,
3008 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3009
3010 /* Vector VQRDMULH T2 variant. */
3011 {ARM_FEATURE_COPROC (FPU_MVE),
3012 MVE_VQRDMULH_T2,
3013 0xff000b40, 0xff811f51,
3014 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3015
3016 /* Vector VQDMULH T3 variant. */
3017 {ARM_FEATURE_COPROC (FPU_MVE),
3018 MVE_VQDMULH_T3,
3019 0xee010e60, 0xff811f70,
3020 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3021
3022 /* Vector VQRDMULH T4 variant. */
3023 {ARM_FEATURE_COPROC (FPU_MVE),
3024 MVE_VQRDMULH_T4,
3025 0xfe010e60, 0xff811f70,
3026 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3027
14b456f2
AV		 3028 /* Vector VQNEG. */
3029 {ARM_FEATURE_COPROC (FPU_MVE),
3030 MVE_VQNEG,
3031 0xffb007c0, 0xffb31fd1,
3032 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3033
ed63aa17
AV		 3034 /* Vector VQRSHL T1 variant. */
3035 {ARM_FEATURE_COPROC (FPU_MVE),
3036 MVE_VQRSHL_T1,
3037 0xef000550, 0xef811f51,
3038 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3039
3040 /* Vector VQRSHL T2 variant. */
3041 {ARM_FEATURE_COPROC (FPU_MVE),
3042 MVE_VQRSHL_T2,
3043 0xee331ee0, 0xefb31ff0,
3044 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3045
3046 /* Vector VQRSHRN. */
3047 {ARM_FEATURE_COPROC (FPU_MVE),
3048 MVE_VQRSHRN,
3049 0xee800f41, 0xefa00fd1,
3050 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3051
3052 /* Vector VQRSHRUN. */
3053 {ARM_FEATURE_COPROC (FPU_MVE),
3054 MVE_VQRSHRUN,
3055 0xfe800fc0, 0xffa00fd1,
3056 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3057
3058 /* Vector VQSHL T1 Variant. */
3059 {ARM_FEATURE_COPROC (FPU_MVE),
3060 MVE_VQSHL_T1,
3061 0xee311ee0, 0xefb31ff0,
3062 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3063
3064 /* Vector VQSHL T4 Variant. */
3065 {ARM_FEATURE_COPROC (FPU_MVE),
3066 MVE_VQSHL_T4,
3067 0xef000450, 0xef811f51,
3068 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3069
3070 /* Vector VQSHRN. */
3071 {ARM_FEATURE_COPROC (FPU_MVE),
3072 MVE_VQSHRN,
3073 0xee800f40, 0xefa00fd1,
3074 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3075
3076 /* Vector VQSHRUN. */
3077 {ARM_FEATURE_COPROC (FPU_MVE),
3078 MVE_VQSHRUN,
3079 0xee800fc0, 0xffa00fd1,
3080 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3081
14b456f2
AV		 3082 /* Vector VQSUB T1 Variant. */
3083 {ARM_FEATURE_COPROC (FPU_MVE),
3084 MVE_VQSUB_T1,
3085 0xef000250, 0xef811f51,
3086 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3087
3088 /* Vector VQSUB T2 Variant. */
3089 {ARM_FEATURE_COPROC (FPU_MVE),
3090 MVE_VQSUB_T2,
3091 0xee001f60, 0xef811f70,
3092 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3093
3094 /* Vector VREV16. */
3095 {ARM_FEATURE_COPROC (FPU_MVE),
3096 MVE_VREV16,
3097 0xffb00140, 0xffb31fd1,
3098 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3099
3100 /* Vector VREV32. */
3101 {ARM_FEATURE_COPROC (FPU_MVE),
3102 MVE_VREV32,
3103 0xffb000c0, 0xffb31fd1,
3104 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3105
3106 /* Vector VREV64. */
3107 {ARM_FEATURE_COPROC (FPU_MVE),
3108 MVE_VREV64,
3109 0xffb00040, 0xffb31fd1,
3110 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3111
bf0b396d
AV		 3112 /* Vector VRINT floating point. */
3113 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3114 MVE_VRINT_FP,
3115 0xffb20440, 0xffb31c51,
3116 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3117
d3b63143
AV		 3118 /* Vector VRMLALDAVH. */
3119 {ARM_FEATURE_COPROC (FPU_MVE),
3120 MVE_VRMLALDAVH,
3121 0xee800f00, 0xef811f51,
3122 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3123
3124 /* Vector VRMLALDAVH. */
3125 {ARM_FEATURE_COPROC (FPU_MVE),
3126 MVE_VRMLALDAVH,
3127 0xee801f00, 0xef811f51,
3128 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3129
ed63aa17
AV		 3130 /* Vector VRSHL T1 Variant. */
3131 {ARM_FEATURE_COPROC (FPU_MVE),
3132 MVE_VRSHL_T1,
3133 0xef000540, 0xef811f51,
3134 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3135
3136 /* Vector VRSHL T2 Variant. */
3137 {ARM_FEATURE_COPROC (FPU_MVE),
3138 MVE_VRSHL_T2,
3139 0xee331e60, 0xefb31ff0,
3140 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3141
3142 /* Vector VRSHRN. */
3143 {ARM_FEATURE_COPROC (FPU_MVE),
3144 MVE_VRSHRN,
3145 0xfe800fc1, 0xffa00fd1,
3146 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3147
66dcaa5d
AV		 3148 /* Vector VSBC. */
3149 {ARM_FEATURE_COPROC (FPU_MVE),
3150 MVE_VSBC,
3151 0xfe300f00, 0xffb10f51,
3152 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3153
ed63aa17
AV		 3154 /* Vector VSHL T2 Variant. */
3155 {ARM_FEATURE_COPROC (FPU_MVE),
3156 MVE_VSHL_T2,
3157 0xee311e60, 0xefb31ff0,
3158 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3159
3160 /* Vector VSHL T3 Variant. */
3161 {ARM_FEATURE_COPROC (FPU_MVE),
3162 MVE_VSHL_T3,
3163 0xef000440, 0xef811f51,
3164 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3165
3166 /* Vector VSHLC. */
3167 {ARM_FEATURE_COPROC (FPU_MVE),
3168 MVE_VSHLC,
3169 0xeea00fc0, 0xffa01ff0,
3170 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3171
3172 /* Vector VSHLL T2 Variant. */
3173 {ARM_FEATURE_COPROC (FPU_MVE),
3174 MVE_VSHLL_T2,
3175 0xee310e01, 0xefb30fd1,
3176 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3177
3178 /* Vector VSHRN. */
3179 {ARM_FEATURE_COPROC (FPU_MVE),
3180 MVE_VSHRN,
3181 0xee800fc1, 0xffa00fd1,
3182 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3183
04d54ace
AV		 3184 /* Vector VST2 no writeback. */
3185 {ARM_FEATURE_COPROC (FPU_MVE),
3186 MVE_VST2,
3187 0xfc801e00, 0xffb01e5f,
3188 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3189
3190 /* Vector VST2 writeback. */
3191 {ARM_FEATURE_COPROC (FPU_MVE),
3192 MVE_VST2,
3193 0xfca01e00, 0xffb01e5f,
3194 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3195
3196 /* Vector VST4 no writeback. */
3197 {ARM_FEATURE_COPROC (FPU_MVE),
3198 MVE_VST4,
3199 0xfc801e01, 0xffb01e1f,
3200 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3201
3202 /* Vector VST4 writeback. */
3203 {ARM_FEATURE_COPROC (FPU_MVE),
3204 MVE_VST4,
3205 0xfca01e01, 0xffb01e1f,
3206 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3207
ef1576a1
AV		 3208 /* Vector VSTRB scatter store, T1 variant. */
3209 {ARM_FEATURE_COPROC (FPU_MVE),
3210 MVE_VSTRB_SCATTER_T1,
3211 0xec800e00, 0xffb01e50,
3212 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3213
3214 /* Vector VSTRH scatter store, T2 variant. */
3215 {ARM_FEATURE_COPROC (FPU_MVE),
3216 MVE_VSTRH_SCATTER_T2,
3217 0xec800e10, 0xffb01e50,
3218 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3219
3220 /* Vector VSTRW scatter store, T3 variant. */
3221 {ARM_FEATURE_COPROC (FPU_MVE),
3222 MVE_VSTRW_SCATTER_T3,
3223 0xec800e40, 0xffb01e50,
3224 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3225
3226 /* Vector VSTRD scatter store, T4 variant. */
3227 {ARM_FEATURE_COPROC (FPU_MVE),
3228 MVE_VSTRD_SCATTER_T4,
3229 0xec800fd0, 0xffb01fd0,
3230 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3231
3232 /* Vector VSTRW scatter store, T5 variant. */
3233 {ARM_FEATURE_COPROC (FPU_MVE),
3234 MVE_VSTRW_SCATTER_T5,
3235 0xfd001e00, 0xff111f00,
3236 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3237
3238 /* Vector VSTRD scatter store, T6 variant. */
3239 {ARM_FEATURE_COPROC (FPU_MVE),
3240 MVE_VSTRD_SCATTER_T6,
3241 0xfd001f00, 0xff111f00,
3242 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3243
aef6d006
AV		 3244 /* Vector VSTRB. */
3245 {ARM_FEATURE_COPROC (FPU_MVE),
3246 MVE_VSTRB_T1,
3247 0xec000e00, 0xfe581e00,
3248 "vstrb%v.%7-8s\t%13-15Q, %d"},
3249
3250 /* Vector VSTRH. */
3251 {ARM_FEATURE_COPROC (FPU_MVE),
3252 MVE_VSTRH_T2,
3253 0xec080e00, 0xfe581e00,
3254 "vstrh%v.%7-8s\t%13-15Q, %d"},
3255
3256 /* Vector VSTRB variant T5. */
3257 {ARM_FEATURE_COPROC (FPU_MVE),
3258 MVE_VSTRB_T5,
3259 0xec001e00, 0xfe101f80,
3260 "vstrb%v.8\t%13-15,22Q, %d"},
3261
3262 /* Vector VSTRH variant T6. */
3263 {ARM_FEATURE_COPROC (FPU_MVE),
3264 MVE_VSTRH_T6,
3265 0xec001e80, 0xfe101f80,
3266 "vstrh%v.16\t%13-15,22Q, %d"},
3267
3268 /* Vector VSTRW variant T7. */
3269 {ARM_FEATURE_COPROC (FPU_MVE),
3270 MVE_VSTRW_T7,
3271 0xec001f00, 0xfe101f80,
3272 "vstrw%v.32\t%13-15,22Q, %d"},
3273
66dcaa5d
AV		 3274 /* Vector VSUB floating point T1 variant. */
3275 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3276 MVE_VSUB_FP_T1,
3277 0xef200d40, 0xffa11f51,
3278 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3279
3280 /* Vector VSUB floating point T2 variant. */
3281 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3282 MVE_VSUB_FP_T2,
3283 0xee301f40, 0xefb11f70,
3284 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3285
3286 /* Vector VSUB T1 variant. */
3287 {ARM_FEATURE_COPROC (FPU_MVE),
3288 MVE_VSUB_VEC_T1,
3289 0xff000840, 0xff811f51,
3290 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3291
3292 /* Vector VSUB T2 variant. */
3293 {ARM_FEATURE_COPROC (FPU_MVE),
3294 MVE_VSUB_VEC_T2,
3295 0xee011f40, 0xff811f70,
3296 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3297
143275ea
AV		 3298 {ARM_FEATURE_CORE_LOW (0),
3299 MVE_NONE,
3300 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3301};
3302
8f06b2d8
PB		 3303/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3304 ordered: they must be searched linearly from the top to obtain a correct
3305 match. */
3306
3307/* print_insn_arm recognizes the following format control codes:
3308
3309 %% %
3310
3311 %a print address for ldr/str instruction
3312 %s print address for ldr/str halfword/signextend instruction
c1e26897 3313 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3314 %b print branch destination
3315 %c print condition code (always bits 28-31)
3316 %m print register mask for ldm/stm instruction
3317 %o print operand2 (immediate or register + shift)
3318 %p print 'p' iff bits 12-15 are 15
3319 %t print 't' iff bit 21 set and bit 24 clear
3320 %B print arm BLX(1) destination
3321 %C print the PSR sub type.
62b3e311
PB		 3322 %U print barrier type.
3323 %P print address for pli instruction.
8f06b2d8
PB		 3324
3325 %<bitfield>r print as an ARM register
9eb6c0f1 3326 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3327 %<bitfield>R as %r but r15 is UNPREDICTABLE
3328 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3329 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3330 %<bitfield>d print the bitfield in decimal
43e65147 3331 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3332 %<bitfield>x print the bitfield in hex
3333 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3334
16980d0b
JB		 3335 %<bitfield>'c print specified char iff bitfield is all ones
3336 %<bitfield>`c print specified char iff bitfield is all zeroes
3337 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3338
8f06b2d8
PB		 3339 %e print arm SMI operand (bits 0..7,8..19).
3340 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3341 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3342 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3343
8f06b2d8
PB		 3344static const struct opcode32 arm_opcodes[] =
3345{
3346 /* ARM instructions. */
823d2571
TG		 3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3348 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3350 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3351
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3353 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3355 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3357 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3359 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3361 0x00800090, 0x0fa000f0,
3362 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3364 0x00a00090, 0x0fa000f0,
3365 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3366
105bde57 3367 /* V8.2 RAS extension instructions. */
4d1464f2 3368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3369 0xe320f010, 0xffffffff, "esb"},
3370
53c4b28b 3371 /* V8 instructions. */
823d2571
TG		 3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3373 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3374 /* Defined in V8 but is in NOP space so available to all arch. */
3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3376 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3378 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3379 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3380 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3382 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3384 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3385 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3386 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3387 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3388 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3389 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3390 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3391 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3392 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3393 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3394 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3395 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3396 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3397 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3398 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3399 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3400 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3401 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3402 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3403 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3404 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3405 /* CRC32 instructions. */
823d2571
TG		 3406 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3407 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3408 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3409 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3410 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3411 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3412 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3413 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3414 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3415 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3416 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3417 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3418
ddfded2f
MW		 3419 /* Privileged Access Never extension instructions. */
3420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3421 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3422
90ec0d68 3423 /* Virtualization Extension instructions. */
823d2571
TG		 3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3426
eea54501 3427 /* Integer Divide Extension instructions. */
823d2571
TG		 3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3429 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3431 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3432
60e5ef9f 3433 /* MP Extension instructions. */
823d2571 3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3435
c597cc3d
SD		 3436 /* Speculation Barriers. */
3437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3440
62b3e311 3441 /* V7 instructions. */
823d2571
TG		 3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3450 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3451
c19d1205 3452 /* ARM V6T2 instructions. */
823d2571
TG		 3453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3454 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3456 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3458 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3460 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3461
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3463 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3465 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3466
ff8646ee 3467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3468 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3470 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3472 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3474 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3475
f4c65163 3476 /* ARM Security extension instructions. */
823d2571
TG		 3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3478 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3479
8f06b2d8 3480 /* ARM V6K instructions. */
823d2571
TG		 3481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3482 0xf57ff01f, 0xffffffff, "clrex"},
3483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3484 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3486 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3488 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3490 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3492 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3494 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3495
7fadb25d
SD		 3496 /* ARMv8.5-A instructions. */
3497 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3498
8f06b2d8 3499 /* ARM V6K NOP hints. */
823d2571
TG		 3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3501 0x0320f001, 0x0fffffff, "yield%c"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3503 0x0320f002, 0x0fffffff, "wfe%c"},
3504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3505 0x0320f003, 0x0fffffff, "wfi%c"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3507 0x0320f004, 0x0fffffff, "sev%c"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3509 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3510
fe56b6ce 3511 /* ARM V6 instructions. */
823d2571
TG		 3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3513 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3515 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3517 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3519 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3521 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3523 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3525 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3527 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3529 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3531 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3533 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3535 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3537 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3539 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3541 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3543 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3545 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3547 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3549 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3551 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3553 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3555 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3557 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3559 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3561 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3563 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3565 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3567 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3569 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3571 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3573 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3575 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3577 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3579 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3581 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3583 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3585 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3587 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3589 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3591 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3593 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3595 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3597 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3599 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3601 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3603 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3605 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3607 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3609 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3611 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3613 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3615 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3617 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3619 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3621 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3623 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3625 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3627 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3629 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3631 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3633 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3635 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3637 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3639 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3641 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3643 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3645 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3647 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3649 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3651 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3653 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3655 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3657 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3659 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3661 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3663 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3665 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3667 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3669 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3671 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3673 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3675 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3677 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3679 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3681 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3683 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3685 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3687 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3689 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3691 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3693 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3695 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3697 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3699 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3701 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3703 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3705 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3707 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3709 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3711 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3713 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3715 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3717 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3719 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3721 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3723 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3725 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3727 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3729 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3731 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3733 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3735 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3737 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3739 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3741 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3743 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3745 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3747 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3749 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3751 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3753 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3755 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3756
8f06b2d8 3757 /* V5J instruction. */
823d2571
TG		 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3759 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3760
8f06b2d8 3761 /* V5 Instructions. */
823d2571
TG		 3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3763 0xe1200070, 0xfff000f0,
3764 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3766 0xfa000000, 0xfe000000, "blx\t%B"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3768 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3770 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3771
3772 /* V5E "El Segundo" Instructions. */
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3774 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3776 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3778 0xf450f000, 0xfc70f000, "pld\t%a"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3780 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3782 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3784 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3786 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3787
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3789 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3791 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3792
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3794 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3796 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3798 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3800 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3801
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3803 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3805 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3807 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3809 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3810
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3812 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3814 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3815
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3817 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3819 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3821 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3823 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3824
8f06b2d8 3825 /* ARM Instructions. */
823d2571
TG		 3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3827 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3828
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3830 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3832 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3834 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3836 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3838 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3840 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3841
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3843 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3845 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3847 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3849 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3850
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3852 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3854 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3856 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3858 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3859
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3861 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3863 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3865 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3866
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3868 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3870 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3872 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3873
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3875 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3877 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3879 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3880
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3882 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3884 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3886 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3887
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3889 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3891 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3893 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3894
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3896 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3898 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3900 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3901
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3903 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3905 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3907 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3908
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3910 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3912 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3914 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3915
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3917 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3919 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3921 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3922
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3924 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3926 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3928 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3929
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3931 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3933 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3935 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 3936
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3938 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3940 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3942 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3943
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3945 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3947 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3949 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3950
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3952 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3954 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3956 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3957
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3959 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3961 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3963 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3965 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3967 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3969 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3971 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3972
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3974 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3976 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3978 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3979
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3981 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3983 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3985 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3986
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3988 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3990 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3991
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3993 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3994
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3996 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3998 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3999
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4001 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4005 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4007 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4009 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4011 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4013 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4015 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4017 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4019 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4021 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4023 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4025 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4027 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4029 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4031 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4033 0x092d0000, 0x0fff0000, "push%c\t%m"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4035 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4037 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4038
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4042 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4044 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4046 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4048 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4058 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4060 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4062 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4077
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4079 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4081 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4082
4083 /* The rest. */
4ab90a7a
AV		 4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4085 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4088 {ARM_FEATURE_CORE_LOW (0),
4089 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4090};
4091
4092/* print_insn_thumb16 recognizes the following format control codes:
4093
4094 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4095 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4096 %<bitfield>I print bitfield as a signed decimal
4097 (top bit of range being the sign bit)
4098 %N print Thumb register mask (with LR)
4099 %O print Thumb register mask (with PC)
4100 %M print Thumb register mask
4101 %b print CZB's 6-bit unsigned branch destination
4102 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4103 %c print the condition code
4104 %C print the condition code, or "s" if not conditional
4105 %x print warning if conditional an not at end of IT block"
4106 %X print "\t; unpredictable <IT:code>" if conditional
4107 %I print IT instruction suffix and operands
4547cb56 4108 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4109 %<bitfield>r print bitfield as an ARM register
4110 %<bitfield>d print bitfield as a decimal
4111 %<bitfield>H print (bitfield * 2) as a decimal
4112 %<bitfield>W print (bitfield * 4) as a decimal
4113 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4114 %<bitfield>B print Thumb branch destination (signed displacement)
4115 %<bitfield>c print bitfield as a condition code
4116 %<bitnum>'c print specified char iff bit is one
4117 %<bitnum>?ab print a if bit is one else print b. */
4118
4119static const struct opcode16 thumb_opcodes[] =
4120{
4121 /* Thumb instructions. */
4122
16a1fa25
TP		 4123 /* ARMv8-M Security Extensions instructions. */
4124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4125 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4126
53c4b28b 4127 /* ARM V8 instructions. */
823d2571
TG		 4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4130 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4131
8f06b2d8 4132 /* ARM V6K no-argument instructions. */
823d2571
TG		 4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4139
4140 /* ARM V6T2 instructions. */
ff8646ee
TP		 4141 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4142 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4143 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4144 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4146
4147 /* ARM V6. */
823d2571
TG		 4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4159
4160 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4162 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4163 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4165 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4166 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4168 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4169 /* Format 4. */
823d2571
TG		 4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4186 /* format 13 */
823d2571
TG		 4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4189 /* format 5 */
823d2571
TG		 4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4194 /* format 14 */
823d2571
TG		 4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4197 /* format 2 */
823d2571
TG		 4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4199 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4201 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4203 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4205 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4206 /* format 8 */
823d2571
TG		 4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4208 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4210 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4212 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4213 /* format 7 */
823d2571
TG		 4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4215 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4217 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4218 /* format 1 */
823d2571
TG		 4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4221 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4224 /* format 3 */
823d2571
TG		 4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4229 /* format 6 */
823d2571
TG		 4230 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4232 0x4800, 0xF800,
4233 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4234 /* format 9 */
823d2571
TG		 4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4236 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4238 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4240 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4242 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4243 /* format 10 */
823d2571
TG		 4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4245 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4247 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4248 /* format 11 */
823d2571
TG		 4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4250 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4252 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4253 /* format 12 */
823d2571
TG		 4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4255 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4257 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4258 /* format 15 */
823d2571
TG		 4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4261 /* format 17 */
823d2571 4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4263 /* format 16 */
823d2571
TG		 4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4267 /* format 18 */
823d2571 4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4269
4270 /* The E800 .. FFFF range is unconditionally redirected to the
4271 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4272 are processed via that table. Thus, we can never encounter a
4273 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4275 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4276};
4277
4278/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4279 We adopt the convention that hw1 is the high 16 bits of .value and
4280 .mask, hw2 the low 16 bits.
4281
4282 print_insn_thumb32 recognizes the following format control codes:
4283
4284 %% %
4285
4286 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4287 %M print a modified 12-bit immediate (same location)
4288 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4289 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4290 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4291 %S print a possibly-shifted Rm
4292
32a94698 4293 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4294 %a print the address of a plain load/store
4295 %w print the width and signedness of a core load/store
4296 %m print register mask for ldm/stm
4b5a202f 4297 %n print register mask for clrm
8f06b2d8
PB		 4298
4299 %E print the lsb and width fields of a bfc/bfi instruction
4300 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4301 %G print a fallback offset for Branch Future instructions
e5d6e09e 4302 %W print an offset for BF instruction
1caf72a5 4303 %Y print an offset for BFL instruction
1889da70 4304 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4305 %Q print an offset for Low Overhead Loop instructions
4306 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4307 %b print a conditional branch offset
4308 %B print an unconditional branch offset
4309 %s print the shift field of an SSAT instruction
4310 %R print the rotation field of an SXT instruction
62b3e311
PB		 4311 %U print barrier type.
4312 %P print address for pli instruction.
c22aaad1
PB		 4313 %c print the condition code
4314 %x print warning if conditional an not at end of IT block"
4315 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4316
4317 %<bitfield>d print bitfield in decimal
f0fba320 4318 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4319 %<bitfield>W print bitfield*4 in decimal
4320 %<bitfield>r print bitfield as an ARM register
dd5181d5 4321 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4322 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4323 %<bitfield>c print bitfield as a condition code
4324
16980d0b
JB		 4325 %<bitfield>'c print specified char iff bitfield is all ones
4326 %<bitfield>`c print specified char iff bitfield is all zeroes
4327 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4328
4329 With one exception at the bottom (done because BL and BLX(1) need
4330 to come dead last), this table was machine-sorted first in
4331 decreasing order of number of bits set in the mask, then in
4332 increasing numeric order of mask, then in increasing numeric order
4333 of opcode. This order is not the clearest for a human reader, but
4334 is guaranteed never to catch a special-case bit pattern with a more
4335 general mask, which is important, because this instruction encoding
4336 makes heavy use of special-case bit patterns. */
4337static const struct opcode32 thumb32_opcodes[] =
4338{
4b5a202f
AV		 4339 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4340 instructions. */
60f993ce 4341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4342 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4344 0xf02fc001, 0xfffff001, "le\t%P"},
4345 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4346 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4348 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4350 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4352 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4354 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4356 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4357
4389b29a
AV		 4358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4359 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4361 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4363 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4364 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4365 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4367 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4368
4b5a202f
AV		 4369 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4370 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4371
16a1fa25
TP		 4372 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4375 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4377 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4379 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4380 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4381 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4382
105bde57 4383 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4385 0xf3af8010, 0xffffffff, "esb"},
4386
53c4b28b 4387 /* V8 instructions. */
823d2571
TG		 4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4389 0xf3af8005, 0xffffffff, "sevl%c.w"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4391 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4393 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4395 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4397 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4399 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4401 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4403 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4405 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4407 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4409 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4411 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4413 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4415 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4417 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4419 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4420
dd5181d5 4421 /* CRC32 instructions. */
823d2571 4422 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4423 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 4424 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4425 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 4426 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4427 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 4428 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4429 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 4430 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4431 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 4432 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4433 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4434
c597cc3d
SD		 4435 /* Speculation Barriers. */
4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4439
62b3e311 4440 /* V7 instructions. */
823d2571
TG		 4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4449 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4451 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4452
90ec0d68 4453 /* Virtualization Extension instructions. */
823d2571 4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4455 /* We skip ERET as that is SUBS pc, lr, #0. */
4456
60e5ef9f 4457 /* MP Extension instructions. */
823d2571 4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4459
f4c65163 4460 /* Security extension instructions. */
823d2571 4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4462
7fadb25d
SD		 4463 /* ARMv8.5-A instructions. */
4464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4465
8f06b2d8 4466 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4473 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4475
ff8646ee 4476 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4477 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4479 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4481 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4483 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4485 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4487 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4489 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4491 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4493 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4495 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4497 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4499 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4501 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4503 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4505 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4507 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4509 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4511 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4513 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4515 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4517 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4519 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4521 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4523 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4525 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4527 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4529 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4531 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4533 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4535 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4537 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4539 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4541 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4543 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4545 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4547 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4549 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4551 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4553 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4555 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4557 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4559 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4561 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4563 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4565 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4567 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4569 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4571 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4573 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4575 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4577 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4579 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4581 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4583 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4585 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4587 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4589 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4591 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4593 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4595 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4597 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4599 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4601 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4603 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4605 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4607 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4609 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4611 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4613 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4615 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4617 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4619 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4621 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4623 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4625 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4627 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4629 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4631 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4632 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4633 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4635 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4637 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4639 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4641 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4643 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4645 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4647 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4649 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4651 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4653 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4655 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4657 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4659 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4661 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4663 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4667 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4669 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4671 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4675 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4677 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4697 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4700 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4701 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4703 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4705 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4707 0xf810f000, 0xff70f000, "pld%c\t%a"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733 0xfb100000, 0xfff000c0,
4734 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736 0xfbc00080, 0xfff000c0,
4737 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4743 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4749 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4753 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4763 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4771 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4774 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4775 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xe9400000, 0xff500000,
4810 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xe9500000, 0xff500000,
4813 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815 0xe8600000, 0xff700000,
4816 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xe8700000, 0xff700000,
4819 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4824
4825 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4834
8f06b2d8 4835 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4837 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4839 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4840
4841 /* Fallback. */
823d2571
TG		 4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4843 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4844 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4845};
ff4a8d2b 4846
8f06b2d8
PB		 4847static const char *const arm_conditional[] =
4848{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4849 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 4850
4851static const char *const arm_fp_const[] =
4852{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4853
4854static const char *const arm_shift[] =
4855{"lsl", "lsr", "asr", "ror"};
4856
4857typedef struct
4858{
4859 const char *name;
4860 const char *description;
4861 const char *reg_names[16];
4862}
4863arm_regname;
4864
4865static const arm_regname regnames[] =
4866{
65b48a81 4867 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4868 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4869 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4870 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4871 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4872 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4873 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4874 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4875 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4876 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4877 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4878 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 4879 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4880 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 4881};
4882
4883static const char *const iwmmxt_wwnames[] =
4884{"b", "h", "w", "d"};
4885
4886static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4887{"b", "bus", "bc", "bss",
4888 "h", "hus", "hc", "hss",
4889 "w", "wus", "wc", "wss",
4890 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4891};
4892
4893static const char *const iwmmxt_regnames[] =
4894{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4895 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4896};
4897
4898static const char *const iwmmxt_cregnames[] =
4899{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4900 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4901};
4902
143275ea
AV		 4903static const char *const vec_condnames[] =
4904{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4905};
4906
4907static const char *const mve_predicatenames[] =
4908{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4909 "eee", "ee", "eet", "e", "ett", "et", "ete"
4910};
4911
4912/* Names for 2-bit size field for mve vector isntructions. */
4913static const char *const mve_vec_sizename[] =
4914 { "8", "16", "32", "64"};
4915
4916/* Indicates whether we are processing a then predicate,
4917 else predicate or none at all. */
4918enum vpt_pred_state
4919{
4920 PRED_NONE,
4921 PRED_THEN,
4922 PRED_ELSE
4923};
4924
4925/* Information used to process a vpt block and subsequent instructions. */
4926struct vpt_block
4927{
4928 /* Are we in a vpt block. */
4929 bfd_boolean in_vpt_block;
4930
4931 /* Next predicate state if in vpt block. */
4932 enum vpt_pred_state next_pred_state;
4933
4934 /* Mask from vpt/vpst instruction. */
4935 long predicate_mask;
4936
4937 /* Instruction number in vpt block. */
4938 long current_insn_num;
4939
4940 /* Number of instructions in vpt block.. */
4941 long num_pred_insn;
4942};
4943
4944static struct vpt_block vpt_block_state =
4945{
4946 FALSE,
4947 PRED_NONE,
4948 0,
4949 0,
4950 0
4951};
4952
8f06b2d8
PB		 4953/* Default to GCC register name set. */
4954static unsigned int regname_selected = 1;
4955
65b48a81 4956#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 4957#define arm_regnames regnames[regname_selected].reg_names
4958
4959static bfd_boolean force_thumb = FALSE;
4960
c22aaad1
PB		 4961/* Current IT instruction state. This contains the same state as the IT
4962 bits in the CPSR. */
4963static unsigned int ifthen_state;
4964/* IT state for the next instruction. */
4965static unsigned int ifthen_next_state;
4966/* The address of the insn for which the IT state is valid. */
4967static bfd_vma ifthen_address;
4968#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 4969/* Indicates that the current Conditional state is unconditional or outside
4970 an IT block. */
4971#define COND_UNCOND 16
c22aaad1 4972
8f06b2d8
PB		 4973\f
4974/* Functions. */
143275ea
AV		 4975/* Extract the predicate mask for a VPT or VPST instruction.
4976 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4977
4978static long
4979mve_extract_pred_mask (long given)
4980{
4981 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4982}
4983
4984/* Return the number of instructions in a MVE predicate block. */
4985static long
4986num_instructions_vpt_block (long given)
4987{
4988 long mask = mve_extract_pred_mask (given);
4989 if (mask == 0)
4990 return 0;
4991
4992 if (mask == 8)
4993 return 1;
4994
4995 if ((mask & 7) == 4)
4996 return 2;
4997
4998 if ((mask & 3) == 2)
4999 return 3;
5000
5001 if ((mask & 1) == 1)
5002 return 4;
5003
5004 return 0;
5005}
5006
5007static void
5008mark_outside_vpt_block (void)
5009{
5010 vpt_block_state.in_vpt_block = FALSE;
5011 vpt_block_state.next_pred_state = PRED_NONE;
5012 vpt_block_state.predicate_mask = 0;
5013 vpt_block_state.current_insn_num = 0;
5014 vpt_block_state.num_pred_insn = 0;
5015}
5016
5017static void
5018mark_inside_vpt_block (long given)
5019{
5020 vpt_block_state.in_vpt_block = TRUE;
5021 vpt_block_state.next_pred_state = PRED_THEN;
5022 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5023 vpt_block_state.current_insn_num = 0;
5024 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5025 assert (vpt_block_state.num_pred_insn >= 1);
5026}
5027
5028static enum vpt_pred_state
5029invert_next_predicate_state (enum vpt_pred_state astate)
5030{
5031 if (astate == PRED_THEN)
5032 return PRED_ELSE;
5033 else if (astate == PRED_ELSE)
5034 return PRED_THEN;
5035 else
5036 return PRED_NONE;
5037}
5038
5039static enum vpt_pred_state
5040update_next_predicate_state (void)
5041{
5042 long pred_mask = vpt_block_state.predicate_mask;
5043 long mask_for_insn = 0;
5044
5045 switch (vpt_block_state.current_insn_num)
5046 {
5047 case 1:
5048 mask_for_insn = 8;
5049 break;
5050
5051 case 2:
5052 mask_for_insn = 4;
5053 break;
5054
5055 case 3:
5056 mask_for_insn = 2;
5057 break;
5058
5059 case 4:
5060 return PRED_NONE;
5061 }
5062
5063 if (pred_mask & mask_for_insn)
5064 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5065 else
5066 return vpt_block_state.next_pred_state;
5067}
5068
5069static void
5070update_vpt_block_state (void)
5071{
5072 vpt_block_state.current_insn_num++;
5073 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5074 {
5075 /* No more instructions to process in vpt block. */
5076 mark_outside_vpt_block ();
5077 return;
5078 }
5079
5080 vpt_block_state.next_pred_state = update_next_predicate_state ();
5081}
8f06b2d8 5082
16980d0b
JB		 5083/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5084 Returns pointer to following character of the format string and
5085 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5086 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5087
5088static const char *
fe56b6ce
NC		 5089arm_decode_bitfield (const char *ptr,
5090 unsigned long insn,
5091 unsigned long *valuep,
5092 int *widthp)
16980d0b
JB		 5093{
5094 unsigned long value = 0;
5095 int width = 0;
43e65147
L		 5096
5097 do
16980d0b
JB		 5098 {
5099 int start, end;
5100 int bits;
5101
5102 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5103 start = start * 10 + *ptr - '0';
5104 if (*ptr == '-')
5105 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5106 end = end * 10 + *ptr - '0';
5107 else
5108 end = start;
5109 bits = end - start;
5110 if (bits < 0)
5111 abort ();
5112 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5113 width += bits + 1;
5114 }
5115 while (*ptr++ == ',');
5116 *valuep = value;
5117 if (widthp)
5118 *widthp = width;
5119 return ptr - 1;
5120}
5121
8f06b2d8 5122static void
37b37b2d 5123arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5124 bfd_boolean print_shift)
8f06b2d8
PB		 5125{
5126 func (stream, "%s", arm_regnames[given & 0xf]);
5127
5128 if ((given & 0xff0) != 0)
5129 {
5130 if ((given & 0x10) == 0)
5131 {
5132 int amount = (given & 0xf80) >> 7;
5133 int shift = (given & 0x60) >> 5;
5134
5135 if (amount == 0)
5136 {
5137 if (shift == 3)
5138 {
5139 func (stream, ", rrx");
5140 return;
5141 }
5142
5143 amount = 32;
5144 }
5145
37b37b2d
RE		 5146 if (print_shift)
5147 func (stream, ", %s #%d", arm_shift[shift], amount);
5148 else
5149 func (stream, ", #%d", amount);
8f06b2d8 5150 }
74bdfecf 5151 else if ((given & 0x80) == 0x80)
aefd8a40 5152 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5153 else if (print_shift)
8f06b2d8
PB		 5154 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5155 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5156 else
5157 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5158 }
5159}
5160
73cd51e5
AV		 5161/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5162
5163static bfd_boolean
5164is_mve_okay_in_it (enum mve_instructions matched_insn)
5165{
c507f10b
AV		 5166 switch (matched_insn)
5167 {
5168 case MVE_VMOV_GP_TO_VEC_LANE:
5169 case MVE_VMOV2_VEC_LANE_TO_GP:
5170 case MVE_VMOV2_GP_TO_VEC_LANE:
5171 case MVE_VMOV_VEC_LANE_TO_GP:
5172 return TRUE;
5173 default:
5174 return FALSE;
5175 }
73cd51e5
AV		 5176}
5177
5178static bfd_boolean
5179is_mve_architecture (struct disassemble_info *info)
5180{
5181 struct arm_private_data *private_data = info->private_data;
5182 arm_feature_set allowed_arches = private_data->features;
5183
5184 arm_feature_set arm_ext_v8_1m_main
5185 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5186
5187 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5188 && !ARM_CPU_IS_ANY (allowed_arches))
5189 return TRUE;
5190 else
5191 return FALSE;
5192}
5193
143275ea
AV		 5194static bfd_boolean
5195is_vpt_instruction (long given)
5196{
5197
5198 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5199 if ((given & 0x0040e000) == 0)
5200 return FALSE;
5201
5202 /* VPT floating point T1 variant. */
5203 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5204 /* VPT floating point T2 variant. */
5205 || ((given & 0xefb10f50) == 0xee310f40)
5206 /* VPT vector T1 variant. */
5207 || ((given & 0xff811f51) == 0xfe010f00)
5208 /* VPT vector T2 variant. */
5209 || ((given & 0xff811f51) == 0xfe010f01
5210 && ((given & 0x300000) != 0x300000))
5211 /* VPT vector T3 variant. */
5212 || ((given & 0xff811f50) == 0xfe011f00)
5213 /* VPT vector T4 variant. */
5214 || ((given & 0xff811f70) == 0xfe010f40)
5215 /* VPT vector T5 variant. */
5216 || ((given & 0xff811f70) == 0xfe010f60)
5217 /* VPT vector T6 variant. */
5218 || ((given & 0xff811f50) == 0xfe011f40)
5219 /* VPST vector T variant. */
5220 || ((given & 0xffbf1fff) == 0xfe310f4d))
5221 return TRUE;
5222 else
5223 return FALSE;
5224}
5225
73cd51e5
AV		 5226/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5227 and ending bitfield = END. END must be greater than START. */
5228
5229static unsigned long
5230arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5231{
5232 int bits = end - start;
5233
5234 if (bits < 0)
5235 abort ();
5236
5237 return ((given >> start) & ((2ul << bits) - 1));
5238}
5239
5240/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5241 START:END and START2:END2. END/END2 must be greater than
5242 START/START2. */
5243
5244static unsigned long
5245arm_decode_field_multiple (unsigned long given, unsigned int start,
5246 unsigned int end, unsigned int start2,
5247 unsigned int end2)
5248{
5249 int bits = end - start;
5250 int bits2 = end2 - start2;
5251 unsigned long value = 0;
5252 int width = 0;
5253
5254 if (bits2 < 0)
5255 abort ();
5256
5257 value = arm_decode_field (given, start, end);
5258 width += bits + 1;
5259
5260 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5261 return value;
5262}
5263
5264/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5265 This helps us decode instructions that change mnemonic depending on specific
5266 operand values/encodings. */
5267
5268static bfd_boolean
5269is_mve_encoding_conflict (unsigned long given,
5270 enum mve_instructions matched_insn)
5271{
143275ea
AV		 5272 switch (matched_insn)
5273 {
5274 case MVE_VPST:
5275 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5276 return TRUE;
5277 else
5278 return FALSE;
5279
5280 case MVE_VPT_FP_T1:
5281 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5282 return TRUE;
5283 if ((arm_decode_field (given, 12, 12) == 0)
5284 && (arm_decode_field (given, 0, 0) == 1))
5285 return TRUE;
5286 return FALSE;
5287
5288 case MVE_VPT_FP_T2:
5289 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5290 return TRUE;
5291 if (arm_decode_field (given, 0, 3) == 0xd)
5292 return TRUE;
5293 return FALSE;
5294
5295 case MVE_VPT_VEC_T1:
5296 case MVE_VPT_VEC_T2:
5297 case MVE_VPT_VEC_T3:
5298 case MVE_VPT_VEC_T4:
5299 case MVE_VPT_VEC_T5:
5300 case MVE_VPT_VEC_T6:
5301 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5302 return TRUE;
5303 if (arm_decode_field (given, 20, 21) == 3)
5304 return TRUE;
5305 return FALSE;
5306
5307 case MVE_VCMP_FP_T1:
5308 if ((arm_decode_field (given, 12, 12) == 0)
5309 && (arm_decode_field (given, 0, 0) == 1))
5310 return TRUE;
5311 else
5312 return FALSE;
5313
5314 case MVE_VCMP_FP_T2:
5315 if (arm_decode_field (given, 0, 3) == 0xd)
5316 return TRUE;
5317 else
5318 return FALSE;
5319
14b456f2
AV		 5320 case MVE_VQADD_T2:
5321 case MVE_VQSUB_T2:
f49bb598
AV		 5322 case MVE_VMUL_VEC_T2:
5323 case MVE_VMULH:
5324 case MVE_VRMULH:
56858bea
AV		 5325 case MVE_VMLA:
5326 case MVE_VMAX:
5327 case MVE_VMIN:
e523f101 5328 case MVE_VBRSR:
66dcaa5d
AV		 5329 case MVE_VADD_VEC_T2:
5330 case MVE_VSUB_VEC_T2:
5331 case MVE_VABAV:
ed63aa17
AV		 5332 case MVE_VQRSHL_T1:
5333 case MVE_VQSHL_T4:
5334 case MVE_VRSHL_T1:
5335 case MVE_VSHL_T3:
897b9bbc
AV		 5336 case MVE_VCADD_VEC:
5337 case MVE_VHCADD:
1c8f2df8
AV		 5338 case MVE_VDDUP:
5339 case MVE_VIDUP:
d3b63143
AV		 5340 case MVE_VQRDMLADH:
5341 case MVE_VQDMLAH:
5342 case MVE_VQRDMLAH:
5343 case MVE_VQDMLASH:
5344 case MVE_VQRDMLASH:
5345 case MVE_VQDMLSDH:
5346 case MVE_VQRDMLSDH:
5347 case MVE_VQDMULH_T3:
5348 case MVE_VQRDMULH_T4:
5349 case MVE_VQDMLADH:
5350 case MVE_VMLAS:
14925797 5351 case MVE_VMULL_INT:
9743db03
AV		 5352 case MVE_VHADD_T2:
5353 case MVE_VHSUB_T2:
143275ea
AV		 5354 case MVE_VCMP_VEC_T1:
5355 case MVE_VCMP_VEC_T2:
5356 case MVE_VCMP_VEC_T3:
5357 case MVE_VCMP_VEC_T4:
5358 case MVE_VCMP_VEC_T5:
5359 case MVE_VCMP_VEC_T6:
5360 if (arm_decode_field (given, 20, 21) == 3)
5361 return TRUE;
5362 else
5363 return FALSE;
5364
04d54ace
AV		 5365 case MVE_VLD2:
5366 case MVE_VLD4:
5367 case MVE_VST2:
5368 case MVE_VST4:
5369 if (arm_decode_field (given, 7, 8) == 3)
5370 return TRUE;
5371 else
5372 return FALSE;
5373
aef6d006
AV		 5374 case MVE_VSTRB_T1:
5375 case MVE_VSTRH_T2:
5376 if ((arm_decode_field (given, 24, 24) == 0)
5377 && (arm_decode_field (given, 21, 21) == 0))
5378 {
5379 return TRUE;
5380 }
5381 else if ((arm_decode_field (given, 7, 8) == 3))
5382 return TRUE;
5383 else
5384 return FALSE;
5385
5386 case MVE_VSTRB_T5:
5387 case MVE_VSTRH_T6:
5388 case MVE_VSTRW_T7:
5389 if ((arm_decode_field (given, 24, 24) == 0)
5390 && (arm_decode_field (given, 21, 21) == 0))
5391 {
5392 return TRUE;
5393 }
5394 else
5395 return FALSE;
5396
bf0b396d
AV		 5397 case MVE_VCVT_FP_FIX_VEC:
5398 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5399
c507f10b
AV		 5400 case MVE_VBIC_IMM:
5401 case MVE_VORR_IMM:
5402 {
5403 unsigned long cmode = arm_decode_field (given, 8, 11);
5404
5405 if ((cmode & 1) == 0)
5406 return TRUE;
5407 else if ((cmode & 0xc) == 0xc)
5408 return TRUE;
5409 else
5410 return FALSE;
5411 }
5412
5413 case MVE_VMVN_IMM:
5414 {
5415 unsigned long cmode = arm_decode_field (given, 8, 11);
5416
5417 if ((cmode & 9) == 1)
5418 return TRUE;
5419 else if ((cmode & 5) == 1)
5420 return TRUE;
5421 else if ((cmode & 0xe) == 0xe)
5422 return TRUE;
5423 else
5424 return FALSE;
5425 }
5426
5427 case MVE_VMOV_IMM_TO_VEC:
5428 if ((arm_decode_field (given, 5, 5) == 1)
5429 && (arm_decode_field (given, 8, 11) != 0xe))
5430 return TRUE;
5431 else
5432 return FALSE;
5433
14925797
AV		 5434 case MVE_VMOVL:
5435 {
5436 unsigned long size = arm_decode_field (given, 19, 20);
5437 if ((size == 0) || (size == 3))
5438 return TRUE;
5439 else
5440 return FALSE;
5441 }
5442
56858bea
AV		 5443 case MVE_VMAXA:
5444 case MVE_VMINA:
5445 case MVE_VMAXV:
5446 case MVE_VMAXAV:
5447 case MVE_VMINV:
5448 case MVE_VMINAV:
ed63aa17
AV		 5449 case MVE_VQRSHL_T2:
5450 case MVE_VQSHL_T1:
5451 case MVE_VRSHL_T2:
5452 case MVE_VSHL_T2:
5453 case MVE_VSHLL_T2:
d3b63143 5454 case MVE_VADDV:
14925797
AV		 5455 case MVE_VMOVN:
5456 case MVE_VQMOVUN:
5457 case MVE_VQMOVN:
5458 if (arm_decode_field (given, 18, 19) == 3)
5459 return TRUE;
5460 else
5461 return FALSE;
5462
d3b63143
AV		 5463 case MVE_VMLSLDAV:
5464 case MVE_VRMLSLDAVH:
5465 case MVE_VMLALDAV:
5466 case MVE_VADDLV:
5467 if (arm_decode_field (given, 20, 22) == 7)
5468 return TRUE;
5469 else
5470 return FALSE;
5471
5472 case MVE_VRMLALDAVH:
5473 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5474 return TRUE;
5475 else
5476 return FALSE;
5477
1c8f2df8
AV		 5478 case MVE_VDWDUP:
5479 case MVE_VIWDUP:
5480 if ((arm_decode_field (given, 20, 21) == 3)
5481 || (arm_decode_field (given, 1, 3) == 7))
5482 return TRUE;
5483 else
5484 return FALSE;
5485
ed63aa17
AV		 5486
5487 case MVE_VSHLL_T1:
5488 if (arm_decode_field (given, 16, 18) == 0)
5489 {
5490 unsigned long sz = arm_decode_field (given, 19, 20);
5491
5492 if ((sz == 1) || (sz == 2))
5493 return TRUE;
5494 else
5495 return FALSE;
5496 }
5497 else
5498 return FALSE;
5499
5500 case MVE_VQSHL_T2:
5501 case MVE_VQSHLU_T3:
5502 case MVE_VRSHR:
5503 case MVE_VSHL_T1:
5504 case MVE_VSHR:
5505 case MVE_VSLI:
5506 case MVE_VSRI:
5507 if (arm_decode_field (given, 19, 21) == 0)
5508 return TRUE;
5509 else
5510 return FALSE;
5511
e523f101
AV		 5512 case MVE_VCTP:
5513 if (arm_decode_field (given, 16, 19) == 0xf)
5514 return TRUE;
5515 else
5516 return FALSE;
5517
143275ea 5518 default:
66dcaa5d
AV		 5519 case MVE_VADD_FP_T1:
5520 case MVE_VADD_FP_T2:
5521 case MVE_VADD_VEC_T1:
143275ea
AV		 5522 return FALSE;
5523
5524 }
73cd51e5
AV		 5525}
5526
aef6d006
AV		 5527static void
5528print_mve_vld_str_addr (struct disassemble_info *info,
5529 unsigned long given,
5530 enum mve_instructions matched_insn)
5531{
5532 void *stream = info->stream;
5533 fprintf_ftype func = info->fprintf_func;
5534
5535 unsigned long p, w, gpr, imm, add, mod_imm;
5536
5537 imm = arm_decode_field (given, 0, 6);
5538 mod_imm = imm;
5539
5540 switch (matched_insn)
5541 {
5542 case MVE_VLDRB_T1:
5543 case MVE_VSTRB_T1:
5544 gpr = arm_decode_field (given, 16, 18);
5545 break;
5546
5547 case MVE_VLDRH_T2:
5548 case MVE_VSTRH_T2:
5549 gpr = arm_decode_field (given, 16, 18);
5550 mod_imm = imm << 1;
5551 break;
5552
5553 case MVE_VLDRH_T6:
5554 case MVE_VSTRH_T6:
5555 gpr = arm_decode_field (given, 16, 19);
5556 mod_imm = imm << 1;
5557 break;
5558
5559 case MVE_VLDRW_T7:
5560 case MVE_VSTRW_T7:
5561 gpr = arm_decode_field (given, 16, 19);
5562 mod_imm = imm << 2;
5563 break;
5564
5565 case MVE_VLDRB_T5:
5566 case MVE_VSTRB_T5:
5567 gpr = arm_decode_field (given, 16, 19);
5568 break;
5569
5570 default:
5571 return;
5572 }
5573
5574 p = arm_decode_field (given, 24, 24);
5575 w = arm_decode_field (given, 21, 21);
5576
5577 add = arm_decode_field (given, 23, 23);
5578
5579 char * add_sub;
5580
5581 /* Don't print anything for '+' as it is implied. */
5582 if (add == 1)
5583 add_sub = "";
5584 else
5585 add_sub = "-";
5586
5587 if (p == 1)
5588 {
5589 /* Offset mode. */
5590 if (w == 0)
5591 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5592 /* Pre-indexed mode. */
5593 else
5594 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5595 }
5596 else if ((p == 0) && (w == 1))
5597 /* Post-index mode. */
5598 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5599}
5600
73cd51e5
AV		 5601/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5602 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5603 this encoding is undefined. */
5604
5605static bfd_boolean
5606is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5607 enum mve_undefined *undefined_code)
5608{
5609 *undefined_code = UNDEF_NONE;
5610
9743db03
AV		 5611 switch (matched_insn)
5612 {
5613 case MVE_VDUP:
5614 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5615 {
5616 *undefined_code = UNDEF_SIZE_3;
5617 return TRUE;
5618 }
5619 else
5620 return FALSE;
5621
14b456f2
AV		 5622 case MVE_VQADD_T1:
5623 case MVE_VQSUB_T1:
f49bb598 5624 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5625 case MVE_VABD_VEC:
5626 case MVE_VADD_VEC_T1:
5627 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5628 case MVE_VQDMULH_T1:
5629 case MVE_VQRDMULH_T2:
9743db03
AV		 5630 case MVE_VRHADD:
5631 case MVE_VHADD_T1:
5632 case MVE_VHSUB_T1:
5633 if (arm_decode_field (given, 20, 21) == 3)
5634 {
5635 *undefined_code = UNDEF_SIZE_3;
5636 return TRUE;
5637 }
5638 else
5639 return FALSE;
5640
aef6d006
AV		 5641 case MVE_VLDRB_T1:
5642 if (arm_decode_field (given, 7, 8) == 3)
5643 {
5644 *undefined_code = UNDEF_SIZE_3;
5645 return TRUE;
5646 }
5647 else
5648 return FALSE;
5649
5650 case MVE_VLDRH_T2:
5651 if (arm_decode_field (given, 7, 8) <= 1)
5652 {
5653 *undefined_code = UNDEF_SIZE_LE_1;
5654 return TRUE;
5655 }
5656 else
5657 return FALSE;
5658
5659 case MVE_VSTRB_T1:
5660 if ((arm_decode_field (given, 7, 8) == 0))
5661 {
5662 *undefined_code = UNDEF_SIZE_0;
5663 return TRUE;
5664 }
5665 else
5666 return FALSE;
5667
5668 case MVE_VSTRH_T2:
5669 if ((arm_decode_field (given, 7, 8) <= 1))
5670 {
5671 *undefined_code = UNDEF_SIZE_LE_1;
5672 return TRUE;
5673 }
5674 else
5675 return FALSE;
5676
ef1576a1
AV		 5677 case MVE_VLDRB_GATHER_T1:
5678 if (arm_decode_field (given, 7, 8) == 3)
5679 {
5680 *undefined_code = UNDEF_SIZE_3;
5681 return TRUE;
5682 }
5683 else if ((arm_decode_field (given, 28, 28) == 0)
5684 && (arm_decode_field (given, 7, 8) == 0))
5685 {
5686 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5687 return TRUE;
5688 }
5689 else
5690 return FALSE;
5691
5692 case MVE_VLDRH_GATHER_T2:
5693 if (arm_decode_field (given, 7, 8) == 3)
5694 {
5695 *undefined_code = UNDEF_SIZE_3;
5696 return TRUE;
5697 }
5698 else if ((arm_decode_field (given, 28, 28) == 0)
5699 && (arm_decode_field (given, 7, 8) == 1))
5700 {
5701 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5702 return TRUE;
5703 }
5704 else if (arm_decode_field (given, 7, 8) == 0)
5705 {
5706 *undefined_code = UNDEF_SIZE_0;
5707 return TRUE;
5708 }
5709 else
5710 return FALSE;
5711
5712 case MVE_VLDRW_GATHER_T3:
5713 if (arm_decode_field (given, 7, 8) != 2)
5714 {
5715 *undefined_code = UNDEF_SIZE_NOT_2;
5716 return TRUE;
5717 }
5718 else if (arm_decode_field (given, 28, 28) == 0)
5719 {
5720 *undefined_code = UNDEF_NOT_UNSIGNED;
5721 return TRUE;
5722 }
5723 else
5724 return FALSE;
5725
5726 case MVE_VLDRD_GATHER_T4:
5727 if (arm_decode_field (given, 7, 8) != 3)
5728 {
5729 *undefined_code = UNDEF_SIZE_NOT_3;
5730 return TRUE;
5731 }
5732 else if (arm_decode_field (given, 28, 28) == 0)
5733 {
5734 *undefined_code = UNDEF_NOT_UNSIGNED;
5735 return TRUE;
5736 }
5737 else
5738 return FALSE;
5739
5740 case MVE_VSTRB_SCATTER_T1:
5741 if (arm_decode_field (given, 7, 8) == 3)
5742 {
5743 *undefined_code = UNDEF_SIZE_3;
5744 return TRUE;
5745 }
5746 else
5747 return FALSE;
5748
5749 case MVE_VSTRH_SCATTER_T2:
5750 {
5751 unsigned long size = arm_decode_field (given, 7, 8);
5752 if (size == 3)
5753 {
5754 *undefined_code = UNDEF_SIZE_3;
5755 return TRUE;
5756 }
5757 else if (size == 0)
5758 {
5759 *undefined_code = UNDEF_SIZE_0;
5760 return TRUE;
5761 }
5762 else
5763 return FALSE;
5764 }
5765
5766 case MVE_VSTRW_SCATTER_T3:
5767 if (arm_decode_field (given, 7, 8) != 2)
5768 {
5769 *undefined_code = UNDEF_SIZE_NOT_2;
5770 return TRUE;
5771 }
5772 else
5773 return FALSE;
5774
5775 case MVE_VSTRD_SCATTER_T4:
5776 if (arm_decode_field (given, 7, 8) != 3)
5777 {
5778 *undefined_code = UNDEF_SIZE_NOT_3;
5779 return TRUE;
5780 }
5781 else
5782 return FALSE;
5783
bf0b396d
AV		 5784 case MVE_VCVT_FP_FIX_VEC:
5785 {
5786 unsigned long imm6 = arm_decode_field (given, 16, 21);
5787 if ((imm6 & 0x20) == 0)
5788 {
5789 *undefined_code = UNDEF_VCVT_IMM6;
5790 return TRUE;
5791 }
5792
5793 if ((arm_decode_field (given, 9, 9) == 0)
5794 && ((imm6 & 0x30) == 0x20))
5795 {
5796 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5797 return TRUE;
5798 }
5799
5800 return FALSE;
5801 }
5802
f49bb598 5803 case MVE_VNEG_FP:
66dcaa5d 5804 case MVE_VABS_FP:
bf0b396d
AV		 5805 case MVE_VCVT_BETWEEN_FP_INT:
5806 case MVE_VCVT_FROM_FP_TO_INT:
5807 {
5808 unsigned long size = arm_decode_field (given, 18, 19);
5809 if (size == 0)
5810 {
5811 *undefined_code = UNDEF_SIZE_0;
5812 return TRUE;
5813 }
5814 else if (size == 3)
5815 {
5816 *undefined_code = UNDEF_SIZE_3;
5817 return TRUE;
5818 }
5819 else
5820 return FALSE;
5821 }
5822
c507f10b
AV		 5823 case MVE_VMOV_VEC_LANE_TO_GP:
5824 {
5825 unsigned long op1 = arm_decode_field (given, 21, 22);
5826 unsigned long op2 = arm_decode_field (given, 5, 6);
5827 unsigned long u = arm_decode_field (given, 23, 23);
5828
5829 if ((op2 == 0) && (u == 1))
5830 {
5831 if ((op1 == 0) || (op1 == 1))
5832 {
5833 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5834 return TRUE;
5835 }
5836 else
5837 return FALSE;
5838 }
5839 else if (op2 == 2)
5840 {
5841 if ((op1 == 0) || (op1 == 1))
5842 {
5843 *undefined_code = UNDEF_BAD_OP1_OP2;
5844 return TRUE;
5845 }
5846 else
5847 return FALSE;
5848 }
5849
5850 return FALSE;
5851 }
5852
5853 case MVE_VMOV_GP_TO_VEC_LANE:
5854 if (arm_decode_field (given, 5, 6) == 2)
5855 {
5856 unsigned long op1 = arm_decode_field (given, 21, 22);
5857 if ((op1 == 0) || (op1 == 1))
5858 {
5859 *undefined_code = UNDEF_BAD_OP1_OP2;
5860 return TRUE;
5861 }
5862 else
5863 return FALSE;
5864 }
5865 else
5866 return FALSE;
5867
5868 case MVE_VMOV_IMM_TO_VEC:
5869 if (arm_decode_field (given, 5, 5) == 0)
5870 {
5871 unsigned long cmode = arm_decode_field (given, 8, 11);
5872
5873 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5874 {
5875 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5876 return TRUE;
5877 }
5878 else
5879 return FALSE;
5880 }
5881 else
5882 return FALSE;
5883
ed63aa17 5884 case MVE_VSHLL_T2:
14925797
AV		 5885 case MVE_VMOVN:
5886 if (arm_decode_field (given, 18, 19) == 2)
5887 {
5888 *undefined_code = UNDEF_SIZE_2;
5889 return TRUE;
5890 }
5891 else
5892 return FALSE;
5893
d3b63143
AV		 5894 case MVE_VRMLALDAVH:
5895 case MVE_VMLADAV_T1:
5896 case MVE_VMLADAV_T2:
5897 case MVE_VMLALDAV:
5898 if ((arm_decode_field (given, 28, 28) == 1)
5899 && (arm_decode_field (given, 12, 12) == 1))
5900 {
5901 *undefined_code = UNDEF_XCHG_UNS;
5902 return TRUE;
5903 }
5904 else
5905 return FALSE;
5906
ed63aa17
AV		 5907 case MVE_VQSHRN:
5908 case MVE_VQSHRUN:
5909 case MVE_VSHLL_T1:
5910 case MVE_VSHRN:
5911 {
5912 unsigned long sz = arm_decode_field (given, 19, 20);
5913 if (sz == 1)
5914 return FALSE;
5915 else if ((sz & 2) == 2)
5916 return FALSE;
5917 else
5918 {
5919 *undefined_code = UNDEF_SIZE;
5920 return TRUE;
5921 }
5922 }
5923 break;
5924
5925 case MVE_VQSHL_T2:
5926 case MVE_VQSHLU_T3:
5927 case MVE_VRSHR:
5928 case MVE_VSHL_T1:
5929 case MVE_VSHR:
5930 case MVE_VSLI:
5931 case MVE_VSRI:
5932 {
5933 unsigned long sz = arm_decode_field (given, 19, 21);
5934 if ((sz & 7) == 1)
5935 return FALSE;
5936 else if ((sz & 6) == 2)
5937 return FALSE;
5938 else if ((sz & 4) == 4)
5939 return FALSE;
5940 else
5941 {
5942 *undefined_code = UNDEF_SIZE;
5943 return TRUE;
5944 }
5945 }
5946
5947 case MVE_VQRSHRN:
5948 case MVE_VQRSHRUN:
5949 if (arm_decode_field (given, 19, 20) == 0)
5950 {
5951 *undefined_code = UNDEF_SIZE_0;
5952 return TRUE;
5953 }
5954 else
5955 return FALSE;
5956
66dcaa5d
AV		 5957 case MVE_VABS_VEC:
5958 if (arm_decode_field (given, 18, 19) == 3)
5959 {
5960 *undefined_code = UNDEF_SIZE_3;
5961 return TRUE;
5962 }
5963 else
5964 return FALSE;
5965
14b456f2
AV		 5966 case MVE_VQNEG:
5967 case MVE_VQABS:
f49bb598 5968 case MVE_VNEG_VEC:
e523f101
AV		 5969 case MVE_VCLS:
5970 case MVE_VCLZ:
5971 if (arm_decode_field (given, 18, 19) == 3)
5972 {
5973 *undefined_code = UNDEF_SIZE_3;
5974 return TRUE;
5975 }
5976 else
5977 return FALSE;
5978
14b456f2
AV		 5979 case MVE_VREV16:
5980 if (arm_decode_field (given, 18, 19) == 0)
5981 return FALSE;
5982 else
5983 {
5984 *undefined_code = UNDEF_SIZE_NOT_0;
5985 return TRUE;
5986 }
5987
5988 case MVE_VREV32:
5989 {
5990 unsigned long size = arm_decode_field (given, 18, 19);
5991 if ((size & 2) == 2)
5992 {
5993 *undefined_code = UNDEF_SIZE_2;
5994 return TRUE;
5995 }
5996 else
5997 return FALSE;
5998 }
5999
6000 case MVE_VREV64:
6001 if (arm_decode_field (given, 18, 19) != 3)
6002 return FALSE;
6003 else
6004 {
6005 *undefined_code = UNDEF_SIZE_3;
6006 return TRUE;
6007 }
6008
9743db03
AV		 6009 default:
6010 return FALSE;
6011 }
73cd51e5
AV		 6012}
6013
6014/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6015 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6016 why this encoding is unpredictable. */
6017
6018static bfd_boolean
6019is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6020 enum mve_unpredictable *unpredictable_code)
6021{
6022 *unpredictable_code = UNPRED_NONE;
6023
143275ea
AV		 6024 switch (matched_insn)
6025 {
6026 case MVE_VCMP_FP_T2:
6027 case MVE_VPT_FP_T2:
6028 if ((arm_decode_field (given, 12, 12) == 0)
6029 && (arm_decode_field (given, 5, 5) == 1))
6030 {
6031 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6032 return TRUE;
6033 }
6034 else
6035 return FALSE;
73cd51e5 6036
143275ea
AV		 6037 case MVE_VPT_VEC_T4:
6038 case MVE_VPT_VEC_T5:
6039 case MVE_VPT_VEC_T6:
6040 case MVE_VCMP_VEC_T4:
6041 case MVE_VCMP_VEC_T5:
6042 case MVE_VCMP_VEC_T6:
6043 if (arm_decode_field (given, 0, 3) == 0xd)
6044 {
6045 *unpredictable_code = UNPRED_R13;
6046 return TRUE;
6047 }
6048 else
6049 return FALSE;
c1e26897 6050
9743db03
AV		 6051 case MVE_VDUP:
6052 {
6053 unsigned long gpr = arm_decode_field (given, 12, 15);
6054 if (gpr == 0xd)
6055 {
6056 *unpredictable_code = UNPRED_R13;
6057 return TRUE;
6058 }
6059 else if (gpr == 0xf)
6060 {
6061 *unpredictable_code = UNPRED_R15;
6062 return TRUE;
6063 }
6064
6065 return FALSE;
6066 }
6067
14b456f2
AV		 6068 case MVE_VQADD_T2:
6069 case MVE_VQSUB_T2:
f49bb598
AV		 6070 case MVE_VMUL_FP_T2:
6071 case MVE_VMUL_VEC_T2:
56858bea 6072 case MVE_VMLA:
e523f101 6073 case MVE_VBRSR:
66dcaa5d
AV		 6074 case MVE_VADD_FP_T2:
6075 case MVE_VSUB_FP_T2:
6076 case MVE_VADD_VEC_T2:
6077 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6078 case MVE_VQRSHL_T2:
6079 case MVE_VQSHL_T1:
6080 case MVE_VRSHL_T2:
6081 case MVE_VSHL_T2:
6082 case MVE_VSHLC:
d3b63143
AV		 6083 case MVE_VQDMLAH:
6084 case MVE_VQRDMLAH:
6085 case MVE_VQDMLASH:
6086 case MVE_VQRDMLASH:
6087 case MVE_VQDMULH_T3:
6088 case MVE_VQRDMULH_T4:
6089 case MVE_VMLAS:
9743db03
AV		 6090 case MVE_VFMA_FP_SCALAR:
6091 case MVE_VFMAS_FP_SCALAR:
6092 case MVE_VHADD_T2:
6093 case MVE_VHSUB_T2:
6094 {
6095 unsigned long gpr = arm_decode_field (given, 0, 3);
6096 if (gpr == 0xd)
6097 {
6098 *unpredictable_code = UNPRED_R13;
6099 return TRUE;
6100 }
6101 else if (gpr == 0xf)
6102 {
6103 *unpredictable_code = UNPRED_R15;
6104 return TRUE;
6105 }
6106
6107 return FALSE;
6108 }
6109
04d54ace
AV		 6110 case MVE_VLD2:
6111 case MVE_VST2:
6112 {
6113 unsigned long rn = arm_decode_field (given, 16, 19);
6114
6115 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6116 {
6117 *unpredictable_code = UNPRED_R13_AND_WB;
6118 return TRUE;
6119 }
6120
6121 if (rn == 0xf)
6122 {
6123 *unpredictable_code = UNPRED_R15;
6124 return TRUE;
6125 }
6126
6127 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6128 {
6129 *unpredictable_code = UNPRED_Q_GT_6;
6130 return TRUE;
6131 }
6132 else
6133 return FALSE;
6134 }
6135
6136 case MVE_VLD4:
6137 case MVE_VST4:
6138 {
6139 unsigned long rn = arm_decode_field (given, 16, 19);
6140
6141 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6142 {
6143 *unpredictable_code = UNPRED_R13_AND_WB;
6144 return TRUE;
6145 }
6146
6147 if (rn == 0xf)
6148 {
6149 *unpredictable_code = UNPRED_R15;
6150 return TRUE;
6151 }
6152
6153 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6154 {
6155 *unpredictable_code = UNPRED_Q_GT_4;
6156 return TRUE;
6157 }
6158 else
6159 return FALSE;
6160 }
6161
aef6d006
AV		 6162 case MVE_VLDRB_T5:
6163 case MVE_VLDRH_T6:
6164 case MVE_VLDRW_T7:
6165 case MVE_VSTRB_T5:
6166 case MVE_VSTRH_T6:
6167 case MVE_VSTRW_T7:
6168 {
6169 unsigned long rn = arm_decode_field (given, 16, 19);
6170
6171 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6172 {
6173 *unpredictable_code = UNPRED_R13_AND_WB;
6174 return TRUE;
6175 }
6176 else if (rn == 0xf)
6177 {
6178 *unpredictable_code = UNPRED_R15;
6179 return TRUE;
6180 }
6181 else
6182 return FALSE;
6183 }
6184
ef1576a1
AV		 6185 case MVE_VLDRB_GATHER_T1:
6186 if (arm_decode_field (given, 0, 0) == 1)
6187 {
6188 *unpredictable_code = UNPRED_OS;
6189 return TRUE;
6190 }
6191
6192 /* fall through. */
6193 /* To handle common code with T2-T4 variants. */
6194 case MVE_VLDRH_GATHER_T2:
6195 case MVE_VLDRW_GATHER_T3:
6196 case MVE_VLDRD_GATHER_T4:
6197 {
6198 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6199 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6200
6201 if (qd == qm)
6202 {
6203 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6204 return TRUE;
6205 }
6206
6207 if (arm_decode_field (given, 16, 19) == 0xf)
6208 {
6209 *unpredictable_code = UNPRED_R15;
6210 return TRUE;
6211 }
6212
6213 return FALSE;
6214 }
6215
6216 case MVE_VLDRW_GATHER_T5:
6217 case MVE_VLDRD_GATHER_T6:
6218 {
6219 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6220 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6221
6222 if (qd == qm)
6223 {
6224 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6225 return TRUE;
6226 }
6227 else
6228 return FALSE;
6229 }
6230
6231 case MVE_VSTRB_SCATTER_T1:
6232 if (arm_decode_field (given, 16, 19) == 0xf)
6233 {
6234 *unpredictable_code = UNPRED_R15;
6235 return TRUE;
6236 }
6237 else if (arm_decode_field (given, 0, 0) == 1)
6238 {
6239 *unpredictable_code = UNPRED_OS;
6240 return TRUE;
6241 }
6242 else
6243 return FALSE;
6244
6245 case MVE_VSTRH_SCATTER_T2:
6246 case MVE_VSTRW_SCATTER_T3:
6247 case MVE_VSTRD_SCATTER_T4:
6248 if (arm_decode_field (given, 16, 19) == 0xf)
6249 {
6250 *unpredictable_code = UNPRED_R15;
6251 return TRUE;
6252 }
6253 else
6254 return FALSE;
6255
c507f10b
AV		 6256 case MVE_VMOV2_VEC_LANE_TO_GP:
6257 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6258 case MVE_VCVT_BETWEEN_FP_INT:
6259 case MVE_VCVT_FROM_FP_TO_INT:
6260 {
6261 unsigned long rt = arm_decode_field (given, 0, 3);
6262 unsigned long rt2 = arm_decode_field (given, 16, 19);
6263
6264 if ((rt == 0xd) || (rt2 == 0xd))
6265 {
6266 *unpredictable_code = UNPRED_R13;
6267 return TRUE;
6268 }
6269 else if ((rt == 0xf) || (rt2 == 0xf))
6270 {
6271 *unpredictable_code = UNPRED_R15;
6272 return TRUE;
6273 }
6274 else if (rt == rt2)
6275 {
6276 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6277 return TRUE;
6278 }
6279
6280 return FALSE;
6281 }
6282
56858bea
AV		 6283 case MVE_VMAXV:
6284 case MVE_VMAXAV:
6285 case MVE_VMAXNMV_FP:
6286 case MVE_VMAXNMAV_FP:
6287 case MVE_VMINNMV_FP:
6288 case MVE_VMINNMAV_FP:
6289 case MVE_VMINV:
6290 case MVE_VMINAV:
66dcaa5d 6291 case MVE_VABAV:
c507f10b
AV		 6292 case MVE_VMOV_HFP_TO_GP:
6293 case MVE_VMOV_GP_TO_VEC_LANE:
6294 case MVE_VMOV_VEC_LANE_TO_GP:
6295 {
6296 unsigned long rda = arm_decode_field (given, 12, 15);
6297 if (rda == 0xd)
6298 {
6299 *unpredictable_code = UNPRED_R13;
6300 return TRUE;
6301 }
6302 else if (rda == 0xf)
6303 {
6304 *unpredictable_code = UNPRED_R15;
6305 return TRUE;
6306 }
6307
6308 return FALSE;
6309 }
6310
d3b63143
AV		 6311 case MVE_VQRDMLADH:
6312 case MVE_VQDMLSDH:
6313 case MVE_VQRDMLSDH:
6314 case MVE_VQDMLADH:
14925797
AV		 6315 case MVE_VMULL_INT:
6316 {
6317 unsigned long Qd;
6318 unsigned long Qm;
6319 unsigned long Qn;
6320
6321 if (arm_decode_field (given, 20, 21) == 2)
6322 {
6323 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6324 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6325 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6326
6327 if ((Qd == Qn) || (Qd == Qm))
6328 {
6329 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6330 return TRUE;
6331 }
6332 else
6333 return FALSE;
6334 }
6335 else
6336 return FALSE;
6337 }
6338
897b9bbc 6339 case MVE_VCMUL_FP:
14925797
AV		 6340 case MVE_VQDMULL_T1:
6341 {
6342 unsigned long Qd;
6343 unsigned long Qm;
6344 unsigned long Qn;
6345
6346 if (arm_decode_field (given, 28, 28) == 1)
6347 {
6348 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6349 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6350 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6351
6352 if ((Qd == Qn) || (Qd == Qm))
6353 {
6354 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6355 return TRUE;
6356 }
6357 else
6358 return FALSE;
6359 }
6360 else
6361 return FALSE;
6362 }
6363
6364 case MVE_VQDMULL_T2:
6365 {
6366 unsigned long gpr = arm_decode_field (given, 0, 3);
6367 if (gpr == 0xd)
6368 {
6369 *unpredictable_code = UNPRED_R13;
6370 return TRUE;
6371 }
6372 else if (gpr == 0xf)
6373 {
6374 *unpredictable_code = UNPRED_R15;
6375 return TRUE;
6376 }
6377
6378 if (arm_decode_field (given, 28, 28) == 1)
6379 {
6380 unsigned long Qd
6381 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6382 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6383
6384 if ((Qd == Qn))
6385 {
6386 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6387 return TRUE;
6388 }
6389 else
6390 return FALSE;
6391 }
6392
6393 return FALSE;
6394 }
6395
d3b63143
AV		 6396 case MVE_VMLSLDAV:
6397 case MVE_VRMLSLDAVH:
6398 case MVE_VMLALDAV:
6399 case MVE_VADDLV:
6400 if (arm_decode_field (given, 20, 22) == 6)
6401 {
6402 *unpredictable_code = UNPRED_R13;
6403 return TRUE;
6404 }
6405 else
6406 return FALSE;
6407
1c8f2df8
AV		 6408 case MVE_VDWDUP:
6409 case MVE_VIWDUP:
6410 if (arm_decode_field (given, 1, 3) == 6)
6411 {
6412 *unpredictable_code = UNPRED_R13;
6413 return TRUE;
6414 }
6415 else
6416 return FALSE;
6417
897b9bbc
AV		 6418 case MVE_VCADD_VEC:
6419 case MVE_VHCADD:
6420 {
6421 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6422 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6423 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6424 {
6425 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6426 return TRUE;
6427 }
6428 else
6429 return FALSE;
6430 }
6431
6432 case MVE_VCADD_FP:
6433 {
6434 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6435 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6436 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6437 {
6438 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6439 return TRUE;
6440 }
6441 else
6442 return FALSE;
6443 }
6444
6445 case MVE_VCMLA_FP:
6446 {
6447 unsigned long Qda;
6448 unsigned long Qm;
6449 unsigned long Qn;
6450
6451 if (arm_decode_field (given, 20, 20) == 1)
6452 {
6453 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6454 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6455 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6456
6457 if ((Qda == Qn) || (Qda == Qm))
6458 {
6459 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6460 return TRUE;
6461 }
6462 else
6463 return FALSE;
6464 }
6465 else
6466 return FALSE;
6467
6468 }
6469
e523f101
AV		 6470 case MVE_VCTP:
6471 if (arm_decode_field (given, 16, 19) == 0xd)
6472 {
6473 *unpredictable_code = UNPRED_R13;
6474 return TRUE;
6475 }
6476 else
6477 return FALSE;
6478
14b456f2
AV		 6479 case MVE_VREV64:
6480 {
6481 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6482 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6483
6484 if (qd == qm)
6485 {
6486 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6487 return TRUE;
6488 }
6489 else
6490 return FALSE;
6491 }
6492
143275ea
AV		 6493 default:
6494 return FALSE;
6495 }
6496}
c1e26897 6497
c507f10b
AV		 6498static void
6499print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6500{
6501 unsigned long op1 = arm_decode_field (given, 21, 22);
6502 unsigned long op2 = arm_decode_field (given, 5, 6);
6503 unsigned long h = arm_decode_field (given, 16, 16);
6504 unsigned long index, esize, targetBeat, idx;
6505 void *stream = info->stream;
6506 fprintf_ftype func = info->fprintf_func;
6507
6508 if ((op1 & 0x2) == 0x2)
6509 {
6510 index = op2;
6511 esize = 8;
6512 }
6513 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6514 {
6515 index = op2 >> 1;
6516 esize = 16;
6517 }
6518 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6519 {
6520 index = 0;
6521 esize = 32;
6522 }
6523 else
6524 {
6525 func (stream, "<undefined index>");
6526 return;
6527 }
6528
6529 targetBeat = (op1 & 0x1) | (h << 1);
6530 idx = index + targetBeat * (32/esize);
6531
6532 func (stream, "%lu", idx);
6533}
6534
6535/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6536 in length and integer of floating-point type. */
6537static void
6538print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6539 unsigned int ibit_loc, const struct mopcode32 *insn)
6540{
6541 int bits = 0;
6542 int cmode = (given >> 8) & 0xf;
6543 int op = (given >> 5) & 0x1;
6544 unsigned long value = 0, hival = 0;
6545 unsigned shift;
6546 int size = 0;
6547 int isfloat = 0;
6548 void *stream = info->stream;
6549 fprintf_ftype func = info->fprintf_func;
6550
6551 /* On Neon the 'i' bit is at bit 24, on mve it is
6552 at bit 28. */
6553 bits |= ((given >> ibit_loc) & 1) << 7;
6554 bits |= ((given >> 16) & 7) << 4;
6555 bits |= ((given >> 0) & 15) << 0;
6556
6557 if (cmode < 8)
6558 {
6559 shift = (cmode >> 1) & 3;
6560 value = (unsigned long) bits << (8 * shift);
6561 size = 32;
6562 }
6563 else if (cmode < 12)
6564 {
6565 shift = (cmode >> 1) & 1;
6566 value = (unsigned long) bits << (8 * shift);
6567 size = 16;
6568 }
6569 else if (cmode < 14)
6570 {
6571 shift = (cmode & 1) + 1;
6572 value = (unsigned long) bits << (8 * shift);
6573 value |= (1ul << (8 * shift)) - 1;
6574 size = 32;
6575 }
6576 else if (cmode == 14)
6577 {
6578 if (op)
6579 {
6580 /* Bit replication into bytes. */
6581 int ix;
6582 unsigned long mask;
6583
6584 value = 0;
6585 hival = 0;
6586 for (ix = 7; ix >= 0; ix--)
6587 {
6588 mask = ((bits >> ix) & 1) ? 0xff : 0;
6589 if (ix <= 3)
6590 value = (value << 8) | mask;
6591 else
6592 hival = (hival << 8) | mask;
6593 }
6594 size = 64;
6595 }
6596 else
6597 {
6598 /* Byte replication. */
6599 value = (unsigned long) bits;
6600 size = 8;
6601 }
6602 }
6603 else if (!op)
6604 {
6605 /* Floating point encoding. */
6606 int tmp;
6607
6608 value = (unsigned long) (bits & 0x7f) << 19;
6609 value |= (unsigned long) (bits & 0x80) << 24;
6610 tmp = bits & 0x40 ? 0x3c : 0x40;
6611 value |= (unsigned long) tmp << 24;
6612 size = 32;
6613 isfloat = 1;
6614 }
6615 else
6616 {
6617 func (stream, "<illegal constant %.8x:%x:%x>",
6618 bits, cmode, op);
6619 size = 32;
6620 return;
6621 }
6622
6623 // printU determines whether the immediate value should be printed as
6624 // unsigned.
6625 unsigned printU = 0;
6626 switch (insn->mve_op)
6627 {
6628 default:
6629 break;
6630 // We want this for instructions that don't have a 'signed' type
6631 case MVE_VBIC_IMM:
6632 case MVE_VORR_IMM:
6633 case MVE_VMVN_IMM:
6634 case MVE_VMOV_IMM_TO_VEC:
6635 printU = 1;
6636 break;
6637 }
6638 switch (size)
6639 {
6640 case 8:
6641 func (stream, "#%ld\t; 0x%.2lx", value, value);
6642 break;
6643
6644 case 16:
6645 func (stream,
6646 printU
6647 ? "#%lu\t; 0x%.4lx"
6648 : "#%ld\t; 0x%.4lx", value, value);
6649 break;
6650
6651 case 32:
6652 if (isfloat)
6653 {
6654 unsigned char valbytes[4];
6655 double fvalue;
6656
6657 /* Do this a byte at a time so we don't have to
6658 worry about the host's endianness. */
6659 valbytes[0] = value & 0xff;
6660 valbytes[1] = (value >> 8) & 0xff;
6661 valbytes[2] = (value >> 16) & 0xff;
6662 valbytes[3] = (value >> 24) & 0xff;
6663
6664 floatformat_to_double
6665 (& floatformat_ieee_single_little, valbytes,
6666 & fvalue);
6667
6668 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6669 value);
6670 }
6671 else
6672 func (stream,
6673 printU
6674 ? "#%lu\t; 0x%.8lx"
6675 : "#%ld\t; 0x%.8lx",
6676 (long) (((value & 0x80000000L) != 0)
6677 && !printU
6678 ? value | ~0xffffffffL : value),
6679 value);
6680 break;
6681
6682 case 64:
6683 func (stream, "#0x%.8lx%.8lx", hival, value);
6684 break;
6685
6686 default:
6687 abort ();
6688 }
6689
6690}
6691
73cd51e5
AV		 6692static void
6693print_mve_undefined (struct disassemble_info *info,
6694 enum mve_undefined undefined_code)
6695{
6696 void *stream = info->stream;
6697 fprintf_ftype func = info->fprintf_func;
6698
6699 func (stream, "\t\tundefined instruction: ");
6700
6701 switch (undefined_code)
6702 {
ed63aa17
AV		 6703 case UNDEF_SIZE:
6704 func (stream, "illegal size");
6705 break;
6706
aef6d006
AV		 6707 case UNDEF_SIZE_0:
6708 func (stream, "size equals zero");
6709 break;
6710
c507f10b
AV		 6711 case UNDEF_SIZE_2:
6712 func (stream, "size equals two");
6713 break;
6714
9743db03
AV		 6715 case UNDEF_SIZE_3:
6716 func (stream, "size equals three");
6717 break;
6718
aef6d006
AV		 6719 case UNDEF_SIZE_LE_1:
6720 func (stream, "size <= 1");
6721 break;
6722
14b456f2
AV		 6723 case UNDEF_SIZE_NOT_0:
6724 func (stream, "size not equal to 0");
6725 break;
6726
ef1576a1
AV		 6727 case UNDEF_SIZE_NOT_2:
6728 func (stream, "size not equal to 2");
6729 break;
6730
6731 case UNDEF_SIZE_NOT_3:
6732 func (stream, "size not equal to 3");
6733 break;
6734
6735 case UNDEF_NOT_UNS_SIZE_0:
6736 func (stream, "not unsigned and size = zero");
6737 break;
6738
6739 case UNDEF_NOT_UNS_SIZE_1:
6740 func (stream, "not unsigned and size = one");
6741 break;
6742
6743 case UNDEF_NOT_UNSIGNED:
6744 func (stream, "not unsigned");
6745 break;
6746
bf0b396d
AV		 6747 case UNDEF_VCVT_IMM6:
6748 func (stream, "invalid imm6");
6749 break;
6750
6751 case UNDEF_VCVT_FSI_IMM6:
6752 func (stream, "fsi = 0 and invalid imm6");
6753 break;
6754
c507f10b
AV		 6755 case UNDEF_BAD_OP1_OP2:
6756 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6757 break;
6758
6759 case UNDEF_BAD_U_OP1_OP2:
6760 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6761 break;
6762
6763 case UNDEF_OP_0_BAD_CMODE:
6764 func (stream, "op field equal 0 and bad cmode");
6765 break;
6766
d3b63143
AV		 6767 case UNDEF_XCHG_UNS:
6768 func (stream, "exchange and unsigned together");
6769 break;
6770
73cd51e5
AV		 6771 case UNDEF_NONE:
6772 break;
6773 }
6774
6775}
6776
6777static void
6778print_mve_unpredictable (struct disassemble_info *info,
6779 enum mve_unpredictable unpredict_code)
6780{
6781 void *stream = info->stream;
6782 fprintf_ftype func = info->fprintf_func;
6783
6784 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6785
6786 switch (unpredict_code)
6787 {
6788 case UNPRED_IT_BLOCK:
6789 func (stream, "mve instruction in it block");
6790 break;
6791
143275ea
AV		 6792 case UNPRED_FCA_0_FCB_1:
6793 func (stream, "condition bits, fca = 0 and fcb = 1");
6794 break;
6795
6796 case UNPRED_R13:
6797 func (stream, "use of r13 (sp)");
6798 break;
6799
9743db03
AV		 6800 case UNPRED_R15:
6801 func (stream, "use of r15 (pc)");
6802 break;
6803
04d54ace
AV		 6804 case UNPRED_Q_GT_4:
6805 func (stream, "start register block > r4");
6806 break;
6807
6808 case UNPRED_Q_GT_6:
6809 func (stream, "start register block > r6");
6810 break;
6811
6812 case UNPRED_R13_AND_WB:
6813 func (stream, "use of r13 and write back");
6814 break;
6815
ef1576a1
AV		 6816 case UNPRED_Q_REGS_EQUAL:
6817 func (stream,
6818 "same vector register used for destination and other operand");
6819 break;
6820
6821 case UNPRED_OS:
6822 func (stream, "use of offset scaled");
6823 break;
6824
bf0b396d
AV		 6825 case UNPRED_GP_REGS_EQUAL:
6826 func (stream, "same general-purpose register used for both operands");
6827 break;
6828
c507f10b
AV		 6829 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6830 func (stream, "use of identical q registers and size = 1");
6831 break;
6832
6833 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6834 func (stream, "use of identical q registers and size = 1");
6835 break;
6836
73cd51e5
AV		 6837 case UNPRED_NONE:
6838 break;
6839 }
6840}
6841
04d54ace
AV		 6842/* Print register block operand for mve vld2/vld4/vst2/vld4. */
6843
6844static void
6845print_mve_register_blocks (struct disassemble_info *info,
6846 unsigned long given,
6847 enum mve_instructions matched_insn)
6848{
6849 void *stream = info->stream;
6850 fprintf_ftype func = info->fprintf_func;
6851
6852 unsigned long q_reg_start = arm_decode_field_multiple (given,
6853 13, 15,
6854 22, 22);
6855 switch (matched_insn)
6856 {
6857 case MVE_VLD2:
6858 case MVE_VST2:
6859 if (q_reg_start <= 6)
6860 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6861 else
6862 func (stream, "<illegal reg q%ld>", q_reg_start);
6863 break;
6864
6865 case MVE_VLD4:
6866 case MVE_VST4:
6867 if (q_reg_start <= 4)
6868 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6869 q_reg_start + 1, q_reg_start + 2,
6870 q_reg_start + 3);
6871 else
6872 func (stream, "<illegal reg q%ld>", q_reg_start);
6873 break;
6874
6875 default:
6876 break;
6877 }
6878}
6879
bf0b396d
AV		 6880static void
6881print_mve_rounding_mode (struct disassemble_info *info,
6882 unsigned long given,
6883 enum mve_instructions matched_insn)
6884{
6885 void *stream = info->stream;
6886 fprintf_ftype func = info->fprintf_func;
6887
6888 switch (matched_insn)
6889 {
6890 case MVE_VCVT_FROM_FP_TO_INT:
6891 {
6892 switch (arm_decode_field (given, 8, 9))
6893 {
6894 case 0:
6895 func (stream, "a");
6896 break;
6897
6898 case 1:
6899 func (stream, "n");
6900 break;
6901
6902 case 2:
6903 func (stream, "p");
6904 break;
6905
6906 case 3:
6907 func (stream, "m");
6908 break;
6909
6910 default:
6911 break;
6912 }
6913 }
6914 break;
6915
6916 case MVE_VRINT_FP:
6917 {
6918 switch (arm_decode_field (given, 7, 9))
6919 {
6920 case 0:
6921 func (stream, "n");
6922 break;
6923
6924 case 1:
6925 func (stream, "x");
6926 break;
6927
6928 case 2:
6929 func (stream, "a");
6930 break;
6931
6932 case 3:
6933 func (stream, "z");
6934 break;
6935
6936 case 5:
6937 func (stream, "m");
6938 break;
6939
6940 case 7:
6941 func (stream, "p");
6942
6943 case 4:
6944 case 6:
6945 default:
6946 break;
6947 }
6948 }
6949 break;
6950
6951 default:
6952 break;
6953 }
6954}
6955
6956static void
6957print_mve_vcvt_size (struct disassemble_info *info,
6958 unsigned long given,
6959 enum mve_instructions matched_insn)
6960{
6961 unsigned long mode = 0;
6962 void *stream = info->stream;
6963 fprintf_ftype func = info->fprintf_func;
6964
6965 switch (matched_insn)
6966 {
6967 case MVE_VCVT_FP_FIX_VEC:
6968 {
6969 mode = (((given & 0x200) >> 7)
6970 | ((given & 0x10000000) >> 27)
6971 | ((given & 0x100) >> 8));
6972
6973 switch (mode)
6974 {
6975 case 0:
6976 func (stream, "f16.s16");
6977 break;
6978
6979 case 1:
6980 func (stream, "s16.f16");
6981 break;
6982
6983 case 2:
6984 func (stream, "f16.u16");
6985 break;
6986
6987 case 3:
6988 func (stream, "u16.f16");
6989 break;
6990
6991 case 4:
6992 func (stream, "f32.s32");
6993 break;
6994
6995 case 5:
6996 func (stream, "s32.f32");
6997 break;
6998
6999 case 6:
7000 func (stream, "f32.u32");
7001 break;
7002
7003 case 7:
7004 func (stream, "u32.f32");
7005 break;
7006
7007 default:
7008 break;
7009 }
7010 break;
7011 }
7012 case MVE_VCVT_BETWEEN_FP_INT:
7013 {
7014 unsigned long size = arm_decode_field (given, 18, 19);
7015 unsigned long op = arm_decode_field (given, 7, 8);
7016
7017 if (size == 1)
7018 {
7019 switch (op)
7020 {
7021 case 0:
7022 func (stream, "f16.s16");
7023 break;
7024
7025 case 1:
7026 func (stream, "f16.u16");
7027 break;
7028
7029 case 2:
7030 func (stream, "s16.f16");
7031 break;
7032
7033 case 3:
7034 func (stream, "u16.f16");
7035 break;
7036
7037 default:
7038 break;
7039 }
7040 }
7041 else if (size == 2)
7042 {
7043 switch (op)
7044 {
7045 case 0:
7046 func (stream, "f32.s32");
7047 break;
7048
7049 case 1:
7050 func (stream, "f32.u32");
7051 break;
7052
7053 case 2:
7054 func (stream, "s32.f32");
7055 break;
7056
7057 case 3:
7058 func (stream, "u32.f32");
7059 break;
7060 }
7061 }
7062 }
7063 break;
7064
7065 case MVE_VCVT_FP_HALF_FP:
7066 {
7067 unsigned long op = arm_decode_field (given, 28, 28);
7068 if (op == 0)
7069 func (stream, "f16.f32");
7070 else if (op == 1)
7071 func (stream, "f32.f16");
7072 }
7073 break;
7074
7075 case MVE_VCVT_FROM_FP_TO_INT:
7076 {
7077 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7078
7079 switch (size)
7080 {
7081 case 2:
7082 func (stream, "s16.f16");
7083 break;
7084
7085 case 3:
7086 func (stream, "u16.f16");
7087 break;
7088
7089 case 4:
7090 func (stream, "s32.f32");
7091 break;
7092
7093 case 5:
7094 func (stream, "u32.f32");
7095 break;
7096
7097 default:
7098 break;
7099 }
7100 }
7101 break;
7102
7103 default:
7104 break;
7105 }
7106}
7107
897b9bbc
AV		 7108static void
7109print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7110 unsigned long rot_width)
7111{
7112 void *stream = info->stream;
7113 fprintf_ftype func = info->fprintf_func;
7114
7115 if (rot_width == 1)
7116 {
7117 switch (rot)
7118 {
7119 case 0:
7120 func (stream, "90");
7121 break;
7122 case 1:
7123 func (stream, "270");
7124 break;
7125 default:
7126 break;
7127 }
7128 }
7129 else if (rot_width == 2)
7130 {
7131 switch (rot)
7132 {
7133 case 0:
7134 func (stream, "0");
7135 break;
7136 case 1:
7137 func (stream, "90");
7138 break;
7139 case 2:
7140 func (stream, "180");
7141 break;
7142 case 3:
7143 func (stream, "270");
7144 break;
7145 default:
7146 break;
7147 }
7148 }
7149}
7150
143275ea
AV		 7151static void
7152print_instruction_predicate (struct disassemble_info *info)
7153{
7154 void *stream = info->stream;
7155 fprintf_ftype func = info->fprintf_func;
7156
7157 if (vpt_block_state.next_pred_state == PRED_THEN)
7158 func (stream, "t");
7159 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7160 func (stream, "e");
7161}
7162
7163static void
7164print_mve_size (struct disassemble_info *info,
7165 unsigned long size,
7166 enum mve_instructions matched_insn)
7167{
7168 void *stream = info->stream;
7169 fprintf_ftype func = info->fprintf_func;
7170
7171 switch (matched_insn)
7172 {
66dcaa5d
AV		 7173 case MVE_VABAV:
7174 case MVE_VABD_VEC:
7175 case MVE_VABS_FP:
7176 case MVE_VABS_VEC:
7177 case MVE_VADD_VEC_T1:
7178 case MVE_VADD_VEC_T2:
d3b63143 7179 case MVE_VADDV:
e523f101 7180 case MVE_VBRSR:
897b9bbc 7181 case MVE_VCADD_VEC:
e523f101
AV		 7182 case MVE_VCLS:
7183 case MVE_VCLZ:
143275ea
AV		 7184 case MVE_VCMP_VEC_T1:
7185 case MVE_VCMP_VEC_T2:
7186 case MVE_VCMP_VEC_T3:
7187 case MVE_VCMP_VEC_T4:
7188 case MVE_VCMP_VEC_T5:
7189 case MVE_VCMP_VEC_T6:
e523f101 7190 case MVE_VCTP:
1c8f2df8
AV		 7191 case MVE_VDDUP:
7192 case MVE_VDWDUP:
9743db03
AV		 7193 case MVE_VHADD_T1:
7194 case MVE_VHADD_T2:
897b9bbc 7195 case MVE_VHCADD:
9743db03
AV		 7196 case MVE_VHSUB_T1:
7197 case MVE_VHSUB_T2:
1c8f2df8
AV		 7198 case MVE_VIDUP:
7199 case MVE_VIWDUP:
04d54ace
AV		 7200 case MVE_VLD2:
7201 case MVE_VLD4:
ef1576a1
AV		 7202 case MVE_VLDRB_GATHER_T1:
7203 case MVE_VLDRH_GATHER_T2:
7204 case MVE_VLDRW_GATHER_T3:
7205 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7206 case MVE_VLDRB_T1:
7207 case MVE_VLDRH_T2:
56858bea
AV		 7208 case MVE_VMAX:
7209 case MVE_VMAXA:
7210 case MVE_VMAXV:
7211 case MVE_VMAXAV:
7212 case MVE_VMIN:
7213 case MVE_VMINA:
7214 case MVE_VMINV:
7215 case MVE_VMINAV:
7216 case MVE_VMLA:
d3b63143 7217 case MVE_VMLAS:
f49bb598
AV		 7218 case MVE_VMUL_VEC_T1:
7219 case MVE_VMUL_VEC_T2:
7220 case MVE_VMULH:
7221 case MVE_VRMULH:
7222 case MVE_VMULL_INT:
7223 case MVE_VNEG_FP:
7224 case MVE_VNEG_VEC:
143275ea
AV		 7225 case MVE_VPT_VEC_T1:
7226 case MVE_VPT_VEC_T2:
7227 case MVE_VPT_VEC_T3:
7228 case MVE_VPT_VEC_T4:
7229 case MVE_VPT_VEC_T5:
7230 case MVE_VPT_VEC_T6:
14b456f2
AV		 7231 case MVE_VQABS:
7232 case MVE_VQADD_T1:
7233 case MVE_VQADD_T2:
d3b63143
AV		 7234 case MVE_VQDMLADH:
7235 case MVE_VQRDMLADH:
7236 case MVE_VQDMLAH:
7237 case MVE_VQRDMLAH:
7238 case MVE_VQDMLASH:
7239 case MVE_VQRDMLASH:
7240 case MVE_VQDMLSDH:
7241 case MVE_VQRDMLSDH:
7242 case MVE_VQDMULH_T1:
7243 case MVE_VQRDMULH_T2:
7244 case MVE_VQDMULH_T3:
7245 case MVE_VQRDMULH_T4:
14b456f2 7246 case MVE_VQNEG:
ed63aa17
AV		 7247 case MVE_VQRSHL_T1:
7248 case MVE_VQRSHL_T2:
7249 case MVE_VQSHL_T1:
7250 case MVE_VQSHL_T4:
14b456f2
AV		 7251 case MVE_VQSUB_T1:
7252 case MVE_VQSUB_T2:
7253 case MVE_VREV32:
7254 case MVE_VREV64:
9743db03 7255 case MVE_VRHADD:
bf0b396d 7256 case MVE_VRINT_FP:
ed63aa17
AV		 7257 case MVE_VRSHL_T1:
7258 case MVE_VRSHL_T2:
7259 case MVE_VSHL_T2:
7260 case MVE_VSHL_T3:
7261 case MVE_VSHLL_T2:
04d54ace
AV		 7262 case MVE_VST2:
7263 case MVE_VST4:
ef1576a1
AV		 7264 case MVE_VSTRB_SCATTER_T1:
7265 case MVE_VSTRH_SCATTER_T2:
7266 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7267 case MVE_VSTRB_T1:
7268 case MVE_VSTRH_T2:
66dcaa5d
AV		 7269 case MVE_VSUB_VEC_T1:
7270 case MVE_VSUB_VEC_T2:
143275ea
AV		 7271 if (size <= 3)
7272 func (stream, "%s", mve_vec_sizename[size]);
7273 else
7274 func (stream, "<undef size>");
7275 break;
7276
66dcaa5d
AV		 7277 case MVE_VABD_FP:
7278 case MVE_VADD_FP_T1:
7279 case MVE_VADD_FP_T2:
7280 case MVE_VSUB_FP_T1:
7281 case MVE_VSUB_FP_T2:
143275ea
AV		 7282 case MVE_VCMP_FP_T1:
7283 case MVE_VCMP_FP_T2:
9743db03
AV		 7284 case MVE_VFMA_FP_SCALAR:
7285 case MVE_VFMA_FP:
7286 case MVE_VFMS_FP:
7287 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7288 case MVE_VMAXNM_FP:
7289 case MVE_VMAXNMA_FP:
7290 case MVE_VMAXNMV_FP:
7291 case MVE_VMAXNMAV_FP:
7292 case MVE_VMINNM_FP:
7293 case MVE_VMINNMA_FP:
7294 case MVE_VMINNMV_FP:
7295 case MVE_VMINNMAV_FP:
f49bb598
AV		 7296 case MVE_VMUL_FP_T1:
7297 case MVE_VMUL_FP_T2:
143275ea
AV		 7298 case MVE_VPT_FP_T1:
7299 case MVE_VPT_FP_T2:
7300 if (size == 0)
7301 func (stream, "32");
7302 else if (size == 1)
7303 func (stream, "16");
7304 break;
7305
897b9bbc
AV		 7306 case MVE_VCADD_FP:
7307 case MVE_VCMLA_FP:
7308 case MVE_VCMUL_FP:
d3b63143
AV		 7309 case MVE_VMLADAV_T1:
7310 case MVE_VMLALDAV:
7311 case MVE_VMLSDAV_T1:
7312 case MVE_VMLSLDAV:
14925797
AV		 7313 case MVE_VMOVN:
7314 case MVE_VQDMULL_T1:
7315 case MVE_VQDMULL_T2:
7316 case MVE_VQMOVN:
7317 case MVE_VQMOVUN:
7318 if (size == 0)
7319 func (stream, "16");
7320 else if (size == 1)
7321 func (stream, "32");
7322 break;
7323
7324 case MVE_VMOVL:
7325 if (size == 1)
7326 func (stream, "8");
7327 else if (size == 2)
7328 func (stream, "16");
7329 break;
7330
9743db03
AV		 7331 case MVE_VDUP:
7332 switch (size)
7333 {
7334 case 0:
7335 func (stream, "32");
7336 break;
7337 case 1:
7338 func (stream, "16");
7339 break;
7340 case 2:
7341 func (stream, "8");
7342 break;
7343 default:
7344 break;
7345 }
7346 break;
7347
c507f10b
AV		 7348 case MVE_VMOV_GP_TO_VEC_LANE:
7349 case MVE_VMOV_VEC_LANE_TO_GP:
7350 switch (size)
7351 {
7352 case 0: case 4:
7353 func (stream, "32");
7354 break;
7355
7356 case 1: case 3:
7357 case 5: case 7:
7358 func (stream, "16");
7359 break;
7360
7361 case 8: case 9: case 10: case 11:
7362 case 12: case 13: case 14: case 15:
7363 func (stream, "8");
7364 break;
7365
7366 default:
7367 break;
7368 }
7369 break;
7370
7371 case MVE_VMOV_IMM_TO_VEC:
7372 switch (size)
7373 {
7374 case 0: case 4: case 8:
7375 case 12: case 24: case 26:
7376 func (stream, "i32");
7377 break;
7378 case 16: case 20:
7379 func (stream, "i16");
7380 break;
7381 case 28:
7382 func (stream, "i8");
7383 break;
7384 case 29:
7385 func (stream, "i64");
7386 break;
7387 case 30:
7388 func (stream, "f32");
7389 break;
7390 default:
7391 break;
7392 }
7393 break;
7394
14925797
AV		 7395 case MVE_VMULL_POLY:
7396 if (size == 0)
7397 func (stream, "p8");
7398 else if (size == 1)
7399 func (stream, "p16");
7400 break;
7401
c507f10b
AV		 7402 case MVE_VMVN_IMM:
7403 switch (size)
7404 {
7405 case 0: case 2: case 4:
7406 case 6: case 12: case 13:
7407 func (stream, "32");
7408 break;
7409
7410 case 8: case 10:
7411 func (stream, "16");
7412 break;
7413
7414 default:
7415 break;
7416 }
7417 break;
7418
7419 case MVE_VBIC_IMM:
7420 case MVE_VORR_IMM:
7421 switch (size)
7422 {
7423 case 1: case 3:
7424 case 5: case 7:
7425 func (stream, "32");
7426 break;
7427
7428 case 9: case 11:
7429 func (stream, "16");
7430 break;
7431
7432 default:
7433 break;
7434 }
7435 break;
7436
ed63aa17
AV		 7437 case MVE_VQSHRN:
7438 case MVE_VQSHRUN:
7439 case MVE_VQRSHRN:
7440 case MVE_VQRSHRUN:
7441 case MVE_VRSHRN:
7442 case MVE_VSHRN:
7443 {
7444 switch (size)
7445 {
7446 case 1:
7447 func (stream, "16");
7448 break;
7449
7450 case 2: case 3:
7451 func (stream, "32");
7452 break;
7453
7454 default:
7455 break;
7456 }
7457 }
7458 break;
7459
7460 case MVE_VQSHL_T2:
7461 case MVE_VQSHLU_T3:
7462 case MVE_VRSHR:
7463 case MVE_VSHL_T1:
7464 case MVE_VSHLL_T1:
7465 case MVE_VSHR:
7466 case MVE_VSLI:
7467 case MVE_VSRI:
7468 {
7469 switch (size)
7470 {
7471 case 1:
7472 func (stream, "8");
7473 break;
7474
7475 case 2: case 3:
7476 func (stream, "16");
7477 break;
7478
7479 case 4: case 5: case 6: case 7:
7480 func (stream, "32");
7481 break;
7482
7483 default:
7484 break;
7485 }
7486 }
7487 break;
7488
143275ea
AV		 7489 default:
7490 break;
7491 }
7492}
7493
ed63aa17
AV		 7494static void
7495print_mve_shift_n (struct disassemble_info *info, long given,
7496 enum mve_instructions matched_insn)
7497{
7498 void *stream = info->stream;
7499 fprintf_ftype func = info->fprintf_func;
7500
7501 int startAt0
7502 = matched_insn == MVE_VQSHL_T2
7503 || matched_insn == MVE_VQSHLU_T3
7504 || matched_insn == MVE_VSHL_T1
7505 || matched_insn == MVE_VSHLL_T1
7506 || matched_insn == MVE_VSLI;
7507
7508 unsigned imm6 = (given & 0x3f0000) >> 16;
7509
7510 if (matched_insn == MVE_VSHLL_T1)
7511 imm6 &= 0x1f;
7512
7513 unsigned shiftAmount = 0;
7514 if ((imm6 & 0x20) != 0)
7515 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7516 else if ((imm6 & 0x10) != 0)
7517 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7518 else if ((imm6 & 0x08) != 0)
7519 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7520 else
7521 print_mve_undefined (info, UNDEF_SIZE_0);
7522
7523 func (stream, "%u", shiftAmount);
7524}
7525
143275ea
AV		 7526static void
7527print_vec_condition (struct disassemble_info *info, long given,
7528 enum mve_instructions matched_insn)
7529{
7530 void *stream = info->stream;
7531 fprintf_ftype func = info->fprintf_func;
7532 long vec_cond = 0;
7533
7534 switch (matched_insn)
7535 {
7536 case MVE_VPT_FP_T1:
7537 case MVE_VCMP_FP_T1:
7538 vec_cond = (((given & 0x1000) >> 10)
7539 | ((given & 1) << 1)
7540 | ((given & 0x0080) >> 7));
7541 func (stream, "%s",vec_condnames[vec_cond]);
7542 break;
7543
7544 case MVE_VPT_FP_T2:
7545 case MVE_VCMP_FP_T2:
7546 vec_cond = (((given & 0x1000) >> 10)
7547 | ((given & 0x0020) >> 4)
7548 | ((given & 0x0080) >> 7));
7549 func (stream, "%s",vec_condnames[vec_cond]);
7550 break;
7551
7552 case MVE_VPT_VEC_T1:
7553 case MVE_VCMP_VEC_T1:
7554 vec_cond = (given & 0x0080) >> 7;
7555 func (stream, "%s",vec_condnames[vec_cond]);
7556 break;
7557
7558 case MVE_VPT_VEC_T2:
7559 case MVE_VCMP_VEC_T2:
7560 vec_cond = 2 | ((given & 0x0080) >> 7);
7561 func (stream, "%s",vec_condnames[vec_cond]);
7562 break;
7563
7564 case MVE_VPT_VEC_T3:
7565 case MVE_VCMP_VEC_T3:
7566 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7567 func (stream, "%s",vec_condnames[vec_cond]);
7568 break;
7569
7570 case MVE_VPT_VEC_T4:
7571 case MVE_VCMP_VEC_T4:
7572 vec_cond = (given & 0x0080) >> 7;
7573 func (stream, "%s",vec_condnames[vec_cond]);
7574 break;
7575
7576 case MVE_VPT_VEC_T5:
7577 case MVE_VCMP_VEC_T5:
7578 vec_cond = 2 | ((given & 0x0080) >> 7);
7579 func (stream, "%s",vec_condnames[vec_cond]);
7580 break;
7581
7582 case MVE_VPT_VEC_T6:
7583 case MVE_VCMP_VEC_T6:
7584 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7585 func (stream, "%s",vec_condnames[vec_cond]);
7586 break;
7587
7588 case MVE_NONE:
7589 case MVE_VPST:
7590 default:
7591 break;
7592 }
7593}
7594
7595#define W_BIT 21
7596#define I_BIT 22
7597#define U_BIT 23
7598#define P_BIT 24
7599
7600#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7601#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7602#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7603#define PRE_BIT_SET (given & (1 << P_BIT))
7604
7605
8f06b2d8
PB		 7606/* Print one coprocessor instruction on INFO->STREAM.
7607 Return TRUE if the instuction matched, FALSE if this is not a
7608 recognised coprocessor instruction. */
7609
7610static bfd_boolean
fe56b6ce
NC		 7611print_insn_coprocessor (bfd_vma pc,
7612 struct disassemble_info *info,
7613 long given,
8f06b2d8
PB		 7614 bfd_boolean thumb)
7615{
6b0dd094 7616 const struct sopcode32 *insn;
8f06b2d8
PB		 7617 void *stream = info->stream;
7618 fprintf_ftype func = info->fprintf_func;
7619 unsigned long mask;
2edcd244 7620 unsigned long value = 0;
c22aaad1 7621 int cond;
8afc7bea 7622 int cp_num;
823d2571
TG		 7623 struct arm_private_data *private_data = info->private_data;
7624 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7625 arm_feature_set arm_ext_v8_1m_main =
7626 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7627
5b616bef 7628 allowed_arches = private_data->features;
8f06b2d8
PB		 7629
7630 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7631 {
ff4a8d2b
NC		 7632 unsigned long u_reg = 16;
7633 bfd_boolean is_unpredictable = FALSE;
05413229 7634 signed long value_in_comment = 0;
0313a2b8
NC		 7635 const char *c;
7636
823d2571 7637 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7638 switch (insn->value)
7639 {
7640 case SENTINEL_IWMMXT_START:
7641 if (info->mach != bfd_mach_arm_XScale
7642 && info->mach != bfd_mach_arm_iWMMXt
7643 && info->mach != bfd_mach_arm_iWMMXt2)
7644 do
7645 insn++;
823d2571
TG		 7646 while ((! ARM_FEATURE_ZERO (insn->arch))
7647 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7648 continue;
7649
7650 case SENTINEL_IWMMXT_END:
7651 continue;
7652
7653 case SENTINEL_GENERIC_START:
5b616bef 7654 allowed_arches = private_data->features;
05413229
NC		 7655 continue;
7656
7657 default:
7658 abort ();
7659 }
8f06b2d8
PB		 7660
7661 mask = insn->mask;
7662 value = insn->value;
8afc7bea
RL		 7663 cp_num = (given >> 8) & 0xf;
7664
8f06b2d8
PB		 7665 if (thumb)
7666 {
7667 /* The high 4 bits are 0xe for Arm conditional instructions, and
7668 0xe for arm unconditional instructions. The rest of the
7669 encoding is the same. */
7670 mask |= 0xf0000000;
7671 value |= 0xe0000000;
c22aaad1
PB		 7672 if (ifthen_state)
7673 cond = IFTHEN_COND;
7674 else
e2efe87d 7675 cond = COND_UNCOND;
8f06b2d8
PB		 7676 }
7677 else
7678 {
7679 /* Only match unconditional instuctions against unconditional
7680 patterns. */
7681 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 7682 {
7683 mask |= 0xf0000000;
e2efe87d 7684 cond = COND_UNCOND;
c22aaad1
PB		 7685 }
7686 else
7687 {
7688 cond = (given >> 28) & 0xf;
7689 if (cond == 0xe)
e2efe87d 7690 cond = COND_UNCOND;
c22aaad1 7691 }
8f06b2d8 7692 }
823d2571 7693
6b0dd094
AV		 7694 if ((insn->isa == T32 && !thumb)
7695 || (insn->isa == ARM && thumb))
7696 continue;
7697
0313a2b8
NC		 7698 if ((given & mask) != value)
7699 continue;
8f06b2d8 7700
823d2571 7701 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 7702 continue;
7703
8afc7bea
RL		 7704 if (insn->value == 0xfe000010 /* mcr2 */
7705 || insn->value == 0xfe100010 /* mrc2 */
7706 || insn->value == 0xfc100000 /* ldc2 */
7707 || insn->value == 0xfc000000) /* stc2 */
7708 {
b0c11777 7709 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7710 is_unpredictable = TRUE;
f08d8ce3
AV		 7711
7712 /* Armv8.1-M Mainline FP & MVE instructions. */
7713 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7714 && !ARM_CPU_IS_ANY (allowed_arches)
7715 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7716 continue;
7717
8afc7bea
RL		 7718 }
7719 else if (insn->value == 0x0e000000 /* cdp */
7720 || insn->value == 0xfe000000 /* cdp2 */
7721 || insn->value == 0x0e000010 /* mcr */
7722 || insn->value == 0x0e100010 /* mrc */
7723 || insn->value == 0x0c100000 /* ldc */
7724 || insn->value == 0x0c000000) /* stc */
7725 {
7726 /* Floating-point instructions. */
b0c11777 7727 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7728 continue;
32c36c3c
AV		 7729
7730 /* Armv8.1-M Mainline FP & MVE instructions. */
7731 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7732 && !ARM_CPU_IS_ANY (allowed_arches)
7733 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7734 continue;
8afc7bea 7735 }
aef6d006
AV		 7736 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7737 || insn->value == 0xec000f80) /* vstr (system register) */
7738 && arm_decode_field (given, 24, 24) == 0
7739 && arm_decode_field (given, 21, 21) == 0)
7740 /* If the P and W bits are both 0 then these encodings match the MVE
7741 VLDR and VSTR instructions, these are in a different table, so we
7742 don't let it match here. */
7743 continue;
7744
0313a2b8
NC		 7745 for (c = insn->assembler; *c; c++)
7746 {
7747 if (*c == '%')
8f06b2d8 7748 {
32c36c3c
AV		 7749 const char mod = *++c;
7750 switch (mod)
8f06b2d8 7751 {
0313a2b8
NC		 7752 case '%':
7753 func (stream, "%%");
7754 break;
7755
7756 case 'A':
32c36c3c 7757 case 'K':
05413229 7758 {
79862e45 7759 int rn = (given >> 16) & 0xf;
b0c11777 7760 bfd_vma offset = given & 0xff;
0313a2b8 7761
32c36c3c
AV		 7762 if (mod == 'K')
7763 offset = given & 0x7f;
7764
05413229 7765 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 7766
79862e45
DJ		 7767 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7768 {
7769 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 7770 if (cp_num == 9)
7771 /* vldr.16/vstr.16 will shift the address
7772 left by 1 bit only. */
7773 offset = offset * 2;
7774 else
7775 offset = offset * 4;
7776
79862e45
DJ		 7777 if (NEGATIVE_BIT_SET)
7778 offset = - offset;
7779 if (rn != 15)
7780 value_in_comment = offset;
7781 }
7782
c1e26897 7783 if (PRE_BIT_SET)
05413229
NC		 7784 {
7785 if (offset)
fe56b6ce 7786 func (stream, ", #%d]%s",
d908c8af 7787 (int) offset,
c1e26897 7788 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 7789 else if (NEGATIVE_BIT_SET)
7790 func (stream, ", #-0]");
05413229
NC		 7791 else
7792 func (stream, "]");
7793 }
7794 else
7795 {
0313a2b8 7796 func (stream, "]");
8f06b2d8 7797
c1e26897 7798 if (WRITEBACK_BIT_SET)
05413229
NC		 7799 {
7800 if (offset)
d908c8af 7801 func (stream, ", #%d", (int) offset);
26d97720
NS		 7802 else if (NEGATIVE_BIT_SET)
7803 func (stream, ", #-0");
05413229
NC		 7804 }
7805 else
fe56b6ce 7806 {
26d97720
NS		 7807 func (stream, ", {%s%d}",
7808 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 7809 (int) offset);
fe56b6ce
NC		 7810 value_in_comment = offset;
7811 }
05413229 7812 }
79862e45
DJ		 7813 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7814 {
7815 func (stream, "\t; ");
6844b2c2
MGD		 7816 /* For unaligned PCs, apply off-by-alignment
7817 correction. */
43e65147 7818 info->print_address_func (offset + pc
6844b2c2
MGD		 7819 + info->bytes_per_chunk * 2
7820 - (pc & 3),
dffaa15c 7821 info);
79862e45 7822 }
05413229 7823 }
0313a2b8 7824 break;
8f06b2d8 7825
0313a2b8
NC		 7826 case 'B':
7827 {
7828 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7829 int offset = (given >> 1) & 0x3f;
7830
7831 if (offset == 1)
7832 func (stream, "{d%d}", regno);
7833 else if (regno + offset > 32)
7834 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
7835 else
7836 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
7837 }
7838 break;
8f06b2d8 7839
efd6b359
AV		 7840 case 'C':
7841 {
7842 bfd_boolean single = ((given >> 8) & 1) == 0;
7843 char reg_prefix = single ? 's' : 'd';
7844 int Dreg = (given >> 22) & 0x1;
7845 int Vdreg = (given >> 12) & 0xf;
7846 int reg = single ? ((Vdreg << 1) | Dreg)
7847 : ((Dreg << 4) | Vdreg);
7848 int num = (given >> (single ? 0 : 1)) & 0x7f;
7849 int maxreg = single ? 31 : 15;
7850 int topreg = reg + num - 1;
7851
7852 if (!num)
7853 func (stream, "{VPR}");
7854 else if (num == 1)
7855 func (stream, "{%c%d, VPR}", reg_prefix, reg);
7856 else if (topreg > maxreg)
7857 func (stream, "{%c%d-<overflow reg d%d, VPR}",
7858 reg_prefix, reg, single ? topreg >> 1 : topreg);
7859 else
7860 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
7861 reg_prefix, topreg);
7862 }
7863 break;
7864
e2efe87d
MGD		 7865 case 'u':
7866 if (cond != COND_UNCOND)
7867 is_unpredictable = TRUE;
7868
7869 /* Fall through. */
0313a2b8 7870 case 'c':
b0c11777
RL		 7871 if (cond != COND_UNCOND && cp_num == 9)
7872 is_unpredictable = TRUE;
7873
0313a2b8
NC		 7874 func (stream, "%s", arm_conditional[cond]);
7875 break;
8f06b2d8 7876
0313a2b8
NC		 7877 case 'I':
7878 /* Print a Cirrus/DSP shift immediate. */
7879 /* Immediates are 7bit signed ints with bits 0..3 in
7880 bits 0..3 of opcode and bits 4..6 in bits 5..7
7881 of opcode. */
7882 {
7883 int imm;
8f06b2d8 7884
0313a2b8 7885 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 7886
0313a2b8
NC		 7887 /* Is ``imm'' a negative number? */
7888 if (imm & 0x40)
24b4cf66 7889 imm -= 0x80;
8f06b2d8 7890
0313a2b8
NC		 7891 func (stream, "%d", imm);
7892 }
7893
7894 break;
8f06b2d8 7895
32c36c3c
AV		 7896 case 'J':
7897 {
73cd51e5
AV		 7898 unsigned long regno
7899 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 7900
7901 switch (regno)
7902 {
7903 case 0x1:
7904 func (stream, "FPSCR");
7905 break;
7906 case 0x2:
7907 func (stream, "FPSCR_nzcvqc");
7908 break;
7909 case 0xc:
7910 func (stream, "VPR");
7911 break;
7912 case 0xd:
7913 func (stream, "P0");
7914 break;
7915 case 0xe:
7916 func (stream, "FPCXTNS");
7917 break;
7918 case 0xf:
7919 func (stream, "FPCXTS");
7920 break;
7921 default:
73cd51e5 7922 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 7923 break;
7924 }
7925 }
7926 break;
7927
0313a2b8
NC		 7928 case 'F':
7929 switch (given & 0x00408000)
7930 {
7931 case 0:
7932 func (stream, "4");
7933 break;
7934 case 0x8000:
7935 func (stream, "1");
7936 break;
7937 case 0x00400000:
7938 func (stream, "2");
8f06b2d8 7939 break;
0313a2b8
NC		 7940 default:
7941 func (stream, "3");
7942 }
7943 break;
8f06b2d8 7944
0313a2b8
NC		 7945 case 'P':
7946 switch (given & 0x00080080)
7947 {
7948 case 0:
7949 func (stream, "s");
7950 break;
7951 case 0x80:
7952 func (stream, "d");
7953 break;
7954 case 0x00080000:
7955 func (stream, "e");
7956 break;
7957 default:
7958 func (stream, _("<illegal precision>"));
8f06b2d8 7959 break;
0313a2b8
NC		 7960 }
7961 break;
8f06b2d8 7962
0313a2b8
NC		 7963 case 'Q':
7964 switch (given & 0x00408000)
7965 {
7966 case 0:
7967 func (stream, "s");
8f06b2d8 7968 break;
0313a2b8
NC		 7969 case 0x8000:
7970 func (stream, "d");
8f06b2d8 7971 break;
0313a2b8
NC		 7972 case 0x00400000:
7973 func (stream, "e");
7974 break;
7975 default:
7976 func (stream, "p");
8f06b2d8 7977 break;
0313a2b8
NC		 7978 }
7979 break;
8f06b2d8 7980
0313a2b8
NC		 7981 case 'R':
7982 switch (given & 0x60)
7983 {
7984 case 0:
7985 break;
7986 case 0x20:
7987 func (stream, "p");
7988 break;
7989 case 0x40:
7990 func (stream, "m");
7991 break;
7992 default:
7993 func (stream, "z");
7994 break;
7995 }
7996 break;
16980d0b 7997
0313a2b8
NC		 7998 case '0': case '1': case '2': case '3': case '4':
7999 case '5': case '6': case '7': case '8': case '9':
8000 {
8001 int width;
8f06b2d8 8002
0313a2b8 8003 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8004
0313a2b8
NC		 8005 switch (*c)
8006 {
ff4a8d2b
NC		 8007 case 'R':
8008 if (value == 15)
8009 is_unpredictable = TRUE;
8010 /* Fall through. */
0313a2b8 8011 case 'r':
ff4a8d2b
NC		 8012 if (c[1] == 'u')
8013 {
8014 /* Eat the 'u' character. */
8015 ++ c;
8016
8017 if (u_reg == value)
8018 is_unpredictable = TRUE;
8019 u_reg = value;
8020 }
0313a2b8
NC		 8021 func (stream, "%s", arm_regnames[value]);
8022 break;
c28eeff2
SN		 8023 case 'V':
8024 if (given & (1 << 6))
8025 goto Q;
8026 /* FALLTHROUGH */
0313a2b8
NC		 8027 case 'D':
8028 func (stream, "d%ld", value);
8029 break;
8030 case 'Q':
c28eeff2 8031 Q:
0313a2b8
NC		 8032 if (value & 1)
8033 func (stream, "<illegal reg q%ld.5>", value >> 1);
8034 else
8035 func (stream, "q%ld", value >> 1);
8036 break;
8037 case 'd':
8038 func (stream, "%ld", value);
05413229 8039 value_in_comment = value;
0313a2b8 8040 break;
6f1c2142
AM		 8041 case 'E':
8042 {
8043 /* Converts immediate 8 bit back to float value. */
8044 unsigned floatVal = (value & 0x80) << 24
8045 | (value & 0x3F) << 19
8046 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8047
8048 /* Quarter float have a maximum value of 31.0.
8049 Get floating point value multiplied by 1e7.
8050 The maximum value stays in limit of a 32-bit int. */
8051 unsigned decVal =
8052 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8053 (16 + (value & 0xF));
8054
8055 if (!(decVal % 1000000))
8056 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8057 floatVal, value & 0x80 ? '-' : ' ',
8058 decVal / 10000000,
8059 decVal % 10000000 / 1000000);
8060 else if (!(decVal % 10000))
8061 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8062 floatVal, value & 0x80 ? '-' : ' ',
8063 decVal / 10000000,
8064 decVal % 10000000 / 10000);
8065 else
8066 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8067 floatVal, value & 0x80 ? '-' : ' ',
8068 decVal / 10000000, decVal % 10000000);
8069 break;
8070 }
0313a2b8
NC		 8071 case 'k':
8072 {
8073 int from = (given & (1 << 7)) ? 32 : 16;
8074 func (stream, "%ld", from - value);
8075 }
8076 break;
8f06b2d8 8077
0313a2b8
NC		 8078 case 'f':
8079 if (value > 7)
8080 func (stream, "#%s", arm_fp_const[value & 7]);
8081 else
8082 func (stream, "f%ld", value);
8083 break;
4146fd53 8084
0313a2b8
NC		 8085 case 'w':
8086 if (width == 2)
8087 func (stream, "%s", iwmmxt_wwnames[value]);
8088 else
8089 func (stream, "%s", iwmmxt_wwssnames[value]);
8090 break;
4146fd53 8091
0313a2b8
NC		 8092 case 'g':
8093 func (stream, "%s", iwmmxt_regnames[value]);
8094 break;
8095 case 'G':
8096 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8097 break;
8f06b2d8 8098
0313a2b8 8099 case 'x':
d1aaab3c 8100 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8101 break;
8f06b2d8 8102
33399f07
MGD		 8103 case 'c':
8104 switch (value)
8105 {
8106 case 0:
8107 func (stream, "eq");
8108 break;
8109
8110 case 1:
8111 func (stream, "vs");
8112 break;
8113
8114 case 2:
8115 func (stream, "ge");
8116 break;
8117
8118 case 3:
8119 func (stream, "gt");
8120 break;
8121
8122 default:
8123 func (stream, "??");
8124 break;
8125 }
8126 break;
8127
0313a2b8
NC		 8128 case '`':
8129 c++;
8130 if (value == 0)
8131 func (stream, "%c", *c);
8132 break;
8133 case '\'':
8134 c++;
8135 if (value == ((1ul << width) - 1))
8136 func (stream, "%c", *c);
8137 break;
8138 case '?':
fe56b6ce 8139 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8140 c += 1 << width;
8141 break;
8142 default:
8143 abort ();
8144 }
dffaa15c
AM		 8145 }
8146 break;
0313a2b8 8147
dffaa15c
AM		 8148 case 'y':
8149 case 'z':
8150 {
8151 int single = *c++ == 'y';
8152 int regno;
8f06b2d8 8153
dffaa15c
AM		 8154 switch (*c)
8155 {
8156 case '4': /* Sm pair */
8157 case '0': /* Sm, Dm */
8158 regno = given & 0x0000000f;
8159 if (single)
8160 {
8161 regno <<= 1;
8162 regno += (given >> 5) & 1;
8163 }
8164 else
8165 regno += ((given >> 5) & 1) << 4;
8166 break;
8f06b2d8 8167
dffaa15c
AM		 8168 case '1': /* Sd, Dd */
8169 regno = (given >> 12) & 0x0000000f;
8170 if (single)
8171 {
8172 regno <<= 1;
8173 regno += (given >> 22) & 1;
8174 }
8175 else
8176 regno += ((given >> 22) & 1) << 4;
8177 break;
7df76b80 8178
dffaa15c
AM		 8179 case '2': /* Sn, Dn */
8180 regno = (given >> 16) & 0x0000000f;
8181 if (single)
8182 {
8183 regno <<= 1;
8184 regno += (given >> 7) & 1;
8185 }
8186 else
8187 regno += ((given >> 7) & 1) << 4;
8188 break;
a7f8487e 8189
dffaa15c
AM		 8190 case '3': /* List */
8191 func (stream, "{");
8192 regno = (given >> 12) & 0x0000000f;
8193 if (single)
8194 {
8195 regno <<= 1;
8196 regno += (given >> 22) & 1;
8197 }
8198 else
8199 regno += ((given >> 22) & 1) << 4;
8200 break;
a7f8487e 8201
dffaa15c
AM		 8202 default:
8203 abort ();
8204 }
0313a2b8 8205
dffaa15c 8206 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8207
dffaa15c
AM		 8208 if (*c == '3')
8209 {
8210 int count = given & 0xff;
b34976b6 8211
dffaa15c
AM		 8212 if (single == 0)
8213 count >>= 1;
0313a2b8 8214
dffaa15c
AM		 8215 if (--count)
8216 {
8217 func (stream, "-%c%d",
8218 single ? 's' : 'd',
8219 regno + count);
8220 }
0313a2b8 8221
dffaa15c 8222 func (stream, "}");
0313a2b8 8223 }
dffaa15c
AM		 8224 else if (*c == '4')
8225 func (stream, ", %c%d", single ? 's' : 'd',
8226 regno + 1);
8227 }
8228 break;
b34976b6 8229
dffaa15c
AM		 8230 case 'L':
8231 switch (given & 0x00400100)
0313a2b8 8232 {
dffaa15c
AM		 8233 case 0x00000000: func (stream, "b"); break;
8234 case 0x00400000: func (stream, "h"); break;
8235 case 0x00000100: func (stream, "w"); break;
8236 case 0x00400100: func (stream, "d"); break;
8237 default:
8238 break;
0313a2b8 8239 }
dffaa15c 8240 break;
2d447fca 8241
dffaa15c
AM		 8242 case 'Z':
8243 {
8244 /* given (20, 23) | given (0, 3) */
8245 value = ((given >> 16) & 0xf0) | (given & 0xf);
8246 func (stream, "%d", (int) value);
8247 }
8248 break;
0313a2b8 8249
dffaa15c
AM		 8250 case 'l':
8251 /* This is like the 'A' operator, except that if
8252 the width field "M" is zero, then the offset is
8253 *not* multiplied by four. */
8254 {
8255 int offset = given & 0xff;
8256 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8257
dffaa15c 8258 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8259
dffaa15c
AM		 8260 if (multiplier > 1)
8261 {
8262 value_in_comment = offset * multiplier;
8263 if (NEGATIVE_BIT_SET)
8264 value_in_comment = - value_in_comment;
8265 }
0313a2b8 8266
dffaa15c
AM		 8267 if (offset)
8268 {
8269 if (PRE_BIT_SET)
8270 func (stream, ", #%s%d]%s",
8271 NEGATIVE_BIT_SET ? "-" : "",
8272 offset * multiplier,
8273 WRITEBACK_BIT_SET ? "!" : "");
8274 else
8275 func (stream, "], #%s%d",
8276 NEGATIVE_BIT_SET ? "-" : "",
8277 offset * multiplier);
8278 }
8279 else
8280 func (stream, "]");
8281 }
8282 break;
2d447fca 8283
dffaa15c
AM		 8284 case 'r':
8285 {
8286 int imm4 = (given >> 4) & 0xf;
8287 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8288 int ubit = ! NEGATIVE_BIT_SET;
8289 const char *rm = arm_regnames [given & 0xf];
8290 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8291
dffaa15c
AM		 8292 switch (puw_bits)
8293 {
8294 case 1:
8295 case 3:
8296 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8297 if (imm4)
8298 func (stream, ", lsl #%d", imm4);
8299 break;
0313a2b8 8300
dffaa15c
AM		 8301 case 4:
8302 case 5:
8303 case 6:
8304 case 7:
8305 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8306 if (imm4 > 0)
8307 func (stream, ", lsl #%d", imm4);
8308 func (stream, "]");
8309 if (puw_bits == 5 || puw_bits == 7)
8310 func (stream, "!");
8311 break;
2d447fca 8312
dffaa15c
AM		 8313 default:
8314 func (stream, "INVALID");
8315 }
8316 }
8317 break;
0313a2b8 8318
dffaa15c
AM		 8319 case 'i':
8320 {
8321 long imm5;
8322 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8323 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8324 }
dffaa15c
AM		 8325 break;
8326
8327 default:
8328 abort ();
252b5132 8329 }
252b5132 8330 }
0313a2b8
NC		 8331 else
8332 func (stream, "%c", *c);
252b5132 8333 }
05413229
NC		 8334
8335 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8336 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8337
ff4a8d2b
NC		 8338 if (is_unpredictable)
8339 func (stream, UNPREDICTABLE_INSTRUCTION);
8340
0313a2b8 8341 return TRUE;
252b5132 8342 }
8f06b2d8 8343 return FALSE;
252b5132
RH		 8344}
8345
05413229
NC		 8346/* Decodes and prints ARM addressing modes. Returns the offset
8347 used in the address, if any, if it is worthwhile printing the
8348 offset as a hexadecimal value in a comment at the end of the
8349 line of disassembly. */
8350
8351static signed long
62b3e311
PB		 8352print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8353{
8354 void *stream = info->stream;
8355 fprintf_ftype func = info->fprintf_func;
f8b960bc 8356 bfd_vma offset = 0;
62b3e311
PB		 8357
8358 if (((given & 0x000f0000) == 0x000f0000)
8359 && ((given & 0x02000000) == 0))
8360 {
05413229 8361 offset = given & 0xfff;
62b3e311
PB		 8362
8363 func (stream, "[pc");
8364
c1e26897 8365 if (PRE_BIT_SET)
62b3e311 8366 {
26d97720
NS		 8367 /* Pre-indexed. Elide offset of positive zero when
8368 non-writeback. */
8369 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8370 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8371
8372 if (NEGATIVE_BIT_SET)
8373 offset = -offset;
62b3e311
PB		 8374
8375 offset += pc + 8;
8376
8377 /* Cope with the possibility of write-back
8378 being used. Probably a very dangerous thing
8379 for the programmer to do, but who are we to
8380 argue ? */
26d97720 8381 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8382 }
c1e26897 8383 else /* Post indexed. */
62b3e311 8384 {
d908c8af 8385 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8386
c1e26897 8387 /* Ie ignore the offset. */
62b3e311
PB		 8388 offset = pc + 8;
8389 }
8390
8391 func (stream, "\t; ");
8392 info->print_address_func (offset, info);
05413229 8393 offset = 0;
62b3e311
PB		 8394 }
8395 else
8396 {
8397 func (stream, "[%s",
8398 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8399
8400 if (PRE_BIT_SET)
62b3e311
PB		 8401 {
8402 if ((given & 0x02000000) == 0)
8403 {
26d97720 8404 /* Elide offset of positive zero when non-writeback. */
05413229 8405 offset = given & 0xfff;
26d97720 8406 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8407 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8408 }
8409 else
8410 {
26d97720 8411 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8412 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8413 }
8414
8415 func (stream, "]%s",
c1e26897 8416 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8417 }
8418 else
8419 {
8420 if ((given & 0x02000000) == 0)
8421 {
26d97720 8422 /* Always show offset. */
05413229 8423 offset = given & 0xfff;
26d97720 8424 func (stream, "], #%s%d",
d908c8af 8425 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8426 }
8427 else
8428 {
8429 func (stream, "], %s",
c1e26897 8430 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8431 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8432 }
8433 }
84919466
MR		 8434 if (NEGATIVE_BIT_SET)
8435 offset = -offset;
62b3e311 8436 }
05413229
NC		 8437
8438 return (signed long) offset;
62b3e311
PB		 8439}
8440
16980d0b
JB		 8441/* Print one neon instruction on INFO->STREAM.
8442 Return TRUE if the instuction matched, FALSE if this is not a
8443 recognised neon instruction. */
8444
8445static bfd_boolean
8446print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8447{
8448 const struct opcode32 *insn;
8449 void *stream = info->stream;
8450 fprintf_ftype func = info->fprintf_func;
8451
8452 if (thumb)
8453 {
8454 if ((given & 0xef000000) == 0xef000000)
8455 {
0313a2b8 8456 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8457 unsigned long bit28 = given & (1 << 28);
8458
8459 given &= 0x00ffffff;
8460 if (bit28)
8461 given |= 0xf3000000;
8462 else
8463 given |= 0xf2000000;
8464 }
8465 else if ((given & 0xff000000) == 0xf9000000)
8466 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 8467 /* vdup is also a valid neon instruction. */
8468 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8469 return FALSE;
8470 }
43e65147 8471
16980d0b
JB		 8472 for (insn = neon_opcodes; insn->assembler; insn++)
8473 {
8474 if ((given & insn->mask) == insn->value)
8475 {
05413229 8476 signed long value_in_comment = 0;
e2efe87d 8477 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 8478 const char *c;
8479
8480 for (c = insn->assembler; *c; c++)
8481 {
8482 if (*c == '%')
8483 {
8484 switch (*++c)
8485 {
8486 case '%':
8487 func (stream, "%%");
8488 break;
8489
e2efe87d
MGD		 8490 case 'u':
8491 if (thumb && ifthen_state)
8492 is_unpredictable = TRUE;
8493
8494 /* Fall through. */
c22aaad1
PB		 8495 case 'c':
8496 if (thumb && ifthen_state)
8497 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8498 break;
8499
16980d0b
JB		 8500 case 'A':
8501 {
43e65147 8502 static const unsigned char enc[16] =
16980d0b
JB		 8503 {
8504 0x4, 0x14, /* st4 0,1 */
8505 0x4, /* st1 2 */
8506 0x4, /* st2 3 */
8507 0x3, /* st3 4 */
8508 0x13, /* st3 5 */
8509 0x3, /* st1 6 */
8510 0x1, /* st1 7 */
8511 0x2, /* st2 8 */
8512 0x12, /* st2 9 */
8513 0x2, /* st1 10 */
8514 0, 0, 0, 0, 0
8515 };
8516 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8517 int rn = ((given >> 16) & 0xf);
8518 int rm = ((given >> 0) & 0xf);
8519 int align = ((given >> 4) & 0x3);
8520 int type = ((given >> 8) & 0xf);
8521 int n = enc[type] & 0xf;
8522 int stride = (enc[type] >> 4) + 1;
8523 int ix;
43e65147 8524
16980d0b
JB		 8525 func (stream, "{");
8526 if (stride > 1)
8527 for (ix = 0; ix != n; ix++)
8528 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8529 else if (n == 1)
8530 func (stream, "d%d", rd);
8531 else
8532 func (stream, "d%d-d%d", rd, rd + n - 1);
8533 func (stream, "}, [%s", arm_regnames[rn]);
8534 if (align)
8e560766 8535 func (stream, " :%d", 32 << align);
16980d0b
JB		 8536 func (stream, "]");
8537 if (rm == 0xd)
8538 func (stream, "!");
8539 else if (rm != 0xf)
8540 func (stream, ", %s", arm_regnames[rm]);
8541 }
8542 break;
43e65147 8543
16980d0b
JB		 8544 case 'B':
8545 {
8546 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8547 int rn = ((given >> 16) & 0xf);
8548 int rm = ((given >> 0) & 0xf);
8549 int idx_align = ((given >> 4) & 0xf);
8550 int align = 0;
8551 int size = ((given >> 10) & 0x3);
8552 int idx = idx_align >> (size + 1);
8553 int length = ((given >> 8) & 3) + 1;
8554 int stride = 1;
8555 int i;
8556
8557 if (length > 1 && size > 0)
8558 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 8559
16980d0b
JB		 8560 switch (length)
8561 {
8562 case 1:
8563 {
8564 int amask = (1 << size) - 1;
8565 if ((idx_align & (1 << size)) != 0)
8566 return FALSE;
8567 if (size > 0)
8568 {
8569 if ((idx_align & amask) == amask)
8570 align = 8 << size;
8571 else if ((idx_align & amask) != 0)
8572 return FALSE;
8573 }
8574 }
8575 break;
43e65147 8576
16980d0b
JB		 8577 case 2:
8578 if (size == 2 && (idx_align & 2) != 0)
8579 return FALSE;
8580 align = (idx_align & 1) ? 16 << size : 0;
8581 break;
43e65147 8582
16980d0b
JB		 8583 case 3:
8584 if ((size == 2 && (idx_align & 3) != 0)
8585 || (idx_align & 1) != 0)
8586 return FALSE;
8587 break;
43e65147 8588
16980d0b
JB		 8589 case 4:
8590 if (size == 2)
8591 {
8592 if ((idx_align & 3) == 3)
8593 return FALSE;
8594 align = (idx_align & 3) * 64;
8595 }
8596 else
8597 align = (idx_align & 1) ? 32 << size : 0;
8598 break;
43e65147 8599
16980d0b
JB		 8600 default:
8601 abort ();
8602 }
43e65147 8603
16980d0b
JB		 8604 func (stream, "{");
8605 for (i = 0; i < length; i++)
8606 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8607 rd + i * stride, idx);
8608 func (stream, "}, [%s", arm_regnames[rn]);
8609 if (align)
8e560766 8610 func (stream, " :%d", align);
16980d0b
JB		 8611 func (stream, "]");
8612 if (rm == 0xd)
8613 func (stream, "!");
8614 else if (rm != 0xf)
8615 func (stream, ", %s", arm_regnames[rm]);
8616 }
8617 break;
43e65147 8618
16980d0b
JB		 8619 case 'C':
8620 {
8621 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8622 int rn = ((given >> 16) & 0xf);
8623 int rm = ((given >> 0) & 0xf);
8624 int align = ((given >> 4) & 0x1);
8625 int size = ((given >> 6) & 0x3);
8626 int type = ((given >> 8) & 0x3);
8627 int n = type + 1;
8628 int stride = ((given >> 5) & 0x1);
8629 int ix;
43e65147 8630
16980d0b
JB		 8631 if (stride && (n == 1))
8632 n++;
8633 else
8634 stride++;
43e65147 8635
16980d0b
JB		 8636 func (stream, "{");
8637 if (stride > 1)
8638 for (ix = 0; ix != n; ix++)
8639 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8640 else if (n == 1)
8641 func (stream, "d%d[]", rd);
8642 else
8643 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8644 func (stream, "}, [%s", arm_regnames[rn]);
8645 if (align)
8646 {
91d6fa6a 8647 align = (8 * (type + 1)) << size;
16980d0b
JB		 8648 if (type == 3)
8649 align = (size > 1) ? align >> 1 : align;
8650 if (type == 2 || (type == 0 && !size))
8e560766 8651 func (stream, " :<bad align %d>", align);
16980d0b 8652 else
8e560766 8653 func (stream, " :%d", align);
16980d0b
JB		 8654 }
8655 func (stream, "]");
8656 if (rm == 0xd)
8657 func (stream, "!");
8658 else if (rm != 0xf)
8659 func (stream, ", %s", arm_regnames[rm]);
8660 }
8661 break;
43e65147 8662
16980d0b
JB		 8663 case 'D':
8664 {
8665 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8666 int size = (given >> 20) & 3;
8667 int reg = raw_reg & ((4 << size) - 1);
8668 int ix = raw_reg >> size >> 2;
43e65147 8669
16980d0b
JB		 8670 func (stream, "d%d[%d]", reg, ix);
8671 }
8672 break;
43e65147 8673
16980d0b 8674 case 'E':
fe56b6ce 8675 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 8676 {
8677 int bits = 0;
8678 int cmode = (given >> 8) & 0xf;
8679 int op = (given >> 5) & 0x1;
8680 unsigned long value = 0, hival = 0;
8681 unsigned shift;
8682 int size = 0;
0dbde4cf 8683 int isfloat = 0;
43e65147 8684
16980d0b
JB		 8685 bits |= ((given >> 24) & 1) << 7;
8686 bits |= ((given >> 16) & 7) << 4;
8687 bits |= ((given >> 0) & 15) << 0;
43e65147 8688
16980d0b
JB		 8689 if (cmode < 8)
8690 {
8691 shift = (cmode >> 1) & 3;
fe56b6ce 8692 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8693 size = 32;
8694 }
8695 else if (cmode < 12)
8696 {
8697 shift = (cmode >> 1) & 1;
fe56b6ce 8698 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8699 size = 16;
8700 }
8701 else if (cmode < 14)
8702 {
8703 shift = (cmode & 1) + 1;
fe56b6ce 8704 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8705 value |= (1ul << (8 * shift)) - 1;
8706 size = 32;
8707 }
8708 else if (cmode == 14)
8709 {
8710 if (op)
8711 {
fe56b6ce 8712 /* Bit replication into bytes. */
16980d0b
JB		 8713 int ix;
8714 unsigned long mask;
43e65147 8715
16980d0b
JB		 8716 value = 0;
8717 hival = 0;
8718 for (ix = 7; ix >= 0; ix--)
8719 {
8720 mask = ((bits >> ix) & 1) ? 0xff : 0;
8721 if (ix <= 3)
8722 value = (value << 8) | mask;
8723 else
8724 hival = (hival << 8) | mask;
8725 }
8726 size = 64;
8727 }
8728 else
8729 {
fe56b6ce
NC		 8730 /* Byte replication. */
8731 value = (unsigned long) bits;
16980d0b
JB		 8732 size = 8;
8733 }
8734 }
8735 else if (!op)
8736 {
fe56b6ce 8737 /* Floating point encoding. */
16980d0b 8738 int tmp;
43e65147 8739
fe56b6ce
NC		 8740 value = (unsigned long) (bits & 0x7f) << 19;
8741 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 8742 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 8743 value |= (unsigned long) tmp << 24;
16980d0b 8744 size = 32;
0dbde4cf 8745 isfloat = 1;
16980d0b
JB		 8746 }
8747 else
8748 {
8749 func (stream, "<illegal constant %.8x:%x:%x>",
8750 bits, cmode, op);
8751 size = 32;
8752 break;
8753 }
8754 switch (size)
8755 {
8756 case 8:
8757 func (stream, "#%ld\t; 0x%.2lx", value, value);
8758 break;
43e65147 8759
16980d0b
JB		 8760 case 16:
8761 func (stream, "#%ld\t; 0x%.4lx", value, value);
8762 break;
8763
8764 case 32:
0dbde4cf
JB		 8765 if (isfloat)
8766 {
8767 unsigned char valbytes[4];
8768 double fvalue;
43e65147 8769
0dbde4cf
JB		 8770 /* Do this a byte at a time so we don't have to
8771 worry about the host's endianness. */
8772 valbytes[0] = value & 0xff;
8773 valbytes[1] = (value >> 8) & 0xff;
8774 valbytes[2] = (value >> 16) & 0xff;
8775 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 8776
8777 floatformat_to_double
c1e26897
NC		 8778 (& floatformat_ieee_single_little, valbytes,
8779 & fvalue);
43e65147 8780
0dbde4cf
JB		 8781 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8782 value);
8783 }
8784 else
4e9d3b81 8785 func (stream, "#%ld\t; 0x%.8lx",
43e65147 8786 (long) (((value & 0x80000000L) != 0)
9d82ec38 8787 ? value | ~0xffffffffL : value),
c1e26897 8788 value);
16980d0b
JB		 8789 break;
8790
8791 case 64:
8792 func (stream, "#0x%.8lx%.8lx", hival, value);
8793 break;
43e65147 8794
16980d0b
JB		 8795 default:
8796 abort ();
8797 }
8798 }
8799 break;
43e65147 8800
16980d0b
JB		 8801 case 'F':
8802 {
8803 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8804 int num = (given >> 8) & 0x3;
43e65147 8805
16980d0b
JB		 8806 if (!num)
8807 func (stream, "{d%d}", regno);
8808 else if (num + regno >= 32)
8809 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8810 else
8811 func (stream, "{d%d-d%d}", regno, regno + num);
8812 }
8813 break;
7e8e6784 8814
16980d0b
JB		 8815
8816 case '0': case '1': case '2': case '3': case '4':
8817 case '5': case '6': case '7': case '8': case '9':
8818 {
8819 int width;
8820 unsigned long value;
8821
8822 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 8823
16980d0b
JB		 8824 switch (*c)
8825 {
8826 case 'r':
8827 func (stream, "%s", arm_regnames[value]);
8828 break;
8829 case 'd':
8830 func (stream, "%ld", value);
05413229 8831 value_in_comment = value;
16980d0b
JB		 8832 break;
8833 case 'e':
8834 func (stream, "%ld", (1ul << width) - value);
8835 break;
43e65147 8836
16980d0b
JB		 8837 case 'S':
8838 case 'T':
8839 case 'U':
05413229 8840 /* Various width encodings. */
16980d0b
JB		 8841 {
8842 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
8843 int limit;
8844 unsigned low, high;
8845
8846 c++;
8847 if (*c >= '0' && *c <= '9')
8848 limit = *c - '0';
8849 else if (*c >= 'a' && *c <= 'f')
8850 limit = *c - 'a' + 10;
8851 else
8852 abort ();
8853 low = limit >> 2;
8854 high = limit & 3;
8855
8856 if (value < low || value > high)
8857 func (stream, "<illegal width %d>", base << value);
8858 else
8859 func (stream, "%d", base << value);
8860 }
8861 break;
8862 case 'R':
8863 if (given & (1 << 6))
8864 goto Q;
8865 /* FALLTHROUGH */
8866 case 'D':
8867 func (stream, "d%ld", value);
8868 break;
8869 case 'Q':
8870 Q:
8871 if (value & 1)
8872 func (stream, "<illegal reg q%ld.5>", value >> 1);
8873 else
8874 func (stream, "q%ld", value >> 1);
8875 break;
43e65147 8876
16980d0b
JB		 8877 case '`':
8878 c++;
8879 if (value == 0)
8880 func (stream, "%c", *c);
8881 break;
8882 case '\'':
8883 c++;
8884 if (value == ((1ul << width) - 1))
8885 func (stream, "%c", *c);
8886 break;
8887 case '?':
fe56b6ce 8888 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 8889 c += 1 << width;
8890 break;
8891 default:
8892 abort ();
8893 }
16980d0b 8894 }
dffaa15c
AM		 8895 break;
8896
8897 default:
8898 abort ();
16980d0b
JB		 8899 }
8900 }
8901 else
8902 func (stream, "%c", *c);
8903 }
05413229
NC		 8904
8905 if (value_in_comment > 32 || value_in_comment < -16)
8906 func (stream, "\t; 0x%lx", value_in_comment);
8907
e2efe87d
MGD		 8908 if (is_unpredictable)
8909 func (stream, UNPREDICTABLE_INSTRUCTION);
8910
16980d0b
JB		 8911 return TRUE;
8912 }
8913 }
8914 return FALSE;
8915}
8916
73cd51e5
AV		 8917/* Print one mve instruction on INFO->STREAM.
8918 Return TRUE if the instuction matched, FALSE if this is not a
8919 recognised mve instruction. */
8920
8921static bfd_boolean
8922print_insn_mve (struct disassemble_info *info, long given)
8923{
8924 const struct mopcode32 *insn;
8925 void *stream = info->stream;
8926 fprintf_ftype func = info->fprintf_func;
8927
8928 for (insn = mve_opcodes; insn->assembler; insn++)
8929 {
8930 if (((given & insn->mask) == insn->value)
8931 && !is_mve_encoding_conflict (given, insn->mve_op))
8932 {
8933 signed long value_in_comment = 0;
8934 bfd_boolean is_unpredictable = FALSE;
8935 bfd_boolean is_undefined = FALSE;
8936 const char *c;
8937 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
8938 enum mve_undefined undefined_cond = UNDEF_NONE;
8939
8940 /* Most vector mve instruction are illegal in a it block.
8941 There are a few exceptions; check for them. */
8942 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
8943 {
8944 is_unpredictable = TRUE;
8945 unpredictable_cond = UNPRED_IT_BLOCK;
8946 }
8947 else if (is_mve_unpredictable (given, insn->mve_op,
8948 &unpredictable_cond))
8949 is_unpredictable = TRUE;
8950
8951 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
8952 is_undefined = TRUE;
8953
8954 for (c = insn->assembler; *c; c++)
8955 {
8956 if (*c == '%')
8957 {
8958 switch (*++c)
8959 {
8960 case '%':
8961 func (stream, "%%");
8962 break;
8963
ef1576a1
AV		 8964 case 'a':
8965 /* Don't print anything for '+' as it is implied. */
8966 if (arm_decode_field (given, 23, 23) == 0)
8967 func (stream, "-");
8968 break;
8969
143275ea
AV		 8970 case 'c':
8971 if (ifthen_state)
8972 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8973 break;
8974
aef6d006
AV		 8975 case 'd':
8976 print_mve_vld_str_addr (info, given, insn->mve_op);
8977 break;
8978
143275ea
AV		 8979 case 'i':
8980 {
8981 long mve_mask = mve_extract_pred_mask (given);
8982 func (stream, "%s", mve_predicatenames[mve_mask]);
8983 }
8984 break;
8985
8986 case 'n':
8987 print_vec_condition (info, given, insn->mve_op);
8988 break;
8989
ef1576a1
AV		 8990 case 'o':
8991 if (arm_decode_field (given, 0, 0) == 1)
8992 {
8993 unsigned long size
8994 = arm_decode_field (given, 4, 4)
8995 | (arm_decode_field (given, 6, 6) << 1);
8996
8997 func (stream, ", uxtw #%lu", size);
8998 }
8999 break;
9000
bf0b396d
AV		 9001 case 'm':
9002 print_mve_rounding_mode (info, given, insn->mve_op);
9003 break;
9004
9005 case 's':
9006 print_mve_vcvt_size (info, given, insn->mve_op);
9007 break;
9008
aef6d006
AV		 9009 case 'u':
9010 {
c507f10b
AV		 9011 unsigned long op1 = arm_decode_field (given, 21, 22);
9012
9013 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9014 {
9015 /* Check for signed. */
9016 if (arm_decode_field (given, 23, 23) == 0)
9017 {
9018 /* We don't print 's' for S32. */
9019 if ((arm_decode_field (given, 5, 6) == 0)
9020 && ((op1 == 0) || (op1 == 1)))
9021 ;
9022 else
9023 func (stream, "s");
9024 }
9025 else
9026 func (stream, "u");
9027 }
aef6d006 9028 else
c507f10b
AV		 9029 {
9030 if (arm_decode_field (given, 28, 28) == 0)
9031 func (stream, "s");
9032 else
9033 func (stream, "u");
9034 }
aef6d006 9035 }
ef1576a1 9036 break;
aef6d006 9037
143275ea
AV		 9038 case 'v':
9039 print_instruction_predicate (info);
9040 break;
9041
04d54ace
AV		 9042 case 'w':
9043 if (arm_decode_field (given, 21, 21) == 1)
9044 func (stream, "!");
9045 break;
9046
9047 case 'B':
9048 print_mve_register_blocks (info, given, insn->mve_op);
9049 break;
9050
c507f10b
AV		 9051 case 'E':
9052 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9053
9054 print_simd_imm8 (info, given, 28, insn);
9055 break;
9056
9057 case 'N':
9058 print_mve_vmov_index (info, given);
9059 break;
9060
14925797
AV		 9061 case 'T':
9062 if (arm_decode_field (given, 12, 12) == 0)
9063 func (stream, "b");
9064 else
9065 func (stream, "t");
9066 break;
9067
d3b63143
AV		 9068 case 'X':
9069 if (arm_decode_field (given, 12, 12) == 1)
9070 func (stream, "x");
9071 break;
9072
143275ea
AV		 9073 case '0': case '1': case '2': case '3': case '4':
9074 case '5': case '6': case '7': case '8': case '9':
9075 {
9076 int width;
9077 unsigned long value;
9078
9079 c = arm_decode_bitfield (c, given, &value, &width);
9080
9081 switch (*c)
9082 {
9083 case 'Z':
9084 if (value == 13)
9085 is_unpredictable = TRUE;
9086 else if (value == 15)
9087 func (stream, "zr");
9088 else
9089 func (stream, "%s", arm_regnames[value]);
9090 break;
9091 case 's':
9092 print_mve_size (info,
9093 value,
9094 insn->mve_op);
9095 break;
66dcaa5d
AV		 9096 case 'I':
9097 if (value == 1)
9098 func (stream, "i");
9099 break;
d3b63143
AV		 9100 case 'A':
9101 if (value == 1)
9102 func (stream, "a");
9103 break;
1c8f2df8
AV		 9104 case 'h':
9105 {
9106 unsigned int odd_reg = (value << 1) | 1;
9107 func (stream, "%s", arm_regnames[odd_reg]);
9108 }
9109 break;
ef1576a1
AV		 9110 case 'i':
9111 {
9112 unsigned long imm
9113 = arm_decode_field (given, 0, 6);
9114 unsigned long mod_imm = imm;
9115
9116 switch (insn->mve_op)
9117 {
9118 case MVE_VLDRW_GATHER_T5:
9119 case MVE_VSTRW_SCATTER_T5:
9120 mod_imm = mod_imm << 2;
9121 break;
9122 case MVE_VSTRD_SCATTER_T6:
9123 case MVE_VLDRD_GATHER_T6:
9124 mod_imm = mod_imm << 3;
9125 break;
9126
9127 default:
9128 break;
9129 }
9130
9131 func (stream, "%lu", mod_imm);
9132 }
9133 break;
bf0b396d
AV		 9134 case 'k':
9135 func (stream, "%lu", 64 - value);
9136 break;
1c8f2df8
AV		 9137 case 'l':
9138 {
9139 unsigned int even_reg = value << 1;
9140 func (stream, "%s", arm_regnames[even_reg]);
9141 }
9142 break;
9143 case 'u':
9144 switch (value)
9145 {
9146 case 0:
9147 func (stream, "1");
9148 break;
9149 case 1:
9150 func (stream, "2");
9151 break;
9152 case 2:
9153 func (stream, "4");
9154 break;
9155 case 3:
9156 func (stream, "8");
9157 break;
9158 default:
9159 break;
9160 }
9161 break;
897b9bbc
AV		 9162 case 'o':
9163 print_mve_rotate (info, value, width);
9164 break;
9743db03
AV		 9165 case 'r':
9166 func (stream, "%s", arm_regnames[value]);
9167 break;
04d54ace 9168 case 'd':
ed63aa17
AV		 9169 if (insn->mve_op == MVE_VQSHL_T2
9170 || insn->mve_op == MVE_VQSHLU_T3
9171 || insn->mve_op == MVE_VRSHR
9172 || insn->mve_op == MVE_VRSHRN
9173 || insn->mve_op == MVE_VSHL_T1
9174 || insn->mve_op == MVE_VSHLL_T1
9175 || insn->mve_op == MVE_VSHR
9176 || insn->mve_op == MVE_VSHRN
9177 || insn->mve_op == MVE_VSLI
9178 || insn->mve_op == MVE_VSRI)
9179 print_mve_shift_n (info, given, insn->mve_op);
9180 else if (insn->mve_op == MVE_VSHLL_T2)
9181 {
9182 switch (value)
9183 {
9184 case 0x00:
9185 func (stream, "8");
9186 break;
9187 case 0x01:
9188 func (stream, "16");
9189 break;
9190 case 0x10:
9191 print_mve_undefined (info, UNDEF_SIZE_0);
9192 break;
9193 default:
9194 assert (0);
9195 break;
9196 }
9197 }
9198 else
9199 {
9200 if (insn->mve_op == MVE_VSHLC && value == 0)
9201 value = 32;
9202 func (stream, "%ld", value);
9203 value_in_comment = value;
9204 }
04d54ace 9205 break;
c507f10b
AV		 9206 case 'F':
9207 func (stream, "s%ld", value);
9208 break;
143275ea
AV		 9209 case 'Q':
9210 if (value & 0x8)
9211 func (stream, "<illegal reg q%ld.5>", value);
9212 else
9213 func (stream, "q%ld", value);
9214 break;
c507f10b
AV		 9215 case 'x':
9216 func (stream, "0x%08lx", value);
9217 break;
143275ea
AV		 9218 default:
9219 abort ();
9220 }
9221 break;
9222 default:
9223 abort ();
9224 }
73cd51e5
AV		 9225 }
9226 }
9227 else
9228 func (stream, "%c", *c);
9229 }
9230
9231 if (value_in_comment > 32 || value_in_comment < -16)
9232 func (stream, "\t; 0x%lx", value_in_comment);
9233
9234 if (is_unpredictable)
9235 print_mve_unpredictable (info, unpredictable_cond);
9236
9237 if (is_undefined)
9238 print_mve_undefined (info, undefined_cond);
9239
143275ea
AV		 9240 if ((vpt_block_state.in_vpt_block == FALSE)
9241 && !ifthen_state
9242 && (is_vpt_instruction (given) == TRUE))
9243 mark_inside_vpt_block (given);
9244 else if (vpt_block_state.in_vpt_block == TRUE)
9245 update_vpt_block_state ();
9246
73cd51e5
AV		 9247 return TRUE;
9248 }
9249 }
9250 return FALSE;
9251}
9252
9253
90ec0d68
MGD		 9254/* Return the name of a v7A special register. */
9255
43e65147 9256static const char *
90ec0d68
MGD		 9257banked_regname (unsigned reg)
9258{
9259 switch (reg)
9260 {
9261 case 15: return "CPSR";
43e65147 9262 case 32: return "R8_usr";
90ec0d68
MGD		 9263 case 33: return "R9_usr";
9264 case 34: return "R10_usr";
9265 case 35: return "R11_usr";
9266 case 36: return "R12_usr";
9267 case 37: return "SP_usr";
9268 case 38: return "LR_usr";
43e65147 9269 case 40: return "R8_fiq";
90ec0d68
MGD		 9270 case 41: return "R9_fiq";
9271 case 42: return "R10_fiq";
9272 case 43: return "R11_fiq";
9273 case 44: return "R12_fiq";
9274 case 45: return "SP_fiq";
9275 case 46: return "LR_fiq";
9276 case 48: return "LR_irq";
9277 case 49: return "SP_irq";
9278 case 50: return "LR_svc";
9279 case 51: return "SP_svc";
9280 case 52: return "LR_abt";
9281 case 53: return "SP_abt";
9282 case 54: return "LR_und";
9283 case 55: return "SP_und";
9284 case 60: return "LR_mon";
9285 case 61: return "SP_mon";
9286 case 62: return "ELR_hyp";
9287 case 63: return "SP_hyp";
9288 case 79: return "SPSR";
9289 case 110: return "SPSR_fiq";
9290 case 112: return "SPSR_irq";
9291 case 114: return "SPSR_svc";
9292 case 116: return "SPSR_abt";
9293 case 118: return "SPSR_und";
9294 case 124: return "SPSR_mon";
9295 case 126: return "SPSR_hyp";
9296 default: return NULL;
9297 }
9298}
9299
e797f7e0
MGD		 9300/* Return the name of the DMB/DSB option. */
9301static const char *
9302data_barrier_option (unsigned option)
9303{
9304 switch (option & 0xf)
9305 {
9306 case 0xf: return "sy";
9307 case 0xe: return "st";
9308 case 0xd: return "ld";
9309 case 0xb: return "ish";
9310 case 0xa: return "ishst";
9311 case 0x9: return "ishld";
9312 case 0x7: return "un";
9313 case 0x6: return "unst";
9314 case 0x5: return "nshld";
9315 case 0x3: return "osh";
9316 case 0x2: return "oshst";
9317 case 0x1: return "oshld";
9318 default: return NULL;
9319 }
9320}
9321
4a5329c6
ZW		 9322/* Print one ARM instruction from PC on INFO->STREAM. */
9323
9324static void
9325print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9326{
6b5d3a4d 9327 const struct opcode32 *insn;
6a51a8a8 9328 void *stream = info->stream;
6b5d3a4d 9329 fprintf_ftype func = info->fprintf_func;
b0e28b39 9330 struct arm_private_data *private_data = info->private_data;
252b5132 9331
16980d0b
JB		 9332 if (print_insn_coprocessor (pc, info, given, FALSE))
9333 return;
9334
9335 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9336 return;
9337
252b5132
RH		 9338 for (insn = arm_opcodes; insn->assembler; insn++)
9339 {
0313a2b8
NC		 9340 if ((given & insn->mask) != insn->value)
9341 continue;
823d2571
TG		 9342
9343 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9344 continue;
9345
9346 /* Special case: an instruction with all bits set in the condition field
9347 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9348 or by the catchall at the end of the table. */
9349 if ((given & 0xF0000000) != 0xF0000000
9350 || (insn->mask & 0xF0000000) == 0xF0000000
9351 || (insn->mask == 0 && insn->value == 0))
252b5132 9352 {
ff4a8d2b
NC		 9353 unsigned long u_reg = 16;
9354 unsigned long U_reg = 16;
ab8e2090 9355 bfd_boolean is_unpredictable = FALSE;
05413229 9356 signed long value_in_comment = 0;
6b5d3a4d 9357 const char *c;
b34976b6 9358
252b5132
RH		 9359 for (c = insn->assembler; *c; c++)
9360 {
9361 if (*c == '%')
9362 {
c1e26897
NC		 9363 bfd_boolean allow_unpredictable = FALSE;
9364
252b5132
RH		 9365 switch (*++c)
9366 {
9367 case '%':
9368 func (stream, "%%");
9369 break;
9370
9371 case 'a':
05413229 9372 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9373 break;
252b5132 9374
62b3e311
PB		 9375 case 'P':
9376 /* Set P address bit and use normal address
9377 printing routine. */
c1e26897 9378 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9379 break;
9380
c1e26897
NC		 9381 case 'S':
9382 allow_unpredictable = TRUE;
1a0670f3 9383 /* Fall through. */
252b5132
RH		 9384 case 's':
9385 if ((given & 0x004f0000) == 0x004f0000)
9386 {
58efb6c0 9387 /* PC relative with immediate offset. */
f8b960bc 9388 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9389
aefd8a40
NC		 9390 if (PRE_BIT_SET)
9391 {
26d97720
NS		 9392 /* Elide positive zero offset. */
9393 if (offset || NEGATIVE_BIT_SET)
9394 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9395 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9396 else
26d97720
NS		 9397 func (stream, "[pc]\t; ");
9398 if (NEGATIVE_BIT_SET)
9399 offset = -offset;
aefd8a40
NC		 9400 info->print_address_func (offset + pc + 8, info);
9401 }
9402 else
9403 {
26d97720
NS		 9404 /* Always show the offset. */
9405 func (stream, "[pc], #%s%d",
d908c8af 9406 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9407 if (! allow_unpredictable)
9408 is_unpredictable = TRUE;
aefd8a40 9409 }
252b5132
RH		 9410 }
9411 else
9412 {
fe56b6ce
NC		 9413 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9414
b34976b6 9415 func (stream, "[%s",
252b5132 9416 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9417
c1e26897 9418 if (PRE_BIT_SET)
252b5132 9419 {
c1e26897 9420 if (IMMEDIATE_BIT_SET)
252b5132 9421 {
26d97720
NS		 9422 /* Elide offset for non-writeback
9423 positive zero. */
9424 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9425 || offset)
9426 func (stream, ", #%s%d",
9427 NEGATIVE_BIT_SET ? "-" : "", offset);
9428
9429 if (NEGATIVE_BIT_SET)
9430 offset = -offset;
945ee430 9431
fe56b6ce 9432 value_in_comment = offset;
252b5132 9433 }
945ee430 9434 else
ff4a8d2b
NC		 9435 {
9436 /* Register Offset or Register Pre-Indexed. */
9437 func (stream, ", %s%s",
9438 NEGATIVE_BIT_SET ? "-" : "",
9439 arm_regnames[given & 0xf]);
9440
9441 /* Writing back to the register that is the source/
9442 destination of the load/store is unpredictable. */
9443 if (! allow_unpredictable
9444 && WRITEBACK_BIT_SET
9445 && ((given & 0xf) == ((given >> 12) & 0xf)))
9446 is_unpredictable = TRUE;
9447 }
252b5132 9448
b34976b6 9449 func (stream, "]%s",
c1e26897 9450 WRITEBACK_BIT_SET ? "!" : "");
252b5132 9451 }
945ee430 9452 else
252b5132 9453 {
c1e26897 9454 if (IMMEDIATE_BIT_SET)
252b5132 9455 {
945ee430 9456 /* Immediate Post-indexed. */
aefd8a40 9457 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 9458 func (stream, "], #%s%d",
9459 NEGATIVE_BIT_SET ? "-" : "", offset);
9460 if (NEGATIVE_BIT_SET)
9461 offset = -offset;
fe56b6ce 9462 value_in_comment = offset;
252b5132 9463 }
945ee430 9464 else
ff4a8d2b
NC		 9465 {
9466 /* Register Post-indexed. */
9467 func (stream, "], %s%s",
9468 NEGATIVE_BIT_SET ? "-" : "",
9469 arm_regnames[given & 0xf]);
9470
9471 /* Writing back to the register that is the source/
9472 destination of the load/store is unpredictable. */
9473 if (! allow_unpredictable
9474 && (given & 0xf) == ((given >> 12) & 0xf))
9475 is_unpredictable = TRUE;
9476 }
c1e26897 9477
07a28fab
NC		 9478 if (! allow_unpredictable)
9479 {
9480 /* Writeback is automatically implied by post- addressing.
9481 Setting the W bit is unnecessary and ARM specify it as
9482 being unpredictable. */
9483 if (WRITEBACK_BIT_SET
9484 /* Specifying the PC register as the post-indexed
9485 registers is also unpredictable. */
ab8e2090
NC		 9486 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9487 is_unpredictable = TRUE;
07a28fab 9488 }
252b5132
RH		 9489 }
9490 }
9491 break;
b34976b6 9492
252b5132 9493 case 'b':
6b5d3a4d 9494 {
f8b960bc 9495 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 9496 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 9497 }
252b5132
RH		 9498 break;
9499
9500 case 'c':
c22aaad1
PB		 9501 if (((given >> 28) & 0xf) != 0xe)
9502 func (stream, "%s",
9503 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 9504 break;
9505
9506 case 'm':
9507 {
9508 int started = 0;
9509 int reg;
9510
9511 func (stream, "{");
9512 for (reg = 0; reg < 16; reg++)
9513 if ((given & (1 << reg)) != 0)
9514 {
9515 if (started)
9516 func (stream, ", ");
9517 started = 1;
9518 func (stream, "%s", arm_regnames[reg]);
9519 }
9520 func (stream, "}");
ab8e2090
NC		 9521 if (! started)
9522 is_unpredictable = TRUE;
252b5132
RH		 9523 }
9524 break;
9525
37b37b2d 9526 case 'q':
78c66db8 9527 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 9528 break;
9529
252b5132
RH		 9530 case 'o':
9531 if ((given & 0x02000000) != 0)
9532 {
a415b1cd
JB		 9533 unsigned int rotate = (given & 0xf00) >> 7;
9534 unsigned int immed = (given & 0xff);
9535 unsigned int a, i;
9536
9537 a = (((immed << (32 - rotate))
9538 | (immed >> rotate)) & 0xffffffff);
9539 /* If there is another encoding with smaller rotate,
9540 the rotate should be specified directly. */
9541 for (i = 0; i < 32; i += 2)
9542 if ((a << i | a >> (32 - i)) <= 0xff)
9543 break;
9544
9545 if (i != rotate)
9546 func (stream, "#%d, %d", immed, rotate);
9547 else
9548 func (stream, "#%d", a);
9549 value_in_comment = a;
252b5132
RH		 9550 }
9551 else
78c66db8 9552 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 9553 break;
9554
9555 case 'p':
9556 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 9557 {
823d2571
TG		 9558 arm_feature_set arm_ext_v6 =
9559 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9560
aefd8a40
NC		 9561 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9562 mechanism for setting PSR flag bits. They are
9563 obsolete in V6 onwards. */
823d2571
TG		 9564 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9565 arm_ext_v6))
aefd8a40 9566 func (stream, "p");
4ab90a7a
AV		 9567 else
9568 is_unpredictable = TRUE;
aefd8a40 9569 }
252b5132
RH		 9570 break;
9571
9572 case 't':
9573 if ((given & 0x01200000) == 0x00200000)
9574 func (stream, "t");
9575 break;
9576
252b5132 9577 case 'A':
05413229
NC		 9578 {
9579 int offset = given & 0xff;
f02232aa 9580
05413229 9581 value_in_comment = offset * 4;
c1e26897 9582 if (NEGATIVE_BIT_SET)
05413229 9583 value_in_comment = - value_in_comment;
f02232aa 9584
05413229 9585 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9586
c1e26897 9587 if (PRE_BIT_SET)
05413229
NC		 9588 {
9589 if (offset)
fe56b6ce 9590 func (stream, ", #%d]%s",
d908c8af 9591 (int) value_in_comment,
c1e26897 9592 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9593 else
9594 func (stream, "]");
9595 }
9596 else
9597 {
9598 func (stream, "]");
f02232aa 9599
c1e26897 9600 if (WRITEBACK_BIT_SET)
05413229
NC		 9601 {
9602 if (offset)
d908c8af 9603 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9604 }
9605 else
fe56b6ce 9606 {
d908c8af 9607 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 9608 value_in_comment = offset;
9609 }
05413229
NC		 9610 }
9611 }
252b5132
RH		 9612 break;
9613
077b8428
NC		 9614 case 'B':
9615 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9616 {
9617 bfd_vma address;
9618 bfd_vma offset = 0;
b34976b6 9619
c1e26897 9620 if (! NEGATIVE_BIT_SET)
077b8428
NC		 9621 /* Is signed, hi bits should be ones. */
9622 offset = (-1) ^ 0x00ffffff;
9623
9624 /* Offset is (SignExtend(offset field)<<2). */
9625 offset += given & 0x00ffffff;
9626 offset <<= 2;
9627 address = offset + pc + 8;
b34976b6 9628
8f06b2d8
PB		 9629 if (given & 0x01000000)
9630 /* H bit allows addressing to 2-byte boundaries. */
9631 address += 2;
b1ee46c5 9632
8f06b2d8 9633 info->print_address_func (address, info);
b1ee46c5 9634 }
b1ee46c5
AH		 9635 break;
9636
252b5132 9637 case 'C':
90ec0d68
MGD		 9638 if ((given & 0x02000200) == 0x200)
9639 {
9640 const char * name;
9641 unsigned sysm = (given & 0x004f0000) >> 16;
9642
9643 sysm |= (given & 0x300) >> 4;
9644 name = banked_regname (sysm);
9645
9646 if (name != NULL)
9647 func (stream, "%s", name);
9648 else
d908c8af 9649 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 9650 }
9651 else
9652 {
43e65147 9653 func (stream, "%cPSR_",
90ec0d68
MGD		 9654 (given & 0x00400000) ? 'S' : 'C');
9655 if (given & 0x80000)
9656 func (stream, "f");
9657 if (given & 0x40000)
9658 func (stream, "s");
9659 if (given & 0x20000)
9660 func (stream, "x");
9661 if (given & 0x10000)
9662 func (stream, "c");
9663 }
252b5132
RH		 9664 break;
9665
62b3e311 9666 case 'U':
43e65147 9667 if ((given & 0xf0) == 0x60)
62b3e311 9668 {
52e7f43d
RE		 9669 switch (given & 0xf)
9670 {
9671 case 0xf: func (stream, "sy"); break;
9672 default:
9673 func (stream, "#%d", (int) given & 0xf);
9674 break;
9675 }
43e65147
L		 9676 }
9677 else
52e7f43d 9678 {
e797f7e0
MGD		 9679 const char * opt = data_barrier_option (given & 0xf);
9680 if (opt != NULL)
9681 func (stream, "%s", opt);
9682 else
52e7f43d 9683 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 9684 }
9685 break;
9686
b34976b6 9687 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 9688 case '5': case '6': case '7': case '8': case '9':
9689 {
16980d0b
JB		 9690 int width;
9691 unsigned long value;
252b5132 9692
16980d0b 9693 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9694
252b5132
RH		 9695 switch (*c)
9696 {
ab8e2090
NC		 9697 case 'R':
9698 if (value == 15)
9699 is_unpredictable = TRUE;
9700 /* Fall through. */
16980d0b 9701 case 'r':
9eb6c0f1
MGD		 9702 case 'T':
9703 /* We want register + 1 when decoding T. */
9704 if (*c == 'T')
9705 ++value;
9706
ff4a8d2b
NC		 9707 if (c[1] == 'u')
9708 {
9709 /* Eat the 'u' character. */
9710 ++ c;
9711
9712 if (u_reg == value)
9713 is_unpredictable = TRUE;
9714 u_reg = value;
9715 }
9716 if (c[1] == 'U')
9717 {
9718 /* Eat the 'U' character. */
9719 ++ c;
9720
9721 if (U_reg == value)
9722 is_unpredictable = TRUE;
9723 U_reg = value;
9724 }
16980d0b
JB		 9725 func (stream, "%s", arm_regnames[value]);
9726 break;
9727 case 'd':
9728 func (stream, "%ld", value);
05413229 9729 value_in_comment = value;
16980d0b
JB		 9730 break;
9731 case 'b':
9732 func (stream, "%ld", value * 8);
05413229 9733 value_in_comment = value * 8;
16980d0b
JB		 9734 break;
9735 case 'W':
9736 func (stream, "%ld", value + 1);
05413229 9737 value_in_comment = value + 1;
16980d0b
JB		 9738 break;
9739 case 'x':
9740 func (stream, "0x%08lx", value);
9741
9742 /* Some SWI instructions have special
9743 meanings. */
9744 if ((given & 0x0fffffff) == 0x0FF00000)
9745 func (stream, "\t; IMB");
9746 else if ((given & 0x0fffffff) == 0x0FF00001)
9747 func (stream, "\t; IMBRange");
9748 break;
9749 case 'X':
9750 func (stream, "%01lx", value & 0xf);
05413229 9751 value_in_comment = value;
252b5132
RH		 9752 break;
9753 case '`':
9754 c++;
16980d0b 9755 if (value == 0)
252b5132
RH		 9756 func (stream, "%c", *c);
9757 break;
9758 case '\'':
9759 c++;
16980d0b 9760 if (value == ((1ul << width) - 1))
252b5132
RH		 9761 func (stream, "%c", *c);
9762 break;
9763 case '?':
fe56b6ce 9764 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 9765 c += 1 << width;
252b5132
RH		 9766 break;
9767 default:
9768 abort ();
9769 }
dffaa15c
AM		 9770 }
9771 break;
0dd132b6 9772
dffaa15c
AM		 9773 case 'e':
9774 {
9775 int imm;
0dd132b6 9776
dffaa15c
AM		 9777 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9778 func (stream, "%d", imm);
9779 value_in_comment = imm;
9780 }
9781 break;
fe56b6ce 9782
dffaa15c
AM		 9783 case 'E':
9784 /* LSB and WIDTH fields of BFI or BFC. The machine-
9785 language instruction encodes LSB and MSB. */
9786 {
9787 long msb = (given & 0x001f0000) >> 16;
9788 long lsb = (given & 0x00000f80) >> 7;
9789 long w = msb - lsb + 1;
0a003adc 9790
dffaa15c
AM		 9791 if (w > 0)
9792 func (stream, "#%lu, #%lu", lsb, w);
9793 else
9794 func (stream, "(invalid: %lu:%lu)", lsb, msb);
9795 }
9796 break;
90ec0d68 9797
dffaa15c
AM		 9798 case 'R':
9799 /* Get the PSR/banked register name. */
9800 {
9801 const char * name;
9802 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 9803
dffaa15c
AM		 9804 sysm |= (given & 0x300) >> 4;
9805 name = banked_regname (sysm);
90ec0d68 9806
dffaa15c
AM		 9807 if (name != NULL)
9808 func (stream, "%s", name);
9809 else
9810 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9811 }
9812 break;
fe56b6ce 9813
dffaa15c
AM		 9814 case 'V':
9815 /* 16-bit unsigned immediate from a MOVT or MOVW
9816 instruction, encoded in bits 0:11 and 15:19. */
9817 {
9818 long hi = (given & 0x000f0000) >> 4;
9819 long lo = (given & 0x00000fff);
9820 long imm16 = hi | lo;
0a003adc 9821
dffaa15c
AM		 9822 func (stream, "#%lu", imm16);
9823 value_in_comment = imm16;
252b5132 9824 }
dffaa15c
AM		 9825 break;
9826
9827 default:
9828 abort ();
252b5132
RH		 9829 }
9830 }
9831 else
9832 func (stream, "%c", *c);
9833 }
05413229
NC		 9834
9835 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 9836 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 9837
9838 if (is_unpredictable)
9839 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 9840
4a5329c6 9841 return;
252b5132
RH		 9842 }
9843 }
0b347048
TC		 9844 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9845 return;
252b5132
RH		 9846}
9847
4a5329c6 9848/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 9849
4a5329c6
ZW		 9850static void
9851print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9852{
6b5d3a4d 9853 const struct opcode16 *insn;
6a51a8a8
AM		 9854 void *stream = info->stream;
9855 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 9856
9857 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 9858 if ((given & insn->mask) == insn->value)
9859 {
05413229 9860 signed long value_in_comment = 0;
6b5d3a4d 9861 const char *c = insn->assembler;
05413229 9862
c19d1205
ZW		 9863 for (; *c; c++)
9864 {
9865 int domaskpc = 0;
9866 int domasklr = 0;
9867
9868 if (*c != '%')
9869 {
9870 func (stream, "%c", *c);
9871 continue;
9872 }
252b5132 9873
c19d1205
ZW		 9874 switch (*++c)
9875 {
9876 case '%':
9877 func (stream, "%%");
9878 break;
b34976b6 9879
c22aaad1
PB		 9880 case 'c':
9881 if (ifthen_state)
9882 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9883 break;
9884
9885 case 'C':
9886 if (ifthen_state)
9887 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9888 else
9889 func (stream, "s");
9890 break;
9891
9892 case 'I':
9893 {
9894 unsigned int tmp;
9895
9896 ifthen_next_state = given & 0xff;
9897 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
9898 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
9899 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
9900 }
9901 break;
9902
9903 case 'x':
9904 if (ifthen_next_state)
9905 func (stream, "\t; unpredictable branch in IT block\n");
9906 break;
9907
9908 case 'X':
9909 if (ifthen_state)
9910 func (stream, "\t; unpredictable <IT:%s>",
9911 arm_conditional[IFTHEN_COND]);
9912 break;
9913
c19d1205
ZW		 9914 case 'S':
9915 {
9916 long reg;
9917
9918 reg = (given >> 3) & 0x7;
9919 if (given & (1 << 6))
9920 reg += 8;
4f3c3dbb 9921
c19d1205
ZW		 9922 func (stream, "%s", arm_regnames[reg]);
9923 }
9924 break;
baf0cc5e 9925
c19d1205 9926 case 'D':
4f3c3dbb 9927 {
c19d1205
ZW		 9928 long reg;
9929
9930 reg = given & 0x7;
9931 if (given & (1 << 7))
9932 reg += 8;
9933
9934 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 9935 }
c19d1205
ZW		 9936 break;
9937
9938 case 'N':
9939 if (given & (1 << 8))
9940 domasklr = 1;
9941 /* Fall through. */
9942 case 'O':
9943 if (*c == 'O' && (given & (1 << 8)))
9944 domaskpc = 1;
9945 /* Fall through. */
9946 case 'M':
9947 {
9948 int started = 0;
9949 int reg;
9950
9951 func (stream, "{");
9952
9953 /* It would be nice if we could spot
9954 ranges, and generate the rS-rE format: */
9955 for (reg = 0; (reg < 8); reg++)
9956 if ((given & (1 << reg)) != 0)
9957 {
9958 if (started)
9959 func (stream, ", ");
9960 started = 1;
9961 func (stream, "%s", arm_regnames[reg]);
9962 }
9963
9964 if (domasklr)
9965 {
9966 if (started)
9967 func (stream, ", ");
9968 started = 1;
d908c8af 9969 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 9970 }
9971
9972 if (domaskpc)
9973 {
9974 if (started)
9975 func (stream, ", ");
d908c8af 9976 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 9977 }
9978
9979 func (stream, "}");
9980 }
9981 break;
9982
4547cb56
NC		 9983 case 'W':
9984 /* Print writeback indicator for a LDMIA. We are doing a
9985 writeback if the base register is not in the register
9986 mask. */
9987 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
9988 func (stream, "!");
dffaa15c 9989 break;
4547cb56 9990
c19d1205
ZW		 9991 case 'b':
9992 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9993 {
9994 bfd_vma address = (pc + 4
9995 + ((given & 0x00f8) >> 2)
9996 + ((given & 0x0200) >> 3));
9997 info->print_address_func (address, info);
9998 }
9999 break;
10000
10001 case 's':
10002 /* Right shift immediate -- bits 6..10; 1-31 print
10003 as themselves, 0 prints as 32. */
10004 {
10005 long imm = (given & 0x07c0) >> 6;
10006 if (imm == 0)
10007 imm = 32;
0fd3a477 10008 func (stream, "#%ld", imm);
c19d1205
ZW		 10009 }
10010 break;
10011
10012 case '0': case '1': case '2': case '3': case '4':
10013 case '5': case '6': case '7': case '8': case '9':
10014 {
10015 int bitstart = *c++ - '0';
10016 int bitend = 0;
10017
10018 while (*c >= '0' && *c <= '9')
10019 bitstart = (bitstart * 10) + *c++ - '0';
10020
10021 switch (*c)
10022 {
10023 case '-':
10024 {
f8b960bc 10025 bfd_vma reg;
c19d1205
ZW		 10026
10027 c++;
10028 while (*c >= '0' && *c <= '9')
10029 bitend = (bitend * 10) + *c++ - '0';
10030 if (!bitend)
10031 abort ();
10032 reg = given >> bitstart;
10033 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10034
c19d1205
ZW		 10035 switch (*c)
10036 {
10037 case 'r':
10038 func (stream, "%s", arm_regnames[reg]);
10039 break;
10040
10041 case 'd':
d908c8af 10042 func (stream, "%ld", (long) reg);
05413229 10043 value_in_comment = reg;
c19d1205
ZW		 10044 break;
10045
10046 case 'H':
d908c8af 10047 func (stream, "%ld", (long) (reg << 1));
05413229 10048 value_in_comment = reg << 1;
c19d1205
ZW		 10049 break;
10050
10051 case 'W':
d908c8af 10052 func (stream, "%ld", (long) (reg << 2));
05413229 10053 value_in_comment = reg << 2;
c19d1205
ZW		 10054 break;
10055
10056 case 'a':
10057 /* PC-relative address -- the bottom two
10058 bits of the address are dropped
10059 before the calculation. */
10060 info->print_address_func
10061 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10062 value_in_comment = 0;
c19d1205
ZW		 10063 break;
10064
10065 case 'x':
d908c8af 10066 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10067 break;
10068
c19d1205
ZW		 10069 case 'B':
10070 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 10071 info->print_address_func (reg * 2 + pc + 4, info);
05413229 10072 value_in_comment = 0;
c19d1205
ZW		 10073 break;
10074
10075 case 'c':
c22aaad1 10076 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10077 break;
10078
10079 default:
10080 abort ();
10081 }
10082 }
10083 break;
10084
10085 case '\'':
10086 c++;
10087 if ((given & (1 << bitstart)) != 0)
10088 func (stream, "%c", *c);
10089 break;
10090
10091 case '?':
10092 ++c;
10093 if ((given & (1 << bitstart)) != 0)
10094 func (stream, "%c", *c++);
10095 else
10096 func (stream, "%c", *++c);
10097 break;
10098
10099 default:
10100 abort ();
10101 }
10102 }
10103 break;
10104
10105 default:
10106 abort ();
10107 }
10108 }
05413229
NC		 10109
10110 if (value_in_comment > 32 || value_in_comment < -16)
10111 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10112 return;
c19d1205
ZW		 10113 }
10114
10115 /* No match. */
0b347048
TC		 10116 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10117 return;
c19d1205
ZW		 10118}
10119
62b3e311 10120/* Return the name of an V7M special register. */
fe56b6ce 10121
62b3e311
PB		 10122static const char *
10123psr_name (int regno)
10124{
10125 switch (regno)
10126 {
1a336194
TP		 10127 case 0x0: return "APSR";
10128 case 0x1: return "IAPSR";
10129 case 0x2: return "EAPSR";
10130 case 0x3: return "PSR";
10131 case 0x5: return "IPSR";
10132 case 0x6: return "EPSR";
10133 case 0x7: return "IEPSR";
10134 case 0x8: return "MSP";
10135 case 0x9: return "PSP";
10136 case 0xa: return "MSPLIM";
10137 case 0xb: return "PSPLIM";
10138 case 0x10: return "PRIMASK";
10139 case 0x11: return "BASEPRI";
10140 case 0x12: return "BASEPRI_MAX";
10141 case 0x13: return "FAULTMASK";
10142 case 0x14: return "CONTROL";
16a1fa25
TP		 10143 case 0x88: return "MSP_NS";
10144 case 0x89: return "PSP_NS";
1a336194
TP		 10145 case 0x8a: return "MSPLIM_NS";
10146 case 0x8b: return "PSPLIM_NS";
10147 case 0x90: return "PRIMASK_NS";
10148 case 0x91: return "BASEPRI_NS";
10149 case 0x93: return "FAULTMASK_NS";
10150 case 0x94: return "CONTROL_NS";
10151 case 0x98: return "SP_NS";
62b3e311
PB		 10152 default: return "<unknown>";
10153 }
10154}
10155
4a5329c6
ZW		 10156/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10157
10158static void
10159print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10160{
6b5d3a4d 10161 const struct opcode32 *insn;
c19d1205
ZW		 10162 void *stream = info->stream;
10163 fprintf_ftype func = info->fprintf_func;
73cd51e5 10164 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10165
16980d0b
JB		 10166 if (print_insn_coprocessor (pc, info, given, TRUE))
10167 return;
10168
73cd51e5
AV		 10169 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10170 return;
10171
10172 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10173 return;
10174
c19d1205
ZW		 10175 for (insn = thumb32_opcodes; insn->assembler; insn++)
10176 if ((given & insn->mask) == insn->value)
10177 {
4b5a202f 10178 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10179 bfd_boolean is_unpredictable = FALSE;
05413229 10180 signed long value_in_comment = 0;
6b5d3a4d 10181 const char *c = insn->assembler;
05413229 10182
c19d1205
ZW		 10183 for (; *c; c++)
10184 {
10185 if (*c != '%')
10186 {
10187 func (stream, "%c", *c);
10188 continue;
10189 }
10190
10191 switch (*++c)
10192 {
10193 case '%':
10194 func (stream, "%%");
10195 break;
10196
c22aaad1
PB		 10197 case 'c':
10198 if (ifthen_state)
10199 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10200 break;
10201
10202 case 'x':
10203 if (ifthen_next_state)
10204 func (stream, "\t; unpredictable branch in IT block\n");
10205 break;
10206
10207 case 'X':
10208 if (ifthen_state)
10209 func (stream, "\t; unpredictable <IT:%s>",
10210 arm_conditional[IFTHEN_COND]);
10211 break;
10212
c19d1205
ZW		 10213 case 'I':
10214 {
10215 unsigned int imm12 = 0;
fe56b6ce 10216
c19d1205
ZW		 10217 imm12 |= (given & 0x000000ffu);
10218 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10219 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10220 func (stream, "#%u", imm12);
10221 value_in_comment = imm12;
c19d1205
ZW		 10222 }
10223 break;
10224
10225 case 'M':
10226 {
10227 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10228
c19d1205
ZW		 10229 bits |= (given & 0x000000ffu);
10230 bits |= (given & 0x00007000u) >> 4;
10231 bits |= (given & 0x04000000u) >> 15;
10232 imm8 = (bits & 0x0ff);
10233 mod = (bits & 0xf00) >> 8;
10234 switch (mod)
10235 {
10236 case 0: imm = imm8; break;
c1e26897
NC		 10237 case 1: imm = ((imm8 << 16) | imm8); break;
10238 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10239 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10240 default:
10241 mod = (bits & 0xf80) >> 7;
10242 imm8 = (bits & 0x07f) | 0x80;
10243 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10244 }
fe56b6ce
NC		 10245 func (stream, "#%u", imm);
10246 value_in_comment = imm;
c19d1205
ZW		 10247 }
10248 break;
43e65147 10249
c19d1205
ZW		 10250 case 'J':
10251 {
10252 unsigned int imm = 0;
fe56b6ce 10253
c19d1205
ZW		 10254 imm |= (given & 0x000000ffu);
10255 imm |= (given & 0x00007000u) >> 4;
10256 imm |= (given & 0x04000000u) >> 15;
10257 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10258 func (stream, "#%u", imm);
10259 value_in_comment = imm;
c19d1205
ZW		 10260 }
10261 break;
10262
10263 case 'K':
10264 {
10265 unsigned int imm = 0;
fe56b6ce 10266
c19d1205
ZW		 10267 imm |= (given & 0x000f0000u) >> 16;
10268 imm |= (given & 0x00000ff0u) >> 0;
10269 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10270 func (stream, "#%u", imm);
10271 value_in_comment = imm;
c19d1205
ZW		 10272 }
10273 break;
10274
74db7efb
NC		 10275 case 'H':
10276 {
10277 unsigned int imm = 0;
10278
10279 imm |= (given & 0x000f0000u) >> 4;
10280 imm |= (given & 0x00000fffu) >> 0;
10281 func (stream, "#%u", imm);
10282 value_in_comment = imm;
10283 }
10284 break;
10285
90ec0d68
MGD		 10286 case 'V':
10287 {
10288 unsigned int imm = 0;
10289
10290 imm |= (given & 0x00000fffu);
10291 imm |= (given & 0x000f0000u) >> 4;
10292 func (stream, "#%u", imm);
10293 value_in_comment = imm;
10294 }
10295 break;
10296
c19d1205
ZW		 10297 case 'S':
10298 {
10299 unsigned int reg = (given & 0x0000000fu);
10300 unsigned int stp = (given & 0x00000030u) >> 4;
10301 unsigned int imm = 0;
10302 imm |= (given & 0x000000c0u) >> 6;
10303 imm |= (given & 0x00007000u) >> 10;
10304
10305 func (stream, "%s", arm_regnames[reg]);
10306 switch (stp)
10307 {
10308 case 0:
10309 if (imm > 0)
10310 func (stream, ", lsl #%u", imm);
10311 break;
10312
10313 case 1:
10314 if (imm == 0)
10315 imm = 32;
10316 func (stream, ", lsr #%u", imm);
10317 break;
10318
10319 case 2:
10320 if (imm == 0)
10321 imm = 32;
10322 func (stream, ", asr #%u", imm);
10323 break;
10324
10325 case 3:
10326 if (imm == 0)
10327 func (stream, ", rrx");
10328 else
10329 func (stream, ", ror #%u", imm);
10330 }
10331 }
10332 break;
10333
10334 case 'a':
10335 {
10336 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 10337 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 10338 unsigned int op = (given & 0x00000f00) >> 8;
10339 unsigned int i12 = (given & 0x00000fff);
10340 unsigned int i8 = (given & 0x000000ff);
10341 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 10342 bfd_vma offset = 0;
c19d1205
ZW		 10343
10344 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 10345 if (U) /* 12-bit positive immediate offset. */
10346 {
10347 offset = i12;
10348 if (Rn != 15)
10349 value_in_comment = offset;
10350 }
10351 else if (Rn == 15) /* 12-bit negative immediate offset. */
10352 offset = - (int) i12;
10353 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 10354 {
10355 unsigned int Rm = (i8 & 0x0f);
10356 unsigned int sh = (i8 & 0x30) >> 4;
05413229 10357
c19d1205
ZW		 10358 func (stream, ", %s", arm_regnames[Rm]);
10359 if (sh)
10360 func (stream, ", lsl #%u", sh);
10361 func (stream, "]");
10362 break;
10363 }
10364 else switch (op)
10365 {
05413229 10366 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 10367 offset = i8;
10368 break;
10369
05413229 10370 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10371 offset = -i8;
10372 break;
10373
05413229 10374 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10375 offset = i8;
10376 writeback = TRUE;
10377 break;
10378
05413229 10379 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10380 offset = -i8;
10381 writeback = TRUE;
10382 break;
10383
05413229 10384 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10385 offset = i8;
10386 postind = TRUE;
10387 break;
10388
05413229 10389 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10390 offset = -i8;
10391 postind = TRUE;
10392 break;
10393
10394 default:
10395 func (stream, ", <undefined>]");
10396 goto skip;
10397 }
10398
10399 if (postind)
d908c8af 10400 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10401 else
10402 {
10403 if (offset)
d908c8af 10404 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 10405 func (stream, writeback ? "]!" : "]");
10406 }
10407
10408 if (Rn == 15)
10409 {
10410 func (stream, "\t; ");
10411 info->print_address_func (((pc + 4) & ~3) + offset, info);
10412 }
10413 }
10414 skip:
10415 break;
10416
10417 case 'A':
10418 {
c1e26897
NC		 10419 unsigned int U = ! NEGATIVE_BIT_SET;
10420 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 10421 unsigned int Rn = (given & 0x000f0000) >> 16;
10422 unsigned int off = (given & 0x000000ff);
10423
10424 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 10425
10426 if (PRE_BIT_SET)
c19d1205
ZW		 10427 {
10428 if (off || !U)
05413229
NC		 10429 {
10430 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 10431 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10432 }
c19d1205
ZW		 10433 func (stream, "]");
10434 if (W)
10435 func (stream, "!");
10436 }
10437 else
10438 {
10439 func (stream, "], ");
10440 if (W)
05413229
NC		 10441 {
10442 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 10443 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10444 }
c19d1205 10445 else
fe56b6ce
NC		 10446 {
10447 func (stream, "{%u}", off);
10448 value_in_comment = off;
10449 }
c19d1205
ZW		 10450 }
10451 }
10452 break;
10453
10454 case 'w':
10455 {
10456 unsigned int Sbit = (given & 0x01000000) >> 24;
10457 unsigned int type = (given & 0x00600000) >> 21;
05413229 10458
c19d1205
ZW		 10459 switch (type)
10460 {
10461 case 0: func (stream, Sbit ? "sb" : "b"); break;
10462 case 1: func (stream, Sbit ? "sh" : "h"); break;
10463 case 2:
10464 if (Sbit)
10465 func (stream, "??");
10466 break;
10467 case 3:
10468 func (stream, "??");
10469 break;
10470 }
10471 }
10472 break;
10473
4b5a202f
AV		 10474 case 'n':
10475 is_clrm = TRUE;
10476 /* Fall through. */
c19d1205
ZW		 10477 case 'm':
10478 {
10479 int started = 0;
10480 int reg;
10481
10482 func (stream, "{");
10483 for (reg = 0; reg < 16; reg++)
10484 if ((given & (1 << reg)) != 0)
10485 {
10486 if (started)
10487 func (stream, ", ");
10488 started = 1;
4b5a202f
AV		 10489 if (is_clrm && reg == 13)
10490 func (stream, "(invalid: %s)", arm_regnames[reg]);
10491 else if (is_clrm && reg == 15)
10492 func (stream, "%s", "APSR");
10493 else
10494 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 10495 }
10496 func (stream, "}");
10497 }
10498 break;
10499
10500 case 'E':
10501 {
10502 unsigned int msb = (given & 0x0000001f);
10503 unsigned int lsb = 0;
fe56b6ce 10504
c19d1205
ZW		 10505 lsb |= (given & 0x000000c0u) >> 6;
10506 lsb |= (given & 0x00007000u) >> 10;
10507 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10508 }
10509 break;
10510
10511 case 'F':
10512 {
10513 unsigned int width = (given & 0x0000001f) + 1;
10514 unsigned int lsb = 0;
fe56b6ce 10515
c19d1205
ZW		 10516 lsb |= (given & 0x000000c0u) >> 6;
10517 lsb |= (given & 0x00007000u) >> 10;
10518 func (stream, "#%u, #%u", lsb, width);
10519 }
10520 break;
10521
e12437dc
AV		 10522 case 'G':
10523 {
10524 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10525 func (stream, "%x", boff);
10526 }
10527 break;
10528
e5d6e09e
AV		 10529 case 'W':
10530 {
10531 unsigned int immA = (given & 0x001f0000u) >> 16;
10532 unsigned int immB = (given & 0x000007feu) >> 1;
10533 unsigned int immC = (given & 0x00000800u) >> 11;
10534 bfd_vma offset = 0;
10535
10536 offset |= immA << 12;
10537 offset |= immB << 2;
10538 offset |= immC << 1;
10539 /* Sign extend. */
10540 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10541
10542 info->print_address_func (pc + 4 + offset, info);
10543 }
10544 break;
10545
1caf72a5
AV		 10546 case 'Y':
10547 {
10548 unsigned int immA = (given & 0x007f0000u) >> 16;
10549 unsigned int immB = (given & 0x000007feu) >> 1;
10550 unsigned int immC = (given & 0x00000800u) >> 11;
10551 bfd_vma offset = 0;
10552
10553 offset |= immA << 12;
10554 offset |= immB << 2;
10555 offset |= immC << 1;
10556 /* Sign extend. */
10557 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10558
10559 info->print_address_func (pc + 4 + offset, info);
10560 }
10561 break;
10562
1889da70
AV		 10563 case 'Z':
10564 {
10565 unsigned int immA = (given & 0x00010000u) >> 16;
10566 unsigned int immB = (given & 0x000007feu) >> 1;
10567 unsigned int immC = (given & 0x00000800u) >> 11;
10568 bfd_vma offset = 0;
10569
10570 offset |= immA << 12;
10571 offset |= immB << 2;
10572 offset |= immC << 1;
10573 /* Sign extend. */
10574 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10575
10576 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 10577
10578 unsigned int T = (given & 0x00020000u) >> 17;
10579 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10580 unsigned int boffset = (T == 1) ? 4 : 2;
10581 func (stream, ", ");
10582 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10583 }
10584 break;
10585
60f993ce
AV		 10586 case 'Q':
10587 {
10588 unsigned int immh = (given & 0x000007feu) >> 1;
10589 unsigned int imml = (given & 0x00000800u) >> 11;
10590 bfd_vma imm32 = 0;
10591
10592 imm32 |= immh << 2;
10593 imm32 |= imml << 1;
10594
10595 info->print_address_func (pc + 4 + imm32, info);
10596 }
10597 break;
10598
10599 case 'P':
10600 {
10601 unsigned int immh = (given & 0x000007feu) >> 1;
10602 unsigned int imml = (given & 0x00000800u) >> 11;
10603 bfd_vma imm32 = 0;
10604
10605 imm32 |= immh << 2;
10606 imm32 |= imml << 1;
10607
10608 info->print_address_func (pc + 4 - imm32, info);
10609 }
10610 break;
10611
c19d1205
ZW		 10612 case 'b':
10613 {
10614 unsigned int S = (given & 0x04000000u) >> 26;
10615 unsigned int J1 = (given & 0x00002000u) >> 13;
10616 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 10617 bfd_vma offset = 0;
c19d1205
ZW		 10618
10619 offset |= !S << 20;
10620 offset |= J2 << 19;
10621 offset |= J1 << 18;
10622 offset |= (given & 0x003f0000) >> 4;
10623 offset |= (given & 0x000007ff) << 1;
10624 offset -= (1 << 20);
10625
10626 info->print_address_func (pc + 4 + offset, info);
10627 }
10628 break;
10629
10630 case 'B':
10631 {
10632 unsigned int S = (given & 0x04000000u) >> 26;
10633 unsigned int I1 = (given & 0x00002000u) >> 13;
10634 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 10635 bfd_vma offset = 0;
c19d1205
ZW		 10636
10637 offset |= !S << 24;
10638 offset |= !(I1 ^ S) << 23;
10639 offset |= !(I2 ^ S) << 22;
10640 offset |= (given & 0x03ff0000u) >> 4;
10641 offset |= (given & 0x000007ffu) << 1;
10642 offset -= (1 << 24);
36b0c57d 10643 offset += pc + 4;
c19d1205 10644
36b0c57d
PB		 10645 /* BLX target addresses are always word aligned. */
10646 if ((given & 0x00001000u) == 0)
10647 offset &= ~2u;
10648
10649 info->print_address_func (offset, info);
c19d1205
ZW		 10650 }
10651 break;
10652
10653 case 's':
10654 {
10655 unsigned int shift = 0;
fe56b6ce 10656
c19d1205
ZW		 10657 shift |= (given & 0x000000c0u) >> 6;
10658 shift |= (given & 0x00007000u) >> 10;
c1e26897 10659 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 10660 func (stream, ", asr #%u", shift);
10661 else if (shift)
10662 func (stream, ", lsl #%u", shift);
10663 /* else print nothing - lsl #0 */
10664 }
10665 break;
10666
10667 case 'R':
10668 {
10669 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 10670
c19d1205
ZW		 10671 if (rot)
10672 func (stream, ", ror #%u", rot * 8);
10673 }
10674 break;
10675
62b3e311 10676 case 'U':
43e65147 10677 if ((given & 0xf0) == 0x60)
62b3e311 10678 {
52e7f43d
RE		 10679 switch (given & 0xf)
10680 {
10681 case 0xf: func (stream, "sy"); break;
10682 default:
10683 func (stream, "#%d", (int) given & 0xf);
10684 break;
10685 }
62b3e311 10686 }
43e65147 10687 else
52e7f43d 10688 {
e797f7e0
MGD		 10689 const char * opt = data_barrier_option (given & 0xf);
10690 if (opt != NULL)
10691 func (stream, "%s", opt);
10692 else
10693 func (stream, "#%d", (int) given & 0xf);
52e7f43d 10694 }
62b3e311
PB		 10695 break;
10696
10697 case 'C':
10698 if ((given & 0xff) == 0)
10699 {
10700 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10701 if (given & 0x800)
10702 func (stream, "f");
10703 if (given & 0x400)
10704 func (stream, "s");
10705 if (given & 0x200)
10706 func (stream, "x");
10707 if (given & 0x100)
10708 func (stream, "c");
10709 }
90ec0d68
MGD		 10710 else if ((given & 0x20) == 0x20)
10711 {
10712 char const* name;
10713 unsigned sysm = (given & 0xf00) >> 8;
10714
10715 sysm |= (given & 0x30);
10716 sysm |= (given & 0x00100000) >> 14;
10717 name = banked_regname (sysm);
43e65147 10718
90ec0d68
MGD		 10719 if (name != NULL)
10720 func (stream, "%s", name);
10721 else
d908c8af 10722 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 10723 }
62b3e311
PB		 10724 else
10725 {
d908c8af 10726 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 10727 }
10728 break;
10729
10730 case 'D':
90ec0d68
MGD		 10731 if (((given & 0xff) == 0)
10732 || ((given & 0x20) == 0x20))
10733 {
10734 char const* name;
10735 unsigned sm = (given & 0xf0000) >> 16;
10736
10737 sm |= (given & 0x30);
10738 sm |= (given & 0x00100000) >> 14;
10739 name = banked_regname (sm);
10740
10741 if (name != NULL)
10742 func (stream, "%s", name);
10743 else
d908c8af 10744 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 10745 }
62b3e311 10746 else
d908c8af 10747 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 10748 break;
10749
c19d1205
ZW		 10750 case '0': case '1': case '2': case '3': case '4':
10751 case '5': case '6': case '7': case '8': case '9':
10752 {
16980d0b
JB		 10753 int width;
10754 unsigned long val;
c19d1205 10755
16980d0b 10756 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 10757
c19d1205
ZW		 10758 switch (*c)
10759 {
d052b9b7
AV		 10760 case 's':
10761 if (val <= 3)
10762 func (stream, "%s", mve_vec_sizename[val]);
10763 else
10764 func (stream, "<undef size>");
10765 break;
10766
05413229
NC		 10767 case 'd':
10768 func (stream, "%lu", val);
10769 value_in_comment = val;
10770 break;
ff4a8d2b 10771
f0fba320
RL		 10772 case 'D':
10773 func (stream, "%lu", val + 1);
10774 value_in_comment = val + 1;
10775 break;
10776
05413229
NC		 10777 case 'W':
10778 func (stream, "%lu", val * 4);
10779 value_in_comment = val * 4;
10780 break;
ff4a8d2b 10781
f1c7f421
AV		 10782 case 'S':
10783 if (val == 13)
10784 is_unpredictable = TRUE;
10785 /* Fall through. */
ff4a8d2b
NC		 10786 case 'R':
10787 if (val == 15)
10788 is_unpredictable = TRUE;
10789 /* Fall through. */
10790 case 'r':
10791 func (stream, "%s", arm_regnames[val]);
10792 break;
c19d1205
ZW		 10793
10794 case 'c':
c22aaad1 10795 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 10796 break;
10797
10798 case '\'':
c19d1205 10799 c++;
16980d0b
JB		 10800 if (val == ((1ul << width) - 1))
10801 func (stream, "%c", *c);
c19d1205 10802 break;
43e65147 10803
c19d1205 10804 case '`':
c19d1205 10805 c++;
16980d0b
JB		 10806 if (val == 0)
10807 func (stream, "%c", *c);
c19d1205
ZW		 10808 break;
10809
10810 case '?':
fe56b6ce 10811 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 10812 c += 1 << width;
c19d1205 10813 break;
43e65147 10814
0bb027fd
RR		 10815 case 'x':
10816 func (stream, "0x%lx", val & 0xffffffffUL);
10817 break;
c19d1205
ZW		 10818
10819 default:
10820 abort ();
10821 }
10822 }
10823 break;
10824
32a94698
NC		 10825 case 'L':
10826 /* PR binutils/12534
10827 If we have a PC relative offset in an LDRD or STRD
10828 instructions then display the decoded address. */
10829 if (((given >> 16) & 0xf) == 0xf)
10830 {
10831 bfd_vma offset = (given & 0xff) * 4;
10832
10833 if ((given & (1 << 23)) == 0)
10834 offset = - offset;
10835 func (stream, "\t; ");
10836 info->print_address_func ((pc & ~3) + 4 + offset, info);
10837 }
10838 break;
10839
c19d1205
ZW		 10840 default:
10841 abort ();
10842 }
10843 }
05413229
NC		 10844
10845 if (value_in_comment > 32 || value_in_comment < -16)
10846 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 10847
10848 if (is_unpredictable)
10849 func (stream, UNPREDICTABLE_INSTRUCTION);
10850
4a5329c6 10851 return;
c19d1205 10852 }
252b5132 10853
58efb6c0 10854 /* No match. */
0b347048
TC		 10855 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10856 return;
252b5132
RH		 10857}
10858
e821645d
DJ		 10859/* Print data bytes on INFO->STREAM. */
10860
10861static void
fe56b6ce
NC		 10862print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
10863 struct disassemble_info *info,
e821645d
DJ		 10864 long given)
10865{
10866 switch (info->bytes_per_chunk)
10867 {
10868 case 1:
10869 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
10870 break;
10871 case 2:
10872 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
10873 break;
10874 case 4:
10875 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
10876 break;
10877 default:
10878 abort ();
10879 }
10880}
10881
22a398e1 10882/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 10883 being displayed in symbol relative addresses.
10884
10885 Also disallow private symbol, with __tagsym$$ prefix,
10886 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 10887
10888bfd_boolean
10889arm_symbol_is_valid (asymbol * sym,
10890 struct disassemble_info * info ATTRIBUTE_UNUSED)
10891{
10892 const char * name;
43e65147 10893
22a398e1
NC		 10894 if (sym == NULL)
10895 return FALSE;
10896
10897 name = bfd_asymbol_name (sym);
10898
d8282f0e 10899 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 10900}
10901
65b48a81 10902/* Parse the string of disassembler options. */
baf0cc5e 10903
65b48a81 10904static void
f995bbe8 10905parse_arm_disassembler_options (const char *options)
dd92f639 10906{
f995bbe8 10907 const char *opt;
b34976b6 10908
65b48a81 10909 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 10910 {
65b48a81
PB		 10911 if (CONST_STRNEQ (opt, "reg-names-"))
10912 {
10913 unsigned int i;
10914 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10915 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
10916 {
10917 regname_selected = i;
10918 break;
10919 }
b34976b6 10920
65b48a81 10921 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 10922 /* xgettext: c-format */
10923 opcodes_error_handler (_("unrecognised register name set: %s"),
10924 opt);
65b48a81
PB		 10925 }
10926 else if (CONST_STRNEQ (opt, "force-thumb"))
10927 force_thumb = 1;
10928 else if (CONST_STRNEQ (opt, "no-force-thumb"))
10929 force_thumb = 0;
10930 else
a6743a54
AM		 10931 /* xgettext: c-format */
10932 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 10933 }
b34976b6 10934
dd92f639
NC		 10935 return;
10936}
10937
5bc5ae88
RL		 10938static bfd_boolean
10939mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10940 enum map_type *map_symbol);
10941
c22aaad1
PB		 10942/* Search back through the insn stream to determine if this instruction is
10943 conditionally executed. */
fe56b6ce 10944
c22aaad1 10945static void
fe56b6ce
NC		 10946find_ifthen_state (bfd_vma pc,
10947 struct disassemble_info *info,
c22aaad1
PB		 10948 bfd_boolean little)
10949{
10950 unsigned char b[2];
10951 unsigned int insn;
10952 int status;
10953 /* COUNT is twice the number of instructions seen. It will be odd if we
10954 just crossed an instruction boundary. */
10955 int count;
10956 int it_count;
10957 unsigned int seen_it;
10958 bfd_vma addr;
10959
10960 ifthen_address = pc;
10961 ifthen_state = 0;
10962
10963 addr = pc;
10964 count = 1;
10965 it_count = 0;
10966 seen_it = 0;
10967 /* Scan backwards looking for IT instructions, keeping track of where
10968 instruction boundaries are. We don't know if something is actually an
10969 IT instruction until we find a definite instruction boundary. */
10970 for (;;)
10971 {
fe56b6ce 10972 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 10973 {
10974 /* A symbol must be on an instruction boundary, and will not
10975 be within an IT block. */
10976 if (seen_it && (count & 1))
10977 break;
10978
10979 return;
10980 }
10981 addr -= 2;
fe56b6ce 10982 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 10983 if (status)
10984 return;
10985
10986 if (little)
10987 insn = (b[0]) | (b[1] << 8);
10988 else
10989 insn = (b[1]) | (b[0] << 8);
10990 if (seen_it)
10991 {
10992 if ((insn & 0xf800) < 0xe800)
10993 {
10994 /* Addr + 2 is an instruction boundary. See if this matches
10995 the expected boundary based on the position of the last
10996 IT candidate. */
10997 if (count & 1)
10998 break;
10999 seen_it = 0;
11000 }
11001 }
11002 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11003 {
5bc5ae88
RL		 11004 enum map_type type = MAP_ARM;
11005 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11006
11007 if (!found || (found && type == MAP_THUMB))
11008 {
11009 /* This could be an IT instruction. */
11010 seen_it = insn;
11011 it_count = count >> 1;
11012 }
c22aaad1
PB		 11013 }
11014 if ((insn & 0xf800) >= 0xe800)
11015 count++;
11016 else
11017 count = (count + 2) | 1;
11018 /* IT blocks contain at most 4 instructions. */
11019 if (count >= 8 && !seen_it)
11020 return;
11021 }
11022 /* We found an IT instruction. */
11023 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11024 if ((ifthen_state & 0xf) == 0)
11025 ifthen_state = 0;
11026}
11027
b0e28b39
DJ		 11028/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11029 mapping symbol. */
11030
11031static int
11032is_mapping_symbol (struct disassemble_info *info, int n,
11033 enum map_type *map_type)
11034{
11035 const char *name;
11036
11037 name = bfd_asymbol_name (info->symtab[n]);
11038 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11039 && (name[2] == 0 || name[2] == '.'))
11040 {
11041 *map_type = ((name[1] == 'a') ? MAP_ARM
11042 : (name[1] == 't') ? MAP_THUMB
11043 : MAP_DATA);
11044 return TRUE;
11045 }
11046
11047 return FALSE;
11048}
11049
11050/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11051 Returns nonzero if *MAP_TYPE was set. */
11052
11053static int
11054get_map_sym_type (struct disassemble_info *info,
11055 int n,
11056 enum map_type *map_type)
11057{
11058 /* If the symbol is in a different section, ignore it. */
11059 if (info->section != NULL && info->section != info->symtab[n]->section)
11060 return FALSE;
11061
11062 return is_mapping_symbol (info, n, map_type);
11063}
11064
11065/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11066 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11067
11068static int
fe56b6ce
NC		 11069get_sym_code_type (struct disassemble_info *info,
11070 int n,
e821645d 11071 enum map_type *map_type)
2087ad84
PB		 11072{
11073 elf_symbol_type *es;
11074 unsigned int type;
b0e28b39
DJ		 11075
11076 /* If the symbol is in a different section, ignore it. */
11077 if (info->section != NULL && info->section != info->symtab[n]->section)
11078 return FALSE;
2087ad84 11079
e821645d 11080 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11081 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11082
11083 /* If the symbol has function type then use that. */
34e77a92 11084 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11085 {
39d911fc
TP		 11086 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11087 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11088 *map_type = MAP_THUMB;
11089 else
11090 *map_type = MAP_ARM;
2087ad84
PB		 11091 return TRUE;
11092 }
11093
2087ad84
PB		 11094 return FALSE;
11095}
11096
5bc5ae88
RL		 11097/* Search the mapping symbol state for instruction at pc. This is only
11098 applicable for elf target.
11099
11100 There is an assumption Here, info->private_data contains the correct AND
11101 up-to-date information about current scan process. The information will be
11102 used to speed this search process.
11103
11104 Return TRUE if the mapping state can be determined, and map_symbol
11105 will be updated accordingly. Otherwise, return FALSE. */
11106
11107static bfd_boolean
11108mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11109 enum map_type *map_symbol)
11110{
796d6298
TC		 11111 bfd_vma addr, section_vma = 0;
11112 int n, last_sym = -1;
5bc5ae88 11113 bfd_boolean found = FALSE;
796d6298
TC		 11114 bfd_boolean can_use_search_opt_p = FALSE;
11115
11116 /* Default to DATA. A text section is required by the ABI to contain an
11117 INSN mapping symbol at the start. A data section has no such
11118 requirement, hence if no mapping symbol is found the section must
11119 contain only data. This however isn't very useful if the user has
11120 fully stripped the binaries. If this is the case use the section
11121 attributes to determine the default. If we have no section default to
11122 INSN as well, as we may be disassembling some raw bytes on a baremetal
11123 HEX file or similar. */
11124 enum map_type type = MAP_DATA;
11125 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11126 type = MAP_ARM;
5bc5ae88
RL		 11127 struct arm_private_data *private_data;
11128
796d6298 11129 if (info->private_data == NULL
5bc5ae88
RL		 11130 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11131 return FALSE;
11132
11133 private_data = info->private_data;
5bc5ae88 11134
796d6298
TC		 11135 /* First, look for mapping symbols. */
11136 if (info->symtab_size != 0)
11137 {
11138 if (pc <= private_data->last_mapping_addr)
11139 private_data->last_mapping_sym = -1;
11140
11141 /* Start scanning at the start of the function, or wherever
11142 we finished last time. */
11143 n = info->symtab_pos + 1;
11144
11145 /* If the last stop offset is different from the current one it means we
11146 are disassembling a different glob of bytes. As such the optimization
11147 would not be safe and we should start over. */
11148 can_use_search_opt_p
11149 = private_data->last_mapping_sym >= 0
11150 && info->stop_offset == private_data->last_stop_offset;
11151
11152 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11153 n = private_data->last_mapping_sym;
11154
11155 /* Look down while we haven't passed the location being disassembled.
11156 The reason for this is that there's no defined order between a symbol
11157 and an mapping symbol that may be at the same address. We may have to
11158 look at least one position ahead. */
11159 for (; n < info->symtab_size; n++)
11160 {
11161 addr = bfd_asymbol_value (info->symtab[n]);
11162 if (addr > pc)
11163 break;
11164 if (get_map_sym_type (info, n, &type))
11165 {
11166 last_sym = n;
11167 found = TRUE;
11168 }
11169 }
5bc5ae88 11170
796d6298
TC		 11171 if (!found)
11172 {
11173 n = info->symtab_pos;
11174 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11175 n = private_data->last_mapping_sym;
11176
11177 /* No mapping symbol found at this address. Look backwards
11178 for a preceeding one, but don't go pass the section start
11179 otherwise a data section with no mapping symbol can pick up
11180 a text mapping symbol of a preceeding section. The documentation
11181 says section can be NULL, in which case we will seek up all the
11182 way to the top. */
11183 if (info->section)
11184 section_vma = info->section->vma;
11185
11186 for (; n >= 0; n--)
11187 {
11188 addr = bfd_asymbol_value (info->symtab[n]);
11189 if (addr < section_vma)
11190 break;
11191
11192 if (get_map_sym_type (info, n, &type))
11193 {
11194 last_sym = n;
11195 found = TRUE;
11196 break;
11197 }
11198 }
11199 }
11200 }
11201
11202 /* If no mapping symbol was found, try looking up without a mapping
11203 symbol. This is done by walking up from the current PC to the nearest
11204 symbol. We don't actually have to loop here since symtab_pos will
11205 contain the nearest symbol already. */
11206 if (!found)
5bc5ae88 11207 {
796d6298
TC		 11208 n = info->symtab_pos;
11209 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11210 {
796d6298
TC		 11211 last_sym = n;
11212 found = TRUE;
5bc5ae88
RL		 11213 }
11214 }
11215
796d6298
TC		 11216 private_data->last_mapping_sym = last_sym;
11217 private_data->last_type = type;
11218 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11219
11220 *map_symbol = type;
11221 return found;
11222}
11223
0313a2b8
NC		 11224/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11225 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11226 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11227
11228 FIXME: This could more efficiently implemented as a constant array,
11229 although it would also be less robust. */
11230
11231static void
11232select_arm_features (unsigned long mach,
11233 arm_feature_set * features)
11234{
c0c468d5
TP		 11235 arm_feature_set arch_fset;
11236 const arm_feature_set fpu_any = FPU_ANY;
11237
1af1dd51
MW		 11238#undef ARM_SET_FEATURES
11239#define ARM_SET_FEATURES(FSET) \
11240 { \
11241 const arm_feature_set fset = FSET; \
c0c468d5 11242 arch_fset = fset; \
1af1dd51 11243 }
823d2571 11244
c0c468d5
TP		 11245 /* When several architecture versions share the same bfd_mach_arm_XXX value
11246 the most featureful is chosen. */
0313a2b8
NC		 11247 switch (mach)
11248 {
c0c468d5
TP		 11249 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11250 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11251 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11252 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11253 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11254 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11255 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11256 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11257 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11258 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11259 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11260 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11261 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11262 break;
c0c468d5
TP		 11263 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11264 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11265 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11266 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11267 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11268 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11269 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11270 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11271 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11272 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11273 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11274 case bfd_mach_arm_8:
11275 {
0632eeea
SD		 11276 /* Add bits for extensions that Armv8.5-A recognizes. */
11277 arm_feature_set armv8_5_ext_fset
11278 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11279 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11280 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 11281 break;
11282 }
11283 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11284 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11285 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 11286 case bfd_mach_arm_8_1M_MAIN:
11287 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11288 force_thumb = 1;
11289 break;
c0c468d5
TP		 11290 /* If the machine type is unknown allow all architecture types and all
11291 extensions. */
11292 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 11293 default:
11294 abort ();
11295 }
1af1dd51 11296#undef ARM_SET_FEATURES
c0c468d5
TP		 11297
11298 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11299 and thus on bfd_mach_arm_XXX value. Therefore for a given
11300 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11301 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 11302}
11303
11304
58efb6c0
NC		 11305/* NOTE: There are no checks in these routines that
11306 the relevant number of data bytes exist. */
baf0cc5e 11307
58efb6c0 11308static int
4a5329c6 11309print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 11310{
c19d1205
ZW		 11311 unsigned char b[4];
11312 long given;
11313 int status;
e821645d 11314 int is_thumb = FALSE;
b0e28b39 11315 int is_data = FALSE;
bd2e2557 11316 int little_code;
e821645d 11317 unsigned int size = 4;
4a5329c6 11318 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 11319 bfd_boolean found = FALSE;
b0e28b39 11320 struct arm_private_data *private_data;
58efb6c0 11321
dd92f639
NC		 11322 if (info->disassembler_options)
11323 {
65b48a81 11324 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 11325
58efb6c0 11326 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 11327 info->disassembler_options = NULL;
11328 }
b34976b6 11329
0313a2b8
NC		 11330 /* PR 10288: Control which instructions will be disassembled. */
11331 if (info->private_data == NULL)
11332 {
b0e28b39 11333 static struct arm_private_data private;
0313a2b8
NC		 11334
11335 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11336 /* If the user did not use the -m command line switch then default to
11337 disassembling all types of ARM instruction.
43e65147 11338
0313a2b8
NC		 11339 The info->mach value has to be ignored as this will be based on
11340 the default archictecture for the target and/or hints in the notes
11341 section, but it will never be greater than the current largest arm
11342 machine value (iWMMXt2), which is only equivalent to the V5TE
11343 architecture. ARM architectures have advanced beyond the machine
11344 value encoding, and these newer architectures would be ignored if
11345 the machine value was used.
11346
11347 Ie the -m switch is used to restrict which instructions will be
11348 disassembled. If it is necessary to use the -m switch to tell
11349 objdump that an ARM binary is being disassembled, eg because the
11350 input is a raw binary file, but it is also desired to disassemble
11351 all ARM instructions then use "-marm". This will select the
11352 "unknown" arm architecture which is compatible with any ARM
11353 instruction. */
11354 info->mach = bfd_mach_arm_unknown;
11355
11356 /* Compute the architecture bitmask from the machine number.
11357 Note: This assumes that the machine number will not change
11358 during disassembly.... */
b0e28b39 11359 select_arm_features (info->mach, & private.features);
0313a2b8 11360
1fbaefec
PB		 11361 private.last_mapping_sym = -1;
11362 private.last_mapping_addr = 0;
796d6298 11363 private.last_stop_offset = 0;
b0e28b39
DJ		 11364
11365 info->private_data = & private;
0313a2b8 11366 }
b0e28b39
DJ		 11367
11368 private_data = info->private_data;
11369
bd2e2557
SS		 11370 /* Decide if our code is going to be little-endian, despite what the
11371 function argument might say. */
11372 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11373
b0e28b39
DJ		 11374 /* For ELF, consult the symbol table to determine what kind of code
11375 or data we have. */
8977d4b2 11376 if (info->symtab_size != 0
e821645d
DJ		 11377 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11378 {
11379 bfd_vma addr;
796d6298 11380 int n;
e821645d 11381 int last_sym = -1;
b0e28b39 11382 enum map_type type = MAP_ARM;
e821645d 11383
796d6298
TC		 11384 found = mapping_symbol_for_insn (pc, info, &type);
11385 last_sym = private_data->last_mapping_sym;
e821645d 11386
1fbaefec
PB		 11387 is_thumb = (private_data->last_type == MAP_THUMB);
11388 is_data = (private_data->last_type == MAP_DATA);
b34976b6 11389
e821645d
DJ		 11390 /* Look a little bit ahead to see if we should print out
11391 two or four bytes of data. If there's a symbol,
11392 mapping or otherwise, after two bytes then don't
11393 print more. */
11394 if (is_data)
11395 {
11396 size = 4 - (pc & 3);
11397 for (n = last_sym + 1; n < info->symtab_size; n++)
11398 {
11399 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 11400 if (addr > pc
11401 && (info->section == NULL
11402 || info->section == info->symtab[n]->section))
e821645d
DJ		 11403 {
11404 if (addr - pc < size)
11405 size = addr - pc;
11406 break;
11407 }
11408 }
11409 /* If the next symbol is after three bytes, we need to
11410 print only part of the data, so that we can use either
11411 .byte or .short. */
11412 if (size == 3)
11413 size = (pc & 1) ? 1 : 2;
11414 }
11415 }
11416
11417 if (info->symbols != NULL)
252b5132 11418 {
5876e06d
NC		 11419 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11420 {
2f0ca46a 11421 coff_symbol_type * cs;
b34976b6 11422
5876e06d
NC		 11423 cs = coffsymbol (*info->symbols);
11424 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11425 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11426 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11427 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11428 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11429 }
e821645d
DJ		 11430 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11431 && !found)
5876e06d 11432 {
2087ad84
PB		 11433 /* If no mapping symbol has been found then fall back to the type
11434 of the function symbol. */
e821645d
DJ		 11435 elf_symbol_type * es;
11436 unsigned int type;
2087ad84 11437
e821645d
DJ		 11438 es = *(elf_symbol_type **)(info->symbols);
11439 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 11440
39d911fc
TP		 11441 is_thumb =
11442 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11443 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 11444 }
e49d43ff
TG		 11445 else if (bfd_asymbol_flavour (*info->symbols)
11446 == bfd_target_mach_o_flavour)
11447 {
11448 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11449
11450 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11451 }
5876e06d 11452 }
b34976b6 11453
e821645d
DJ		 11454 if (force_thumb)
11455 is_thumb = TRUE;
11456
b8f9ee44
CL		 11457 if (is_data)
11458 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11459 else
11460 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11461
c19d1205 11462 info->bytes_per_line = 4;
252b5132 11463
1316c8b3
NC		 11464 /* PR 10263: Disassemble data if requested to do so by the user. */
11465 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 11466 {
11467 int i;
11468
1316c8b3 11469 /* Size was already set above. */
e821645d
DJ		 11470 info->bytes_per_chunk = size;
11471 printer = print_insn_data;
11472
fe56b6ce 11473 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 11474 given = 0;
11475 if (little)
11476 for (i = size - 1; i >= 0; i--)
11477 given = b[i] | (given << 8);
11478 else
11479 for (i = 0; i < (int) size; i++)
11480 given = b[i] | (given << 8);
11481 }
11482 else if (!is_thumb)
252b5132 11483 {
c19d1205
ZW		 11484 /* In ARM mode endianness is a straightforward issue: the instruction
11485 is four bytes long and is either ordered 0123 or 3210. */
11486 printer = print_insn_arm;
11487 info->bytes_per_chunk = 4;
4a5329c6 11488 size = 4;
c19d1205 11489
0313a2b8 11490 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 11491 if (little_code)
c19d1205
ZW		 11492 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11493 else
11494 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 11495 }
58efb6c0 11496 else
252b5132 11497 {
c19d1205
ZW		 11498 /* In Thumb mode we have the additional wrinkle of two
11499 instruction lengths. Fortunately, the bits that determine
11500 the length of the current instruction are always to be found
11501 in the first two bytes. */
4a5329c6 11502 printer = print_insn_thumb16;
c19d1205 11503 info->bytes_per_chunk = 2;
4a5329c6
ZW		 11504 size = 2;
11505
fe56b6ce 11506 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 11507 if (little_code)
9a2ff3f5
AM		 11508 given = (b[0]) | (b[1] << 8);
11509 else
11510 given = (b[1]) | (b[0] << 8);
11511
c19d1205 11512 if (!status)
252b5132 11513 {
c19d1205
ZW		 11514 /* These bit patterns signal a four-byte Thumb
11515 instruction. */
11516 if ((given & 0xF800) == 0xF800
11517 || (given & 0xF800) == 0xF000
11518 || (given & 0xF800) == 0xE800)
252b5132 11519 {
0313a2b8 11520 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 11521 if (little_code)
c19d1205 11522 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 11523 else
c19d1205
ZW		 11524 given = (b[1]) | (b[0] << 8) | (given << 16);
11525
11526 printer = print_insn_thumb32;
4a5329c6 11527 size = 4;
252b5132 11528 }
252b5132 11529 }
c22aaad1
PB		 11530
11531 if (ifthen_address != pc)
0313a2b8 11532 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 11533
11534 if (ifthen_state)
11535 {
11536 if ((ifthen_state & 0xf) == 0x8)
11537 ifthen_next_state = 0;
11538 else
11539 ifthen_next_state = (ifthen_state & 0xe0)
11540 | ((ifthen_state & 0xf) << 1);
11541 }
252b5132 11542 }
b34976b6 11543
c19d1205
ZW		 11544 if (status)
11545 {
11546 info->memory_error_func (status, pc, info);
11547 return -1;
11548 }
6a56ec7e
NC		 11549 if (info->flags & INSN_HAS_RELOC)
11550 /* If the instruction has a reloc associated with it, then
11551 the offset field in the instruction will actually be the
11552 addend for the reloc. (We are using REL type relocs).
11553 In such cases, we can ignore the pc when computing
11554 addresses, since the addend is not currently pc-relative. */
11555 pc = 0;
b34976b6 11556
4a5329c6 11557 printer (pc, info, given);
c22aaad1
PB		 11558
11559 if (is_thumb)
11560 {
11561 ifthen_state = ifthen_next_state;
11562 ifthen_address += size;
11563 }
4a5329c6 11564 return size;
252b5132
RH		 11565}
11566
11567int
4a5329c6 11568print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 11569{
bd2e2557
SS		 11570 /* Detect BE8-ness and record it in the disassembler info. */
11571 if (info->flavour == bfd_target_elf_flavour
11572 && info->section != NULL
11573 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11574 info->endian_code = BFD_ENDIAN_LITTLE;
11575
b34976b6 11576 return print_insn (pc, info, FALSE);
58efb6c0 11577}
01c7f630 11578
58efb6c0 11579int
4a5329c6 11580print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11581{
b34976b6 11582 return print_insn (pc, info, TRUE);
58efb6c0 11583}
252b5132 11584
471b9d15 11585const disasm_options_and_args_t *
65b48a81
PB		 11586disassembler_options_arm (void)
11587{
471b9d15 11588 static disasm_options_and_args_t *opts_and_args;
65b48a81 11589
471b9d15 11590 if (opts_and_args == NULL)
65b48a81 11591 {
471b9d15 11592 disasm_options_t *opts;
65b48a81 11593 unsigned int i;
471b9d15
MR		 11594
11595 opts_and_args = XNEW (disasm_options_and_args_t);
11596 opts_and_args->args = NULL;
11597
11598 opts = &opts_and_args->options;
65b48a81
PB		 11599 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11600 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11601 opts->arg = NULL;
65b48a81
PB		 11602 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11603 {
11604 opts->name[i] = regnames[i].name;
11605 if (regnames[i].description != NULL)
11606 opts->description[i] = _(regnames[i].description);
11607 else
11608 opts->description[i] = NULL;
11609 }
11610 /* The array we return must be NULL terminated. */
11611 opts->name[i] = NULL;
11612 opts->description[i] = NULL;
11613 }
11614
471b9d15 11615 return opts_and_args;
65b48a81
PB		 11616}
11617
58efb6c0 11618void
4a5329c6 11619print_arm_disassembler_options (FILE *stream)
58efb6c0 11620{
65b48a81 11621 unsigned int i, max_len = 0;
58efb6c0
NC		 11622 fprintf (stream, _("\n\
11623The following ARM specific disassembler options are supported for use with\n\
11624the -M switch:\n"));
b34976b6 11625
65b48a81
PB		 11626 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11627 {
11628 unsigned int len = strlen (regnames[i].name);
11629 if (max_len < len)
11630 max_len = len;
11631 }
58efb6c0 11632
65b48a81
PB		 11633 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11634 fprintf (stream, " %s%*c %s\n",
11635 regnames[i].name,
11636 (int)(max_len - strlen (regnames[i].name)), ' ',
11637 _(regnames[i].description));
252b5132 11638}
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