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arch-mx6: fix MX6_PAD_DECLARE macro to work with MX6 duallite
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
CommitLineData
23608e23
JL		 1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
23608e23
JL		 5 */
6
7#include <common.h>
5a660169 8#include <div64.h>
23608e23
JL		 9#include <asm/io.h>
10#include <asm/errno.h>
11#include <asm/arch/imx-regs.h>
6a376046 12#include <asm/arch/crm_regs.h>
23608e23 13#include <asm/arch/clock.h>
6a376046 14#include <asm/arch/sys_proto.h>
23608e23
JL		 15
16enum pll_clocks {
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
9ba18ff8
PF		 21 PLL_AUDIO, /* AUDIO PLL */
22 PLL_VIDEO, /* AUDIO PLL */
23608e23
JL		 23};
24
6a376046 25struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
23608e23 26
112fd2ec
BT		 27#ifdef CONFIG_MXC_OCOTP
28void enable_ocotp_clk(unsigned char enable)
29{
30 u32 reg;
31
32 reg = __raw_readl(&imx_ccm->CCGR2);
33 if (enable)
34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 else
36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
37 __raw_writel(reg, &imx_ccm->CCGR2);
38}
39#endif
40
224beb83
NK		 41#ifdef CONFIG_NAND_MXS
42void setup_gpmi_io_clk(u32 cfg)
43{
44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm->CCGR4,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
51
90447ef0
YL		 52#if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
54
55 clrsetbits_le32(&imx_ccm->cs2cdr,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
59 cfg);
60
61 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
62#else
224beb83
NK		 63 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
64
65 clrsetbits_le32(&imx_ccm->cs2cdr,
66 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
67 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
68 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
69 cfg);
70
71 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
90447ef0 72#endif
224beb83
NK		 73 setbits_le32(&imx_ccm->CCGR4,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
79}
80#endif
81
3f467529
WG		 82void enable_usboh3_clk(unsigned char enable)
83{
84 u32 reg;
85
86 reg = __raw_readl(&imx_ccm->CCGR6);
87 if (enable)
0bb7e316 88 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
3f467529 89 else
0bb7e316 90 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
3f467529
WG		 91 __raw_writel(reg, &imx_ccm->CCGR6);
92
93}
94
3d8f1798 95#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
224beb83
NK		 96void enable_enet_clk(unsigned char enable)
97{
43cb127b
PF		 98 u32 mask, *addr;
99
b949fd2c 100 if (is_mx6ul()) {
43cb127b
PF		 101 mask = MXC_CCM_CCGR3_ENET_MASK;
102 addr = &imx_ccm->CCGR3;
103 } else {
104 mask = MXC_CCM_CCGR1_ENET_MASK;
105 addr = &imx_ccm->CCGR1;
106 }
224beb83
NK		 107
108 if (enable)
43cb127b 109 setbits_le32(addr, mask);
224beb83 110 else
43cb127b 111 clrbits_le32(addr, mask);
224beb83
NK		 112}
113#endif
114
115#ifdef CONFIG_MXC_UART
116void enable_uart_clk(unsigned char enable)
117{
43cb127b
PF		 118 u32 mask;
119
b949fd2c 120 if (is_mx6ul())
43cb127b
PF		 121 mask = MXC_CCM_CCGR5_UART_MASK;
122 else
123 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
224beb83
NK		 124
125 if (enable)
126 setbits_le32(&imx_ccm->CCGR5, mask);
127 else
128 clrbits_le32(&imx_ccm->CCGR5, mask);
129}
130#endif
131
224beb83
NK		 132#ifdef CONFIG_MMC
133int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
134{
135 u32 mask;
136
137 if (bus_num > 3)
138 return -EINVAL;
139
140 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
141 if (enable)
142 setbits_le32(&imx_ccm->CCGR6, mask);
143 else
144 clrbits_le32(&imx_ccm->CCGR6, mask);
145
146 return 0;
147}
148#endif
149
fac96408 150#ifdef CONFIG_SYS_I2C_MXC
21a26940 151/* i2c_num can be from 0 - 3 */
cc54a0f7
TK		 152int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
153{
154 u32 reg;
155 u32 mask;
19c6ec70 156 u32 *addr;
cc54a0f7 157
21a26940 158 if (i2c_num > 3)
cc54a0f7 159 return -EINVAL;
21a26940
HS		 160 if (i2c_num < 3) {
161 mask = MXC_CCM_CCGR_CG_MASK
162 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
163 + (i2c_num << 1));
164 reg = __raw_readl(&imx_ccm->CCGR2);
165 if (enable)
166 reg |= mask;
167 else
168 reg &= ~mask;
169 __raw_writel(reg, &imx_ccm->CCGR2);
170 } else {
b949fd2c 171 if (is_mx6sx() || is_mx6ul()) {
19c6ec70
PF		 172 mask = MXC_CCM_CCGR6_I2C4_MASK;
173 addr = &imx_ccm->CCGR6;
174 } else {
175 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
176 addr = &imx_ccm->CCGR1;
177 }
178 reg = __raw_readl(addr);
21a26940
HS		 179 if (enable)
180 reg |= mask;
181 else
182 reg &= ~mask;
19c6ec70 183 __raw_writel(reg, addr);
21a26940 184 }
cc54a0f7
TK		 185 return 0;
186}
187#endif
188
a0ae0091
HS		 189/* spi_num can be from 0 - SPI_MAX_NUM */
190int enable_spi_clk(unsigned char enable, unsigned spi_num)
191{
192 u32 reg;
193 u32 mask;
194
195 if (spi_num > SPI_MAX_NUM)
196 return -EINVAL;
197
198 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
199 reg = __raw_readl(&imx_ccm->CCGR1);
200 if (enable)
201 reg |= mask;
202 else
203 reg &= ~mask;
204 __raw_writel(reg, &imx_ccm->CCGR1);
205 return 0;
206}
23608e23
JL		 207static u32 decode_pll(enum pll_clocks pll, u32 infreq)
208{
9ba18ff8 209 u32 div, test_div, pll_num, pll_denom;
23608e23
JL		 210
211 switch (pll) {
212 case PLL_SYS:
213 div = __raw_readl(&imx_ccm->analog_pll_sys);
214 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
215
2eb268f6 216 return (infreq * div) >> 1;
23608e23
JL		 217 case PLL_BUS:
218 div = __raw_readl(&imx_ccm->analog_pll_528);
219 div &= BM_ANADIG_PLL_528_DIV_SELECT;
220
221 return infreq * (20 + (div << 1));
222 case PLL_USBOTG:
223 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
224 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
225
226 return infreq * (20 + (div << 1));
227 case PLL_ENET:
228 div = __raw_readl(&imx_ccm->analog_pll_enet);
229 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
230
89cfd0f5 231 return 25000000 * (div + (div >> 1) + 1);
9ba18ff8
PF		 232 case PLL_AUDIO:
233 div = __raw_readl(&imx_ccm->analog_pll_audio);
234 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
235 return 0;
236 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
237 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
238 return MXC_HCLK;
239 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
240 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
241 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
242 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
243 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
244 if (test_div == 3) {
245 debug("Error test_div\n");
246 return 0;
247 }
248 test_div = 1 << (2 - test_div);
249
250 return infreq * (div + pll_num / pll_denom) / test_div;
251 case PLL_VIDEO:
252 div = __raw_readl(&imx_ccm->analog_pll_video);
253 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
254 return 0;
255 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
256 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
257 return MXC_HCLK;
258 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
259 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
260 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
261 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
262 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
263 if (test_div == 3) {
264 debug("Error test_div\n");
265 return 0;
266 }
267 test_div = 1 << (2 - test_div);
268
269 return infreq * (div + pll_num / pll_denom) / test_div;
23608e23
JL		 270 default:
271 return 0;
272 }
273 /* NOTREACHED */
274}
762a88cc
PA		 275static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
276{
277 u32 div;
278 u64 freq;
279
280 switch (pll) {
281 case PLL_BUS:
b949fd2c 282 if (!is_mx6ul()) {
43cb127b
PF		 283 if (pfd_num == 3) {
284 /* No PFD3 on PPL2 */
285 return 0;
286 }
762a88cc
PA		 287 }
288 div = __raw_readl(&imx_ccm->analog_pfd_528);
289 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
290 break;
291 case PLL_USBOTG:
292 div = __raw_readl(&imx_ccm->analog_pfd_480);
293 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
294 break;
295 default:
296 /* No PFD on other PLL */
297 return 0;
298 }
299
5a660169 300 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
762a88cc
PA		 301 ANATOP_PFD_FRAC_SHIFT(pfd_num));
302}
23608e23
JL		 303
304static u32 get_mcu_main_clk(void)
305{
306 u32 reg, freq;
307
308 reg = __raw_readl(&imx_ccm->cacrr);
309 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
310 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
833b6435 311 freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23
JL		 312
313 return freq / (reg + 1);
314}
315
6a376046 316u32 get_periph_clk(void)
23608e23 317{
43cb127b 318 u32 reg, div = 0, freq = 0;
23608e23
JL		 319
320 reg = __raw_readl(&imx_ccm->cbcdr);
321 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
43cb127b
PF		 322 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
323 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
23608e23
JL		 324 reg = __raw_readl(&imx_ccm->cbcmr);
325 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
326 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
327
328 switch (reg) {
329 case 0:
833b6435 330 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23
JL		 331 break;
332 case 1:
333 case 2:
833b6435 334 freq = MXC_HCLK;
23608e23
JL		 335 break;
336 default:
337 break;
338 }
339 } else {
340 reg = __raw_readl(&imx_ccm->cbcmr);
341 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
342 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
343
344 switch (reg) {
345 case 0:
833b6435 346 freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23
JL		 347 break;
348 case 1:
762a88cc 349 freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23
JL		 350 break;
351 case 2:
762a88cc 352 freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23
JL		 353 break;
354 case 3:
762a88cc
PA		 355 /* static / 2 divider */
356 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
23608e23
JL		 357 break;
358 default:
359 break;
360 }
361 }
362
43cb127b 363 return freq / (div + 1);
23608e23
JL		 364}
365
23608e23
JL		 366static u32 get_ipg_clk(void)
367{
368 u32 reg, ipg_podf;
369
370 reg = __raw_readl(&imx_ccm->cbcdr);
371 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
372 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
373
374 return get_ahb_clk() / (ipg_podf + 1);
375}
376
377static u32 get_ipg_per_clk(void)
378{
379 u32 reg, perclk_podf;
380
381 reg = __raw_readl(&imx_ccm->cscmr1);
b949fd2c
PF		 382 if (is_mx6sl() || is_mx6sx() ||
383 is_mx6dqp() || is_mx6ul()) {
e1c2d68b
PF		 384 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
385 return MXC_HCLK; /* OSC 24Mhz */
386 }
387
23608e23
JL		 388 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
389
390 return get_ipg_clk() / (perclk_podf + 1);
391}
392
393static u32 get_uart_clk(void)
394{
395 u32 reg, uart_podf;
762a88cc 396 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
23608e23 397 reg = __raw_readl(&imx_ccm->cscdr1);
e1c2d68b 398
b949fd2c 399 if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
e1c2d68b
PF		 400 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
401 freq = MXC_HCLK;
402 }
403
23608e23
JL		 404 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
405 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
406
25b4aa14 407 return freq / (uart_podf + 1);
23608e23
JL		 408}
409
410static u32 get_cspi_clk(void)
411{
412 u32 reg, cspi_podf;
413
414 reg = __raw_readl(&imx_ccm->cscdr2);
e1c2d68b
PF		 415 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
416 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
417
b949fd2c 418 if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
e1c2d68b
PF		 419 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
420 return MXC_HCLK / (cspi_podf + 1);
421 }
23608e23 422
762a88cc 423 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
23608e23
JL		 424}
425
426static u32 get_axi_clk(void)
427{
428 u32 root_freq, axi_podf;
429 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
430
431 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
432 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
433
434 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
435 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
762a88cc 436 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23 437 else
762a88cc 438 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
23608e23
JL		 439 } else
440 root_freq = get_periph_clk();
441
442 return root_freq / (axi_podf + 1);
443}
444
445static u32 get_emi_slow_clk(void)
446{
d55e0dab 447 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
23608e23
JL		 448
449 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
450 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
451 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
d55e0dab
AG		 452 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
453 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
23608e23
JL		 454
455 switch (emi_clk_sel) {
456 case 0:
457 root_freq = get_axi_clk();
458 break;
459 case 1:
833b6435 460 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23
JL		 461 break;
462 case 2:
762a88cc 463 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23
JL		 464 break;
465 case 3:
762a88cc 466 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23
JL		 467 break;
468 }
469
d55e0dab 470 return root_freq / (emi_slow_podf + 1);
23608e23
JL		 471}
472
25b4aa14
FE		 473static u32 get_mmdc_ch0_clk(void)
474{
475 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
476 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
25b4aa14 477
9ba18ff8 478 u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
43cb127b 479
b949fd2c 480 if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
43cb127b
PF		 481 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
482 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
483 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
484 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
485 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
b949fd2c 486 if (is_mx6sl()) {
43cb127b
PF		 487 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
488 freq = MXC_HCLK;
489 else
490 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
491 } else {
492 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
493 freq = decode_pll(PLL_BUS, MXC_HCLK);
494 else
495 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
496 }
497 } else {
498 per2_clk2_podf = 0;
499 switch ((cbcmr &
500 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
501 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
502 case 0:
503 freq = decode_pll(PLL_BUS, MXC_HCLK);
504 break;
505 case 1:
506 freq = mxc_get_pll_pfd(PLL_BUS, 2);
507 break;
508 case 2:
509 freq = mxc_get_pll_pfd(PLL_BUS, 0);
510 break;
511 case 3:
9ba18ff8
PF		 512 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
513 switch (pmu_misc2_audio_div) {
514 case 0:
515 case 2:
516 pmu_misc2_audio_div = 1;
517 break;
518 case 1:
519 pmu_misc2_audio_div = 2;
520 break;
521 case 3:
522 pmu_misc2_audio_div = 4;
523 break;
524 }
525 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
526 pmu_misc2_audio_div;
43cb127b
PF		 527 break;
528 }
529 }
530 return freq / (podf + 1) / (per2_clk2_podf + 1);
531 } else {
532 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
533 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
534 return get_periph_clk() / (podf + 1);
25b4aa14 535 }
25b4aa14 536}
c655b816 537
ad153782
PF		 538#if defined(CONFIG_VIDEO_MXS)
539static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
540 u32 post_div)
541{
542 u32 reg = 0;
543 ulong start;
544
545 debug("pll5 div = %d, num = %d, denom = %d\n",
546 pll_div, pll_num, pll_denom);
547
548 /* Power up PLL5 video */
549 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
550 BM_ANADIG_PLL_VIDEO_BYPASS |
551 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
552 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
553 &imx_ccm->analog_pll_video_clr);
554
555 /* Set div, num and denom */
556 switch (post_div) {
557 case 1:
558 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
559 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
560 &imx_ccm->analog_pll_video_set);
561 break;
562 case 2:
563 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
564 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
565 &imx_ccm->analog_pll_video_set);
566 break;
567 case 4:
568 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
569 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
570 &imx_ccm->analog_pll_video_set);
571 break;
572 default:
573 puts("Wrong test_div!\n");
574 return -EINVAL;
575 }
576
577 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
578 &imx_ccm->analog_pll_video_num);
579 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
580 &imx_ccm->analog_pll_video_denom);
581
582 /* Wait PLL5 lock */
583 start = get_timer(0); /* Get current timestamp */
584
585 do {
586 reg = readl(&imx_ccm->analog_pll_video);
587 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
588 /* Enable PLL out */
589 writel(BM_ANADIG_PLL_VIDEO_ENABLE,
590 &imx_ccm->analog_pll_video_set);
591 return 0;
592 }
593 } while (get_timer(0) < (start + 10)); /* Wait 10ms */
594
595 puts("Lock PLL5 timeout\n");
596
597 return -ETIME;
598}
599
600/*
601 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
602 *
603 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
604 */
605void mxs_set_lcdclk(u32 base_addr, u32 freq)
606{
607 u32 reg = 0;
608 u32 hck = MXC_HCLK / 1000;
609 /* DIV_SELECT ranges from 27 to 54 */
610 u32 min = hck * 27;
611 u32 max = hck * 54;
612 u32 temp, best = 0;
613 u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
614 u32 pll_div, pll_num, pll_denom, post_div = 1;
615
616 debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
617
b949fd2c 618 if (!is_mx6sx() && !is_mx6ul()) {
ad153782
PF		 619 debug("This chip not support lcd!\n");
620 return;
621 }
622
623 if (base_addr == LCDIF1_BASE_ADDR) {
624 reg = readl(&imx_ccm->cscdr2);
625 /* Can't change clocks when clock not from pre-mux */
626 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
627 return;
628 }
629
b949fd2c 630 if (is_mx6sx()) {
ad153782
PF		 631 reg = readl(&imx_ccm->cscdr2);
632 /* Can't change clocks when clock not from pre-mux */
633 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
634 return;
635 }
636
637 temp = freq * max_pred * max_postd;
ad153782
PF		 638 if (temp < min) {
639 /*
640 * Register: PLL_VIDEO
641 * Bit Field: POST_DIV_SELECT
642 * 00 — Divide by 4.
643 * 01 — Divide by 2.
644 * 10 — Divide by 1.
645 * 11 — Reserved
646 * No need to check post_div(1)
647 */
648 for (post_div = 2; post_div <= 4; post_div <<= 1) {
649 if ((temp * post_div) > min) {
650 freq *= post_div;
651 break;
652 }
653 }
654
655 if (post_div > 4) {
656 printf("Fail to set rate to %dkhz", freq);
657 return;
658 }
659 }
660
661 /* Choose the best pred and postd to match freq for lcd */
662 for (i = 1; i <= max_pred; i++) {
663 for (j = 1; j <= max_postd; j++) {
664 temp = freq * i * j;
665 if (temp > max || temp < min)
666 continue;
667 if (best == 0 || temp < best) {
668 best = temp;
669 pred = i;
670 postd = j;
671 }
672 }
673 }
674
675 if (best == 0) {
676 printf("Fail to set rate to %dKHz", freq);
677 return;
678 }
679
680 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
681
682 pll_div = best / hck;
683 pll_denom = 1000000;
684 pll_num = (best - hck * pll_div) * pll_denom / hck;
685
686 /*
687 * pll_num
688 * (24MHz * (pll_div + --------- ))
689 * pll_denom
690 *freq KHz = --------------------------------
691 * post_div * pred * postd * 1000
692 */
693
694 if (base_addr == LCDIF1_BASE_ADDR) {
695 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
696 return;
697
698 /* Select pre-lcd clock to PLL5 and set pre divider */
699 clrsetbits_le32(&imx_ccm->cscdr2,
700 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
701 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
702 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
703 ((pred - 1) <<
704 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
705
706 /* Set the post divider */
707 clrsetbits_le32(&imx_ccm->cbcmr,
708 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
709 ((postd - 1) <<
710 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
b949fd2c 711 } else if (is_mx6sx()) {
ad153782
PF		 712 /* Setting LCDIF2 for i.MX6SX */
713 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
714 return;
715
716 /* Select pre-lcd clock to PLL5 and set pre divider */
717 clrsetbits_le32(&imx_ccm->cscdr2,
718 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
719 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
720 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
721 ((pred - 1) <<
722 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
723
724 /* Set the post divider */
725 clrsetbits_le32(&imx_ccm->cscmr1,
726 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
727 ((postd - 1) <<
728 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
729 }
730}
731
732int enable_lcdif_clock(u32 base_addr)
733{
734 u32 reg = 0;
735 u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
736
b949fd2c 737 if (is_mx6sx()) {
9655ebdd
YL		 738 if ((base_addr != LCDIF1_BASE_ADDR) &&
739 (base_addr != LCDIF2_BASE_ADDR)) {
ad153782
PF		 740 puts("Wrong LCD interface!\n");
741 return -EINVAL;
742 }
743 /* Set to pre-mux clock at default */
744 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
745 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
746 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
747 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
748 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
749 MXC_CCM_CCGR3_DISP_AXI_MASK) :
750 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
751 MXC_CCM_CCGR3_DISP_AXI_MASK);
b949fd2c 752 } else if (is_mx6ul()) {
ad153782
PF		 753 if (base_addr != LCDIF1_BASE_ADDR) {
754 puts("Wrong LCD interface!\n");
755 return -EINVAL;
756 }
757 /* Set to pre-mux clock at default */
758 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
759 lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
760 } else {
761 return 0;
762 }
763
764 reg = readl(&imx_ccm->cscdr2);
765 reg &= ~lcdif_clk_sel_mask;
766 writel(reg, &imx_ccm->cscdr2);
767
768 /* Enable the LCDIF pix clock */
769 reg = readl(&imx_ccm->CCGR3);
770 reg |= lcdif_ccgr3_mask;
771 writel(reg, &imx_ccm->CCGR3);
772
773 reg = readl(&imx_ccm->CCGR2);
774 reg |= MXC_CCM_CCGR2_LCD_MASK;
775 writel(reg, &imx_ccm->CCGR2);
0ff47e59
JH		 776
777 return 0;
ad153782
PF		 778}
779#endif
780
43cb127b 781#ifdef CONFIG_FSL_QSPI
b93ab2ee
PF		 782/* qspi_num can be from 0 - 1 */
783void enable_qspi_clk(int qspi_num)
784{
785 u32 reg = 0;
786 /* Enable QuadSPI clock */
787 switch (qspi_num) {
788 case 0:
789 /* disable the clock gate */
790 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
791
792 /* set 50M : (50 = 396 / 2 / 4) */
793 reg = readl(&imx_ccm->cscmr1);
794 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
795 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
796 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
797 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
798 writel(reg, &imx_ccm->cscmr1);
799
800 /* enable the clock gate */
801 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
802 break;
803 case 1:
804 /*
805 * disable the clock gate
806 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
807 * disable both of them.
808 */
809 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
810 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
811
812 /* set 50M : (50 = 396 / 2 / 4) */
813 reg = readl(&imx_ccm->cs2cdr);
814 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
815 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
816 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
817 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
818 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
819 writel(reg, &imx_ccm->cs2cdr);
820
821 /*enable the clock gate*/
822 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
823 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
824 break;
825 default:
826 break;
827 }
828}
829#endif
830
c655b816 831#ifdef CONFIG_FEC_MXC
6d97dc10 832int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
31f07964
FE		 833{
834 u32 reg = 0;
835 s32 timeout = 100000;
836
837 struct anatop_regs __iomem *anatop =
838 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
839
7731745c 840 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
5f98d0b5
FE		 841 return -EINVAL;
842
e2748b41
PF		 843 reg = readl(&anatop->pll_enet);
844
6d97dc10
PF		 845 if (fec_id == 0) {
846 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
847 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
848 } else if (fec_id == 1) {
849 /* Only i.MX6SX/UL support ENET2 */
b949fd2c 850 if (!(is_mx6sx() || is_mx6ul()))
6d97dc10
PF		 851 return -EINVAL;
852 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
853 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
854 } else {
855 return -EINVAL;
856 }
5f98d0b5 857
31f07964
FE		 858 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
859 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
860 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
861 writel(reg, &anatop->pll_enet);
862 while (timeout--) {
863 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
864 break;
865 }
866 if (timeout < 0)
867 return -ETIMEDOUT;
868 }
869
870 /* Enable FEC clock */
6d97dc10
PF		 871 if (fec_id == 0)
872 reg |= BM_ANADIG_PLL_ENET_ENABLE;
873 else
874 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
31f07964
FE		 875 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
876 writel(reg, &anatop->pll_enet);
877
5c045cdd
FE		 878#ifdef CONFIG_MX6SX
879 /*
880 * Set enet ahb clock to 200MHz
881 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
882 */
883 reg = readl(&imx_ccm->chsccdr);
884 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
885 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
886 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
887 /* PLL2 PFD2 */
888 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
889 /* Div = 2*/
890 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
891 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
892 writel(reg, &imx_ccm->chsccdr);
893
894 /* Enable enet system clock */
895 reg = readl(&imx_ccm->CCGR3);
896 reg |= MXC_CCM_CCGR3_ENET_MASK;
897 writel(reg, &imx_ccm->CCGR3);
898#endif
31f07964
FE		 899 return 0;
900}
25b4aa14 901#endif
23608e23
JL		 902
903static u32 get_usdhc_clk(u32 port)
904{
905 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
906 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
907 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
908
909 switch (port) {
910 case 0:
911 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
912 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
913 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
914
915 break;
916 case 1:
917 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
918 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
919 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
920
921 break;
922 case 2:
923 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
924 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
925 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
926
927 break;
928 case 3:
929 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
930 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
931 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
932
933 break;
934 default:
935 break;
936 }
937
938 if (clk_sel)
762a88cc 939 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23 940 else
762a88cc 941 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23
JL		 942
943 return root_freq / (usdhc_podf + 1);
944}
945
946u32 imx_get_uartclk(void)
947{
948 return get_uart_clk();
949}
950
ff167df5
JL		 951u32 imx_get_fecclk(void)
952{
adadc915 953 return mxc_get_clock(MXC_IPG_CLK);
ff167df5
JL		 954}
955
43cb127b 956#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
79814492 957static int enable_enet_pll(uint32_t en)
64e7cdb5 958{
64e7cdb5
EN		 959 struct mxc_ccm_reg *const imx_ccm
960 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
79814492
MV		 961 s32 timeout = 100000;
962 u32 reg = 0;
64e7cdb5
EN		 963
964 /* Enable PLLs */
965 reg = readl(&imx_ccm->analog_pll_enet);
966 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
967 writel(reg, &imx_ccm->analog_pll_enet);
968 reg |= BM_ANADIG_PLL_SYS_ENABLE;
969 while (timeout--) {
970 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
971 break;
972 }
973 if (timeout <= 0)
974 return -EIO;
975 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
976 writel(reg, &imx_ccm->analog_pll_enet);
79814492 977 reg |= en;
64e7cdb5 978 writel(reg, &imx_ccm->analog_pll_enet);
79814492
MV		 979 return 0;
980}
43cb127b 981#endif
64e7cdb5 982
43cb127b 983#ifdef CONFIG_CMD_SATA
79814492
MV		 984static void ungate_sata_clock(void)
985{
986 struct mxc_ccm_reg *const imx_ccm =
987 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
988
989 /* Enable SATA clock. */
990 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
991}
992
79814492
MV		 993int enable_sata_clock(void)
994{
995 ungate_sata_clock();
996 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
997}
8d29cef5
NK		 998
999void disable_sata_clock(void)
1000{
1001 struct mxc_ccm_reg *const imx_ccm =
1002 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1003
1004 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1005}
d95b6ab8 1006#endif
79814492 1007
43cb127b
PF		 1008#ifdef CONFIG_PCIE_IMX
1009static void ungate_pcie_clock(void)
1010{
1011 struct mxc_ccm_reg *const imx_ccm =
1012 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1013
1014 /* Enable PCIe clock. */
1015 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1016}
1017
79814492
MV		 1018int enable_pcie_clock(void)
1019{
1020 struct anatop_regs *anatop_regs =
1021 (struct anatop_regs *)ANATOP_BASE_ADDR;
1022 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1b8ad74a 1023 u32 lvds1_clk_sel;
79814492
MV		 1024
1025 /*
1026 * Here be dragons!
1027 *
1028 * The register ANATOP_MISC1 is not documented in the Freescale
1029 * MX6RM. The register that is mapped in the ANATOP space and
1030 * marked as ANATOP_MISC1 is actually documented in the PMU section
1031 * of the datasheet as PMU_MISC1.
1032 *
1b8ad74a
FE		 1033 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1034 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1035 * for PCI express link that is clocked from the i.MX6.
79814492
MV		 1036 */
1037#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1038#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1039#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1b8ad74a
FE		 1040#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1041#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1042
b949fd2c 1043 if (is_mx6sx())
1b8ad74a
FE		 1044 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1045 else
1046 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1047
79814492
MV		 1048 clrsetbits_le32(&anatop_regs->ana_misc1,
1049 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1050 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1b8ad74a 1051 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
79814492
MV		 1052
1053 /* PCIe reference clock sourced from AXI. */
1054 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1055
1056 /* Party time! Ungate the clock to the PCIe. */
43cb127b 1057#ifdef CONFIG_CMD_SATA
79814492 1058 ungate_sata_clock();
d95b6ab8 1059#endif
79814492
MV		 1060 ungate_pcie_clock();
1061
1062 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1063 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
64e7cdb5 1064}
43cb127b 1065#endif
64e7cdb5 1066
36c1ca4d
NG		 1067#ifdef CONFIG_SECURE_BOOT
1068void hab_caam_clock_enable(unsigned char enable)
1069{
1070 u32 reg;
1071
1072 /* CG4 ~ CG6, CAAM clocks */
1073 reg = __raw_readl(&imx_ccm->CCGR0);
1074 if (enable)
1075 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1076 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1077 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1078 else
1079 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1080 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1081 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1082 __raw_writel(reg, &imx_ccm->CCGR0);
1083
1084 /* EMI slow clk */
1085 reg = __raw_readl(&imx_ccm->CCGR6);
1086 if (enable)
1087 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1088 else
1089 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1090 __raw_writel(reg, &imx_ccm->CCGR6);
1091}
1092#endif
1093
cf202d26
NG		 1094static void enable_pll3(void)
1095{
1096 struct anatop_regs __iomem *anatop =
1097 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1098
1099 /* make sure pll3 is enabled */
1100 if ((readl(&anatop->usb1_pll_480_ctrl) &
1101 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1102 /* enable pll's power */
1103 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1104 &anatop->usb1_pll_480_ctrl_set);
1105 writel(0x80, &anatop->ana_misc2_clr);
1106 /* wait for pll lock */
1107 while ((readl(&anatop->usb1_pll_480_ctrl) &
1108 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1109 ;
1110 /* disable bypass */
1111 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1112 &anatop->usb1_pll_480_ctrl_clr);
1113 /* enable pll output */
1114 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1115 &anatop->usb1_pll_480_ctrl_set);
1116 }
1117}
1118
1119void enable_thermal_clk(void)
1120{
1121 enable_pll3();
1122}
1123
23608e23
JL		 1124unsigned int mxc_get_clock(enum mxc_clock clk)
1125{
1126 switch (clk) {
1127 case MXC_ARM_CLK:
1128 return get_mcu_main_clk();
1129 case MXC_PER_CLK:
1130 return get_periph_clk();
1131 case MXC_AHB_CLK:
1132 return get_ahb_clk();
1133 case MXC_IPG_CLK:
1134 return get_ipg_clk();
1135 case MXC_IPG_PERCLK:
e7bed5c2 1136 case MXC_I2C_CLK:
23608e23
JL		 1137 return get_ipg_per_clk();
1138 case MXC_UART_CLK:
1139 return get_uart_clk();
1140 case MXC_CSPI_CLK:
1141 return get_cspi_clk();
1142 case MXC_AXI_CLK:
1143 return get_axi_clk();
1144 case MXC_EMI_SLOW_CLK:
1145 return get_emi_slow_clk();
1146 case MXC_DDR_CLK:
1147 return get_mmdc_ch0_clk();
1148 case MXC_ESDHC_CLK:
1149 return get_usdhc_clk(0);
1150 case MXC_ESDHC2_CLK:
1151 return get_usdhc_clk(1);
1152 case MXC_ESDHC3_CLK:
1153 return get_usdhc_clk(2);
1154 case MXC_ESDHC4_CLK:
1155 return get_usdhc_clk(3);
1156 case MXC_SATA_CLK:
1157 return get_ahb_clk();
1158 default:
eb412d79 1159 printf("Unsupported MXC CLK: %d\n", clk);
23608e23
JL		 1160 break;
1161 }
1162
eb412d79 1163 return 0;
23608e23
JL		 1164}
1165
1166/*
1167 * Dump some core clockes.
1168 */
1169int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1170{
1171 u32 freq;
833b6435 1172 freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23 1173 printf("PLL_SYS %8d MHz\n", freq / 1000000);
833b6435 1174 freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23 1175 printf("PLL_BUS %8d MHz\n", freq / 1000000);
833b6435 1176 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23 1177 printf("PLL_OTG %8d MHz\n", freq / 1000000);
833b6435 1178 freq = decode_pll(PLL_ENET, MXC_HCLK);
23608e23
JL		 1179 printf("PLL_NET %8d MHz\n", freq / 1000000);
1180
1181 printf("\n");
d78e7f27 1182 printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
23608e23
JL		 1183 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1184 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
cc446726 1185#ifdef CONFIG_MXC_SPI
23608e23 1186 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
cc446726 1187#endif
23608e23
JL		 1188 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1189 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1190 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1191 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1192 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1193 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1194 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1195 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1196 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1197
1198 return 0;
1199}
1200
d95b6ab8 1201#ifndef CONFIG_MX6SX
5ea7f0e3
PKS		 1202void enable_ipu_clock(void)
1203{
1204 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1205 int reg;
1206 reg = readl(&mxc_ccm->CCGR3);
a0a0dacf 1207 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
5ea7f0e3 1208 writel(reg, &mxc_ccm->CCGR3);
8d779461
PF		 1209
1210 if (is_mx6dqp()) {
1211 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1212 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1213 }
5ea7f0e3 1214}
d95b6ab8 1215#endif
90d7cc42
AB		 1216
1217#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1218 defined(CONFIG_MX6S)
1219static void disable_ldb_di_clock_sources(void)
1220{
1221 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1222 int reg;
1223
1224 /* Make sure PFDs are disabled at boot. */
1225 reg = readl(&mxc_ccm->analog_pfd_528);
1226 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
b949fd2c 1227 if (is_mx6sdl())
90d7cc42
AB		 1228 reg |= 0x80008080;
1229 else
1230 reg |= 0x80808080;
1231 writel(reg, &mxc_ccm->analog_pfd_528);
1232
1233 /* Disable PLL3 PFDs */
1234 reg = readl(&mxc_ccm->analog_pfd_480);
1235 reg |= 0x80808080;
1236 writel(reg, &mxc_ccm->analog_pfd_480);
1237
1238 /* Disable PLL5 */
1239 reg = readl(&mxc_ccm->analog_pll_video);
1240 reg &= ~(1 << 13);
1241 writel(reg, &mxc_ccm->analog_pll_video);
1242}
1243
1244static void enable_ldb_di_clock_sources(void)
1245{
1246 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1247 int reg;
1248
1249 reg = readl(&mxc_ccm->analog_pfd_528);
b949fd2c 1250 if (is_mx6sdl())
90d7cc42
AB		 1251 reg &= ~(0x80008080);
1252 else
1253 reg &= ~(0x80808080);
1254 writel(reg, &mxc_ccm->analog_pfd_528);
1255
1256 reg = readl(&mxc_ccm->analog_pfd_480);
1257 reg &= ~(0x80808080);
1258 writel(reg, &mxc_ccm->analog_pfd_480);
1259}
1260
1261/*
1262 * Try call this function as early in the boot process as possible since the
1263 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1264 */
1265void select_ldb_di_clock_source(enum ldb_di_clock clk)
1266{
1267 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1268 int reg;
1269
1270 /*
1271 * Need to follow a strict procedure when changing the LDB
1272 * clock, else we can introduce a glitch. Things to keep in
1273 * mind:
1274 * 1. The current and new parent clocks must be disabled.
1275 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1276 * no CG bit.
1277 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1278 * the top four options are in one mux and the PLL3 option along
1279 * with another option is in the second mux. There is third mux
1280 * used to decide between the first and second mux.
1281 * The code below switches the parent to the bottom mux first
1282 * and then manipulates the top mux. This ensures that no glitch
1283 * will enter the divider.
1284 *
1285 * Need to disable MMDC_CH1 clock manually as there is no CG bit
1286 * for this clock. The only way to disable this clock is to move
1287 * it to pll3_sw_clk and then to disable pll3_sw_clk
1288 * Make sure periph2_clk2_sel is set to pll3_sw_clk
1289 */
1290
1291 /* Disable all ldb_di clock parents */
1292 disable_ldb_di_clock_sources();
1293
1294 /* Set MMDC_CH1 mask bit */
1295 reg = readl(&mxc_ccm->ccdr);
1296 reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1297 writel(reg, &mxc_ccm->ccdr);
1298
1299 /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1300 reg = readl(&mxc_ccm->cbcmr);
1301 reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
1302 writel(reg, &mxc_ccm->cbcmr);
1303
1304 /*
1305 * Set the periph2_clk_sel to the top mux so that
1306 * mmdc_ch1 is from pll3_sw_clk.
1307 */
1308 reg = readl(&mxc_ccm->cbcdr);
1309 reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1310 writel(reg, &mxc_ccm->cbcdr);
1311
1312 /* Wait for the clock switch */
1313 while (readl(&mxc_ccm->cdhipr))
1314 ;
1315 /* Disable pll3_sw_clk by selecting bypass clock source */
1316 reg = readl(&mxc_ccm->ccsr);
1317 reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1318 writel(reg, &mxc_ccm->ccsr);
1319
1320 /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1321 reg = readl(&mxc_ccm->cs2cdr);
1322 reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1323 | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1324 writel(reg, &mxc_ccm->cs2cdr);
1325
1326 /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1327 reg = readl(&mxc_ccm->cs2cdr);
1328 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1329 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1330 reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1331 | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1332 writel(reg, &mxc_ccm->cs2cdr);
1333
1334 /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1335 reg = readl(&mxc_ccm->cs2cdr);
1336 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1337 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1338 reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1339 | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1340 writel(reg, &mxc_ccm->cs2cdr);
1341
1342 /* Unbypass pll3_sw_clk */
1343 reg = readl(&mxc_ccm->ccsr);
1344 reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1345 writel(reg, &mxc_ccm->ccsr);
1346
1347 /*
1348 * Set the periph2_clk_sel back to the bottom mux so that
1349 * mmdc_ch1 is from its original parent.
1350 */
1351 reg = readl(&mxc_ccm->cbcdr);
1352 reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1353 writel(reg, &mxc_ccm->cbcdr);
1354
1355 /* Wait for the clock switch */
1356 while (readl(&mxc_ccm->cdhipr))
1357 ;
1358 /* Clear MMDC_CH1 mask bit */
1359 reg = readl(&mxc_ccm->ccdr);
1360 reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1361 writel(reg, &mxc_ccm->ccdr);
1362
1363 enable_ldb_di_clock_sources();
1364}
1365#endif
1366
23608e23
JL		 1367/***************************************************/
1368
1369U_BOOT_CMD(
1370 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1371 "display clocks",
1372 ""
1373);
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