[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / cpu_init.c

/*
 * (C) Copyright 2000-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/ppc4xx-emac.h>
#include <asm/processor.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/ppc4xx.h>

#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
DECLARE_GLOBAL_DATA_PTR;
#endif

#ifndef CONFIG_SYS_PLL_RECONFIG
#define CONFIG_SYS_PLL_RECONFIG	0
#endif

#if defined(CONFIG_440EPX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
static void reset_with_rli(void)
{
	u32 reg;

	/*
	 * Set reload inhibit so configuration will persist across
	 * processor resets
	 */
	mfcpr(CPR0_ICFG, reg);
	reg |= CPR0_ICFG_RLI_MASK;
	mtcpr(CPR0_ICFG, reg);

	/* Reset processor if configuration changed */
	__asm__ __volatile__ ("sync; isync");
	mtspr(SPRN_DBCR0, 0x20000000);
}
#endif

void reconfigure_pll(u32 new_cpu_freq)
{
#if defined(CONFIG_440EPX)
	int	reset_needed = 0;
	u32	reg, temp;
	u32	prbdv0, target_prbdv0,				/* CLK_PRIMBD */
		fwdva, target_fwdva, fwdvb, target_fwdvb,	/* CLK_PLLD */
		fbdv, target_fbdv, lfbdv, target_lfbdv,
		perdv0,	target_perdv0,				/* CLK_PERD */
		spcid0,	target_spcid0;				/* CLK_SPCID */

	/* Reconfigure clocks if necessary.
	 * See PPC440EPx User's Manual, sections 8.2 and 14 */
	if (new_cpu_freq == 667) {
		target_prbdv0 = 2;
		target_fwdva = 2;
		target_fwdvb = 4;
		target_fbdv = 20;
		target_lfbdv = 1;
		target_perdv0 = 4;
		target_spcid0 = 4;

		mfcpr(CPR0_PRIMBD0, reg);
		temp = (reg & PRBDV_MASK) >> 24;
		prbdv0 = temp ? temp : 8;
		if (prbdv0 != target_prbdv0) {
			reg &= ~PRBDV_MASK;
			reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
			mtcpr(CPR0_PRIMBD0, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_PLLD, reg);

		temp = (reg & PLLD_FWDVA_MASK) >> 16;
		fwdva = temp ? temp : 16;

		temp = (reg & PLLD_FWDVB_MASK) >> 8;
		fwdvb = temp ? temp : 8;

		temp = (reg & PLLD_FBDV_MASK) >> 24;
		fbdv = temp ? temp : 32;

		temp = (reg & PLLD_LFBDV_MASK);
		lfbdv = temp ? temp : 64;

		if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
				 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
			reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
				((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
				((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
				(target_lfbdv == 64 ? 0 : target_lfbdv);
			mtcpr(CPR0_PLLD, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_PERD, reg);
		perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
		if (perdv0 != target_perdv0) {
			reg &= ~CPR0_PERD_PERDV0_MASK;
			reg |= (target_perdv0 << 24);
			mtcpr(CPR0_PERD, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_SPCID, reg);
		temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
		spcid0 = temp ? temp : 4;
		if (spcid0 != target_spcid0) {
			reg &= ~CPR0_SPCID_SPCIDV0_MASK;
			reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
			mtcpr(CPR0_SPCID, reg);
			reset_needed = 1;
		}
	}

	/* Get current value of FWDVA.*/
	mfcpr(CPR0_PLLD, reg);
	temp = (reg & PLLD_FWDVA_MASK) >> 16;

	/*
	 * Check to see if FWDVA has been set to value of 1. if it has we must
	 * modify it.
	 */
	if (temp == 1) {
		/*
		 * Load register that contains current boot strapping option.
		 */
		mfcpr(CPR0_ICFG, reg);
		/*
		 * Strapping option bits (ICS) are already in correct position,
		 * only masking needed.
		 */
		reg &= CPR0_ICFG_ICS_MASK;

		if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
		    (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
			mfcpr(CPR0_PLLD, reg);

			/* Get current value of fbdv.  */
			temp = (reg & PLLD_FBDV_MASK) >> 24;
			fbdv = temp ? temp : 32;

			/* Get current value of lfbdv. */
			temp = (reg & PLLD_LFBDV_MASK);
			lfbdv = temp ? temp : 64;

			/*
			 * Get current value of FWDVA. Assign current FWDVA to
			 * new FWDVB.
			 */
			mfcpr(CPR0_PLLD, reg);
			target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
			fwdvb = target_fwdvb ? target_fwdvb : 8;

			/*
			 * Get current value of FWDVB. Assign current FWDVB to
			 * new FWDVA.
			 */
			target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
			fwdva = target_fwdva ? target_fwdva : 16;

			/*
			 * Update CPR0_PLLD with switched FWDVA and FWDVB.
			 */
			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
				PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
			reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
				((fwdvb == 8 ? 0 : fwdvb) << 8) |
				((fbdv == 32 ? 0 : fbdv) << 24) |
				(lfbdv == 64 ? 0 : lfbdv);
			mtcpr(CPR0_PLLD, reg);

			/* Acknowledge that a reset is required. */
			reset_needed = 1;
		}
	}

	/* Now reset the CPU if needed */
	if (reset_needed)
		reset_with_rli();
#endif

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	u32 reg;

	/*
	 * See "9.2.1.1 Booting with Option E" in the 460EX/GT
	 * users manual
	 */
	mfcpr(CPR0_PLLC, reg);
	if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
		/*
		 * Set engage bit
		 */
		reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
		mtcpr(CPR0_PLLC, reg);

		/* Now reset the CPU */
		reset_with_rli();
	}
#endif
}

#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
void
chip_21_errata(void)
{
	/*
	 * See rev 1.09 of the 405EX/405EXr errata.  CHIP_21 says that
	 * sometimes reading the PVR and/or SDR0_ECID results in incorrect
	 * values.  Since the rev-D chip uses the SDR0_ECID bits to control
	 * internal features, that means the second PCIe or ethernet of an EX
	 * variant could fail to work.  Also, security features of both EX and
	 * EXr might be incorrectly disabled.
	 *
	 * The suggested workaround is as follows (covering rev-C and rev-D):
	 *
	 * 1.Read the PVR and SDR0_ECID3.
	 *
	 * 2.If the PVR matches an expected Revision C PVR value AND if
	 * SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
	 * Revision C: continue executing the initialization code (no reset
	 * required).  else go to step 3.
	 *
	 * 3.If the PVR matches an expected Revision D PVR value AND if
	 * SDR0_ECID3[10:11] matches its expected value, then continue
	 * executing initialization code, no reset required.  else write
	 * DBCR0[RST] = 0b11 to generate a SysReset.
	 */

	u32 pvr;
	u32 pvr_28_31;
	u32 ecid3;
	u32 ecid3_10_11;
	u32 ecid3_12_15;

	/* Step 1: */
	pvr = get_pvr();
	mfsdr(SDR0_ECID3, ecid3);

	/* Step 2: */
	pvr_28_31 = pvr & 0xf;
	ecid3_10_11 = (ecid3 >> 20) & 0x3;
	ecid3_12_15 = (ecid3 >> 16) & 0xf;
	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
			(pvr_28_31 != ecid3_12_15)) {
		/* No reset required. */
		return;
	}

	/* Step 3: */
	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
			(ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
		/* No reset required. */
		return;
	}

	/* Reset required. */
	__asm__ __volatile__ ("sync; isync");
	mtspr(SPRN_DBCR0, 0x30000000);
}
#endif

/*
 * Breath some life into the CPU...
 *
 * Reconfigure PLL if necessary,
 * set up the memory map,
 * initialize a bunch of registers
 */
void
cpu_init_f (void)
{
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
	u32 val;
#endif

#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
	chip_21_errata();
#endif

	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);

#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
    !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
	/*
	 * GPIO0 setup (select GPIO or alternate function)
	 */
#if defined(CONFIG_SYS_GPIO0_OR)
	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR);		/* set initial state of output pins	*/
#endif
#if defined(CONFIG_SYS_GPIO0_ODR)
	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);	/* open-drain select			*/
#endif
	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select			*/
	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select				*/
	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select			*/
	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
#if defined(CONFIG_SYS_GPIO0_ISR2H)
	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
#endif
#if defined (CONFIG_SYS_GPIO0_TCR)
	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);	/* enable output driver for outputs	*/
#endif
#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */

#if defined (CONFIG_405EP)
	/*
	 * Set EMAC noise filter bits
	 */
	mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
#endif /* CONFIG_405EP */

#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
	gpio_set_chip_configuration();
#endif /* CONFIG_SYS_4xx_GPIO_TABLE */

	/*
	 * External Bus Controller (EBC) Setup
	 */
#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_405))
	/*
	 * Move the next instructions into icache, since these modify the flash
	 * we are running from!
	 */
	asm volatile("	bl	0f"		::: "lr");
	asm volatile("0:	mflr	3"		::: "r3");
	asm volatile("	addi	4, 0, 14"	::: "r4");
	asm volatile("	mtctr	4"		::: "ctr");
	asm volatile("1:	icbt	0, 3");
	asm volatile("	addi	3, 3, 32"	::: "r3");
	asm volatile("	bdnz	1b"		::: "ctr", "cr0");
	asm volatile("	addis	3, 0, 0x0"	::: "r3");
	asm volatile("	ori	3, 3, 0xA000"	::: "r3");
	asm volatile("	mtctr	3"		::: "ctr");
	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
#endif

	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
	mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
	mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
	mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
	mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
	mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
	mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
	mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
	mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
	mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
	mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
	mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
	mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
#endif

#if defined (CONFIG_SYS_EBC_CFG)
	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
#endif

#if defined(CONFIG_WATCHDOG)
	val = mfspr(SPRN_TCR);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
	val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
#else
	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
#endif
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
	val &= ~0x30000000;			/* clear WRC bits */
	val |= CONFIG_SYS_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
#endif
	mtspr(SPRN_TCR, val);

	val = mfspr(SPRN_TSR);
	val |= 0x80000000;      /* enable watchdog timer */
	mtspr(SPRN_TSR, val);

	reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */

#if defined(CONFIG_440GX)
	/* Take the GX out of compatibility mode
	 * Travis Sawyer, 9 Mar 2004
	 * NOTE: 440gx user manual inconsistency here
	 *       Compatibility mode and Ethernet Clock select are not
	 *       correct in the manual
	 */
	mfsdr(SDR0_MFR, val);
	val &= ~0x10000000;
	mtsdr(SDR0_MFR,val);
#endif /* CONFIG_440GX */

#if defined(CONFIG_460EX)
	/*
	 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	 */
	mfsdr(SDR0_AHB_CFG, val);
	val |= 0x80;
	val &= ~0x40;
	mtsdr(SDR0_AHB_CFG, val);
	mfsdr(SDR0_USB2HOST_CFG, val);
	val &= ~0xf00;
	val |= 0x400;
	mtsdr(SDR0_USB2HOST_CFG, val);
#endif /* CONFIG_460EX */

#if defined(CONFIG_405EX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
	/*
	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	 */
	mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
	      PLB4Ax_ACR_RDP_4DEEP);
	mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
	      PLB4Ax_ACR_RDP_4DEEP);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
#if defined(CONFIG_405GP)
	uint pvr = get_pvr();

	/*
	 * Set edge conditioning circuitry on PPC405GPr
	 * for compatibility to existing PPC405GP designs.
	 */
	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
		mtdcr(CPC0_ECR, 0x60606000);
	}
#endif  /* defined(CONFIG_405GP) */

	return 0;
}

#if defined(CONFIG_PCI) && \
	(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
	 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
/*
 * 440EP(x)/GR(x) PCI async/sync clocking restriction:
 *
 * In asynchronous PCI mode, the synchronous PCI clock must meet
 * certain requirements. The following equation describes the
 * relationship that must be maintained between the asynchronous PCI
 * clock and synchronous PCI clock. Select an appropriate PCI:PLB
 * ratio to maintain the relationship:
 *
 * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
 */
static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
{
	if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
		return 0;
	else
		return 1;
}

int ppc4xx_pci_sync_clock_config(u32 async)
{
	sys_info_t sys_info;
	u32 sync;
	int div;
	u32 reg;
	u32 spcid_val[] = {
		CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
		CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };

	get_sys_info(&sys_info);
	sync = sys_info.freqPCI;

	/*
	 * First check if the equation above is met
	 */
	if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
		/*
		 * Reconfigure PCI sync clock to meet the equation.
		 * Start with highest possible PCI sync frequency
		 * (divider 1).
		 */
		for (div = 1; div <= 4; div++) {
			sync = sys_info.freqPLB / div;
			if (ppc4xx_pci_sync_clock_ok(sync, async))
			    break;
		}

		if (div <= 4) {
			mtcpr(CPR0_SPCID, spcid_val[div]);

			mfcpr(CPR0_ICFG, reg);
			reg |= CPR0_ICFG_RLI_MASK;
			mtcpr(CPR0_ICFG, reg);

			/* do chip reset */
			mtspr(SPRN_DBCR0, 0x20000000);
		} else {
			/* Impossible to configure the PCI sync clock */
			return -1;
		}
	}

	return 0;
}
#endif
Commit	Line	Data
4a9cbbe8	1	/*
dbbd1257	2	* (C) Copyright 2000-2007
4a9cbbe8 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <watchdog.h>
b36df561	26	#include <asm/ppc4xx-emac.h>
4a9cbbe8	27	#include <asm/processor.h>
09887762	28	#include <asm/ppc4xx-gpio.h>
b36df561	29	#include <asm/ppc4xx.h>
4a9cbbe8	30
d87080b7 WD	31	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
	32	DECLARE_GLOBAL_DATA_PTR;
	33	#endif
	34
6d0f6bcf JCPV	35	#ifndef CONFIG_SYS_PLL_RECONFIG
6d0f6bcf JCPV	36	#define CONFIG_SYS_PLL_RECONFIG 0
f66e2c8b MN	37	#endif
f66e2c8b MN	38
fe7cca71 SR	39	#if defined(CONFIG_440EPX) \|\| \
	40	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	41	static void reset_with_rli(void)
	42	{
	43	u32 reg;
	44
	45	/*
	46	* Set reload inhibit so configuration will persist across
	47	* processor resets
	48	*/
	49	mfcpr(CPR0_ICFG, reg);
	50	reg \|= CPR0_ICFG_RLI_MASK;
	51	mtcpr(CPR0_ICFG, reg);
	52
	53	/* Reset processor if configuration changed */
	54	__asm__ __volatile__ ("sync; isync");
	55	mtspr(SPRN_DBCR0, 0x20000000);
	56	}
	57	#endif
	58
f66e2c8b MN	59	void reconfigure_pll(u32 new_cpu_freq)
	60	{
	61	#if defined(CONFIG_440EPX)
	62	int reset_needed = 0;
	63	u32 reg, temp;
	64	u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
	65	fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
	66	fbdv, target_fbdv, lfbdv, target_lfbdv,
	67	perdv0, target_perdv0, /* CLK_PERD */
	68	spcid0, target_spcid0; /* CLK_SPCID */
	69
	70	/* Reconfigure clocks if necessary.
	71	* See PPC440EPx User's Manual, sections 8.2 and 14 */
	72	if (new_cpu_freq == 667) {
	73	target_prbdv0 = 2;
	74	target_fwdva = 2;
	75	target_fwdvb = 4;
	76	target_fbdv = 20;
	77	target_lfbdv = 1;
	78	target_perdv0 = 4;
	79	target_spcid0 = 4;
	80
ddc922ff	81	mfcpr(CPR0_PRIMBD0, reg);
f66e2c8b MN	82	temp = (reg & PRBDV_MASK) >> 24;
	83	prbdv0 = temp ? temp : 8;
	84	if (prbdv0 != target_prbdv0) {
	85	reg &= ~PRBDV_MASK;
	86	reg \|= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
ddc922ff	87	mtcpr(CPR0_PRIMBD0, reg);
f66e2c8b MN	88	reset_needed = 1;
	89	}
	90
d1c3b275	91	mfcpr(CPR0_PLLD, reg);
f66e2c8b MN	92
	93	temp = (reg & PLLD_FWDVA_MASK) >> 16;
	94	fwdva = temp ? temp : 16;
	95
	96	temp = (reg & PLLD_FWDVB_MASK) >> 8;
	97	fwdvb = temp ? temp : 8;
	98
	99	temp = (reg & PLLD_FBDV_MASK) >> 24;
	100	fbdv = temp ? temp : 32;
	101
	102	temp = (reg & PLLD_LFBDV_MASK);
	103	lfbdv = temp ? temp : 64;
	104
	105	if (fwdva != target_fwdva \|\| fbdv != target_fbdv \|\| lfbdv != target_lfbdv) {
	106	reg &= ~(PLLD_FWDVA_MASK \| PLLD_FWDVB_MASK \|
	107	PLLD_FBDV_MASK \| PLLD_LFBDV_MASK);
	108	reg \|= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) \|
	109	((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) \|
	110	((target_fbdv == 32 ? 0 : target_fbdv) << 24) \|
	111	(target_lfbdv == 64 ? 0 : target_lfbdv);
d1c3b275	112	mtcpr(CPR0_PLLD, reg);
f66e2c8b MN	113	reset_needed = 1;
	114	}
	115
d1c3b275	116	mfcpr(CPR0_PERD, reg);
f66e2c8b MN	117	perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
	118	if (perdv0 != target_perdv0) {
	119	reg &= ~CPR0_PERD_PERDV0_MASK;
	120	reg \|= (target_perdv0 << 24);
d1c3b275	121	mtcpr(CPR0_PERD, reg);
f66e2c8b MN	122	reset_needed = 1;
	123	}
	124
d1c3b275	125	mfcpr(CPR0_SPCID, reg);
f66e2c8b MN	126	temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
	127	spcid0 = temp ? temp : 4;
	128	if (spcid0 != target_spcid0) {
	129	reg &= ~CPR0_SPCID_SPCIDV0_MASK;
	130	reg \|= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
d1c3b275	131	mtcpr(CPR0_SPCID, reg);
f66e2c8b MN	132	reset_needed = 1;
f66e2c8b MN	133	}
c550afad RS	134	}
	135
	136	/* Get current value of FWDVA.*/
	137	mfcpr(CPR0_PLLD, reg);
	138	temp = (reg & PLLD_FWDVA_MASK) >> 16;
f66e2c8b	139
c550afad RS	140	/*
	141	* Check to see if FWDVA has been set to value of 1. if it has we must
	142	* modify it.
	143	*/
	144	if (temp == 1) {
c550afad RS	145	/*
	146	* Load register that contains current boot strapping option.
	147	*/
	148	mfcpr(CPR0_ICFG, reg);
c1ab75c7 SR	149	/*
	150	* Strapping option bits (ICS) are already in correct position,
	151	* only masking needed.
	152	*/
	153	reg &= CPR0_ICFG_ICS_MASK;
c550afad RS	154
	155	if ((reg == BOOT_STRAP_OPTION_A) \|\| (reg == BOOT_STRAP_OPTION_B) \|\|
	156	(reg == BOOT_STRAP_OPTION_D) \|\| (reg == BOOT_STRAP_OPTION_E)) {
c1ab75c7 SR	157	mfcpr(CPR0_PLLD, reg);
	158
	159	/* Get current value of fbdv. */
	160	temp = (reg & PLLD_FBDV_MASK) >> 24;
	161	fbdv = temp ? temp : 32;
	162
	163	/* Get current value of lfbdv. */
	164	temp = (reg & PLLD_LFBDV_MASK);
	165	lfbdv = temp ? temp : 64;
	166
c550afad RS	167	/*
	168	* Get current value of FWDVA. Assign current FWDVA to
	169	* new FWDVB.
	170	*/
	171	mfcpr(CPR0_PLLD, reg);
	172	target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
	173	fwdvb = target_fwdvb ? target_fwdvb : 8;
c1ab75c7	174
c550afad RS	175	/*
	176	* Get current value of FWDVB. Assign current FWDVB to
	177	* new FWDVA.
	178	*/
	179	target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
	180	fwdva = target_fwdva ? target_fwdva : 16;
c1ab75c7	181
c550afad RS	182	/*
	183	* Update CPR0_PLLD with switched FWDVA and FWDVB.
	184	*/
	185	reg &= ~(PLLD_FWDVA_MASK \| PLLD_FWDVB_MASK \|
	186	PLLD_FBDV_MASK \| PLLD_LFBDV_MASK);
	187	reg \|= ((fwdva == 16 ? 0 : fwdva) << 16) \|
	188	((fwdvb == 8 ? 0 : fwdvb) << 8) \|
	189	((fbdv == 32 ? 0 : fbdv) << 24) \|
	190	(lfbdv == 64 ? 0 : lfbdv);
	191	mtcpr(CPR0_PLLD, reg);
c1ab75c7	192
c550afad RS	193	/* Acknowledge that a reset is required. */
	194	reset_needed = 1;
	195	}
	196	}
	197
fe7cca71 SR	198	/* Now reset the CPU if needed */
	199	if (reset_needed)
	200	reset_with_rli();
	201	#endif
	202
	203	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	204	u32 reg;
	205
	206	/*
	207	* See "9.2.1.1 Booting with Option E" in the 460EX/GT
	208	* users manual
	209	*/
	210	mfcpr(CPR0_PLLC, reg);
	211	if ((reg & (CPR0_PLLC_RST \| CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
c550afad	212	/*
fe7cca71	213	* Set engage bit
c550afad	214	*/
fe7cca71 SR	215	reg = (reg & ~CPR0_PLLC_RST) \| CPR0_PLLC_ENG;
fe7cca71 SR	216	mtcpr(CPR0_PLLC, reg);
f66e2c8b	217
fe7cca71 SR	218	/* Now reset the CPU */
fe7cca71 SR	219	reset_with_rli();
f66e2c8b MN	220	}
	221	#endif
	222	}
	223
644362c4 SF	224	#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
	225	void
	226	chip_21_errata(void)
	227	{
	228	/*
	229	* See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that
	230	* sometimes reading the PVR and/or SDR0_ECID results in incorrect
	231	* values. Since the rev-D chip uses the SDR0_ECID bits to control
	232	* internal features, that means the second PCIe or ethernet of an EX
	233	* variant could fail to work. Also, security features of both EX and
	234	* EXr might be incorrectly disabled.
	235	*
	236	* The suggested workaround is as follows (covering rev-C and rev-D):
	237	*
	238	* 1.Read the PVR and SDR0_ECID3.
	239	*
	240	* 2.If the PVR matches an expected Revision C PVR value AND if
	241	* SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
	242	* Revision C: continue executing the initialization code (no reset
	243	* required). else go to step 3.
	244	*
	245	* 3.If the PVR matches an expected Revision D PVR value AND if
	246	* SDR0_ECID3[10:11] matches its expected value, then continue
	247	* executing initialization code, no reset required. else write
	248	* DBCR0[RST] = 0b11 to generate a SysReset.
	249	*/
	250
	251	u32 pvr;
	252	u32 pvr_28_31;
	253	u32 ecid3;
	254	u32 ecid3_10_11;
	255	u32 ecid3_12_15;
	256
	257	/* Step 1: */
	258	pvr = get_pvr();
	259	mfsdr(SDR0_ECID3, ecid3);
	260
	261	/* Step 2: */
	262	pvr_28_31 = pvr & 0xf;
	263	ecid3_10_11 = (ecid3 >> 20) & 0x3;
	264	ecid3_12_15 = (ecid3 >> 16) & 0xf;
	265	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
	266	(pvr_28_31 != ecid3_12_15)) {
	267	/* No reset required. */
	268	return;
	269	}
	270
	271	/* Step 3: */
	272	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
	273	(ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
	274	/* No reset required. */
	275	return;
	276	}
	277
	278	/* Reset required. */
	279	__asm__ __volatile__ ("sync; isync");
	280	mtspr(SPRN_DBCR0, 0x30000000);
	281	}
	282	#endif
	283
4a9cbbe8 WD	284	/*
	285	* Breath some life into the CPU...
	286	*
f66e2c8b MN	287	* Reconfigure PLL if necessary,
f66e2c8b MN	288	* set up the memory map,
4a9cbbe8 WD	289	* initialize a bunch of registers
	290	*/
	291	void
	292	cpu_init_f (void)
	293	{
f5564837	294	#if defined(CONFIG_WATCHDOG) \|\| defined(CONFIG_440GX) \|\| defined(CONFIG_460EX)
745d8a0d	295	u32 val;
f11033e7	296	#endif
5de85140	297
644362c4 SF	298	#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
	299	chip_21_errata();
	300	#endif
	301
6d0f6bcf	302	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
f11033e7	303
1b8fec13 TM	304	#if (defined(CONFIG_405EP) \|\| defined (CONFIG_405EX)) && \
1b8fec13 TM	305	!defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
b867d705 SR	306	/*
	307	* GPIO0 setup (select GPIO or alternate function)
	308	*/
6d0f6bcf JCPV	309	#if defined(CONFIG_SYS_GPIO0_OR)
6d0f6bcf JCPV	310	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
e0a46554	311	#endif
6d0f6bcf JCPV	312	#if defined(CONFIG_SYS_GPIO0_ODR)
6d0f6bcf JCPV	313	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
e0a46554	314	#endif
6d0f6bcf JCPV	315	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
	316	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
	317	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
	318	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
	319	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
	320	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
	321	#if defined(CONFIG_SYS_GPIO0_ISR2H)
	322	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
	323	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
dbbd1257	324	#endif
6d0f6bcf JCPV	325	#if defined (CONFIG_SYS_GPIO0_TCR)
6d0f6bcf JCPV	326	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
dbbd1257	327	#endif
6d0f6bcf	328	#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
b867d705	329
bec92646	330	#if defined (CONFIG_405EP)
b867d705 SR	331	/*
	332	* Set EMAC noise filter bits
	333	*/
afabb498	334	mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE \| CPC0_EPCTL_E1NFE);
b867d705 SR	335	#endif /* CONFIG_405EP */
b867d705 SR	336
6d0f6bcf	337	#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
0d974d52	338	gpio_set_chip_configuration();
6d0f6bcf	339	#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
a4c8d138	340
4a9cbbe8 WD	341	/*
	342	* External Bus Controller (EBC) Setup
	343	*/
6d0f6bcf	344	#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
a4c8d138	345	#if (defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| \
e01bd218	346	defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| \
dbbd1257	347	defined(CONFIG_405EX) \|\| defined(CONFIG_405))
4a9cbbe8 WD	348	/*
	349	* Move the next instructions into icache, since these modify the flash
	350	* we are running from!
	351	*/
	352	asm volatile(" bl 0f" ::: "lr");
	353	asm volatile("0: mflr 3" ::: "r3");
1636d1c8	354	asm volatile(" addi 4, 0, 14" ::: "r4");
4a9cbbe8 WD	355	asm volatile(" mtctr 4" ::: "ctr");
	356	asm volatile("1: icbt 0, 3");
	357	asm volatile(" addi 3, 3, 32" ::: "r3");
	358	asm volatile(" bdnz 1b" ::: "ctr", "cr0");
	359	asm volatile(" addis 3, 0, 0x0" ::: "r3");
	360	asm volatile(" ori 3, 3, 0xA000" ::: "r3");
	361	asm volatile(" mtctr 3" ::: "ctr");
	362	asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
a4c8d138	363	#endif
4a9cbbe8	364
d1c3b275 SR	365	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
d1c3b275 SR	366	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
4a9cbbe8 WD	367	#endif
4a9cbbe8 WD	368
6d0f6bcf	369	#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
d1c3b275 SR	370	mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
d1c3b275 SR	371	mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
4a9cbbe8 WD	372	#endif
4a9cbbe8 WD	373
6d0f6bcf	374	#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
d1c3b275 SR	375	mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
d1c3b275 SR	376	mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
4a9cbbe8 WD	377	#endif
4a9cbbe8 WD	378
6d0f6bcf	379	#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
d1c3b275 SR	380	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
d1c3b275 SR	381	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
4a9cbbe8 WD	382	#endif
4a9cbbe8 WD	383
6d0f6bcf	384	#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
d1c3b275 SR	385	mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
d1c3b275 SR	386	mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
4a9cbbe8 WD	387	#endif
4a9cbbe8 WD	388
6d0f6bcf	389	#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
d1c3b275 SR	390	mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
d1c3b275 SR	391	mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
4a9cbbe8 WD	392	#endif
4a9cbbe8 WD	393
6d0f6bcf	394	#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
d1c3b275 SR	395	mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
d1c3b275 SR	396	mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
4a9cbbe8 WD	397	#endif
4a9cbbe8 WD	398
6d0f6bcf	399	#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
d1c3b275 SR	400	mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
d1c3b275 SR	401	mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
4a9cbbe8 WD	402	#endif
4a9cbbe8 WD	403
6d0f6bcf JCPV	404	#if defined (CONFIG_SYS_EBC_CFG)
6d0f6bcf JCPV	405	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
ca43ba18	406	#endif
4a9cbbe8	407
f11033e7	408	#if defined(CONFIG_WATCHDOG)
f472069f	409	val = mfspr(SPRN_TCR);
846b0dd2	410	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
c157d8e2	411	val \|= 0xb8000000; /* generate system reset after 1.34 seconds */
a11e0696 IL	412	#elif defined(CONFIG_440EPX)
a11e0696 IL	413	val \|= 0xb0000000; /* generate system reset after 1.34 seconds */
c157d8e2	414	#else
4a9cbbe8	415	val \|= 0xf0000000; /* generate system reset after 2.684 seconds */
1c2ce226	416	#endif
6d0f6bcf	417	#if defined(CONFIG_SYS_4xx_RESET_TYPE)
1c2ce226	418	val &= ~0x30000000; /* clear WRC bits */
6d0f6bcf	419	val \|= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
c157d8e2	420	#endif
f472069f	421	mtspr(SPRN_TCR, val);
4a9cbbe8	422
f472069f	423	val = mfspr(SPRN_TSR);
4a9cbbe8	424	val \|= 0x80000000; /* enable watchdog timer */
f472069f	425	mtspr(SPRN_TSR, val);
4a9cbbe8 WD	426
	427	reset_4xx_watchdog();
	428	#endif /* CONFIG_WATCHDOG */
745d8a0d	429
5de85140 SR	430	#if defined(CONFIG_440GX)
	431	/* Take the GX out of compatibility mode
	432	* Travis Sawyer, 9 Mar 2004
	433	* NOTE: 440gx user manual inconsistency here
	434	* Compatibility mode and Ethernet Clock select are not
	435	* correct in the manual
	436	*/
d1c3b275	437	mfsdr(SDR0_MFR, val);
5de85140	438	val &= ~0x10000000;
d1c3b275	439	mtsdr(SDR0_MFR,val);
5de85140 SR	440	#endif /* CONFIG_440GX */
5de85140 SR	441
745d8a0d SR	442	#if defined(CONFIG_460EX)
	443	/*
	444	* Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	445	* clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	446	* regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	447	*/
	448	mfsdr(SDR0_AHB_CFG, val);
	449	val \|= 0x80;
	450	val &= ~0x40;
	451	mtsdr(SDR0_AHB_CFG, val);
	452	mfsdr(SDR0_USB2HOST_CFG, val);
	453	val &= ~0xf00;
	454	val \|= 0x400;
	455	mtsdr(SDR0_USB2HOST_CFG, val);
	456	#endif /* CONFIG_460EX */
079589bc	457
f5564837 SR	458	#if defined(CONFIG_405EX) \|\| \
f5564837 SR	459	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
079589bc	460	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
1b8fec13	461	defined(CONFIG_460SX) \|\| defined(CONFIG_APM821XX)
079589bc PH	462	/*
	463	* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	464	*/
5e7abce9 SR	465	mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) \|
	466	PLB4Ax_ACR_RDP_4DEEP);
	467	mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) \|
	468	PLB4Ax_ACR_RDP_4DEEP);
079589bc	469	#endif /* CONFIG_440SP/SPE \|\| CONFIG_460EX/GT \|\| CONFIG_405EX */
4a9cbbe8 WD	470	}
	471
	472	/*
	473	* initialize higher level parts of CPU like time base and timers
	474	*/
	475	int cpu_init_r (void)
	476	{
b867d705	477	#if defined(CONFIG_405GP)
38daa27d	478	uint pvr = get_pvr();
38daa27d SR	479
	480	/*
	481	* Set edge conditioning circuitry on PPC405GPr
	482	* for compatibility to existing PPC405GP designs.
	483	*/
baa3d528	484	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
d1c3b275	485	mtdcr(CPC0_ECR, 0x60606000);
38daa27d	486	}
b867d705	487	#endif /* defined(CONFIG_405GP) */
2801b2d2	488
9cd69016	489	return 0;
4a9cbbe8	490	}
5e47f953 SR	491
	492	#if defined(CONFIG_PCI) && \
	493	(defined(CONFIG_440EP) \|\| defined(CONFIG_440EPX) \|\| \
	494	defined(CONFIG_440GR) \|\| defined(CONFIG_440GRX))
	495	/*
	496	* 440EP(x)/GR(x) PCI async/sync clocking restriction:
	497	*
	498	* In asynchronous PCI mode, the synchronous PCI clock must meet
	499	* certain requirements. The following equation describes the
	500	* relationship that must be maintained between the asynchronous PCI
	501	* clock and synchronous PCI clock. Select an appropriate PCI:PLB
	502	* ratio to maintain the relationship:
	503	*
	504	* AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
	505	*/
	506	static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
	507	{
	508	if (((async - 1000000) > sync) \|\| (sync > ((2 * async) - 1000000)))
	509	return 0;
	510	else
	511	return 1;
	512	}
	513
	514	int ppc4xx_pci_sync_clock_config(u32 async)
	515	{
	516	sys_info_t sys_info;
	517	u32 sync;
	518	int div;
	519	u32 reg;
	520	u32 spcid_val[] = {
	521	CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
	522	CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
	523
	524	get_sys_info(&sys_info);
	525	sync = sys_info.freqPCI;
	526
	527	/*
	528	* First check if the equation above is met
	529	*/
	530	if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
	531	/*
	532	* Reconfigure PCI sync clock to meet the equation.
	533	* Start with highest possible PCI sync frequency
	534	* (divider 1).
	535	*/
	536	for (div = 1; div <= 4; div++) {
	537	sync = sys_info.freqPLB / div;
	538	if (ppc4xx_pci_sync_clock_ok(sync, async))
	539	break;
	540	}
	541
	542	if (div <= 4) {
	543	mtcpr(CPR0_SPCID, spcid_val[div]);
	544
	545	mfcpr(CPR0_ICFG, reg);
	546	reg \|= CPR0_ICFG_RLI_MASK;
	547	mtcpr(CPR0_ICFG, reg);
	548
	549	/* do chip reset */
	550	mtspr(SPRN_DBCR0, 0x20000000);
	551	} else {
	552	/* Impossible to configure the PCI sync clock */
	553	return -1;
	554	}
555	}
556
557	return 0;
558	}
559	#endif