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Commit | Line | Data |
---|---|---|
887e2ec9 | 1 | /* |
5132106a | 2 | * (C) Copyright 2006-2009 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
865f0f97 | 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
887e2ec9 | 8 | * |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
887e2ec9 SR |
10 | */ |
11 | ||
12 | #include <common.h> | |
13628884 SR |
13 | #include <libfdt.h> |
14 | #include <fdt_support.h> | |
b36df561 | 15 | #include <asm/ppc4xx.h> |
09887762 | 16 | #include <asm/ppc4xx-gpio.h> |
887e2ec9 | 17 | #include <asm/processor.h> |
5a5958b7 | 18 | #include <asm/io.h> |
83a49c8d | 19 | #include <asm/bitops.h> |
887e2ec9 SR |
20 | |
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
d873133f | 23 | #if !defined(CONFIG_SYS_NO_FLASH) |
6d0f6bcf | 24 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
d873133f | 25 | #endif |
887e2ec9 | 26 | |
5132106a SR |
27 | extern void __ft_board_setup(void *blob, bd_t *bd); |
28 | ulong flash_get_size(ulong base, int banknum); | |
1b3c360c | 29 | |
23c51a2d SR |
30 | static inline u32 get_async_pci_freq(void) |
31 | { | |
32 | if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & | |
33 | CONFIG_SYS_BCSR5_PCI66EN) | |
34 | return 66666666; | |
35 | else | |
36 | return 33333333; | |
37 | } | |
38 | ||
887e2ec9 SR |
39 | int board_early_init_f(void) |
40 | { | |
a78bc443 SR |
41 | u32 sdr0_cust0; |
42 | u32 sdr0_pfc1, sdr0_pfc2; | |
43 | u32 reg; | |
887e2ec9 | 44 | |
d1c3b275 SR |
45 | mtdcr(EBC0_CFGADDR, EBC0_CFG); |
46 | mtdcr(EBC0_CFGDATA, 0xb8400000); | |
887e2ec9 | 47 | |
83a49c8d | 48 | /* |
887e2ec9 | 49 | * Setup the interrupt controller polarities, triggers, etc. |
83a49c8d | 50 | */ |
952e7760 SR |
51 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
52 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
53 | mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ | |
54 | mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ | |
55 | mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ | |
56 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ | |
57 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 58 | |
952e7760 SR |
59 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
60 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
61 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
62 | mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ | |
63 | mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ | |
64 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ | |
65 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 66 | |
952e7760 SR |
67 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
68 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
69 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
70 | mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ | |
71 | mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ | |
72 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ | |
73 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 74 | |
23c51a2d SR |
75 | /* Check and reconfigure the PCI sync clock if necessary */ |
76 | ppc4xx_pci_sync_clock_config(get_async_pci_freq()); | |
77 | ||
887e2ec9 | 78 | /* 50MHz tmrclk */ |
6d0f6bcf | 79 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); |
887e2ec9 SR |
80 | |
81 | /* clear write protects */ | |
6d0f6bcf | 82 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00); |
887e2ec9 SR |
83 | |
84 | /* enable Ethernet */ | |
6d0f6bcf | 85 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00); |
887e2ec9 SR |
86 | |
87 | /* enable USB device */ | |
6d0f6bcf | 88 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20); |
887e2ec9 | 89 | |
b738654d | 90 | /* select Ethernet (and optionally IIC1) pins */ |
887e2ec9 | 91 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
83a49c8d MF |
92 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | |
93 | SDR0_PFC1_SELECT_CONFIG_4; | |
b738654d MN |
94 | #ifdef CONFIG_I2C_MULTI_BUS |
95 | sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); | |
96 | #endif | |
eab10073 SF |
97 | /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */ |
98 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; | |
99 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS; | |
100 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS; | |
101 | ||
887e2ec9 | 102 | mfsdr(SDR0_PFC2, sdr0_pfc2); |
83a49c8d MF |
103 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | |
104 | SDR0_PFC2_SELECT_CONFIG_4; | |
887e2ec9 SR |
105 | mtsdr(SDR0_PFC2, sdr0_pfc2); |
106 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
107 | ||
108 | /* PCI arbiter enabled */ | |
d1c3b275 SR |
109 | mfsdr(SDR0_PCI0, reg); |
110 | mtsdr(SDR0_PCI0, 0x80000000 | reg); | |
887e2ec9 SR |
111 | |
112 | /* setup NAND FLASH */ | |
113 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
511d0c72 | 114 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
887e2ec9 SR |
115 | SDR0_CUST0_NDFC_ENABLE | |
116 | SDR0_CUST0_NDFC_BW_8_BIT | | |
117 | SDR0_CUST0_NDFC_ARE_MASK | | |
6d0f6bcf | 118 | (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); |
511d0c72 | 119 | mtsdr(SDR0_CUST0, sdr0_cust0); |
887e2ec9 SR |
120 | |
121 | return 0; | |
122 | } | |
123 | ||
887e2ec9 SR |
124 | int misc_init_r(void) |
125 | { | |
d873133f | 126 | #if !defined(CONFIG_SYS_NO_FLASH) |
887e2ec9 SR |
127 | uint pbcr; |
128 | int size_val = 0; | |
d873133f | 129 | #endif |
854bc8da | 130 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
131 | unsigned long usb2d0cr = 0; |
132 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
133 | unsigned long sdr0_pfc1; | |
134 | char *act = getenv("usbact"); | |
854bc8da | 135 | #endif |
d873133f | 136 | u32 reg; |
887e2ec9 | 137 | |
d873133f | 138 | #if !defined(CONFIG_SYS_NO_FLASH) |
83a49c8d | 139 | /* Re-do flash sizing to get full correct info */ |
1b3c360c SR |
140 | |
141 | /* adjust flash start and offset */ | |
142 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
143 | gd->bd->bi_flashoffset = 0; | |
144 | ||
4adcbdc6 SR |
145 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ |
146 | defined(CONFIG_SYS_RAMBOOT) | |
d1c3b275 | 147 | mtdcr(EBC0_CFGADDR, PB3CR); |
887e2ec9 | 148 | #else |
d1c3b275 | 149 | mtdcr(EBC0_CFGADDR, PB0CR); |
887e2ec9 | 150 | #endif |
d1c3b275 | 151 | pbcr = mfdcr(EBC0_CFGDATA); |
865f0f97 | 152 | size_val = ffs(gd->bd->bi_flashsize) - 21; |
887e2ec9 | 153 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
4adcbdc6 SR |
154 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ |
155 | defined(CONFIG_SYS_RAMBOOT) | |
d1c3b275 | 156 | mtdcr(EBC0_CFGADDR, PB3CR); |
887e2ec9 | 157 | #else |
d1c3b275 | 158 | mtdcr(EBC0_CFGADDR, PB0CR); |
887e2ec9 | 159 | #endif |
d1c3b275 | 160 | mtdcr(EBC0_CFGDATA, pbcr); |
887e2ec9 | 161 | |
1b3c360c SR |
162 | /* |
163 | * Re-check to get correct base address | |
164 | */ | |
165 | flash_get_size(gd->bd->bi_flashstart, 0); | |
887e2ec9 | 166 | |
5a1aceb0 | 167 | #ifdef CONFIG_ENV_IS_IN_FLASH |
887e2ec9 SR |
168 | /* Monitor protection ON by default */ |
169 | (void)flash_protect(FLAG_PROTECT_SET, | |
6d0f6bcf | 170 | -CONFIG_SYS_MONITOR_LEN, |
887e2ec9 SR |
171 | 0xffffffff, |
172 | &flash_info[0]); | |
173 | ||
174 | /* Env protection ON by default */ | |
175 | (void)flash_protect(FLAG_PROTECT_SET, | |
0e8d1586 JCPV |
176 | CONFIG_ENV_ADDR_REDUND, |
177 | CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, | |
887e2ec9 SR |
178 | &flash_info[0]); |
179 | #endif | |
d873133f | 180 | #endif /* CONFIG_SYS_NO_FLASH */ |
887e2ec9 SR |
181 | |
182 | /* | |
183 | * USB suff... | |
184 | */ | |
854bc8da | 185 | #ifdef CONFIG_440EPX |
83a49c8d | 186 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
887e2ec9 | 187 | /* SDR Setting */ |
511d0c72 | 188 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 189 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
190 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
191 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
192 | |
193 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 194 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 195 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 196 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 197 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 198 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 199 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 200 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 201 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 202 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 | 203 | |
83a49c8d MF |
204 | /* |
205 | * An 8-bit/60MHz interface is the only possible alternative | |
206 | * when connecting the Device to the PHY | |
207 | */ | |
511d0c72 | 208 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
83a49c8d | 209 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 210 | |
83a49c8d MF |
211 | /* |
212 | * To enable the USB 2.0 Device function | |
213 | * through the UTMI interface | |
214 | */ | |
511d0c72 | 215 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
83a49c8d | 216 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; |
887e2ec9 | 217 | |
511d0c72 | 218 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
83a49c8d | 219 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; |
887e2ec9 | 220 | |
511d0c72 | 221 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 222 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
223 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
224 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
225 | |
226 | /*clear resets*/ | |
227 | udelay (1000); | |
228 | mtsdr(SDR0_SRST1, 0x00000000); | |
229 | udelay (1000); | |
230 | mtsdr(SDR0_SRST0, 0x00000000); | |
231 | ||
232 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
233 | ||
234 | } else if (strcmp(act, "dev") == 0) { | |
235 | /*-------------------PATCH-------------------------------*/ | |
236 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
237 | ||
238 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 239 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
887e2ec9 | 240 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 241 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 242 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 243 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 244 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 245 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 SR |
246 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
247 | ||
248 | udelay (1000); | |
249 | mtsdr(SDR0_SRST1, 0x672c6000); | |
250 | ||
251 | udelay (1000); | |
252 | mtsdr(SDR0_SRST0, 0x00000080); | |
253 | ||
254 | udelay (1000); | |
255 | mtsdr(SDR0_SRST1, 0x60206000); | |
256 | ||
257 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
258 | ||
259 | udelay (1000); | |
260 | mtsdr(SDR0_SRST1, 0x60306000); | |
261 | /*-------------------PATCH-------------------------------*/ | |
262 | ||
263 | /* SDR Setting */ | |
511d0c72 | 264 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
887e2ec9 | 265 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
f780b833 | 266 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
267 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
268 | ||
269 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 270 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 271 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 272 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; |
887e2ec9 | 273 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 274 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; |
887e2ec9 | 275 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 276 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; |
887e2ec9 | 277 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 278 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; |
887e2ec9 SR |
279 | |
280 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
83a49c8d | 281 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; |
887e2ec9 SR |
282 | |
283 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
83a49c8d | 284 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; |
887e2ec9 SR |
285 | |
286 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
83a49c8d | 287 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; |
887e2ec9 | 288 | |
511d0c72 WD |
289 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
290 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
f780b833 | 291 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
292 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
293 | ||
83a49c8d | 294 | /* clear resets */ |
887e2ec9 SR |
295 | udelay (1000); |
296 | mtsdr(SDR0_SRST1, 0x00000000); | |
297 | udelay (1000); | |
298 | mtsdr(SDR0_SRST0, 0x00000000); | |
299 | ||
300 | printf("USB: Device(int phy)\n"); | |
301 | } | |
854bc8da | 302 | #endif /* CONFIG_440EPX */ |
887e2ec9 | 303 | |
8ce16f55 JO |
304 | mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ |
305 | reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); | |
306 | mtsdr(SDR0_SRST1, reg); | |
307 | ||
a78bc443 SR |
308 | /* |
309 | * Clear PLB4A0_ACR[WRP] | |
310 | * This fix will make the MAL burst disabling patch for the Linux | |
311 | * EMAC driver obsolete. | |
312 | */ | |
5e7abce9 SR |
313 | reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; |
314 | mtdcr(PLB4A0_ACR, reg); | |
a78bc443 | 315 | |
887e2ec9 SR |
316 | return 0; |
317 | } | |
318 | ||
319 | int checkboard(void) | |
320 | { | |
f0c0b3a9 WD |
321 | char buf[64]; |
322 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
e0b9ea8c | 323 | u8 rev; |
23c51a2d | 324 | u32 clock = get_async_pci_freq(); |
887e2ec9 | 325 | |
854bc8da | 326 | #ifdef CONFIG_440EPX |
887e2ec9 | 327 | printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
854bc8da SR |
328 | #else |
329 | printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); | |
330 | #endif | |
e0b9ea8c | 331 | |
6d0f6bcf | 332 | rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); |
23c51a2d | 333 | printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); |
e0b9ea8c | 334 | |
f0c0b3a9 | 335 | if (i > 0) { |
887e2ec9 | 336 | puts(", serial# "); |
f0c0b3a9 | 337 | puts(buf); |
887e2ec9 SR |
338 | } |
339 | putc('\n'); | |
340 | ||
23c51a2d SR |
341 | /* |
342 | * Reconfiguration of the PCI sync clock is already done, | |
343 | * now check again if everything is in range: | |
344 | */ | |
345 | if (ppc4xx_pci_sync_clock_config(clock)) { | |
346 | printf("ERROR: PCI clocking incorrect (async=%d " | |
347 | "sync=%ld)!\n", clock, get_PCI_freq()); | |
348 | } | |
349 | ||
887e2ec9 SR |
350 | return (0); |
351 | } | |
352 | ||
1f84021a MF |
353 | #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) |
354 | /* | |
355 | * Assign interrupts to PCI devices. | |
356 | */ | |
a760b020 | 357 | void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
1f84021a | 358 | { |
d1631fe1 | 359 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); |
1f84021a MF |
360 | } |
361 | #endif | |
362 | ||
d873133f | 363 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) |
5132106a SR |
364 | /* |
365 | * On NAND-booting sequoia, we need to patch the chips select numbers | |
366 | * in the dtb (CS0 - NAND, CS3 - NOR) | |
367 | */ | |
368 | void ft_board_setup(void *blob, bd_t *bd) | |
369 | { | |
370 | int rc; | |
371 | int len; | |
372 | int nodeoffset; | |
373 | struct fdt_property *prop; | |
374 | u32 *reg; | |
375 | char path[32]; | |
376 | ||
377 | /* First do common fdt setup */ | |
378 | __ft_board_setup(blob, bd); | |
379 | ||
380 | /* And now configure NOR chip select to 3 instead of 0 */ | |
381 | strcpy(path, "/plb/opb/ebc/nor_flash@0,0"); | |
382 | nodeoffset = fdt_path_offset(blob, path); | |
383 | prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); | |
384 | if (prop == NULL) { | |
385 | printf("Unable to update NOR chip select for NAND booting\n"); | |
386 | return; | |
387 | } | |
388 | reg = (u32 *)&prop->data[0]; | |
389 | reg[0] = 3; | |
390 | rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); | |
391 | if (rc) { | |
392 | printf("Unable to update property NOR mappings, err=%s\n", | |
393 | fdt_strerror(rc)); | |
394 | return; | |
395 | } | |
396 | ||
397 | /* And now configure NAND chip select to 0 instead of 3 */ | |
398 | strcpy(path, "/plb/opb/ebc/ndfc@3,0"); | |
399 | nodeoffset = fdt_path_offset(blob, path); | |
400 | prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); | |
401 | if (prop == NULL) { | |
402 | printf("Unable to update NDFC chip select for NAND booting\n"); | |
403 | return; | |
404 | } | |
405 | reg = (u32 *)&prop->data[0]; | |
406 | reg[0] = 0; | |
407 | rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); | |
408 | if (rc) { | |
409 | printf("Unable to update property NDFC mappings, err=%s\n", | |
410 | fdt_strerror(rc)); | |
411 | return; | |
412 | } | |
413 | } | |
414 | #endif /* CONFIG_NAND_U_BOOT */ |