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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <version.h> | |
16 | #include <environment.h> | |
17 | #include <fdtdec.h> | |
f828bf25 | 18 | #include <fs.h> |
e4fef6cf SG |
19 | #if defined(CONFIG_CMD_IDE) |
20 | #include <ide.h> | |
21 | #endif | |
22 | #include <i2c.h> | |
1938f4a5 SG |
23 | #include <initcall.h> |
24 | #include <logbuff.h> | |
e4fef6cf SG |
25 | |
26 | /* TODO: Can we move these into arch/ headers? */ | |
27 | #ifdef CONFIG_8xx | |
28 | #include <mpc8xx.h> | |
29 | #endif | |
30 | #ifdef CONFIG_5xx | |
31 | #include <mpc5xx.h> | |
32 | #endif | |
33 | #ifdef CONFIG_MPC5xxx | |
34 | #include <mpc5xxx.h> | |
35 | #endif | |
36 | ||
a733b06b | 37 | #include <os.h> |
1938f4a5 | 38 | #include <post.h> |
e4fef6cf | 39 | #include <spi.h> |
71c52dba | 40 | #include <trace.h> |
e4fef6cf | 41 | #include <watchdog.h> |
a733b06b | 42 | #include <asm/errno.h> |
1938f4a5 | 43 | #include <asm/io.h> |
e4fef6cf SG |
44 | #ifdef CONFIG_MP |
45 | #include <asm/mp.h> | |
46 | #endif | |
1938f4a5 | 47 | #include <asm/sections.h> |
48a33806 SG |
48 | #ifdef CONFIG_X86 |
49 | #include <asm/init_helpers.h> | |
50 | #include <asm/relocate.h> | |
51 | #endif | |
a733b06b SG |
52 | #ifdef CONFIG_SANDBOX |
53 | #include <asm/state.h> | |
54 | #endif | |
1938f4a5 SG |
55 | #include <linux/compiler.h> |
56 | ||
57 | /* | |
58 | * Pointer to initial global data area | |
59 | * | |
60 | * Here we initialize it if needed. | |
61 | */ | |
62 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
63 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
64 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
65 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
66 | #else | |
67 | DECLARE_GLOBAL_DATA_PTR; | |
68 | #endif | |
69 | ||
70 | /* | |
71 | * sjg: IMO this code should be | |
72 | * refactored to a single function, something like: | |
73 | * | |
74 | * void led_set_state(enum led_colour_t colour, int on); | |
75 | */ | |
76 | /************************************************************************ | |
77 | * Coloured LED functionality | |
78 | ************************************************************************ | |
79 | * May be supplied by boards if desired | |
80 | */ | |
81 | inline void __coloured_LED_init(void) {} | |
82 | void coloured_LED_init(void) | |
83 | __attribute__((weak, alias("__coloured_LED_init"))); | |
84 | inline void __red_led_on(void) {} | |
85 | void red_led_on(void) __attribute__((weak, alias("__red_led_on"))); | |
86 | inline void __red_led_off(void) {} | |
87 | void red_led_off(void) __attribute__((weak, alias("__red_led_off"))); | |
88 | inline void __green_led_on(void) {} | |
89 | void green_led_on(void) __attribute__((weak, alias("__green_led_on"))); | |
90 | inline void __green_led_off(void) {} | |
91 | void green_led_off(void) __attribute__((weak, alias("__green_led_off"))); | |
92 | inline void __yellow_led_on(void) {} | |
93 | void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on"))); | |
94 | inline void __yellow_led_off(void) {} | |
95 | void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off"))); | |
96 | inline void __blue_led_on(void) {} | |
97 | void blue_led_on(void) __attribute__((weak, alias("__blue_led_on"))); | |
98 | inline void __blue_led_off(void) {} | |
99 | void blue_led_off(void) __attribute__((weak, alias("__blue_led_off"))); | |
100 | ||
101 | /* | |
102 | * Why is gd allocated a register? Prior to reloc it might be better to | |
103 | * just pass it around to each function in this file? | |
104 | * | |
105 | * After reloc one could argue that it is hardly used and doesn't need | |
106 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
107 | * global data for all modules, so that post-reloc we can avoid the massive | |
108 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
109 | * a structure... | |
110 | */ | |
111 | ||
112 | /* | |
113 | * Could the CONFIG_SPL_BUILD infection become a flag in gd? | |
114 | */ | |
115 | ||
e4fef6cf SG |
116 | #if defined(CONFIG_WATCHDOG) |
117 | static int init_func_watchdog_init(void) | |
118 | { | |
119 | puts(" Watchdog enabled\n"); | |
120 | WATCHDOG_RESET(); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | int init_func_watchdog_reset(void) | |
126 | { | |
127 | WATCHDOG_RESET(); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | #endif /* CONFIG_WATCHDOG */ | |
132 | ||
133 | void __board_add_ram_info(int use_default) | |
134 | { | |
135 | /* please define platform specific board_add_ram_info() */ | |
136 | } | |
137 | ||
138 | void board_add_ram_info(int) | |
139 | __attribute__ ((weak, alias("__board_add_ram_info"))); | |
140 | ||
1938f4a5 SG |
141 | static int init_baud_rate(void) |
142 | { | |
143 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
144 | return 0; | |
145 | } | |
146 | ||
147 | static int display_text_info(void) | |
148 | { | |
a733b06b | 149 | #ifndef CONFIG_SANDBOX |
1938f4a5 SG |
150 | ulong bss_start, bss_end; |
151 | ||
632efa74 | 152 | #ifdef CONFIG_SYS_SYM_OFFSETS |
1938f4a5 SG |
153 | bss_start = _bss_start_ofs + _TEXT_BASE; |
154 | bss_end = _bss_end_ofs + _TEXT_BASE; | |
632efa74 SG |
155 | #else |
156 | bss_start = (ulong)&__bss_start; | |
157 | bss_end = (ulong)&__bss_end; | |
158 | #endif | |
1938f4a5 SG |
159 | debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", |
160 | CONFIG_SYS_TEXT_BASE, bss_start, bss_end); | |
a733b06b | 161 | #endif |
1938f4a5 SG |
162 | |
163 | #ifdef CONFIG_MODEM_SUPPORT | |
164 | debug("Modem Support enabled\n"); | |
165 | #endif | |
166 | #ifdef CONFIG_USE_IRQ | |
167 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
168 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
169 | #endif | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | static int announce_dram_init(void) | |
175 | { | |
176 | puts("DRAM: "); | |
177 | return 0; | |
178 | } | |
179 | ||
e4fef6cf SG |
180 | #ifdef CONFIG_PPC |
181 | static int init_func_ram(void) | |
182 | { | |
183 | #ifdef CONFIG_BOARD_TYPES | |
184 | int board_type = gd->board_type; | |
185 | #else | |
186 | int board_type = 0; /* use dummy arg */ | |
187 | #endif | |
188 | ||
189 | gd->ram_size = initdram(board_type); | |
190 | ||
191 | if (gd->ram_size > 0) | |
192 | return 0; | |
193 | ||
194 | puts("*** failed ***\n"); | |
195 | return 1; | |
196 | } | |
197 | #endif | |
198 | ||
1938f4a5 SG |
199 | static int show_dram_config(void) |
200 | { | |
201 | ulong size; | |
202 | ||
203 | #ifdef CONFIG_NR_DRAM_BANKS | |
204 | int i; | |
205 | ||
206 | debug("\nRAM Configuration:\n"); | |
207 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
208 | size += gd->bd->bi_dram[i].size; | |
209 | debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); | |
210 | #ifdef DEBUG | |
211 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
212 | #endif | |
213 | } | |
214 | debug("\nDRAM: "); | |
215 | #else | |
216 | size = gd->ram_size; | |
217 | #endif | |
218 | ||
e4fef6cf SG |
219 | print_size(size, ""); |
220 | board_add_ram_info(0); | |
221 | putc('\n'); | |
1938f4a5 SG |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
e4fef6cf SG |
226 | ulong get_effective_memsize(void) |
227 | { | |
228 | #ifndef CONFIG_VERY_BIG_RAM | |
229 | return gd->ram_size; | |
230 | #else | |
231 | /* limit stack to what we can reasonable map */ | |
232 | return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? | |
233 | CONFIG_MAX_MEM_MAPPED : gd->ram_size); | |
234 | #endif | |
235 | } | |
236 | ||
1938f4a5 SG |
237 | void __dram_init_banksize(void) |
238 | { | |
239 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
240 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
241 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
242 | #endif | |
243 | } | |
244 | ||
245 | void dram_init_banksize(void) | |
246 | __attribute__((weak, alias("__dram_init_banksize"))); | |
247 | ||
ea818dbb | 248 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
249 | static int init_func_i2c(void) |
250 | { | |
251 | puts("I2C: "); | |
815a76f2 | 252 | #ifdef CONFIG_SYS_I2C |
253 | i2c_init_all(); | |
254 | #else | |
e4fef6cf | 255 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 256 | #endif |
e4fef6cf SG |
257 | puts("ready\n"); |
258 | return 0; | |
259 | } | |
260 | #endif | |
261 | ||
262 | #if defined(CONFIG_HARD_SPI) | |
263 | static int init_func_spi(void) | |
264 | { | |
265 | puts("SPI: "); | |
266 | spi_init(); | |
267 | puts("ready\n"); | |
268 | return 0; | |
269 | } | |
270 | #endif | |
271 | ||
272 | __maybe_unused | |
1938f4a5 SG |
273 | static int zero_global_data(void) |
274 | { | |
275 | memset((void *)gd, '\0', sizeof(gd_t)); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | static int setup_mon_len(void) | |
281 | { | |
632efa74 | 282 | #ifdef CONFIG_SYS_SYM_OFFSETS |
1938f4a5 | 283 | gd->mon_len = _bss_end_ofs; |
a733b06b SG |
284 | #elif defined(CONFIG_SANDBOX) |
285 | gd->mon_len = (ulong)&_end - (ulong)_init; | |
632efa74 | 286 | #else |
e4fef6cf SG |
287 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
288 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 289 | #endif |
1938f4a5 SG |
290 | return 0; |
291 | } | |
292 | ||
293 | __weak int arch_cpu_init(void) | |
294 | { | |
295 | return 0; | |
296 | } | |
297 | ||
f828bf25 SG |
298 | #ifdef CONFIG_OF_HOSTFILE |
299 | ||
300 | #define CHECK(x) err = (x); if (err) goto failed; | |
301 | ||
302 | /* Create an empty device tree blob */ | |
303 | static int make_empty_fdt(void *fdt) | |
304 | { | |
305 | int err; | |
306 | ||
307 | CHECK(fdt_create(fdt, 256)); | |
308 | CHECK(fdt_finish_reservemap(fdt)); | |
309 | CHECK(fdt_begin_node(fdt, "")); | |
310 | CHECK(fdt_end_node(fdt)); | |
311 | CHECK(fdt_finish(fdt)); | |
312 | ||
313 | return 0; | |
314 | failed: | |
315 | printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); | |
316 | return -EACCES; | |
317 | } | |
318 | ||
319 | static int read_fdt_from_file(void) | |
320 | { | |
321 | struct sandbox_state *state = state_get_current(); | |
322 | void *blob; | |
323 | int size; | |
324 | int err; | |
325 | ||
326 | blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); | |
327 | if (!state->fdt_fname) { | |
328 | err = make_empty_fdt(blob); | |
329 | if (!err) | |
330 | goto done; | |
331 | return err; | |
332 | } | |
333 | err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX); | |
334 | if (err) | |
335 | return err; | |
336 | size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0); | |
337 | if (size < 0) | |
338 | return -EIO; | |
339 | ||
340 | done: | |
341 | gd->fdt_blob = blob; | |
342 | ||
343 | return 0; | |
344 | } | |
345 | #endif | |
346 | ||
a733b06b SG |
347 | #ifdef CONFIG_SANDBOX |
348 | static int setup_ram_buf(void) | |
349 | { | |
350 | gd->arch.ram_buf = os_malloc(CONFIG_SYS_SDRAM_SIZE); | |
351 | assert(gd->arch.ram_buf); | |
352 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; | |
353 | ||
354 | return 0; | |
355 | } | |
356 | #endif | |
357 | ||
1938f4a5 SG |
358 | static int setup_fdt(void) |
359 | { | |
360 | #ifdef CONFIG_OF_EMBED | |
361 | /* Get a pointer to the FDT */ | |
362 | gd->fdt_blob = _binary_dt_dtb_start; | |
363 | #elif defined CONFIG_OF_SEPARATE | |
364 | /* FDT is at end of image */ | |
632efa74 | 365 | # ifdef CONFIG_SYS_SYM_OFFSETS |
1938f4a5 | 366 | gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE); |
632efa74 SG |
367 | # else |
368 | gd->fdt_blob = (ulong *)&_end; | |
369 | # endif | |
f828bf25 SG |
370 | #elif defined(CONFIG_OF_HOSTFILE) |
371 | if (read_fdt_from_file()) { | |
372 | puts("Failed to read control FDT\n"); | |
373 | return -1; | |
374 | } | |
1938f4a5 SG |
375 | #endif |
376 | /* Allow the early environment to override the fdt address */ | |
377 | gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, | |
378 | (uintptr_t)gd->fdt_blob); | |
379 | return 0; | |
380 | } | |
381 | ||
382 | /* Get the top of usable RAM */ | |
383 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
384 | { | |
385 | return gd->ram_top; | |
386 | } | |
387 | ||
388 | static int setup_dest_addr(void) | |
389 | { | |
390 | debug("Monitor len: %08lX\n", gd->mon_len); | |
391 | /* | |
392 | * Ram is setup, size stored in gd !! | |
393 | */ | |
394 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
395 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) | |
396 | /* | |
397 | * Subtract specified amount of memory to hide so that it won't | |
398 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
399 | * the Linux kernel should now get passed the now "corrected" | |
400 | * memory size and won't touch it either. This should work | |
401 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
402 | * arch/powerpc with bootwrapper support, that recalculate the | |
403 | * memory size from the SDRAM controller setup will have to | |
404 | * get fixed. | |
405 | */ | |
406 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; | |
407 | #endif | |
408 | #ifdef CONFIG_SYS_SDRAM_BASE | |
409 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
410 | #endif | |
e4fef6cf | 411 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 412 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 413 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 414 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
e4fef6cf SG |
415 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
416 | /* | |
417 | * We need to make sure the location we intend to put secondary core | |
418 | * boot code is reserved and not used by any part of u-boot | |
419 | */ | |
a0ba279a MY |
420 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
421 | gd->relocaddr = determine_mp_bootpg(NULL); | |
422 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
423 | } |
424 | #endif | |
1938f4a5 SG |
425 | return 0; |
426 | } | |
427 | ||
428 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
429 | static int reserve_logbuffer(void) | |
430 | { | |
431 | /* reserve kernel log buffer */ | |
a0ba279a | 432 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 433 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 434 | gd->relocaddr); |
1938f4a5 SG |
435 | return 0; |
436 | } | |
437 | #endif | |
438 | ||
439 | #ifdef CONFIG_PRAM | |
440 | /* reserve protected RAM */ | |
441 | static int reserve_pram(void) | |
442 | { | |
443 | ulong reg; | |
444 | ||
445 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 446 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 447 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 448 | gd->relocaddr); |
1938f4a5 SG |
449 | return 0; |
450 | } | |
451 | #endif /* CONFIG_PRAM */ | |
452 | ||
453 | /* Round memory pointer down to next 4 kB limit */ | |
454 | static int reserve_round_4k(void) | |
455 | { | |
a0ba279a | 456 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
457 | return 0; |
458 | } | |
459 | ||
460 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
461 | defined(CONFIG_ARM) | |
462 | static int reserve_mmu(void) | |
463 | { | |
464 | /* reserve TLB table */ | |
465 | gd->arch.tlb_size = 4096 * 4; | |
a0ba279a | 466 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
467 | |
468 | /* round down to next 64 kB limit */ | |
a0ba279a | 469 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 470 | |
a0ba279a | 471 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
472 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
473 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
474 | return 0; | |
475 | } | |
476 | #endif | |
477 | ||
478 | #ifdef CONFIG_LCD | |
479 | static int reserve_lcd(void) | |
480 | { | |
481 | #ifdef CONFIG_FB_ADDR | |
482 | gd->fb_base = CONFIG_FB_ADDR; | |
483 | #else | |
484 | /* reserve memory for LCD display (always full pages) */ | |
a0ba279a MY |
485 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
486 | gd->fb_base = gd->relocaddr; | |
1938f4a5 SG |
487 | #endif /* CONFIG_FB_ADDR */ |
488 | return 0; | |
489 | } | |
490 | #endif /* CONFIG_LCD */ | |
491 | ||
71c52dba SG |
492 | static int reserve_trace(void) |
493 | { | |
494 | #ifdef CONFIG_TRACE | |
495 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
496 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
497 | debug("Reserving %dk for trace data at: %08lx\n", | |
498 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
499 | #endif | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
e4fef6cf | 504 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ |
48a33806 | 505 | && !defined(CONFIG_ARM) && !defined(CONFIG_X86) |
e4fef6cf SG |
506 | static int reserve_video(void) |
507 | { | |
508 | /* reserve memory for video display (always full pages) */ | |
a0ba279a MY |
509 | gd->relocaddr = video_setmem(gd->relocaddr); |
510 | gd->fb_base = gd->relocaddr; | |
e4fef6cf SG |
511 | |
512 | return 0; | |
513 | } | |
514 | #endif | |
515 | ||
1938f4a5 SG |
516 | static int reserve_uboot(void) |
517 | { | |
518 | /* | |
519 | * reserve memory for U-Boot code, data & bss | |
520 | * round down to next 4 kB limit | |
521 | */ | |
a0ba279a MY |
522 | gd->relocaddr -= gd->mon_len; |
523 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
524 | #ifdef CONFIG_E500 |
525 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 526 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 527 | #endif |
1938f4a5 SG |
528 | |
529 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
530 | gd->relocaddr); |
531 | ||
532 | gd->start_addr_sp = gd->relocaddr; | |
533 | ||
1938f4a5 SG |
534 | return 0; |
535 | } | |
536 | ||
8cae8a68 | 537 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
538 | /* reserve memory for malloc() area */ |
539 | static int reserve_malloc(void) | |
540 | { | |
a0ba279a | 541 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 542 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 543 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
544 | return 0; |
545 | } | |
546 | ||
547 | /* (permanently) allocate a Board Info struct */ | |
548 | static int reserve_board(void) | |
549 | { | |
a0ba279a MY |
550 | gd->start_addr_sp -= sizeof(bd_t); |
551 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
1938f4a5 SG |
552 | memset(gd->bd, '\0', sizeof(bd_t)); |
553 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
a0ba279a | 554 | sizeof(bd_t), gd->start_addr_sp); |
1938f4a5 SG |
555 | return 0; |
556 | } | |
8cae8a68 | 557 | #endif |
1938f4a5 SG |
558 | |
559 | static int setup_machine(void) | |
560 | { | |
561 | #ifdef CONFIG_MACH_TYPE | |
562 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
563 | #endif | |
564 | return 0; | |
565 | } | |
566 | ||
567 | static int reserve_global_data(void) | |
568 | { | |
a0ba279a MY |
569 | gd->start_addr_sp -= sizeof(gd_t); |
570 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 571 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 572 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
573 | return 0; |
574 | } | |
575 | ||
576 | static int reserve_fdt(void) | |
577 | { | |
578 | /* | |
579 | * If the device tree is sitting immediate above our image then we | |
580 | * must relocate it. If it is embedded in the data section, then it | |
581 | * will be relocated with other data. | |
582 | */ | |
583 | if (gd->fdt_blob) { | |
584 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
585 | ||
a0ba279a MY |
586 | gd->start_addr_sp -= gd->fdt_size; |
587 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 588 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 589 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 SG |
590 | } |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | static int reserve_stacks(void) | |
596 | { | |
8cae8a68 SG |
597 | #ifdef CONFIG_SPL_BUILD |
598 | # ifdef CONFIG_ARM | |
a0ba279a MY |
599 | gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ |
600 | gd->irq_sp = gd->start_addr_sp; | |
8cae8a68 SG |
601 | # endif |
602 | #else | |
e4fef6cf SG |
603 | # ifdef CONFIG_PPC |
604 | ulong *s; | |
605 | # endif | |
8cae8a68 | 606 | |
1938f4a5 | 607 | /* setup stack pointer for exceptions */ |
a0ba279a MY |
608 | gd->start_addr_sp -= 16; |
609 | gd->start_addr_sp &= ~0xf; | |
610 | gd->irq_sp = gd->start_addr_sp; | |
1938f4a5 SG |
611 | |
612 | /* | |
613 | * Handle architecture-specific things here | |
614 | * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack() | |
615 | * to handle this and put in arch/xxx/lib/stack.c | |
616 | */ | |
617 | # ifdef CONFIG_ARM | |
618 | # ifdef CONFIG_USE_IRQ | |
a0ba279a | 619 | gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); |
1938f4a5 | 620 | debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", |
a0ba279a | 621 | CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp); |
1938f4a5 SG |
622 | |
623 | /* 8-byte alignment for ARM ABI compliance */ | |
a0ba279a | 624 | gd->start_addr_sp &= ~0x07; |
1938f4a5 SG |
625 | # endif |
626 | /* leave 3 words for abort-stack, plus 1 for alignment */ | |
a0ba279a | 627 | gd->start_addr_sp -= 16; |
e4fef6cf SG |
628 | # elif defined(CONFIG_PPC) |
629 | /* Clear initial stack frame */ | |
a0ba279a | 630 | s = (ulong *) gd->start_addr_sp; |
e4fef6cf SG |
631 | *s = 0; /* Terminate back chain */ |
632 | *++s = 0; /* NULL return address */ | |
8cae8a68 | 633 | # endif /* Architecture specific code */ |
1938f4a5 SG |
634 | |
635 | return 0; | |
8cae8a68 | 636 | #endif |
1938f4a5 SG |
637 | } |
638 | ||
639 | static int display_new_sp(void) | |
640 | { | |
a0ba279a | 641 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
642 | |
643 | return 0; | |
644 | } | |
645 | ||
e4fef6cf SG |
646 | #ifdef CONFIG_PPC |
647 | static int setup_board_part1(void) | |
648 | { | |
649 | bd_t *bd = gd->bd; | |
650 | ||
651 | /* | |
652 | * Save local variables to board info struct | |
653 | */ | |
654 | ||
655 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ | |
656 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
657 | ||
658 | #ifdef CONFIG_SYS_SRAM_BASE | |
659 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
660 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
661 | #endif | |
662 | ||
663 | #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ | |
664 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) | |
665 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
666 | #endif | |
667 | #if defined(CONFIG_MPC5xxx) | |
668 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ | |
669 | #endif | |
670 | #if defined(CONFIG_MPC83xx) | |
671 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
672 | #endif | |
e4fef6cf SG |
673 | |
674 | return 0; | |
675 | } | |
676 | ||
677 | static int setup_board_part2(void) | |
678 | { | |
679 | bd_t *bd = gd->bd; | |
680 | ||
681 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
682 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
683 | #if defined(CONFIG_CPM2) | |
684 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
685 | bd->bi_brgfreq = gd->arch.brg_clk; | |
686 | bd->bi_sccfreq = gd->arch.scc_clk; | |
687 | bd->bi_vco = gd->arch.vco_out; | |
688 | #endif /* CONFIG_CPM2 */ | |
689 | #if defined(CONFIG_MPC512X) | |
690 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
691 | #endif /* CONFIG_MPC512X */ | |
692 | #if defined(CONFIG_MPC5xxx) | |
693 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
694 | bd->bi_pcifreq = gd->pci_clk; | |
695 | #endif /* CONFIG_MPC5xxx */ | |
696 | ||
697 | return 0; | |
698 | } | |
699 | #endif | |
700 | ||
701 | #ifdef CONFIG_SYS_EXTBDINFO | |
702 | static int setup_board_extra(void) | |
703 | { | |
704 | bd_t *bd = gd->bd; | |
705 | ||
706 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); | |
707 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
708 | sizeof(bd->bi_r_version)); | |
709 | ||
710 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
711 | bd->bi_plb_busfreq = gd->bus_clk; | |
712 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ | |
713 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
714 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
715 | bd->bi_pci_busfreq = get_PCI_freq(); | |
716 | bd->bi_opbfreq = get_OPB_freq(); | |
717 | #elif defined(CONFIG_XILINX_405) | |
718 | bd->bi_pci_busfreq = get_PCI_freq(); | |
719 | #endif | |
720 | ||
721 | return 0; | |
722 | } | |
723 | #endif | |
724 | ||
1938f4a5 SG |
725 | #ifdef CONFIG_POST |
726 | static int init_post(void) | |
727 | { | |
728 | post_bootmode_init(); | |
729 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
730 | ||
731 | return 0; | |
732 | } | |
733 | #endif | |
734 | ||
735 | static int setup_baud_rate(void) | |
736 | { | |
737 | /* Ick, can we get rid of this line? */ | |
738 | gd->bd->bi_baudrate = gd->baudrate; | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
743 | static int setup_dram_config(void) | |
744 | { | |
745 | /* Ram is board specific, so move it to board code ... */ | |
746 | dram_init_banksize(); | |
747 | ||
748 | return 0; | |
749 | } | |
750 | ||
751 | static int reloc_fdt(void) | |
752 | { | |
753 | if (gd->new_fdt) { | |
754 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
755 | gd->fdt_blob = gd->new_fdt; | |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | static int setup_reloc(void) | |
762 | { | |
a0ba279a | 763 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
1938f4a5 SG |
764 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
765 | ||
766 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 767 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
768 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
769 | gd->start_addr_sp); | |
1938f4a5 SG |
770 | |
771 | return 0; | |
772 | } | |
773 | ||
774 | /* ARM calls relocate_code from its crt0.S */ | |
775 | #if !defined(CONFIG_ARM) | |
776 | ||
777 | static int jump_to_copy(void) | |
778 | { | |
48a33806 SG |
779 | /* |
780 | * x86 is special, but in a nice way. It uses a trampoline which | |
781 | * enables the dcache if possible. | |
782 | * | |
783 | * For now, other archs use relocate_code(), which is implemented | |
784 | * similarly for all archs. When we do generic relocation, hopefully | |
785 | * we can make all archs enable the dcache prior to relocation. | |
786 | */ | |
787 | #ifdef CONFIG_X86 | |
788 | /* | |
789 | * SDRAM and console are now initialised. The final stack can now | |
790 | * be setup in SDRAM. Code execution will continue in Flash, but | |
791 | * with the stack in SDRAM and Global Data in temporary memory | |
792 | * (CPU cache) | |
793 | */ | |
794 | board_init_f_r_trampoline(gd->start_addr_sp); | |
a733b06b SG |
795 | #elif defined(CONFIG_SANDBOX) |
796 | board_init_r(gd->new_gd, 0); | |
48a33806 | 797 | #else |
a0ba279a | 798 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 799 | #endif |
1938f4a5 SG |
800 | |
801 | return 0; | |
802 | } | |
803 | #endif | |
804 | ||
805 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
806 | static int mark_bootstage(void) | |
807 | { | |
808 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | static init_fnc_t init_sequence_f[] = { | |
e4fef6cf SG |
814 | #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ |
815 | !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ | |
7525c2da | 816 | !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86) |
632efa74 | 817 | zero_global_data, |
a733b06b SG |
818 | #endif |
819 | #ifdef CONFIG_SANDBOX | |
820 | setup_ram_buf, | |
e4fef6cf | 821 | #endif |
1938f4a5 | 822 | setup_mon_len, |
71c52dba SG |
823 | setup_fdt, |
824 | trace_early_init, | |
e4fef6cf SG |
825 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
826 | /* TODO: can this go into arch_cpu_init()? */ | |
827 | probecpu, | |
828 | #endif | |
1938f4a5 | 829 | arch_cpu_init, /* basic arch cpu dependent setup */ |
48a33806 SG |
830 | #ifdef CONFIG_X86 |
831 | cpu_init_f, /* TODO(sjg@chromium.org): remove */ | |
832 | # ifdef CONFIG_OF_CONTROL | |
833 | find_fdt, /* TODO(sjg@chromium.org): remove */ | |
834 | # endif | |
835 | #endif | |
1938f4a5 SG |
836 | mark_bootstage, |
837 | #ifdef CONFIG_OF_CONTROL | |
838 | fdtdec_check_fdt, | |
839 | #endif | |
840 | #if defined(CONFIG_BOARD_EARLY_INIT_F) | |
841 | board_early_init_f, | |
842 | #endif | |
e4fef6cf SG |
843 | /* TODO: can any of this go into arch_cpu_init()? */ |
844 | #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) | |
845 | get_clocks, /* get CPU and bus clocks (etc.) */ | |
846 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ | |
847 | && !defined(CONFIG_TQM885D) | |
848 | adjust_sdram_tbs_8xx, | |
849 | #endif | |
850 | /* TODO: can we rename this to timer_init()? */ | |
851 | init_timebase, | |
852 | #endif | |
e4fef6cf | 853 | #ifdef CONFIG_ARM |
1938f4a5 | 854 | timer_init, /* initialize timer */ |
e4fef6cf | 855 | #endif |
e4fef6cf SG |
856 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
857 | #if !defined(CONFIG_CPM2) | |
858 | dpram_init, | |
859 | #endif | |
860 | #endif | |
861 | #if defined(CONFIG_BOARD_POSTCLK_INIT) | |
862 | board_postclk_init, | |
b8521b74 MY |
863 | #endif |
864 | #ifdef CONFIG_FSL_ESDHC | |
865 | get_clocks, | |
1938f4a5 SG |
866 | #endif |
867 | env_init, /* initialize environment */ | |
e4fef6cf SG |
868 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
869 | /* get CPU and bus clocks according to the environment variable */ | |
870 | get_clocks_866, | |
871 | /* adjust sdram refresh rate according to the new clock */ | |
872 | sdram_adjust_866, | |
873 | init_timebase, | |
874 | #endif | |
1938f4a5 SG |
875 | init_baud_rate, /* initialze baudrate settings */ |
876 | serial_init, /* serial communications setup */ | |
877 | console_init_f, /* stage 1 init of console */ | |
a733b06b SG |
878 | #ifdef CONFIG_SANDBOX |
879 | sandbox_early_getopt_check, | |
880 | #endif | |
881 | #ifdef CONFIG_OF_CONTROL | |
882 | fdtdec_prepare_fdt, | |
48a33806 | 883 | #endif |
1938f4a5 SG |
884 | display_options, /* say that we are here */ |
885 | display_text_info, /* show debugging info if required */ | |
e4fef6cf SG |
886 | #if defined(CONFIG_8260) |
887 | prt_8260_rsr, | |
888 | prt_8260_clks, | |
889 | #endif /* CONFIG_8260 */ | |
890 | #if defined(CONFIG_MPC83xx) | |
891 | prt_83xx_rsr, | |
892 | #endif | |
893 | #ifdef CONFIG_PPC | |
894 | checkcpu, | |
895 | #endif | |
1938f4a5 SG |
896 | #if defined(CONFIG_DISPLAY_CPUINFO) |
897 | print_cpuinfo, /* display cpu info (and speed) */ | |
898 | #endif | |
e4fef6cf SG |
899 | #if defined(CONFIG_MPC5xxx) |
900 | prt_mpc5xxx_clks, | |
901 | #endif /* CONFIG_MPC5xxx */ | |
1938f4a5 SG |
902 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
903 | checkboard, /* display board info */ | |
e4fef6cf SG |
904 | #endif |
905 | INIT_FUNC_WATCHDOG_INIT | |
906 | #if defined(CONFIG_MISC_INIT_F) | |
907 | misc_init_f, | |
908 | #endif | |
909 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 910 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
911 | init_func_i2c, |
912 | #endif | |
913 | #if defined(CONFIG_HARD_SPI) | |
914 | init_func_spi, | |
915 | #endif | |
916 | #ifdef CONFIG_X86 | |
917 | dram_init_f, /* configure available RAM banks */ | |
8b42dfc3 | 918 | calculate_relocation_address, |
1938f4a5 SG |
919 | #endif |
920 | announce_dram_init, | |
921 | /* TODO: unify all these dram functions? */ | |
922 | #ifdef CONFIG_ARM | |
923 | dram_init, /* configure available RAM banks */ | |
924 | #endif | |
e4fef6cf SG |
925 | #ifdef CONFIG_PPC |
926 | init_func_ram, | |
927 | #endif | |
928 | #ifdef CONFIG_POST | |
929 | post_init_f, | |
930 | #endif | |
931 | INIT_FUNC_WATCHDOG_RESET | |
932 | #if defined(CONFIG_SYS_DRAM_TEST) | |
933 | testdram, | |
934 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
935 | INIT_FUNC_WATCHDOG_RESET | |
936 | ||
1938f4a5 SG |
937 | #ifdef CONFIG_POST |
938 | init_post, | |
939 | #endif | |
e4fef6cf | 940 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
941 | /* |
942 | * Now that we have DRAM mapped and working, we can | |
943 | * relocate the code and continue running from DRAM. | |
944 | * | |
945 | * Reserve memory at end of RAM for (top down in that order): | |
946 | * - area that won't get touched by U-Boot and Linux (optional) | |
947 | * - kernel log buffer | |
948 | * - protected RAM | |
949 | * - LCD framebuffer | |
950 | * - monitor code | |
951 | * - board info struct | |
952 | */ | |
953 | setup_dest_addr, | |
954 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
955 | reserve_logbuffer, | |
956 | #endif | |
957 | #ifdef CONFIG_PRAM | |
958 | reserve_pram, | |
959 | #endif | |
960 | reserve_round_4k, | |
961 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
962 | defined(CONFIG_ARM) | |
963 | reserve_mmu, | |
964 | #endif | |
965 | #ifdef CONFIG_LCD | |
966 | reserve_lcd, | |
e4fef6cf | 967 | #endif |
71c52dba | 968 | reserve_trace, |
e4fef6cf SG |
969 | /* TODO: Why the dependency on CONFIG_8xx? */ |
970 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ | |
48a33806 | 971 | && !defined(CONFIG_ARM) && !defined(CONFIG_X86) |
e4fef6cf | 972 | reserve_video, |
1938f4a5 SG |
973 | #endif |
974 | reserve_uboot, | |
8cae8a68 | 975 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
976 | reserve_malloc, |
977 | reserve_board, | |
8cae8a68 | 978 | #endif |
1938f4a5 SG |
979 | setup_machine, |
980 | reserve_global_data, | |
981 | reserve_fdt, | |
982 | reserve_stacks, | |
983 | setup_dram_config, | |
984 | show_dram_config, | |
e4fef6cf SG |
985 | #ifdef CONFIG_PPC |
986 | setup_board_part1, | |
987 | INIT_FUNC_WATCHDOG_RESET | |
988 | setup_board_part2, | |
989 | #endif | |
1938f4a5 SG |
990 | setup_baud_rate, |
991 | display_new_sp, | |
e4fef6cf SG |
992 | #ifdef CONFIG_SYS_EXTBDINFO |
993 | setup_board_extra, | |
994 | #endif | |
995 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
996 | reloc_fdt, |
997 | setup_reloc, | |
998 | #ifndef CONFIG_ARM | |
999 | jump_to_copy, | |
1000 | #endif | |
1001 | NULL, | |
1002 | }; | |
1003 | ||
1004 | void board_init_f(ulong boot_flags) | |
1005 | { | |
48a33806 | 1006 | #ifndef CONFIG_X86 |
1938f4a5 SG |
1007 | gd_t data; |
1008 | ||
1009 | gd = &data; | |
48a33806 | 1010 | #endif |
1938f4a5 SG |
1011 | |
1012 | gd->flags = boot_flags; | |
9aed5a27 | 1013 | gd->have_console = 0; |
1938f4a5 SG |
1014 | |
1015 | if (initcall_run_list(init_sequence_f)) | |
1016 | hang(); | |
1017 | ||
1018 | #ifndef CONFIG_ARM | |
1019 | /* NOTREACHED - jump_to_copy() does not return */ | |
1020 | hang(); | |
1021 | #endif | |
1022 | } | |
1023 | ||
48a33806 SG |
1024 | #ifdef CONFIG_X86 |
1025 | /* | |
1026 | * For now this code is only used on x86. | |
1027 | * | |
1028 | * init_sequence_f_r is the list of init functions which are run when | |
1029 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
1030 | * The following limitations must be considered when implementing an | |
1031 | * '_f_r' function: | |
1032 | * - 'static' variables are read-only | |
1033 | * - Global Data (gd->xxx) is read/write | |
1034 | * | |
1035 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1036 | * supported). It _should_, if possible, copy global data to RAM and | |
1037 | * initialise the CPU caches (to speed up the relocation process) | |
1038 | * | |
1039 | * NOTE: At present only x86 uses this route, but it is intended that | |
1040 | * all archs will move to this when generic relocation is implemented. | |
1041 | */ | |
1042 | static init_fnc_t init_sequence_f_r[] = { | |
1043 | init_cache_f_r, | |
1044 | copy_uboot_to_ram, | |
1045 | clear_bss, | |
1046 | do_elf_reloc_fixups, | |
1047 | ||
1048 | NULL, | |
1049 | }; | |
1050 | ||
1051 | void board_init_f_r(void) | |
1052 | { | |
1053 | if (initcall_run_list(init_sequence_f_r)) | |
1054 | hang(); | |
1055 | ||
1056 | /* | |
1057 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1058 | * Transfer execution from Flash to RAM by calculating the address | |
1059 | * of the in-RAM copy of board_init_r() and calling it | |
1060 | */ | |
1061 | (board_init_r + gd->reloc_off)(gd, gd->relocaddr); | |
1062 | ||
1063 | /* NOTREACHED - board_init_r() does not return */ | |
1064 | hang(); | |
1065 | } | |
1066 | #endif /* CONFIG_X86 */ |