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Merge branch 'master' of git://git.denx.de/u-boot-net
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
CommitLineData
de941241
SG		 1/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
93bfd616 27#include <malloc.h>
de941241
SG		 28#include <mmc.h>
29#include <part.h>
30#include <i2c.h>
31#include <twl4030.h>
14fa2dd0 32#include <twl6030.h>
cb199102 33#include <palmas.h>
de941241
SG		 34#include <asm/io.h>
35#include <asm/arch/mmc_host_def.h>
3b68939f
RQ		 36#if !defined(CONFIG_SOC_KEYSTONE)
37#include <asm/gpio.h>
96e0e7b3 38#include <asm/arch/sys_proto.h>
3b68939f 39#endif
a9d6a7e2 40#include <dm.h>
6aca17c9 41#include <asm/arch-omap3/mux.h>
a9d6a7e2
M		 42
43DECLARE_GLOBAL_DATA_PTR;
de941241 44
ab769f22
PA		 45/* simplify defines to OMAP_HSMMC_USE_GPIO */
46#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
47 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
48#define OMAP_HSMMC_USE_GPIO
49#else
50#undef OMAP_HSMMC_USE_GPIO
51#endif
52
25c719e2
GI		 53/* common definitions for all OMAPs */
54#define SYSCTL_SRC (1 << 25)
55#define SYSCTL_SRD (1 << 26)
56
cc22b0c0
NK		 57struct omap_hsmmc_data {
58 struct hsmmc *base_addr;
93bfd616 59 struct mmc_config cfg;
ab769f22 60#ifdef OMAP_HSMMC_USE_GPIO
a9d6a7e2
M		 61#ifdef CONFIG_DM_MMC
62 struct gpio_desc cd_gpio; /* Change Detect GPIO */
63 struct gpio_desc wp_gpio; /* Write Protect GPIO */
64 bool cd_inverted;
65#else
e874d5b0 66 int cd_gpio;
e3913f56 67 int wp_gpio;
ab769f22 68#endif
a9d6a7e2 69#endif
cc22b0c0
NK		 70};
71
eb9a28f6
NM		 72/* If we fail after 1 second wait, something is really bad */
73#define MAX_RETRY_MS 1000
74
933efe64
S		 75static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
76static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
77 unsigned int siz);
14fa2dd0 78
a9d6a7e2 79#if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
e874d5b0
NK		 80static int omap_mmc_setup_gpio_in(int gpio, const char *label)
81{
5915a2ad 82 int ret;
e874d5b0 83
5915a2ad
SG		 84#ifndef CONFIG_DM_GPIO
85 if (!gpio_is_valid(gpio))
e874d5b0 86 return -1;
5915a2ad
SG		 87#endif
88 ret = gpio_request(gpio, label);
89 if (ret)
90 return ret;
e874d5b0 91
5915a2ad
SG		 92 ret = gpio_direction_input(gpio);
93 if (ret)
94 return ret;
e874d5b0
NK		 95
96 return gpio;
97}
e874d5b0
NK		 98#endif
99
750121c3 100static unsigned char mmc_board_init(struct mmc *mmc)
de941241 101{
de941241
SG		 102#if defined(CONFIG_OMAP34XX)
103 t2_t *t2_base = (t2_t *)T2_BASE;
104 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
b1e725f2 105 u32 pbias_lite;
6aca17c9
AF		 106#ifdef CONFIG_MMC_OMAP36XX_PINS
107 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
108#endif
de941241 109
b1e725f2
GI		 110 pbias_lite = readl(&t2_base->pbias_lite);
111 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
5bfdd1fc
AA		 112#ifdef CONFIG_TARGET_OMAP3_CAIRO
113 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
114 pbias_lite &= ~PBIASLITEVMODE0;
6aca17c9
AF		 115#endif
116#ifdef CONFIG_MMC_OMAP36XX_PINS
117 if (get_cpu_family() == CPU_OMAP36XX) {
118 /* Disable extended drain IO before changing PBIAS */
119 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
120 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
121 }
5bfdd1fc 122#endif
b1e725f2 123 writel(pbias_lite, &t2_base->pbias_lite);
aac5450e 124
b1e725f2 125 writel(pbias_lite | PBIASLITEPWRDNZ1 |
de941241
SG		 126 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
127 &t2_base->pbias_lite);
128
6aca17c9
AF		 129#ifdef CONFIG_MMC_OMAP36XX_PINS
130 if (get_cpu_family() == CPU_OMAP36XX)
131 /* Enable extended drain IO after changing PBIAS */
132 writel(wkup_ctrl |
133 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
134 OMAP34XX_CTRL_WKUP_CTRL);
135#endif
de941241
SG		 136 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
137 &t2_base->devconf0);
138
139 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
140 &t2_base->devconf1);
141
bbbc1ae9 142 /* Change from default of 52MHz to 26MHz if necessary */
93bfd616 143 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
bbbc1ae9
JS		 144 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
145 &t2_base->ctl_prog_io1);
146
de941241
SG		 147 writel(readl(&prcm_base->fclken1_core) |
148 EN_MMC1 | EN_MMC2 | EN_MMC3,
149 &prcm_base->fclken1_core);
150
151 writel(readl(&prcm_base->iclken1_core) |
152 EN_MMC1 | EN_MMC2 | EN_MMC3,
153 &prcm_base->iclken1_core);
154#endif
155
b4b06006 156#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
14fa2dd0 157 /* PBIAS config needed for MMC1 only */
bcce53d0 158 if (mmc->block_dev.devnum == 0)
b4b06006 159 vmmc_pbias_config(LDO_VOLT_3V0);
dd23e59d 160#endif
de941241
SG		 161
162 return 0;
163}
164
933efe64 165void mmc_init_stream(struct hsmmc *mmc_base)
de941241 166{
eb9a28f6 167 ulong start;
de941241
SG		 168
169 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
170
171 writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6
NM		 172 start = get_timer(0);
173 while (!(readl(&mmc_base->stat) & CC_MASK)) {
174 if (get_timer(0) - start > MAX_RETRY_MS) {
175 printf("%s: timedout waiting for cc!\n", __func__);
176 return;
177 }
178 }
de941241
SG		 179 writel(CC_MASK, &mmc_base->stat)
180 ;
181 writel(MMC_CMD0, &mmc_base->cmd)
182 ;
eb9a28f6
NM		 183 start = get_timer(0);
184 while (!(readl(&mmc_base->stat) & CC_MASK)) {
185 if (get_timer(0) - start > MAX_RETRY_MS) {
186 printf("%s: timedout waiting for cc2!\n", __func__);
187 return;
188 }
189 }
de941241
SG		 190 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
191}
192
ab769f22 193static int omap_hsmmc_init_setup(struct mmc *mmc)
de941241 194{
cc22b0c0 195 struct hsmmc *mmc_base;
de941241
SG		 196 unsigned int reg_val;
197 unsigned int dsor;
eb9a28f6 198 ulong start;
de941241 199
cc22b0c0 200 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
14fa2dd0 201 mmc_board_init(mmc);
de941241
SG		 202
203 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
204 &mmc_base->sysconfig);
eb9a28f6
NM		 205 start = get_timer(0);
206 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
207 if (get_timer(0) - start > MAX_RETRY_MS) {
208 printf("%s: timedout waiting for cc2!\n", __func__);
915ffa52 209 return -ETIMEDOUT;
eb9a28f6
NM		 210 }
211 }
de941241 212 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6
NM		 213 start = get_timer(0);
214 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
215 if (get_timer(0) - start > MAX_RETRY_MS) {
216 printf("%s: timedout waiting for softresetall!\n",
217 __func__);
915ffa52 218 return -ETIMEDOUT;
eb9a28f6
NM		 219 }
220 }
de941241
SG		 221 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
222 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
223 &mmc_base->capa);
224
225 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
226
227 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
228 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
229 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
230
231 dsor = 240;
232 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
233 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
234 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
235 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
eb9a28f6
NM		 236 start = get_timer(0);
237 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
238 if (get_timer(0) - start > MAX_RETRY_MS) {
239 printf("%s: timedout waiting for ics!\n", __func__);
915ffa52 240 return -ETIMEDOUT;
eb9a28f6
NM		 241 }
242 }
de941241
SG		 243 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
244
245 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
246
247 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
248 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
249 &mmc_base->ie);
250
251 mmc_init_stream(mmc_base);
252
253 return 0;
254}
255
25c719e2
GI		 256/*
257 * MMC controller internal finite state machine reset
258 *
259 * Used to reset command or data internal state machines, using respectively
260 * SRC or SRD bit of SYSCTL register
261 */
262static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
263{
264 ulong start;
265
266 mmc_reg_out(&mmc_base->sysctl, bit, bit);
267
61a6cc27
OT		 268 /*
269 * CMD(DAT) lines reset procedures are slightly different
270 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
271 * According to OMAP3 TRM:
272 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
273 * returns to 0x0.
274 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
275 * procedure steps must be as follows:
276 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
277 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
278 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
279 * 3. Wait until the SRC (SRD) bit returns to 0x0
280 * (reset procedure is completed).
281 */
282#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
dce55b93 283 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
61a6cc27
OT		 284 if (!(readl(&mmc_base->sysctl) & bit)) {
285 start = get_timer(0);
286 while (!(readl(&mmc_base->sysctl) & bit)) {
287 if (get_timer(0) - start > MAX_RETRY_MS)
288 return;
289 }
290 }
291#endif
25c719e2
GI		 292 start = get_timer(0);
293 while ((readl(&mmc_base->sysctl) & bit) != 0) {
294 if (get_timer(0) - start > MAX_RETRY_MS) {
295 printf("%s: timedout waiting for sysctl %x to clear\n",
296 __func__, bit);
297 return;
298 }
299 }
300}
de941241 301
ab769f22 302static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
de941241
SG		 303 struct mmc_data *data)
304{
cc22b0c0 305 struct hsmmc *mmc_base;
de941241 306 unsigned int flags, mmc_stat;
eb9a28f6 307 ulong start;
de941241 308
cc22b0c0 309 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
eb9a28f6 310 start = get_timer(0);
a7778f8f 311 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
eb9a28f6 312 if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f
TR		 313 printf("%s: timedout waiting on cmd inhibit to clear\n",
314 __func__);
915ffa52 315 return -ETIMEDOUT;
eb9a28f6
NM		 316 }
317 }
de941241 318 writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6
NM		 319 start = get_timer(0);
320 while (readl(&mmc_base->stat)) {
321 if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de
GI		 322 printf("%s: timedout waiting for STAT (%x) to clear\n",
323 __func__, readl(&mmc_base->stat));
915ffa52 324 return -ETIMEDOUT;
eb9a28f6
NM		 325 }
326 }
de941241
SG		 327 /*
328 * CMDREG
329 * CMDIDX[13:8] : Command index
330 * DATAPRNT[5] : Data Present Select
331 * ENCMDIDX[4] : Command Index Check Enable
332 * ENCMDCRC[3] : Command CRC Check Enable
333 * RSPTYP[1:0]
334 * 00 = No Response
335 * 01 = Length 136
336 * 10 = Length 48
337 * 11 = Length 48 Check busy after response
338 */
339 /* Delay added before checking the status of frq change
340 * retry not supported by mmc.c(core file)
341 */
342 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
343 udelay(50000); /* wait 50 ms */
344
345 if (!(cmd->resp_type & MMC_RSP_PRESENT))
346 flags = 0;
347 else if (cmd->resp_type & MMC_RSP_136)
348 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
349 else if (cmd->resp_type & MMC_RSP_BUSY)
350 flags = RSP_TYPE_LGHT48B;
351 else
352 flags = RSP_TYPE_LGHT48;
353
354 /* enable default flags */
355 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
356 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
357
358 if (cmd->resp_type & MMC_RSP_CRC)
359 flags |= CCCE_CHECK;
360 if (cmd->resp_type & MMC_RSP_OPCODE)
361 flags |= CICE_CHECK;
362
363 if (data) {
364 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
365 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
366 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
367 data->blocksize = 512;
368 writel(data->blocksize | (data->blocks << 16),
369 &mmc_base->blk);
370 } else
371 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
372
373 if (data->flags & MMC_DATA_READ)
374 flags |= (DP_DATA | DDIR_READ);
375 else
376 flags |= (DP_DATA | DDIR_WRITE);
377 }
378
379 writel(cmd->cmdarg, &mmc_base->arg);
152ba363 380 udelay(20); /* To fix "No status update" error on eMMC */
de941241
SG		 381 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
382
eb9a28f6 383 start = get_timer(0);
de941241
SG		 384 do {
385 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 386 if (get_timer(0) - start > MAX_RETRY_MS) {
387 printf("%s : timeout: No status update\n", __func__);
915ffa52 388 return -ETIMEDOUT;
eb9a28f6
NM		 389 }
390 } while (!mmc_stat);
de941241 391
25c719e2
GI		 392 if ((mmc_stat & IE_CTO) != 0) {
393 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
915ffa52 394 return -ETIMEDOUT;
25c719e2 395 } else if ((mmc_stat & ERRI_MASK) != 0)
de941241
SG		 396 return -1;
397
398 if (mmc_stat & CC_MASK) {
399 writel(CC_MASK, &mmc_base->stat);
400 if (cmd->resp_type & MMC_RSP_PRESENT) {
401 if (cmd->resp_type & MMC_RSP_136) {
402 /* response type 2 */
403 cmd->response[3] = readl(&mmc_base->rsp10);
404 cmd->response[2] = readl(&mmc_base->rsp32);
405 cmd->response[1] = readl(&mmc_base->rsp54);
406 cmd->response[0] = readl(&mmc_base->rsp76);
407 } else
408 /* response types 1, 1b, 3, 4, 5, 6 */
409 cmd->response[0] = readl(&mmc_base->rsp10);
410 }
411 }
412
413 if (data && (data->flags & MMC_DATA_READ)) {
414 mmc_read_data(mmc_base, data->dest,
415 data->blocksize * data->blocks);
416 } else if (data && (data->flags & MMC_DATA_WRITE)) {
417 mmc_write_data(mmc_base, data->src,
418 data->blocksize * data->blocks);
419 }
420 return 0;
421}
422
933efe64 423static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
de941241
SG		 424{
425 unsigned int *output_buf = (unsigned int *)buf;
426 unsigned int mmc_stat;
427 unsigned int count;
428
429 /*
430 * Start Polled Read
431 */
432 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
433 count /= 4;
434
435 while (size) {
eb9a28f6 436 ulong start = get_timer(0);
de941241
SG		 437 do {
438 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 439 if (get_timer(0) - start > MAX_RETRY_MS) {
440 printf("%s: timedout waiting for status!\n",
441 __func__);
915ffa52 442 return -ETIMEDOUT;
eb9a28f6 443 }
de941241
SG		 444 } while (mmc_stat == 0);
445
25c719e2
GI		 446 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
447 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
448
de941241
SG		 449 if ((mmc_stat & ERRI_MASK) != 0)
450 return 1;
451
452 if (mmc_stat & BRR_MASK) {
453 unsigned int k;
454
455 writel(readl(&mmc_base->stat) | BRR_MASK,
456 &mmc_base->stat);
457 for (k = 0; k < count; k++) {
458 *output_buf = readl(&mmc_base->data);
459 output_buf++;
460 }
461 size -= (count*4);
462 }
463
464 if (mmc_stat & BWR_MASK)
465 writel(readl(&mmc_base->stat) | BWR_MASK,
466 &mmc_base->stat);
467
468 if (mmc_stat & TC_MASK) {
469 writel(readl(&mmc_base->stat) | TC_MASK,
470 &mmc_base->stat);
471 break;
472 }
473 }
474 return 0;
475}
476
933efe64
S		 477static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
478 unsigned int size)
de941241
SG		 479{
480 unsigned int *input_buf = (unsigned int *)buf;
481 unsigned int mmc_stat;
482 unsigned int count;
483
484 /*
152ba363 485 * Start Polled Write
de941241
SG		 486 */
487 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
488 count /= 4;
489
490 while (size) {
eb9a28f6 491 ulong start = get_timer(0);
de941241
SG		 492 do {
493 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 494 if (get_timer(0) - start > MAX_RETRY_MS) {
495 printf("%s: timedout waiting for status!\n",
496 __func__);
915ffa52 497 return -ETIMEDOUT;
eb9a28f6 498 }
de941241
SG		 499 } while (mmc_stat == 0);
500
25c719e2
GI		 501 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
502 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
503
de941241
SG		 504 if ((mmc_stat & ERRI_MASK) != 0)
505 return 1;
506
507 if (mmc_stat & BWR_MASK) {
508 unsigned int k;
509
510 writel(readl(&mmc_base->stat) | BWR_MASK,
511 &mmc_base->stat);
512 for (k = 0; k < count; k++) {
513 writel(*input_buf, &mmc_base->data);
514 input_buf++;
515 }
516 size -= (count*4);
517 }
518
519 if (mmc_stat & BRR_MASK)
520 writel(readl(&mmc_base->stat) | BRR_MASK,
521 &mmc_base->stat);
522
523 if (mmc_stat & TC_MASK) {
524 writel(readl(&mmc_base->stat) | TC_MASK,
525 &mmc_base->stat);
526 break;
527 }
528 }
529 return 0;
530}
531
07b0b9c0 532static int omap_hsmmc_set_ios(struct mmc *mmc)
de941241 533{
cc22b0c0 534 struct hsmmc *mmc_base;
de941241 535 unsigned int dsor = 0;
eb9a28f6 536 ulong start;
de941241 537
cc22b0c0 538 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
de941241
SG		 539 /* configue bus width */
540 switch (mmc->bus_width) {
541 case 8:
542 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
543 &mmc_base->con);
544 break;
545
546 case 4:
547 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
548 &mmc_base->con);
549 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
550 &mmc_base->hctl);
551 break;
552
553 case 1:
554 default:
555 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
556 &mmc_base->con);
557 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
558 &mmc_base->hctl);
559 break;
560 }
561
562 /* configure clock with 96Mhz system clock.
563 */
564 if (mmc->clock != 0) {
565 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
566 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
567 dsor++;
568 }
569
570 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
571 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
572
573 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
574 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
575
eb9a28f6
NM		 576 start = get_timer(0);
577 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
578 if (get_timer(0) - start > MAX_RETRY_MS) {
579 printf("%s: timedout waiting for ics!\n", __func__);
07b0b9c0 580 return -ETIMEDOUT;
eb9a28f6
NM		 581 }
582 }
de941241 583 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
07b0b9c0
JC		 584
585 return 0;
de941241
SG		 586}
587
ab769f22 588#ifdef OMAP_HSMMC_USE_GPIO
a9d6a7e2
M		 589#ifdef CONFIG_DM_MMC
590static int omap_hsmmc_getcd(struct mmc *mmc)
591{
592 struct omap_hsmmc_data *priv = mmc->priv;
593 int value;
594
595 value = dm_gpio_get_value(&priv->cd_gpio);
596 /* if no CD return as 1 */
597 if (value < 0)
598 return 1;
599
600 if (priv->cd_inverted)
601 return !value;
602 return value;
603}
604
605static int omap_hsmmc_getwp(struct mmc *mmc)
606{
607 struct omap_hsmmc_data *priv = mmc->priv;
608 int value;
609
610 value = dm_gpio_get_value(&priv->wp_gpio);
611 /* if no WP return as 0 */
612 if (value < 0)
613 return 0;
614 return value;
615}
616#else
ab769f22
PA		 617static int omap_hsmmc_getcd(struct mmc *mmc)
618{
619 struct omap_hsmmc_data *priv_data = mmc->priv;
620 int cd_gpio;
621
622 /* if no CD return as 1 */
623 cd_gpio = priv_data->cd_gpio;
624 if (cd_gpio < 0)
625 return 1;
626
0b03a931
IG		 627 /* NOTE: assumes card detect signal is active-low */
628 return !gpio_get_value(cd_gpio);
ab769f22
PA		 629}
630
631static int omap_hsmmc_getwp(struct mmc *mmc)
632{
633 struct omap_hsmmc_data *priv_data = mmc->priv;
634 int wp_gpio;
635
636 /* if no WP return as 0 */
637 wp_gpio = priv_data->wp_gpio;
638 if (wp_gpio < 0)
639 return 0;
640
0b03a931 641 /* NOTE: assumes write protect signal is active-high */
ab769f22
PA		 642 return gpio_get_value(wp_gpio);
643}
644#endif
a9d6a7e2 645#endif
ab769f22
PA		 646
647static const struct mmc_ops omap_hsmmc_ops = {
648 .send_cmd = omap_hsmmc_send_cmd,
649 .set_ios = omap_hsmmc_set_ios,
650 .init = omap_hsmmc_init_setup,
651#ifdef OMAP_HSMMC_USE_GPIO
652 .getcd = omap_hsmmc_getcd,
653 .getwp = omap_hsmmc_getwp,
654#endif
655};
656
a9d6a7e2 657#ifndef CONFIG_DM_MMC
e3913f56
NK		 658int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
659 int wp_gpio)
de941241 660{
93bfd616
PA		 661 struct mmc *mmc;
662 struct omap_hsmmc_data *priv_data;
663 struct mmc_config *cfg;
664 uint host_caps_val;
665
666 priv_data = malloc(sizeof(*priv_data));
667 if (priv_data == NULL)
668 return -1;
de941241 669
5a20397b 670 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
de941241
SG		 671
672 switch (dev_index) {
673 case 0:
cc22b0c0 674 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 675 break;
1037d585 676#ifdef OMAP_HSMMC2_BASE
de941241 677 case 1:
cc22b0c0 678 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
152ba363 679#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
3891a54f 680 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
3b68939f
RQ		 681 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
682 defined(CONFIG_HSMMC2_8BIT)
152ba363
LP		 683 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
684 host_caps_val |= MMC_MODE_8BIT;
685#endif
de941241 686 break;
1037d585
TR		 687#endif
688#ifdef OMAP_HSMMC3_BASE
de941241 689 case 2:
cc22b0c0 690 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
3891a54f 691#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
152ba363
LP		 692 /* Enable 8-bit interface for eMMC on DRA7XX */
693 host_caps_val |= MMC_MODE_8BIT;
694#endif
de941241 695 break;
1037d585 696#endif
de941241 697 default:
cc22b0c0 698 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241
SG		 699 return 1;
700 }
ab769f22
PA		 701#ifdef OMAP_HSMMC_USE_GPIO
702 /* on error gpio values are set to -1, which is what we want */
e874d5b0 703 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
e3913f56 704 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
ab769f22 705#endif
173ddc5b 706
93bfd616 707 cfg = &priv_data->cfg;
de941241 708
93bfd616
PA		 709 cfg->name = "OMAP SD/MMC";
710 cfg->ops = &omap_hsmmc_ops;
711
712 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
713 cfg->host_caps = host_caps_val & ~host_caps_mask;
714
715 cfg->f_min = 400000;
bbbc1ae9
JS		 716
717 if (f_max != 0)
93bfd616 718 cfg->f_max = f_max;
bbbc1ae9 719 else {
93bfd616
PA		 720 if (cfg->host_caps & MMC_MODE_HS) {
721 if (cfg->host_caps & MMC_MODE_HS_52MHz)
722 cfg->f_max = 52000000;
bbbc1ae9 723 else
93bfd616 724 cfg->f_max = 26000000;
bbbc1ae9 725 } else
93bfd616 726 cfg->f_max = 20000000;
bbbc1ae9 727 }
de941241 728
93bfd616 729 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
8feafcc4 730
4ca9244d
JR		 731#if defined(CONFIG_OMAP34XX)
732 /*
733 * Silicon revs 2.1 and older do not support multiblock transfers.
734 */
735 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
93bfd616 736 cfg->b_max = 1;
4ca9244d 737#endif
93bfd616
PA		 738 mmc = mmc_create(cfg, priv_data);
739 if (mmc == NULL)
740 return -1;
de941241
SG		 741
742 return 0;
743}
a9d6a7e2
M		 744#else
745static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
746{
747 struct omap_hsmmc_data *priv = dev_get_priv(dev);
748 const void *fdt = gd->fdt_blob;
e160f7d4 749 int node = dev_of_offset(dev);
a9d6a7e2
M		 750 struct mmc_config *cfg;
751 int val;
752
4bc5e19e
M		 753 priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
754 MAP_NOCACHE);
a9d6a7e2
M		 755 cfg = &priv->cfg;
756
757 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
758 val = fdtdec_get_int(fdt, node, "bus-width", -1);
759 if (val < 0) {
760 printf("error: bus-width property missing\n");
761 return -ENOENT;
762 }
763
764 switch (val) {
765 case 0x8:
766 cfg->host_caps |= MMC_MODE_8BIT;
767 case 0x4:
768 cfg->host_caps |= MMC_MODE_4BIT;
769 break;
770 default:
771 printf("error: invalid bus-width property\n");
772 return -ENOENT;
773 }
774
775 cfg->f_min = 400000;
776 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
777 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
778 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
779
4de2de51 780#ifdef OMAP_HSMMC_USE_GPIO
a9d6a7e2 781 priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
4de2de51 782#endif
a9d6a7e2
M		 783
784 return 0;
785}
786
787static int omap_hsmmc_probe(struct udevice *dev)
788{
789 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
790 struct omap_hsmmc_data *priv = dev_get_priv(dev);
791 struct mmc_config *cfg;
792 struct mmc *mmc;
793
794 cfg = &priv->cfg;
795 cfg->name = "OMAP SD/MMC";
796 cfg->ops = &omap_hsmmc_ops;
797
798 mmc = mmc_create(cfg, priv);
799 if (mmc == NULL)
800 return -1;
801
5cc6a245
M		 802#ifdef OMAP_HSMMC_USE_GPIO
803 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
804 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
805#endif
806
cffe5d86 807 mmc->dev = dev;
a9d6a7e2
M		 808 upriv->mmc = mmc;
809
810 return 0;
811}
812
813static const struct udevice_id omap_hsmmc_ids[] = {
814 { .compatible = "ti,omap3-hsmmc" },
815 { .compatible = "ti,omap4-hsmmc" },
816 { .compatible = "ti,am33xx-hsmmc" },
817 { }
818};
819
820U_BOOT_DRIVER(omap_hsmmc) = {
821 .name = "omap_hsmmc",
822 .id = UCLASS_MMC,
823 .of_match = omap_hsmmc_ids,
824 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
825 .probe = omap_hsmmc_probe,
826 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
827};
828#endif
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