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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <malloc.h> | |
26 | #include <net.h> | |
27 | #include <miiphy.h> | |
28 | #include "fec_mxc.h" | |
29 | ||
30 | #include <asm/arch/clock.h> | |
31 | #include <asm/arch/imx-regs.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/errno.h> | |
34 | ||
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
37 | #ifndef CONFIG_MII | |
38 | #error "CONFIG_MII has to be defined!" | |
39 | #endif | |
40 | ||
392b8502 MV |
41 | #ifndef CONFIG_FEC_XCV_TYPE |
42 | #define CONFIG_FEC_XCV_TYPE MII100 | |
43 | #endif | |
44 | ||
be7e87e2 MV |
45 | /* |
46 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
47 | * sending and after receiving. | |
48 | */ | |
49 | #ifdef CONFIG_MX28 | |
50 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
51 | #endif | |
52 | ||
0b23fb36 IY |
53 | #undef DEBUG |
54 | ||
55 | struct nbuf { | |
56 | uint8_t data[1500]; /**< actual data */ | |
57 | int length; /**< actual length */ | |
58 | int used; /**< buffer in use or not */ | |
59 | uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ | |
60 | }; | |
61 | ||
be7e87e2 MV |
62 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
63 | static void swap_packet(uint32_t *packet, int length) | |
64 | { | |
65 | int i; | |
66 | ||
67 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
68 | packet[i] = __swab32(packet[i]); | |
69 | } | |
70 | #endif | |
71 | ||
72 | /* | |
73 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
74 | * Only the first one can access the MDIO bus. | |
75 | */ | |
76 | #ifdef CONFIG_MX28 | |
77 | static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) | |
78 | { | |
79 | return (struct ethernet_regs *)MXS_ENET0_BASE; | |
80 | } | |
81 | #else | |
82 | static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) | |
83 | { | |
84 | return fec->eth; | |
85 | } | |
86 | #endif | |
87 | ||
0b23fb36 IY |
88 | /* |
89 | * MII-interface related functions | |
90 | */ | |
5700bb63 | 91 | static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, |
0b23fb36 IY |
92 | uint16_t *retVal) |
93 | { | |
94 | struct eth_device *edev = eth_get_dev_by_name(dev); | |
95 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
be7e87e2 | 96 | struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); |
0b23fb36 IY |
97 | |
98 | uint32_t reg; /* convenient holder for the PHY register */ | |
99 | uint32_t phy; /* convenient holder for the PHY */ | |
100 | uint32_t start; | |
101 | ||
102 | /* | |
103 | * reading from any PHY's register is done by properly | |
104 | * programming the FEC's MII data register. | |
105 | */ | |
d133b881 | 106 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
107 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
108 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
109 | ||
110 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 111 | phy | reg, ð->mii_data); |
0b23fb36 IY |
112 | |
113 | /* | |
114 | * wait for the related interrupt | |
115 | */ | |
a60d1e5b | 116 | start = get_timer(0); |
d133b881 | 117 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
118 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
119 | printf("Read MDIO failed...\n"); | |
120 | return -1; | |
121 | } | |
122 | } | |
123 | ||
124 | /* | |
125 | * clear mii interrupt bit | |
126 | */ | |
d133b881 | 127 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
128 | |
129 | /* | |
130 | * it's now safe to read the PHY's register | |
131 | */ | |
d133b881 | 132 | *retVal = readl(ð->mii_data); |
0b23fb36 IY |
133 | debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, |
134 | regAddr, *retVal); | |
135 | return 0; | |
136 | } | |
137 | ||
4294b248 SB |
138 | static void fec_mii_setspeed(struct fec_priv *fec) |
139 | { | |
140 | /* | |
141 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
142 | * and do not drop the Preamble. | |
143 | */ | |
144 | writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, | |
145 | &fec->eth->mii_speed); | |
eda959f3 | 146 | debug("fec_init: mii_speed %08x\n", |
879cf261 | 147 | readl(&fec->eth->mii_speed)); |
4294b248 | 148 | } |
5700bb63 | 149 | static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, |
0b23fb36 IY |
150 | uint16_t data) |
151 | { | |
152 | struct eth_device *edev = eth_get_dev_by_name(dev); | |
153 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
be7e87e2 | 154 | struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); |
0b23fb36 IY |
155 | |
156 | uint32_t reg; /* convenient holder for the PHY register */ | |
157 | uint32_t phy; /* convenient holder for the PHY */ | |
158 | uint32_t start; | |
159 | ||
160 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
161 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
162 | ||
163 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 164 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
165 | |
166 | /* | |
167 | * wait for the MII interrupt | |
168 | */ | |
a60d1e5b | 169 | start = get_timer(0); |
d133b881 | 170 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
171 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
172 | printf("Write MDIO failed...\n"); | |
173 | return -1; | |
174 | } | |
175 | } | |
176 | ||
177 | /* | |
178 | * clear MII interrupt bit | |
179 | */ | |
d133b881 | 180 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
181 | debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, |
182 | regAddr, data); | |
183 | ||
184 | return 0; | |
185 | } | |
186 | ||
187 | static int miiphy_restart_aneg(struct eth_device *dev) | |
188 | { | |
9e27e9dc | 189 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
2e5f4421 | 190 | int ret = 0; |
9e27e9dc | 191 | |
0b23fb36 IY |
192 | /* |
193 | * Wake up from sleep if necessary | |
194 | * Reset PHY, then delay 300ns | |
195 | */ | |
cb17b92d | 196 | #ifdef CONFIG_MX27 |
9e27e9dc | 197 | miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 198 | #endif |
9e27e9dc | 199 | miiphy_write(dev->name, fec->phy_id, MII_BMCR, |
8ef583a0 | 200 | BMCR_RESET); |
0b23fb36 IY |
201 | udelay(1000); |
202 | ||
203 | /* | |
204 | * Set the auto-negotiation advertisement register bits | |
205 | */ | |
9e27e9dc | 206 | miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
207 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
208 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
9e27e9dc | 209 | miiphy_write(dev->name, fec->phy_id, MII_BMCR, |
8ef583a0 | 210 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
211 | |
212 | if (fec->mii_postcall) | |
213 | ret = fec->mii_postcall(fec->phy_id); | |
214 | ||
215 | return ret; | |
0b23fb36 IY |
216 | } |
217 | ||
218 | static int miiphy_wait_aneg(struct eth_device *dev) | |
219 | { | |
220 | uint32_t start; | |
221 | uint16_t status; | |
9e27e9dc | 222 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
223 | |
224 | /* | |
225 | * Wait for AN completion | |
226 | */ | |
a60d1e5b | 227 | start = get_timer(0); |
0b23fb36 IY |
228 | do { |
229 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
230 | printf("%s: Autonegotiation timeout\n", dev->name); | |
231 | return -1; | |
232 | } | |
233 | ||
9e27e9dc | 234 | if (miiphy_read(dev->name, fec->phy_id, |
8ef583a0 | 235 | MII_BMSR, &status)) { |
0b23fb36 IY |
236 | printf("%s: Autonegotiation failed. status: 0x%04x\n", |
237 | dev->name, status); | |
238 | return -1; | |
239 | } | |
8ef583a0 | 240 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
241 | |
242 | return 0; | |
243 | } | |
244 | static int fec_rx_task_enable(struct fec_priv *fec) | |
245 | { | |
246 | writel(1 << 24, &fec->eth->r_des_active); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static int fec_rx_task_disable(struct fec_priv *fec) | |
251 | { | |
252 | return 0; | |
253 | } | |
254 | ||
255 | static int fec_tx_task_enable(struct fec_priv *fec) | |
256 | { | |
257 | writel(1 << 24, &fec->eth->x_des_active); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | static int fec_tx_task_disable(struct fec_priv *fec) | |
262 | { | |
263 | return 0; | |
264 | } | |
265 | ||
266 | /** | |
267 | * Initialize receive task's buffer descriptors | |
268 | * @param[in] fec all we know about the device yet | |
269 | * @param[in] count receive buffer count to be allocated | |
270 | * @param[in] size size of each receive buffer | |
271 | * @return 0 on success | |
272 | * | |
273 | * For this task we need additional memory for the data buffers. And each | |
274 | * data buffer requires some alignment. Thy must be aligned to a specific | |
275 | * boundary each (DB_DATA_ALIGNMENT). | |
276 | */ | |
277 | static int fec_rbd_init(struct fec_priv *fec, int count, int size) | |
278 | { | |
279 | int ix; | |
280 | uint32_t p = 0; | |
281 | ||
282 | /* reserve data memory and consider alignment */ | |
651ef90f M |
283 | if (fec->rdb_ptr == NULL) |
284 | fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); | |
0b23fb36 IY |
285 | p = (uint32_t)fec->rdb_ptr; |
286 | if (!p) { | |
4294b248 | 287 | puts("fec_mxc: not enough malloc memory\n"); |
0b23fb36 IY |
288 | return -ENOMEM; |
289 | } | |
290 | memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); | |
291 | p += DB_DATA_ALIGNMENT-1; | |
292 | p &= ~(DB_DATA_ALIGNMENT-1); | |
293 | ||
294 | for (ix = 0; ix < count; ix++) { | |
295 | writel(p, &fec->rbd_base[ix].data_pointer); | |
296 | p += size; | |
297 | writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); | |
298 | writew(0, &fec->rbd_base[ix].data_length); | |
299 | } | |
300 | /* | |
301 | * mark the last RBD to close the ring | |
302 | */ | |
303 | writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); | |
304 | fec->rbd_index = 0; | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | /** | |
310 | * Initialize transmit task's buffer descriptors | |
311 | * @param[in] fec all we know about the device yet | |
312 | * | |
313 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
314 | * Note: There is a race condition in the hardware. When only one BD is in | |
315 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
316 | * This bit in combination with the READY bit results into double transmit | |
317 | * of each data buffer. It seems the state machine checks READY earlier then | |
318 | * resetting it after the first transfer. | |
319 | * Using two BDs solves this issue. | |
320 | */ | |
321 | static void fec_tbd_init(struct fec_priv *fec) | |
322 | { | |
323 | writew(0x0000, &fec->tbd_base[0].status); | |
324 | writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); | |
325 | fec->tbd_index = 0; | |
326 | } | |
327 | ||
328 | /** | |
329 | * Mark the given read buffer descriptor as free | |
330 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
331 | * @param[in] pRbd buffer descriptor to mark free again | |
332 | */ | |
333 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
334 | { | |
335 | /* | |
336 | * Reset buffer descriptor as empty | |
337 | */ | |
338 | if (last) | |
339 | writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); | |
340 | else | |
341 | writew(FEC_RBD_EMPTY, &pRbd->status); | |
342 | /* | |
343 | * no data in it | |
344 | */ | |
345 | writew(0, &pRbd->data_length); | |
346 | } | |
347 | ||
be252b65 FE |
348 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
349 | unsigned char *mac) | |
0b23fb36 | 350 | { |
be252b65 | 351 | imx_get_mac_from_fuse(dev_id, mac); |
2e236bf2 | 352 | return !is_valid_ether_addr(mac); |
0b23fb36 IY |
353 | } |
354 | ||
4294b248 | 355 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 356 | { |
4294b248 | 357 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
358 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
359 | ||
360 | writel(0, &fec->eth->iaddr1); | |
361 | writel(0, &fec->eth->iaddr2); | |
362 | writel(0, &fec->eth->gaddr1); | |
363 | writel(0, &fec->eth->gaddr2); | |
364 | ||
365 | /* | |
366 | * Set physical address | |
367 | */ | |
368 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
369 | &fec->eth->paddr1); | |
370 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | /** | |
376 | * Start the FEC engine | |
377 | * @param[in] dev Our device to handle | |
378 | */ | |
379 | static int fec_open(struct eth_device *edev) | |
380 | { | |
381 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
382 | ||
383 | debug("fec_open: fec_open(dev)\n"); | |
384 | /* full-duplex, heartbeat disabled */ | |
385 | writel(1 << 2, &fec->eth->x_cntrl); | |
386 | fec->rbd_index = 0; | |
387 | ||
2ef2b950 JL |
388 | #if defined(CONFIG_MX6Q) |
389 | /* Enable ENET HW endian SWAP */ | |
390 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
391 | &fec->eth->ecntrl); | |
392 | /* Enable ENET store and forward mode */ | |
393 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
394 | &fec->eth->x_wmrk); | |
395 | #endif | |
0b23fb36 IY |
396 | /* |
397 | * Enable FEC-Lite controller | |
398 | */ | |
cb17b92d JR |
399 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
400 | &fec->eth->ecntrl); | |
96912453 | 401 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) |
740d6ae5 JR |
402 | udelay(100); |
403 | /* | |
404 | * setup the MII gasket for RMII mode | |
405 | */ | |
406 | ||
407 | /* disable the gasket */ | |
408 | writew(0, &fec->eth->miigsk_enr); | |
409 | ||
410 | /* wait for the gasket to be disabled */ | |
411 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
412 | udelay(2); | |
413 | ||
414 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
415 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
416 | ||
417 | /* re-enable the gasket */ | |
418 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
419 | ||
420 | /* wait until MII gasket is ready */ | |
421 | int max_loops = 10; | |
422 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
423 | if (--max_loops <= 0) { | |
424 | printf("WAIT for MII Gasket ready timed out\n"); | |
425 | break; | |
426 | } | |
427 | } | |
428 | #endif | |
0b23fb36 IY |
429 | |
430 | miiphy_wait_aneg(edev); | |
9e27e9dc MV |
431 | miiphy_speed(edev->name, fec->phy_id); |
432 | miiphy_duplex(edev->name, fec->phy_id); | |
0b23fb36 IY |
433 | |
434 | /* | |
435 | * Enable SmartDMA receive task | |
436 | */ | |
437 | fec_rx_task_enable(fec); | |
438 | ||
439 | udelay(100000); | |
440 | return 0; | |
441 | } | |
442 | ||
443 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
444 | { | |
445 | uint32_t base; | |
446 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
9e27e9dc | 447 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
9eb3770b | 448 | uint32_t rcntrl; |
9e27e9dc | 449 | int i; |
0b23fb36 | 450 | |
e9319f11 JR |
451 | /* Initialize MAC address */ |
452 | fec_set_hwaddr(dev); | |
453 | ||
0b23fb36 IY |
454 | /* |
455 | * reserve memory for both buffer descriptor chains at once | |
456 | * Datasheet forces the startaddress of each chain is 16 byte | |
457 | * aligned | |
458 | */ | |
651ef90f M |
459 | if (fec->base_ptr == NULL) |
460 | fec->base_ptr = malloc((2 + FEC_RBD_NUM) * | |
461 | sizeof(struct fec_bd) + DB_ALIGNMENT); | |
0b23fb36 IY |
462 | base = (uint32_t)fec->base_ptr; |
463 | if (!base) { | |
4294b248 | 464 | puts("fec_mxc: not enough malloc memory\n"); |
0b23fb36 IY |
465 | return -ENOMEM; |
466 | } | |
467 | memset((void *)base, 0, (2 + FEC_RBD_NUM) * | |
468 | sizeof(struct fec_bd) + DB_ALIGNMENT); | |
469 | base += (DB_ALIGNMENT-1); | |
470 | base &= ~(DB_ALIGNMENT-1); | |
471 | ||
472 | fec->rbd_base = (struct fec_bd *)base; | |
473 | ||
474 | base += FEC_RBD_NUM * sizeof(struct fec_bd); | |
475 | ||
476 | fec->tbd_base = (struct fec_bd *)base; | |
477 | ||
478 | /* | |
479 | * Set interrupt mask register | |
480 | */ | |
481 | writel(0x00000000, &fec->eth->imask); | |
482 | ||
483 | /* | |
484 | * Clear FEC-Lite interrupt event register(IEVENT) | |
485 | */ | |
486 | writel(0xffffffff, &fec->eth->ievent); | |
487 | ||
488 | ||
489 | /* | |
490 | * Set FEC-Lite receive control register(R_CNTRL): | |
491 | */ | |
4294b248 | 492 | |
9eb3770b MV |
493 | /* Start with frame length = 1518, common for all modes. */ |
494 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
495 | if (fec->xcv_type == SEVENWIRE) | |
496 | rcntrl |= FEC_RCNTRL_FCE; | |
2ef2b950 JL |
497 | else if (fec->xcv_type == RGMII) |
498 | rcntrl |= FEC_RCNTRL_RGMII; | |
a50a90c9 MV |
499 | else if (fec->xcv_type == RMII) |
500 | rcntrl |= FEC_RCNTRL_RMII; | |
9eb3770b MV |
501 | else /* MII mode */ |
502 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
503 | ||
504 | writel(rcntrl, &fec->eth->r_cntrl); | |
505 | ||
506 | if (fec->xcv_type == MII10 || fec->xcv_type == MII100) | |
4294b248 | 507 | fec_mii_setspeed(fec); |
9eb3770b | 508 | |
0b23fb36 IY |
509 | /* |
510 | * Set Opcode/Pause Duration Register | |
511 | */ | |
512 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
513 | writel(0x2, &fec->eth->x_wmrk); | |
514 | /* | |
515 | * Set multicast address filter | |
516 | */ | |
517 | writel(0x00000000, &fec->eth->gaddr1); | |
518 | writel(0x00000000, &fec->eth->gaddr2); | |
519 | ||
520 | ||
521 | /* clear MIB RAM */ | |
9e27e9dc MV |
522 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) |
523 | writel(0, i); | |
0b23fb36 IY |
524 | |
525 | /* FIFO receive start register */ | |
526 | writel(0x520, &fec->eth->r_fstart); | |
527 | ||
528 | /* size and address of each buffer */ | |
529 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
530 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
531 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
532 | ||
533 | /* | |
534 | * Initialize RxBD/TxBD rings | |
535 | */ | |
536 | if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { | |
537 | free(fec->base_ptr); | |
c179a289 | 538 | fec->base_ptr = NULL; |
0b23fb36 IY |
539 | return -ENOMEM; |
540 | } | |
541 | fec_tbd_init(fec); | |
542 | ||
543 | ||
544 | if (fec->xcv_type != SEVENWIRE) | |
545 | miiphy_restart_aneg(dev); | |
546 | ||
547 | fec_open(dev); | |
548 | return 0; | |
549 | } | |
550 | ||
551 | /** | |
552 | * Halt the FEC engine | |
553 | * @param[in] dev Our device to handle | |
554 | */ | |
555 | static void fec_halt(struct eth_device *dev) | |
556 | { | |
9e27e9dc | 557 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
558 | int counter = 0xffff; |
559 | ||
560 | /* | |
561 | * issue graceful stop command to the FEC transmitter if necessary | |
562 | */ | |
cb17b92d | 563 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
564 | &fec->eth->x_cntrl); |
565 | ||
566 | debug("eth_halt: wait for stop regs\n"); | |
567 | /* | |
568 | * wait for graceful stop to register | |
569 | */ | |
570 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 571 | udelay(1); |
0b23fb36 IY |
572 | |
573 | /* | |
574 | * Disable SmartDMA tasks | |
575 | */ | |
576 | fec_tx_task_disable(fec); | |
577 | fec_rx_task_disable(fec); | |
578 | ||
579 | /* | |
580 | * Disable the Ethernet Controller | |
581 | * Note: this will also reset the BD index counter! | |
582 | */ | |
740d6ae5 JR |
583 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
584 | &fec->eth->ecntrl); | |
0b23fb36 IY |
585 | fec->rbd_index = 0; |
586 | fec->tbd_index = 0; | |
0b23fb36 IY |
587 | debug("eth_halt: done\n"); |
588 | } | |
589 | ||
590 | /** | |
591 | * Transmit one frame | |
592 | * @param[in] dev Our ethernet device to handle | |
593 | * @param[in] packet Pointer to the data to be transmitted | |
594 | * @param[in] length Data count in bytes | |
595 | * @return 0 on success | |
596 | */ | |
597 | static int fec_send(struct eth_device *dev, volatile void* packet, int length) | |
598 | { | |
599 | unsigned int status; | |
600 | ||
601 | /* | |
602 | * This routine transmits one frame. This routine only accepts | |
603 | * 6-byte Ethernet addresses. | |
604 | */ | |
605 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
606 | ||
607 | /* | |
608 | * Check for valid length of data. | |
609 | */ | |
610 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 611 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
612 | return -1; |
613 | } | |
614 | ||
615 | /* | |
616 | * Setup the transmit buffer | |
617 | * Note: We are always using the first buffer for transmission, | |
618 | * the second will be empty and only used to stop the DMA engine | |
619 | */ | |
be7e87e2 MV |
620 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
621 | swap_packet((uint32_t *)packet, length); | |
622 | #endif | |
0b23fb36 IY |
623 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
624 | writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); | |
625 | /* | |
626 | * update BD's status now | |
627 | * This block: | |
628 | * - is always the last in a chain (means no chain) | |
629 | * - should transmitt the CRC | |
630 | * - might be the last BD in the list, so the address counter should | |
631 | * wrap (-> keep the WRAP flag) | |
632 | */ | |
633 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
634 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
635 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
636 | ||
637 | /* | |
638 | * Enable SmartDMA transmit task | |
639 | */ | |
640 | fec_tx_task_enable(fec); | |
641 | ||
642 | /* | |
643 | * wait until frame is sent . | |
644 | */ | |
645 | while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { | |
cb17b92d | 646 | udelay(1); |
0b23fb36 IY |
647 | } |
648 | debug("fec_send: status 0x%x index %d\n", | |
649 | readw(&fec->tbd_base[fec->tbd_index].status), | |
650 | fec->tbd_index); | |
651 | /* for next transmission use the other buffer */ | |
652 | if (fec->tbd_index) | |
653 | fec->tbd_index = 0; | |
654 | else | |
655 | fec->tbd_index = 1; | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | /** | |
661 | * Pull one frame from the card | |
662 | * @param[in] dev Our ethernet device to handle | |
663 | * @return Length of packet read | |
664 | */ | |
665 | static int fec_recv(struct eth_device *dev) | |
666 | { | |
667 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
668 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
669 | unsigned long ievent; | |
670 | int frame_length, len = 0; | |
671 | struct nbuf *frame; | |
672 | uint16_t bd_status; | |
673 | uchar buff[FEC_MAX_PKT_SIZE]; | |
674 | ||
675 | /* | |
676 | * Check if any critical events have happened | |
677 | */ | |
678 | ievent = readl(&fec->eth->ievent); | |
679 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 680 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
681 | if (ievent & FEC_IEVENT_BABR) { |
682 | fec_halt(dev); | |
683 | fec_init(dev, fec->bd); | |
684 | printf("some error: 0x%08lx\n", ievent); | |
685 | return 0; | |
686 | } | |
687 | if (ievent & FEC_IEVENT_HBERR) { | |
688 | /* Heartbeat error */ | |
689 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
690 | &fec->eth->x_cntrl); | |
691 | } | |
692 | if (ievent & FEC_IEVENT_GRA) { | |
693 | /* Graceful stop complete */ | |
694 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
695 | fec_halt(dev); | |
696 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
697 | &fec->eth->x_cntrl); | |
698 | fec_init(dev, fec->bd); | |
699 | } | |
700 | } | |
701 | ||
702 | /* | |
703 | * ensure reading the right buffer status | |
704 | */ | |
705 | bd_status = readw(&rbd->status); | |
706 | debug("fec_recv: status 0x%x\n", bd_status); | |
707 | ||
708 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
709 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
710 | ((readw(&rbd->data_length) - 4) > 14)) { | |
711 | /* | |
712 | * Get buffer address and size | |
713 | */ | |
714 | frame = (struct nbuf *)readl(&rbd->data_pointer); | |
715 | frame_length = readw(&rbd->data_length) - 4; | |
716 | /* | |
717 | * Fill the buffer and pass it to upper layers | |
718 | */ | |
be7e87e2 MV |
719 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
720 | swap_packet((uint32_t *)frame->data, frame_length); | |
721 | #endif | |
0b23fb36 IY |
722 | memcpy(buff, frame->data, frame_length); |
723 | NetReceive(buff, frame_length); | |
724 | len = frame_length; | |
725 | } else { | |
726 | if (bd_status & FEC_RBD_ERR) | |
727 | printf("error frame: 0x%08lx 0x%08x\n", | |
728 | (ulong)rbd->data_pointer, | |
729 | bd_status); | |
730 | } | |
731 | /* | |
732 | * free the current buffer, restart the engine | |
733 | * and move forward to the next buffer | |
734 | */ | |
735 | fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); | |
736 | fec_rx_task_enable(fec); | |
737 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
738 | } | |
739 | debug("fec_recv: stop\n"); | |
740 | ||
741 | return len; | |
742 | } | |
743 | ||
9e27e9dc | 744 | static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) |
0b23fb36 | 745 | { |
0b23fb36 | 746 | struct eth_device *edev; |
9e27e9dc | 747 | struct fec_priv *fec; |
0b23fb36 | 748 | unsigned char ethaddr[6]; |
e382fb48 MV |
749 | uint32_t start; |
750 | int ret = 0; | |
0b23fb36 IY |
751 | |
752 | /* create and fill edev struct */ | |
753 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
754 | if (!edev) { | |
9e27e9dc | 755 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
756 | ret = -ENOMEM; |
757 | goto err1; | |
9e27e9dc MV |
758 | } |
759 | ||
760 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
761 | if (!fec) { | |
762 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
763 | ret = -ENOMEM; |
764 | goto err2; | |
0b23fb36 | 765 | } |
9e27e9dc | 766 | |
de0b9576 | 767 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
768 | memset(fec, 0, sizeof(*fec)); |
769 | ||
0b23fb36 IY |
770 | edev->priv = fec; |
771 | edev->init = fec_init; | |
772 | edev->send = fec_send; | |
773 | edev->recv = fec_recv; | |
774 | edev->halt = fec_halt; | |
fb57ec97 | 775 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 776 | |
9e27e9dc | 777 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
778 | fec->bd = bd; |
779 | ||
392b8502 | 780 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
781 | |
782 | /* Reset chip. */ | |
cb17b92d | 783 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
784 | start = get_timer(0); |
785 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
786 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
787 | printf("FEC MXC: Timeout reseting chip\n"); | |
788 | goto err3; | |
789 | } | |
0b23fb36 | 790 | udelay(10); |
e382fb48 | 791 | } |
0b23fb36 IY |
792 | |
793 | /* | |
794 | * Set interrupt mask register | |
795 | */ | |
796 | writel(0x00000000, &fec->eth->imask); | |
797 | ||
798 | /* | |
799 | * Clear FEC-Lite interrupt event register(IEVENT) | |
800 | */ | |
801 | writel(0xffffffff, &fec->eth->ievent); | |
802 | ||
803 | /* | |
804 | * Set FEC-Lite receive control register(R_CNTRL): | |
805 | */ | |
806 | /* | |
807 | * Frame length=1518; MII mode; | |
808 | */ | |
9eb3770b MV |
809 | writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | |
810 | FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); | |
4294b248 | 811 | fec_mii_setspeed(fec); |
0b23fb36 | 812 | |
9e27e9dc MV |
813 | if (dev_id == -1) { |
814 | sprintf(edev->name, "FEC"); | |
815 | fec->dev_id = 0; | |
816 | } else { | |
817 | sprintf(edev->name, "FEC%i", dev_id); | |
818 | fec->dev_id = dev_id; | |
819 | } | |
820 | fec->phy_id = phy_id; | |
0b23fb36 IY |
821 | |
822 | miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); | |
823 | ||
824 | eth_register(edev); | |
825 | ||
be252b65 FE |
826 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { |
827 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
4294b248 | 828 | memcpy(edev->enetaddr, ethaddr, 6); |
0b23fb36 | 829 | } |
0b23fb36 | 830 | |
e382fb48 MV |
831 | return ret; |
832 | ||
833 | err3: | |
834 | free(fec); | |
835 | err2: | |
836 | free(edev); | |
837 | err1: | |
838 | return ret; | |
0b23fb36 IY |
839 | } |
840 | ||
9e27e9dc | 841 | #ifndef CONFIG_FEC_MXC_MULTI |
0b23fb36 IY |
842 | int fecmxc_initialize(bd_t *bd) |
843 | { | |
844 | int lout = 1; | |
845 | ||
846 | debug("eth_init: fec_probe(bd)\n"); | |
9e27e9dc MV |
847 | lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
848 | ||
849 | return lout; | |
850 | } | |
851 | #endif | |
852 | ||
853 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) | |
854 | { | |
855 | int lout = 1; | |
856 | ||
857 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); | |
858 | lout = fec_probe(bd, dev_id, phy_id, addr); | |
0b23fb36 IY |
859 | |
860 | return lout; | |
861 | } | |
2e5f4421 MV |
862 | |
863 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) | |
864 | { | |
865 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
866 | fec->mii_postcall = cb; | |
867 | return 0; | |
868 | } |