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1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
1cb8e980 WD |
32 | /* |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
ac67804f | 36 | #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ |
37 | #define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ | |
38 | #define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ | |
39 | #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ | |
1cb8e980 | 40 | |
0bf42fec DMEA |
41 | #define CONFIG_SYS_TEXT_BASE 0x0 |
42 | ||
1cb8e980 WD |
43 | /* input clock of PLL */ |
44 | #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ | |
45 | ||
46 | #define USE_920T_MMU 1 | |
47 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
48 | ||
53677ef1 | 49 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
1cb8e980 WD |
50 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
51 | #define CONFIG_INITRD_TAG 1 | |
52 | ||
a5562901 | 53 | |
a1aa0bb5 JL |
54 | /* |
55 | * BOOTP options | |
56 | */ | |
57 | #define CONFIG_BOOTP_BOOTFILESIZE | |
58 | #define CONFIG_BOOTP_BOOTPATH | |
59 | #define CONFIG_BOOTP_GATEWAY | |
60 | #define CONFIG_BOOTP_HOSTNAME | |
61 | ||
62 | ||
a5562901 JL |
63 | /* |
64 | * Command line configuration. | |
65 | */ | |
66 | #include <config_cmd_default.h> | |
67 | ||
68 | #define CONFIG_CMD_CACHE | |
69 | #define CONFIG_CMD_EEPROM | |
70 | #define CONFIG_CMD_I2C | |
71 | #define CONFIG_CMD_USB | |
72 | #define CONFIG_CMD_REGINFO | |
73 | #define CONFIG_CMD_FAT | |
74 | #define CONFIG_CMD_DATE | |
75 | #define CONFIG_CMD_ELF | |
76 | #define CONFIG_CMD_DHCP | |
77 | #define CONFIG_CMD_PING | |
78 | #define CONFIG_CMD_BSP | |
79 | ||
1cb8e980 | 80 | |
6d0f6bcf JCPV |
81 | #define CONFIG_SYS_HUSH_PARSER |
82 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1cb8e980 WD |
83 | /*********************************************************** |
84 | * I2C stuff: | |
85 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
86 | * address 0x50 with 16bit addressing | |
87 | ***********************************************************/ | |
88 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ |
90 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ | |
1cb8e980 | 91 | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
93 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
bb1f8b4f | 94 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
95 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ |
96 | #define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ | |
1cb8e980 | 97 | |
6d0f6bcf JCPV |
98 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
99 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ | |
100 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
1cb8e980 WD |
101 | |
102 | /* | |
103 | * Size of malloc() pool | |
104 | */ | |
0e8d1586 | 105 | /*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ |
1cb8e980 | 106 | |
6d0f6bcf | 107 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
6d754843 | 108 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
6d0f6bcf | 109 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ |
1cb8e980 WD |
110 | |
111 | /* | |
112 | * Hardware drivers | |
113 | */ | |
b1c0eaac BW |
114 | #define CONFIG_NET_MULTI |
115 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ | |
116 | #define CONFIG_CS8900_BASE 0x20000300 | |
117 | #define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ | |
1cb8e980 WD |
118 | |
119 | #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ | |
120 | ||
121 | /* | |
122 | * select serial console configuration | |
123 | */ | |
300f99f4 | 124 | #define CONFIG_S3C24X0_SERIAL |
1cb8e980 WD |
125 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
126 | ||
48b42616 WD |
127 | /************************************************************ |
128 | * USB support | |
129 | ************************************************************/ | |
a2663ea4 WD |
130 | #define CONFIG_USB_OHCI 1 |
131 | #define CONFIG_USB_KEYBOARD 1 | |
132 | #define CONFIG_USB_STORAGE 1 | |
133 | #define CONFIG_DOS_PARTITION 1 | |
48b42616 WD |
134 | |
135 | /* Enable needed helper functions */ | |
52cb4d4f | 136 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
48b42616 WD |
137 | |
138 | /************************************************************ | |
139 | * RTC | |
140 | ************************************************************/ | |
141 | #define CONFIG_RTC_S3C24X0 1 | |
142 | ||
143 | ||
1cb8e980 WD |
144 | /* allow to overwrite serial and ethaddr */ |
145 | #define CONFIG_ENV_OVERWRITE | |
146 | ||
147 | #define CONFIG_BAUDRATE 9600 | |
148 | ||
a2663ea4 WD |
149 | #define CONFIG_BOOTDELAY 5 |
150 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ | |
2893ecbf | 151 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
53677ef1 | 152 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ |
a2663ea4 | 153 | |
1cb8e980 WD |
154 | #define CONFIG_NETMASK 255.255.255.0 |
155 | #define CONFIG_IPADDR 10.0.0.110 | |
156 | #define CONFIG_SERVERIP 10.0.0.1 | |
157 | ||
a5562901 | 158 | #if defined(CONFIG_CMD_KGDB) |
1cb8e980 WD |
159 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
160 | /* what's this ? it's not used anywhere */ | |
161 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
162 | #endif | |
163 | ||
164 | /* | |
165 | * Miscellaneous configurable options | |
166 | */ | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
168 | #define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ | |
169 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
170 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
171 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
172 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
1cb8e980 | 173 | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
175 | #define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ | |
531716e1 | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_ALT_MEMTEST |
178 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */ | |
1cb8e980 | 179 | |
1cb8e980 | 180 | /* we configure PWM Timer 4 to 1us ~ 1MHz */ |
6d0f6bcf JCPV |
181 | /*#define CONFIG_SYS_HZ 1000000 */ |
182 | #define CONFIG_SYS_HZ 1562500 | |
1cb8e980 WD |
183 | |
184 | /* valid baudrates */ | |
6d0f6bcf | 185 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
1cb8e980 | 186 | |
a2663ea4 WD |
187 | /* support BZIP2 compression */ |
188 | #define CONFIG_BZIP2 1 | |
189 | ||
48b42616 WD |
190 | /************************************************************ |
191 | * Ident | |
192 | ************************************************************/ | |
193 | /*#define VERSION_TAG "released"*/ | |
194 | #define VERSION_TAG "unstable" | |
195 | #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG | |
196 | ||
1cb8e980 WD |
197 | /*----------------------------------------------------------------------- |
198 | * Stack sizes | |
199 | * | |
200 | * The stack sizes are set up in start.S using the settings below | |
201 | */ | |
202 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
203 | #ifdef CONFIG_USE_IRQ | |
204 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
205 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
206 | #endif | |
207 | ||
208 | /*----------------------------------------------------------------------- | |
209 | * Physical Memory Map | |
210 | */ | |
211 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
212 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
1cb8e980 WD |
213 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
214 | ||
6d754843 | 215 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 WD |
216 | |
217 | /*----------------------------------------------------------------------- | |
218 | * FLASH and environment organization | |
219 | */ | |
220 | ||
6d754843 DMEA |
221 | #define CONFIG_SYS_FLASH_CFI |
222 | #define CONFIG_FLASH_CFI_DRIVER | |
223 | #define CONFIG_FLASH_CFI_LEGACY | |
224 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
225 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
1cb8e980 | 226 | |
6d0f6bcf | 227 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
6d754843 DMEA |
228 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
229 | #define CONFIG_SYS_MAX_FLASH_SECT (19) | |
1cb8e980 WD |
230 | |
231 | #if 0 | |
5a1aceb0 | 232 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 233 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
1cb8e980 WD |
234 | #endif |
235 | ||
48b42616 | 236 | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
238 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
48b42616 WD |
239 | |
240 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 | |
241 | ||
d2d94571 DMEA |
242 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
243 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
244 | GENERATED_GBL_DATA_SIZE) | |
245 | ||
246 | ||
1cb8e980 | 247 | #endif /* __CONFIG_H */ |