[people/ms/u-boot.git] / include / configs / mx31pdk.h

/*
 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
 *
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Kshitij Gupta <kshitij@ti.com>
 *
 * Configuration settings for the Freescale i.MX31 PDK board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

/* High Level Configuration Options */
#define CONFIG_MX31			/* This is a mx31 */

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_MACH_TYPE	MACH_TYPE_MX31_3DS

#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE	2048

#define CONFIG_SPL_TEXT_BASE	0x87dc0000
#define CONFIG_SYS_TEXT_BASE	0x87e00000

#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(2*CONFIG_ENV_SIZE + 2 * 128 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE
#define CONFIG_MXC_GPIO

#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	2
#define CONFIG_FSL_PMIC_CLK	1000000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN	32
#define CONFIG_RTC_MC13XXX

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX		1

/***********************************************************
 * Command definition
 ***********************************************************/
#define CONFIG_CMD_NAND


#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
	"bootcmd=run bootcmd_net\0"					\
	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
		"tftpboot 0x81000000 uImage-mx31; bootm\0"		\
	"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "		\
		"nand erase 0x0 0x40000; "				\
		"nand write 0x81000000 0x0 0x40000\0"

#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE	0xB6000000
#define CONFIG_SMC911X_32_BIT

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
/* max number of command args */
#define CONFIG_SYS_MAXARGS	16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x80010000

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		0x81000000

#define CONFIG_CMDLINE_EDITING

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_INIT_RAM_SIZE)

/*
 * environment organization
 */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_OFFSET_REDUND	0x60000
#define CONFIG_ENV_SIZE			(128 * 1024)

/*
 * NAND driver
 */
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE     1
#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE

/* NAND configuration for the NAND_SPL */

/* Start copying real U-Boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x3f800
/* Load U-Boot to this address */
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST

#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0

/* Configuration of lowlevel_init.S (clocks and SDRAM) */
#define CCM_CCMR_SETUP		0x074B0BF5
#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
				 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
				 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
				 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
				 PLL_MFN(12))

#define ESDMISC_MDDR_SETUP	0x00000004
#define ESDMISC_MDDR_RESET_DL	0x0000000c
#define ESDCFG0_MDDR_SETUP	0x006ac73a

#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
#define ESDCTL_RW		ESDCTL_SETTINGS

#endif /* __CONFIG_H */
Commit	Line	Data
8449f287 ML	1	/*
	2	* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
	3	*
	4	* (C) Copyright 2004
	5	* Texas Instruments.
	6	* Richard Woodruff <r-woodruff2@ti.com>
	7	* Kshitij Gupta <kshitij@ti.com>
	8	*
	9	* Configuration settings for the Freescale i.MX31 PDK board.
	10	*
3765b3e7	11	* SPDX-License-Identifier: GPL-2.0+
8449f287 ML	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
86271115	17	#include <asm/arch/imx-regs.h>
38a8b3ea	18
8449f287	19	/* High Level Configuration Options */
3fd968e9	20	#define CONFIG_MX31 /* This is a mx31 */
8449f287	21
e89f1f91 FE	22	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	23	#define CONFIG_SETUP_MEMORY_TAGS
	24	#define CONFIG_INITRD_TAG
8449f287	25
9aa3c6a1 FE	26	#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
9aa3c6a1 FE	27
da962b71 BT	28	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	29	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
	30	#define CONFIG_SPL_MAX_SIZE 2048
da962b71 BT	31
	32	#define CONFIG_SPL_TEXT_BASE 0x87dc0000
	33	#define CONFIG_SYS_TEXT_BASE 0x87e00000
	34
	35	#ifndef CONFIG_SPL_BUILD
8449f287	36	#define CONFIG_SKIP_LOWLEVEL_INIT
d08e5ca3	37	#endif
8449f287 ML	38
	39	/*
	40	* Size of malloc() pool
	41	*/
38a8b3ea	42	#define CONFIG_SYS_MALLOC_LEN (2CONFIG_ENV_SIZE + 2 128 * 1024)
8449f287 ML	43
	44	/*
	45	* Hardware drivers
	46	*/
	47
e89f1f91	48	#define CONFIG_MXC_UART
40f6fffe	49	#define CONFIG_MXC_UART_BASE UART1_BASE
6f2a4be9	50	#define CONFIG_MXC_GPIO
8449f287	51
e89f1f91 FE	52	#define CONFIG_HARD_SPI
e89f1f91 FE	53	#define CONFIG_MXC_SPI
8449f287	54	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	55	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
8449f287	56
877a438a	57	/* PMIC Controller */
be3b51aa ŁM	58	#define CONFIG_POWER
	59	#define CONFIG_POWER_SPI
	60	#define CONFIG_POWER_FSL
dfe5e14f SB	61	#define CONFIG_FSL_PMIC_BUS 1
	62	#define CONFIG_FSL_PMIC_CS 2
	63	#define CONFIG_FSL_PMIC_CLK 1000000
9f481e95	64	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
877a438a	65	#define CONFIG_FSL_PMIC_BITLEN 32
4e8b7544	66	#define CONFIG_RTC_MC13XXX
8449f287	67
8449f287 ML	68	/* allow to overwrite serial and ethaddr */
	69	#define CONFIG_ENV_OVERWRITE
	70	#define CONFIG_CONS_INDEX 1
8449f287 ML	71
	72	/***********************************************************
	73	* Command definition
	74	***********************************************************/
38a8b3ea	75	#define CONFIG_CMD_NAND
8449f287	76
8449f287 ML	77
	78	#define CONFIG_EXTRA_ENV_SETTINGS \
	79	"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
	80	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
	81	"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
	82	"bootcmd=run bootcmd_net\0" \
	83	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
38a8b3ea	84	"tftpboot 0x81000000 uImage-mx31; bootm\0" \
da962b71	85	"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
38a8b3ea ML	86	"nand erase 0x0 0x40000; " \
38a8b3ea ML	87	"nand write 0x81000000 0x0 0x40000\0"
8449f287	88
e89f1f91	89	#define CONFIG_SMC911X
736fead8	90	#define CONFIG_SMC911X_BASE 0xB6000000
e89f1f91	91	#define CONFIG_SMC911X_32_BIT
8449f287 ML	92
	93	/*
	94	* Miscellaneous configurable options
	95	*/
	96	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8449f287	97	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8449f287 ML	98	/* max number of command args */
	99	#define CONFIG_SYS_MAXARGS 16
	100	/* Boot Argument Buffer Size */
	101	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	102
	103	/* memtest works on */
	104	#define CONFIG_SYS_MEMTEST_START 0x80000000
304e49e6	105	#define CONFIG_SYS_MEMTEST_END 0x80010000
8449f287 ML	106
	107	/* default load address */
	108	#define CONFIG_SYS_LOAD_ADDR 0x81000000
	109
e89f1f91	110	#define CONFIG_CMDLINE_EDITING
8449f287	111
8449f287 ML	112	/*-----------------------------------------------------------------------
	113	* Physical Memory Map
	114	*/
	115	#define CONFIG_NR_DRAM_BANKS 1
	116	#define PHYS_SDRAM_1 CSD0_BASE
	117	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
	118
ed3df72d FE	119	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	120	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	121	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
026ca659 FE	122	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	123	GENERATED_GBL_DATA_SIZE)
	124	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
da962b71	125	CONFIG_SYS_INIT_RAM_SIZE)
ed3df72d	126
e856bdcf MY	127	/*
e856bdcf MY	128	* environment organization
8449f287	129	*/
e89f1f91	130	#define CONFIG_ENV_IS_IN_NAND
38a8b3ea ML	131	#define CONFIG_ENV_OFFSET 0x40000
	132	#define CONFIG_ENV_OFFSET_REDUND 0x60000
	133	#define CONFIG_ENV_SIZE (128 * 1024)
8449f287	134
38a8b3ea ML	135	/*
	136	* NAND driver
	137	*/
	138	#define CONFIG_NAND_MXC
	139	#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
	140	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	141	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
	142	#define CONFIG_MXC_NAND_HWECC
	143	#define CONFIG_SYS_NAND_LARGEPAGE
8449f287	144
d08e5ca3 ML	145	/* NAND configuration for the NAND_SPL */
d08e5ca3 ML	146
a187559e	147	/* Start copying real U-Boot from the second page */
da962b71 BT	148	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
da962b71 BT	149	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
d08e5ca3	150	/* Load U-Boot to this address */
da962b71	151	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
d08e5ca3 ML	152	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	153
	154	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	155	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	156	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	157	#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
	158	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	159
d08e5ca3 ML	160	/* Configuration of lowlevel_init.S (clocks and SDRAM) */
d08e5ca3 ML	161	#define CCM_CCMR_SETUP 0x074B0BF5
9e0081d5 BT	162	#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) \| PDR0_CSI_PRDF(7) \| \
	163	PDR0_PER_PODF(7) \| PDR0_HSP_PODF(3) \| \
	164	PDR0_NFC_PODF(5) \| PDR0_IPG_PODF(1) \| \
	165	PDR0_MAX_PODF(3) \| PDR0_MCU_PODF(0))
	166	#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) \| PLL_MFD(51) \| PLL_MFI(10) \| \
d08e5ca3 ML	167	PLL_MFN(12))
	168
	169	#define ESDMISC_MDDR_SETUP 0x00000004
	170	#define ESDMISC_MDDR_RESET_DL 0x0000000c
	171	#define ESDCFG0_MDDR_SETUP 0x006ac73a
	172
	173	#define ESDCTL_ROW_COL (ESDCTL_SDE \| ESDCTL_ROW(2) \| ESDCTL_COL(2))
	174	#define ESDCTL_SETTINGS (ESDCTL_ROW_COL \| ESDCTL_SREFR(3) \| \
	175	ESDCTL_DSIZ(2) \| ESDCTL_BL(1))
	176	#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL \| ESDCTL_CMD_PRECHARGE)
	177	#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL \| ESDCTL_CMD_AUTOREFRESH)
	178	#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL \| ESDCTL_CMD_LOADMODEREG)
	179	#define ESDCTL_RW ESDCTL_SETTINGS
	180
8449f287	181	#endif /* __CONFIG_H */