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1/*
2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
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8#ifndef _TEGRA_COMMON_H_
9#define _TEGRA_COMMON_H_
1ace4022 10#include <linux/sizes.h>
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11#include <linux/stringify.h>
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
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17#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
18
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19#include <asm/arch/tegra.h> /* get chip and board defs */
20
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21/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
22#ifndef CONFIG_ARM64
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23#define CONFIG_SYS_TIMER_RATE 1000000
24#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
f41f0a19 25#endif
31df9893 26
f01b631f 27#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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28
29/* Environment */
30#define CONFIG_ENV_VARS_UBOOT_CONFIG
31#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
32
f01b631f 33/*
bfcf46db 34 * NS16550 Configuration
f01b631f 35 */
1874626b 36#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
f01b631f 37
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38/*
39 * Common HW configuration.
40 * If this varies between SoCs later, move to tegraNN-common.h
41 * Note: This is number of devices, not max device ID.
42 */
43#define CONFIG_SYS_MMC_MAX_DEVICE 4
44
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45/*
46 * select serial console configuration
47 */
48#define CONFIG_CONS_INDEX 1
49
50/* allow to overwrite serial and ethaddr */
51#define CONFIG_ENV_OVERWRITE
52#define CONFIG_BAUDRATE 115200
53
f01b631f 54/* turn on command-line edit/hist/auto */
f01b631f 55#define CONFIG_COMMAND_HISTORY
f01b631f 56
11d9c030 57/* turn on commonly used storage-related commands */
11d9c030 58#define CONFIG_PARTITION_UUIDS
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59#define CONFIG_CMD_PART
60
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61#define CONFIG_SYS_NO_FLASH
62
63#define CONFIG_CONSOLE_MUX
64#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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65#ifndef CONFIG_SPL_BUILD
66#define CONFIG_SYS_STDIO_DEREGISTER
67#endif
f01b631f 68
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69/*
70 * Increasing the size of the IO buffer as default nfsargs size is more
71 * than 256 and so it is not possible to edit it
72 */
64a4fe74 73#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
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74/* Print Buffer Size */
75#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
76 sizeof(CONFIG_SYS_PROMPT) + 16)
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77#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
78
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79/* Boot Argument Buffer Size */
80#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
81
82#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
83#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
84
6527268d 85#ifndef CONFIG_ARM64
9dacbb27 86#ifndef CONFIG_SPL_BUILD
4270d5af 87#define CONFIG_USE_ARCH_MEMCPY
9dacbb27 88#endif
6527268d 89#endif
4270d5af 90
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91/*-----------------------------------------------------------------------
92 * Physical Memory Map
93 */
bbc1b99e 94#define CONFIG_NR_DRAM_BANKS 2
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95#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
96#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
97
98#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
99#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
100
101#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
102
103#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
104#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
105#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
106 CONFIG_SYS_INIT_RAM_SIZE - \
107 GENERATED_GBL_DATA_SIZE)
108
f01b631f 109#define CONFIG_CMD_ENTERRCM
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110
111/* Defines for SPL */
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112#define CONFIG_SPL_FRAMEWORK
113#define CONFIG_SPL_RAM_DEVICE
114#define CONFIG_SPL_BOARD_INIT
115#define CONFIG_SPL_NAND_SIMPLE
6ebc3461 116#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
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117 CONFIG_SPL_TEXT_BASE)
118#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
119
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120#define CONFIG_BOARD_EARLY_INIT_F
121#define CONFIG_BOARD_LATE_INIT
3efff99f 122
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123/* Misc utility code */
124#define CONFIG_BOUNCE_BUFFER
3efff99f 125#define CONFIG_CRC32_VERIFY
dd7f65f6 126
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127#ifndef CONFIG_SPL_BUILD
128#include <config_distro_defaults.h>
68295a48 129#define CONFIG_FAT_WRITE
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130#endif
131
f01b631f 132#endif /* _TEGRA_COMMON_H_ */