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5894ca00 | 1 | /* |
e8a92932 MY |
2 | * Copyright (C) 2012-2015 Panasonic Corporation |
3 | * Copyright (C) 2015-2016 Socionext Inc. | |
4 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
5894ca00 MY |
5 | * |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
a187559e | 9 | /* U-Boot - Common settings for UniPhier Family */ |
5894ca00 MY |
10 | |
11 | #ifndef __CONFIG_UNIPHIER_COMMON_H__ | |
12 | #define __CONFIG_UNIPHIER_COMMON_H__ | |
13 | ||
e8a92932 MY |
14 | #define CONFIG_ARMV7_PSCI |
15 | #define CONFIG_ARMV7_PSCI_NR_CPUS 4 | |
16 | ||
233e42a9 MY |
17 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
18 | ||
f5d0b9b2 MY |
19 | #define CONFIG_SMC911X |
20 | ||
d7728aa4 MY |
21 | /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ |
22 | #define CONFIG_SMC911X_BASE 0 | |
5894ca00 MY |
23 | #define CONFIG_SMC911X_32_BIT |
24 | ||
5894ca00 MY |
25 | /*----------------------------------------------------------------------- |
26 | * MMU and Cache Setting | |
27 | *----------------------------------------------------------------------*/ | |
28 | ||
29 | /* Comment out the following to enable L1 cache */ | |
30 | /* #define CONFIG_SYS_ICACHE_OFF */ | |
31 | /* #define CONFIG_SYS_DCACHE_OFF */ | |
32 | ||
8fca0732 MY |
33 | #ifdef CONFIG_CACHE_UNIPHIER |
34 | #define CONFIG_SYS_CACHELINE_SIZE 128 | |
35 | #else | |
53c45d4e | 36 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
8fca0732 | 37 | #endif |
53c45d4e | 38 | |
5894ca00 MY |
39 | #define CONFIG_DISPLAY_CPUINFO |
40 | #define CONFIG_DISPLAY_BOARDINFO | |
08fda258 | 41 | #define CONFIG_MISC_INIT_F |
84ccd791 | 42 | #define CONFIG_BOARD_EARLY_INIT_F |
7a3620b2 | 43 | #define CONFIG_BOARD_EARLY_INIT_R |
5894ca00 MY |
44 | #define CONFIG_BOARD_LATE_INIT |
45 | ||
46 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
47 | ||
48 | #define CONFIG_TIMESTAMP | |
49 | ||
50 | /* FLASH related */ | |
51 | #define CONFIG_MTD_DEVICE | |
52 | ||
53 | /* | |
54 | * uncomment the following to disable FLASH related code. | |
55 | */ | |
56 | /* #define CONFIG_SYS_NO_FLASH */ | |
57 | ||
58 | #define CONFIG_FLASH_CFI_DRIVER | |
59 | #define CONFIG_SYS_FLASH_CFI | |
60 | ||
61 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
62 | #define CONFIG_SYS_MONITOR_BASE 0 | |
d085ecd6 | 63 | #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ |
5894ca00 MY |
64 | #define CONFIG_SYS_FLASH_BASE 0 |
65 | ||
66 | /* | |
67 | * flash_toggle does not work for out supoort card. | |
68 | * We need to use flash_status_poll. | |
69 | */ | |
70 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
71 | ||
72 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
73 | ||
9879842c | 74 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
5894ca00 MY |
75 | |
76 | /* serial console configuration */ | |
77 | #define CONFIG_BAUDRATE 115200 | |
78 | ||
9d0c2ceb | 79 | #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) |
5894ca00 MY |
80 | #define CONFIG_USE_ARCH_MEMSET |
81 | #define CONFIG_USE_ARCH_MEMCPY | |
82 | #endif | |
83 | ||
84 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
85 | ||
86 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
5894ca00 MY |
87 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
88 | /* Print Buffer Size */ | |
89 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
90 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
91 | /* Boot Argument Buffer Size */ | |
92 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
93 | ||
94 | #define CONFIG_CONS_INDEX 1 | |
95 | ||
aa8a9348 | 96 | /* #define CONFIG_ENV_IS_NOWHERE */ |
5894ca00 | 97 | /* #define CONFIG_ENV_IS_IN_NAND */ |
aa8a9348 MY |
98 | #define CONFIG_ENV_IS_IN_MMC |
99 | #define CONFIG_ENV_OFFSET 0x80000 | |
5894ca00 | 100 | #define CONFIG_ENV_SIZE 0x2000 |
5894ca00 MY |
101 | /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ |
102 | ||
aa8a9348 MY |
103 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
104 | #define CONFIG_SYS_MMC_ENV_PART 1 | |
105 | ||
9d0c2ceb | 106 | #ifdef CONFIG_ARM64 |
50862a51 | 107 | #define CPU_RELEASE_ADDR 0x80000000 |
9d0c2ceb MY |
108 | #define COUNTER_FREQUENCY 50000000 |
109 | #define CONFIG_GICV3 | |
110 | #define GICD_BASE 0x5fe00000 | |
667dbcd0 MY |
111 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
112 | #define GICR_BASE 0x5fe40000 | |
113 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 114 | #define GICR_BASE 0x5fe80000 |
667dbcd0 | 115 | #endif |
9d0c2ceb | 116 | #else |
5894ca00 MY |
117 | /* Time clock 1MHz */ |
118 | #define CONFIG_SYS_TIMER_RATE 1000000 | |
9d0c2ceb MY |
119 | #endif |
120 | ||
5894ca00 | 121 | |
5894ca00 MY |
122 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
123 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
124 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
125 | ||
126 | #define CONFIG_NAND_DENALI_ECC_SIZE 1024 | |
127 | ||
ea65c980 | 128 | #ifdef CONFIG_ARCH_UNIPHIER_SLD3 |
3365b4eb MY |
129 | #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 |
130 | #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 | |
131 | #else | |
5894ca00 MY |
132 | #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 |
133 | #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 | |
3365b4eb | 134 | #endif |
5894ca00 MY |
135 | |
136 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
137 | ||
138 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
139 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
140 | ||
495deb44 | 141 | /* USB */ |
495deb44 | 142 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
53c45d4e | 143 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 |
495deb44 MY |
144 | #define CONFIG_FAT_WRITE |
145 | #define CONFIG_DOS_PARTITION | |
146 | ||
4aceb3f8 | 147 | /* SD/MMC */ |
a55d9fee | 148 | #define CONFIG_SUPPORT_EMMC_BOOT |
4aceb3f8 MY |
149 | #define CONFIG_GENERIC_MMC |
150 | ||
5894ca00 MY |
151 | /* memtest works on */ |
152 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
153 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) | |
154 | ||
5894ca00 MY |
155 | /* |
156 | * Network Configuration | |
157 | */ | |
5894ca00 MY |
158 | #define CONFIG_SERVERIP 192.168.11.1 |
159 | #define CONFIG_IPADDR 192.168.11.10 | |
160 | #define CONFIG_GATEWAYIP 192.168.11.1 | |
161 | #define CONFIG_NETMASK 255.255.255.0 | |
162 | ||
163 | #define CONFIG_LOADADDR 0x84000000 | |
164 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
5894ca00 MY |
165 | |
166 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
167 | ||
168 | #define CONFIG_BOOTCOMMAND "run $bootmode" | |
169 | ||
170 | #define CONFIG_ROOTPATH "/nfs/root/path" | |
171 | #define CONFIG_NFSBOOTCOMMAND \ | |
172 | "setenv bootargs $bootargs root=/dev/nfs rw " \ | |
173 | "nfsroot=$serverip:$rootpath " \ | |
174 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ | |
d566f754 | 175 | "run __nfsboot" |
5894ca00 | 176 | |
421376ae MY |
177 | #ifdef CONFIG_FIT |
178 | #define CONFIG_BOOTFILE "fitImage" | |
179 | #define LINUXBOOT_ENV_SETTINGS \ | |
180 | "fit_addr=0x00100000\0" \ | |
181 | "fit_addr_r=0x84100000\0" \ | |
182 | "fit_size=0x00f00000\0" \ | |
5451b777 | 183 | "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ |
421376ae | 184 | "bootm $fit_addr\0" \ |
5451b777 | 185 | "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ |
e037db0c | 186 | "bootm $fit_addr_r\0" \ |
5451b777 | 187 | "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ |
d566f754 MY |
188 | "bootm $fit_addr_r\0" \ |
189 | "__nfsboot=run tftpboot\0" | |
421376ae | 190 | #else |
9d0c2ceb | 191 | #ifdef CONFIG_ARM64 |
9d0c2ceb MY |
192 | #define CONFIG_BOOTFILE "Image" |
193 | #define LINUXBOOT_CMD "booti" | |
194 | #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" | |
195 | #define KERNEL_SIZE "kernel_size=0x00c00000\0" | |
196 | #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" | |
197 | #else | |
89835b35 | 198 | #define CONFIG_BOOTFILE "zImage" |
9d0c2ceb MY |
199 | #define LINUXBOOT_CMD "bootz" |
200 | #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" | |
201 | #define KERNEL_SIZE "kernel_size=0x00800000\0" | |
202 | #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" | |
203 | #endif | |
421376ae MY |
204 | #define LINUXBOOT_ENV_SETTINGS \ |
205 | "fdt_addr=0x00100000\0" \ | |
206 | "fdt_addr_r=0x84100000\0" \ | |
207 | "fdt_size=0x00008000\0" \ | |
208 | "kernel_addr=0x00200000\0" \ | |
9d0c2ceb MY |
209 | KERNEL_ADDR_R \ |
210 | KERNEL_SIZE \ | |
211 | RAMDISK_ADDR \ | |
421376ae MY |
212 | "ramdisk_addr_r=0x84a00000\0" \ |
213 | "ramdisk_size=0x00600000\0" \ | |
e037db0c | 214 | "ramdisk_file=rootfs.cpio.uboot\0" \ |
cd5d9565 | 215 | "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ |
9d0c2ceb | 216 | LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ |
cd5d9565 | 217 | "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ |
b75e072c MY |
218 | "setexpr kernel_size $kernel_size / 4 &&" \ |
219 | "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ | |
cd5d9565 MY |
220 | "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ |
221 | "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ | |
222 | "run boot_common\0" \ | |
223 | "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ | |
421376ae MY |
224 | "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ |
225 | "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ | |
cd5d9565 MY |
226 | "run boot_common\0" \ |
227 | "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
e037db0c MY |
228 | "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ |
229 | "tftpboot $fdt_addr_r $fdt_file &&" \ | |
d566f754 MY |
230 | "run boot_common\0" \ |
231 | "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
d566f754 MY |
232 | "tftpboot $fdt_addr_r $fdt_file &&" \ |
233 | "setenv ramdisk_addr_r - &&" \ | |
cd5d9565 | 234 | "run boot_common\0" |
421376ae MY |
235 | #endif |
236 | ||
237 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
238 | "netdev=eth0\0" \ | |
239 | "verify=n\0" \ | |
90a6e929 | 240 | "nor_base=0x42000000\0" \ |
61a4f5bd MY |
241 | "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ |
242 | "tftpboot $tmp_addr u-boot-spl.bin &&" \ | |
243 | "setexpr tmp_addr $nor_base + 0x60000 &&" \ | |
244 | "tftpboot $tmp_addr u-boot.bin\0" \ | |
c231c436 MY |
245 | "emmcupdate=mmcsetn &&" \ |
246 | "mmc partconf $mmc_first_dev 0 1 1 &&" \ | |
c231c436 MY |
247 | "tftpboot u-boot-spl.bin &&" \ |
248 | "mmc write $loadaddr 0 80 &&" \ | |
d085ecd6 | 249 | "tftpboot u-boot.bin &&" \ |
c231c436 | 250 | "mmc write $loadaddr 80 780\0" \ |
421376ae | 251 | "nandupdate=nand erase 0 0x00100000 &&" \ |
3cb9abc9 | 252 | "tftpboot u-boot-spl.bin &&" \ |
421376ae | 253 | "nand write $loadaddr 0 0x00010000 &&" \ |
d085ecd6 | 254 | "tftpboot u-boot.bin &&" \ |
421376ae | 255 | "nand write $loadaddr 0x00010000 0x000f0000\0" \ |
421376ae | 256 | LINUXBOOT_ENV_SETTINGS |
5894ca00 | 257 | |
17bd4a21 MY |
258 | #define CONFIG_SYS_BOOTMAPSZ 0x20000000 |
259 | ||
cf88affa | 260 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
5894ca00 | 261 | #define CONFIG_NR_DRAM_BANKS 2 |
23869698 MY |
262 | /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ |
263 | #define CONFIG_SYS_MEM_TOP_HIDE 64 | |
5894ca00 | 264 | |
9d0c2ceb MY |
265 | #if defined(CONFIG_ARM64) |
266 | #define CONFIG_SPL_TEXT_BASE 0x30000000 | |
267 | #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ | |
268 | defined(CONFIG_ARCH_UNIPHIER_LD4) || \ | |
ea65c980 | 269 | defined(CONFIG_ARCH_UNIPHIER_SLD8) |
f5d0b9b2 | 270 | #define CONFIG_SPL_TEXT_BASE 0x00040000 |
323d1f9d | 271 | #else |
f5d0b9b2 MY |
272 | #define CONFIG_SPL_TEXT_BASE 0x00100000 |
273 | #endif | |
274 | ||
667dbcd0 MY |
275 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
276 | #define CONFIG_SPL_STACK (0x30014c00) | |
277 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb MY |
278 | #define CONFIG_SPL_STACK (0x3001c000) |
279 | #else | |
755c7d9a | 280 | #define CONFIG_SPL_STACK (0x00100000) |
9d0c2ceb | 281 | #endif |
8cddc279 | 282 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) |
5894ca00 | 283 | |
a286039b MY |
284 | #define CONFIG_PANIC_HANG |
285 | ||
5894ca00 | 286 | #define CONFIG_SPL_FRAMEWORK |
499785b9 | 287 | #define CONFIG_SPL_SERIAL_SUPPORT |
cbbc2d80 | 288 | #define CONFIG_SPL_NOR_SUPPORT |
adb3928f MY |
289 | #ifdef CONFIG_ARM64 |
290 | #define CONFIG_SPL_BOARD_LOAD_IMAGE | |
291 | #else | |
5894ca00 | 292 | #define CONFIG_SPL_NAND_SUPPORT |
a55d9fee | 293 | #define CONFIG_SPL_MMC_SUPPORT |
9d0c2ceb | 294 | #endif |
5894ca00 MY |
295 | |
296 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ | |
297 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
298 | ||
299 | #define CONFIG_SPL_BOARD_INIT | |
300 | ||
301 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 | |
cbbc2d80 | 302 | |
d085ecd6 MY |
303 | /* subtract sizeof(struct image_header) */ |
304 | #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) | |
a55d9fee | 305 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 |
5894ca00 | 306 | |
d085ecd6 | 307 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
6a3cffe8 | 308 | #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 |
86c3345a | 309 | #define CONFIG_SPL_MAX_SIZE 0x10000 |
667dbcd0 MY |
310 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
311 | #define CONFIG_SPL_BSS_START_ADDR 0x30012000 | |
312 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 313 | #define CONFIG_SPL_BSS_START_ADDR 0x30016000 |
667dbcd0 | 314 | #endif |
9d0c2ceb | 315 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 |
6a3cffe8 | 316 | |
5894ca00 | 317 | #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ |