[people/ms/u-boot.git] / include / configs / zynq-common.h

/*
 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
 * (C) Copyright 2013 Xilinx, Inc.
 *
 * Common configuration options for all Zynq boards.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_ZYNQ_COMMON_H
#define __CONFIG_ZYNQ_COMMON_H

/* CPU clock */
#ifndef CONFIG_CPU_FREQ_HZ
# define CONFIG_CPU_FREQ_HZ	800000000
#endif

/* Cache options */
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310
# define CONFIG_SYS_PL310_BASE		0xf8f02000
#endif

#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
#define CONFIG_SYS_TIMERBASE		ZYNQ_SCUTIMER_BASEADDR
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)

/* Serial drivers */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

#define CONFIG_ARM_DCC
#define CONFIG_ZYNQ_SERIAL

/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHY_MARVELL
# define CONFIG_PHY_REALTEK
# define CONFIG_PHY_XILINX
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_HOSTNAME
# define CONFIG_BOOTP_MAY_FAIL
#endif

/* SPI */
#ifdef CONFIG_ZYNQ_SPI
#endif

/* QSPI */
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED	30000000
# define CONFIG_SPI_FLASH_ISSI
#endif

/* NOR */
#ifdef CONFIG_MTD_NOR_FLASH
# define CONFIG_SYS_FLASH_BASE		0xE2000000
# define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
# define CONFIG_SYS_MAX_FLASH_BANKS	1
# define CONFIG_SYS_MAX_FLASH_SECT	512
# define CONFIG_SYS_FLASH_ERASE_TOUT	1000
# define CONFIG_SYS_FLASH_WRITE_TOUT	5000
# define CONFIG_FLASH_SHOW_PROGRESS	10
# define CONFIG_SYS_FLASH_CFI
# undef CONFIG_SYS_FLASH_EMPTY_INFO
# define CONFIG_FLASH_CFI_DRIVER
# undef CONFIG_SYS_FLASH_PROTECTION
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#endif

#ifdef CONFIG_NAND_ZYNQ
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_MTD_DEVICE
#endif

/* MMC */
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ	52000000
#endif

#ifdef CONFIG_USB_EHCI_ZYNQ
# define CONFIG_EHCI_IS_TDI

# define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x600000
# define DFU_DEFAULT_POLL_TIMEOUT	300
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_THOR_DOWNLOAD
# define CONFIG_THOR_RESET_OFF
# define CONFIG_USB_FUNCTION_THOR
# define DFU_ALT_INFO_RAM \
	"dfu_ram_info=" \
	"set dfu_alt_info " \
	"${kernel_image} ram 0x3000000 0x500000\\\\;" \
	"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
	"${ramdisk_image} ram 0x2000000 0x600000\0" \
	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

# if defined(CONFIG_MMC_SDHCI_ZYNQ)
#  define DFU_ALT_INFO_MMC \
	"dfu_mmc_info=" \
	"set dfu_alt_info " \
	"${kernel_image} fat 0 1\\\\;" \
	"${devicetree_image} fat 0 1\\\\;" \
	"${ramdisk_image} fat 0 1\0" \
	"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
	"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"

#  define DFU_ALT_INFO	\
	DFU_ALT_INFO_RAM \
	DFU_ALT_INFO_MMC
# else
#  define DFU_ALT_INFO	\
	DFU_ALT_INFO_RAM
# endif
#endif

#if !defined(DFU_ALT_INFO)
# define DFU_ALT_INFO
#endif

#if defined(CONFIG_MMC_SDHCI_ZYNQ) || defined(CONFIG_ZYNQ_USB)
# define CONFIG_SUPPORT_VFAT
# define CONFIG_FAT_WRITE
#endif

#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
#define CONFIG_SYS_I2C_ZYNQ
#endif

/* I2C */
#if defined(CONFIG_SYS_I2C_ZYNQ)
# define CONFIG_SYS_I2C
# define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
# define CONFIG_SYS_I2C_ZYNQ_SLAVE		0
#endif

/* EEPROM */
#ifdef CONFIG_ZYNQ_EEPROM
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
# define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
# define CONFIG_SYS_EEPROM_SIZE			1024 /* Bytes */
#endif

/* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE			(128 << 10)

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Environment */
#ifndef CONFIG_ENV_IS_NOWHERE
# ifdef CONFIG_MTD_NOR_FLASH
/* Environment in NOR flash */
#  define CONFIG_ENV_IS_IN_FLASH
# elif defined(CONFIG_ZYNQ_QSPI)
/* Environment in Serial Flash */
#  define CONFIG_ENV_IS_IN_SPI_FLASH
# elif !defined(CONFIG_MTD_NOR_FLASH)
#  define CONFIG_ENV_IS_NOWHERE
# endif

# define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
# define CONFIG_ENV_OFFSET		0xE0000
#endif

/* enable preboot to be loaded before CONFIG_BOOTDELAY */
#define CONFIG_PREBOOT

/* Default environment */
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"fit_image=fit.itb\0"		\
	"load_addr=0x2000000\0"		\
	"fit_size=0x800000\0"		\
	"flash_off=0x100000\0"		\
	"nor_flash_off=0xE2100000\0"	\
	"fdt_high=0x20000000\0"		\
	"initrd_high=0x20000000\0"	\
	"loadbootenv_addr=0x2000000\0" \
	"bootenv=uEnv.txt\0" \
	"bootenv_dev=mmc\0" \
	"loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
	"importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
		"env import -t ${loadbootenv_addr} $filesize\0" \
	"bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
	"setbootenv=if env run bootenv_existence_test; then " \
			"if env run loadbootenv; then " \
				"env run importbootenv; " \
			"fi; " \
		"fi; \0" \
	"sd_loadbootenv=set bootenv_dev mmc && " \
			"run setbootenv \0" \
	"usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
	"preboot=if test $modeboot = sdboot; then " \
			"run sd_loadbootenv; " \
			"echo Checking if uenvcmd is set ...; " \
			"if test -n $uenvcmd; then " \
				"echo Running uenvcmd ...; " \
				"run uenvcmd; " \
			"fi; " \
		"fi; \0" \
	"norboot=echo Copying FIT from NOR flash to RAM... && " \
		"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
		"bootm ${load_addr}\0" \
	"sdboot=echo Copying FIT from SD to RAM... && " \
		"load mmc 0 ${load_addr} ${fit_image} && " \
		"bootm ${load_addr}\0" \
	"jtagboot=echo TFTPing FIT to RAM... && " \
		"tftpboot ${load_addr} ${fit_image} && " \
		"bootm ${load_addr}\0" \
	"usbboot=if usb start; then " \
			"echo Copying FIT from USB to RAM... && " \
			"load usb 0 ${load_addr} ${fit_image} && " \
			"bootm ${load_addr}; fi\0" \
		DFU_ALT_INFO
#endif

#define CONFIG_BOOTCOMMAND		"run $modeboot"
#define CONFIG_SYS_LOAD_ADDR		0 /* default? */

/* Miscellaneous configurable options */

#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
#define CONFIG_SYS_CBSIZE		256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)

#ifndef CONFIG_NR_DRAM_BANKS
# define CONFIG_NR_DRAM_BANKS		1
#endif

#define CONFIG_SYS_MEMTEST_START	0
#define CONFIG_SYS_MEMTEST_END		0x1000

#define CONFIG_SYS_MALLOC_LEN		0x1400000

#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)

/* Enable the PL to be downloaded */
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_ZYNQPL
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_FPGA_LOADP
#define CONFIG_CMD_FPGA_LOADBP
#define CONFIG_CMD_FPGA_LOADFS

/* FIT support */
#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */

/* FDT support */
#define CONFIG_DISPLAY_BOARDINFO_LATE

/* Extend size of kernel image for uncompression */
#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)

/* Boot FreeBSD/vxWorks from an ELF image */
#define CONFIG_SYS_MMC_MAX_DEVICE	1

#define CONFIG_SYS_LDSCRIPT  "arch/arm/mach-zynq/u-boot.lds"

/* Commands */

/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK

#define CONFIG_SPL_LDSCRIPT	"arch/arm/mach-zynq/u-boot-spl.lds"

/* MMC support */
#ifdef CONFIG_MMC_SDHCI_ZYNQ
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
#endif

/* Disable dcache for SPL just for sure */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_FPGA
#endif

/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR	0x10000000

#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"system.dtb"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"

/* Not using MMC raw mode - just for compilation purpose */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0

/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
#define CONFIG_SYS_SPI_ARGS_OFFS	0x200000
#define CONFIG_SYS_SPI_ARGS_SIZE	0x80000
#define CONFIG_SYS_SPI_KERNEL_OFFS	(CONFIG_SYS_SPI_ARGS_OFFS + \
					CONFIG_SYS_SPI_ARGS_SIZE)
#endif

/* for booting directly linux */

/* SP location before relocation, must use scratch RAM */
#define CONFIG_SPL_TEXT_BASE	0x0

/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
#define CONFIG_SPL_MAX_SIZE	0x30000

/* The highest 64k OCM address */
#define OCM_HIGH_ADDR	0xffff0000

/* On the top of OCM space */
#define CONFIG_SYS_SPL_MALLOC_START	OCM_HIGH_ADDR
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x2000

/*
 * SPL stack position - and stack goes down
 * 0xfffffe00 is used for putting wfi loop.
 * Set it up as limit for now.
 */
#define CONFIG_SPL_STACK	0xfffffe00

/* BSS setup */
#define CONFIG_SPL_BSS_START_ADDR	0x100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x100000

#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE

#endif /* __CONFIG_ZYNQ_COMMON_H */
Commit	Line	Data
f22651cf MS	1	/*
f22651cf MS	2	* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
06fe8dae JT	3	* (C) Copyright 2013 Xilinx, Inc.
	4	*
	5	* Common configuration options for all Zynq boards.
f22651cf	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
f22651cf MS	8	*/
f22651cf MS	9
06fe8dae JT	10	#ifndef __CONFIG_ZYNQ_COMMON_H
06fe8dae JT	11	#define __CONFIG_ZYNQ_COMMON_H
f22651cf	12
f22651cf	13	/* CPU clock */
53e49f74 JT	14	#ifndef CONFIG_CPU_FREQ_HZ
	15	# define CONFIG_CPU_FREQ_HZ 800000000
	16	#endif
f22651cf	17
8cfac504	18	/* Cache options */
8cfac504 JT	19	#define CONFIG_SYS_L2CACHE_OFF
	20	#ifndef CONFIG_SYS_L2CACHE_OFF
	21	# define CONFIG_SYS_L2_PL310
	22	# define CONFIG_SYS_PL310_BASE 0xf8f02000
	23	#endif
	24
a2ec7fb9 MS	25	#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
	26	#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR
	27	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	28	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
	29
53e49f74	30	/* Serial drivers */
f22651cf MS	31	/* The following table includes the supported baudrates */
	32	#define CONFIG_SYS_BAUDRATE_TABLE \
	33	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	34
636ac181 MS	35	#define CONFIG_ARM_DCC
636ac181 MS	36	#define CONFIG_ZYNQ_SERIAL
53e49f74	37
f22651cf	38	/* Ethernet driver */
596e5782	39	#if defined(CONFIG_ZYNQ_GEM)
88fcfb1c JT	40	# define CONFIG_MII
88fcfb1c JT	41	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
88fcfb1c	42	# define CONFIG_PHY_MARVELL
9ec2cf00	43	# define CONFIG_PHY_REALTEK
217185b3	44	# define CONFIG_PHY_XILINX
dd1c351f MS	45	# define CONFIG_BOOTP_BOOTPATH
	46	# define CONFIG_BOOTP_GATEWAY
	47	# define CONFIG_BOOTP_HOSTNAME
	48	# define CONFIG_BOOTP_MAY_FAIL
88fcfb1c	49	#endif
f22651cf	50
53e49f74 JT	51	/* SPI */
53e49f74 JT	52	#ifdef CONFIG_ZYNQ_SPI
53e49f74 JT	53	#endif
53e49f74 JT	54
a241d4ec JT	55	/* QSPI */
	56	#ifdef CONFIG_ZYNQ_QSPI
	57	# define CONFIG_SF_DEFAULT_SPEED 30000000
232a8e4e	58	# define CONFIG_SPI_FLASH_ISSI
a241d4ec JT	59	#endif
a241d4ec JT	60
fe5eddbf	61	/* NOR */
e856bdcf	62	#ifdef CONFIG_MTD_NOR_FLASH
fe5eddbf JT	63	# define CONFIG_SYS_FLASH_BASE 0xE2000000
	64	# define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
	65	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	66	# define CONFIG_SYS_MAX_FLASH_SECT 512
	67	# define CONFIG_SYS_FLASH_ERASE_TOUT 1000
	68	# define CONFIG_SYS_FLASH_WRITE_TOUT 5000
	69	# define CONFIG_FLASH_SHOW_PROGRESS 10
	70	# define CONFIG_SYS_FLASH_CFI
	71	# undef CONFIG_SYS_FLASH_EMPTY_INFO
	72	# define CONFIG_FLASH_CFI_DRIVER
	73	# undef CONFIG_SYS_FLASH_PROTECTION
	74	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	75	#endif
	76
ba8adb26 SDPP	77	#ifdef CONFIG_NAND_ZYNQ
	78	#define CONFIG_CMD_NAND_LOCK_UNLOCK
	79	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	80	#define CONFIG_SYS_NAND_ONFI_DETECTION
	81	#define CONFIG_MTD_DEVICE
	82	#endif
	83
293eb33f	84	/* MMC */
08aa0334	85	#if defined(CONFIG_MMC_SDHCI_ZYNQ)
f3bd7280	86	# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
293eb33f MS	87	#endif
293eb33f MS	88
2cdc778b	89	#ifdef CONFIG_USB_EHCI_ZYNQ
c6024c8e	90	# define CONFIG_EHCI_IS_TDI
87f3dbdf	91
87f3dbdf SDPP	92	# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
87f3dbdf SDPP	93	# define DFU_DEFAULT_POLL_TIMEOUT 300
87f3dbdf	94	# define CONFIG_USB_CABLE_CHECK
c4fa5114	95	# define CONFIG_CMD_THOR_DOWNLOAD
1e8d3830	96	# define CONFIG_THOR_RESET_OFF
01acd6ab	97	# define CONFIG_USB_FUNCTION_THOR
87f3dbdf SDPP	98	# define DFU_ALT_INFO_RAM \
	99	"dfu_ram_info=" \
	100	"set dfu_alt_info " \
	101	"${kernel_image} ram 0x3000000 0x500000\\\\;" \
	102	"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
	103	"${ramdisk_image} ram 0x2000000 0x600000\0" \
c4fa5114 SDPP	104	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
c4fa5114 SDPP	105	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
87f3dbdf	106
08aa0334	107	# if defined(CONFIG_MMC_SDHCI_ZYNQ)
87f3dbdf SDPP	108	# define DFU_ALT_INFO_MMC \
	109	"dfu_mmc_info=" \
	110	"set dfu_alt_info " \
	111	"${kernel_image} fat 0 1\\\\;" \
	112	"${devicetree_image} fat 0 1\\\\;" \
	113	"${ramdisk_image} fat 0 1\0" \
c4fa5114 SDPP	114	"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
	115	"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
	116
87f3dbdf SDPP	117	# define DFU_ALT_INFO \
	118	DFU_ALT_INFO_RAM \
	119	DFU_ALT_INFO_MMC
	120	# else
	121	# define DFU_ALT_INFO \
	122	DFU_ALT_INFO_RAM
	123	# endif
	124	#endif
	125
	126	#if !defined(DFU_ALT_INFO)
	127	# define DFU_ALT_INFO
c6024c8e SDPP	128	#endif
c6024c8e SDPP	129
08aa0334	130	#if defined(CONFIG_MMC_SDHCI_ZYNQ) \|\| defined(CONFIG_ZYNQ_USB)
293eb33f	131	# define CONFIG_SUPPORT_VFAT
47b35a51	132	# define CONFIG_FAT_WRITE
293eb33f MS	133	#endif
293eb33f MS	134
1c3f2c72	135	#if defined(CONFIG_ZYNQ_I2C0) \|\| defined(CONFIG_ZYNQ_I2C1)
18948632	136	#define CONFIG_SYS_I2C_ZYNQ
1c3f2c72 SDPP	137	#endif
1c3f2c72 SDPP	138
8934f784	139	/* I2C */
18948632	140	#if defined(CONFIG_SYS_I2C_ZYNQ)
0bdffe71	141	# define CONFIG_SYS_I2C
0bdffe71	142	# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000
18948632	143	# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0
8934f784 MS	144	#endif
8934f784 MS	145
65da1efd JT	146	/* EEPROM */
65da1efd JT	147	#ifdef CONFIG_ZYNQ_EEPROM
65da1efd JT	148	# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	149	# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	150	# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	151	# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	152	# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */
	153	#endif
	154
18eee22f JT	155	/* Total Size of Environment Sector */
	156	#define CONFIG_ENV_SIZE (128 << 10)
	157
b660ca13 JT	158	/* Allow to overwrite serial and ethaddr */
	159	#define CONFIG_ENV_OVERWRITE
	160
f22651cf	161	/* Environment */
ed53e4d6	162	#ifndef CONFIG_ENV_IS_NOWHERE
e856bdcf	163	# ifdef CONFIG_MTD_NOR_FLASH
18c61e95	164	/* Environment in NOR flash */
ed53e4d6	165	# define CONFIG_ENV_IS_IN_FLASH
18c61e95 MS	166	# elif defined(CONFIG_ZYNQ_QSPI)
	167	/* Environment in Serial Flash */
	168	# define CONFIG_ENV_IS_IN_SPI_FLASH
e856bdcf	169	# elif !defined(CONFIG_MTD_NOR_FLASH)
ed53e4d6 JT	170	# define CONFIG_ENV_IS_NOWHERE
	171	# endif
	172
	173	# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
	174	# define CONFIG_ENV_OFFSET 0xE0000
ed53e4d6	175	#endif
e83f61a6	176
4d1ed9c7 MS	177	/* enable preboot to be loaded before CONFIG_BOOTDELAY */
	178	#define CONFIG_PREBOOT
	179
e83f61a6	180	/* Default environment */
b7b3efe7	181	#ifndef CONFIG_EXTRA_ENV_SETTINGS
e83f61a6 JT	182	#define CONFIG_EXTRA_ENV_SETTINGS \
	183	"fit_image=fit.itb\0" \
	184	"load_addr=0x2000000\0" \
	185	"fit_size=0x800000\0" \
	186	"flash_off=0x100000\0" \
	187	"nor_flash_off=0xE2100000\0" \
	188	"fdt_high=0x20000000\0" \
	189	"initrd_high=0x20000000\0" \
4d1ed9c7 MS	190	"loadbootenv_addr=0x2000000\0" \
	191	"bootenv=uEnv.txt\0" \
	192	"bootenv_dev=mmc\0" \
	193	"loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
	194	"importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
	195	"env import -t ${loadbootenv_addr} $filesize\0" \
	196	"bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
	197	"setbootenv=if env run bootenv_existence_test; then " \
	198	"if env run loadbootenv; then " \
	199	"env run importbootenv; " \
	200	"fi; " \
	201	"fi; \0" \
	202	"sd_loadbootenv=set bootenv_dev mmc && " \
	203	"run setbootenv \0" \
	204	"usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
	205	"preboot=if test $modeboot = sdboot; then " \
	206	"run sd_loadbootenv; " \
	207	"echo Checking if uenvcmd is set ...; " \
	208	"if test -n $uenvcmd; then " \
	209	"echo Running uenvcmd ...; " \
	210	"run uenvcmd; " \
	211	"fi; " \
	212	"fi; \0" \
e83f61a6 JT	213	"norboot=echo Copying FIT from NOR flash to RAM... && " \
	214	"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
	215	"bootm ${load_addr}\0" \
	216	"sdboot=echo Copying FIT from SD to RAM... && " \
e9d69c1c	217	"load mmc 0 ${load_addr} ${fit_image} && " \
e83f61a6 JT	218	"bootm ${load_addr}\0" \
e83f61a6 JT	219	"jtagboot=echo TFTPing FIT to RAM... && " \
dfa94058	220	"tftpboot ${load_addr} ${fit_image} && " \
c6024c8e SDPP	221	"bootm ${load_addr}\0" \
	222	"usbboot=if usb start; then " \
	223	"echo Copying FIT from USB to RAM... && " \
e9d69c1c	224	"load usb 0 ${load_addr} ${fit_image} && " \
39bc1a8c	225	"bootm ${load_addr}; fi\0" \
87f3dbdf	226	DFU_ALT_INFO
b7b3efe7	227	#endif
c6024c8e	228
e83f61a6	229	#define CONFIG_BOOTCOMMAND "run $modeboot"
e83f61a6	230	#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
f22651cf	231
36e0e197	232	/* Miscellaneous configurable options */
36e0e197 JT	233
	234	#define CONFIG_CMDLINE_EDITING
	235	#define CONFIG_AUTO_COMPLETE
	236	#define CONFIG_SYS_LONGHELP
6c3e61de	237	#define CONFIG_CLOCKS
841426ad	238	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
36e0e197 JT	239	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
36e0e197 JT	240	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
f22651cf MS	241	sizeof(CONFIG_SYS_PROMPT) + 16)
f22651cf MS	242
758f29d0 MS	243	#ifndef CONFIG_NR_DRAM_BANKS
	244	# define CONFIG_NR_DRAM_BANKS 1
	245	#endif
7cd04192	246
c1584e2a MS	247	#define CONFIG_SYS_MEMTEST_START 0
c1584e2a MS	248	#define CONFIG_SYS_MEMTEST_END 0x1000
7cd04192	249
599807fc	250	#define CONFIG_SYS_MALLOC_LEN 0x1400000
c1584e2a MS	251
	252	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
	253	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
7cd04192 JT	254	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	255	CONFIG_SYS_INIT_RAM_SIZE - \
	256	GENERATED_GBL_DATA_SIZE)
53e49f74 JT	257
	258	/* Enable the PL to be downloaded */
	259	#define CONFIG_FPGA
	260	#define CONFIG_FPGA_XILINX
	261	#define CONFIG_FPGA_ZYNQPL
64e809af	262	#define CONFIG_CMD_FPGA_LOADMK
26ea9ce5 MS	263	#define CONFIG_CMD_FPGA_LOADP
26ea9ce5 MS	264	#define CONFIG_CMD_FPGA_LOADBP
1a897668	265	#define CONFIG_CMD_FPGA_LOADFS
53e49f74	266
53e49f74	267	/* FIT support */
21d29f7f	268	#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
f22651cf	269
f8f36c5d	270	/* FDT support */
f8f36c5d JT	271	#define CONFIG_DISPLAY_BOARDINFO_LATE
f8f36c5d JT	272
ae9f4899	273	/* Extend size of kernel image for uncompression */
3d456eec	274	#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
ae9f4899	275
09ed635b	276	/* Boot FreeBSD/vxWorks from an ELF image */
d82d63cc	277	#define CONFIG_SYS_MMC_MAX_DEVICE 1
09ed635b	278
0107f240	279	#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds"
38716189	280
f22651cf	281	/* Commands */
f22651cf	282
d7e269cf	283	/* SPL part */
d7e269cf MS	284	#define CONFIG_CMD_SPL
d7e269cf MS	285	#define CONFIG_SPL_FRAMEWORK
d7e269cf	286
0107f240	287	#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
d7e269cf	288
d7e269cf	289	/* MMC support */
08aa0334	290	#ifdef CONFIG_MMC_SDHCI_ZYNQ
e2ccdf89	291	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
7f307d93	292	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
0dfbcf02 MY	293	#endif
	294
	295	/* Disable dcache for SPL just for sure */
	296	#ifdef CONFIG_SPL_BUILD
	297	#define CONFIG_SYS_DCACHE_OFF
	298	#undef CONFIG_FPGA
d7e269cf MS	299	#endif
	300
	301	/* Address in RAM where the parameters must be copied by SPL. */
	302	#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
	303
205b4f33 GG	304	#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb"
205b4f33 GG	305	#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
d7e269cf MS	306
	307	/* Not using MMC raw mode - just for compilation purpose */
	308	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0
	309	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0
	310	#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0
	311
	312	/* qspi mode is working fine */
	313	#ifdef CONFIG_ZYNQ_QSPI
d7e269cf	314	#define CONFIG_SPL_SPI_LOAD
d7e269cf	315	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
8e0e01d3 SDPP	316	#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
	317	#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
	318	#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \
	319	CONFIG_SYS_SPI_ARGS_SIZE)
d7e269cf MS	320	#endif
	321
	322	/* for booting directly linux */
d7e269cf MS	323
	324	/* SP location before relocation, must use scratch RAM */
	325	#define CONFIG_SPL_TEXT_BASE 0x0
	326
	327	/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
	328	#define CONFIG_SPL_MAX_SIZE 0x30000
	329
	330	/* The highest 64k OCM address */
	331	#define OCM_HIGH_ADDR 0xffff0000
	332
d7e269cf	333	/* On the top of OCM space */
83b6464d	334	#define CONFIG_SYS_SPL_MALLOC_START OCM_HIGH_ADDR
ec016a17	335	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000
d7e269cf	336
83b6464d MS	337	/*
	338	* SPL stack position - and stack goes down
	339	* 0xfffffe00 is used for putting wfi loop.
	340	* Set it up as limit for now.
	341	*/
	342	#define CONFIG_SPL_STACK 0xfffffe00
	343
d7e269cf MS	344	/* BSS setup */
	345	#define CONFIG_SPL_BSS_START_ADDR 0x100000
	346	#define CONFIG_SPL_BSS_MAX_SIZE 0x100000
	347
	348	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
f22651cf	349
06fe8dae	350	#endif /* __CONFIG_ZYNQ_COMMON_H */