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252b5132 1/* Instruction printing code for the ARM
fd67aa11 2 Copyright (C) 1994-2024 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
1fbaefec
PB		 42/* Cached mapping symbol state. */
43enum map_type
44{
45 MAP_ARM,
46 MAP_THUMB,
47 MAP_DATA
48};
49
b0e28b39
DJ		 50struct arm_private_data
51{
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features;
54
1fbaefec
PB		 55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type;
57
58 /* Tracking symbol table information */
59 int last_mapping_sym;
796d6298
TC		 60
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset;
1fbaefec 63 bfd_vma last_mapping_addr;
b0e28b39
DJ		 64};
65
73cd51e5
AV		 66enum mve_instructions
67{
143275ea
AV		 68 MVE_VPST,
69 MVE_VPT_FP_T1,
70 MVE_VPT_FP_T2,
71 MVE_VPT_VEC_T1,
72 MVE_VPT_VEC_T2,
73 MVE_VPT_VEC_T3,
74 MVE_VPT_VEC_T4,
75 MVE_VPT_VEC_T5,
76 MVE_VPT_VEC_T6,
77 MVE_VCMP_FP_T1,
78 MVE_VCMP_FP_T2,
79 MVE_VCMP_VEC_T1,
80 MVE_VCMP_VEC_T2,
81 MVE_VCMP_VEC_T3,
82 MVE_VCMP_VEC_T4,
83 MVE_VCMP_VEC_T5,
84 MVE_VCMP_VEC_T6,
9743db03
AV		 85 MVE_VDUP,
86 MVE_VEOR,
87 MVE_VFMAS_FP_SCALAR,
88 MVE_VFMA_FP_SCALAR,
89 MVE_VFMA_FP,
90 MVE_VFMS_FP,
91 MVE_VHADD_T1,
92 MVE_VHADD_T2,
93 MVE_VHSUB_T1,
94 MVE_VHSUB_T2,
95 MVE_VRHADD,
04d54ace
AV		 96 MVE_VLD2,
97 MVE_VLD4,
98 MVE_VST2,
99 MVE_VST4,
aef6d006
AV		 100 MVE_VLDRB_T1,
101 MVE_VLDRH_T2,
102 MVE_VLDRB_T5,
103 MVE_VLDRH_T6,
104 MVE_VLDRW_T7,
105 MVE_VSTRB_T1,
106 MVE_VSTRH_T2,
107 MVE_VSTRB_T5,
108 MVE_VSTRH_T6,
109 MVE_VSTRW_T7,
ef1576a1
AV		 110 MVE_VLDRB_GATHER_T1,
111 MVE_VLDRH_GATHER_T2,
112 MVE_VLDRW_GATHER_T3,
113 MVE_VLDRD_GATHER_T4,
114 MVE_VLDRW_GATHER_T5,
115 MVE_VLDRD_GATHER_T6,
116 MVE_VSTRB_SCATTER_T1,
117 MVE_VSTRH_SCATTER_T2,
118 MVE_VSTRW_SCATTER_T3,
119 MVE_VSTRD_SCATTER_T4,
120 MVE_VSTRW_SCATTER_T5,
121 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 122 MVE_VCVT_FP_FIX_VEC,
123 MVE_VCVT_BETWEEN_FP_INT,
124 MVE_VCVT_FP_HALF_FP,
125 MVE_VCVT_FROM_FP_TO_INT,
126 MVE_VRINT_FP,
c507f10b
AV		 127 MVE_VMOV_HFP_TO_GP,
128 MVE_VMOV_GP_TO_VEC_LANE,
129 MVE_VMOV_IMM_TO_VEC,
130 MVE_VMOV_VEC_TO_VEC,
131 MVE_VMOV2_VEC_LANE_TO_GP,
132 MVE_VMOV2_GP_TO_VEC_LANE,
133 MVE_VMOV_VEC_LANE_TO_GP,
134 MVE_VMVN_IMM,
135 MVE_VMVN_REG,
136 MVE_VORR_IMM,
137 MVE_VORR_REG,
138 MVE_VORN,
139 MVE_VBIC_IMM,
140 MVE_VBIC_REG,
141 MVE_VMOVX,
14925797
AV		 142 MVE_VMOVL,
143 MVE_VMOVN,
144 MVE_VMULL_INT,
145 MVE_VMULL_POLY,
146 MVE_VQDMULL_T1,
147 MVE_VQDMULL_T2,
148 MVE_VQMOVN,
149 MVE_VQMOVUN,
d3b63143
AV		 150 MVE_VADDV,
151 MVE_VMLADAV_T1,
152 MVE_VMLADAV_T2,
153 MVE_VMLALDAV,
154 MVE_VMLAS,
155 MVE_VADDLV,
156 MVE_VMLSDAV_T1,
157 MVE_VMLSDAV_T2,
158 MVE_VMLSLDAV,
159 MVE_VRMLALDAVH,
160 MVE_VRMLSLDAVH,
161 MVE_VQDMLADH,
162 MVE_VQRDMLADH,
163 MVE_VQDMLAH,
164 MVE_VQRDMLAH,
165 MVE_VQDMLASH,
166 MVE_VQRDMLASH,
167 MVE_VQDMLSDH,
168 MVE_VQRDMLSDH,
169 MVE_VQDMULH_T1,
170 MVE_VQRDMULH_T2,
171 MVE_VQDMULH_T3,
172 MVE_VQRDMULH_T4,
1c8f2df8
AV		 173 MVE_VDDUP,
174 MVE_VDWDUP,
175 MVE_VIWDUP,
176 MVE_VIDUP,
897b9bbc
AV		 177 MVE_VCADD_FP,
178 MVE_VCADD_VEC,
179 MVE_VHCADD,
180 MVE_VCMLA_FP,
181 MVE_VCMUL_FP,
ed63aa17
AV		 182 MVE_VQRSHL_T1,
183 MVE_VQRSHL_T2,
184 MVE_VQRSHRN,
185 MVE_VQRSHRUN,
186 MVE_VQSHL_T1,
187 MVE_VQSHL_T2,
188 MVE_VQSHLU_T3,
189 MVE_VQSHL_T4,
190 MVE_VQSHRN,
191 MVE_VQSHRUN,
192 MVE_VRSHL_T1,
193 MVE_VRSHL_T2,
194 MVE_VRSHR,
195 MVE_VRSHRN,
196 MVE_VSHL_T1,
197 MVE_VSHL_T2,
198 MVE_VSHL_T3,
199 MVE_VSHLC,
200 MVE_VSHLL_T1,
201 MVE_VSHLL_T2,
202 MVE_VSHR,
203 MVE_VSHRN,
204 MVE_VSLI,
205 MVE_VSRI,
66dcaa5d
AV		 206 MVE_VADC,
207 MVE_VABAV,
208 MVE_VABD_FP,
209 MVE_VABD_VEC,
210 MVE_VABS_FP,
211 MVE_VABS_VEC,
212 MVE_VADD_FP_T1,
213 MVE_VADD_FP_T2,
214 MVE_VADD_VEC_T1,
215 MVE_VADD_VEC_T2,
216 MVE_VSBC,
217 MVE_VSUB_FP_T1,
218 MVE_VSUB_FP_T2,
219 MVE_VSUB_VEC_T1,
220 MVE_VSUB_VEC_T2,
e523f101
AV		 221 MVE_VAND,
222 MVE_VBRSR,
223 MVE_VCLS,
224 MVE_VCLZ,
225 MVE_VCTP,
56858bea
AV		 226 MVE_VMAX,
227 MVE_VMAXA,
228 MVE_VMAXNM_FP,
229 MVE_VMAXNMA_FP,
230 MVE_VMAXNMV_FP,
231 MVE_VMAXNMAV_FP,
232 MVE_VMAXV,
233 MVE_VMAXAV,
234 MVE_VMIN,
235 MVE_VMINA,
236 MVE_VMINNM_FP,
237 MVE_VMINNMA_FP,
238 MVE_VMINNMV_FP,
239 MVE_VMINNMAV_FP,
240 MVE_VMINV,
241 MVE_VMINAV,
242 MVE_VMLA,
f49bb598
AV		 243 MVE_VMUL_FP_T1,
244 MVE_VMUL_FP_T2,
245 MVE_VMUL_VEC_T1,
246 MVE_VMUL_VEC_T2,
247 MVE_VMULH,
248 MVE_VRMULH,
249 MVE_VNEG_FP,
250 MVE_VNEG_VEC,
14b456f2
AV		 251 MVE_VPNOT,
252 MVE_VPSEL,
253 MVE_VQABS,
254 MVE_VQADD_T1,
255 MVE_VQADD_T2,
256 MVE_VQSUB_T1,
257 MVE_VQSUB_T2,
258 MVE_VQNEG,
259 MVE_VREV16,
260 MVE_VREV32,
261 MVE_VREV64,
23d00a41
SD		 262 MVE_LSLL,
263 MVE_LSLLI,
264 MVE_LSRL,
265 MVE_ASRL,
266 MVE_ASRLI,
267 MVE_SQRSHRL,
268 MVE_SQRSHR,
269 MVE_UQRSHL,
270 MVE_UQRSHLL,
271 MVE_UQSHL,
272 MVE_UQSHLL,
273 MVE_URSHRL,
274 MVE_URSHR,
275 MVE_SRSHRL,
276 MVE_SRSHR,
277 MVE_SQSHLL,
278 MVE_SQSHL,
e39c1607
SD		 279 MVE_CINC,
280 MVE_CINV,
281 MVE_CNEG,
282 MVE_CSINC,
283 MVE_CSINV,
284 MVE_CSET,
285 MVE_CSETM,
286 MVE_CSNEG,
287 MVE_CSEL,
73cd51e5
AV		 288 MVE_NONE
289};
290
291enum mve_unpredictable
292{
293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
294 */
143275ea
AV		 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
296 fcB = 1 (vpt). */
297 UNPRED_R13, /* Unpredictable because r13 (sp) or
298 r15 (sp) used. */
9743db03 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 300 UNPRED_Q_GT_4, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
305 and WB bit = 1. */
ef1576a1
AV		 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
307 equal. */
308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
310 same. */
c507f10b
AV		 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
312 size = 1. */
313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
314 size = 2. */
73cd51e5
AV		 315 UNPRED_NONE /* No unpredictable behavior. */
316};
317
318enum mve_undefined
319{
ed63aa17 320 UNDEF_SIZE, /* undefined size. */
bf0b396d 321 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 322 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 323 UNDEF_SIZE_3, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
329 size == 0. */
330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
331 size == 1. */
332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
336 op1 == (0 or 1). */
337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
340 in {0xx1, x0x1}. */
d3b63143 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 342 UNDEF_NONE /* no undefined behavior. */
343};
344
6b5d3a4d
ZW		 345struct opcode32
346{
823d2571
TG		 347 arm_feature_set arch; /* Architecture defining this insn. */
348 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 350 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 351};
352
4934a27c
MM		 353struct cdeopcode32
354{
355 arm_feature_set arch; /* Architecture defining this insn. */
356 uint8_t coproc_shift; /* coproc is this far into op. */
357 uint16_t coproc_mask; /* Length of coproc field in op. */
358 unsigned long value; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask; /* Recognise insn if (op & mask) == value. */
360 const char * assembler; /* How to disassemble this insn. */
361};
362
73cd51e5
AV		 363/* MVE opcodes. */
364
365struct mopcode32
366{
367 arm_feature_set arch; /* Architecture defining this insn. */
368 enum mve_instructions mve_op; /* Specific mve instruction for faster
369 decoding. */
370 unsigned long value; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask; /* Recognise insn if (op & mask) == value. */
372 const char * assembler; /* How to disassemble this insn. */
373};
374
6b0dd094
AV		 375enum isa {
376 ANY,
377 T32,
378 ARM
379};
380
381
382/* Shared (between Arm and Thumb mode) opcode. */
383struct sopcode32
384{
385 enum isa isa; /* Execution mode instruction availability. */
386 arm_feature_set arch; /* Architecture defining this insn. */
387 unsigned long value; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask; /* Recognise insn if (op & mask) == value. */
389 const char * assembler; /* How to disassemble this insn. */
390};
391
6b5d3a4d
ZW		 392struct opcode16
393{
823d2571 394 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 396 const char *assembler; /* How to disassemble this insn. */
397};
b7693d02 398
8f06b2d8 399/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 400
2fbad815 401 %% %
4a5329c6 402
c22aaad1 403 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 404 %b print condition code allowing cp_num == 9
37b37b2d 405 %q print shifter argument
e2efe87d
MGD		 406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
4a5329c6 408 %A print address for ldc/stc/ldf/stf instruction
16980d0b 409 %B print vstm/vldm register list
efd6b359 410 %C print vscclrm register list
4a5329c6 411 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 412 %J print register for VLDR instruction
413 %K print address for VLDR instruction
4a5329c6
ZW		 414 %F print the COUNT field of a LFM/SFM instruction.
415 %P print floating point precision in arithmetic insn
416 %Q print floating point precision in ldf/stf insn
417 %R print floating point rounding mode
418
33399f07 419 %<bitfield>c print as a condition code (for vsel)
4a5329c6 420 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
422 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 423 %<bitfield>d print the bitfield in decimal
16980d0b 424 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 425 %<bitfield>x print the bitfield in hex
426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 427 %<bitfield>f print a floating point constant if >7 else a
428 floating point register
4a5329c6
ZW		 429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
430 %<bitfield>g print as an iWMMXt 64-bit register
431 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 432 %<bitfield>D print as a NEON D register
433 %<bitfield>Q print as a NEON Q register
c28eeff2 434 %<bitfield>V print as a NEON D or Q register
6f1c2142 435 %<bitfield>E print a quarter-float immediate value
4a5329c6 436
16980d0b 437 %y<code> print a single precision VFP reg.
2fbad815 438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 439 %z<code> print a double precision VFP reg
2fbad815 440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 441
16980d0b
JB		 442 %<bitfield>'c print specified char iff bitfield is all ones
443 %<bitfield>`c print specified char iff bitfield is all zeroes
444 %<bitfield>?ab... select from array of values in big endian order
43e65147 445
2fbad815 446 %L print as an iWMMXt N/M width field.
4a5329c6 447 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 448 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 449 versions.
450 %i print 5-bit immediate in bits 8,3..0
451 (print "32" when 0)
fe56b6ce 452 %r print register offset address for wldt/wstr instruction. */
2fbad815 453
21d799b5 454enum opcode_sentinel_enum
05413229
NC		 455{
456 SENTINEL_IWMMXT_START = 1,
457 SENTINEL_IWMMXT_END,
458 SENTINEL_GENERIC_START
459} opcode_sentinels;
460
8cb6e175
AB		 461#define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x"
462#define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x"
463#define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x"
464#define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>"
05413229 465
8f06b2d8 466/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 467
4934a27c
MM		 468/* print_insn_cde recognizes the following format control codes:
469
470 %% %
471
472 %a print 'a' iff bit 28 is 1
473 %p print bits 8-10 as coprocessor
474 %<bitfield>d print as decimal
475 %<bitfield>r print as an ARM register
476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
477 %<bitfield>T print as an ARM register + 1
478 %<bitfield>R as %r but r13 is UNPREDICTABLE
479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
480 %j print immediate taken from bits (16..21,7,0..5)
481 %k print immediate taken from bits (20..21,7,0..5).
482 %l print immediate taken from bits (20..22,7,4..5). */
483
484/* At the moment there is only one valid position for the coprocessor number,
485 and hence that's encoded in the macro below. */
486#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487 { ARCH, 8, 7, VALUE, MASK, ASM }
488static const struct cdeopcode32 cde_opcodes[] =
489{
490 /* Custom Datapath Extension instructions. */
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492 0xee000000, 0xefc00840,
6576bffe 493 "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495 0xee000040, 0xefc00840,
6576bffe 496 "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
4934a27c
MM		 497
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499 0xee400000, 0xefc00840,
6576bffe 500 "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502 0xee400040, 0xefc00840,
6576bffe 503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
4934a27c
MM		 504
505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506 0xee800000, 0xef800840,
6576bffe 507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c
MM		 508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509 0xee800040, 0xef800840,
6576bffe 510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
4934a27c 511
5aae9ae9
MM		 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513 0xec200000, 0xeeb00840,
6576bffe 514 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
5aae9ae9
MM		 515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516 0xec200040, 0xeeb00840,
6576bffe 517 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
5aae9ae9
MM		 518
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520 0xec300000, 0xeeb00840,
6576bffe 521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
5aae9ae9
MM		 522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523 0xec300040, 0xeeb00840,
6576bffe 524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
5aae9ae9
MM		 525
526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527 0xec800000, 0xee800840,
6576bffe 528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
5aae9ae9
MM		 529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530 0xec800040, 0xee800840,
6576bffe 531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
5aae9ae9 532
4934a27c
MM		 533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535};
536
6b0dd094 537static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 538{
2fbad815 539 /* XScale instructions. */
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 541 0x0e200010, 0x0fff0ff0,
6576bffe 542 "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0x0e280010, 0x0fff0ff0,
6576bffe 545 "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 549 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
05413229 552
2fbad815 553 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 554 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 628 0x0e800120, 0x0f800ff0,
629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 643 0x0e8000a0, 0x0f800ff0,
644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
6576bffe 676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 707 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 708 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 709
fe56b6ce 710 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 797
efd6b359
AV		 798 /* Armv8.1-M Mainline instructions. */
799 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
16a1fa25 804 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 805 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 807 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
fe56b6ce 810 /* Register load/store. */
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 843 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 847
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
8cb6e175 855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
16980d0b 856
fe56b6ce 857 /* Data transfer between ARM and NEON registers. */
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
8e79c3df 874 /* Half-precision conversion instructions. */
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 883
fe56b6ce 884 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 886 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
2da2eaf4 887 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 888 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
ba6cd17f 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 890 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 892 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 894 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 896 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 898 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 900 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 902 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
2da2eaf4 903 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 904 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
2da2eaf4 905 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 906 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
ba6cd17f 907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 908 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
ba6cd17f 909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 910 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 914 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
2da2eaf4 915 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
6576bffe 916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
ba6cd17f 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
6576bffe 920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
2da2eaf4 931 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
2da2eaf4 933 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
6576bffe 934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
ba6cd17f 935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
ba6cd17f 937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
6576bffe 952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
6576bffe 954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6576bffe 998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6576bffe 1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 1043
1044 /* Cirrus coprocessor instructions. */
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1046 0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1048 0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1050 0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1052 0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1054 0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1056 0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1058 0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1060 0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1062 0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1064 0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1066 0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1068 0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1070 0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1072 0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1074 0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1076 0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1078 0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1080 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1082 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1084 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1086 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1088 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1090 0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1092 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1094 0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1096 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1098 0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1100 0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1102 0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1104 0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1106 0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1108 0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1110 0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1112 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1114 0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1116 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
6b0dd094 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1118 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
6b0dd094 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1120 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
6b0dd094 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1122 0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1124 0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1126 0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1128 0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1130 0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1132 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1134 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1135 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1136 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1138 0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1140 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1141 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1142 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1143 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1144 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1145 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1146 0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
6b0dd094 1147 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1148 0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
6b0dd094 1149 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1150 0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
6b0dd094 1151 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1152 0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
6b0dd094 1153 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1154 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1155 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1156 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1157 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1158 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1160 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1161 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1162 0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1163 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1164 0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1165 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1166 0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
6b0dd094 1167 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1168 0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
6b0dd094 1169 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1170 0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1171 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1172 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1173 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1174 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1175 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1176 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1177 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1178 0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
6b0dd094 1179 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1180 0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
6b0dd094 1181 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1182 0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1183 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1184 0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1185 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1186 0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
6b0dd094 1187 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1188 0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
6b0dd094 1189 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1190 0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1191 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1192 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1193 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1194 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1195 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1196 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1197 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1198 0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1199 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1200 0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
6b0dd094 1201 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1202 0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1203 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
6576bffe 1204 0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1205 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1206 0x0e000600, 0x0ff00f10,
6576bffe 1207 "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1209 0x0e100600, 0x0ff00f10,
6576bffe 1210 "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1211 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1212 0x0e200600, 0x0ff00f10,
6576bffe 1213 "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
6b0dd094 1214 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1215 0x0e300600, 0x0ff00f10,
6576bffe 1216 "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
2fbad815 1217
62f3b8c8 1218 /* VFP Fused multiply add instructions. */
6b0dd094 1219 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1220 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1221 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1222 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1223 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1224 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1225 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1226 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1227 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1228 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1229 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1230 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1231 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1232 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1233 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1234 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1235
33399f07 1236 /* FP v5. */
6b0dd094 1237 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1238 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1239 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1240 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1241 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1242 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1243 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1244 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1245 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1246 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1247 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1248 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1249 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1250 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1251 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1252 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1253 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1254 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1255 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1256 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1257 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1258 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1259 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1260 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1261
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1263 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1265 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1267 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1269 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1271 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1273 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
6b0dd094 1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1275 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1277 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
6b0dd094 1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1279 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
6b0dd094 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1281 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
6b0dd094 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
6576bffe 1283 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
c28eeff2 1284
aab2c27d
MM		 1285 /* BFloat16 instructions. */
1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
c604a79a 1289 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1290 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1291 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1292 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
6576bffe 1293 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
c604a79a 1294
dec41383 1295 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1297 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1299 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
6b0dd094 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1301 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1303 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
6b0dd094 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1305 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1307 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
6b0dd094 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1309 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
6b0dd094 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
6576bffe 1311 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
dec41383 1312
b0c11777
RL		 1313 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314 cp_num: bit <11:8> == 0b1001.
1315 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1316 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1317 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1318 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1319 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1320 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1321 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1322 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1323 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
6b0dd094 1324 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1325 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1326 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1327 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
6b0dd094 1328 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1329 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1330 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1331 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1332 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1333 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1334 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1335 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1336 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1337 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1338 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1339 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1340 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1341 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1342 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1343 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1344 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1345 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1346 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1347 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1348 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1349 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1350 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1351 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1352 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1353 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1354 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1355 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1356 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1357 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1359 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1360 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1361 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1362 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1363 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1364 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
6576bffe 1365 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
6b0dd094 1366 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1367 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1368 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1369 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1370 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1371 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1372 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1373 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1374 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1375 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1376 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1377 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1378 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1379 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1380 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1381 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1382 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1383 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1384 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1385 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
49e8a725 1387 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1388 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1389 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
6b0dd094 1391 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1392};
1393
33593eaf
MM		 1394/* Generic coprocessor instructions. These are only matched if a more specific
1395 SIMD or co-processor instruction does not match first. */
1396
1397static const struct sopcode32 generic_coprocessor_opcodes[] =
1398{
1399 /* Generic coprocessor instructions. */
1400 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
6576bffe 1401 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
33593eaf
MM		 1402 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403 0x0c500000, 0x0ff00000,
6576bffe 1404 "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406 0x0e000000, 0x0f000010,
6576bffe 1407 "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1408 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409 0x0e10f010, 0x0f10f010,
6576bffe 1410 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1411 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412 0x0e100010, 0x0f100010,
6576bffe 1413 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1414 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415 0x0e000010, 0x0f100010,
6576bffe 1416 "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf 1417 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1418 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
6576bffe 1420 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1421
1422 /* V6 coprocessor instructions. */
1423 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424 0xfc500000, 0xfff00000,
6576bffe 1425 "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
33593eaf
MM		 1426 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427 0xfc400000, 0xfff00000,
6576bffe 1428 "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
33593eaf
MM		 1429
1430 /* V5 coprocessor instructions. */
1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1432 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf 1433 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
6576bffe 1434 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
33593eaf
MM		 1435 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436 0xfe000000, 0xff000010,
6576bffe 1437 "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439 0xfe000010, 0xff100010,
6576bffe 1440 "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1441 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442 0xfe100010, 0xff100010,
6576bffe 1443 "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
33593eaf
MM		 1444
1445 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446};
1447
16980d0b
JB		 1448/* Neon opcode table: This does not encode the top byte -- that is
1449 checked by the print_insn_neon routine, as it depends on whether we are
1450 doing thumb32 or arm32 disassembly. */
1451
1452/* print_insn_neon recognizes the following format control codes:
1453
1454 %% %
1455
c22aaad1 1456 %c print condition code
e2efe87d
MGD		 1457 %u print condition code (unconditional in ARM mode,
1458 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1459 %A print v{st,ld}[1234] operands
1460 %B print v{st,ld}[1234] any one operands
1461 %C print v{st,ld}[1234] single->all operands
1462 %D print scalar
1463 %E print vmov, vmvn, vorr, vbic encoded constant
1464 %F print vtbl,vtbx register list
1465
1466 %<bitfield>r print as an ARM register
1467 %<bitfield>d print the bitfield in decimal
1468 %<bitfield>e print the 2^N - bitfield in decimal
1469 %<bitfield>D print as a NEON D register
1470 %<bitfield>Q print as a NEON Q register
1471 %<bitfield>R print as a NEON D or Q register
1472 %<bitfield>Sn print byte scaled width limited by n
1473 %<bitfield>Tn print short scaled width limited by n
1474 %<bitfield>Un print long scaled width limited by n
43e65147 1475
16980d0b
JB		 1476 %<bitfield>'c print specified char iff bitfield is all ones
1477 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1478 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1479
1480static const struct opcode32 neon_opcodes[] =
1481{
fe56b6ce 1482 /* Extract. */
823d2571
TG		 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2b00840, 0xffb00850,
6576bffe 1485 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
823d2571
TG		 1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2b00000, 0xffb00810,
6576bffe 1488 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
16980d0b 1489
9743db03
AV		 1490 /* Data transfer between ARM and NEON registers. */
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1492 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1494 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1496 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1498 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1500 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1502 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1503
fe56b6ce 1504 /* Move data element to all lanes. */
823d2571 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1506 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
823d2571 1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1508 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
823d2571 1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1510 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
16980d0b 1511
fe56b6ce 1512 /* Table lookup. */
823d2571
TG		 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
8e79c3df 1518 /* Half-precision conversions. */
823d2571
TG		 1519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1523
1524 /* NEON fused multiply add instructions. */
823d2571 1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1526 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1530 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1533
aab2c27d
MM		 1534 /* BFloat16 instructions. */
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1538 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
aab2c27d
MM		 1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
6576bffe 1546 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
aab2c27d 1547
616ce08e
MM		 1548 /* Matrix Multiply instructions. */
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1558 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
6576bffe 1560 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
616ce08e 1561
fe56b6ce 1562 /* Two registers, miscellaneous. */
823d2571
TG		 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1571 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf3b20300, 0xffb30fd0,
6576bffe 1607 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
823d2571
TG		 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1637 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1639 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1641 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1643 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571 1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1645 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
823d2571
TG		 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1655 0xf3bb0600, 0xffbf0e10,
823d2571 1656 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658 0xf3b70600, 0xffbf0e10,
1659 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1660
fe56b6ce 1661 /* Three registers of the same length. */
823d2571
TG		 1662 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1677 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1681 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1701 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1705 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1709 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1713 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1717 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1721 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1725 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1729 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1733 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1737 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1741 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1745 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1749 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1753 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1757 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1761 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1765 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1769 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2000b00, 0xff800f10,
1780 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2000b10, 0xff800f10,
1783 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf3000b00, 0xff800f10,
1792 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2000000, 0xfe800f10,
1795 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2000010, 0xfe800f10,
1798 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2000100, 0xfe800f10,
1801 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2000200, 0xfe800f10,
1804 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2000210, 0xfe800f10,
1807 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2000300, 0xfe800f10,
1810 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2000310, 0xfe800f10,
1813 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2000400, 0xfe800f10,
1816 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2000410, 0xfe800f10,
1819 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2000500, 0xfe800f10,
1822 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824 0xf2000510, 0xfe800f10,
1825 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2000600, 0xfe800f10,
1828 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf2000610, 0xfe800f10,
1831 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2000700, 0xfe800f10,
1834 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2000710, 0xfe800f10,
1837 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2000910, 0xfe800f10,
1840 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2000a00, 0xfe800f10,
1843 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2000a10, 0xfe800f10,
1846 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848 0xf3000b10, 0xff800f10,
1849 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851 0xf3000c10, 0xff800f10,
1852 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1853
fe56b6ce 1854 /* One register and an immediate value. */
823d2571
TG		 1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1881
fe56b6ce 1882 /* Two registers and a shift amount. */
823d2571 1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1884 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1886 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1888 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1890 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1892 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571
TG		 1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf2880950, 0xfeb80fd0,
6576bffe 1895 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
823d2571 1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1897 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
823d2571 1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1899 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1901 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1903 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1905 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1907 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1909 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1911 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1913 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1915 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571
TG		 1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf2900950, 0xfeb00fd0,
6576bffe 1918 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
823d2571 1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1920 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
823d2571 1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1922 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1924 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1926 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1928 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
823d2571 1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1930 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
823d2571 1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1932 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1934 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1936 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1938 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1940 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1942 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1944 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
823d2571 1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1946 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1948 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1950 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1952 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
823d2571 1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1954 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
823d2571 1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1956 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1958 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1960 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571
TG		 1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2a00950, 0xfea00fd0,
6576bffe 1963 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
823d2571 1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1965 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1967 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1969 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1971 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1973 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1975 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1977 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1979 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
823d2571 1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1981 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
823d2571 1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1983 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1985 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1987 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1989 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571 1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1991 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1993 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1995 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1997 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
823d2571 1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
6576bffe 1999 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
823d2571
TG		 2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2a00e10, 0xfea00e90,
6576bffe 2002 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
cc933301
JW		 2003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004 0xf2a00c10, 0xfea00e90,
6576bffe 2005 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
16980d0b 2006
fe56b6ce 2007 /* Three registers of different lengths. */
823d2571
TG		 2008 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013 0xf2800400, 0xff800f50,
2014 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016 0xf2800600, 0xff800f50,
2017 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019 0xf2800900, 0xff800f50,
2020 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf2800b00, 0xff800f50,
2023 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025 0xf2800d00, 0xff800f50,
2026 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf3800400, 0xff800f50,
2029 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031 0xf3800600, 0xff800f50,
2032 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf2800000, 0xfe800f50,
2035 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037 0xf2800100, 0xfe800f50,
2038 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf2800200, 0xfe800f50,
2041 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043 0xf2800300, 0xfe800f50,
2044 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf2800500, 0xfe800f50,
2047 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049 0xf2800700, 0xfe800f50,
2050 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf2800800, 0xfe800f50,
2053 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055 0xf2800a00, 0xfe800f50,
2056 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf2800c00, 0xfe800f50,
2059 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 2060
fe56b6ce 2061 /* Two registers and a scalar. */
823d2571
TG		 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2065 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2073 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2081 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2093 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2099 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2105 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113 0xf2800240, 0xfe800f50,
2114 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116 0xf2800640, 0xfe800f50,
2117 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119 0xf2800a40, 0xfe800f50,
2120 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122 0xf2800e40, 0xff800f50,
2123 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125 0xf2800f40, 0xff800f50,
2126 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128 0xf3800e40, 0xff800f50,
2129 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131 0xf3800f40, 0xff800f50,
2132 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133 },
16980d0b 2134
fe56b6ce 2135 /* Element and structure load/store. */
823d2571
TG		 2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2176};
2177
73cd51e5
AV		 2178/* mve opcode table. */
2179
2180/* print_insn_mve recognizes the following format control codes:
2181
2182 %% %
2183
ef1576a1
AV		 2184 %a print '+' or '-' or imm offset in vldr[bhwd] and
2185 vstr[bhwd]
9743db03 2186 %c print condition code
aef6d006
AV		 2187 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2188 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2189 %i print MVE predicate(s) for vpt and vpst
23d00a41 2190 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2191 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2192 %m print rounding mode for vcvt and vrint
143275ea 2193 %n print vector comparison code for predicated instruction
bf0b396d 2194 %s print size for various vcvt instructions
143275ea
AV		 2195 %v print vector predicate for instruction in predicated
2196 block
ef1576a1 2197 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2198 %w print writeback mode for MVE v{st,ld}[24]
2199 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2200 %E print vmov, vmvn, vorr, vbic encoded constant
2201 %N print generic index for vmov
14925797 2202 %T print bottom ('b') or top ('t') of source register
d3b63143 2203 %X print exchange field in vmla* instructions
04d54ace 2204
9743db03 2205 %<bitfield>r print as an ARM register
04d54ace 2206 %<bitfield>d print the bitfield in decimal
d3b63143 2207 %<bitfield>A print accumulate or not
e39c1607
SD		 2208 %<bitfield>c print bitfield as a condition code
2209 %<bitfield>C print bitfield as an inverted condition code
143275ea 2210 %<bitfield>Q print as a MVE Q register
c507f10b 2211 %<bitfield>F print as a MVE S register
143275ea
AV		 2212 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2213 UNPREDICTABLE
23d00a41
SD		 2214
2215 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2216 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2217 %<bitfield>I print carry flag or not
ef1576a1 2218 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2219 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2220 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2221 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2222 %<bitfield>o print rotate value for vcmul
1c8f2df8 2223 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2224 %<bitfield>x print the bitfield in hex.
1c8f2df8 2225 */
73cd51e5
AV		 2226
2227static const struct mopcode32 mve_opcodes[] =
2228{
143275ea
AV		 2229 /* MVE. */
2230
2da2eaf4 2231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2232 MVE_VPST,
2233 0xfe310f4d, 0xffbf1fff,
2234 "vpst%i"
2235 },
2236
2237 /* Floating point VPT T1. */
2da2eaf4 2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2239 MVE_VPT_FP_T1,
2240 0xee310f00, 0xefb10f50,
2241 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Floating point VPT T2. */
2da2eaf4 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2244 MVE_VPT_FP_T2,
2245 0xee310f40, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248 /* Vector VPT T1. */
2da2eaf4 2249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2250 MVE_VPT_VEC_T1,
2251 0xfe010f00, 0xff811f51,
2252 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253 /* Vector VPT T2. */
2da2eaf4 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2255 MVE_VPT_VEC_T2,
2256 0xfe010f01, 0xff811f51,
2257 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T3. */
2da2eaf4 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2260 MVE_VPT_VEC_T3,
2261 0xfe011f00, 0xff811f50,
2262 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T4. */
2da2eaf4 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2265 MVE_VPT_VEC_T4,
2266 0xfe010f40, 0xff811f70,
2267 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268 /* Vector VPT T5. */
2da2eaf4 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2270 MVE_VPT_VEC_T5,
2271 0xfe010f60, 0xff811f70,
2272 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T6. */
2da2eaf4 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2275 MVE_VPT_VEC_T6,
2276 0xfe011f40, 0xff811f50,
2277 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
c507f10b 2279 /* Vector VBIC immediate. */
2da2eaf4 2280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2281 MVE_VBIC_IMM,
2282 0xef800070, 0xefb81070,
2283 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285 /* Vector VBIC register. */
2da2eaf4 2286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2287 MVE_VBIC_REG,
2288 0xef100150, 0xffb11f51,
2289 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
66dcaa5d 2291 /* Vector VABAV. */
2da2eaf4 2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2293 MVE_VABAV,
2294 0xee800f01, 0xefc10f51,
2295 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297 /* Vector VABD floating point. */
2da2eaf4 2298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2299 MVE_VABD_FP,
2300 0xff200d40, 0xffa11f51,
2301 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303 /* Vector VABD. */
2da2eaf4 2304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2305 MVE_VABD_VEC,
2306 0xef000740, 0xef811f51,
2307 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309 /* Vector VABS floating point. */
2da2eaf4 2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2311 MVE_VABS_FP,
2312 0xFFB10740, 0xFFB31FD1,
2313 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314 /* Vector VABS. */
2da2eaf4 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2316 MVE_VABS_VEC,
2317 0xffb10340, 0xffb31fd1,
2318 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320 /* Vector VADD floating point T1. */
2da2eaf4 2321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2322 MVE_VADD_FP_T1,
2323 0xef000d40, 0xffa11f51,
2324 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325 /* Vector VADD floating point T2. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2327 MVE_VADD_FP_T2,
2328 0xee300f40, 0xefb11f70,
2329 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330 /* Vector VADD T1. */
2da2eaf4 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2332 MVE_VADD_VEC_T1,
2333 0xef000840, 0xff811f51,
2334 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335 /* Vector VADD T2. */
2da2eaf4 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2337 MVE_VADD_VEC_T2,
2338 0xee010f40, 0xff811f70,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
d3b63143 2341 /* Vector VADDLV. */
2da2eaf4 2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2343 MVE_VADDLV,
2344 0xee890f00, 0xef8f1fd1,
2345 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347 /* Vector VADDV. */
2da2eaf4 2348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2349 MVE_VADDV,
2350 0xeef10f00, 0xeff31fd1,
2351 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
66dcaa5d 2353 /* Vector VADC. */
2da2eaf4 2354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2355 MVE_VADC,
2356 0xee300f00, 0xffb10f51,
2357 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
e523f101 2359 /* Vector VAND. */
2da2eaf4 2360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2361 MVE_VAND,
2362 0xef000150, 0xffb11f51,
2363 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365 /* Vector VBRSR register. */
2da2eaf4 2366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2367 MVE_VBRSR,
2368 0xfe011e60, 0xff811f70,
2369 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
897b9bbc 2371 /* Vector VCADD floating point. */
2da2eaf4 2372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2373 MVE_VCADD_FP,
2374 0xfc800840, 0xfea11f51,
6576bffe 2375 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
897b9bbc
AV		 2376
2377 /* Vector VCADD. */
2da2eaf4 2378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2379 MVE_VCADD_VEC,
2380 0xfe000f00, 0xff810f51,
6576bffe 2381 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2382
e523f101 2383 /* Vector VCLS. */
2da2eaf4 2384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2385 MVE_VCLS,
2386 0xffb00440, 0xffb31fd1,
2387 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389 /* Vector VCLZ. */
2da2eaf4 2390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2391 MVE_VCLZ,
2392 0xffb004c0, 0xffb31fd1,
2393 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
897b9bbc 2395 /* Vector VCMLA. */
2da2eaf4 2396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2397 MVE_VCMLA_FP,
2398 0xfc200840, 0xfe211f51,
6576bffe 2399 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
897b9bbc 2400
143275ea 2401 /* Vector VCMP floating point T1. */
2da2eaf4 2402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2403 MVE_VCMP_FP_T1,
2404 0xee310f00, 0xeff1ef50,
2405 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407 /* Vector VCMP floating point T2. */
2da2eaf4 2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2409 MVE_VCMP_FP_T2,
2410 0xee310f40, 0xeff1ef50,
2411 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413 /* Vector VCMP T1. */
2da2eaf4 2414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2415 MVE_VCMP_VEC_T1,
2416 0xfe010f00, 0xffc1ff51,
2417 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418 /* Vector VCMP T2. */
2da2eaf4 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2420 MVE_VCMP_VEC_T2,
2421 0xfe010f01, 0xffc1ff51,
2422 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T3. */
2da2eaf4 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2425 MVE_VCMP_VEC_T3,
2426 0xfe011f00, 0xffc1ff50,
2427 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T4. */
2da2eaf4 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2430 MVE_VCMP_VEC_T4,
2431 0xfe010f40, 0xffc1ff70,
2432 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433 /* Vector VCMP T5. */
2da2eaf4 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2435 MVE_VCMP_VEC_T5,
2436 0xfe010f60, 0xffc1ff70,
2437 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T6. */
2da2eaf4 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2440 MVE_VCMP_VEC_T6,
2441 0xfe011f40, 0xffc1ff50,
2442 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
9743db03 2444 /* Vector VDUP. */
2da2eaf4 2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2446 MVE_VDUP,
2447 0xeea00b10, 0xffb10f5f,
2448 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450 /* Vector VEOR. */
2da2eaf4 2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2452 MVE_VEOR,
2453 0xff000150, 0xffd11f51,
2454 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456 /* Vector VFMA, vector * scalar. */
2da2eaf4 2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2458 MVE_VFMA_FP_SCALAR,
2459 0xee310e40, 0xefb11f70,
2460 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462 /* Vector VFMA floating point. */
2da2eaf4 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2464 MVE_VFMA_FP,
2465 0xef000c50, 0xffa11f51,
2466 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468 /* Vector VFMS floating point. */
2da2eaf4 2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2470 MVE_VFMS_FP,
2471 0xef200c50, 0xffa11f51,
2472 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2476 MVE_VFMAS_FP_SCALAR,
2477 0xee311e40, 0xefb11f70,
2478 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480 /* Vector VHADD T1. */
2da2eaf4 2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2482 MVE_VHADD_T1,
2483 0xef000040, 0xef811f51,
2484 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486 /* Vector VHADD T2. */
2da2eaf4 2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2488 MVE_VHADD_T2,
2489 0xee000f40, 0xef811f70,
2490 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492 /* Vector VHSUB T1. */
2da2eaf4 2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2494 MVE_VHSUB_T1,
2495 0xef000240, 0xef811f51,
2496 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498 /* Vector VHSUB T2. */
2da2eaf4 2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2500 MVE_VHSUB_T2,
2501 0xee001f40, 0xef811f70,
2502 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
897b9bbc 2504 /* Vector VCMUL. */
2da2eaf4 2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2506 MVE_VCMUL_FP,
2507 0xee300e00, 0xefb10f50,
6576bffe 2508 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
897b9bbc 2509
e523f101 2510 /* Vector VCTP. */
2da2eaf4 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2512 MVE_VCTP,
2513 0xf000e801, 0xffc0ffff,
2514 "vctp%v.%20-21s\t%16-19r"},
2515
9743db03 2516 /* Vector VDUP. */
2da2eaf4 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2518 MVE_VDUP,
2519 0xeea00b10, 0xffb10f5f,
2520 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522 /* Vector VRHADD. */
2da2eaf4 2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2524 MVE_VRHADD,
2525 0xef000140, 0xef811f51,
2526 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
bf0b396d 2528 /* Vector VCVT. */
2da2eaf4 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2530 MVE_VCVT_FP_FIX_VEC,
2531 0xef800c50, 0xef801cd1,
6576bffe 2532 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
bf0b396d
AV		 2533
2534 /* Vector VCVT. */
2da2eaf4 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2536 MVE_VCVT_BETWEEN_FP_INT,
2537 0xffb30640, 0xffb31e51,
2538 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2542 MVE_VCVT_FP_HALF_FP,
2543 0xee3f0e01, 0xefbf1fd1,
2544 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2548 MVE_VCVT_FP_HALF_FP,
2549 0xee3f1e01, 0xefbf1fd1,
2550 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552 /* Vector VCVT. */
2da2eaf4 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2554 MVE_VCVT_FROM_FP_TO_INT,
2555 0xffb30040, 0xffb31c51,
2556 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
1c8f2df8 2558 /* Vector VDDUP. */
2da2eaf4 2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2560 MVE_VDDUP,
2561 0xee011f6e, 0xff811f7e,
6576bffe 2562 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8
AV		 2563
2564 /* Vector VDWDUP. */
2da2eaf4 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2566 MVE_VDWDUP,
2567 0xee011f60, 0xff811f70,
6576bffe 2568 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8 2569
897b9bbc 2570 /* Vector VHCADD. */
2da2eaf4 2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2572 MVE_VHCADD,
2573 0xee000f00, 0xff810f51,
6576bffe 2574 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
897b9bbc 2575
1c8f2df8 2576 /* Vector VIWDUP. */
2da2eaf4 2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2578 MVE_VIWDUP,
2579 0xee010f60, 0xff811f70,
6576bffe 2580 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
1c8f2df8
AV		 2581
2582 /* Vector VIDUP. */
2da2eaf4 2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2584 MVE_VIDUP,
2585 0xee010f6e, 0xff811f7e,
6576bffe 2586 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
1c8f2df8 2587
04d54ace 2588 /* Vector VLD2. */
2da2eaf4 2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2590 MVE_VLD2,
2591 0xfc901e00, 0xff901e5f,
2592 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594 /* Vector VLD4. */
2da2eaf4 2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2596 MVE_VLD4,
2597 0xfc901e01, 0xff901e1f,
2598 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
ef1576a1 2600 /* Vector VLDRB gather load. */
2da2eaf4 2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2602 MVE_VLDRB_GATHER_T1,
2603 0xec900e00, 0xefb01e50,
2604 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606 /* Vector VLDRH gather load. */
2da2eaf4 2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2608 MVE_VLDRH_GATHER_T2,
2609 0xec900e10, 0xefb01e50,
2610 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612 /* Vector VLDRW gather load. */
2da2eaf4 2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2614 MVE_VLDRW_GATHER_T3,
2615 0xfc900f40, 0xffb01fd0,
2616 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618 /* Vector VLDRD gather load. */
2da2eaf4 2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2620 MVE_VLDRD_GATHER_T4,
2621 0xec900fd0, 0xefb01fd0,
2622 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624 /* Vector VLDRW gather load. */
2da2eaf4 2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2626 MVE_VLDRW_GATHER_T5,
2627 0xfd101e00, 0xff111f00,
6576bffe 2628 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 2629
2630 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2632 MVE_VLDRD_GATHER_T6,
2633 0xfd101f00, 0xff111f00,
6576bffe 2634 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 2635
aef6d006 2636 /* Vector VLDRB. */
2da2eaf4 2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2638 MVE_VLDRB_T1,
2639 0xec100e00, 0xee581e00,
2640 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642 /* Vector VLDRH. */
2da2eaf4 2643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2644 MVE_VLDRH_T2,
2645 0xec180e00, 0xee581e00,
2646 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2650 MVE_VLDRB_T5,
2651 0xec101e00, 0xfe101f80,
2652 "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2656 MVE_VLDRH_T6,
2657 0xec101e80, 0xfe101f80,
2658 "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2662 MVE_VLDRW_T7,
2663 0xec101f00, 0xfe101f80,
2664 "vldrw%v.u32\t%13-15,22Q, %d"},
2665
56858bea 2666 /* Vector VMAX. */
2da2eaf4 2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2668 MVE_VMAX,
2669 0xef000640, 0xef811f51,
2670 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672 /* Vector VMAXA. */
2da2eaf4 2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2674 MVE_VMAXA,
2675 0xee330e81, 0xffb31fd1,
2676 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678 /* Vector VMAXNM floating point. */
2da2eaf4 2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2680 MVE_VMAXNM_FP,
2681 0xff000f50, 0xffa11f51,
2682 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684 /* Vector VMAXNMA floating point. */
2da2eaf4 2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2686 MVE_VMAXNMA_FP,
2687 0xee3f0e81, 0xefbf1fd1,
2688 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690 /* Vector VMAXNMV floating point. */
2da2eaf4 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2692 MVE_VMAXNMV_FP,
2693 0xeeee0f00, 0xefff0fd1,
2694 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696 /* Vector VMAXNMAV floating point. */
2da2eaf4 2697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2698 MVE_VMAXNMAV_FP,
2699 0xeeec0f00, 0xefff0fd1,
2700 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702 /* Vector VMAXV. */
2da2eaf4 2703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2704 MVE_VMAXV,
2705 0xeee20f00, 0xeff30fd1,
2706 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708 /* Vector VMAXAV. */
2da2eaf4 2709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2710 MVE_VMAXAV,
2711 0xeee00f00, 0xfff30fd1,
2712 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714 /* Vector VMIN. */
2da2eaf4 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2716 MVE_VMIN,
2717 0xef000650, 0xef811f51,
2718 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720 /* Vector VMINA. */
2da2eaf4 2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2722 MVE_VMINA,
2723 0xee331e81, 0xffb31fd1,
2724 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726 /* Vector VMINNM floating point. */
2da2eaf4 2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2728 MVE_VMINNM_FP,
2729 0xff200f50, 0xffa11f51,
2730 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732 /* Vector VMINNMA floating point. */
2da2eaf4 2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2734 MVE_VMINNMA_FP,
2735 0xee3f1e81, 0xefbf1fd1,
2736 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738 /* Vector VMINNMV floating point. */
2da2eaf4 2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2740 MVE_VMINNMV_FP,
2741 0xeeee0f80, 0xefff0fd1,
2742 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744 /* Vector VMINNMAV floating point. */
2da2eaf4 2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2746 MVE_VMINNMAV_FP,
2747 0xeeec0f80, 0xefff0fd1,
2748 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750 /* Vector VMINV. */
2da2eaf4 2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2752 MVE_VMINV,
2753 0xeee20f80, 0xeff30fd1,
2754 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756 /* Vector VMINAV. */
2da2eaf4 2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2758 MVE_VMINAV,
2759 0xeee00f80, 0xfff30fd1,
2760 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762 /* Vector VMLA. */
2da2eaf4 2763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2764 MVE_VMLA,
2765 0xee010e40, 0xef811f70,
3e562e4b 2766 "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
56858bea 2767
d3b63143
AV		 2768 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2769 opcode aliasing. */
2da2eaf4 2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2771 MVE_VMLALDAV,
2772 0xee801e00, 0xef801f51,
2773 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2da2eaf4 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2776 MVE_VMLALDAV,
2777 0xee800e00, 0xef801f51,
2778 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2782 MVE_VMLADAV_T1,
2783 0xeef00e00, 0xeff01f51,
2784 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2788 MVE_VMLADAV_T2,
2789 0xeef00f00, 0xeff11f51,
2790 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792 /* Vector VMLADAV T1 variant. */
2da2eaf4 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2794 MVE_VMLADAV_T1,
2795 0xeef01e00, 0xeff01f51,
2796 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798 /* Vector VMLADAV T2 variant. */
2da2eaf4 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2800 MVE_VMLADAV_T2,
2801 0xeef01f00, 0xeff11f51,
2802 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804 /* Vector VMLAS. */
2da2eaf4 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2806 MVE_VMLAS,
2807 0xee011e40, 0xef811f70,
2808 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2811 opcode aliasing. */
2da2eaf4 2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2813 MVE_VRMLSLDAVH,
2814 0xfe800e01, 0xff810f51,
2815 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2818 opcdoe aliasing. */
2da2eaf4 2819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2820 MVE_VMLSLDAV,
2821 0xee800e01, 0xff800f51,
2822 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2826 MVE_VMLSDAV_T1,
2827 0xeef00e01, 0xfff00f51,
2828 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2832 MVE_VMLSDAV_T2,
2833 0xfef00e01, 0xfff10f51,
2834 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
c507f10b 2836 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2838 MVE_VMOV_HFP_TO_GP,
2839 0xee000910, 0xfff00f7f,
2840 "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2844 MVE_VMOV_HFP_TO_GP,
2845 0xee100910, 0xfff00f7f,
2846 "vmov.f16\t%12-15r, %7,16-19F"},
2847
2da2eaf4 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2849 MVE_VMOV_GP_TO_VEC_LANE,
2850 0xee000b10, 0xff900f1f,
6576bffe 2851 "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
c507f10b
AV		 2852
2853 /* Vector VORR immediate to vector.
2854 NOTE: MVE_VORR_IMM must appear in the table
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2857 MVE_VORR_IMM,
2858 0xef800050, 0xefb810f0,
2859 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
ed63aa17
AV		 2861 /* Vector VQSHL T2 Variant.
2862 NOTE: MVE_VQSHL_T2 must appear in the table before
2863 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2865 MVE_VQSHL_T2,
2866 0xef800750, 0xef801fd1,
6576bffe 2867 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2868
2869 /* Vector VQSHLU T3 Variant
2870 NOTE: MVE_VQSHL_T2 must appear in the table before
2871 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2872
2da2eaf4 2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2874 MVE_VQSHLU_T3,
2875 0xff800650, 0xff801fd1,
6576bffe 2876 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2877
2878 /* Vector VRSHR
2879 NOTE: MVE_VRSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2882 MVE_VRSHR,
2883 0xef800250, 0xef801fd1,
6576bffe 2884 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2885
2886 /* Vector VSHL.
2887 NOTE: MVE_VSHL must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2890 MVE_VSHL_T1,
2891 0xef800550, 0xff801fd1,
6576bffe 2892 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2893
2894 /* Vector VSHR
2895 NOTE: MVE_VSHR must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2898 MVE_VSHR,
2899 0xef800050, 0xef801fd1,
6576bffe 2900 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2901
2902 /* Vector VSLI
2903 NOTE: MVE_VSLI must appear in the table before
2904 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2906 MVE_VSLI,
2907 0xff800550, 0xff801fd1,
6576bffe 2908 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 2909
2910 /* Vector VSRI
2911 NOTE: MVE_VSRI must appear in the table before
2912 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2914 MVE_VSRI,
2915 0xff800450, 0xff801fd1,
6576bffe 2916 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2917
c507f10b 2918 /* Vector VMOV immediate to vector,
ce760a76 2919 undefinded for cmode == 1111 */
2da2eaf4 2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2921 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923 /* Vector VMOV immediate to vector,
2924 cmode == 1101 */
2da2eaf4 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2926 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2928
2929 /* Vector VMOV immediate to vector. */
2da2eaf4 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2931 MVE_VMOV_IMM_TO_VEC,
2932 0xef800050, 0xefb810d0,
2933 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2937 MVE_VMOV2_VEC_LANE_TO_GP,
2938 0xec000f00, 0xffb01ff0,
6576bffe 2939 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
c507f10b
AV		 2940
2941 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2943 MVE_VMOV2_VEC_LANE_TO_GP,
2944 0xec000f10, 0xffb01ff0,
6576bffe 2945 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
c507f10b
AV		 2946
2947 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2949 MVE_VMOV2_GP_TO_VEC_LANE,
2950 0xec100f00, 0xffb01ff0,
6576bffe 2951 "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
c507f10b
AV		 2952
2953 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2955 MVE_VMOV2_GP_TO_VEC_LANE,
2956 0xec100f10, 0xffb01ff0,
6576bffe 2957 "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
c507f10b
AV		 2958
2959 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2961 MVE_VMOV_VEC_LANE_TO_GP,
2962 0xee100b10, 0xff100f1f,
6576bffe 2963 "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
c507f10b 2964
ed63aa17
AV		 2965 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2966 to instruction opcode aliasing. */
2da2eaf4 2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2968 MVE_VSHLL_T1,
2969 0xeea00f40, 0xefa00fd1,
6576bffe 2970 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 2971
14925797 2972 /* Vector VMOVL long. */
2da2eaf4 2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2974 MVE_VMOVL,
2975 0xeea00f40, 0xefa70fd1,
2976 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978 /* Vector VMOV and narrow. */
2da2eaf4 2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2980 MVE_VMOVN,
2981 0xfe310e81, 0xffb30fd1,
2982 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
c507f10b 2984 /* Floating point move extract. */
2da2eaf4 2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2986 MVE_VMOVX,
2987 0xfeb00a40, 0xffbf0fd0,
2988 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
f49bb598 2990 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2992 MVE_VMUL_FP_T1,
2993 0xff000d50, 0xffa11f51,
2994 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 2997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2998 MVE_VMUL_FP_T2,
2999 0xee310e60, 0xefb11f70,
3000 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002 /* Vector VMUL T1 variant. */
2da2eaf4 3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3004 MVE_VMUL_VEC_T1,
3005 0xef000950, 0xff811f51,
3006 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008 /* Vector VMUL T2 variant. */
2da2eaf4 3009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3010 MVE_VMUL_VEC_T2,
3011 0xee011e60, 0xff811f70,
3012 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014 /* Vector VMULH. */
2da2eaf4 3015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3016 MVE_VMULH,
3017 0xee010e01, 0xef811f51,
3018 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020 /* Vector VRMULH. */
2da2eaf4 3021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3022 MVE_VRMULH,
3023 0xee011e01, 0xef811f51,
3024 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
14925797 3026 /* Vector VMULL integer. */
2da2eaf4 3027 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3028 MVE_VMULL_INT,
3029 0xee010e00, 0xef810f51,
3030 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032 /* Vector VMULL polynomial. */
2da2eaf4 3033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3034 MVE_VMULL_POLY,
3035 0xee310e00, 0xefb10f51,
3036 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
c507f10b 3038 /* Vector VMVN immediate to vector. */
2da2eaf4 3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3040 MVE_VMVN_IMM,
3041 0xef800070, 0xefb810f0,
3042 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044 /* Vector VMVN register. */
2da2eaf4 3045 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3046 MVE_VMVN_REG,
3047 0xffb005c0, 0xffbf1fd1,
3048 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
f49bb598 3050 /* Vector VNEG floating point. */
2da2eaf4 3051 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3052 MVE_VNEG_FP,
3053 0xffb107c0, 0xffb31fd1,
3054 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056 /* Vector VNEG. */
2da2eaf4 3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3058 MVE_VNEG_VEC,
3059 0xffb103c0, 0xffb31fd1,
3060 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
c507f10b 3062 /* Vector VORN, vector bitwise or not. */
2da2eaf4 3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3064 MVE_VORN,
3065 0xef300150, 0xffb11f51,
3066 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068 /* Vector VORR register. */
2da2eaf4 3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3070 MVE_VORR_REG,
3071 0xef200150, 0xffb11f51,
3072 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
c4a23bf8
SP		 3074 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077 array. */
3078
2da2eaf4 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 3080 MVE_VMOV_VEC_TO_VEC,
3081 0xef200150, 0xffb11f51,
3082 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
14925797 3084 /* Vector VQDMULL T1 variant. */
2da2eaf4 3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3086 MVE_VQDMULL_T1,
3087 0xee300f01, 0xefb10f51,
3088 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
14b456f2 3090 /* Vector VPNOT. */
2da2eaf4 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3092 MVE_VPNOT,
3093 0xfe310f4d, 0xffffffff,
3094 "vpnot%v"},
3095
3096 /* Vector VPSEL. */
2da2eaf4 3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3098 MVE_VPSEL,
3099 0xfe310f01, 0xffb11f51,
3100 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102 /* Vector VQABS. */
2da2eaf4 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3104 MVE_VQABS,
3105 0xffb00740, 0xffb31fd1,
3106 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108 /* Vector VQADD T1 variant. */
2da2eaf4 3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3110 MVE_VQADD_T1,
3111 0xef000050, 0xef811f51,
3112 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114 /* Vector VQADD T2 variant. */
2da2eaf4 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3116 MVE_VQADD_T2,
3117 0xee000f60, 0xef811f70,
3118 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
14925797 3120 /* Vector VQDMULL T2 variant. */
2da2eaf4 3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3122 MVE_VQDMULL_T2,
3123 0xee300f60, 0xefb10f70,
3124 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126 /* Vector VQMOVN. */
2da2eaf4 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3128 MVE_VQMOVN,
3129 0xee330e01, 0xefb30fd1,
3130 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132 /* Vector VQMOVUN. */
2da2eaf4 3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3134 MVE_VQMOVUN,
3135 0xee310e81, 0xffb30fd1,
3136 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
d3b63143 3138 /* Vector VQDMLADH. */
2da2eaf4 3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3140 MVE_VQDMLADH,
3141 0xee000e00, 0xff810f51,
3142 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144 /* Vector VQRDMLADH. */
2da2eaf4 3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3146 MVE_VQRDMLADH,
3147 0xee000e01, 0xff810f51,
3148 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150 /* Vector VQDMLAH. */
2da2eaf4 3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3152 MVE_VQDMLAH,
23d188c7 3153 0xee000e60, 0xff811f70,
d3b63143
AV		 3154 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156 /* Vector VQRDMLAH. */
2da2eaf4 3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3158 MVE_VQRDMLAH,
23d188c7 3159 0xee000e40, 0xff811f70,
d3b63143
AV		 3160 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162 /* Vector VQDMLASH. */
2da2eaf4 3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3164 MVE_VQDMLASH,
23d188c7 3165 0xee001e60, 0xff811f70,
d3b63143
AV		 3166 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168 /* Vector VQRDMLASH. */
2da2eaf4 3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3170 MVE_VQRDMLASH,
23d188c7 3171 0xee001e40, 0xff811f70,
d3b63143
AV		 3172 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174 /* Vector VQDMLSDH. */
2da2eaf4 3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3176 MVE_VQDMLSDH,
3177 0xfe000e00, 0xff810f51,
3178 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180 /* Vector VQRDMLSDH. */
2da2eaf4 3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3182 MVE_VQRDMLSDH,
3183 0xfe000e01, 0xff810f51,
3184 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186 /* Vector VQDMULH T1 variant. */
2da2eaf4 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3188 MVE_VQDMULH_T1,
3189 0xef000b40, 0xff811f51,
3190 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3194 MVE_VQRDMULH_T2,
3195 0xff000b40, 0xff811f51,
3196 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198 /* Vector VQDMULH T3 variant. */
2da2eaf4 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3200 MVE_VQDMULH_T3,
3201 0xee010e60, 0xff811f70,
3202 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3206 MVE_VQRDMULH_T4,
3207 0xfe010e60, 0xff811f70,
3208 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
14b456f2 3210 /* Vector VQNEG. */
2da2eaf4 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3212 MVE_VQNEG,
3213 0xffb007c0, 0xffb31fd1,
3214 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
ed63aa17 3216 /* Vector VQRSHL T1 variant. */
2da2eaf4 3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3218 MVE_VQRSHL_T1,
3219 0xef000550, 0xef811f51,
3220 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222 /* Vector VQRSHL T2 variant. */
2da2eaf4 3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3224 MVE_VQRSHL_T2,
3225 0xee331ee0, 0xefb31ff0,
3226 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228 /* Vector VQRSHRN. */
2da2eaf4 3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3230 MVE_VQRSHRN,
3231 0xee800f41, 0xefa00fd1,
6576bffe 3232 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3233
3234 /* Vector VQRSHRUN. */
2da2eaf4 3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3236 MVE_VQRSHRUN,
3237 0xfe800fc0, 0xffa00fd1,
6576bffe 3238 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3239
3240 /* Vector VQSHL T1 Variant. */
2da2eaf4 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3242 MVE_VQSHL_T1,
3243 0xee311ee0, 0xefb31ff0,
3244 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246 /* Vector VQSHL T4 Variant. */
2da2eaf4 3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3248 MVE_VQSHL_T4,
3249 0xef000450, 0xef811f51,
3250 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252 /* Vector VQSHRN. */
2da2eaf4 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3254 MVE_VQSHRN,
3255 0xee800f40, 0xefa00fd1,
6576bffe 3256 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17
AV		 3257
3258 /* Vector VQSHRUN. */
2da2eaf4 3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3260 MVE_VQSHRUN,
3261 0xee800fc0, 0xffa00fd1,
6576bffe 3262 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3263
14b456f2 3264 /* Vector VQSUB T1 Variant. */
2da2eaf4 3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3266 MVE_VQSUB_T1,
3267 0xef000250, 0xef811f51,
3268 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270 /* Vector VQSUB T2 Variant. */
2da2eaf4 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3272 MVE_VQSUB_T2,
3273 0xee001f60, 0xef811f70,
3274 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276 /* Vector VREV16. */
2da2eaf4 3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3278 MVE_VREV16,
3279 0xffb00140, 0xffb31fd1,
3280 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282 /* Vector VREV32. */
2da2eaf4 3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3284 MVE_VREV32,
3285 0xffb000c0, 0xffb31fd1,
3286 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288 /* Vector VREV64. */
2da2eaf4 3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3290 MVE_VREV64,
3291 0xffb00040, 0xffb31fd1,
3292 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
bf0b396d 3294 /* Vector VRINT floating point. */
2da2eaf4 3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3296 MVE_VRINT_FP,
3297 0xffb20440, 0xffb31c51,
3298 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
d3b63143 3300 /* Vector VRMLALDAVH. */
2da2eaf4 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3302 MVE_VRMLALDAVH,
3303 0xee800f00, 0xef811f51,
3304 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306 /* Vector VRMLALDAVH. */
2da2eaf4 3307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3308 MVE_VRMLALDAVH,
3309 0xee801f00, 0xef811f51,
3310 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
ed63aa17 3312 /* Vector VRSHL T1 Variant. */
2da2eaf4 3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3314 MVE_VRSHL_T1,
3315 0xef000540, 0xef811f51,
3316 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318 /* Vector VRSHL T2 Variant. */
2da2eaf4 3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3320 MVE_VRSHL_T2,
3321 0xee331e60, 0xefb31ff0,
3322 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324 /* Vector VRSHRN. */
2da2eaf4 3325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3326 MVE_VRSHRN,
3327 0xfe800fc1, 0xffa00fd1,
6576bffe 3328 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3329
66dcaa5d 3330 /* Vector VSBC. */
2da2eaf4 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3332 MVE_VSBC,
3333 0xfe300f00, 0xffb10f51,
3334 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
ed63aa17 3336 /* Vector VSHL T2 Variant. */
2da2eaf4 3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3338 MVE_VSHL_T2,
3339 0xee311e60, 0xefb31ff0,
3340 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342 /* Vector VSHL T3 Variant. */
2da2eaf4 3343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3344 MVE_VSHL_T3,
3345 0xef000440, 0xef811f51,
3346 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348 /* Vector VSHLC. */
2da2eaf4 3349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3350 MVE_VSHLC,
3351 0xeea00fc0, 0xffa01ff0,
6576bffe 3352 "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
ed63aa17
AV		 3353
3354 /* Vector VSHLL T2 Variant. */
2da2eaf4 3355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3356 MVE_VSHLL_T2,
3357 0xee310e01, 0xefb30fd1,
6576bffe 3358 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
ed63aa17
AV		 3359
3360 /* Vector VSHRN. */
2da2eaf4 3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3362 MVE_VSHRN,
3363 0xee800fc1, 0xffa00fd1,
6576bffe 3364 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
ed63aa17 3365
04d54ace 3366 /* Vector VST2 no writeback. */
2da2eaf4 3367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3368 MVE_VST2,
3369 0xfc801e00, 0xffb01e5f,
3370 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372 /* Vector VST2 writeback. */
2da2eaf4 3373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3374 MVE_VST2,
3375 0xfca01e00, 0xffb01e5f,
3376 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378 /* Vector VST4 no writeback. */
2da2eaf4 3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3380 MVE_VST4,
3381 0xfc801e01, 0xffb01e1f,
3382 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384 /* Vector VST4 writeback. */
2da2eaf4 3385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3386 MVE_VST4,
3387 0xfca01e01, 0xffb01e1f,
3388 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
ef1576a1 3390 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3392 MVE_VSTRB_SCATTER_T1,
3393 0xec800e00, 0xffb01e50,
3394 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3398 MVE_VSTRH_SCATTER_T2,
3399 0xec800e10, 0xffb01e50,
3400 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3404 MVE_VSTRW_SCATTER_T3,
3405 0xec800e40, 0xffb01e50,
3406 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3410 MVE_VSTRD_SCATTER_T4,
3411 0xec800fd0, 0xffb01fd0,
3412 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3416 MVE_VSTRW_SCATTER_T5,
3417 0xfd001e00, 0xff111f00,
6576bffe 3418 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1
AV		 3419
3420 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3422 MVE_VSTRD_SCATTER_T6,
3423 0xfd001f00, 0xff111f00,
6576bffe 3424 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
ef1576a1 3425
aef6d006 3426 /* Vector VSTRB. */
2da2eaf4 3427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3428 MVE_VSTRB_T1,
3429 0xec000e00, 0xfe581e00,
3430 "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432 /* Vector VSTRH. */
2da2eaf4 3433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3434 MVE_VSTRH_T2,
3435 0xec080e00, 0xfe581e00,
3436 "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438 /* Vector VSTRB variant T5. */
2da2eaf4 3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3440 MVE_VSTRB_T5,
3441 0xec001e00, 0xfe101f80,
3442 "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444 /* Vector VSTRH variant T6. */
2da2eaf4 3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3446 MVE_VSTRH_T6,
3447 0xec001e80, 0xfe101f80,
3448 "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450 /* Vector VSTRW variant T7. */
2da2eaf4 3451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3452 MVE_VSTRW_T7,
3453 0xec001f00, 0xfe101f80,
3454 "vstrw%v.32\t%13-15,22Q, %d"},
3455
66dcaa5d 3456 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3458 MVE_VSUB_FP_T1,
3459 0xef200d40, 0xffa11f51,
3460 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3464 MVE_VSUB_FP_T2,
3465 0xee301f40, 0xefb11f70,
3466 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468 /* Vector VSUB T1 variant. */
2da2eaf4 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3470 MVE_VSUB_VEC_T1,
3471 0xff000840, 0xff811f51,
3472 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474 /* Vector VSUB T2 variant. */
2da2eaf4 3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3476 MVE_VSUB_VEC_T2,
3477 0xee011f40, 0xff811f70,
3478 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
2da2eaf4 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3481 MVE_ASRLI,
3482 0xea50012f, 0xfff1813f,
3483 "asrl%c\t%17-19l, %9-11h, %j"},
3484
2da2eaf4 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3486 MVE_ASRL,
3487 0xea50012d, 0xfff101ff,
3488 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
2da2eaf4 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3491 MVE_LSLLI,
3492 0xea50010f, 0xfff1813f,
3493 "lsll%c\t%17-19l, %9-11h, %j"},
3494
2da2eaf4 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3496 MVE_LSLL,
3497 0xea50010d, 0xfff101ff,
3498 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
2da2eaf4 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3501 MVE_LSRL,
3502 0xea50011f, 0xfff1813f,
3503 "lsrl%c\t%17-19l, %9-11h, %j"},
3504
2da2eaf4 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3506 MVE_SQRSHRL,
08132bdd
SP		 3507 0xea51012d, 0xfff1017f,
3508 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3509
2da2eaf4 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3511 MVE_SQRSHR,
3512 0xea500f2d, 0xfff00fff,
3513 "sqrshr%c\t%16-19S, %12-15S"},
3514
2da2eaf4 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3516 MVE_SQSHLL,
3517 0xea51013f, 0xfff1813f,
3518 "sqshll%c\t%17-19l, %9-11h, %j"},
3519
2da2eaf4 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3521 MVE_SQSHL,
3522 0xea500f3f, 0xfff08f3f,
3523 "sqshl%c\t%16-19S, %j"},
3524
2da2eaf4 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3526 MVE_SRSHRL,
3527 0xea51012f, 0xfff1813f,
3528 "srshrl%c\t%17-19l, %9-11h, %j"},
3529
2da2eaf4 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3531 MVE_SRSHR,
3532 0xea500f2f, 0xfff08f3f,
3533 "srshr%c\t%16-19S, %j"},
3534
2da2eaf4 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3536 MVE_UQRSHLL,
08132bdd
SP		 3537 0xea51010d, 0xfff1017f,
3538 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3539
2da2eaf4 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3541 MVE_UQRSHL,
3542 0xea500f0d, 0xfff00fff,
3543 "uqrshl%c\t%16-19S, %12-15S"},
3544
2da2eaf4 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3546 MVE_UQSHLL,
3547 0xea51010f, 0xfff1813f,
3548 "uqshll%c\t%17-19l, %9-11h, %j"},
3549
2da2eaf4 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3551 MVE_UQSHL,
3552 0xea500f0f, 0xfff08f3f,
3553 "uqshl%c\t%16-19S, %j"},
3554
2da2eaf4 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3556 MVE_URSHRL,
3557 0xea51011f, 0xfff1813f,
3558 "urshrl%c\t%17-19l, %9-11h, %j"},
3559
2da2eaf4 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3561 MVE_URSHR,
3562 0xea500f1f, 0xfff08f3f,
3563 "urshr%c\t%16-19S, %j"},
3564
e39c1607
SD		 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566 MVE_CSINC,
3567 0xea509000, 0xfff0f000,
3568 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571 MVE_CSINV,
3572 0xea50a000, 0xfff0f000,
3573 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576 MVE_CSET,
3577 0xea5f900f, 0xfffff00f,
3578 "cset\t%8-11S, %4-7C"},
3579
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581 MVE_CSETM,
3582 0xea5fa00f, 0xfffff00f,
3583 "csetm\t%8-11S, %4-7C"},
3584
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586 MVE_CSEL,
3587 0xea508000, 0xfff0f000,
3588 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591 MVE_CSNEG,
3592 0xea50b000, 0xfff0f000,
3593 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596 MVE_CINC,
3597 0xea509000, 0xfff0f000,
3598 "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601 MVE_CINV,
3602 0xea50a000, 0xfff0f000,
3603 "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606 MVE_CNEG,
3607 0xea50b000, 0xfff0f000,
3608 "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
143275ea
AV		 3610 {ARM_FEATURE_CORE_LOW (0),
3611 MVE_NONE,
3612 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3613};
3614
8f06b2d8
PB		 3615/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3616 ordered: they must be searched linearly from the top to obtain a correct
3617 match. */
3618
3619/* print_insn_arm recognizes the following format control codes:
3620
3621 %% %
3622
3623 %a print address for ldr/str instruction
3624 %s print address for ldr/str halfword/signextend instruction
c1e26897 3625 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3626 %b print branch destination
3627 %c print condition code (always bits 28-31)
3628 %m print register mask for ldm/stm instruction
3629 %o print operand2 (immediate or register + shift)
3630 %p print 'p' iff bits 12-15 are 15
3631 %t print 't' iff bit 21 set and bit 24 clear
3632 %B print arm BLX(1) destination
3633 %C print the PSR sub type.
62b3e311
PB		 3634 %U print barrier type.
3635 %P print address for pli instruction.
8f06b2d8
PB		 3636
3637 %<bitfield>r print as an ARM register
9eb6c0f1 3638 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3639 %<bitfield>R as %r but r15 is UNPREDICTABLE
3640 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3642 %<bitfield>d print the bitfield in decimal
43e65147 3643 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3644 %<bitfield>x print the bitfield in hex
3645 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3646
16980d0b
JB		 3647 %<bitfield>'c print specified char iff bitfield is all ones
3648 %<bitfield>`c print specified char iff bitfield is all zeroes
3649 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3650
8f06b2d8
PB		 3651 %e print arm SMI operand (bits 0..7,8..19).
3652 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3653 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3654 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3655
8f06b2d8
PB		 3656static const struct opcode32 arm_opcodes[] =
3657{
3658 /* ARM instructions. */
823d2571 3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 3660 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
823d2571 3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3662 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
823d2571
TG		 3663
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673 0x00800090, 0x0fa000f0,
3674 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676 0x00a00090, 0x0fa000f0,
3677 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3678
105bde57 3679 /* V8.2 RAS extension instructions. */
4d1464f2 3680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3681 0xe320f010, 0xffffffff, "esb"},
3682
26417f19
AC		 3683 /* V8-R instructions. */
3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685 0xf57ff04c, 0xffffffff, "dfb"},
3686
53c4b28b 3687 /* V8 instructions. */
823d2571
TG		 3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3690 /* Defined in V8 but is in NOP space so available to all arch. */
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
6576bffe 3692 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
4ed7ed8d 3693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3694 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3696 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3701 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3702 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3703 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3704 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3705 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3706 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3707 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3708 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3709 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3710 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3711 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3712 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3713 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3714 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3716 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3717 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3718 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3719 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3720 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3721 /* CRC32 instructions. */
8b301fbb 3722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3723 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3725 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3727 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3729 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3731 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3733 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3734
ddfded2f
MW		 3735 /* Privileged Access Never extension instructions. */
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
6576bffe 3737 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
ddfded2f 3738
90ec0d68 3739 /* Virtualization Extension instructions. */
823d2571
TG		 3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3742
eea54501 3743 /* Integer Divide Extension instructions. */
823d2571
TG		 3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3748
60e5ef9f 3749 /* MP Extension instructions. */
823d2571 3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3751
c597cc3d
SD		 3752 /* Speculation Barriers. */
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
62b3e311 3757 /* V7 instructions. */
823d2571 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
6576bffe 3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a 3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 3766 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
62b3e311 3767
c19d1205 3768 /* ARM V6T2 instructions. */
823d2571
TG		 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
ff8646ee 3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3784 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3786 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 3790 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
885fc257 3791
f4c65163 3792 /* ARM Security extension instructions. */
823d2571
TG		 3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3795
8f06b2d8 3796 /* ARM V6K instructions. */
823d2571
TG		 3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798 0xf57ff01f, 0xffffffff, "clrex"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3811
7fadb25d
SD		 3812 /* ARMv8.5-A instructions. */
3813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
8f06b2d8 3815 /* ARM V6K NOP hints. */
823d2571
TG		 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817 0x0320f001, 0x0fffffff, "yield%c"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819 0x0320f002, 0x0fffffff, "wfe%c"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821 0x0320f003, 0x0fffffff, "wfi%c"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823 0x0320f004, 0x0fffffff, "sev%c"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
6576bffe 3825 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
c19d1205 3826
fe56b6ce 3827 /* ARM V6 instructions. */
823d2571 3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3829 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
823d2571 3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3831 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3833 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
823d2571 3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4fc808ae 3835 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
823d2571 3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3837 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
823d2571
TG		 3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3841 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3843 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
823d2571 3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3845 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3847 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
823d2571
TG		 3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3931 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3933 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3935 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3939 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3941 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3943 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3947 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3949 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3951 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3955 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3957 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3959 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3963 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3965 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3967 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3971 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3973 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3975 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3979 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3981 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3983 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3987 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3989 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3991 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3995 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3997 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 3999 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4003 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4005 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4007 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4011 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4013 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4015 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
823d2571
TG		 4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4019 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
823d2571 4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4021 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
823d2571 4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4023 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
823d2571
TG		 4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4027 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
823d2571
TG		 4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4047 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4049 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
823d2571 4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4051 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4053 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4055 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
823d2571
TG		 4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4065 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
823d2571 4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4067 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
823d2571 4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4069 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
823d2571 4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
6576bffe 4071 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
c19d1205 4072
8f06b2d8 4073 /* V5J instruction. */
823d2571
TG		 4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 4076
8f06b2d8 4077 /* V5 Instructions. */
823d2571
TG		 4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079 0xe1200070, 0xfff000f0,
6576bffe 4080 "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
823d2571
TG		 4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082 0xfa000000, 0xfe000000, "blx\t%B"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088 /* V5E "El Segundo" Instructions. */
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094 0xf450f000, 0xfc70f000, "pld\t%a"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4140
8f06b2d8 4141 /* ARM Instructions. */
823d2571 4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 4143 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
823d2571
TG		 4144
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4247 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4249 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4251 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4252
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
8cb6e175 4306 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
823d2571
TG		 4307
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349 0x092d0000, 0x0fff0000, "push%c\t%m"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4398
4399 /* The rest. */
4ab90a7a 4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
6576bffe 4401 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404 {ARM_FEATURE_CORE_LOW (0),
4405 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4406};
4407
4408/* print_insn_thumb16 recognizes the following format control codes:
4409
4410 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4411 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4412 %<bitfield>I print bitfield as a signed decimal
4413 (top bit of range being the sign bit)
4414 %N print Thumb register mask (with LR)
4415 %O print Thumb register mask (with PC)
4416 %M print Thumb register mask
4417 %b print CZB's 6-bit unsigned branch destination
4418 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4419 %c print the condition code
4420 %C print the condition code, or "s" if not conditional
4421 %x print warning if conditional an not at end of IT block"
8cb6e175 4422 %X print "\t@ unpredictable <IT:code>" if conditional
c22aaad1 4423 %I print IT instruction suffix and operands
4547cb56 4424 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4425 %<bitfield>r print bitfield as an ARM register
4426 %<bitfield>d print bitfield as a decimal
4427 %<bitfield>H print (bitfield * 2) as a decimal
4428 %<bitfield>W print (bitfield * 4) as a decimal
4429 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4430 %<bitfield>B print Thumb branch destination (signed displacement)
4431 %<bitfield>c print bitfield as a condition code
4432 %<bitnum>'c print specified char iff bit is one
4433 %<bitnum>?ab print a if bit is one else print b. */
4434
4435static const struct opcode16 thumb_opcodes[] =
4436{
4437 /* Thumb instructions. */
4438
16a1fa25
TP		 4439 /* ARMv8-M Security Extensions instructions. */
4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4442
53c4b28b 4443 /* ARM V8 instructions. */
823d2571
TG		 4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
6576bffe 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
53c4b28b 4447
8f06b2d8 4448 /* ARM V6K no-argument instructions. */
823d2571
TG		 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4455
4456 /* ARM V6T2 instructions. */
ff8646ee
TP		 4457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4462
4463 /* ARM V6. */
6576bffe
AB		 4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
823d2571
TG		 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
6576bffe 4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
823d2571
TG		 4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4475
4476 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4479 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4482 /* ARM V4T ISA (Thumb v1). */
823d2571 4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
8cb6e175 4484 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
8f06b2d8 4485 /* Format 4. */
823d2571
TG		 4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4502 /* format 13 */
6576bffe
AB		 4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
8f06b2d8 4505 /* format 5 */
823d2571
TG		 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4510 /* format 14 */
823d2571
TG		 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4513 /* format 2 */
823d2571
TG		 4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4519 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
823d2571 4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4521 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
8f06b2d8 4522 /* format 8 */
823d2571
TG		 4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4529 /* format 7 */
823d2571
TG		 4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4534 /* format 1 */
823d2571
TG		 4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4537 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
823d2571
TG		 4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4540 /* format 3 */
6576bffe
AB		 4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
8f06b2d8 4545 /* format 6 */
823d2571
TG		 4546 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548 0x4800, 0xF800,
6576bffe 4549 "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
8f06b2d8 4550 /* format 9 */
823d2571 4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4552 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4554 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
823d2571 4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4556 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
823d2571 4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4558 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
8f06b2d8 4559 /* format 10 */
823d2571 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4561 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
823d2571 4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4563 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
8f06b2d8 4564 /* format 11 */
823d2571 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4566 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
823d2571 4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4568 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
8f06b2d8 4569 /* format 12 */
823d2571 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4571 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
823d2571 4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
6576bffe 4573 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
8f06b2d8 4574 /* format 15 */
823d2571
TG		 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4577 /* format 17 */
823d2571 4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4579 /* format 16 */
6576bffe 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
823d2571
TG		 4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4583 /* format 18 */
823d2571 4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4585
4586 /* The E800 .. FFFF range is unconditionally redirected to the
4587 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588 are processed via that table. Thus, we can never encounter a
4589 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4592};
4593
4594/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595 We adopt the convention that hw1 is the high 16 bits of .value and
4596 .mask, hw2 the low 16 bits.
4597
4598 print_insn_thumb32 recognizes the following format control codes:
4599
4600 %% %
4601
4602 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603 %M print a modified 12-bit immediate (same location)
4604 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4606 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4607 %S print a possibly-shifted Rm
4608
32a94698 4609 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4610 %a print the address of a plain load/store
4611 %w print the width and signedness of a core load/store
4612 %m print register mask for ldm/stm
4b5a202f 4613 %n print register mask for clrm
8f06b2d8
PB		 4614
4615 %E print the lsb and width fields of a bfc/bfi instruction
4616 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4617 %G print a fallback offset for Branch Future instructions
e5d6e09e 4618 %W print an offset for BF instruction
1caf72a5 4619 %Y print an offset for BFL instruction
1889da70 4620 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4621 %Q print an offset for Low Overhead Loop instructions
4622 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4623 %b print a conditional branch offset
4624 %B print an unconditional branch offset
4625 %s print the shift field of an SSAT instruction
4626 %R print the rotation field of an SXT instruction
62b3e311
PB		 4627 %U print barrier type.
4628 %P print address for pli instruction.
c22aaad1
PB		 4629 %c print the condition code
4630 %x print warning if conditional an not at end of IT block"
8cb6e175 4631 %X print "\t@ unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4632
4633 %<bitfield>d print bitfield in decimal
f0fba320 4634 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4635 %<bitfield>W print bitfield*4 in decimal
4636 %<bitfield>r print bitfield as an ARM register
dd5181d5 4637 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4638 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4639 %<bitfield>c print bitfield as a condition code
4640
16980d0b
JB		 4641 %<bitfield>'c print specified char iff bitfield is all ones
4642 %<bitfield>`c print specified char iff bitfield is all zeroes
4643 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4644
4645 With one exception at the bottom (done because BL and BLX(1) need
4646 to come dead last), this table was machine-sorted first in
4647 decreasing order of number of bits set in the mask, then in
4648 increasing numeric order of mask, then in increasing numeric order
4649 of opcode. This order is not the clearest for a human reader, but
4650 is guaranteed never to catch a special-case bit pattern with a more
4651 general mask, which is important, because this instruction encoding
4652 makes heavy use of special-case bit patterns. */
4653static const struct opcode32 thumb32_opcodes[] =
4654{
3751264c
AC		 4655 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4656 Identification Extension. */
e43ca2cb 4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4658 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
be05908c
AC		 4659 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4660 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
3751264c
AC		 4661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4662 0xf3af800f, 0xffffffff, "bti"},
e07352fa
AC		 4663 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4664 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
ce537a7d 4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4666 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
f1e1d7f3 4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4668 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
5c43020d
AC		 4669 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4670 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
3751264c 4671
4b5a202f
AV		 4672 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4673 instructions. */
60f993ce 4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4675 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677 0xf02fc001, 0xfffff001, "le\t%P"},
4678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4679 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
d052b9b7 4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4681 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
d052b9b7 4682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4683 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4685 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
d052b9b7 4686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4687 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
d052b9b7 4688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4689 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
60f993ce 4690
4389b29a
AV		 4691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4692 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4694 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4696 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4698 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d 4699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
6576bffe 4700 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4389b29a 4701
4b5a202f
AV		 4702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4703 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4704
16a1fa25
TP		 4705 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4708 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4710 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4712 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4713 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4714 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4715
105bde57 4716 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4717 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4718 0xf3af8010, 0xffffffff, "esb"},
4719
53c4b28b 4720 /* V8 instructions. */
823d2571
TG		 4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722 0xf3af8005, 0xffffffff, "sevl%c.w"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4738 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4740 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4742 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4744 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4746 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4748 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4750 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4752 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4753
26417f19
AC		 4754 /* V8-R instructions. */
4755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4756 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4757
dd5181d5 4758 /* CRC32 instructions. */
8b301fbb 4759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4760 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4762 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4764 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4766 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4768 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4769 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4770 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4771
c597cc3d
SD		 4772 /* Speculation Barriers. */
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4776
62b3e311 4777 /* V7 instructions. */
823d2571 4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
6576bffe 4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
823d2571
TG		 4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4786 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4788 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4789
90ec0d68 4790 /* Virtualization Extension instructions. */
823d2571 4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4792 /* We skip ERET as that is SUBS pc, lr, #0. */
4793
60e5ef9f 4794 /* MP Extension instructions. */
823d2571 4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4796
f4c65163 4797 /* Security extension instructions. */
823d2571 4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4799
7fadb25d
SD		 4800 /* ARMv8.5-A instructions. */
4801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4802
8f06b2d8 4803 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4810 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
823d2571
TG		 4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4812
ff8646ee 4813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4814 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4816 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571 4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4818 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
823d2571
TG		 4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4828 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
823d2571
TG		 4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4832 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
823d2571 4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4834 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4836 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
823d2571 4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4838 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
823d2571
TG		 4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4842 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4844 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4846 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571 4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4848 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
823d2571
TG		 4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4862 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4970 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4972 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
823d2571 4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 4974 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
823d2571
TG		 4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 5037 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 5038 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044 0xf810f000, 0xff70f000, "pld%c\t%a"},
5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5060 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5062 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5068 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5070 0xfb100000, 0xfff000c0,
5071 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5073 0xfbc00080, 0xfff000c0,
5074 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5076 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5078 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 5080 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
823d2571 5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
6576bffe 5082 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
823d2571
TG		 5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5084 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5086 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5088 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5089 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5090 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5092 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5100 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5102 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5110 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
6576bffe 5112 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
823d2571
TG		 5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5128 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5130 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5134 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5136 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5140 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5142 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5144 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5146 0xe9400000, 0xff500000,
6576bffe 5147 "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 5148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5149 0xe9500000, 0xff500000,
6576bffe 5150 "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
823d2571
TG		 5151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5152 0xe8600000, 0xff700000,
6576bffe 5153 "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 5154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5155 0xe8700000, 0xff700000,
6576bffe 5156 "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
823d2571
TG		 5157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5158 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5160 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5161
5162 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5164 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5166 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5168 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5170 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5171
8f06b2d8 5172 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5174 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5176 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5177
5178 /* Fallback. */
823d2571
TG		 5179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5180 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5181 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5182};
ff4a8d2b 5183
8f06b2d8
PB		 5184static const char *const arm_conditional[] =
5185{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5186 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5187
5188static const char *const arm_fp_const[] =
5189{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5190
5191static const char *const arm_shift[] =
5192{"lsl", "lsr", "asr", "ror"};
5193
5194typedef struct
5195{
5196 const char *name;
5197 const char *description;
5198 const char *reg_names[16];
5199}
5200arm_regname;
5201
5202static const arm_regname regnames[] =
5203{
65b48a81 5204 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5205 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5206 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5207 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5208 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5209 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5210 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5211 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5212 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5213 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5214 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5215 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5216 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5217 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5218 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5219};
5220
5221static const char *const iwmmxt_wwnames[] =
5222{"b", "h", "w", "d"};
5223
5224static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5225{"b", "bus", "bc", "bss",
5226 "h", "hus", "hc", "hss",
5227 "w", "wus", "wc", "wss",
5228 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5229};
5230
5231static const char *const iwmmxt_regnames[] =
5232{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5233 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5234};
5235
5236static const char *const iwmmxt_cregnames[] =
5237{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5238 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5239};
5240
143275ea
AV		 5241static const char *const vec_condnames[] =
5242{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5243};
5244
5245static const char *const mve_predicatenames[] =
5246{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5247 "eee", "ee", "eet", "e", "ett", "et", "ete"
5248};
5249
5250/* Names for 2-bit size field for mve vector isntructions. */
5251static const char *const mve_vec_sizename[] =
5252 { "8", "16", "32", "64"};
5253
5254/* Indicates whether we are processing a then predicate,
5255 else predicate or none at all. */
5256enum vpt_pred_state
5257{
5258 PRED_NONE,
5259 PRED_THEN,
5260 PRED_ELSE
5261};
5262
5263/* Information used to process a vpt block and subsequent instructions. */
5264struct vpt_block
5265{
5266 /* Are we in a vpt block. */
78933a4a 5267 bool in_vpt_block;
143275ea
AV		 5268
5269 /* Next predicate state if in vpt block. */
5270 enum vpt_pred_state next_pred_state;
5271
5272 /* Mask from vpt/vpst instruction. */
5273 long predicate_mask;
5274
5275 /* Instruction number in vpt block. */
5276 long current_insn_num;
5277
5278 /* Number of instructions in vpt block.. */
5279 long num_pred_insn;
5280};
5281
5282static struct vpt_block vpt_block_state =
5283{
78933a4a 5284 false,
143275ea
AV		 5285 PRED_NONE,
5286 0,
5287 0,
5288 0
5289};
5290
8f06b2d8
PB		 5291/* Default to GCC register name set. */
5292static unsigned int regname_selected = 1;
5293
65b48a81 5294#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5295#define arm_regnames regnames[regname_selected].reg_names
5296
78933a4a 5297static bool force_thumb = false;
4934a27c 5298static uint16_t cde_coprocs = 0;
8f06b2d8 5299
c22aaad1
PB		 5300/* Current IT instruction state. This contains the same state as the IT
5301 bits in the CPSR. */
5302static unsigned int ifthen_state;
5303/* IT state for the next instruction. */
5304static unsigned int ifthen_next_state;
5305/* The address of the insn for which the IT state is valid. */
5306static bfd_vma ifthen_address;
5307#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5308/* Indicates that the current Conditional state is unconditional or outside
5309 an IT block. */
5310#define COND_UNCOND 16
c22aaad1 5311
8f06b2d8
PB		 5312\f
5313/* Functions. */
143275ea
AV		 5314/* Extract the predicate mask for a VPT or VPST instruction.
5315 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5316
5317static long
5318mve_extract_pred_mask (long given)
5319{
5320 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5321}
5322
5323/* Return the number of instructions in a MVE predicate block. */
5324static long
5325num_instructions_vpt_block (long given)
5326{
5327 long mask = mve_extract_pred_mask (given);
5328 if (mask == 0)
5329 return 0;
5330
5331 if (mask == 8)
5332 return 1;
5333
5334 if ((mask & 7) == 4)
5335 return 2;
5336
5337 if ((mask & 3) == 2)
5338 return 3;
5339
5340 if ((mask & 1) == 1)
5341 return 4;
5342
5343 return 0;
5344}
5345
5346static void
5347mark_outside_vpt_block (void)
5348{
78933a4a 5349 vpt_block_state.in_vpt_block = false;
143275ea
AV		 5350 vpt_block_state.next_pred_state = PRED_NONE;
5351 vpt_block_state.predicate_mask = 0;
5352 vpt_block_state.current_insn_num = 0;
5353 vpt_block_state.num_pred_insn = 0;
5354}
5355
5356static void
5357mark_inside_vpt_block (long given)
5358{
78933a4a 5359 vpt_block_state.in_vpt_block = true;
143275ea
AV		 5360 vpt_block_state.next_pred_state = PRED_THEN;
5361 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5362 vpt_block_state.current_insn_num = 0;
5363 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5364 assert (vpt_block_state.num_pred_insn >= 1);
5365}
5366
5367static enum vpt_pred_state
5368invert_next_predicate_state (enum vpt_pred_state astate)
5369{
5370 if (astate == PRED_THEN)
5371 return PRED_ELSE;
5372 else if (astate == PRED_ELSE)
5373 return PRED_THEN;
5374 else
5375 return PRED_NONE;
5376}
5377
5378static enum vpt_pred_state
5379update_next_predicate_state (void)
5380{
5381 long pred_mask = vpt_block_state.predicate_mask;
5382 long mask_for_insn = 0;
5383
5384 switch (vpt_block_state.current_insn_num)
5385 {
5386 case 1:
5387 mask_for_insn = 8;
5388 break;
5389
5390 case 2:
5391 mask_for_insn = 4;
5392 break;
5393
5394 case 3:
5395 mask_for_insn = 2;
5396 break;
5397
5398 case 4:
5399 return PRED_NONE;
5400 }
5401
5402 if (pred_mask & mask_for_insn)
5403 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5404 else
5405 return vpt_block_state.next_pred_state;
5406}
5407
5408static void
5409update_vpt_block_state (void)
5410{
5411 vpt_block_state.current_insn_num++;
5412 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5413 {
5414 /* No more instructions to process in vpt block. */
5415 mark_outside_vpt_block ();
5416 return;
5417 }
5418
5419 vpt_block_state.next_pred_state = update_next_predicate_state ();
5420}
8f06b2d8 5421
16980d0b
JB		 5422/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5423 Returns pointer to following character of the format string and
5424 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5425 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5426
5427static const char *
fe56b6ce
NC		 5428arm_decode_bitfield (const char *ptr,
5429 unsigned long insn,
5430 unsigned long *valuep,
5431 int *widthp)
16980d0b
JB		 5432{
5433 unsigned long value = 0;
5434 int width = 0;
43e65147
L		 5435
5436 do
16980d0b
JB		 5437 {
5438 int start, end;
5439 int bits;
5440
5441 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5442 start = start * 10 + *ptr - '0';
5443 if (*ptr == '-')
5444 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5445 end = end * 10 + *ptr - '0';
5446 else
5447 end = start;
5448 bits = end - start;
5449 if (bits < 0)
5450 abort ();
5451 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5452 width += bits + 1;
5453 }
5454 while (*ptr++ == ',');
5455 *valuep = value;
5456 if (widthp)
5457 *widthp = width;
5458 return ptr - 1;
5459}
5460
8f06b2d8 5461static void
6576bffe 5462arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
78933a4a 5463 bool print_shift)
8f06b2d8 5464{
6576bffe 5465 func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
8f06b2d8
PB		 5466
5467 if ((given & 0xff0) != 0)
5468 {
5469 if ((given & 0x10) == 0)
5470 {
5471 int amount = (given & 0xf80) >> 7;
5472 int shift = (given & 0x60) >> 5;
5473
5474 if (amount == 0)
5475 {
5476 if (shift == 3)
5477 {
6576bffe
AB		 5478 func (stream, dis_style_text, ", ");
5479 func (stream, dis_style_sub_mnemonic, "rrx");
8f06b2d8
PB		 5480 return;
5481 }
5482
5483 amount = 32;
5484 }
5485
37b37b2d 5486 if (print_shift)
6576bffe
AB		 5487 {
5488 func (stream, dis_style_text, ", ");
5489 func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5490 func (stream, dis_style_immediate, "#%d", amount);
5491 }
37b37b2d 5492 else
6576bffe
AB		 5493 {
5494 func (stream, dis_style_text, ", ");
5495 func (stream, dis_style_immediate, "#%d", amount);
5496 }
8f06b2d8 5497 }
74bdfecf 5498 else if ((given & 0x80) == 0x80)
6576bffe
AB		 5499 func (stream, dis_style_comment_start,
5500 "\t@ <illegal shifter operand>");
37b37b2d 5501 else if (print_shift)
6576bffe
AB		 5502 {
5503 func (stream, dis_style_text, ", ");
5504 func (stream, dis_style_sub_mnemonic, "%s ",
5505 arm_shift[(given & 0x60) >> 5]);
5506 func (stream, dis_style_register, "%s",
5507 arm_regnames[(given & 0xf00) >> 8]);
5508 }
37b37b2d 5509 else
6576bffe
AB		 5510 {
5511 func (stream, dis_style_text, ", ");
5512 func (stream, dis_style_register, "%s",
5513 arm_regnames[(given & 0xf00) >> 8]);
5514 }
8f06b2d8
PB		 5515 }
5516}
5517
73cd51e5
AV		 5518/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5519
78933a4a 5520static bool
73cd51e5
AV		 5521is_mve_okay_in_it (enum mve_instructions matched_insn)
5522{
c507f10b
AV		 5523 switch (matched_insn)
5524 {
5525 case MVE_VMOV_GP_TO_VEC_LANE:
5526 case MVE_VMOV2_VEC_LANE_TO_GP:
5527 case MVE_VMOV2_GP_TO_VEC_LANE:
5528 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5529 case MVE_LSLL:
5530 case MVE_LSLLI:
5531 case MVE_LSRL:
5532 case MVE_ASRL:
5533 case MVE_ASRLI:
5534 case MVE_SQRSHRL:
5535 case MVE_SQRSHR:
5536 case MVE_UQRSHL:
5537 case MVE_UQRSHLL:
5538 case MVE_UQSHL:
5539 case MVE_UQSHLL:
5540 case MVE_URSHRL:
5541 case MVE_URSHR:
5542 case MVE_SRSHRL:
5543 case MVE_SRSHR:
5544 case MVE_SQSHLL:
5545 case MVE_SQSHL:
78933a4a 5546 return true;
c507f10b 5547 default:
78933a4a 5548 return false;
c507f10b 5549 }
73cd51e5
AV		 5550}
5551
78933a4a 5552static bool
73cd51e5
AV		 5553is_mve_architecture (struct disassemble_info *info)
5554{
5555 struct arm_private_data *private_data = info->private_data;
5556 arm_feature_set allowed_arches = private_data->features;
5557
5558 arm_feature_set arm_ext_v8_1m_main
5559 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5560
5561 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5562 && !ARM_CPU_IS_ANY (allowed_arches))
78933a4a 5563 return true;
73cd51e5 5564 else
78933a4a 5565 return false;
73cd51e5
AV		 5566}
5567
78933a4a 5568static bool
143275ea
AV		 5569is_vpt_instruction (long given)
5570{
5571
5572 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5573 if ((given & 0x0040e000) == 0)
78933a4a 5574 return false;
143275ea
AV		 5575
5576 /* VPT floating point T1 variant. */
5577 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5578 /* VPT floating point T2 variant. */
5579 || ((given & 0xefb10f50) == 0xee310f40)
5580 /* VPT vector T1 variant. */
5581 || ((given & 0xff811f51) == 0xfe010f00)
5582 /* VPT vector T2 variant. */
5583 || ((given & 0xff811f51) == 0xfe010f01
5584 && ((given & 0x300000) != 0x300000))
5585 /* VPT vector T3 variant. */
5586 || ((given & 0xff811f50) == 0xfe011f00)
5587 /* VPT vector T4 variant. */
5588 || ((given & 0xff811f70) == 0xfe010f40)
5589 /* VPT vector T5 variant. */
5590 || ((given & 0xff811f70) == 0xfe010f60)
5591 /* VPT vector T6 variant. */
5592 || ((given & 0xff811f50) == 0xfe011f40)
5593 /* VPST vector T variant. */
5594 || ((given & 0xffbf1fff) == 0xfe310f4d))
78933a4a 5595 return true;
143275ea 5596 else
78933a4a 5597 return false;
143275ea
AV		 5598}
5599
73cd51e5
AV		 5600/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5601 and ending bitfield = END. END must be greater than START. */
5602
5603static unsigned long
5604arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5605{
5606 int bits = end - start;
5607
5608 if (bits < 0)
5609 abort ();
5610
5611 return ((given >> start) & ((2ul << bits) - 1));
5612}
5613
5614/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5615 START:END and START2:END2. END/END2 must be greater than
5616 START/START2. */
5617
5618static unsigned long
5619arm_decode_field_multiple (unsigned long given, unsigned int start,
5620 unsigned int end, unsigned int start2,
5621 unsigned int end2)
5622{
5623 int bits = end - start;
5624 int bits2 = end2 - start2;
5625 unsigned long value = 0;
5626 int width = 0;
5627
5628 if (bits2 < 0)
5629 abort ();
5630
5631 value = arm_decode_field (given, start, end);
5632 width += bits + 1;
5633
5634 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5635 return value;
5636}
5637
5638/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5639 This helps us decode instructions that change mnemonic depending on specific
5640 operand values/encodings. */
5641
78933a4a 5642static bool
73cd51e5
AV		 5643is_mve_encoding_conflict (unsigned long given,
5644 enum mve_instructions matched_insn)
5645{
143275ea
AV		 5646 switch (matched_insn)
5647 {
5648 case MVE_VPST:
5649 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5650 return true;
143275ea 5651 else
78933a4a 5652 return false;
143275ea
AV		 5653
5654 case MVE_VPT_FP_T1:
5655 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5656 return true;
143275ea
AV		 5657 if ((arm_decode_field (given, 12, 12) == 0)
5658 && (arm_decode_field (given, 0, 0) == 1))
78933a4a
AM		 5659 return true;
5660 return false;
143275ea
AV		 5661
5662 case MVE_VPT_FP_T2:
5663 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5664 return true;
143275ea 5665 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a
AM		 5666 return true;
5667 return false;
143275ea
AV		 5668
5669 case MVE_VPT_VEC_T1:
5670 case MVE_VPT_VEC_T2:
5671 case MVE_VPT_VEC_T3:
5672 case MVE_VPT_VEC_T4:
5673 case MVE_VPT_VEC_T5:
5674 case MVE_VPT_VEC_T6:
5675 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5676 return true;
143275ea 5677 if (arm_decode_field (given, 20, 21) == 3)
78933a4a
AM		 5678 return true;
5679 return false;
143275ea
AV		 5680
5681 case MVE_VCMP_FP_T1:
5682 if ((arm_decode_field (given, 12, 12) == 0)
5683 && (arm_decode_field (given, 0, 0) == 1))
78933a4a 5684 return true;
143275ea 5685 else
78933a4a 5686 return false;
143275ea
AV		 5687
5688 case MVE_VCMP_FP_T2:
5689 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5690 return true;
143275ea 5691 else
78933a4a 5692 return false;
143275ea 5693
14b456f2
AV		 5694 case MVE_VQADD_T2:
5695 case MVE_VQSUB_T2:
f49bb598
AV		 5696 case MVE_VMUL_VEC_T2:
5697 case MVE_VMULH:
5698 case MVE_VRMULH:
56858bea
AV		 5699 case MVE_VMLA:
5700 case MVE_VMAX:
5701 case MVE_VMIN:
e523f101 5702 case MVE_VBRSR:
66dcaa5d
AV		 5703 case MVE_VADD_VEC_T2:
5704 case MVE_VSUB_VEC_T2:
5705 case MVE_VABAV:
ed63aa17
AV		 5706 case MVE_VQRSHL_T1:
5707 case MVE_VQSHL_T4:
5708 case MVE_VRSHL_T1:
5709 case MVE_VSHL_T3:
897b9bbc
AV		 5710 case MVE_VCADD_VEC:
5711 case MVE_VHCADD:
1c8f2df8
AV		 5712 case MVE_VDDUP:
5713 case MVE_VIDUP:
d3b63143
AV		 5714 case MVE_VQRDMLADH:
5715 case MVE_VQDMLAH:
5716 case MVE_VQRDMLAH:
5717 case MVE_VQDMLASH:
5718 case MVE_VQRDMLASH:
5719 case MVE_VQDMLSDH:
5720 case MVE_VQRDMLSDH:
5721 case MVE_VQDMULH_T3:
5722 case MVE_VQRDMULH_T4:
5723 case MVE_VQDMLADH:
5724 case MVE_VMLAS:
14925797 5725 case MVE_VMULL_INT:
9743db03
AV		 5726 case MVE_VHADD_T2:
5727 case MVE_VHSUB_T2:
143275ea
AV		 5728 case MVE_VCMP_VEC_T1:
5729 case MVE_VCMP_VEC_T2:
5730 case MVE_VCMP_VEC_T3:
5731 case MVE_VCMP_VEC_T4:
5732 case MVE_VCMP_VEC_T5:
5733 case MVE_VCMP_VEC_T6:
5734 if (arm_decode_field (given, 20, 21) == 3)
78933a4a 5735 return true;
143275ea 5736 else
78933a4a 5737 return false;
143275ea 5738
04d54ace
AV		 5739 case MVE_VLD2:
5740 case MVE_VLD4:
5741 case MVE_VST2:
5742 case MVE_VST4:
5743 if (arm_decode_field (given, 7, 8) == 3)
78933a4a 5744 return true;
04d54ace 5745 else
78933a4a 5746 return false;
04d54ace 5747
aef6d006
AV		 5748 case MVE_VSTRB_T1:
5749 case MVE_VSTRH_T2:
5750 if ((arm_decode_field (given, 24, 24) == 0)
5751 && (arm_decode_field (given, 21, 21) == 0))
5752 {
78933a4a 5753 return true;
aef6d006
AV		 5754 }
5755 else if ((arm_decode_field (given, 7, 8) == 3))
78933a4a 5756 return true;
aef6d006 5757 else
78933a4a 5758 return false;
aef6d006 5759
e683cb41
AC		 5760 case MVE_VLDRB_T1:
5761 case MVE_VLDRH_T2:
5762 case MVE_VLDRW_T7:
aef6d006
AV		 5763 case MVE_VSTRB_T5:
5764 case MVE_VSTRH_T6:
5765 case MVE_VSTRW_T7:
5766 if ((arm_decode_field (given, 24, 24) == 0)
5767 && (arm_decode_field (given, 21, 21) == 0))
5768 {
78933a4a 5769 return true;
aef6d006
AV		 5770 }
5771 else
78933a4a 5772 return false;
aef6d006 5773
bf0b396d
AV		 5774 case MVE_VCVT_FP_FIX_VEC:
5775 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5776
c507f10b
AV		 5777 case MVE_VBIC_IMM:
5778 case MVE_VORR_IMM:
5779 {
5780 unsigned long cmode = arm_decode_field (given, 8, 11);
5781
5782 if ((cmode & 1) == 0)
78933a4a 5783 return true;
c507f10b 5784 else if ((cmode & 0xc) == 0xc)
78933a4a 5785 return true;
c507f10b 5786 else
78933a4a 5787 return false;
c507f10b
AV		 5788 }
5789
5790 case MVE_VMVN_IMM:
5791 {
5792 unsigned long cmode = arm_decode_field (given, 8, 11);
5793
ce760a76 5794 if (cmode == 0xe)
78933a4a 5795 return true;
ce760a76 5796 else if ((cmode & 0x9) == 1)
78933a4a 5797 return true;
ce760a76 5798 else if ((cmode & 0xd) == 9)
78933a4a 5799 return true;
c507f10b 5800 else
78933a4a 5801 return false;
c507f10b
AV		 5802 }
5803
5804 case MVE_VMOV_IMM_TO_VEC:
5805 if ((arm_decode_field (given, 5, 5) == 1)
5806 && (arm_decode_field (given, 8, 11) != 0xe))
78933a4a 5807 return true;
c507f10b 5808 else
78933a4a 5809 return false;
c507f10b 5810
14925797
AV		 5811 case MVE_VMOVL:
5812 {
5813 unsigned long size = arm_decode_field (given, 19, 20);
5814 if ((size == 0) || (size == 3))
78933a4a 5815 return true;
14925797 5816 else
78933a4a 5817 return false;
14925797
AV		 5818 }
5819
56858bea
AV		 5820 case MVE_VMAXA:
5821 case MVE_VMINA:
5822 case MVE_VMAXV:
5823 case MVE_VMAXAV:
5824 case MVE_VMINV:
5825 case MVE_VMINAV:
ed63aa17
AV		 5826 case MVE_VQRSHL_T2:
5827 case MVE_VQSHL_T1:
5828 case MVE_VRSHL_T2:
5829 case MVE_VSHL_T2:
5830 case MVE_VSHLL_T2:
d3b63143 5831 case MVE_VADDV:
14925797
AV		 5832 case MVE_VMOVN:
5833 case MVE_VQMOVUN:
5834 case MVE_VQMOVN:
5835 if (arm_decode_field (given, 18, 19) == 3)
78933a4a 5836 return true;
14925797 5837 else
78933a4a 5838 return false;
14925797 5839
d3b63143
AV		 5840 case MVE_VMLSLDAV:
5841 case MVE_VRMLSLDAVH:
5842 case MVE_VMLALDAV:
5843 case MVE_VADDLV:
5844 if (arm_decode_field (given, 20, 22) == 7)
78933a4a 5845 return true;
d3b63143 5846 else
78933a4a 5847 return false;
d3b63143
AV		 5848
5849 case MVE_VRMLALDAVH:
5850 if ((arm_decode_field (given, 20, 22) & 6) == 6)
78933a4a 5851 return true;
d3b63143 5852 else
78933a4a 5853 return false;
d3b63143 5854
1c8f2df8
AV		 5855 case MVE_VDWDUP:
5856 case MVE_VIWDUP:
5857 if ((arm_decode_field (given, 20, 21) == 3)
5858 || (arm_decode_field (given, 1, 3) == 7))
78933a4a 5859 return true;
1c8f2df8 5860 else
78933a4a 5861 return false;
1c8f2df8 5862
ed63aa17
AV		 5863
5864 case MVE_VSHLL_T1:
5865 if (arm_decode_field (given, 16, 18) == 0)
5866 {
5867 unsigned long sz = arm_decode_field (given, 19, 20);
5868
5869 if ((sz == 1) || (sz == 2))
78933a4a 5870 return true;
ed63aa17 5871 else
78933a4a 5872 return false;
ed63aa17
AV		 5873 }
5874 else
78933a4a 5875 return false;
ed63aa17
AV		 5876
5877 case MVE_VQSHL_T2:
5878 case MVE_VQSHLU_T3:
5879 case MVE_VRSHR:
5880 case MVE_VSHL_T1:
5881 case MVE_VSHR:
5882 case MVE_VSLI:
5883 case MVE_VSRI:
5884 if (arm_decode_field (given, 19, 21) == 0)
78933a4a 5885 return true;
ed63aa17 5886 else
78933a4a 5887 return false;
ed63aa17 5888
e523f101
AV		 5889 case MVE_VCTP:
5890 if (arm_decode_field (given, 16, 19) == 0xf)
78933a4a 5891 return true;
e523f101 5892 else
78933a4a 5893 return false;
e523f101 5894
23d00a41
SD		 5895 case MVE_ASRLI:
5896 case MVE_ASRL:
5897 case MVE_LSLLI:
5898 case MVE_LSLL:
5899 case MVE_LSRL:
5900 case MVE_SQRSHRL:
5901 case MVE_SQSHLL:
5902 case MVE_SRSHRL:
5903 case MVE_UQRSHLL:
5904 case MVE_UQSHLL:
5905 case MVE_URSHRL:
5906 if (arm_decode_field (given, 9, 11) == 0x7)
78933a4a 5907 return true;
23d00a41 5908 else
78933a4a 5909 return false;
23d00a41 5910
e39c1607
SD		 5911 case MVE_CSINC:
5912 case MVE_CSINV:
5913 {
5914 unsigned long rm, rn;
5915 rm = arm_decode_field (given, 0, 3);
5916 rn = arm_decode_field (given, 16, 19);
5917 /* CSET/CSETM. */
5918 if (rm == 0xf && rn == 0xf)
78933a4a 5919 return true;
e39c1607
SD		 5920 /* CINC/CINV. */
5921 else if (rn == rm && rn != 0xf)
78933a4a 5922 return true;
e39c1607
SD		 5923 }
5924 /* Fall through. */
5925 case MVE_CSEL:
5926 case MVE_CSNEG:
5927 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5928 return true;
e39c1607
SD		 5929 /* CNEG. */
5930 else if (matched_insn == MVE_CSNEG)
5931 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
78933a4a
AM		 5932 return true;
5933 return false;
e39c1607 5934
143275ea 5935 default:
66dcaa5d
AV		 5936 case MVE_VADD_FP_T1:
5937 case MVE_VADD_FP_T2:
5938 case MVE_VADD_VEC_T1:
78933a4a 5939 return false;
143275ea
AV		 5940
5941 }
73cd51e5
AV		 5942}
5943
aef6d006
AV		 5944static void
5945print_mve_vld_str_addr (struct disassemble_info *info,
5946 unsigned long given,
5947 enum mve_instructions matched_insn)
5948{
5949 void *stream = info->stream;
6576bffe 5950 fprintf_styled_ftype func = info->fprintf_styled_func;
aef6d006
AV		 5951
5952 unsigned long p, w, gpr, imm, add, mod_imm;
5953
5954 imm = arm_decode_field (given, 0, 6);
5955 mod_imm = imm;
5956
5957 switch (matched_insn)
5958 {
5959 case MVE_VLDRB_T1:
5960 case MVE_VSTRB_T1:
5961 gpr = arm_decode_field (given, 16, 18);
5962 break;
5963
5964 case MVE_VLDRH_T2:
5965 case MVE_VSTRH_T2:
5966 gpr = arm_decode_field (given, 16, 18);
5967 mod_imm = imm << 1;
5968 break;
5969
5970 case MVE_VLDRH_T6:
5971 case MVE_VSTRH_T6:
5972 gpr = arm_decode_field (given, 16, 19);
5973 mod_imm = imm << 1;
5974 break;
5975
5976 case MVE_VLDRW_T7:
5977 case MVE_VSTRW_T7:
5978 gpr = arm_decode_field (given, 16, 19);
5979 mod_imm = imm << 2;
5980 break;
5981
5982 case MVE_VLDRB_T5:
5983 case MVE_VSTRB_T5:
5984 gpr = arm_decode_field (given, 16, 19);
5985 break;
5986
5987 default:
5988 return;
5989 }
5990
5991 p = arm_decode_field (given, 24, 24);
5992 w = arm_decode_field (given, 21, 21);
5993
5994 add = arm_decode_field (given, 23, 23);
5995
5996 char * add_sub;
5997
5998 /* Don't print anything for '+' as it is implied. */
5999 if (add == 1)
6000 add_sub = "";
6001 else
6002 add_sub = "-";
6003
6576bffe 6004 func (stream, dis_style_text, "[");
4575eafb 6005 func (stream, dis_style_register, "%s", arm_regnames[gpr]);
aef6d006
AV		 6006 if (p == 1)
6007 {
6576bffe
AB		 6008 func (stream, dis_style_text, ", ");
6009 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
aef6d006
AV		 6010 /* Offset mode. */
6011 if (w == 0)
6576bffe 6012 func (stream, dis_style_text, "]");
aef6d006
AV		 6013 /* Pre-indexed mode. */
6014 else
6576bffe 6015 func (stream, dis_style_text, "]!");
aef6d006
AV		 6016 }
6017 else if ((p == 0) && (w == 1))
6576bffe
AB		 6018 {
6019 /* Post-index mode. */
6020 func (stream, dis_style_text, "], ");
6021 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
6022 }
aef6d006
AV		 6023}
6024
73cd51e5
AV		 6025/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
6026 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
6027 this encoding is undefined. */
6028
78933a4a 6029static bool
73cd51e5
AV		 6030is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
6031 enum mve_undefined *undefined_code)
6032{
6033 *undefined_code = UNDEF_NONE;
6034
9743db03
AV		 6035 switch (matched_insn)
6036 {
6037 case MVE_VDUP:
6038 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
6039 {
6040 *undefined_code = UNDEF_SIZE_3;
78933a4a 6041 return true;
9743db03
AV		 6042 }
6043 else
78933a4a 6044 return false;
9743db03 6045
14b456f2
AV		 6046 case MVE_VQADD_T1:
6047 case MVE_VQSUB_T1:
f49bb598 6048 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 6049 case MVE_VABD_VEC:
6050 case MVE_VADD_VEC_T1:
6051 case MVE_VSUB_VEC_T1:
d3b63143
AV		 6052 case MVE_VQDMULH_T1:
6053 case MVE_VQRDMULH_T2:
9743db03
AV		 6054 case MVE_VRHADD:
6055 case MVE_VHADD_T1:
6056 case MVE_VHSUB_T1:
6057 if (arm_decode_field (given, 20, 21) == 3)
6058 {
6059 *undefined_code = UNDEF_SIZE_3;
78933a4a 6060 return true;
9743db03
AV		 6061 }
6062 else
78933a4a 6063 return false;
9743db03 6064
aef6d006
AV		 6065 case MVE_VLDRB_T1:
6066 if (arm_decode_field (given, 7, 8) == 3)
6067 {
6068 *undefined_code = UNDEF_SIZE_3;
78933a4a 6069 return true;
aef6d006
AV		 6070 }
6071 else
78933a4a 6072 return false;
aef6d006
AV		 6073
6074 case MVE_VLDRH_T2:
6075 if (arm_decode_field (given, 7, 8) <= 1)
6076 {
6077 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6078 return true;
aef6d006
AV		 6079 }
6080 else
78933a4a 6081 return false;
aef6d006
AV		 6082
6083 case MVE_VSTRB_T1:
6084 if ((arm_decode_field (given, 7, 8) == 0))
6085 {
6086 *undefined_code = UNDEF_SIZE_0;
78933a4a 6087 return true;
aef6d006
AV		 6088 }
6089 else
78933a4a 6090 return false;
aef6d006
AV		 6091
6092 case MVE_VSTRH_T2:
6093 if ((arm_decode_field (given, 7, 8) <= 1))
6094 {
6095 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6096 return true;
aef6d006
AV		 6097 }
6098 else
78933a4a 6099 return false;
aef6d006 6100
ef1576a1
AV		 6101 case MVE_VLDRB_GATHER_T1:
6102 if (arm_decode_field (given, 7, 8) == 3)
6103 {
6104 *undefined_code = UNDEF_SIZE_3;
78933a4a 6105 return true;
ef1576a1
AV		 6106 }
6107 else if ((arm_decode_field (given, 28, 28) == 0)
6108 && (arm_decode_field (given, 7, 8) == 0))
6109 {
6110 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
78933a4a 6111 return true;
ef1576a1
AV		 6112 }
6113 else
78933a4a 6114 return false;
ef1576a1
AV		 6115
6116 case MVE_VLDRH_GATHER_T2:
6117 if (arm_decode_field (given, 7, 8) == 3)
6118 {
6119 *undefined_code = UNDEF_SIZE_3;
78933a4a 6120 return true;
ef1576a1
AV		 6121 }
6122 else if ((arm_decode_field (given, 28, 28) == 0)
6123 && (arm_decode_field (given, 7, 8) == 1))
6124 {
6125 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
78933a4a 6126 return true;
ef1576a1
AV		 6127 }
6128 else if (arm_decode_field (given, 7, 8) == 0)
6129 {
6130 *undefined_code = UNDEF_SIZE_0;
78933a4a 6131 return true;
ef1576a1
AV		 6132 }
6133 else
78933a4a 6134 return false;
ef1576a1
AV		 6135
6136 case MVE_VLDRW_GATHER_T3:
6137 if (arm_decode_field (given, 7, 8) != 2)
6138 {
6139 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6140 return true;
ef1576a1
AV		 6141 }
6142 else if (arm_decode_field (given, 28, 28) == 0)
6143 {
6144 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6145 return true;
ef1576a1
AV		 6146 }
6147 else
78933a4a 6148 return false;
ef1576a1
AV		 6149
6150 case MVE_VLDRD_GATHER_T4:
6151 if (arm_decode_field (given, 7, 8) != 3)
6152 {
6153 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6154 return true;
ef1576a1
AV		 6155 }
6156 else if (arm_decode_field (given, 28, 28) == 0)
6157 {
6158 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6159 return true;
ef1576a1
AV		 6160 }
6161 else
78933a4a 6162 return false;
ef1576a1
AV		 6163
6164 case MVE_VSTRB_SCATTER_T1:
6165 if (arm_decode_field (given, 7, 8) == 3)
6166 {
6167 *undefined_code = UNDEF_SIZE_3;
78933a4a 6168 return true;
ef1576a1
AV		 6169 }
6170 else
78933a4a 6171 return false;
ef1576a1
AV		 6172
6173 case MVE_VSTRH_SCATTER_T2:
6174 {
6175 unsigned long size = arm_decode_field (given, 7, 8);
6176 if (size == 3)
6177 {
6178 *undefined_code = UNDEF_SIZE_3;
78933a4a 6179 return true;
ef1576a1
AV		 6180 }
6181 else if (size == 0)
6182 {
6183 *undefined_code = UNDEF_SIZE_0;
78933a4a 6184 return true;
ef1576a1
AV		 6185 }
6186 else
78933a4a 6187 return false;
ef1576a1
AV		 6188 }
6189
6190 case MVE_VSTRW_SCATTER_T3:
6191 if (arm_decode_field (given, 7, 8) != 2)
6192 {
6193 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6194 return true;
ef1576a1
AV		 6195 }
6196 else
78933a4a 6197 return false;
ef1576a1
AV		 6198
6199 case MVE_VSTRD_SCATTER_T4:
6200 if (arm_decode_field (given, 7, 8) != 3)
6201 {
6202 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6203 return true;
ef1576a1
AV		 6204 }
6205 else
78933a4a 6206 return false;
ef1576a1 6207
bf0b396d
AV		 6208 case MVE_VCVT_FP_FIX_VEC:
6209 {
6210 unsigned long imm6 = arm_decode_field (given, 16, 21);
6211 if ((imm6 & 0x20) == 0)
6212 {
6213 *undefined_code = UNDEF_VCVT_IMM6;
78933a4a 6214 return true;
bf0b396d
AV		 6215 }
6216
6217 if ((arm_decode_field (given, 9, 9) == 0)
6218 && ((imm6 & 0x30) == 0x20))
6219 {
6220 *undefined_code = UNDEF_VCVT_FSI_IMM6;
78933a4a 6221 return true;
bf0b396d
AV		 6222 }
6223
78933a4a 6224 return false;
bf0b396d
AV		 6225 }
6226
f49bb598 6227 case MVE_VNEG_FP:
66dcaa5d 6228 case MVE_VABS_FP:
bf0b396d
AV		 6229 case MVE_VCVT_BETWEEN_FP_INT:
6230 case MVE_VCVT_FROM_FP_TO_INT:
6231 {
6232 unsigned long size = arm_decode_field (given, 18, 19);
6233 if (size == 0)
6234 {
6235 *undefined_code = UNDEF_SIZE_0;
78933a4a 6236 return true;
bf0b396d
AV		 6237 }
6238 else if (size == 3)
6239 {
6240 *undefined_code = UNDEF_SIZE_3;
78933a4a 6241 return true;
bf0b396d
AV		 6242 }
6243 else
78933a4a 6244 return false;
bf0b396d
AV		 6245 }
6246
c507f10b
AV		 6247 case MVE_VMOV_VEC_LANE_TO_GP:
6248 {
6249 unsigned long op1 = arm_decode_field (given, 21, 22);
6250 unsigned long op2 = arm_decode_field (given, 5, 6);
6251 unsigned long u = arm_decode_field (given, 23, 23);
6252
6253 if ((op2 == 0) && (u == 1))
6254 {
6255 if ((op1 == 0) || (op1 == 1))
6256 {
6257 *undefined_code = UNDEF_BAD_U_OP1_OP2;
78933a4a 6258 return true;
c507f10b
AV		 6259 }
6260 else
78933a4a 6261 return false;
c507f10b
AV		 6262 }
6263 else if (op2 == 2)
6264 {
6265 if ((op1 == 0) || (op1 == 1))
6266 {
6267 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6268 return true;
c507f10b
AV		 6269 }
6270 else
78933a4a 6271 return false;
c507f10b
AV		 6272 }
6273
78933a4a 6274 return false;
c507f10b
AV		 6275 }
6276
6277 case MVE_VMOV_GP_TO_VEC_LANE:
6278 if (arm_decode_field (given, 5, 6) == 2)
6279 {
6280 unsigned long op1 = arm_decode_field (given, 21, 22);
6281 if ((op1 == 0) || (op1 == 1))
6282 {
6283 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6284 return true;
c507f10b
AV		 6285 }
6286 else
78933a4a 6287 return false;
c507f10b
AV		 6288 }
6289 else
78933a4a 6290 return false;
c507f10b 6291
c4a23bf8
SP		 6292 case MVE_VMOV_VEC_TO_VEC:
6293 if ((arm_decode_field (given, 5, 5) == 1)
6294 || (arm_decode_field (given, 22, 22) == 1))
78933a4a
AM		 6295 return true;
6296 return false;
c4a23bf8 6297
c507f10b
AV		 6298 case MVE_VMOV_IMM_TO_VEC:
6299 if (arm_decode_field (given, 5, 5) == 0)
6300 {
6301 unsigned long cmode = arm_decode_field (given, 8, 11);
6302
6303 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6304 {
6305 *undefined_code = UNDEF_OP_0_BAD_CMODE;
78933a4a 6306 return true;
c507f10b
AV		 6307 }
6308 else
78933a4a 6309 return false;
c507f10b
AV		 6310 }
6311 else
78933a4a 6312 return false;
c507f10b 6313
ed63aa17 6314 case MVE_VSHLL_T2:
14925797
AV		 6315 case MVE_VMOVN:
6316 if (arm_decode_field (given, 18, 19) == 2)
6317 {
6318 *undefined_code = UNDEF_SIZE_2;
78933a4a 6319 return true;
14925797
AV		 6320 }
6321 else
78933a4a 6322 return false;
14925797 6323
d3b63143
AV		 6324 case MVE_VRMLALDAVH:
6325 case MVE_VMLADAV_T1:
6326 case MVE_VMLADAV_T2:
6327 case MVE_VMLALDAV:
6328 if ((arm_decode_field (given, 28, 28) == 1)
6329 && (arm_decode_field (given, 12, 12) == 1))
6330 {
6331 *undefined_code = UNDEF_XCHG_UNS;
78933a4a 6332 return true;
d3b63143
AV		 6333 }
6334 else
78933a4a 6335 return false;
d3b63143 6336
ed63aa17
AV		 6337 case MVE_VQSHRN:
6338 case MVE_VQSHRUN:
6339 case MVE_VSHLL_T1:
6340 case MVE_VSHRN:
6341 {
6342 unsigned long sz = arm_decode_field (given, 19, 20);
6343 if (sz == 1)
78933a4a 6344 return false;
ed63aa17 6345 else if ((sz & 2) == 2)
78933a4a 6346 return false;
ed63aa17
AV		 6347 else
6348 {
6349 *undefined_code = UNDEF_SIZE;
78933a4a 6350 return true;
ed63aa17
AV		 6351 }
6352 }
6353 break;
6354
6355 case MVE_VQSHL_T2:
6356 case MVE_VQSHLU_T3:
6357 case MVE_VRSHR:
6358 case MVE_VSHL_T1:
6359 case MVE_VSHR:
6360 case MVE_VSLI:
6361 case MVE_VSRI:
6362 {
6363 unsigned long sz = arm_decode_field (given, 19, 21);
6364 if ((sz & 7) == 1)
78933a4a 6365 return false;
ed63aa17 6366 else if ((sz & 6) == 2)
78933a4a 6367 return false;
ed63aa17 6368 else if ((sz & 4) == 4)
78933a4a 6369 return false;
ed63aa17
AV		 6370 else
6371 {
6372 *undefined_code = UNDEF_SIZE;
78933a4a 6373 return true;
ed63aa17
AV		 6374 }
6375 }
6376
6377 case MVE_VQRSHRN:
6378 case MVE_VQRSHRUN:
6379 if (arm_decode_field (given, 19, 20) == 0)
6380 {
6381 *undefined_code = UNDEF_SIZE_0;
78933a4a 6382 return true;
ed63aa17
AV		 6383 }
6384 else
78933a4a 6385 return false;
ed63aa17 6386
66dcaa5d
AV		 6387 case MVE_VABS_VEC:
6388 if (arm_decode_field (given, 18, 19) == 3)
6389 {
6390 *undefined_code = UNDEF_SIZE_3;
78933a4a 6391 return true;
66dcaa5d
AV		 6392 }
6393 else
78933a4a 6394 return false;
66dcaa5d 6395
14b456f2
AV		 6396 case MVE_VQNEG:
6397 case MVE_VQABS:
f49bb598 6398 case MVE_VNEG_VEC:
e523f101
AV		 6399 case MVE_VCLS:
6400 case MVE_VCLZ:
6401 if (arm_decode_field (given, 18, 19) == 3)
6402 {
6403 *undefined_code = UNDEF_SIZE_3;
78933a4a 6404 return true;
e523f101
AV		 6405 }
6406 else
78933a4a 6407 return false;
e523f101 6408
14b456f2
AV		 6409 case MVE_VREV16:
6410 if (arm_decode_field (given, 18, 19) == 0)
78933a4a 6411 return false;
14b456f2
AV		 6412 else
6413 {
6414 *undefined_code = UNDEF_SIZE_NOT_0;
78933a4a 6415 return true;
14b456f2
AV		 6416 }
6417
6418 case MVE_VREV32:
6419 {
6420 unsigned long size = arm_decode_field (given, 18, 19);
6421 if ((size & 2) == 2)
6422 {
6423 *undefined_code = UNDEF_SIZE_2;
78933a4a 6424 return true;
14b456f2
AV		 6425 }
6426 else
78933a4a 6427 return false;
14b456f2
AV		 6428 }
6429
6430 case MVE_VREV64:
6431 if (arm_decode_field (given, 18, 19) != 3)
78933a4a 6432 return false;
14b456f2
AV		 6433 else
6434 {
6435 *undefined_code = UNDEF_SIZE_3;
78933a4a 6436 return true;
14b456f2
AV		 6437 }
6438
9743db03 6439 default:
78933a4a 6440 return false;
9743db03 6441 }
73cd51e5
AV		 6442}
6443
6444/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6445 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6446 why this encoding is unpredictable. */
6447
78933a4a 6448static bool
73cd51e5
AV		 6449is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6450 enum mve_unpredictable *unpredictable_code)
6451{
6452 *unpredictable_code = UNPRED_NONE;
6453
143275ea
AV		 6454 switch (matched_insn)
6455 {
6456 case MVE_VCMP_FP_T2:
6457 case MVE_VPT_FP_T2:
6458 if ((arm_decode_field (given, 12, 12) == 0)
6459 && (arm_decode_field (given, 5, 5) == 1))
6460 {
6461 *unpredictable_code = UNPRED_FCA_0_FCB_1;
78933a4a 6462 return true;
143275ea
AV		 6463 }
6464 else
78933a4a 6465 return false;
73cd51e5 6466
143275ea
AV		 6467 case MVE_VPT_VEC_T4:
6468 case MVE_VPT_VEC_T5:
6469 case MVE_VPT_VEC_T6:
6470 case MVE_VCMP_VEC_T4:
6471 case MVE_VCMP_VEC_T5:
6472 case MVE_VCMP_VEC_T6:
6473 if (arm_decode_field (given, 0, 3) == 0xd)
6474 {
6475 *unpredictable_code = UNPRED_R13;
78933a4a 6476 return true;
143275ea
AV		 6477 }
6478 else
78933a4a 6479 return false;
c1e26897 6480
9743db03
AV		 6481 case MVE_VDUP:
6482 {
6483 unsigned long gpr = arm_decode_field (given, 12, 15);
6484 if (gpr == 0xd)
6485 {
6486 *unpredictable_code = UNPRED_R13;
78933a4a 6487 return true;
9743db03
AV		 6488 }
6489 else if (gpr == 0xf)
6490 {
6491 *unpredictable_code = UNPRED_R15;
78933a4a 6492 return true;
9743db03
AV		 6493 }
6494
78933a4a 6495 return false;
9743db03
AV		 6496 }
6497
14b456f2
AV		 6498 case MVE_VQADD_T2:
6499 case MVE_VQSUB_T2:
f49bb598
AV		 6500 case MVE_VMUL_FP_T2:
6501 case MVE_VMUL_VEC_T2:
56858bea 6502 case MVE_VMLA:
e523f101 6503 case MVE_VBRSR:
66dcaa5d
AV		 6504 case MVE_VADD_FP_T2:
6505 case MVE_VSUB_FP_T2:
6506 case MVE_VADD_VEC_T2:
6507 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6508 case MVE_VQRSHL_T2:
6509 case MVE_VQSHL_T1:
6510 case MVE_VRSHL_T2:
6511 case MVE_VSHL_T2:
6512 case MVE_VSHLC:
d3b63143
AV		 6513 case MVE_VQDMLAH:
6514 case MVE_VQRDMLAH:
6515 case MVE_VQDMLASH:
6516 case MVE_VQRDMLASH:
6517 case MVE_VQDMULH_T3:
6518 case MVE_VQRDMULH_T4:
6519 case MVE_VMLAS:
9743db03
AV		 6520 case MVE_VFMA_FP_SCALAR:
6521 case MVE_VFMAS_FP_SCALAR:
6522 case MVE_VHADD_T2:
6523 case MVE_VHSUB_T2:
6524 {
6525 unsigned long gpr = arm_decode_field (given, 0, 3);
6526 if (gpr == 0xd)
6527 {
6528 *unpredictable_code = UNPRED_R13;
78933a4a 6529 return true;
9743db03
AV		 6530 }
6531 else if (gpr == 0xf)
6532 {
6533 *unpredictable_code = UNPRED_R15;
78933a4a 6534 return true;
9743db03
AV		 6535 }
6536
78933a4a 6537 return false;
9743db03
AV		 6538 }
6539
04d54ace
AV		 6540 case MVE_VLD2:
6541 case MVE_VST2:
6542 {
6543 unsigned long rn = arm_decode_field (given, 16, 19);
6544
6545 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6546 {
6547 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6548 return true;
04d54ace
AV		 6549 }
6550
6551 if (rn == 0xf)
6552 {
6553 *unpredictable_code = UNPRED_R15;
78933a4a 6554 return true;
04d54ace
AV		 6555 }
6556
6557 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6558 {
6559 *unpredictable_code = UNPRED_Q_GT_6;
78933a4a 6560 return true;
04d54ace
AV		 6561 }
6562 else
78933a4a 6563 return false;
04d54ace
AV		 6564 }
6565
6566 case MVE_VLD4:
6567 case MVE_VST4:
6568 {
6569 unsigned long rn = arm_decode_field (given, 16, 19);
6570
6571 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6572 {
6573 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6574 return true;
04d54ace
AV		 6575 }
6576
6577 if (rn == 0xf)
6578 {
6579 *unpredictable_code = UNPRED_R15;
78933a4a 6580 return true;
04d54ace
AV		 6581 }
6582
6583 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6584 {
6585 *unpredictable_code = UNPRED_Q_GT_4;
78933a4a 6586 return true;
04d54ace
AV		 6587 }
6588 else
78933a4a 6589 return false;
04d54ace
AV		 6590 }
6591
aef6d006
AV		 6592 case MVE_VLDRB_T5:
6593 case MVE_VLDRH_T6:
6594 case MVE_VLDRW_T7:
6595 case MVE_VSTRB_T5:
6596 case MVE_VSTRH_T6:
6597 case MVE_VSTRW_T7:
6598 {
6599 unsigned long rn = arm_decode_field (given, 16, 19);
6600
6601 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6602 {
6603 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6604 return true;
aef6d006
AV		 6605 }
6606 else if (rn == 0xf)
6607 {
6608 *unpredictable_code = UNPRED_R15;
78933a4a 6609 return true;
aef6d006
AV		 6610 }
6611 else
78933a4a 6612 return false;
aef6d006
AV		 6613 }
6614
ef1576a1
AV		 6615 case MVE_VLDRB_GATHER_T1:
6616 if (arm_decode_field (given, 0, 0) == 1)
6617 {
6618 *unpredictable_code = UNPRED_OS;
78933a4a 6619 return true;
ef1576a1
AV		 6620 }
6621
6622 /* fall through. */
6623 /* To handle common code with T2-T4 variants. */
6624 case MVE_VLDRH_GATHER_T2:
6625 case MVE_VLDRW_GATHER_T3:
6626 case MVE_VLDRD_GATHER_T4:
6627 {
6628 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6629 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6630
6631 if (qd == qm)
6632 {
6633 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6634 return true;
ef1576a1
AV		 6635 }
6636
6637 if (arm_decode_field (given, 16, 19) == 0xf)
6638 {
6639 *unpredictable_code = UNPRED_R15;
78933a4a 6640 return true;
ef1576a1
AV		 6641 }
6642
78933a4a 6643 return false;
ef1576a1
AV		 6644 }
6645
6646 case MVE_VLDRW_GATHER_T5:
6647 case MVE_VLDRD_GATHER_T6:
6648 {
6649 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6650 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6651
6652 if (qd == qm)
6653 {
6654 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6655 return true;
ef1576a1
AV		 6656 }
6657 else
78933a4a 6658 return false;
ef1576a1
AV		 6659 }
6660
6661 case MVE_VSTRB_SCATTER_T1:
6662 if (arm_decode_field (given, 16, 19) == 0xf)
6663 {
6664 *unpredictable_code = UNPRED_R15;
78933a4a 6665 return true;
ef1576a1
AV		 6666 }
6667 else if (arm_decode_field (given, 0, 0) == 1)
6668 {
6669 *unpredictable_code = UNPRED_OS;
78933a4a 6670 return true;
ef1576a1
AV		 6671 }
6672 else
78933a4a 6673 return false;
ef1576a1
AV		 6674
6675 case MVE_VSTRH_SCATTER_T2:
6676 case MVE_VSTRW_SCATTER_T3:
6677 case MVE_VSTRD_SCATTER_T4:
6678 if (arm_decode_field (given, 16, 19) == 0xf)
6679 {
6680 *unpredictable_code = UNPRED_R15;
78933a4a 6681 return true;
ef1576a1
AV		 6682 }
6683 else
78933a4a 6684 return false;
ef1576a1 6685
c507f10b
AV		 6686 case MVE_VMOV2_VEC_LANE_TO_GP:
6687 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6688 case MVE_VCVT_BETWEEN_FP_INT:
6689 case MVE_VCVT_FROM_FP_TO_INT:
6690 {
6691 unsigned long rt = arm_decode_field (given, 0, 3);
6692 unsigned long rt2 = arm_decode_field (given, 16, 19);
6693
6694 if ((rt == 0xd) || (rt2 == 0xd))
6695 {
6696 *unpredictable_code = UNPRED_R13;
78933a4a 6697 return true;
bf0b396d
AV		 6698 }
6699 else if ((rt == 0xf) || (rt2 == 0xf))
6700 {
6701 *unpredictable_code = UNPRED_R15;
78933a4a 6702 return true;
bf0b396d 6703 }
e683cb41 6704 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
bf0b396d
AV		 6705 {
6706 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
78933a4a 6707 return true;
bf0b396d
AV		 6708 }
6709
78933a4a 6710 return false;
bf0b396d
AV		 6711 }
6712
56858bea
AV		 6713 case MVE_VMAXV:
6714 case MVE_VMAXAV:
6715 case MVE_VMAXNMV_FP:
6716 case MVE_VMAXNMAV_FP:
6717 case MVE_VMINNMV_FP:
6718 case MVE_VMINNMAV_FP:
6719 case MVE_VMINV:
6720 case MVE_VMINAV:
66dcaa5d 6721 case MVE_VABAV:
c507f10b
AV		 6722 case MVE_VMOV_HFP_TO_GP:
6723 case MVE_VMOV_GP_TO_VEC_LANE:
6724 case MVE_VMOV_VEC_LANE_TO_GP:
6725 {
6726 unsigned long rda = arm_decode_field (given, 12, 15);
6727 if (rda == 0xd)
6728 {
6729 *unpredictable_code = UNPRED_R13;
78933a4a 6730 return true;
c507f10b
AV		 6731 }
6732 else if (rda == 0xf)
6733 {
6734 *unpredictable_code = UNPRED_R15;
78933a4a 6735 return true;
c507f10b
AV		 6736 }
6737
78933a4a 6738 return false;
c507f10b
AV		 6739 }
6740
14925797
AV		 6741 case MVE_VMULL_INT:
6742 {
6743 unsigned long Qd;
6744 unsigned long Qm;
6745 unsigned long Qn;
6746
6747 if (arm_decode_field (given, 20, 21) == 2)
6748 {
6749 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6750 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6751 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6752
6753 if ((Qd == Qn) || (Qd == Qm))
6754 {
6755 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6756 return true;
14925797
AV		 6757 }
6758 else
78933a4a 6759 return false;
14925797
AV		 6760 }
6761 else
78933a4a 6762 return false;
14925797
AV		 6763 }
6764
897b9bbc 6765 case MVE_VCMUL_FP:
14925797
AV		 6766 case MVE_VQDMULL_T1:
6767 {
6768 unsigned long Qd;
6769 unsigned long Qm;
6770 unsigned long Qn;
6771
6772 if (arm_decode_field (given, 28, 28) == 1)
6773 {
6774 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6775 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6776 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6777
6778 if ((Qd == Qn) || (Qd == Qm))
6779 {
6780 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6781 return true;
14925797
AV		 6782 }
6783 else
78933a4a 6784 return false;
14925797
AV		 6785 }
6786 else
78933a4a 6787 return false;
14925797
AV		 6788 }
6789
6790 case MVE_VQDMULL_T2:
6791 {
6792 unsigned long gpr = arm_decode_field (given, 0, 3);
6793 if (gpr == 0xd)
6794 {
6795 *unpredictable_code = UNPRED_R13;
78933a4a 6796 return true;
14925797
AV		 6797 }
6798 else if (gpr == 0xf)
6799 {
6800 *unpredictable_code = UNPRED_R15;
78933a4a 6801 return true;
14925797
AV		 6802 }
6803
6804 if (arm_decode_field (given, 28, 28) == 1)
6805 {
6806 unsigned long Qd
6807 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6808 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6809
a9d96ab9 6810 if (Qd == Qn)
14925797
AV		 6811 {
6812 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6813 return true;
14925797
AV		 6814 }
6815 else
78933a4a 6816 return false;
14925797
AV		 6817 }
6818
78933a4a 6819 return false;
14925797
AV		 6820 }
6821
d3b63143
AV		 6822 case MVE_VMLSLDAV:
6823 case MVE_VRMLSLDAVH:
6824 case MVE_VMLALDAV:
6825 case MVE_VADDLV:
6826 if (arm_decode_field (given, 20, 22) == 6)
6827 {
6828 *unpredictable_code = UNPRED_R13;
78933a4a 6829 return true;
d3b63143
AV		 6830 }
6831 else
78933a4a 6832 return false;
d3b63143 6833
1c8f2df8
AV		 6834 case MVE_VDWDUP:
6835 case MVE_VIWDUP:
6836 if (arm_decode_field (given, 1, 3) == 6)
6837 {
6838 *unpredictable_code = UNPRED_R13;
78933a4a 6839 return true;
1c8f2df8
AV		 6840 }
6841 else
78933a4a 6842 return false;
1c8f2df8 6843
897b9bbc
AV		 6844 case MVE_VCADD_VEC:
6845 case MVE_VHCADD:
6846 {
6847 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6848 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6849 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6850 {
6851 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6852 return true;
897b9bbc
AV		 6853 }
6854 else
78933a4a 6855 return false;
897b9bbc
AV		 6856 }
6857
6858 case MVE_VCADD_FP:
6859 {
6860 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6861 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6862 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6863 {
6864 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6865 return true;
897b9bbc
AV		 6866 }
6867 else
78933a4a 6868 return false;
897b9bbc
AV		 6869 }
6870
6871 case MVE_VCMLA_FP:
6872 {
6873 unsigned long Qda;
6874 unsigned long Qm;
6875 unsigned long Qn;
6876
6877 if (arm_decode_field (given, 20, 20) == 1)
6878 {
6879 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6880 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6881 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6882
6883 if ((Qda == Qn) || (Qda == Qm))
6884 {
6885 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6886 return true;
897b9bbc
AV		 6887 }
6888 else
78933a4a 6889 return false;
897b9bbc
AV		 6890 }
6891 else
78933a4a 6892 return false;
897b9bbc
AV		 6893
6894 }
6895
e523f101
AV		 6896 case MVE_VCTP:
6897 if (arm_decode_field (given, 16, 19) == 0xd)
6898 {
6899 *unpredictable_code = UNPRED_R13;
78933a4a 6900 return true;
e523f101
AV		 6901 }
6902 else
78933a4a 6903 return false;
e523f101 6904
14b456f2
AV		 6905 case MVE_VREV64:
6906 {
6907 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6908 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6909
6910 if (qd == qm)
6911 {
6912 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6913 return true;
14b456f2
AV		 6914 }
6915 else
78933a4a 6916 return false;
14b456f2
AV		 6917 }
6918
23d00a41
SD		 6919 case MVE_LSLL:
6920 case MVE_LSLLI:
6921 case MVE_LSRL:
6922 case MVE_ASRL:
6923 case MVE_ASRLI:
6924 case MVE_UQSHLL:
6925 case MVE_UQRSHLL:
6926 case MVE_URSHRL:
6927 case MVE_SRSHRL:
6928 case MVE_SQSHLL:
6929 case MVE_SQRSHRL:
6930 {
6931 unsigned long gpr = arm_decode_field (given, 9, 11);
6932 gpr = ((gpr << 1) | 1);
6933 if (gpr == 0xd)
6934 {
6935 *unpredictable_code = UNPRED_R13;
78933a4a 6936 return true;
23d00a41
SD		 6937 }
6938 else if (gpr == 0xf)
6939 {
6940 *unpredictable_code = UNPRED_R15;
78933a4a 6941 return true;
23d00a41
SD		 6942 }
6943
78933a4a 6944 return false;
23d00a41
SD		 6945 }
6946
143275ea 6947 default:
78933a4a 6948 return false;
143275ea
AV		 6949 }
6950}
c1e26897 6951
c507f10b
AV		 6952static void
6953print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6954{
6955 unsigned long op1 = arm_decode_field (given, 21, 22);
6956 unsigned long op2 = arm_decode_field (given, 5, 6);
6957 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6958 unsigned long index_operand, esize, targetBeat, idx;
c507f10b 6959 void *stream = info->stream;
6576bffe 6960 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 6961
6962 if ((op1 & 0x2) == 0x2)
6963 {
43dd7626 6964 index_operand = op2;
c507f10b
AV		 6965 esize = 8;
6966 }
6967 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6968 {
43dd7626 6969 index_operand = op2 >> 1;
c507f10b
AV		 6970 esize = 16;
6971 }
6972 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6973 {
43dd7626 6974 index_operand = 0;
c507f10b
AV		 6975 esize = 32;
6976 }
6977 else
6978 {
6576bffe 6979 func (stream, dis_style_text, "<undefined index>");
c507f10b
AV		 6980 return;
6981 }
6982
6983 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6984 idx = index_operand + targetBeat * (32/esize);
c507f10b 6985
6576bffe 6986 func (stream, dis_style_immediate, "%lu", idx);
c507f10b
AV		 6987}
6988
6989/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6990 in length and integer of floating-point type. */
6991static void
6992print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6993 unsigned int ibit_loc, const struct mopcode32 *insn)
6994{
6995 int bits = 0;
6996 int cmode = (given >> 8) & 0xf;
6997 int op = (given >> 5) & 0x1;
6998 unsigned long value = 0, hival = 0;
6999 unsigned shift;
7000 int size = 0;
7001 int isfloat = 0;
7002 void *stream = info->stream;
6576bffe 7003 fprintf_styled_ftype func = info->fprintf_styled_func;
c507f10b
AV		 7004
7005 /* On Neon the 'i' bit is at bit 24, on mve it is
7006 at bit 28. */
7007 bits |= ((given >> ibit_loc) & 1) << 7;
7008 bits |= ((given >> 16) & 7) << 4;
7009 bits |= ((given >> 0) & 15) << 0;
7010
7011 if (cmode < 8)
7012 {
7013 shift = (cmode >> 1) & 3;
7014 value = (unsigned long) bits << (8 * shift);
7015 size = 32;
7016 }
7017 else if (cmode < 12)
7018 {
7019 shift = (cmode >> 1) & 1;
7020 value = (unsigned long) bits << (8 * shift);
7021 size = 16;
7022 }
7023 else if (cmode < 14)
7024 {
7025 shift = (cmode & 1) + 1;
7026 value = (unsigned long) bits << (8 * shift);
7027 value |= (1ul << (8 * shift)) - 1;
7028 size = 32;
7029 }
7030 else if (cmode == 14)
7031 {
7032 if (op)
7033 {
7034 /* Bit replication into bytes. */
7035 int ix;
7036 unsigned long mask;
7037
7038 value = 0;
7039 hival = 0;
7040 for (ix = 7; ix >= 0; ix--)
7041 {
7042 mask = ((bits >> ix) & 1) ? 0xff : 0;
7043 if (ix <= 3)
7044 value = (value << 8) | mask;
7045 else
7046 hival = (hival << 8) | mask;
7047 }
7048 size = 64;
7049 }
7050 else
7051 {
7052 /* Byte replication. */
7053 value = (unsigned long) bits;
7054 size = 8;
7055 }
7056 }
7057 else if (!op)
7058 {
7059 /* Floating point encoding. */
7060 int tmp;
7061
7062 value = (unsigned long) (bits & 0x7f) << 19;
7063 value |= (unsigned long) (bits & 0x80) << 24;
7064 tmp = bits & 0x40 ? 0x3c : 0x40;
7065 value |= (unsigned long) tmp << 24;
7066 size = 32;
7067 isfloat = 1;
7068 }
7069 else
7070 {
6576bffe 7071 func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
c507f10b
AV		 7072 bits, cmode, op);
7073 size = 32;
7074 return;
7075 }
7076
279edac5
AM		 7077 /* printU determines whether the immediate value should be printed as
7078 unsigned. */
c507f10b
AV		 7079 unsigned printU = 0;
7080 switch (insn->mve_op)
7081 {
7082 default:
7083 break;
279edac5 7084 /* We want this for instructions that don't have a 'signed' type. */
c507f10b
AV		 7085 case MVE_VBIC_IMM:
7086 case MVE_VORR_IMM:
7087 case MVE_VMVN_IMM:
7088 case MVE_VMOV_IMM_TO_VEC:
7089 printU = 1;
7090 break;
7091 }
7092 switch (size)
7093 {
7094 case 8:
6576bffe
AB		 7095 func (stream, dis_style_immediate, "#%ld", value);
7096 func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
c507f10b
AV		 7097 break;
7098
7099 case 16:
6576bffe
AB		 7100 func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
7101 func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
c507f10b
AV		 7102 break;
7103
7104 case 32:
7105 if (isfloat)
7106 {
7107 unsigned char valbytes[4];
7108 double fvalue;
7109
7110 /* Do this a byte at a time so we don't have to
7111 worry about the host's endianness. */
7112 valbytes[0] = value & 0xff;
7113 valbytes[1] = (value >> 8) & 0xff;
7114 valbytes[2] = (value >> 16) & 0xff;
7115 valbytes[3] = (value >> 24) & 0xff;
7116
7117 floatformat_to_double
7118 (& floatformat_ieee_single_little, valbytes,
7119 & fvalue);
7120
6576bffe
AB		 7121 func (stream, dis_style_immediate, "#%.7g", fvalue);
7122 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
c507f10b
AV		 7123 }
7124 else
6576bffe
AB		 7125 {
7126 func (stream, dis_style_immediate,
7127 printU ? "#%lu" : "#%ld",
7128 (long) (((value & 0x80000000L) != 0)
7129 && !printU
7130 ? value | ~0xffffffffL : value));
7131 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
7132 }
c507f10b
AV		 7133 break;
7134
7135 case 64:
6576bffe 7136 func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
c507f10b
AV		 7137 break;
7138
7139 default:
7140 abort ();
7141 }
7142
7143}
7144
73cd51e5
AV		 7145static void
7146print_mve_undefined (struct disassemble_info *info,
7147 enum mve_undefined undefined_code)
7148{
7149 void *stream = info->stream;
6576bffe 7150 fprintf_styled_ftype func = info->fprintf_styled_func;
d8521074
AB		 7151 /* Initialize REASON to avoid compiler warning about uninitialized
7152 usage, though such usage should be impossible. */
7153 const char *reason = "??";
73cd51e5
AV		 7154
7155 switch (undefined_code)
7156 {
ed63aa17 7157 case UNDEF_SIZE:
6576bffe 7158 reason = "illegal size";
ed63aa17
AV		 7159 break;
7160
aef6d006 7161 case UNDEF_SIZE_0:
6576bffe 7162 reason = "size equals zero";
aef6d006
AV		 7163 break;
7164
c507f10b 7165 case UNDEF_SIZE_2:
6576bffe 7166 reason = "size equals two";
c507f10b
AV		 7167 break;
7168
9743db03 7169 case UNDEF_SIZE_3:
6576bffe 7170 reason = "size equals three";
9743db03
AV		 7171 break;
7172
aef6d006 7173 case UNDEF_SIZE_LE_1:
6576bffe 7174 reason = "size <= 1";
aef6d006
AV		 7175 break;
7176
14b456f2 7177 case UNDEF_SIZE_NOT_0:
6576bffe 7178 reason = "size not equal to 0";
14b456f2
AV		 7179 break;
7180
ef1576a1 7181 case UNDEF_SIZE_NOT_2:
6576bffe 7182 reason = "size not equal to 2";
ef1576a1
AV		 7183 break;
7184
7185 case UNDEF_SIZE_NOT_3:
6576bffe 7186 reason = "size not equal to 3";
ef1576a1
AV		 7187 break;
7188
7189 case UNDEF_NOT_UNS_SIZE_0:
6576bffe 7190 reason = "not unsigned and size = zero";
ef1576a1
AV		 7191 break;
7192
7193 case UNDEF_NOT_UNS_SIZE_1:
6576bffe 7194 reason = "not unsigned and size = one";
ef1576a1
AV		 7195 break;
7196
7197 case UNDEF_NOT_UNSIGNED:
6576bffe 7198 reason = "not unsigned";
ef1576a1
AV		 7199 break;
7200
bf0b396d 7201 case UNDEF_VCVT_IMM6:
6576bffe 7202 reason = "invalid imm6";
bf0b396d
AV		 7203 break;
7204
7205 case UNDEF_VCVT_FSI_IMM6:
6576bffe 7206 reason = "fsi = 0 and invalid imm6";
bf0b396d
AV		 7207 break;
7208
c507f10b 7209 case UNDEF_BAD_OP1_OP2:
6576bffe 7210 reason = "bad size with op2 = 2 and op1 = 0 or 1";
c507f10b
AV		 7211 break;
7212
7213 case UNDEF_BAD_U_OP1_OP2:
6576bffe 7214 reason = "unsigned with op2 = 0 and op1 = 0 or 1";
c507f10b
AV		 7215 break;
7216
7217 case UNDEF_OP_0_BAD_CMODE:
6576bffe 7218 reason = "op field equal 0 and bad cmode";
c507f10b
AV		 7219 break;
7220
d3b63143 7221 case UNDEF_XCHG_UNS:
6576bffe 7222 reason = "exchange and unsigned together";
d3b63143
AV		 7223 break;
7224
73cd51e5 7225 case UNDEF_NONE:
6576bffe 7226 reason = "";
73cd51e5
AV		 7227 break;
7228 }
7229
6576bffe 7230 func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
73cd51e5
AV		 7231}
7232
7233static void
7234print_mve_unpredictable (struct disassemble_info *info,
7235 enum mve_unpredictable unpredict_code)
7236{
7237 void *stream = info->stream;
6576bffe 7238 fprintf_styled_ftype func = info->fprintf_styled_func;
2df82cd4
AB		 7239 /* Initialize REASON to avoid compiler warning about uninitialized
7240 usage, though such usage should be impossible. */
7241 const char *reason = "??";
73cd51e5
AV		 7242
7243 switch (unpredict_code)
7244 {
7245 case UNPRED_IT_BLOCK:
6576bffe 7246 reason = "mve instruction in it block";
73cd51e5
AV		 7247 break;
7248
143275ea 7249 case UNPRED_FCA_0_FCB_1:
6576bffe 7250 reason = "condition bits, fca = 0 and fcb = 1";
143275ea
AV		 7251 break;
7252
7253 case UNPRED_R13:
6576bffe 7254 reason = "use of r13 (sp)";
143275ea
AV		 7255 break;
7256
9743db03 7257 case UNPRED_R15:
6576bffe 7258 reason = "use of r15 (pc)";
9743db03
AV		 7259 break;
7260
04d54ace 7261 case UNPRED_Q_GT_4:
6576bffe 7262 reason = "start register block > r4";
04d54ace
AV		 7263 break;
7264
7265 case UNPRED_Q_GT_6:
6576bffe 7266 reason = "start register block > r6";
04d54ace
AV		 7267 break;
7268
7269 case UNPRED_R13_AND_WB:
6576bffe 7270 reason = "use of r13 and write back";
04d54ace
AV		 7271 break;
7272
ef1576a1 7273 case UNPRED_Q_REGS_EQUAL:
6576bffe 7274 reason = "same vector register used for destination and other operand";
ef1576a1
AV		 7275 break;
7276
7277 case UNPRED_OS:
6576bffe 7278 reason = "use of offset scaled";
ef1576a1
AV		 7279 break;
7280
bf0b396d 7281 case UNPRED_GP_REGS_EQUAL:
6576bffe 7282 reason = "same general-purpose register used for both operands";
bf0b396d
AV		 7283 break;
7284
c507f10b 7285 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6576bffe 7286 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7287 break;
7288
7289 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6576bffe 7290 reason = "use of identical q registers and size = 1";
c507f10b
AV		 7291 break;
7292
73cd51e5 7293 case UNPRED_NONE:
6576bffe 7294 reason = "";
73cd51e5
AV		 7295 break;
7296 }
6576bffe
AB		 7297
7298 func (stream, dis_style_comment_start, "%s: %s",
7299 UNPREDICTABLE_INSTRUCTION, reason);
73cd51e5
AV		 7300}
7301
04d54ace
AV		 7302/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7303
7304static void
7305print_mve_register_blocks (struct disassemble_info *info,
7306 unsigned long given,
7307 enum mve_instructions matched_insn)
7308{
7309 void *stream = info->stream;
6576bffe 7310 fprintf_styled_ftype func = info->fprintf_styled_func;
04d54ace
AV		 7311
7312 unsigned long q_reg_start = arm_decode_field_multiple (given,
7313 13, 15,
7314 22, 22);
7315 switch (matched_insn)
7316 {
7317 case MVE_VLD2:
7318 case MVE_VST2:
7319 if (q_reg_start <= 6)
6576bffe
AB		 7320 {
7321 func (stream, dis_style_text, "{");
7322 func (stream, dis_style_register, "q%ld", q_reg_start);
7323 func (stream, dis_style_text, ", ");
7324 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7325 func (stream, dis_style_text, "}");
7326 }
04d54ace 7327 else
6576bffe 7328 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7329 break;
7330
7331 case MVE_VLD4:
7332 case MVE_VST4:
7333 if (q_reg_start <= 4)
6576bffe
AB		 7334 {
7335 func (stream, dis_style_text, "{");
7336 func (stream, dis_style_register, "q%ld", q_reg_start);
7337 func (stream, dis_style_text, ", ");
7338 func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7339 func (stream, dis_style_text, ", ");
7340 func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7341 func (stream, dis_style_text, ", ");
7342 func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7343 func (stream, dis_style_text, "}");
7344 }
04d54ace 7345 else
6576bffe 7346 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
04d54ace
AV		 7347 break;
7348
7349 default:
7350 break;
7351 }
7352}
7353
bf0b396d
AV		 7354static void
7355print_mve_rounding_mode (struct disassemble_info *info,
7356 unsigned long given,
7357 enum mve_instructions matched_insn)
7358{
7359 void *stream = info->stream;
6576bffe 7360 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7361
7362 switch (matched_insn)
7363 {
7364 case MVE_VCVT_FROM_FP_TO_INT:
7365 {
7366 switch (arm_decode_field (given, 8, 9))
7367 {
7368 case 0:
6576bffe 7369 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7370 break;
7371
7372 case 1:
6576bffe 7373 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7374 break;
7375
7376 case 2:
6576bffe 7377 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7378 break;
7379
7380 case 3:
6576bffe 7381 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7382 break;
7383
7384 default:
7385 break;
7386 }
7387 }
7388 break;
7389
7390 case MVE_VRINT_FP:
7391 {
7392 switch (arm_decode_field (given, 7, 9))
7393 {
7394 case 0:
6576bffe 7395 func (stream, dis_style_mnemonic, "n");
bf0b396d
AV		 7396 break;
7397
7398 case 1:
6576bffe 7399 func (stream, dis_style_mnemonic, "x");
bf0b396d
AV		 7400 break;
7401
7402 case 2:
6576bffe 7403 func (stream, dis_style_mnemonic, "a");
bf0b396d
AV		 7404 break;
7405
7406 case 3:
6576bffe 7407 func (stream, dis_style_mnemonic, "z");
bf0b396d
AV		 7408 break;
7409
7410 case 5:
6576bffe 7411 func (stream, dis_style_mnemonic, "m");
bf0b396d
AV		 7412 break;
7413
7414 case 7:
6576bffe 7415 func (stream, dis_style_mnemonic, "p");
bf0b396d
AV		 7416
7417 case 4:
7418 case 6:
7419 default:
7420 break;
7421 }
7422 }
7423 break;
7424
7425 default:
7426 break;
7427 }
7428}
7429
7430static void
7431print_mve_vcvt_size (struct disassemble_info *info,
7432 unsigned long given,
7433 enum mve_instructions matched_insn)
7434{
7435 unsigned long mode = 0;
7436 void *stream = info->stream;
6576bffe 7437 fprintf_styled_ftype func = info->fprintf_styled_func;
bf0b396d
AV		 7438
7439 switch (matched_insn)
7440 {
7441 case MVE_VCVT_FP_FIX_VEC:
7442 {
7443 mode = (((given & 0x200) >> 7)
7444 | ((given & 0x10000000) >> 27)
7445 | ((given & 0x100) >> 8));
7446
7447 switch (mode)
7448 {
7449 case 0:
6576bffe 7450 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7451 break;
7452
7453 case 1:
6576bffe 7454 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7455 break;
7456
7457 case 2:
6576bffe 7458 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7459 break;
7460
7461 case 3:
6576bffe 7462 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7463 break;
7464
7465 case 4:
6576bffe 7466 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7467 break;
7468
7469 case 5:
6576bffe 7470 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7471 break;
7472
7473 case 6:
6576bffe 7474 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7475 break;
7476
7477 case 7:
6576bffe 7478 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7479 break;
7480
7481 default:
7482 break;
7483 }
7484 break;
7485 }
7486 case MVE_VCVT_BETWEEN_FP_INT:
7487 {
7488 unsigned long size = arm_decode_field (given, 18, 19);
7489 unsigned long op = arm_decode_field (given, 7, 8);
7490
7491 if (size == 1)
7492 {
7493 switch (op)
7494 {
7495 case 0:
6576bffe 7496 func (stream, dis_style_mnemonic, "f16.s16");
bf0b396d
AV		 7497 break;
7498
7499 case 1:
6576bffe 7500 func (stream, dis_style_mnemonic, "f16.u16");
bf0b396d
AV		 7501 break;
7502
7503 case 2:
6576bffe 7504 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7505 break;
7506
7507 case 3:
6576bffe 7508 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7509 break;
7510
7511 default:
7512 break;
7513 }
7514 }
7515 else if (size == 2)
7516 {
7517 switch (op)
7518 {
7519 case 0:
6576bffe 7520 func (stream, dis_style_mnemonic, "f32.s32");
bf0b396d
AV		 7521 break;
7522
7523 case 1:
6576bffe 7524 func (stream, dis_style_mnemonic, "f32.u32");
bf0b396d
AV		 7525 break;
7526
7527 case 2:
6576bffe 7528 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7529 break;
7530
7531 case 3:
6576bffe 7532 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7533 break;
7534 }
7535 }
7536 }
7537 break;
7538
7539 case MVE_VCVT_FP_HALF_FP:
7540 {
7541 unsigned long op = arm_decode_field (given, 28, 28);
7542 if (op == 0)
6576bffe 7543 func (stream, dis_style_mnemonic, "f16.f32");
bf0b396d 7544 else if (op == 1)
6576bffe 7545 func (stream, dis_style_mnemonic, "f32.f16");
bf0b396d
AV		 7546 }
7547 break;
7548
7549 case MVE_VCVT_FROM_FP_TO_INT:
7550 {
7551 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7552
7553 switch (size)
7554 {
7555 case 2:
6576bffe 7556 func (stream, dis_style_mnemonic, "s16.f16");
bf0b396d
AV		 7557 break;
7558
7559 case 3:
6576bffe 7560 func (stream, dis_style_mnemonic, "u16.f16");
bf0b396d
AV		 7561 break;
7562
7563 case 4:
6576bffe 7564 func (stream, dis_style_mnemonic, "s32.f32");
bf0b396d
AV		 7565 break;
7566
7567 case 5:
6576bffe 7568 func (stream, dis_style_mnemonic, "u32.f32");
bf0b396d
AV		 7569 break;
7570
7571 default:
7572 break;
7573 }
7574 }
7575 break;
7576
7577 default:
7578 break;
7579 }
7580}
7581
897b9bbc
AV		 7582static void
7583print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7584 unsigned long rot_width)
7585{
7586 void *stream = info->stream;
6576bffe 7587 fprintf_styled_ftype func = info->fprintf_styled_func;
897b9bbc
AV		 7588
7589 if (rot_width == 1)
7590 {
7591 switch (rot)
7592 {
7593 case 0:
6576bffe 7594 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7595 break;
7596 case 1:
6576bffe 7597 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7598 break;
7599 default:
7600 break;
7601 }
7602 }
7603 else if (rot_width == 2)
7604 {
7605 switch (rot)
7606 {
7607 case 0:
6576bffe 7608 func (stream, dis_style_immediate, "0");
897b9bbc
AV		 7609 break;
7610 case 1:
6576bffe 7611 func (stream, dis_style_immediate, "90");
897b9bbc
AV		 7612 break;
7613 case 2:
6576bffe 7614 func (stream, dis_style_immediate, "180");
897b9bbc
AV		 7615 break;
7616 case 3:
6576bffe 7617 func (stream, dis_style_immediate, "270");
897b9bbc
AV		 7618 break;
7619 default:
7620 break;
7621 }
7622 }
7623}
7624
143275ea
AV		 7625static void
7626print_instruction_predicate (struct disassemble_info *info)
7627{
7628 void *stream = info->stream;
6576bffe 7629 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7630
7631 if (vpt_block_state.next_pred_state == PRED_THEN)
6576bffe 7632 func (stream, dis_style_mnemonic, "t");
143275ea 7633 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6576bffe 7634 func (stream, dis_style_mnemonic, "e");
143275ea
AV		 7635}
7636
7637static void
7638print_mve_size (struct disassemble_info *info,
7639 unsigned long size,
7640 enum mve_instructions matched_insn)
7641{
7642 void *stream = info->stream;
6576bffe 7643 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 7644
7645 switch (matched_insn)
7646 {
66dcaa5d
AV		 7647 case MVE_VABAV:
7648 case MVE_VABD_VEC:
7649 case MVE_VABS_FP:
7650 case MVE_VABS_VEC:
7651 case MVE_VADD_VEC_T1:
7652 case MVE_VADD_VEC_T2:
d3b63143 7653 case MVE_VADDV:
e523f101 7654 case MVE_VBRSR:
897b9bbc 7655 case MVE_VCADD_VEC:
e523f101
AV		 7656 case MVE_VCLS:
7657 case MVE_VCLZ:
143275ea
AV		 7658 case MVE_VCMP_VEC_T1:
7659 case MVE_VCMP_VEC_T2:
7660 case MVE_VCMP_VEC_T3:
7661 case MVE_VCMP_VEC_T4:
7662 case MVE_VCMP_VEC_T5:
7663 case MVE_VCMP_VEC_T6:
e523f101 7664 case MVE_VCTP:
1c8f2df8
AV		 7665 case MVE_VDDUP:
7666 case MVE_VDWDUP:
9743db03
AV		 7667 case MVE_VHADD_T1:
7668 case MVE_VHADD_T2:
897b9bbc 7669 case MVE_VHCADD:
9743db03
AV		 7670 case MVE_VHSUB_T1:
7671 case MVE_VHSUB_T2:
1c8f2df8
AV		 7672 case MVE_VIDUP:
7673 case MVE_VIWDUP:
04d54ace
AV		 7674 case MVE_VLD2:
7675 case MVE_VLD4:
ef1576a1
AV		 7676 case MVE_VLDRB_GATHER_T1:
7677 case MVE_VLDRH_GATHER_T2:
7678 case MVE_VLDRW_GATHER_T3:
7679 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7680 case MVE_VLDRB_T1:
7681 case MVE_VLDRH_T2:
56858bea
AV		 7682 case MVE_VMAX:
7683 case MVE_VMAXA:
7684 case MVE_VMAXV:
7685 case MVE_VMAXAV:
7686 case MVE_VMIN:
7687 case MVE_VMINA:
7688 case MVE_VMINV:
7689 case MVE_VMINAV:
7690 case MVE_VMLA:
d3b63143 7691 case MVE_VMLAS:
f49bb598
AV		 7692 case MVE_VMUL_VEC_T1:
7693 case MVE_VMUL_VEC_T2:
7694 case MVE_VMULH:
7695 case MVE_VRMULH:
7696 case MVE_VMULL_INT:
7697 case MVE_VNEG_FP:
7698 case MVE_VNEG_VEC:
143275ea
AV		 7699 case MVE_VPT_VEC_T1:
7700 case MVE_VPT_VEC_T2:
7701 case MVE_VPT_VEC_T3:
7702 case MVE_VPT_VEC_T4:
7703 case MVE_VPT_VEC_T5:
7704 case MVE_VPT_VEC_T6:
14b456f2
AV		 7705 case MVE_VQABS:
7706 case MVE_VQADD_T1:
7707 case MVE_VQADD_T2:
d3b63143
AV		 7708 case MVE_VQDMLADH:
7709 case MVE_VQRDMLADH:
7710 case MVE_VQDMLAH:
7711 case MVE_VQRDMLAH:
7712 case MVE_VQDMLASH:
7713 case MVE_VQRDMLASH:
7714 case MVE_VQDMLSDH:
7715 case MVE_VQRDMLSDH:
7716 case MVE_VQDMULH_T1:
7717 case MVE_VQRDMULH_T2:
7718 case MVE_VQDMULH_T3:
7719 case MVE_VQRDMULH_T4:
14b456f2 7720 case MVE_VQNEG:
ed63aa17
AV		 7721 case MVE_VQRSHL_T1:
7722 case MVE_VQRSHL_T2:
7723 case MVE_VQSHL_T1:
7724 case MVE_VQSHL_T4:
14b456f2
AV		 7725 case MVE_VQSUB_T1:
7726 case MVE_VQSUB_T2:
7727 case MVE_VREV32:
7728 case MVE_VREV64:
9743db03 7729 case MVE_VRHADD:
bf0b396d 7730 case MVE_VRINT_FP:
ed63aa17
AV		 7731 case MVE_VRSHL_T1:
7732 case MVE_VRSHL_T2:
7733 case MVE_VSHL_T2:
7734 case MVE_VSHL_T3:
7735 case MVE_VSHLL_T2:
04d54ace
AV		 7736 case MVE_VST2:
7737 case MVE_VST4:
ef1576a1
AV		 7738 case MVE_VSTRB_SCATTER_T1:
7739 case MVE_VSTRH_SCATTER_T2:
7740 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7741 case MVE_VSTRB_T1:
7742 case MVE_VSTRH_T2:
66dcaa5d
AV		 7743 case MVE_VSUB_VEC_T1:
7744 case MVE_VSUB_VEC_T2:
143275ea 7745 if (size <= 3)
6576bffe 7746 func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
143275ea 7747 else
6576bffe 7748 func (stream, dis_style_text, "<undef size>");
143275ea
AV		 7749 break;
7750
66dcaa5d
AV		 7751 case MVE_VABD_FP:
7752 case MVE_VADD_FP_T1:
7753 case MVE_VADD_FP_T2:
7754 case MVE_VSUB_FP_T1:
7755 case MVE_VSUB_FP_T2:
143275ea
AV		 7756 case MVE_VCMP_FP_T1:
7757 case MVE_VCMP_FP_T2:
9743db03
AV		 7758 case MVE_VFMA_FP_SCALAR:
7759 case MVE_VFMA_FP:
7760 case MVE_VFMS_FP:
7761 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7762 case MVE_VMAXNM_FP:
7763 case MVE_VMAXNMA_FP:
7764 case MVE_VMAXNMV_FP:
7765 case MVE_VMAXNMAV_FP:
7766 case MVE_VMINNM_FP:
7767 case MVE_VMINNMA_FP:
7768 case MVE_VMINNMV_FP:
7769 case MVE_VMINNMAV_FP:
f49bb598
AV		 7770 case MVE_VMUL_FP_T1:
7771 case MVE_VMUL_FP_T2:
143275ea
AV		 7772 case MVE_VPT_FP_T1:
7773 case MVE_VPT_FP_T2:
7774 if (size == 0)
6576bffe 7775 func (stream, dis_style_mnemonic, "32");
143275ea 7776 else if (size == 1)
6576bffe 7777 func (stream, dis_style_mnemonic, "16");
143275ea
AV		 7778 break;
7779
897b9bbc
AV		 7780 case MVE_VCADD_FP:
7781 case MVE_VCMLA_FP:
7782 case MVE_VCMUL_FP:
d3b63143
AV		 7783 case MVE_VMLADAV_T1:
7784 case MVE_VMLALDAV:
7785 case MVE_VMLSDAV_T1:
7786 case MVE_VMLSLDAV:
14925797
AV		 7787 case MVE_VMOVN:
7788 case MVE_VQDMULL_T1:
7789 case MVE_VQDMULL_T2:
7790 case MVE_VQMOVN:
7791 case MVE_VQMOVUN:
7792 if (size == 0)
6576bffe 7793 func (stream, dis_style_mnemonic, "16");
14925797 7794 else if (size == 1)
6576bffe 7795 func (stream, dis_style_mnemonic, "32");
14925797
AV		 7796 break;
7797
7798 case MVE_VMOVL:
7799 if (size == 1)
6576bffe 7800 func (stream, dis_style_mnemonic, "8");
14925797 7801 else if (size == 2)
6576bffe 7802 func (stream, dis_style_mnemonic, "16");
14925797
AV		 7803 break;
7804
9743db03
AV		 7805 case MVE_VDUP:
7806 switch (size)
7807 {
7808 case 0:
6576bffe 7809 func (stream, dis_style_mnemonic, "32");
9743db03
AV		 7810 break;
7811 case 1:
6576bffe 7812 func (stream, dis_style_mnemonic, "16");
9743db03
AV		 7813 break;
7814 case 2:
6576bffe 7815 func (stream, dis_style_mnemonic, "8");
9743db03
AV		 7816 break;
7817 default:
7818 break;
7819 }
7820 break;
7821
c507f10b
AV		 7822 case MVE_VMOV_GP_TO_VEC_LANE:
7823 case MVE_VMOV_VEC_LANE_TO_GP:
7824 switch (size)
7825 {
7826 case 0: case 4:
6576bffe 7827 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7828 break;
7829
7830 case 1: case 3:
7831 case 5: case 7:
6576bffe 7832 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7833 break;
7834
7835 case 8: case 9: case 10: case 11:
7836 case 12: case 13: case 14: case 15:
6576bffe 7837 func (stream, dis_style_mnemonic, "8");
c507f10b
AV		 7838 break;
7839
7840 default:
7841 break;
7842 }
7843 break;
7844
7845 case MVE_VMOV_IMM_TO_VEC:
7846 switch (size)
7847 {
7848 case 0: case 4: case 8:
7849 case 12: case 24: case 26:
6576bffe 7850 func (stream, dis_style_mnemonic, "i32");
c507f10b
AV		 7851 break;
7852 case 16: case 20:
6576bffe 7853 func (stream, dis_style_mnemonic, "i16");
c507f10b
AV		 7854 break;
7855 case 28:
6576bffe 7856 func (stream, dis_style_mnemonic, "i8");
c507f10b
AV		 7857 break;
7858 case 29:
6576bffe 7859 func (stream, dis_style_mnemonic, "i64");
c507f10b
AV		 7860 break;
7861 case 30:
6576bffe 7862 func (stream, dis_style_mnemonic, "f32");
c507f10b
AV		 7863 break;
7864 default:
7865 break;
7866 }
7867 break;
7868
14925797
AV		 7869 case MVE_VMULL_POLY:
7870 if (size == 0)
6576bffe 7871 func (stream, dis_style_mnemonic, "p8");
14925797 7872 else if (size == 1)
6576bffe 7873 func (stream, dis_style_mnemonic, "p16");
14925797
AV		 7874 break;
7875
c507f10b
AV		 7876 case MVE_VMVN_IMM:
7877 switch (size)
7878 {
7879 case 0: case 2: case 4:
7880 case 6: case 12: case 13:
6576bffe 7881 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7882 break;
7883
7884 case 8: case 10:
6576bffe 7885 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7886 break;
7887
7888 default:
7889 break;
7890 }
7891 break;
7892
7893 case MVE_VBIC_IMM:
7894 case MVE_VORR_IMM:
7895 switch (size)
7896 {
7897 case 1: case 3:
7898 case 5: case 7:
6576bffe 7899 func (stream, dis_style_mnemonic, "32");
c507f10b
AV		 7900 break;
7901
7902 case 9: case 11:
6576bffe 7903 func (stream, dis_style_mnemonic, "16");
c507f10b
AV		 7904 break;
7905
7906 default:
7907 break;
7908 }
7909 break;
7910
ed63aa17
AV		 7911 case MVE_VQSHRN:
7912 case MVE_VQSHRUN:
7913 case MVE_VQRSHRN:
7914 case MVE_VQRSHRUN:
7915 case MVE_VRSHRN:
7916 case MVE_VSHRN:
7917 {
7918 switch (size)
7919 {
7920 case 1:
6576bffe 7921 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7922 break;
7923
7924 case 2: case 3:
6576bffe 7925 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7926 break;
7927
7928 default:
7929 break;
7930 }
7931 }
7932 break;
7933
7934 case MVE_VQSHL_T2:
7935 case MVE_VQSHLU_T3:
7936 case MVE_VRSHR:
7937 case MVE_VSHL_T1:
7938 case MVE_VSHLL_T1:
7939 case MVE_VSHR:
7940 case MVE_VSLI:
7941 case MVE_VSRI:
7942 {
7943 switch (size)
7944 {
7945 case 1:
6576bffe 7946 func (stream, dis_style_mnemonic, "8");
ed63aa17
AV		 7947 break;
7948
7949 case 2: case 3:
6576bffe 7950 func (stream, dis_style_mnemonic, "16");
ed63aa17
AV		 7951 break;
7952
7953 case 4: case 5: case 6: case 7:
6576bffe 7954 func (stream, dis_style_mnemonic, "32");
ed63aa17
AV		 7955 break;
7956
7957 default:
7958 break;
7959 }
7960 }
7961 break;
7962
143275ea
AV		 7963 default:
7964 break;
7965 }
7966}
7967
f9d6cf2e
AC		 7968/* Return true if INSN is a shift insn with an immediate shift amount
7969 which needs decoding as per print_mve_shift_n. */
7970
7971static bool
7972mve_shift_insn_p (enum mve_instructions insn)
7973{
7974 switch (insn)
7975 {
7976 case MVE_VQSHL_T2:
7977 case MVE_VQSHLU_T3:
cd714ac0
AC		 7978 case MVE_VQSHRN:
7979 case MVE_VQSHRUN:
7980 case MVE_VQRSHRN:
7981 case MVE_VQRSHRUN:
f9d6cf2e
AC		 7982 case MVE_VRSHR:
7983 case MVE_VRSHRN:
7984 case MVE_VSHL_T1:
7985 case MVE_VSHLL_T1:
7986 case MVE_VSHR:
7987 case MVE_VSHRN:
7988 case MVE_VSLI:
7989 case MVE_VSRI:
7990 return true;
7991 default:
7992 return false;
7993 }
7994}
7995
ed63aa17
AV		 7996static void
7997print_mve_shift_n (struct disassemble_info *info, long given,
7998 enum mve_instructions matched_insn)
7999{
8000 void *stream = info->stream;
6576bffe 8001 fprintf_styled_ftype func = info->fprintf_styled_func;
ed63aa17
AV		 8002
8003 int startAt0
8004 = matched_insn == MVE_VQSHL_T2
8005 || matched_insn == MVE_VQSHLU_T3
8006 || matched_insn == MVE_VSHL_T1
8007 || matched_insn == MVE_VSHLL_T1
8008 || matched_insn == MVE_VSLI;
8009
8010 unsigned imm6 = (given & 0x3f0000) >> 16;
8011
8012 if (matched_insn == MVE_VSHLL_T1)
8013 imm6 &= 0x1f;
8014
8015 unsigned shiftAmount = 0;
8016 if ((imm6 & 0x20) != 0)
8017 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
8018 else if ((imm6 & 0x10) != 0)
8019 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
8020 else if ((imm6 & 0x08) != 0)
8021 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
8022 else
8023 print_mve_undefined (info, UNDEF_SIZE_0);
8024
6576bffe 8025 func (stream, dis_style_immediate, "%u", shiftAmount);
ed63aa17
AV		 8026}
8027
143275ea
AV		 8028static void
8029print_vec_condition (struct disassemble_info *info, long given,
8030 enum mve_instructions matched_insn)
8031{
8032 void *stream = info->stream;
6576bffe 8033 fprintf_styled_ftype func = info->fprintf_styled_func;
143275ea
AV		 8034 long vec_cond = 0;
8035
8036 switch (matched_insn)
8037 {
8038 case MVE_VPT_FP_T1:
8039 case MVE_VCMP_FP_T1:
8040 vec_cond = (((given & 0x1000) >> 10)
8041 | ((given & 1) << 1)
8042 | ((given & 0x0080) >> 7));
6576bffe 8043 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8044 break;
8045
8046 case MVE_VPT_FP_T2:
8047 case MVE_VCMP_FP_T2:
8048 vec_cond = (((given & 0x1000) >> 10)
8049 | ((given & 0x0020) >> 4)
8050 | ((given & 0x0080) >> 7));
6576bffe 8051 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8052 break;
8053
8054 case MVE_VPT_VEC_T1:
8055 case MVE_VCMP_VEC_T1:
8056 vec_cond = (given & 0x0080) >> 7;
6576bffe 8057 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8058 break;
8059
8060 case MVE_VPT_VEC_T2:
8061 case MVE_VCMP_VEC_T2:
8062 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 8063 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8064 break;
8065
8066 case MVE_VPT_VEC_T3:
8067 case MVE_VCMP_VEC_T3:
8068 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6576bffe 8069 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8070 break;
8071
8072 case MVE_VPT_VEC_T4:
8073 case MVE_VCMP_VEC_T4:
8074 vec_cond = (given & 0x0080) >> 7;
6576bffe 8075 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8076 break;
8077
8078 case MVE_VPT_VEC_T5:
8079 case MVE_VCMP_VEC_T5:
8080 vec_cond = 2 | ((given & 0x0080) >> 7);
6576bffe 8081 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8082 break;
8083
8084 case MVE_VPT_VEC_T6:
8085 case MVE_VCMP_VEC_T6:
8086 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6576bffe 8087 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
143275ea
AV		 8088 break;
8089
8090 case MVE_NONE:
8091 case MVE_VPST:
8092 default:
8093 break;
8094 }
8095}
8096
8097#define W_BIT 21
8098#define I_BIT 22
8099#define U_BIT 23
8100#define P_BIT 24
8101
8102#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8103#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8104#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8105#define PRE_BIT_SET (given & (1 << P_BIT))
8106
6576bffe
AB		 8107/* The assembler string for an instruction can include %{X:...%} patterns,
8108 where the 'X' is one of the characters understood by this function.
8109
8110 This function takes the X character, and returns a new style. This new
8111 style will be used by the caller to temporarily change the current base
8112 style. */
8113
8114static enum disassembler_style
8115decode_base_style (const char x)
8116{
8117 switch (x)
8118 {
8119 case 'A': return dis_style_address;
8120 case 'B': return dis_style_sub_mnemonic;
8121 case 'C': return dis_style_comment_start;
8122 case 'D': return dis_style_assembler_directive;
8123 case 'I': return dis_style_immediate;
8124 case 'M': return dis_style_mnemonic;
8125 case 'O': return dis_style_address_offset;
8126 case 'R': return dis_style_register;
8127 case 'S': return dis_style_symbol;
8128 case 'T': return dis_style_text;
8129 default:
8130 abort ();
8131 }
8132}
143275ea 8133
8f06b2d8
PB		 8134/* Print one coprocessor instruction on INFO->STREAM.
8135 Return TRUE if the instuction matched, FALSE if this is not a
8136 recognised coprocessor instruction. */
8137
78933a4a 8138static bool
33593eaf
MM		 8139print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8140 bfd_vma pc,
8141 struct disassemble_info *info,
8142 long given,
78933a4a 8143 bool thumb)
8f06b2d8 8144{
6b0dd094 8145 const struct sopcode32 *insn;
8f06b2d8 8146 void *stream = info->stream;
6576bffe 8147 fprintf_styled_ftype func = info->fprintf_styled_func;
8f06b2d8 8148 unsigned long mask;
2edcd244 8149 unsigned long value = 0;
c22aaad1 8150 int cond;
8afc7bea 8151 int cp_num;
823d2571
TG		 8152 struct arm_private_data *private_data = info->private_data;
8153 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 8154 arm_feature_set arm_ext_v8_1m_main =
8155 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
6576bffe
AB		 8156 enum disassembler_style base_style = dis_style_mnemonic;
8157 enum disassembler_style old_base_style = base_style;
823d2571 8158
5b616bef 8159 allowed_arches = private_data->features;
8f06b2d8 8160
33593eaf 8161 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 8162 {
ff4a8d2b 8163 unsigned long u_reg = 16;
78933a4a 8164 bool is_unpredictable = false;
05413229 8165 signed long value_in_comment = 0;
0313a2b8
NC		 8166 const char *c;
8167
823d2571 8168 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 8169 switch (insn->value)
8170 {
8171 case SENTINEL_IWMMXT_START:
8172 if (info->mach != bfd_mach_arm_XScale
8173 && info->mach != bfd_mach_arm_iWMMXt
8174 && info->mach != bfd_mach_arm_iWMMXt2)
8175 do
8176 insn++;
823d2571
TG		 8177 while ((! ARM_FEATURE_ZERO (insn->arch))
8178 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8179 continue;
8180
8181 case SENTINEL_IWMMXT_END:
8182 continue;
8183
8184 case SENTINEL_GENERIC_START:
5b616bef 8185 allowed_arches = private_data->features;
05413229
NC		 8186 continue;
8187
8188 default:
8189 abort ();
8190 }
8f06b2d8
PB		 8191
8192 mask = insn->mask;
8193 value = insn->value;
8afc7bea
RL		 8194 cp_num = (given >> 8) & 0xf;
8195
8f06b2d8
PB		 8196 if (thumb)
8197 {
8198 /* The high 4 bits are 0xe for Arm conditional instructions, and
8199 0xe for arm unconditional instructions. The rest of the
8200 encoding is the same. */
8201 mask |= 0xf0000000;
8202 value |= 0xe0000000;
c22aaad1
PB		 8203 if (ifthen_state)
8204 cond = IFTHEN_COND;
8205 else
e2efe87d 8206 cond = COND_UNCOND;
8f06b2d8
PB		 8207 }
8208 else
8209 {
8210 /* Only match unconditional instuctions against unconditional
8211 patterns. */
8212 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8213 {
8214 mask |= 0xf0000000;
e2efe87d 8215 cond = COND_UNCOND;
c22aaad1
PB		 8216 }
8217 else
8218 {
8219 cond = (given >> 28) & 0xf;
8220 if (cond == 0xe)
e2efe87d 8221 cond = COND_UNCOND;
c22aaad1 8222 }
8f06b2d8 8223 }
823d2571 8224
6b0dd094
AV		 8225 if ((insn->isa == T32 && !thumb)
8226 || (insn->isa == ARM && thumb))
8227 continue;
8228
0313a2b8
NC		 8229 if ((given & mask) != value)
8230 continue;
8f06b2d8 8231
823d2571 8232 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8233 continue;
8234
8afc7bea
RL		 8235 if (insn->value == 0xfe000010 /* mcr2 */
8236 || insn->value == 0xfe100010 /* mrc2 */
8237 || insn->value == 0xfc100000 /* ldc2 */
8238 || insn->value == 0xfc000000) /* stc2 */
8239 {
b0c11777 8240 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
78933a4a 8241 is_unpredictable = true;
f08d8ce3
AV		 8242
8243 /* Armv8.1-M Mainline FP & MVE instructions. */
8244 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8245 && !ARM_CPU_IS_ANY (allowed_arches)
8246 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8247 continue;
8248
8afc7bea
RL		 8249 }
8250 else if (insn->value == 0x0e000000 /* cdp */
8251 || insn->value == 0xfe000000 /* cdp2 */
8252 || insn->value == 0x0e000010 /* mcr */
8253 || insn->value == 0x0e100010 /* mrc */
8254 || insn->value == 0x0c100000 /* ldc */
8255 || insn->value == 0x0c000000) /* stc */
8256 {
8257 /* Floating-point instructions. */
b0c11777 8258 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8259 continue;
32c36c3c
AV		 8260
8261 /* Armv8.1-M Mainline FP & MVE instructions. */
8262 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8263 && !ARM_CPU_IS_ANY (allowed_arches)
8264 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8265 continue;
8afc7bea 8266 }
aef6d006
AV		 8267 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8268 || insn->value == 0xec000f80) /* vstr (system register) */
8269 && arm_decode_field (given, 24, 24) == 0
8270 && arm_decode_field (given, 21, 21) == 0)
8271 /* If the P and W bits are both 0 then these encodings match the MVE
8272 VLDR and VSTR instructions, these are in a different table, so we
8273 don't let it match here. */
8274 continue;
8275
0313a2b8
NC		 8276 for (c = insn->assembler; *c; c++)
8277 {
8278 if (*c == '%')
8f06b2d8 8279 {
32c36c3c 8280 const char mod = *++c;
6576bffe 8281
32c36c3c 8282 switch (mod)
8f06b2d8 8283 {
6576bffe
AB		 8284 case '{':
8285 ++c;
8286 if (*c == '\0')
8287 abort ();
8288 old_base_style = base_style;
8289 base_style = decode_base_style (*c);
8290 ++c;
8291 if (*c != ':')
8292 abort ();
8293 break;
8294
8295 case '}':
8296 base_style = old_base_style;
8297 break;
8298
0313a2b8 8299 case '%':
6576bffe 8300 func (stream, base_style, "%%");
0313a2b8
NC		 8301 break;
8302
8303 case 'A':
32c36c3c 8304 case 'K':
05413229 8305 {
79862e45 8306 int rn = (given >> 16) & 0xf;
b0c11777 8307 bfd_vma offset = given & 0xff;
0313a2b8 8308
32c36c3c
AV		 8309 if (mod == 'K')
8310 offset = given & 0x7f;
8311
6576bffe
AB		 8312 func (stream, dis_style_text, "[");
8313 func (stream, dis_style_register, "%s",
8314 arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8315
79862e45
DJ		 8316 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8317 {
8318 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8319 if (cp_num == 9)
8320 /* vldr.16/vstr.16 will shift the address
8321 left by 1 bit only. */
8322 offset = offset * 2;
8323 else
8324 offset = offset * 4;
8325
79862e45
DJ		 8326 if (NEGATIVE_BIT_SET)
8327 offset = - offset;
8328 if (rn != 15)
8329 value_in_comment = offset;
8330 }
8331
c1e26897 8332 if (PRE_BIT_SET)
05413229
NC		 8333 {
8334 if (offset)
6576bffe
AB		 8335 {
8336 func (stream, dis_style_text, ", ");
8337 func (stream, dis_style_immediate, "#%d",
8338 (int) offset);
8339 func (stream, dis_style_text, "]%s",
8340 WRITEBACK_BIT_SET ? "!" : "");
8341 }
26d97720 8342 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8343 {
8344 func (stream, dis_style_text, ", ");
8345 func (stream, dis_style_immediate, "#-0");
8346 func (stream, dis_style_text, "]");
8347 }
05413229 8348 else
6576bffe 8349 func (stream, dis_style_text, "]");
05413229
NC		 8350 }
8351 else
8352 {
6576bffe 8353 func (stream, dis_style_text, "]");
8f06b2d8 8354
c1e26897 8355 if (WRITEBACK_BIT_SET)
05413229
NC		 8356 {
8357 if (offset)
6576bffe
AB		 8358 {
8359 func (stream, dis_style_text, ", ");
8360 func (stream, dis_style_immediate,
8361 "#%d", (int) offset);
8362 }
26d97720 8363 else if (NEGATIVE_BIT_SET)
6576bffe
AB		 8364 {
8365 func (stream, dis_style_text, ", ");
8366 func (stream, dis_style_immediate, "#-0");
8367 }
05413229
NC		 8368 }
8369 else
fe56b6ce 8370 {
6576bffe
AB		 8371 func (stream, dis_style_text, ", {");
8372 func (stream, dis_style_immediate, "%s%d",
26d97720 8373 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8374 (int) offset);
6576bffe 8375 func (stream, dis_style_text, "}");
fe56b6ce
NC		 8376 value_in_comment = offset;
8377 }
05413229 8378 }
79862e45
DJ		 8379 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8380 {
6576bffe 8381 func (stream, dis_style_comment_start, "\t@ ");
6844b2c2
MGD		 8382 /* For unaligned PCs, apply off-by-alignment
8383 correction. */
43e65147 8384 info->print_address_func (offset + pc
6844b2c2
MGD		 8385 + info->bytes_per_chunk * 2
8386 - (pc & 3),
dffaa15c 8387 info);
79862e45 8388 }
05413229 8389 }
0313a2b8 8390 break;
8f06b2d8 8391
0313a2b8
NC		 8392 case 'B':
8393 {
8394 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8395 int offset = (given >> 1) & 0x3f;
8396
6576bffe 8397 func (stream, dis_style_text, "{");
0313a2b8 8398 if (offset == 1)
6576bffe 8399 func (stream, dis_style_register, "d%d", regno);
0313a2b8 8400 else if (regno + offset > 32)
6576bffe
AB		 8401 {
8402 func (stream, dis_style_register, "d%d", regno);
8403 func (stream, dis_style_text, "-<overflow reg d%d>",
8404 regno + offset - 1);
8405 }
0313a2b8 8406 else
6576bffe
AB		 8407 {
8408 func (stream, dis_style_register, "d%d", regno);
8409 func (stream, dis_style_text, "-");
8410 func (stream, dis_style_register, "d%d",
8411 regno + offset - 1);
8412 }
8413 func (stream, dis_style_text, "}");
0313a2b8
NC		 8414 }
8415 break;
8f06b2d8 8416
efd6b359
AV		 8417 case 'C':
8418 {
78933a4a 8419 bool single = ((given >> 8) & 1) == 0;
efd6b359
AV		 8420 char reg_prefix = single ? 's' : 'd';
8421 int Dreg = (given >> 22) & 0x1;
8422 int Vdreg = (given >> 12) & 0xf;
8423 int reg = single ? ((Vdreg << 1) | Dreg)
8424 : ((Dreg << 4) | Vdreg);
8425 int num = (given >> (single ? 0 : 1)) & 0x7f;
8426 int maxreg = single ? 31 : 15;
8427 int topreg = reg + num - 1;
8428
6576bffe 8429 func (stream, dis_style_text, "{");
efd6b359 8430 if (!num)
6576bffe
AB		 8431 {
8432 /* Nothing. */
8433 }
efd6b359 8434 else if (num == 1)
6576bffe
AB		 8435 {
8436 func (stream, dis_style_register,
8437 "%c%d", reg_prefix, reg);
8438 func (stream, dis_style_text, ", ");
8439 }
efd6b359 8440 else if (topreg > maxreg)
6576bffe
AB		 8441 {
8442 func (stream, dis_style_register, "%c%d",
8443 reg_prefix, reg);
8444 func (stream, dis_style_text, "-<overflow reg d%d, ",
8445 single ? topreg >> 1 : topreg);
8446 }
efd6b359 8447 else
6576bffe
AB		 8448 {
8449 func (stream, dis_style_register,
8450 "%c%d", reg_prefix, reg);
8451 func (stream, dis_style_text, "-");
8452 func (stream, dis_style_register, "%c%d",
8453 reg_prefix, topreg);
8454 func (stream, dis_style_text, ", ");
8455 }
8456 func (stream, dis_style_register, "VPR");
8457 func (stream, dis_style_text, "}");
efd6b359
AV		 8458 }
8459 break;
8460
e2efe87d
MGD		 8461 case 'u':
8462 if (cond != COND_UNCOND)
78933a4a 8463 is_unpredictable = true;
e2efe87d
MGD		 8464
8465 /* Fall through. */
0313a2b8 8466 case 'c':
b0c11777 8467 if (cond != COND_UNCOND && cp_num == 9)
78933a4a 8468 is_unpredictable = true;
b0c11777 8469
aab2c27d
MM		 8470 /* Fall through. */
8471 case 'b':
6576bffe
AB		 8472 func (stream, dis_style_mnemonic, "%s",
8473 arm_conditional[cond]);
0313a2b8 8474 break;
8f06b2d8 8475
0313a2b8
NC		 8476 case 'I':
8477 /* Print a Cirrus/DSP shift immediate. */
8478 /* Immediates are 7bit signed ints with bits 0..3 in
8479 bits 0..3 of opcode and bits 4..6 in bits 5..7
8480 of opcode. */
8481 {
8482 int imm;
8f06b2d8 8483
0313a2b8 8484 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8485
0313a2b8
NC		 8486 /* Is ``imm'' a negative number? */
8487 if (imm & 0x40)
24b4cf66 8488 imm -= 0x80;
8f06b2d8 8489
6576bffe 8490 func (stream, dis_style_immediate, "%d", imm);
0313a2b8
NC		 8491 }
8492
8493 break;
8f06b2d8 8494
32c36c3c
AV		 8495 case 'J':
8496 {
73cd51e5
AV		 8497 unsigned long regno
8498 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8499
8500 switch (regno)
8501 {
8502 case 0x1:
6576bffe 8503 func (stream, dis_style_register, "FPSCR");
32c36c3c
AV		 8504 break;
8505 case 0x2:
6576bffe 8506 func (stream, dis_style_register, "FPSCR_nzcvqc");
32c36c3c
AV		 8507 break;
8508 case 0xc:
6576bffe 8509 func (stream, dis_style_register, "VPR");
32c36c3c
AV		 8510 break;
8511 case 0xd:
6576bffe 8512 func (stream, dis_style_register, "P0");
32c36c3c
AV		 8513 break;
8514 case 0xe:
6576bffe 8515 func (stream, dis_style_register, "FPCXTNS");
32c36c3c
AV		 8516 break;
8517 case 0xf:
6576bffe 8518 func (stream, dis_style_register, "FPCXTS");
32c36c3c
AV		 8519 break;
8520 default:
6576bffe
AB		 8521 func (stream, dis_style_text, "<invalid reg %lu>",
8522 regno);
32c36c3c
AV		 8523 break;
8524 }
8525 }
8526 break;
8527
0313a2b8
NC		 8528 case 'F':
8529 switch (given & 0x00408000)
8530 {
8531 case 0:
6576bffe 8532 func (stream, dis_style_immediate, "4");
0313a2b8
NC		 8533 break;
8534 case 0x8000:
6576bffe 8535 func (stream, dis_style_immediate, "1");
0313a2b8
NC		 8536 break;
8537 case 0x00400000:
6576bffe 8538 func (stream, dis_style_immediate, "2");
8f06b2d8 8539 break;
0313a2b8 8540 default:
6576bffe 8541 func (stream, dis_style_immediate, "3");
0313a2b8
NC		 8542 }
8543 break;
8f06b2d8 8544
0313a2b8
NC		 8545 case 'P':
8546 switch (given & 0x00080080)
8547 {
8548 case 0:
6576bffe 8549 func (stream, dis_style_mnemonic, "s");
0313a2b8
NC		 8550 break;
8551 case 0x80:
6576bffe 8552 func (stream, dis_style_mnemonic, "d");
0313a2b8
NC		 8553 break;
8554 case 0x00080000:
6576bffe 8555 func (stream, dis_style_mnemonic, "e");
0313a2b8
NC		 8556 break;
8557 default:
6576bffe 8558 func (stream, dis_style_text, _("<illegal precision>"));
8f06b2d8 8559 break;
0313a2b8
NC		 8560 }
8561 break;
8f06b2d8 8562
0313a2b8
NC		 8563 case 'Q':
8564 switch (given & 0x00408000)
8565 {
8566 case 0:
6576bffe 8567 func (stream, dis_style_mnemonic, "s");
8f06b2d8 8568 break;
0313a2b8 8569 case 0x8000:
6576bffe 8570 func (stream, dis_style_mnemonic, "d");
8f06b2d8 8571 break;
0313a2b8 8572 case 0x00400000:
6576bffe 8573 func (stream, dis_style_mnemonic, "e");
0313a2b8
NC		 8574 break;
8575 default:
6576bffe 8576 func (stream, dis_style_mnemonic, "p");
8f06b2d8 8577 break;
0313a2b8
NC		 8578 }
8579 break;
8f06b2d8 8580
0313a2b8
NC		 8581 case 'R':
8582 switch (given & 0x60)
8583 {
8584 case 0:
8585 break;
8586 case 0x20:
6576bffe 8587 func (stream, dis_style_mnemonic, "p");
0313a2b8
NC		 8588 break;
8589 case 0x40:
6576bffe 8590 func (stream, dis_style_mnemonic, "m");
0313a2b8
NC		 8591 break;
8592 default:
6576bffe 8593 func (stream, dis_style_mnemonic, "z");
0313a2b8
NC		 8594 break;
8595 }
8596 break;
16980d0b 8597
0313a2b8
NC		 8598 case '0': case '1': case '2': case '3': case '4':
8599 case '5': case '6': case '7': case '8': case '9':
8600 {
8601 int width;
8f06b2d8 8602
0313a2b8 8603 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8604
0313a2b8
NC		 8605 switch (*c)
8606 {
ff4a8d2b
NC		 8607 case 'R':
8608 if (value == 15)
78933a4a 8609 is_unpredictable = true;
ff4a8d2b 8610 /* Fall through. */
0313a2b8 8611 case 'r':
ff4a8d2b
NC		 8612 if (c[1] == 'u')
8613 {
8614 /* Eat the 'u' character. */
8615 ++ c;
8616
8617 if (u_reg == value)
78933a4a 8618 is_unpredictable = true;
ff4a8d2b
NC		 8619 u_reg = value;
8620 }
4575eafb
AB		 8621 func (stream, dis_style_register, "%s",
8622 arm_regnames[value]);
0313a2b8 8623 break;
c28eeff2
SN		 8624 case 'V':
8625 if (given & (1 << 6))
8626 goto Q;
8627 /* FALLTHROUGH */
0313a2b8 8628 case 'D':
6576bffe 8629 func (stream, dis_style_register, "d%ld", value);
0313a2b8
NC		 8630 break;
8631 case 'Q':
c28eeff2 8632 Q:
0313a2b8 8633 if (value & 1)
6576bffe
AB		 8634 func (stream, dis_style_text,
8635 "<illegal reg q%ld.5>", value >> 1);
0313a2b8 8636 else
6576bffe
AB		 8637 func (stream, dis_style_register,
8638 "q%ld", value >> 1);
0313a2b8
NC		 8639 break;
8640 case 'd':
6576bffe 8641 func (stream, base_style, "%ld", value);
05413229 8642 value_in_comment = value;
0313a2b8 8643 break;
6f1c2142
AM		 8644 case 'E':
8645 {
8646 /* Converts immediate 8 bit back to float value. */
8647 unsigned floatVal = (value & 0x80) << 24
8648 | (value & 0x3F) << 19
8649 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8650
8651 /* Quarter float have a maximum value of 31.0.
8652 Get floating point value multiplied by 1e7.
8653 The maximum value stays in limit of a 32-bit int. */
8654 unsigned decVal =
8655 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8656 (16 + (value & 0xF));
8657
8658 if (!(decVal % 1000000))
6576bffe
AB		 8659 {
8660 func (stream, dis_style_immediate, "%ld", value);
8661 func (stream, dis_style_comment_start,
8662 "\t@ 0x%08x %c%u.%01u",
8663 floatVal, value & 0x80 ? '-' : ' ',
8664 decVal / 10000000,
8665 decVal % 10000000 / 1000000);
8666 }
6f1c2142 8667 else if (!(decVal % 10000))
6576bffe
AB		 8668 {
8669 func (stream, dis_style_immediate, "%ld", value);
8670 func (stream, dis_style_comment_start,
8671 "\t@ 0x%08x %c%u.%03u",
8672 floatVal, value & 0x80 ? '-' : ' ',
8673 decVal / 10000000,
8674 decVal % 10000000 / 10000);
8675 }
6f1c2142 8676 else
6576bffe
AB		 8677 {
8678 func (stream, dis_style_immediate, "%ld", value);
8679 func (stream, dis_style_comment_start,
8680 "\t@ 0x%08x %c%u.%07u",
8681 floatVal, value & 0x80 ? '-' : ' ',
8682 decVal / 10000000, decVal % 10000000);
8683 }
6f1c2142
AM		 8684 break;
8685 }
0313a2b8
NC		 8686 case 'k':
8687 {
8688 int from = (given & (1 << 7)) ? 32 : 16;
6576bffe
AB		 8689 func (stream, dis_style_immediate, "%ld",
8690 from - value);
0313a2b8
NC		 8691 }
8692 break;
8f06b2d8 8693
0313a2b8
NC		 8694 case 'f':
8695 if (value > 7)
6576bffe
AB		 8696 func (stream, dis_style_immediate, "#%s",
8697 arm_fp_const[value & 7]);
0313a2b8 8698 else
6576bffe 8699 func (stream, dis_style_register, "f%ld", value);
0313a2b8 8700 break;
4146fd53 8701
0313a2b8
NC		 8702 case 'w':
8703 if (width == 2)
6576bffe
AB		 8704 func (stream, dis_style_mnemonic, "%s",
8705 iwmmxt_wwnames[value]);
0313a2b8 8706 else
6576bffe
AB		 8707 func (stream, dis_style_mnemonic, "%s",
8708 iwmmxt_wwssnames[value]);
0313a2b8 8709 break;
4146fd53 8710
0313a2b8 8711 case 'g':
6576bffe
AB		 8712 func (stream, dis_style_register, "%s",
8713 iwmmxt_regnames[value]);
0313a2b8
NC		 8714 break;
8715 case 'G':
6576bffe
AB		 8716 func (stream, dis_style_register, "%s",
8717 iwmmxt_cregnames[value]);
16980d0b 8718 break;
8f06b2d8 8719
0313a2b8 8720 case 'x':
6576bffe
AB		 8721 func (stream, dis_style_immediate, "0x%lx",
8722 (value & 0xffffffffUL));
0313a2b8 8723 break;
8f06b2d8 8724
33399f07
MGD		 8725 case 'c':
8726 switch (value)
8727 {
8728 case 0:
6576bffe 8729 func (stream, dis_style_mnemonic, "eq");
33399f07
MGD		 8730 break;
8731
8732 case 1:
6576bffe 8733 func (stream, dis_style_mnemonic, "vs");
33399f07
MGD		 8734 break;
8735
8736 case 2:
6576bffe 8737 func (stream, dis_style_mnemonic, "ge");
33399f07
MGD		 8738 break;
8739
8740 case 3:
6576bffe 8741 func (stream, dis_style_mnemonic, "gt");
33399f07
MGD		 8742 break;
8743
8744 default:
6576bffe 8745 func (stream, dis_style_text, "??");
33399f07
MGD		 8746 break;
8747 }
8748 break;
8749
0313a2b8
NC		 8750 case '`':
8751 c++;
8752 if (value == 0)
6576bffe 8753 func (stream, dis_style_mnemonic, "%c", *c);
0313a2b8
NC		 8754 break;
8755 case '\'':
8756 c++;
8757 if (value == ((1ul << width) - 1))
6576bffe 8758 func (stream, base_style, "%c", *c);
0313a2b8
NC		 8759 break;
8760 case '?':
6576bffe
AB		 8761 func (stream, base_style, "%c",
8762 c[(1 << width) - (int) value]);
0313a2b8
NC		 8763 c += 1 << width;
8764 break;
8765 default:
8766 abort ();
8767 }
dffaa15c
AM		 8768 }
8769 break;
0313a2b8 8770
dffaa15c
AM		 8771 case 'y':
8772 case 'z':
8773 {
8774 int single = *c++ == 'y';
8775 int regno;
8f06b2d8 8776
dffaa15c
AM		 8777 switch (*c)
8778 {
8779 case '4': /* Sm pair */
8780 case '0': /* Sm, Dm */
8781 regno = given & 0x0000000f;
8782 if (single)
8783 {
8784 regno <<= 1;
8785 regno += (given >> 5) & 1;
8786 }
8787 else
8788 regno += ((given >> 5) & 1) << 4;
8789 break;
8f06b2d8 8790
dffaa15c
AM		 8791 case '1': /* Sd, Dd */
8792 regno = (given >> 12) & 0x0000000f;
8793 if (single)
8794 {
8795 regno <<= 1;
8796 regno += (given >> 22) & 1;
8797 }
8798 else
8799 regno += ((given >> 22) & 1) << 4;
8800 break;
7df76b80 8801
dffaa15c
AM		 8802 case '2': /* Sn, Dn */
8803 regno = (given >> 16) & 0x0000000f;
8804 if (single)
8805 {
8806 regno <<= 1;
8807 regno += (given >> 7) & 1;
8808 }
8809 else
8810 regno += ((given >> 7) & 1) << 4;
8811 break;
a7f8487e 8812
dffaa15c 8813 case '3': /* List */
6576bffe 8814 func (stream, dis_style_text, "{");
dffaa15c
AM		 8815 regno = (given >> 12) & 0x0000000f;
8816 if (single)
8817 {
8818 regno <<= 1;
8819 regno += (given >> 22) & 1;
8820 }
8821 else
8822 regno += ((given >> 22) & 1) << 4;
8823 break;
a7f8487e 8824
dffaa15c
AM		 8825 default:
8826 abort ();
8827 }
0313a2b8 8828
6576bffe
AB		 8829 func (stream, dis_style_register, "%c%d",
8830 single ? 's' : 'd', regno);
a7f8487e 8831
dffaa15c
AM		 8832 if (*c == '3')
8833 {
8834 int count = given & 0xff;
b34976b6 8835
dffaa15c
AM		 8836 if (single == 0)
8837 count >>= 1;
0313a2b8 8838
dffaa15c
AM		 8839 if (--count)
8840 {
6576bffe
AB		 8841 func (stream, dis_style_text, "-");
8842 func (stream, dis_style_register, "%c%d",
dffaa15c
AM		 8843 single ? 's' : 'd',
8844 regno + count);
8845 }
0313a2b8 8846
6576bffe 8847 func (stream, dis_style_text, "}");
0313a2b8 8848 }
dffaa15c 8849 else if (*c == '4')
6576bffe
AB		 8850 {
8851 func (stream, dis_style_text, ", ");
8852 func (stream, dis_style_register, "%c%d",
8853 single ? 's' : 'd', regno + 1);
8854 }
dffaa15c
AM		 8855 }
8856 break;
b34976b6 8857
dffaa15c
AM		 8858 case 'L':
8859 switch (given & 0x00400100)
0313a2b8 8860 {
6576bffe
AB		 8861 case 0x00000000:
8862 func (stream, dis_style_mnemonic, "b");
8863 break;
8864 case 0x00400000:
8865 func (stream, dis_style_mnemonic, "h");
8866 break;
8867 case 0x00000100:
8868 func (stream, dis_style_mnemonic, "w");
8869 break;
8870 case 0x00400100:
8871 func (stream, dis_style_mnemonic, "d");
8872 break;
dffaa15c
AM		 8873 default:
8874 break;
0313a2b8 8875 }
dffaa15c 8876 break;
2d447fca 8877
dffaa15c
AM		 8878 case 'Z':
8879 {
8880 /* given (20, 23) | given (0, 3) */
8881 value = ((given >> 16) & 0xf0) | (given & 0xf);
6576bffe 8882 func (stream, dis_style_immediate, "%d", (int) value);
dffaa15c
AM		 8883 }
8884 break;
0313a2b8 8885
dffaa15c
AM		 8886 case 'l':
8887 /* This is like the 'A' operator, except that if
8888 the width field "M" is zero, then the offset is
8889 *not* multiplied by four. */
8890 {
8891 int offset = given & 0xff;
8892 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8893
6576bffe
AB		 8894 func (stream, dis_style_text, "[");
8895 func (stream, dis_style_register, "%s",
8896 arm_regnames [(given >> 16) & 0xf]);
05413229 8897
dffaa15c
AM		 8898 if (multiplier > 1)
8899 {
8900 value_in_comment = offset * multiplier;
8901 if (NEGATIVE_BIT_SET)
8902 value_in_comment = - value_in_comment;
8903 }
0313a2b8 8904
dffaa15c
AM		 8905 if (offset)
8906 {
8907 if (PRE_BIT_SET)
6576bffe
AB		 8908 {
8909 func (stream, dis_style_text, ", ");
8910 func (stream, dis_style_immediate, "#%s%d",
8911 NEGATIVE_BIT_SET ? "-" : "",
8912 offset * multiplier);
8913 func (stream, dis_style_text, "]%s",
8914 WRITEBACK_BIT_SET ? "!" : "");
8915 }
dffaa15c 8916 else
6576bffe
AB		 8917 {
8918 func (stream, dis_style_text, "], ");
8919 func (stream, dis_style_immediate, "#%s%d",
8920 NEGATIVE_BIT_SET ? "-" : "",
8921 offset * multiplier);
8922 }
dffaa15c
AM		 8923 }
8924 else
6576bffe 8925 func (stream, dis_style_text, "]");
dffaa15c
AM		 8926 }
8927 break;
2d447fca 8928
dffaa15c
AM		 8929 case 'r':
8930 {
8931 int imm4 = (given >> 4) & 0xf;
8932 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8933 int ubit = ! NEGATIVE_BIT_SET;
8934 const char *rm = arm_regnames [given & 0xf];
8935 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8936
dffaa15c
AM		 8937 switch (puw_bits)
8938 {
8939 case 1:
8940 case 3:
6576bffe
AB		 8941 func (stream, dis_style_text, "[");
8942 func (stream, dis_style_register, "%s", rn);
8943 func (stream, dis_style_text, "], ");
8944 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8945 func (stream, dis_style_register, "%s", rm);
dffaa15c 8946 if (imm4)
6576bffe
AB		 8947 {
8948 func (stream, dis_style_text, ", ");
8949 func (stream, dis_style_sub_mnemonic, "lsl ");
8950 func (stream, dis_style_immediate, "#%d", imm4);
8951 }
dffaa15c 8952 break;
0313a2b8 8953
dffaa15c
AM		 8954 case 4:
8955 case 5:
8956 case 6:
8957 case 7:
6576bffe
AB		 8958 func (stream, dis_style_text, "[");
8959 func (stream, dis_style_register, "%s", rn);
8960 func (stream, dis_style_text, ", ");
8961 func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8962 func (stream, dis_style_register, "%s", rm);
dffaa15c 8963 if (imm4 > 0)
6576bffe
AB		 8964 {
8965 func (stream, dis_style_text, ", ");
8966 func (stream, dis_style_sub_mnemonic, "lsl ");
8967 func (stream, dis_style_immediate, "#%d", imm4);
8968 }
8969 func (stream, dis_style_text, "]");
dffaa15c 8970 if (puw_bits == 5 || puw_bits == 7)
6576bffe 8971 func (stream, dis_style_text, "!");
dffaa15c 8972 break;
2d447fca 8973
dffaa15c 8974 default:
6576bffe 8975 func (stream, dis_style_text, "INVALID");
dffaa15c
AM		 8976 }
8977 }
8978 break;
0313a2b8 8979
dffaa15c
AM		 8980 case 'i':
8981 {
8982 long imm5;
8983 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
6576bffe
AB		 8984 func (stream, dis_style_immediate, "%ld",
8985 (imm5 == 0) ? 32 : imm5);
0313a2b8 8986 }
dffaa15c
AM		 8987 break;
8988
8989 default:
8990 abort ();
252b5132 8991 }
252b5132 8992 }
0313a2b8 8993 else
6576bffe
AB		 8994 {
8995 if (*c == '@')
8996 base_style = dis_style_comment_start;
8997
8998 if (*c == '\t')
8999 base_style = dis_style_text;
9000
9001 func (stream, base_style, "%c", *c);
9002 }
252b5132 9003 }
05413229
NC		 9004
9005 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 9006 func (stream, dis_style_comment_start, "\t@ 0x%lx",
9007 (value_in_comment & 0xffffffffUL));
05413229 9008
ff4a8d2b 9009 if (is_unpredictable)
6576bffe 9010 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 9011
78933a4a 9012 return true;
252b5132 9013 }
78933a4a 9014 return false;
252b5132
RH		 9015}
9016
78933a4a 9017static bool
33593eaf
MM		 9018print_insn_coprocessor (bfd_vma pc,
9019 struct disassemble_info *info,
9020 long given,
78933a4a 9021 bool thumb)
33593eaf
MM		 9022{
9023 return print_insn_coprocessor_1 (coprocessor_opcodes,
9024 pc, info, given, thumb);
9025}
9026
78933a4a 9027static bool
33593eaf
MM		 9028print_insn_generic_coprocessor (bfd_vma pc,
9029 struct disassemble_info *info,
9030 long given,
78933a4a 9031 bool thumb)
33593eaf
MM		 9032{
9033 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
9034 pc, info, given, thumb);
9035}
9036
05413229
NC		 9037/* Decodes and prints ARM addressing modes. Returns the offset
9038 used in the address, if any, if it is worthwhile printing the
9039 offset as a hexadecimal value in a comment at the end of the
9040 line of disassembly. */
9041
9042static signed long
62b3e311
PB		 9043print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
9044{
9045 void *stream = info->stream;
6576bffe 9046 fprintf_styled_ftype func = info->fprintf_styled_func;
f8b960bc 9047 bfd_vma offset = 0;
62b3e311
PB		 9048
9049 if (((given & 0x000f0000) == 0x000f0000)
9050 && ((given & 0x02000000) == 0))
9051 {
05413229 9052 offset = given & 0xfff;
62b3e311 9053
6576bffe
AB		 9054 func (stream, dis_style_text, "[");
9055 func (stream, dis_style_register, "pc");
62b3e311 9056
c1e26897 9057 if (PRE_BIT_SET)
62b3e311 9058 {
26d97720
NS		 9059 /* Pre-indexed. Elide offset of positive zero when
9060 non-writeback. */
9061 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 9062 {
9063 func (stream, dis_style_text, ", ");
9064 func (stream, dis_style_immediate, "#%s%d",
9065 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9066 }
26d97720
NS		 9067
9068 if (NEGATIVE_BIT_SET)
9069 offset = -offset;
62b3e311
PB		 9070
9071 offset += pc + 8;
9072
9073 /* Cope with the possibility of write-back
9074 being used. Probably a very dangerous thing
9075 for the programmer to do, but who are we to
9076 argue ? */
6576bffe 9077 func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 9078 }
c1e26897 9079 else /* Post indexed. */
62b3e311 9080 {
6576bffe
AB		 9081 func (stream, dis_style_text, "], ");
9082 func (stream, dis_style_immediate, "#%s%d",
9083 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 9084
c1e26897 9085 /* Ie ignore the offset. */
62b3e311
PB		 9086 offset = pc + 8;
9087 }
9088
6576bffe 9089 func (stream, dis_style_comment_start, "\t@ ");
62b3e311 9090 info->print_address_func (offset, info);
05413229 9091 offset = 0;
62b3e311
PB		 9092 }
9093 else
9094 {
6576bffe
AB		 9095 func (stream, dis_style_text, "[");
9096 func (stream, dis_style_register, "%s",
62b3e311 9097 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 9098
9099 if (PRE_BIT_SET)
62b3e311
PB		 9100 {
9101 if ((given & 0x02000000) == 0)
9102 {
26d97720 9103 /* Elide offset of positive zero when non-writeback. */
05413229 9104 offset = given & 0xfff;
26d97720 9105 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
6576bffe
AB		 9106 {
9107 func (stream, dis_style_text, ", ");
9108 func (stream, dis_style_immediate, "#%s%d",
9109 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9110 }
62b3e311
PB		 9111 }
9112 else
9113 {
6576bffe
AB		 9114 func (stream, dis_style_text, ", %s",
9115 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 9116 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 9117 }
9118
6576bffe 9119 func (stream, dis_style_text, "]%s",
c1e26897 9120 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 9121 }
9122 else
9123 {
9124 if ((given & 0x02000000) == 0)
9125 {
26d97720 9126 /* Always show offset. */
05413229 9127 offset = given & 0xfff;
6576bffe
AB		 9128 func (stream, dis_style_text, "], ");
9129 func (stream, dis_style_immediate, "#%s%d",
d908c8af 9130 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 9131 }
9132 else
9133 {
6576bffe 9134 func (stream, dis_style_text, "], %s",
c1e26897 9135 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 9136 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 9137 }
9138 }
84919466
MR		 9139 if (NEGATIVE_BIT_SET)
9140 offset = -offset;
62b3e311 9141 }
05413229
NC		 9142
9143 return (signed long) offset;
62b3e311
PB		 9144}
9145
4934a27c
MM		 9146
9147/* Print one cde instruction on INFO->STREAM.
9148 Return TRUE if the instuction matched, FALSE if this is not a
9149 recognised cde instruction. */
78933a4a
AM		 9150static bool
9151print_insn_cde (struct disassemble_info *info, long given, bool thumb)
4934a27c
MM		 9152{
9153 const struct cdeopcode32 *insn;
9154 void *stream = info->stream;
6576bffe
AB		 9155 fprintf_styled_ftype func = info->fprintf_styled_func;
9156 enum disassembler_style base_style = dis_style_mnemonic;
9157 enum disassembler_style old_base_style = base_style;
4934a27c
MM		 9158
9159 if (thumb)
9160 {
9161 /* Manually extract the coprocessor code from a known point.
9162 This position is the same across all CDE instructions. */
9163 for (insn = cde_opcodes; insn->assembler; insn++)
9164 {
9165 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
9166 uint16_t coproc_mask = 1 << coproc;
9167 if (! (coproc_mask & cde_coprocs))
9168 continue;
9169
9170 if ((given & insn->mask) == insn->value)
9171 {
78933a4a 9172 bool is_unpredictable = false;
4934a27c
MM		 9173 const char *c;
9174
9175 for (c = insn->assembler; *c; c++)
9176 {
9177 if (*c == '%')
9178 {
9179 switch (*++c)
9180 {
6576bffe
AB		 9181 case '{':
9182 ++c;
9183 if (*c == '\0')
9184 abort ();
9185 old_base_style = base_style;
9186 base_style = decode_base_style (*c);
9187 ++c;
9188 if (*c != ':')
9189 abort ();
9190 break;
9191
9192 case '}':
9193 base_style = old_base_style;
9194 break;
9195
4934a27c 9196 case '%':
6576bffe 9197 func (stream, base_style, "%%");
4934a27c
MM		 9198 break;
9199
9200 case '0': case '1': case '2': case '3': case '4':
9201 case '5': case '6': case '7': case '8': case '9':
9202 {
9203 int width;
9204 unsigned long value;
9205
9206 c = arm_decode_bitfield (c, given, &value, &width);
9207
9208 switch (*c)
9209 {
9210 case 'S':
9211 if (value > 10)
78933a4a 9212 is_unpredictable = true;
4934a27c
MM		 9213 /* Fall through. */
9214 case 'R':
9215 if (value == 13)
78933a4a 9216 is_unpredictable = true;
4934a27c
MM		 9217 /* Fall through. */
9218 case 'r':
6576bffe
AB		 9219 func (stream, dis_style_register, "%s",
9220 arm_regnames[value]);
4934a27c
MM		 9221 break;
9222
9223 case 'n':
9224 if (value == 15)
6576bffe 9225 func (stream, dis_style_register, "%s", "APSR_nzcv");
4934a27c 9226 else
6576bffe
AB		 9227 func (stream, dis_style_register, "%s",
9228 arm_regnames[value]);
4934a27c
MM		 9229 break;
9230
9231 case 'T':
6576bffe
AB		 9232 func (stream, dis_style_register, "%s",
9233 arm_regnames[(value + 1) & 15]);
4934a27c
MM		 9234 break;
9235
9236 case 'd':
6576bffe 9237 func (stream, dis_style_immediate, "%ld", value);
4934a27c
MM		 9238 break;
9239
5aae9ae9
MM		 9240 case 'V':
9241 if (given & (1 << 6))
6576bffe 9242 func (stream, dis_style_register, "q%ld", value >> 1);
5aae9ae9 9243 else if (given & (1 << 24))
6576bffe 9244 func (stream, dis_style_register, "d%ld", value);
5aae9ae9
MM		 9245 else
9246 {
9247 /* Encoding for S register is different than for D and
9248 Q registers. S registers are encoded using the top
9249 single bit in position 22 as the lowest bit of the
9250 register number, while for Q and D it represents the
9251 highest bit of the register number. */
9252 uint8_t top_bit = (value >> 4) & 1;
9253 uint8_t tmp = (value << 1) & 0x1e;
9254 uint8_t res = tmp | top_bit;
6576bffe 9255 func (stream, dis_style_register, "s%u", res);
5aae9ae9
MM		 9256 }
9257 break;
9258
4934a27c
MM		 9259 default:
9260 abort ();
9261 }
9262 }
9263 break;
9264
9265 case 'p':
9266 {
9267 uint8_t proc_number = (given >> 8) & 0x7;
6576bffe 9268 func (stream, dis_style_register, "p%u", proc_number);
4934a27c
MM		 9269 break;
9270 }
9271
9272 case 'a':
9273 {
9274 uint8_t a_offset = 28;
9275 if (given & (1 << a_offset))
6576bffe 9276 func (stream, dis_style_mnemonic, "a");
4934a27c
MM		 9277 break;
9278 }
9279 default:
9280 abort ();
9281 }
9282 }
9283 else
6576bffe
AB		 9284 {
9285 if (*c == '@')
9286 base_style = dis_style_comment_start;
9287 if (*c == '\t')
9288 base_style = dis_style_text;
9289
9290 func (stream, base_style, "%c", *c);
9291 }
4934a27c
MM		 9292 }
9293
9294 if (is_unpredictable)
6576bffe 9295 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
4934a27c 9296
78933a4a 9297 return true;
4934a27c
MM		 9298 }
9299 }
78933a4a 9300 return false;
4934a27c
MM		 9301 }
9302 else
78933a4a 9303 return false;
4934a27c
MM		 9304}
9305
9306
16980d0b
JB		 9307/* Print one neon instruction on INFO->STREAM.
9308 Return TRUE if the instuction matched, FALSE if this is not a
9309 recognised neon instruction. */
9310
78933a4a
AM		 9311static bool
9312print_insn_neon (struct disassemble_info *info, long given, bool thumb)
16980d0b
JB		 9313{
9314 const struct opcode32 *insn;
9315 void *stream = info->stream;
6576bffe
AB		 9316 fprintf_styled_ftype func = info->fprintf_styled_func;
9317 enum disassembler_style base_style = dis_style_mnemonic;
9318 enum disassembler_style old_base_style = base_style;
16980d0b
JB		 9319
9320 if (thumb)
9321 {
9322 if ((given & 0xef000000) == 0xef000000)
9323 {
0313a2b8 9324 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 9325 unsigned long bit28 = given & (1 << 28);
9326
9327 given &= 0x00ffffff;
9328 if (bit28)
9329 given |= 0xf3000000;
9330 else
9331 given |= 0xf2000000;
9332 }
9333 else if ((given & 0xff000000) == 0xf9000000)
9334 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 9335 /* BFloat16 neon instructions without special top byte handling. */
9336 else if ((given & 0xff000000) == 0xfe000000
9337 || (given & 0xff000000) == 0xfc000000)
9338 ;
9743db03 9339 /* vdup is also a valid neon instruction. */
e409955d 9340 else if ((given & 0xff900f5f) != 0xee800b10)
78933a4a 9341 return false;
16980d0b 9342 }
43e65147 9343
16980d0b
JB		 9344 for (insn = neon_opcodes; insn->assembler; insn++)
9345 {
e409955d
FS		 9346 unsigned long cond_mask = insn->mask;
9347 unsigned long cond_value = insn->value;
9348 int cond;
9349
9350 if (thumb)
9351 {
9352 if ((cond_mask & 0xf0000000) == 0) {
9353 /* For the entries in neon_opcodes, an opcode mask/value with
9354 the high 4 bits equal to 0 indicates a conditional
9355 instruction. For thumb however, we need to include those
9356 bits in the instruction matching. */
9357 cond_mask |= 0xf0000000;
9358 /* Furthermore, the thumb encoding of a conditional instruction
9359 will have the high 4 bits equal to 0xe. */
9360 cond_value |= 0xe0000000;
9361 }
9362 if (ifthen_state)
9363 cond = IFTHEN_COND;
9364 else
9365 cond = COND_UNCOND;
9366 }
9367 else
9368 {
9369 if ((given & 0xf0000000) == 0xf0000000)
9370 {
9371 /* If the instruction is unconditional, update the mask to only
9372 match against unconditional opcode values. */
9373 cond_mask |= 0xf0000000;
9374 cond = COND_UNCOND;
9375 }
9376 else
9377 {
9378 cond = (given >> 28) & 0xf;
9379 if (cond == 0xe)
9380 cond = COND_UNCOND;
9381 }
9382 }
9383
9384 if ((given & cond_mask) == cond_value)
16980d0b 9385 {
05413229 9386 signed long value_in_comment = 0;
78933a4a 9387 bool is_unpredictable = false;
16980d0b
JB		 9388 const char *c;
9389
9390 for (c = insn->assembler; *c; c++)
9391 {
9392 if (*c == '%')
9393 {
9394 switch (*++c)
9395 {
6576bffe
AB		 9396 case '{':
9397 ++c;
9398 if (*c == '\0')
9399 abort ();
9400 old_base_style = base_style;
9401 base_style = decode_base_style (*c);
9402 ++c;
9403 if (*c != ':')
9404 abort ();
9405 break;
9406
9407 case '}':
9408 base_style = old_base_style;
9409 break;
9410
16980d0b 9411 case '%':
6576bffe 9412 func (stream, base_style, "%%");
16980d0b
JB		 9413 break;
9414
e2efe87d
MGD		 9415 case 'u':
9416 if (thumb && ifthen_state)
78933a4a 9417 is_unpredictable = true;
e2efe87d
MGD		 9418
9419 /* Fall through. */
c22aaad1 9420 case 'c':
6576bffe
AB		 9421 func (stream, dis_style_mnemonic, "%s",
9422 arm_conditional[cond]);
c22aaad1
PB		 9423 break;
9424
16980d0b
JB		 9425 case 'A':
9426 {
43e65147 9427 static const unsigned char enc[16] =
16980d0b
JB		 9428 {
9429 0x4, 0x14, /* st4 0,1 */
9430 0x4, /* st1 2 */
9431 0x4, /* st2 3 */
9432 0x3, /* st3 4 */
9433 0x13, /* st3 5 */
9434 0x3, /* st1 6 */
9435 0x1, /* st1 7 */
9436 0x2, /* st2 8 */
9437 0x12, /* st2 9 */
9438 0x2, /* st1 10 */
9439 0, 0, 0, 0, 0
9440 };
9441 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9442 int rn = ((given >> 16) & 0xf);
9443 int rm = ((given >> 0) & 0xf);
9444 int align = ((given >> 4) & 0x3);
9445 int type = ((given >> 8) & 0xf);
9446 int n = enc[type] & 0xf;
9447 int stride = (enc[type] >> 4) + 1;
9448 int ix;
43e65147 9449
6576bffe 9450 func (stream, dis_style_text, "{");
16980d0b
JB		 9451 if (stride > 1)
9452 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9453 {
9454 if (ix > 0)
9455 func (stream, dis_style_text, ",");
9456 func (stream, dis_style_register, "d%d",
9457 rd + ix * stride);
9458 }
16980d0b 9459 else if (n == 1)
6576bffe 9460 func (stream, dis_style_register, "d%d", rd);
16980d0b 9461 else
6576bffe
AB		 9462 {
9463 func (stream, dis_style_register, "d%d", rd);
9464 func (stream, dis_style_text, "-");
9465 func (stream, dis_style_register, "d%d",
9466 rd + n - 1);
9467 }
9468 func (stream, dis_style_text, "}, [");
9469 func (stream, dis_style_register, "%s",
9470 arm_regnames[rn]);
16980d0b 9471 if (align)
6576bffe
AB		 9472 {
9473 func (stream, dis_style_text, " :");
9474 func (stream, dis_style_immediate, "%d",
9475 32 << align);
9476 }
9477 func (stream, dis_style_text, "]");
16980d0b 9478 if (rm == 0xd)
6576bffe 9479 func (stream, dis_style_text, "!");
16980d0b 9480 else if (rm != 0xf)
6576bffe
AB		 9481 {
9482 func (stream, dis_style_text, ", ");
9483 func (stream, dis_style_register, "%s",
9484 arm_regnames[rm]);
9485 }
16980d0b
JB		 9486 }
9487 break;
43e65147 9488
16980d0b
JB		 9489 case 'B':
9490 {
9491 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9492 int rn = ((given >> 16) & 0xf);
9493 int rm = ((given >> 0) & 0xf);
9494 int idx_align = ((given >> 4) & 0xf);
9495 int align = 0;
9496 int size = ((given >> 10) & 0x3);
9497 int idx = idx_align >> (size + 1);
9498 int length = ((given >> 8) & 3) + 1;
9499 int stride = 1;
9500 int i;
9501
9502 if (length > 1 && size > 0)
9503 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9504
16980d0b
JB		 9505 switch (length)
9506 {
9507 case 1:
9508 {
9509 int amask = (1 << size) - 1;
9510 if ((idx_align & (1 << size)) != 0)
78933a4a 9511 return false;
16980d0b
JB		 9512 if (size > 0)
9513 {
9514 if ((idx_align & amask) == amask)
9515 align = 8 << size;
9516 else if ((idx_align & amask) != 0)
78933a4a 9517 return false;
16980d0b
JB		 9518 }
9519 }
9520 break;
43e65147 9521
16980d0b
JB		 9522 case 2:
9523 if (size == 2 && (idx_align & 2) != 0)
78933a4a 9524 return false;
16980d0b
JB		 9525 align = (idx_align & 1) ? 16 << size : 0;
9526 break;
43e65147 9527
16980d0b
JB		 9528 case 3:
9529 if ((size == 2 && (idx_align & 3) != 0)
9530 || (idx_align & 1) != 0)
78933a4a 9531 return false;
16980d0b 9532 break;
43e65147 9533
16980d0b
JB		 9534 case 4:
9535 if (size == 2)
9536 {
9537 if ((idx_align & 3) == 3)
78933a4a 9538 return false;
16980d0b
JB		 9539 align = (idx_align & 3) * 64;
9540 }
9541 else
9542 align = (idx_align & 1) ? 32 << size : 0;
9543 break;
43e65147 9544
16980d0b
JB		 9545 default:
9546 abort ();
9547 }
43e65147 9548
6576bffe 9549 func (stream, dis_style_text, "{");
16980d0b 9550 for (i = 0; i < length; i++)
6576bffe
AB		 9551 {
9552 if (i > 0)
9553 func (stream, dis_style_text, ",");
9554 func (stream, dis_style_register, "d%d[%d]",
9555 rd + i * stride, idx);
9556 }
9557 func (stream, dis_style_text, "}, [");
9558 func (stream, dis_style_register, "%s",
9559 arm_regnames[rn]);
16980d0b 9560 if (align)
6576bffe
AB		 9561 {
9562 func (stream, dis_style_text, " :");
9563 func (stream, dis_style_immediate, "%d", align);
9564 }
9565 func (stream, dis_style_text, "]");
16980d0b 9566 if (rm == 0xd)
6576bffe 9567 func (stream, dis_style_text, "!");
16980d0b 9568 else if (rm != 0xf)
6576bffe
AB		 9569 {
9570 func (stream, dis_style_text, ", ");
9571 func (stream, dis_style_register, "%s",
9572 arm_regnames[rm]);
9573 }
16980d0b
JB		 9574 }
9575 break;
43e65147 9576
16980d0b
JB		 9577 case 'C':
9578 {
9579 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9580 int rn = ((given >> 16) & 0xf);
9581 int rm = ((given >> 0) & 0xf);
9582 int align = ((given >> 4) & 0x1);
9583 int size = ((given >> 6) & 0x3);
9584 int type = ((given >> 8) & 0x3);
9585 int n = type + 1;
9586 int stride = ((given >> 5) & 0x1);
9587 int ix;
43e65147 9588
16980d0b
JB		 9589 if (stride && (n == 1))
9590 n++;
9591 else
9592 stride++;
43e65147 9593
6576bffe 9594 func (stream, dis_style_text, "{");
16980d0b
JB		 9595 if (stride > 1)
9596 for (ix = 0; ix != n; ix++)
6576bffe
AB		 9597 {
9598 if (ix > 0)
9599 func (stream, dis_style_text, ",");
9600 func (stream, dis_style_register, "d%d[]",
9601 rd + ix * stride);
9602 }
16980d0b 9603 else if (n == 1)
6576bffe 9604 func (stream, dis_style_register, "d%d[]", rd);
16980d0b 9605 else
6576bffe
AB		 9606 {
9607 func (stream, dis_style_register, "d%d[]", rd);
9608 func (stream, dis_style_text, "-");
9609 func (stream, dis_style_register, "d%d[]",
9610 rd + n - 1);
9611 }
9612 func (stream, dis_style_text, "}, [");
9613 func (stream, dis_style_register, "%s",
9614 arm_regnames[rn]);
16980d0b
JB		 9615 if (align)
9616 {
91d6fa6a 9617 align = (8 * (type + 1)) << size;
16980d0b
JB		 9618 if (type == 3)
9619 align = (size > 1) ? align >> 1 : align;
9620 if (type == 2 || (type == 0 && !size))
6576bffe
AB		 9621 func (stream, dis_style_text,
9622 " :<bad align %d>", align);
16980d0b 9623 else
6576bffe
AB		 9624 {
9625 func (stream, dis_style_text, " :");
9626 func (stream, dis_style_immediate,
9627 "%d", align);
9628 }
16980d0b 9629 }
6576bffe 9630 func (stream, dis_style_text, "]");
16980d0b 9631 if (rm == 0xd)
6576bffe 9632 func (stream, dis_style_text, "!");
16980d0b 9633 else if (rm != 0xf)
6576bffe
AB		 9634 {
9635 func (stream, dis_style_text, ", ");
9636 func (stream, dis_style_register, "%s",
9637 arm_regnames[rm]);
9638 }
16980d0b
JB		 9639 }
9640 break;
43e65147 9641
16980d0b
JB		 9642 case 'D':
9643 {
9644 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9645 int size = (given >> 20) & 3;
9646 int reg = raw_reg & ((4 << size) - 1);
9647 int ix = raw_reg >> size >> 2;
43e65147 9648
6576bffe 9649 func (stream, dis_style_register, "d%d[%d]", reg, ix);
16980d0b
JB		 9650 }
9651 break;
43e65147 9652
16980d0b 9653 case 'E':
fe56b6ce 9654 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9655 {
9656 int bits = 0;
9657 int cmode = (given >> 8) & 0xf;
9658 int op = (given >> 5) & 0x1;
9659 unsigned long value = 0, hival = 0;
9660 unsigned shift;
9661 int size = 0;
0dbde4cf 9662 int isfloat = 0;
43e65147 9663
16980d0b
JB		 9664 bits |= ((given >> 24) & 1) << 7;
9665 bits |= ((given >> 16) & 7) << 4;
9666 bits |= ((given >> 0) & 15) << 0;
43e65147 9667
16980d0b
JB		 9668 if (cmode < 8)
9669 {
9670 shift = (cmode >> 1) & 3;
fe56b6ce 9671 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9672 size = 32;
9673 }
9674 else if (cmode < 12)
9675 {
9676 shift = (cmode >> 1) & 1;
fe56b6ce 9677 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9678 size = 16;
9679 }
9680 else if (cmode < 14)
9681 {
9682 shift = (cmode & 1) + 1;
fe56b6ce 9683 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9684 value |= (1ul << (8 * shift)) - 1;
9685 size = 32;
9686 }
9687 else if (cmode == 14)
9688 {
9689 if (op)
9690 {
fe56b6ce 9691 /* Bit replication into bytes. */
16980d0b
JB		 9692 int ix;
9693 unsigned long mask;
43e65147 9694
16980d0b
JB		 9695 value = 0;
9696 hival = 0;
9697 for (ix = 7; ix >= 0; ix--)
9698 {
9699 mask = ((bits >> ix) & 1) ? 0xff : 0;
9700 if (ix <= 3)
9701 value = (value << 8) | mask;
9702 else
9703 hival = (hival << 8) | mask;
9704 }
9705 size = 64;
9706 }
9707 else
9708 {
fe56b6ce
NC		 9709 /* Byte replication. */
9710 value = (unsigned long) bits;
16980d0b
JB		 9711 size = 8;
9712 }
9713 }
9714 else if (!op)
9715 {
fe56b6ce 9716 /* Floating point encoding. */
16980d0b 9717 int tmp;
43e65147 9718
fe56b6ce
NC		 9719 value = (unsigned long) (bits & 0x7f) << 19;
9720 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9721 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9722 value |= (unsigned long) tmp << 24;
16980d0b 9723 size = 32;
0dbde4cf 9724 isfloat = 1;
16980d0b
JB		 9725 }
9726 else
9727 {
6576bffe
AB		 9728 func (stream, dis_style_text,
9729 "<illegal constant %.8x:%x:%x>",
16980d0b
JB		 9730 bits, cmode, op);
9731 size = 32;
9732 break;
9733 }
9734 switch (size)
9735 {
9736 case 8:
6576bffe
AB		 9737 func (stream, dis_style_immediate, "#%ld", value);
9738 func (stream, dis_style_comment_start,
9739 "\t@ 0x%.2lx", value);
16980d0b 9740 break;
43e65147 9741
16980d0b 9742 case 16:
6576bffe
AB		 9743 func (stream, dis_style_immediate, "#%ld", value);
9744 func (stream, dis_style_comment_start,
9745 "\t@ 0x%.4lx", value);
16980d0b
JB		 9746 break;
9747
9748 case 32:
0dbde4cf
JB		 9749 if (isfloat)
9750 {
9751 unsigned char valbytes[4];
9752 double fvalue;
43e65147 9753
0dbde4cf
JB		 9754 /* Do this a byte at a time so we don't have to
9755 worry about the host's endianness. */
9756 valbytes[0] = value & 0xff;
9757 valbytes[1] = (value >> 8) & 0xff;
9758 valbytes[2] = (value >> 16) & 0xff;
9759 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9760
9761 floatformat_to_double
c1e26897
NC		 9762 (& floatformat_ieee_single_little, valbytes,
9763 & fvalue);
43e65147 9764
6576bffe
AB		 9765 func (stream, dis_style_immediate,
9766 "#%.7g", fvalue);
9767 func (stream, dis_style_comment_start,
9768 "\t@ 0x%.8lx", value);
0dbde4cf
JB		 9769 }
9770 else
6576bffe
AB		 9771 {
9772 func (stream, dis_style_immediate, "#%ld",
9773 (long) (((value & 0x80000000L) != 0)
9774 ? value | ~0xffffffffL : value));
9775 func (stream, dis_style_comment_start,
9776 "\t@ 0x%.8lx", value);
9777 }
16980d0b
JB		 9778 break;
9779
9780 case 64:
6576bffe
AB		 9781 func (stream, dis_style_immediate,
9782 "#0x%.8lx%.8lx", hival, value);
16980d0b 9783 break;
43e65147 9784
16980d0b
JB		 9785 default:
9786 abort ();
9787 }
9788 }
9789 break;
43e65147 9790
16980d0b
JB		 9791 case 'F':
9792 {
9793 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9794 int num = (given >> 8) & 0x3;
43e65147 9795
6576bffe 9796 func (stream, dis_style_text, "{");
16980d0b 9797 if (!num)
6576bffe 9798 func (stream, dis_style_register, "d%d", regno);
16980d0b 9799 else if (num + regno >= 32)
6576bffe
AB		 9800 {
9801 func (stream, dis_style_register, "d%d", regno);
9802 func (stream, dis_style_text, "-<overflow reg d%d",
9803 regno + num);
9804 }
16980d0b 9805 else
6576bffe
AB		 9806 {
9807 func (stream, dis_style_register, "d%d", regno);
9808 func (stream, dis_style_text, "-");
9809 func (stream, dis_style_register, "d%d",
9810 regno + num);
9811 }
9812 func (stream, dis_style_text, "}");
16980d0b
JB		 9813 }
9814 break;
7e8e6784 9815
16980d0b
JB		 9816
9817 case '0': case '1': case '2': case '3': case '4':
9818 case '5': case '6': case '7': case '8': case '9':
9819 {
9820 int width;
9821 unsigned long value;
9822
9823 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9824
16980d0b
JB		 9825 switch (*c)
9826 {
9827 case 'r':
6576bffe
AB		 9828 func (stream, dis_style_register, "%s",
9829 arm_regnames[value]);
16980d0b
JB		 9830 break;
9831 case 'd':
6576bffe 9832 func (stream, base_style, "%ld", value);
05413229 9833 value_in_comment = value;
16980d0b
JB		 9834 break;
9835 case 'e':
6576bffe
AB		 9836 func (stream, dis_style_immediate, "%ld",
9837 (1ul << width) - value);
16980d0b 9838 break;
43e65147 9839
16980d0b
JB		 9840 case 'S':
9841 case 'T':
9842 case 'U':
05413229 9843 /* Various width encodings. */
16980d0b
JB		 9844 {
9845 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9846 int limit;
9847 unsigned low, high;
9848
9849 c++;
9850 if (*c >= '0' && *c <= '9')
9851 limit = *c - '0';
9852 else if (*c >= 'a' && *c <= 'f')
9853 limit = *c - 'a' + 10;
9854 else
9855 abort ();
9856 low = limit >> 2;
9857 high = limit & 3;
9858
9859 if (value < low || value > high)
6576bffe
AB		 9860 func (stream, dis_style_text,
9861 "<illegal width %d>", base << value);
16980d0b 9862 else
6576bffe
AB		 9863 func (stream, base_style, "%d",
9864 base << value);
16980d0b
JB		 9865 }
9866 break;
9867 case 'R':
9868 if (given & (1 << 6))
9869 goto Q;
9870 /* FALLTHROUGH */
9871 case 'D':
6576bffe 9872 func (stream, dis_style_register, "d%ld", value);
16980d0b
JB		 9873 break;
9874 case 'Q':
9875 Q:
9876 if (value & 1)
6576bffe
AB		 9877 func (stream, dis_style_text,
9878 "<illegal reg q%ld.5>", value >> 1);
16980d0b 9879 else
6576bffe
AB		 9880 func (stream, dis_style_register,
9881 "q%ld", value >> 1);
16980d0b 9882 break;
43e65147 9883
16980d0b
JB		 9884 case '`':
9885 c++;
9886 if (value == 0)
6576bffe 9887 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9888 break;
9889 case '\'':
9890 c++;
9891 if (value == ((1ul << width) - 1))
6576bffe 9892 func (stream, dis_style_text, "%c", *c);
16980d0b
JB		 9893 break;
9894 case '?':
6576bffe
AB		 9895 func (stream, dis_style_mnemonic, "%c",
9896 c[(1 << width) - (int) value]);
16980d0b
JB		 9897 c += 1 << width;
9898 break;
9899 default:
9900 abort ();
9901 }
16980d0b 9902 }
dffaa15c
AM		 9903 break;
9904
9905 default:
9906 abort ();
16980d0b
JB		 9907 }
9908 }
9909 else
6576bffe
AB		 9910 {
9911 if (*c == '@')
9912 base_style = dis_style_comment_start;
9913
9914 if (*c == '\t')
9915 base_style = dis_style_text;
9916
9917 func (stream, base_style, "%c", *c);
9918
9919 }
16980d0b 9920 }
05413229
NC		 9921
9922 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 9923 func (stream, dis_style_comment_start, "\t@ 0x%lx",
9924 value_in_comment);
05413229 9925
e2efe87d 9926 if (is_unpredictable)
6576bffe 9927 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
e2efe87d 9928
78933a4a 9929 return true;
16980d0b
JB		 9930 }
9931 }
78933a4a 9932 return false;
16980d0b
JB		 9933}
9934
73cd51e5
AV		 9935/* Print one mve instruction on INFO->STREAM.
9936 Return TRUE if the instuction matched, FALSE if this is not a
9937 recognised mve instruction. */
9938
78933a4a 9939static bool
73cd51e5
AV		 9940print_insn_mve (struct disassemble_info *info, long given)
9941{
9942 const struct mopcode32 *insn;
9943 void *stream = info->stream;
6576bffe
AB		 9944 fprintf_styled_ftype func = info->fprintf_styled_func;
9945 enum disassembler_style base_style = dis_style_mnemonic;
9946 enum disassembler_style old_base_style = base_style;
73cd51e5
AV		 9947
9948 for (insn = mve_opcodes; insn->assembler; insn++)
9949 {
9950 if (((given & insn->mask) == insn->value)
9951 && !is_mve_encoding_conflict (given, insn->mve_op))
9952 {
9953 signed long value_in_comment = 0;
78933a4a
AM		 9954 bool is_unpredictable = false;
9955 bool is_undefined = false;
73cd51e5
AV		 9956 const char *c;
9957 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9958 enum mve_undefined undefined_cond = UNDEF_NONE;
9959
9960 /* Most vector mve instruction are illegal in a it block.
9961 There are a few exceptions; check for them. */
9962 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9963 {
78933a4a 9964 is_unpredictable = true;
73cd51e5
AV		 9965 unpredictable_cond = UNPRED_IT_BLOCK;
9966 }
9967 else if (is_mve_unpredictable (given, insn->mve_op,
9968 &unpredictable_cond))
78933a4a 9969 is_unpredictable = true;
73cd51e5
AV		 9970
9971 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
78933a4a 9972 is_undefined = true;
73cd51e5 9973
c4a23bf8
SP		 9974 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9975 i.e "VMOV Qd, Qm". */
9976 if ((insn->mve_op == MVE_VORR_REG)
9977 && (arm_decode_field (given, 1, 3)
9978 == arm_decode_field (given, 17, 19)))
9979 continue;
9980
73cd51e5
AV		 9981 for (c = insn->assembler; *c; c++)
9982 {
9983 if (*c == '%')
9984 {
9985 switch (*++c)
9986 {
6576bffe
AB		 9987 case '{':
9988 ++c;
9989 if (*c == '\0')
9990 abort ();
9991 old_base_style = base_style;
9992 base_style = decode_base_style (*c);
9993 ++c;
9994 if (*c != ':')
9995 abort ();
9996 break;
9997
9998 case '}':
9999 base_style = old_base_style;
10000 break;
10001
73cd51e5 10002 case '%':
6576bffe 10003 func (stream, base_style, "%%");
73cd51e5
AV		 10004 break;
10005
ef1576a1
AV		 10006 case 'a':
10007 /* Don't print anything for '+' as it is implied. */
10008 if (arm_decode_field (given, 23, 23) == 0)
6576bffe 10009 func (stream, dis_style_immediate, "-");
ef1576a1
AV		 10010 break;
10011
143275ea
AV		 10012 case 'c':
10013 if (ifthen_state)
6576bffe
AB		 10014 func (stream, dis_style_mnemonic, "%s",
10015 arm_conditional[IFTHEN_COND]);
143275ea
AV		 10016 break;
10017
aef6d006
AV		 10018 case 'd':
10019 print_mve_vld_str_addr (info, given, insn->mve_op);
10020 break;
10021
143275ea
AV		 10022 case 'i':
10023 {
10024 long mve_mask = mve_extract_pred_mask (given);
6576bffe
AB		 10025 func (stream, dis_style_mnemonic, "%s",
10026 mve_predicatenames[mve_mask]);
143275ea
AV		 10027 }
10028 break;
10029
23d00a41
SD		 10030 case 'j':
10031 {
10032 unsigned int imm5 = 0;
10033 imm5 |= arm_decode_field (given, 6, 7);
10034 imm5 |= (arm_decode_field (given, 12, 14) << 2);
6576bffe
AB		 10035 func (stream, dis_style_immediate, "#%u",
10036 (imm5 == 0) ? 32 : imm5);
23d00a41
SD		 10037 }
10038 break;
10039
08132bdd 10040 case 'k':
6576bffe 10041 func (stream, dis_style_immediate, "#%u",
08132bdd
SP		 10042 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
10043 break;
10044
143275ea
AV		 10045 case 'n':
10046 print_vec_condition (info, given, insn->mve_op);
10047 break;
10048
ef1576a1
AV		 10049 case 'o':
10050 if (arm_decode_field (given, 0, 0) == 1)
10051 {
10052 unsigned long size
10053 = arm_decode_field (given, 4, 4)
10054 | (arm_decode_field (given, 6, 6) << 1);
10055
6576bffe
AB		 10056 func (stream, dis_style_text, ", ");
10057 func (stream, dis_style_sub_mnemonic, "uxtw ");
10058 func (stream, dis_style_immediate, "#%lu", size);
ef1576a1
AV		 10059 }
10060 break;
10061
bf0b396d
AV		 10062 case 'm':
10063 print_mve_rounding_mode (info, given, insn->mve_op);
10064 break;
10065
10066 case 's':
10067 print_mve_vcvt_size (info, given, insn->mve_op);
10068 break;
10069
aef6d006
AV		 10070 case 'u':
10071 {
c507f10b
AV		 10072 unsigned long op1 = arm_decode_field (given, 21, 22);
10073
10074 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
10075 {
10076 /* Check for signed. */
10077 if (arm_decode_field (given, 23, 23) == 0)
10078 {
10079 /* We don't print 's' for S32. */
10080 if ((arm_decode_field (given, 5, 6) == 0)
10081 && ((op1 == 0) || (op1 == 1)))
10082 ;
10083 else
6576bffe 10084 func (stream, dis_style_mnemonic, "s");
c507f10b
AV		 10085 }
10086 else
6576bffe 10087 func (stream, dis_style_mnemonic, "u");
c507f10b 10088 }
aef6d006 10089 else
c507f10b
AV		 10090 {
10091 if (arm_decode_field (given, 28, 28) == 0)
6576bffe 10092 func (stream, dis_style_mnemonic, "s");
c507f10b 10093 else
6576bffe 10094 func (stream, dis_style_mnemonic, "u");
c507f10b 10095 }
aef6d006 10096 }
ef1576a1 10097 break;
aef6d006 10098
143275ea
AV		 10099 case 'v':
10100 print_instruction_predicate (info);
10101 break;
10102
04d54ace
AV		 10103 case 'w':
10104 if (arm_decode_field (given, 21, 21) == 1)
6576bffe 10105 func (stream, dis_style_text, "!");
04d54ace
AV		 10106 break;
10107
10108 case 'B':
10109 print_mve_register_blocks (info, given, insn->mve_op);
10110 break;
10111
c507f10b
AV		 10112 case 'E':
10113 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
10114
10115 print_simd_imm8 (info, given, 28, insn);
10116 break;
10117
10118 case 'N':
10119 print_mve_vmov_index (info, given);
10120 break;
10121
14925797
AV		 10122 case 'T':
10123 if (arm_decode_field (given, 12, 12) == 0)
6576bffe 10124 func (stream, dis_style_mnemonic, "b");
14925797 10125 else
6576bffe 10126 func (stream, dis_style_mnemonic, "t");
14925797
AV		 10127 break;
10128
d3b63143
AV		 10129 case 'X':
10130 if (arm_decode_field (given, 12, 12) == 1)
6576bffe 10131 func (stream, dis_style_mnemonic, "x");
d3b63143
AV		 10132 break;
10133
143275ea
AV		 10134 case '0': case '1': case '2': case '3': case '4':
10135 case '5': case '6': case '7': case '8': case '9':
10136 {
10137 int width;
10138 unsigned long value;
10139
10140 c = arm_decode_bitfield (c, given, &value, &width);
10141
10142 switch (*c)
10143 {
10144 case 'Z':
10145 if (value == 13)
78933a4a 10146 is_unpredictable = true;
143275ea 10147 else if (value == 15)
6576bffe 10148 func (stream, dis_style_register, "zr");
143275ea 10149 else
6576bffe
AB		 10150 func (stream, dis_style_register, "%s",
10151 arm_regnames[value]);
143275ea 10152 break;
23d00a41 10153
e39c1607 10154 case 'c':
6576bffe
AB		 10155 func (stream, dis_style_sub_mnemonic, "%s",
10156 arm_conditional[value]);
e39c1607
SD		 10157 break;
10158
10159 case 'C':
10160 value ^= 1;
6576bffe
AB		 10161 func (stream, dis_style_sub_mnemonic, "%s",
10162 arm_conditional[value]);
e39c1607
SD		 10163 break;
10164
23d00a41
SD		 10165 case 'S':
10166 if (value == 13 || value == 15)
78933a4a 10167 is_unpredictable = true;
23d00a41 10168 else
6576bffe
AB		 10169 func (stream, dis_style_register, "%s",
10170 arm_regnames[value]);
23d00a41
SD		 10171 break;
10172
143275ea
AV		 10173 case 's':
10174 print_mve_size (info,
10175 value,
10176 insn->mve_op);
10177 break;
66dcaa5d
AV		 10178 case 'I':
10179 if (value == 1)
6576bffe 10180 func (stream, dis_style_mnemonic, "i");
66dcaa5d 10181 break;
d3b63143
AV		 10182 case 'A':
10183 if (value == 1)
6576bffe 10184 func (stream, dis_style_mnemonic, "a");
d3b63143 10185 break;
1c8f2df8
AV		 10186 case 'h':
10187 {
10188 unsigned int odd_reg = (value << 1) | 1;
6576bffe
AB		 10189 func (stream, dis_style_register, "%s",
10190 arm_regnames[odd_reg]);
1c8f2df8
AV		 10191 }
10192 break;
ef1576a1
AV		 10193 case 'i':
10194 {
10195 unsigned long imm
10196 = arm_decode_field (given, 0, 6);
10197 unsigned long mod_imm = imm;
10198
10199 switch (insn->mve_op)
10200 {
10201 case MVE_VLDRW_GATHER_T5:
10202 case MVE_VSTRW_SCATTER_T5:
10203 mod_imm = mod_imm << 2;
10204 break;
10205 case MVE_VSTRD_SCATTER_T6:
10206 case MVE_VLDRD_GATHER_T6:
10207 mod_imm = mod_imm << 3;
10208 break;
10209
10210 default:
10211 break;
10212 }
10213
6576bffe
AB		 10214 func (stream, dis_style_immediate, "%lu",
10215 mod_imm);
ef1576a1
AV		 10216 }
10217 break;
bf0b396d 10218 case 'k':
6576bffe
AB		 10219 func (stream, dis_style_immediate, "%lu",
10220 64 - value);
bf0b396d 10221 break;
1c8f2df8
AV		 10222 case 'l':
10223 {
10224 unsigned int even_reg = value << 1;
6576bffe
AB		 10225 func (stream, dis_style_register, "%s",
10226 arm_regnames[even_reg]);
1c8f2df8
AV		 10227 }
10228 break;
10229 case 'u':
10230 switch (value)
10231 {
10232 case 0:
6576bffe 10233 func (stream, dis_style_immediate, "1");
1c8f2df8
AV		 10234 break;
10235 case 1:
6576bffe 10236 func (stream, dis_style_immediate, "2");
1c8f2df8
AV		 10237 break;
10238 case 2:
6576bffe 10239 func (stream, dis_style_immediate, "4");
1c8f2df8
AV		 10240 break;
10241 case 3:
6576bffe 10242 func (stream, dis_style_immediate, "8");
1c8f2df8
AV		 10243 break;
10244 default:
10245 break;
10246 }
10247 break;
897b9bbc
AV		 10248 case 'o':
10249 print_mve_rotate (info, value, width);
10250 break;
9743db03 10251 case 'r':
6576bffe
AB		 10252 func (stream, dis_style_register, "%s",
10253 arm_regnames[value]);
9743db03 10254 break;
04d54ace 10255 case 'd':
f9d6cf2e 10256 if (mve_shift_insn_p (insn->mve_op))
ed63aa17
AV		 10257 print_mve_shift_n (info, given, insn->mve_op);
10258 else if (insn->mve_op == MVE_VSHLL_T2)
10259 {
10260 switch (value)
10261 {
10262 case 0x00:
6576bffe 10263 func (stream, dis_style_immediate, "8");
ed63aa17
AV		 10264 break;
10265 case 0x01:
6576bffe 10266 func (stream, dis_style_immediate, "16");
ed63aa17
AV		 10267 break;
10268 case 0x10:
10269 print_mve_undefined (info, UNDEF_SIZE_0);
10270 break;
10271 default:
10272 assert (0);
10273 break;
10274 }
10275 }
10276 else
10277 {
10278 if (insn->mve_op == MVE_VSHLC && value == 0)
10279 value = 32;
6576bffe 10280 func (stream, base_style, "%ld", value);
ed63aa17
AV		 10281 value_in_comment = value;
10282 }
04d54ace 10283 break;
c507f10b 10284 case 'F':
6576bffe 10285 func (stream, dis_style_register, "s%ld", value);
c507f10b 10286 break;
143275ea
AV		 10287 case 'Q':
10288 if (value & 0x8)
6576bffe
AB		 10289 func (stream, dis_style_text,
10290 "<illegal reg q%ld.5>", value);
143275ea 10291 else
6576bffe 10292 func (stream, dis_style_register, "q%ld", value);
143275ea 10293 break;
c507f10b 10294 case 'x':
6576bffe
AB		 10295 func (stream, dis_style_immediate,
10296 "0x%08lx", value);
c507f10b 10297 break;
143275ea
AV		 10298 default:
10299 abort ();
10300 }
10301 break;
10302 default:
10303 abort ();
10304 }
73cd51e5
AV		 10305 }
10306 }
10307 else
6576bffe
AB		 10308 {
10309 if (*c == '@')
10310 base_style = dis_style_comment_start;
10311
10312 if (*c == '\t')
10313 base_style = dis_style_text;
10314
10315 func (stream, base_style, "%c", *c);
10316 }
73cd51e5
AV		 10317 }
10318
10319 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 10320 func (stream, dis_style_comment_start, "\t@ 0x%lx",
10321 value_in_comment);
73cd51e5
AV		 10322
10323 if (is_unpredictable)
10324 print_mve_unpredictable (info, unpredictable_cond);
10325
10326 if (is_undefined)
10327 print_mve_undefined (info, undefined_cond);
10328
63b4cc53 10329 if (!vpt_block_state.in_vpt_block
143275ea 10330 && !ifthen_state
63b4cc53 10331 && is_vpt_instruction (given))
143275ea 10332 mark_inside_vpt_block (given);
63b4cc53 10333 else if (vpt_block_state.in_vpt_block)
143275ea
AV		 10334 update_vpt_block_state ();
10335
78933a4a 10336 return true;
73cd51e5
AV		 10337 }
10338 }
78933a4a 10339 return false;
73cd51e5
AV		 10340}
10341
10342
90ec0d68
MGD		 10343/* Return the name of a v7A special register. */
10344
43e65147 10345static const char *
90ec0d68
MGD		 10346banked_regname (unsigned reg)
10347{
10348 switch (reg)
10349 {
10350 case 15: return "CPSR";
43e65147 10351 case 32: return "R8_usr";
90ec0d68
MGD		 10352 case 33: return "R9_usr";
10353 case 34: return "R10_usr";
10354 case 35: return "R11_usr";
10355 case 36: return "R12_usr";
10356 case 37: return "SP_usr";
10357 case 38: return "LR_usr";
43e65147 10358 case 40: return "R8_fiq";
90ec0d68
MGD		 10359 case 41: return "R9_fiq";
10360 case 42: return "R10_fiq";
10361 case 43: return "R11_fiq";
10362 case 44: return "R12_fiq";
10363 case 45: return "SP_fiq";
10364 case 46: return "LR_fiq";
10365 case 48: return "LR_irq";
10366 case 49: return "SP_irq";
10367 case 50: return "LR_svc";
10368 case 51: return "SP_svc";
10369 case 52: return "LR_abt";
10370 case 53: return "SP_abt";
10371 case 54: return "LR_und";
10372 case 55: return "SP_und";
10373 case 60: return "LR_mon";
10374 case 61: return "SP_mon";
10375 case 62: return "ELR_hyp";
10376 case 63: return "SP_hyp";
10377 case 79: return "SPSR";
10378 case 110: return "SPSR_fiq";
10379 case 112: return "SPSR_irq";
10380 case 114: return "SPSR_svc";
10381 case 116: return "SPSR_abt";
10382 case 118: return "SPSR_und";
10383 case 124: return "SPSR_mon";
10384 case 126: return "SPSR_hyp";
10385 default: return NULL;
10386 }
10387}
10388
e797f7e0
MGD		 10389/* Return the name of the DMB/DSB option. */
10390static const char *
10391data_barrier_option (unsigned option)
10392{
10393 switch (option & 0xf)
10394 {
10395 case 0xf: return "sy";
10396 case 0xe: return "st";
10397 case 0xd: return "ld";
10398 case 0xb: return "ish";
10399 case 0xa: return "ishst";
10400 case 0x9: return "ishld";
10401 case 0x7: return "un";
10402 case 0x6: return "unst";
10403 case 0x5: return "nshld";
10404 case 0x3: return "osh";
10405 case 0x2: return "oshst";
10406 case 0x1: return "oshld";
10407 default: return NULL;
10408 }
10409}
10410
4a5329c6
ZW		 10411/* Print one ARM instruction from PC on INFO->STREAM. */
10412
10413static void
10414print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10415{
6b5d3a4d 10416 const struct opcode32 *insn;
6a51a8a8 10417 void *stream = info->stream;
6576bffe 10418 fprintf_styled_ftype func = info->fprintf_styled_func;
b0e28b39 10419 struct arm_private_data *private_data = info->private_data;
6576bffe
AB		 10420 enum disassembler_style base_style = dis_style_mnemonic;
10421 enum disassembler_style old_base_style = base_style;
252b5132 10422
78933a4a 10423 if (print_insn_coprocessor (pc, info, given, false))
16980d0b
JB		 10424 return;
10425
78933a4a 10426 if (print_insn_neon (info, given, false))
8f06b2d8
PB		 10427 return;
10428
78933a4a 10429 if (print_insn_generic_coprocessor (pc, info, given, false))
33593eaf
MM		 10430 return;
10431
252b5132
RH		 10432 for (insn = arm_opcodes; insn->assembler; insn++)
10433 {
0313a2b8
NC		 10434 if ((given & insn->mask) != insn->value)
10435 continue;
823d2571
TG		 10436
10437 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 10438 continue;
10439
10440 /* Special case: an instruction with all bits set in the condition field
10441 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10442 or by the catchall at the end of the table. */
10443 if ((given & 0xF0000000) != 0xF0000000
10444 || (insn->mask & 0xF0000000) == 0xF0000000
10445 || (insn->mask == 0 && insn->value == 0))
252b5132 10446 {
ff4a8d2b
NC		 10447 unsigned long u_reg = 16;
10448 unsigned long U_reg = 16;
78933a4a 10449 bool is_unpredictable = false;
05413229 10450 signed long value_in_comment = 0;
6b5d3a4d 10451 const char *c;
b34976b6 10452
252b5132
RH		 10453 for (c = insn->assembler; *c; c++)
10454 {
10455 if (*c == '%')
10456 {
78933a4a 10457 bool allow_unpredictable = false;
c1e26897 10458
252b5132
RH		 10459 switch (*++c)
10460 {
6576bffe
AB		 10461 case '{':
10462 ++c;
10463 if (*c == '\0')
10464 abort ();
10465 old_base_style = base_style;
10466 base_style = decode_base_style (*c);
10467 ++c;
10468 if (*c != ':')
10469 abort ();
10470 break;
10471
10472 case '}':
10473 base_style = old_base_style;
10474 break;
10475
252b5132 10476 case '%':
6576bffe 10477 func (stream, base_style, "%%");
252b5132
RH		 10478 break;
10479
10480 case 'a':
05413229 10481 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10482 break;
252b5132 10483
62b3e311
PB		 10484 case 'P':
10485 /* Set P address bit and use normal address
10486 printing routine. */
c1e26897 10487 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10488 break;
10489
c1e26897 10490 case 'S':
78933a4a 10491 allow_unpredictable = true;
1a0670f3 10492 /* Fall through. */
252b5132
RH		 10493 case 's':
10494 if ((given & 0x004f0000) == 0x004f0000)
10495 {
58efb6c0 10496 /* PC relative with immediate offset. */
f8b960bc 10497 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10498
aefd8a40
NC		 10499 if (PRE_BIT_SET)
10500 {
26d97720
NS		 10501 /* Elide positive zero offset. */
10502 if (offset || NEGATIVE_BIT_SET)
6576bffe
AB		 10503 {
10504 func (stream, dis_style_text, "[");
10505 func (stream, dis_style_register, "pc");
10506 func (stream, dis_style_text, ", ");
10507 func (stream, dis_style_immediate, "#%s%d",
10508 (NEGATIVE_BIT_SET ? "-" : ""),
10509 (int) offset);
10510 func (stream, dis_style_text, "]");
10511 }
945ee430 10512 else
6576bffe
AB		 10513 {
10514 func (stream, dis_style_text, "[");
10515 func (stream, dis_style_register, "pc");
10516 func (stream, dis_style_text, "]");
10517 }
26d97720
NS		 10518 if (NEGATIVE_BIT_SET)
10519 offset = -offset;
6576bffe 10520 func (stream, dis_style_comment_start, "\t@ ");
aefd8a40
NC		 10521 info->print_address_func (offset + pc + 8, info);
10522 }
10523 else
10524 {
26d97720 10525 /* Always show the offset. */
6576bffe
AB		 10526 func (stream, dis_style_text, "[");
10527 func (stream, dis_style_register, "pc");
10528 func (stream, dis_style_text, "], ");
10529 func (stream, dis_style_immediate, "#%s%d",
d908c8af 10530 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b 10531 if (! allow_unpredictable)
78933a4a 10532 is_unpredictable = true;
aefd8a40 10533 }
252b5132
RH		 10534 }
10535 else
10536 {
fe56b6ce
NC		 10537 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10538
6576bffe
AB		 10539 func (stream, dis_style_text, "[");
10540 func (stream, dis_style_register, "%s",
252b5132 10541 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10542
c1e26897 10543 if (PRE_BIT_SET)
252b5132 10544 {
c1e26897 10545 if (IMMEDIATE_BIT_SET)
252b5132 10546 {
26d97720
NS		 10547 /* Elide offset for non-writeback
10548 positive zero. */
10549 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10550 || offset)
6576bffe
AB		 10551 {
10552 func (stream, dis_style_text, ", ");
10553 func (stream, dis_style_immediate,
10554 "#%s%d",
10555 (NEGATIVE_BIT_SET ? "-" : ""),
10556 offset);
10557 }
26d97720
NS		 10558
10559 if (NEGATIVE_BIT_SET)
10560 offset = -offset;
945ee430 10561
fe56b6ce 10562 value_in_comment = offset;
252b5132 10563 }
945ee430 10564 else
ff4a8d2b
NC		 10565 {
10566 /* Register Offset or Register Pre-Indexed. */
6576bffe
AB		 10567 func (stream, dis_style_text, ", %s",
10568 NEGATIVE_BIT_SET ? "-" : "");
10569 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10570 arm_regnames[given & 0xf]);
10571
10572 /* Writing back to the register that is the source/
10573 destination of the load/store is unpredictable. */
10574 if (! allow_unpredictable
10575 && WRITEBACK_BIT_SET
10576 && ((given & 0xf) == ((given >> 12) & 0xf)))
78933a4a 10577 is_unpredictable = true;
ff4a8d2b 10578 }
252b5132 10579
6576bffe 10580 func (stream, dis_style_text, "]%s",
c1e26897 10581 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10582 }
945ee430 10583 else
252b5132 10584 {
c1e26897 10585 if (IMMEDIATE_BIT_SET)
252b5132 10586 {
945ee430 10587 /* Immediate Post-indexed. */
aefd8a40 10588 /* PR 10924: Offset must be printed, even if it is zero. */
6576bffe
AB		 10589 func (stream, dis_style_text, "], ");
10590 func (stream, dis_style_immediate, "#%s%d",
26d97720
NS		 10591 NEGATIVE_BIT_SET ? "-" : "", offset);
10592 if (NEGATIVE_BIT_SET)
10593 offset = -offset;
fe56b6ce 10594 value_in_comment = offset;
252b5132 10595 }
945ee430 10596 else
ff4a8d2b
NC		 10597 {
10598 /* Register Post-indexed. */
6576bffe
AB		 10599 func (stream, dis_style_text, "], %s",
10600 NEGATIVE_BIT_SET ? "-" : "");
10601 func (stream, dis_style_register, "%s",
ff4a8d2b
NC		 10602 arm_regnames[given & 0xf]);
10603
10604 /* Writing back to the register that is the source/
10605 destination of the load/store is unpredictable. */
10606 if (! allow_unpredictable
10607 && (given & 0xf) == ((given >> 12) & 0xf))
78933a4a 10608 is_unpredictable = true;
ff4a8d2b 10609 }
c1e26897 10610
07a28fab
NC		 10611 if (! allow_unpredictable)
10612 {
10613 /* Writeback is automatically implied by post- addressing.
10614 Setting the W bit is unnecessary and ARM specify it as
10615 being unpredictable. */
10616 if (WRITEBACK_BIT_SET
10617 /* Specifying the PC register as the post-indexed
10618 registers is also unpredictable. */
ab8e2090 10619 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
78933a4a 10620 is_unpredictable = true;
07a28fab 10621 }
252b5132
RH		 10622 }
10623 }
10624 break;
b34976b6 10625
252b5132 10626 case 'b':
6b5d3a4d 10627 {
f8b960bc 10628 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10629 bfd_vma target = disp * 4 + pc + 8;
10630 info->print_address_func (target, info);
10631
10632 /* Fill in instruction information. */
10633 info->insn_info_valid = 1;
10634 info->insn_type = dis_branch;
10635 info->target = target;
6b5d3a4d 10636 }
252b5132
RH		 10637 break;
10638
10639 case 'c':
c22aaad1 10640 if (((given >> 28) & 0xf) != 0xe)
6576bffe 10641 func (stream, dis_style_mnemonic, "%s",
c22aaad1 10642 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10643 break;
10644
10645 case 'm':
10646 {
10647 int started = 0;
10648 int reg;
10649
6576bffe 10650 func (stream, dis_style_text, "{");
252b5132
RH		 10651 for (reg = 0; reg < 16; reg++)
10652 if ((given & (1 << reg)) != 0)
10653 {
10654 if (started)
6576bffe 10655 func (stream, dis_style_text, ", ");
252b5132 10656 started = 1;
6576bffe
AB		 10657 func (stream, dis_style_register, "%s",
10658 arm_regnames[reg]);
252b5132 10659 }
6576bffe 10660 func (stream, dis_style_text, "}");
ab8e2090 10661 if (! started)
78933a4a 10662 is_unpredictable = true;
252b5132
RH		 10663 }
10664 break;
10665
37b37b2d 10666 case 'q':
78933a4a 10667 arm_decode_shift (given, func, stream, false);
37b37b2d
RE		 10668 break;
10669
252b5132
RH		 10670 case 'o':
10671 if ((given & 0x02000000) != 0)
10672 {
a415b1cd
JB		 10673 unsigned int rotate = (given & 0xf00) >> 7;
10674 unsigned int immed = (given & 0xff);
10675 unsigned int a, i;
10676
ebd1c6d1
AM		 10677 a = (immed << ((32 - rotate) & 31)
10678 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10679 /* If there is another encoding with smaller rotate,
10680 the rotate should be specified directly. */
10681 for (i = 0; i < 32; i += 2)
ebd1c6d1 10682 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10683 break;
10684
10685 if (i != rotate)
6576bffe
AB		 10686 {
10687 func (stream, dis_style_immediate, "#%d", immed);
10688 func (stream, dis_style_text, ", ");
10689 func (stream, dis_style_immediate, "%d", rotate);
10690 }
a415b1cd 10691 else
6576bffe 10692 func (stream, dis_style_immediate, "#%d", a);
a415b1cd 10693 value_in_comment = a;
252b5132
RH		 10694 }
10695 else
78933a4a 10696 arm_decode_shift (given, func, stream, true);
252b5132
RH		 10697 break;
10698
10699 case 'p':
10700 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10701 {
823d2571
TG		 10702 arm_feature_set arm_ext_v6 =
10703 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10704
aefd8a40
NC		 10705 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10706 mechanism for setting PSR flag bits. They are
10707 obsolete in V6 onwards. */
823d2571
TG		 10708 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10709 arm_ext_v6))
6576bffe 10710 func (stream, dis_style_mnemonic, "p");
4ab90a7a 10711 else
78933a4a 10712 is_unpredictable = true;
aefd8a40 10713 }
252b5132
RH		 10714 break;
10715
10716 case 't':
10717 if ((given & 0x01200000) == 0x00200000)
6576bffe 10718 func (stream, dis_style_mnemonic, "t");
252b5132
RH		 10719 break;
10720
252b5132 10721 case 'A':
05413229
NC		 10722 {
10723 int offset = given & 0xff;
f02232aa 10724
05413229 10725 value_in_comment = offset * 4;
c1e26897 10726 if (NEGATIVE_BIT_SET)
05413229 10727 value_in_comment = - value_in_comment;
f02232aa 10728
6576bffe
AB		 10729 func (stream, dis_style_text, "[%s",
10730 arm_regnames [(given >> 16) & 0xf]);
f02232aa 10731
c1e26897 10732 if (PRE_BIT_SET)
05413229
NC		 10733 {
10734 if (offset)
6576bffe 10735 func (stream, dis_style_text, ", #%d]%s",
d908c8af 10736 (int) value_in_comment,
c1e26897 10737 WRITEBACK_BIT_SET ? "!" : "");
05413229 10738 else
6576bffe 10739 func (stream, dis_style_text, "]");
05413229
NC		 10740 }
10741 else
10742 {
6576bffe 10743 func (stream, dis_style_text, "]");
f02232aa 10744
c1e26897 10745 if (WRITEBACK_BIT_SET)
05413229
NC		 10746 {
10747 if (offset)
6576bffe
AB		 10748 func (stream, dis_style_text,
10749 ", #%d", (int) value_in_comment);
05413229
NC		 10750 }
10751 else
fe56b6ce 10752 {
6576bffe
AB		 10753 func (stream, dis_style_text,
10754 ", {%d}", (int) offset);
fe56b6ce
NC		 10755 value_in_comment = offset;
10756 }
05413229
NC		 10757 }
10758 }
252b5132
RH		 10759 break;
10760
077b8428
NC		 10761 case 'B':
10762 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10763 {
10764 bfd_vma address;
10765 bfd_vma offset = 0;
b34976b6 10766
c1e26897 10767 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10768 /* Is signed, hi bits should be ones. */
10769 offset = (-1) ^ 0x00ffffff;
10770
10771 /* Offset is (SignExtend(offset field)<<2). */
10772 offset += given & 0x00ffffff;
10773 offset <<= 2;
10774 address = offset + pc + 8;
b34976b6 10775
8f06b2d8
PB		 10776 if (given & 0x01000000)
10777 /* H bit allows addressing to 2-byte boundaries. */
10778 address += 2;
b1ee46c5 10779
8f06b2d8 10780 info->print_address_func (address, info);
1d67fe3b
TT		 10781
10782 /* Fill in instruction information. */
10783 info->insn_info_valid = 1;
10784 info->insn_type = dis_branch;
10785 info->target = address;
b1ee46c5 10786 }
b1ee46c5
AH		 10787 break;
10788
252b5132 10789 case 'C':
90ec0d68
MGD		 10790 if ((given & 0x02000200) == 0x200)
10791 {
10792 const char * name;
10793 unsigned sysm = (given & 0x004f0000) >> 16;
10794
10795 sysm |= (given & 0x300) >> 4;
10796 name = banked_regname (sysm);
10797
10798 if (name != NULL)
6576bffe 10799 func (stream, dis_style_register, "%s", name);
90ec0d68 10800 else
6576bffe
AB		 10801 func (stream, dis_style_text,
10802 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10803 }
10804 else
10805 {
6576bffe 10806 func (stream, dis_style_register, "%cPSR_",
90ec0d68 10807 (given & 0x00400000) ? 'S' : 'C');
6576bffe 10808
90ec0d68 10809 if (given & 0x80000)
6576bffe 10810 func (stream, dis_style_register, "f");
90ec0d68 10811 if (given & 0x40000)
6576bffe 10812 func (stream, dis_style_register, "s");
90ec0d68 10813 if (given & 0x20000)
6576bffe 10814 func (stream, dis_style_register, "x");
90ec0d68 10815 if (given & 0x10000)
6576bffe 10816 func (stream, dis_style_register, "c");
90ec0d68 10817 }
252b5132
RH		 10818 break;
10819
62b3e311 10820 case 'U':
43e65147 10821 if ((given & 0xf0) == 0x60)
62b3e311 10822 {
52e7f43d
RE		 10823 switch (given & 0xf)
10824 {
6576bffe
AB		 10825 case 0xf:
10826 func (stream, dis_style_sub_mnemonic, "sy");
10827 break;
52e7f43d 10828 default:
6576bffe
AB		 10829 func (stream, dis_style_immediate, "#%d",
10830 (int) given & 0xf);
52e7f43d
RE		 10831 break;
10832 }
43e65147
L		 10833 }
10834 else
52e7f43d 10835 {
e797f7e0
MGD		 10836 const char * opt = data_barrier_option (given & 0xf);
10837 if (opt != NULL)
6576bffe 10838 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 10839 else
6576bffe
AB		 10840 func (stream, dis_style_immediate,
10841 "#%d", (int) given & 0xf);
62b3e311
PB		 10842 }
10843 break;
10844
b34976b6 10845 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10846 case '5': case '6': case '7': case '8': case '9':
10847 {
16980d0b
JB		 10848 int width;
10849 unsigned long value;
252b5132 10850
16980d0b 10851 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10852
252b5132
RH		 10853 switch (*c)
10854 {
ab8e2090
NC		 10855 case 'R':
10856 if (value == 15)
78933a4a 10857 is_unpredictable = true;
ab8e2090 10858 /* Fall through. */
16980d0b 10859 case 'r':
9eb6c0f1
MGD		 10860 case 'T':
10861 /* We want register + 1 when decoding T. */
10862 if (*c == 'T')
2bddb71a 10863 value = (value + 1) & 0xf;
9eb6c0f1 10864
ff4a8d2b
NC		 10865 if (c[1] == 'u')
10866 {
10867 /* Eat the 'u' character. */
10868 ++ c;
10869
10870 if (u_reg == value)
78933a4a 10871 is_unpredictable = true;
ff4a8d2b
NC		 10872 u_reg = value;
10873 }
10874 if (c[1] == 'U')
10875 {
10876 /* Eat the 'U' character. */
10877 ++ c;
10878
10879 if (U_reg == value)
78933a4a 10880 is_unpredictable = true;
ff4a8d2b
NC		 10881 U_reg = value;
10882 }
6576bffe
AB		 10883 func (stream, dis_style_register, "%s",
10884 arm_regnames[value]);
16980d0b
JB		 10885 break;
10886 case 'd':
6576bffe 10887 func (stream, base_style, "%ld", value);
05413229 10888 value_in_comment = value;
16980d0b
JB		 10889 break;
10890 case 'b':
6576bffe
AB		 10891 func (stream, dis_style_immediate,
10892 "%ld", value * 8);
05413229 10893 value_in_comment = value * 8;
16980d0b
JB		 10894 break;
10895 case 'W':
6576bffe
AB		 10896 func (stream, dis_style_immediate,
10897 "%ld", value + 1);
05413229 10898 value_in_comment = value + 1;
16980d0b
JB		 10899 break;
10900 case 'x':
6576bffe
AB		 10901 func (stream, dis_style_immediate,
10902 "0x%08lx", value);
16980d0b
JB		 10903
10904 /* Some SWI instructions have special
10905 meanings. */
10906 if ((given & 0x0fffffff) == 0x0FF00000)
6576bffe
AB		 10907 func (stream, dis_style_comment_start,
10908 "\t@ IMB");
16980d0b 10909 else if ((given & 0x0fffffff) == 0x0FF00001)
6576bffe
AB		 10910 func (stream, dis_style_comment_start,
10911 "\t@ IMBRange");
16980d0b
JB		 10912 break;
10913 case 'X':
6576bffe
AB		 10914 func (stream, dis_style_immediate,
10915 "%01lx", value & 0xf);
05413229 10916 value_in_comment = value;
252b5132
RH		 10917 break;
10918 case '`':
10919 c++;
16980d0b 10920 if (value == 0)
6576bffe 10921 func (stream, dis_style_text, "%c", *c);
252b5132
RH		 10922 break;
10923 case '\'':
10924 c++;
16980d0b 10925 if (value == ((1ul << width) - 1))
6576bffe 10926 func (stream, base_style, "%c", *c);
252b5132
RH		 10927 break;
10928 case '?':
6576bffe
AB		 10929 func (stream, base_style, "%c",
10930 c[(1 << width) - (int) value]);
16980d0b 10931 c += 1 << width;
252b5132
RH		 10932 break;
10933 default:
10934 abort ();
10935 }
dffaa15c
AM		 10936 }
10937 break;
0dd132b6 10938
dffaa15c
AM		 10939 case 'e':
10940 {
10941 int imm;
0dd132b6 10942
dffaa15c 10943 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
6576bffe 10944 func (stream, dis_style_immediate, "%d", imm);
dffaa15c
AM		 10945 value_in_comment = imm;
10946 }
10947 break;
fe56b6ce 10948
dffaa15c
AM		 10949 case 'E':
10950 /* LSB and WIDTH fields of BFI or BFC. The machine-
10951 language instruction encodes LSB and MSB. */
10952 {
10953 long msb = (given & 0x001f0000) >> 16;
10954 long lsb = (given & 0x00000f80) >> 7;
10955 long w = msb - lsb + 1;
0a003adc 10956
dffaa15c 10957 if (w > 0)
6576bffe
AB		 10958 {
10959 func (stream, dis_style_immediate, "#%lu", lsb);
10960 func (stream, dis_style_text, ", ");
10961 func (stream, dis_style_immediate, "#%lu", w);
10962 }
dffaa15c 10963 else
6576bffe
AB		 10964 func (stream, dis_style_text,
10965 "(invalid: %lu:%lu)", lsb, msb);
dffaa15c
AM		 10966 }
10967 break;
90ec0d68 10968
dffaa15c
AM		 10969 case 'R':
10970 /* Get the PSR/banked register name. */
10971 {
10972 const char * name;
10973 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10974
dffaa15c
AM		 10975 sysm |= (given & 0x300) >> 4;
10976 name = banked_regname (sysm);
90ec0d68 10977
dffaa15c 10978 if (name != NULL)
6576bffe 10979 func (stream, dis_style_register, "%s", name);
dffaa15c 10980 else
6576bffe
AB		 10981 func (stream, dis_style_text,
10982 "(UNDEF: %lu)", (unsigned long) sysm);
dffaa15c
AM		 10983 }
10984 break;
fe56b6ce 10985
dffaa15c
AM		 10986 case 'V':
10987 /* 16-bit unsigned immediate from a MOVT or MOVW
10988 instruction, encoded in bits 0:11 and 15:19. */
10989 {
10990 long hi = (given & 0x000f0000) >> 4;
10991 long lo = (given & 0x00000fff);
10992 long imm16 = hi | lo;
0a003adc 10993
6576bffe 10994 func (stream, dis_style_immediate, "#%lu", imm16);
dffaa15c 10995 value_in_comment = imm16;
252b5132 10996 }
dffaa15c
AM		 10997 break;
10998
10999 default:
11000 abort ();
252b5132
RH		 11001 }
11002 }
11003 else
6576bffe
AB		 11004 {
11005
11006 if (*c == '@')
11007 base_style = dis_style_comment_start;
11008
11009 if (*c == '\t')
11010 base_style = dis_style_text;
11011
11012 func (stream, base_style, "%c", *c);
11013 }
252b5132 11014 }
05413229
NC		 11015
11016 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 11017 func (stream, dis_style_comment_start, "\t@ 0x%lx",
11018 (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 11019
11020 if (is_unpredictable)
6576bffe 11021 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 11022
4a5329c6 11023 return;
252b5132
RH		 11024 }
11025 }
6576bffe
AB		 11026 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
11027 (unsigned) given);
0b347048 11028 return;
252b5132
RH		 11029}
11030
4a5329c6 11031/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 11032
4a5329c6
ZW		 11033static void
11034print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 11035{
6b5d3a4d 11036 const struct opcode16 *insn;
6a51a8a8 11037 void *stream = info->stream;
6576bffe
AB		 11038 fprintf_styled_ftype func = info->fprintf_styled_func;
11039 enum disassembler_style base_style = dis_style_mnemonic;
11040 enum disassembler_style old_base_style = base_style;
252b5132
RH		 11041
11042 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 11043 if ((given & insn->mask) == insn->value)
11044 {
05413229 11045 signed long value_in_comment = 0;
6b5d3a4d 11046 const char *c = insn->assembler;
05413229 11047
c19d1205
ZW		 11048 for (; *c; c++)
11049 {
11050 int domaskpc = 0;
11051 int domasklr = 0;
11052
11053 if (*c != '%')
11054 {
6576bffe
AB		 11055 if (*c == '@')
11056 base_style = dis_style_comment_start;
11057
11058 if (*c == '\t')
11059 base_style = dis_style_text;
11060
11061 func (stream, base_style, "%c", *c);
11062
c19d1205
ZW		 11063 continue;
11064 }
252b5132 11065
c19d1205
ZW		 11066 switch (*++c)
11067 {
6576bffe
AB		 11068 case '{':
11069 ++c;
11070 if (*c == '\0')
11071 abort ();
11072 old_base_style = base_style;
11073 base_style = decode_base_style (*c);
11074 ++c;
11075 if (*c != ':')
11076 abort ();
11077 break;
11078
11079 case '}':
11080 base_style = old_base_style;
11081 break;
11082
c19d1205 11083 case '%':
6576bffe 11084 func (stream, base_style, "%%");
c19d1205 11085 break;
b34976b6 11086
c22aaad1
PB		 11087 case 'c':
11088 if (ifthen_state)
6576bffe
AB		 11089 func (stream, dis_style_mnemonic, "%s",
11090 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 11091 break;
11092
11093 case 'C':
11094 if (ifthen_state)
6576bffe
AB		 11095 func (stream, dis_style_mnemonic, "%s",
11096 arm_conditional[IFTHEN_COND]);
c22aaad1 11097 else
6576bffe 11098 func (stream, dis_style_mnemonic, "s");
c22aaad1
PB		 11099 break;
11100
11101 case 'I':
11102 {
11103 unsigned int tmp;
11104
11105 ifthen_next_state = given & 0xff;
11106 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
6576bffe
AB		 11107 func (stream, dis_style_mnemonic,
11108 ((given ^ tmp) & 0x10) ? "e" : "t");
11109 func (stream, dis_style_text, "\t");
11110 func (stream, dis_style_sub_mnemonic, "%s",
11111 arm_conditional[(given >> 4) & 0xf]);
c22aaad1
PB		 11112 }
11113 break;
11114
11115 case 'x':
11116 if (ifthen_next_state)
6576bffe
AB		 11117 func (stream, dis_style_comment_start,
11118 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 11119 break;
11120
11121 case 'X':
11122 if (ifthen_state)
6576bffe
AB		 11123 func (stream, dis_style_comment_start,
11124 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 11125 arm_conditional[IFTHEN_COND]);
11126 break;
11127
c19d1205
ZW		 11128 case 'S':
11129 {
11130 long reg;
11131
11132 reg = (given >> 3) & 0x7;
11133 if (given & (1 << 6))
11134 reg += 8;
4f3c3dbb 11135
6576bffe 11136 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 11137 }
11138 break;
baf0cc5e 11139
c19d1205 11140 case 'D':
4f3c3dbb 11141 {
c19d1205
ZW		 11142 long reg;
11143
11144 reg = given & 0x7;
11145 if (given & (1 << 7))
11146 reg += 8;
11147
6576bffe 11148 func (stream, dis_style_register, "%s", arm_regnames[reg]);
4f3c3dbb 11149 }
c19d1205
ZW		 11150 break;
11151
11152 case 'N':
11153 if (given & (1 << 8))
11154 domasklr = 1;
11155 /* Fall through. */
11156 case 'O':
11157 if (*c == 'O' && (given & (1 << 8)))
11158 domaskpc = 1;
11159 /* Fall through. */
11160 case 'M':
11161 {
11162 int started = 0;
11163 int reg;
11164
6576bffe 11165 func (stream, dis_style_text, "{");
c19d1205
ZW		 11166
11167 /* It would be nice if we could spot
11168 ranges, and generate the rS-rE format: */
11169 for (reg = 0; (reg < 8); reg++)
11170 if ((given & (1 << reg)) != 0)
11171 {
11172 if (started)
6576bffe 11173 func (stream, dis_style_text, ", ");
c19d1205 11174 started = 1;
6576bffe
AB		 11175 func (stream, dis_style_register, "%s",
11176 arm_regnames[reg]);
c19d1205
ZW		 11177 }
11178
11179 if (domasklr)
11180 {
11181 if (started)
6576bffe 11182 func (stream, dis_style_text, ", ");
c19d1205 11183 started = 1;
6576bffe
AB		 11184 func (stream, dis_style_register, "%s",
11185 arm_regnames[14] /* "lr" */);
c19d1205
ZW		 11186 }
11187
11188 if (domaskpc)
11189 {
11190 if (started)
6576bffe
AB		 11191 func (stream, dis_style_text, ", ");
11192 func (stream, dis_style_register, "%s",
11193 arm_regnames[15] /* "pc" */);
c19d1205
ZW		 11194 }
11195
6576bffe 11196 func (stream, dis_style_text, "}");
c19d1205
ZW		 11197 }
11198 break;
11199
4547cb56
NC		 11200 case 'W':
11201 /* Print writeback indicator for a LDMIA. We are doing a
11202 writeback if the base register is not in the register
11203 mask. */
11204 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
6576bffe 11205 func (stream, dis_style_text, "!");
dffaa15c 11206 break;
4547cb56 11207
c19d1205
ZW		 11208 case 'b':
11209 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
11210 {
11211 bfd_vma address = (pc + 4
11212 + ((given & 0x00f8) >> 2)
11213 + ((given & 0x0200) >> 3));
11214 info->print_address_func (address, info);
1d67fe3b
TT		 11215
11216 /* Fill in instruction information. */
11217 info->insn_info_valid = 1;
11218 info->insn_type = dis_branch;
11219 info->target = address;
c19d1205
ZW		 11220 }
11221 break;
11222
11223 case 's':
11224 /* Right shift immediate -- bits 6..10; 1-31 print
11225 as themselves, 0 prints as 32. */
11226 {
11227 long imm = (given & 0x07c0) >> 6;
11228 if (imm == 0)
11229 imm = 32;
6576bffe 11230 func (stream, dis_style_immediate, "#%ld", imm);
c19d1205
ZW		 11231 }
11232 break;
11233
11234 case '0': case '1': case '2': case '3': case '4':
11235 case '5': case '6': case '7': case '8': case '9':
11236 {
11237 int bitstart = *c++ - '0';
11238 int bitend = 0;
11239
11240 while (*c >= '0' && *c <= '9')
11241 bitstart = (bitstart * 10) + *c++ - '0';
11242
11243 switch (*c)
11244 {
11245 case '-':
11246 {
f8b960bc 11247 bfd_vma reg;
c19d1205
ZW		 11248
11249 c++;
11250 while (*c >= '0' && *c <= '9')
11251 bitend = (bitend * 10) + *c++ - '0';
11252 if (!bitend)
11253 abort ();
11254 reg = given >> bitstart;
459cde81 11255 reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
ff4a8d2b 11256
c19d1205
ZW		 11257 switch (*c)
11258 {
11259 case 'r':
6576bffe
AB		 11260 func (stream, dis_style_register, "%s",
11261 arm_regnames[reg]);
c19d1205
ZW		 11262 break;
11263
11264 case 'd':
6576bffe
AB		 11265 func (stream, dis_style_immediate, "%ld",
11266 (long) reg);
05413229 11267 value_in_comment = reg;
c19d1205
ZW		 11268 break;
11269
11270 case 'H':
6576bffe
AB		 11271 func (stream, dis_style_immediate, "%ld",
11272 (long) (reg << 1));
05413229 11273 value_in_comment = reg << 1;
c19d1205
ZW		 11274 break;
11275
11276 case 'W':
6576bffe
AB		 11277 func (stream, dis_style_immediate, "%ld",
11278 (long) (reg << 2));
05413229 11279 value_in_comment = reg << 2;
c19d1205
ZW		 11280 break;
11281
11282 case 'a':
11283 /* PC-relative address -- the bottom two
11284 bits of the address are dropped
11285 before the calculation. */
11286 info->print_address_func
11287 (((pc + 4) & ~3) + (reg << 2), info);
05413229 11288 value_in_comment = 0;
c19d1205
ZW		 11289 break;
11290
11291 case 'x':
6576bffe
AB		 11292 func (stream, dis_style_immediate, "0x%04lx",
11293 (long) reg);
c19d1205
ZW		 11294 break;
11295
c19d1205
ZW		 11296 case 'B':
11297 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 11298 bfd_vma target = reg * 2 + pc + 4;
11299 info->print_address_func (target, info);
05413229 11300 value_in_comment = 0;
1d67fe3b
TT		 11301
11302 /* Fill in instruction information. */
11303 info->insn_info_valid = 1;
11304 info->insn_type = dis_branch;
11305 info->target = target;
c19d1205
ZW		 11306 break;
11307
11308 case 'c':
6576bffe
AB		 11309 func (stream, dis_style_mnemonic, "%s",
11310 arm_conditional [reg]);
c19d1205
ZW		 11311 break;
11312
11313 default:
11314 abort ();
11315 }
11316 }
11317 break;
11318
11319 case '\'':
11320 c++;
11321 if ((given & (1 << bitstart)) != 0)
6576bffe 11322 func (stream, base_style, "%c", *c);
c19d1205
ZW		 11323 break;
11324
11325 case '?':
11326 ++c;
11327 if ((given & (1 << bitstart)) != 0)
6576bffe 11328 func (stream, base_style, "%c", *c++);
c19d1205 11329 else
6576bffe 11330 func (stream, base_style, "%c", *++c);
c19d1205
ZW		 11331 break;
11332
11333 default:
11334 abort ();
11335 }
11336 }
11337 break;
11338
11339 default:
11340 abort ();
11341 }
11342 }
05413229
NC		 11343
11344 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 11345 func (stream, dis_style_comment_start,
11346 "\t@ 0x%lx", value_in_comment);
4a5329c6 11347 return;
c19d1205
ZW		 11348 }
11349
11350 /* No match. */
6576bffe
AB		 11351 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
11352 (unsigned) given);
0b347048 11353 return;
c19d1205
ZW		 11354}
11355
62b3e311 11356/* Return the name of an V7M special register. */
fe56b6ce 11357
62b3e311
PB		 11358static const char *
11359psr_name (int regno)
11360{
11361 switch (regno)
11362 {
1a336194
TP		 11363 case 0x0: return "APSR";
11364 case 0x1: return "IAPSR";
11365 case 0x2: return "EAPSR";
11366 case 0x3: return "PSR";
11367 case 0x5: return "IPSR";
11368 case 0x6: return "EPSR";
11369 case 0x7: return "IEPSR";
11370 case 0x8: return "MSP";
11371 case 0x9: return "PSP";
11372 case 0xa: return "MSPLIM";
11373 case 0xb: return "PSPLIM";
11374 case 0x10: return "PRIMASK";
11375 case 0x11: return "BASEPRI";
11376 case 0x12: return "BASEPRI_MAX";
11377 case 0x13: return "FAULTMASK";
11378 case 0x14: return "CONTROL";
16a1fa25
TP		 11379 case 0x88: return "MSP_NS";
11380 case 0x89: return "PSP_NS";
1a336194
TP		 11381 case 0x8a: return "MSPLIM_NS";
11382 case 0x8b: return "PSPLIM_NS";
11383 case 0x90: return "PRIMASK_NS";
11384 case 0x91: return "BASEPRI_NS";
11385 case 0x93: return "FAULTMASK_NS";
11386 case 0x94: return "CONTROL_NS";
11387 case 0x98: return "SP_NS";
62b3e311
PB		 11388 default: return "<unknown>";
11389 }
11390}
11391
4a5329c6
ZW		 11392/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
11393
11394static void
11395print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 11396{
6b5d3a4d 11397 const struct opcode32 *insn;
c19d1205 11398 void *stream = info->stream;
6576bffe 11399 fprintf_styled_ftype func = info->fprintf_styled_func;
78933a4a 11400 bool is_mve = is_mve_architecture (info);
6576bffe
AB		 11401 enum disassembler_style base_style = dis_style_mnemonic;
11402 enum disassembler_style old_base_style = base_style;
c19d1205 11403
78933a4a 11404 if (print_insn_coprocessor (pc, info, given, true))
16980d0b
JB		 11405 return;
11406
78933a4a 11407 if (!is_mve && print_insn_neon (info, given, true))
73cd51e5
AV		 11408 return;
11409
11410 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 11411 return;
11412
78933a4a 11413 if (print_insn_cde (info, given, true))
4934a27c
MM		 11414 return;
11415
78933a4a 11416 if (print_insn_generic_coprocessor (pc, info, given, true))
33593eaf
MM		 11417 return;
11418
c19d1205
ZW		 11419 for (insn = thumb32_opcodes; insn->assembler; insn++)
11420 if ((given & insn->mask) == insn->value)
11421 {
78933a4a
AM		 11422 bool is_clrm = false;
11423 bool is_unpredictable = false;
05413229 11424 signed long value_in_comment = 0;
6b5d3a4d 11425 const char *c = insn->assembler;
05413229 11426
c19d1205
ZW		 11427 for (; *c; c++)
11428 {
11429 if (*c != '%')
11430 {
6576bffe
AB		 11431 if (*c == '@')
11432 base_style = dis_style_comment_start;
11433 if (*c == '\t')
11434 base_style = dis_style_text;
11435 func (stream, base_style, "%c", *c);
c19d1205
ZW		 11436 continue;
11437 }
11438
11439 switch (*++c)
11440 {
6576bffe
AB		 11441 case '{':
11442 ++c;
11443 if (*c == '\0')
11444 abort ();
11445 old_base_style = base_style;
11446 base_style = decode_base_style (*c);
11447 ++c;
11448 if (*c != ':')
11449 abort ();
11450 break;
11451
11452 case '}':
11453 base_style = old_base_style;
11454 break;
11455
c19d1205 11456 case '%':
6576bffe 11457 func (stream, base_style, "%%");
c19d1205
ZW		 11458 break;
11459
c22aaad1
PB		 11460 case 'c':
11461 if (ifthen_state)
6576bffe
AB		 11462 func (stream, dis_style_mnemonic, "%s",
11463 arm_conditional[IFTHEN_COND]);
c22aaad1
PB		 11464 break;
11465
11466 case 'x':
11467 if (ifthen_next_state)
6576bffe
AB		 11468 func (stream, dis_style_comment_start,
11469 "\t@ unpredictable branch in IT block\n");
c22aaad1
PB		 11470 break;
11471
11472 case 'X':
11473 if (ifthen_state)
6576bffe
AB		 11474 func (stream, dis_style_comment_start,
11475 "\t@ unpredictable <IT:%s>",
c22aaad1
PB		 11476 arm_conditional[IFTHEN_COND]);
11477 break;
11478
c19d1205
ZW		 11479 case 'I':
11480 {
11481 unsigned int imm12 = 0;
fe56b6ce 11482
c19d1205
ZW		 11483 imm12 |= (given & 0x000000ffu);
11484 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 11485 imm12 |= (given & 0x04000000u) >> 15;
6576bffe 11486 func (stream, dis_style_immediate, "#%u", imm12);
fe56b6ce 11487 value_in_comment = imm12;
c19d1205
ZW		 11488 }
11489 break;
11490
11491 case 'M':
11492 {
11493 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 11494
c19d1205
ZW		 11495 bits |= (given & 0x000000ffu);
11496 bits |= (given & 0x00007000u) >> 4;
11497 bits |= (given & 0x04000000u) >> 15;
11498 imm8 = (bits & 0x0ff);
11499 mod = (bits & 0xf00) >> 8;
11500 switch (mod)
11501 {
11502 case 0: imm = imm8; break;
c1e26897
NC		 11503 case 1: imm = ((imm8 << 16) | imm8); break;
11504 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11505 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 11506 default:
11507 mod = (bits & 0xf80) >> 7;
11508 imm8 = (bits & 0x07f) | 0x80;
11509 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11510 }
6576bffe 11511 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11512 value_in_comment = imm;
c19d1205
ZW		 11513 }
11514 break;
43e65147 11515
c19d1205
ZW		 11516 case 'J':
11517 {
11518 unsigned int imm = 0;
fe56b6ce 11519
c19d1205
ZW		 11520 imm |= (given & 0x000000ffu);
11521 imm |= (given & 0x00007000u) >> 4;
11522 imm |= (given & 0x04000000u) >> 15;
11523 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11524 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11525 value_in_comment = imm;
c19d1205
ZW		 11526 }
11527 break;
11528
11529 case 'K':
11530 {
11531 unsigned int imm = 0;
fe56b6ce 11532
c19d1205
ZW		 11533 imm |= (given & 0x000f0000u) >> 16;
11534 imm |= (given & 0x00000ff0u) >> 0;
11535 imm |= (given & 0x0000000fu) << 12;
6576bffe 11536 func (stream, dis_style_immediate, "#%u", imm);
fe56b6ce 11537 value_in_comment = imm;
c19d1205
ZW		 11538 }
11539 break;
11540
74db7efb
NC		 11541 case 'H':
11542 {
11543 unsigned int imm = 0;
11544
11545 imm |= (given & 0x000f0000u) >> 4;
11546 imm |= (given & 0x00000fffu) >> 0;
6576bffe 11547 func (stream, dis_style_immediate, "#%u", imm);
74db7efb
NC		 11548 value_in_comment = imm;
11549 }
11550 break;
11551
90ec0d68
MGD		 11552 case 'V':
11553 {
11554 unsigned int imm = 0;
11555
11556 imm |= (given & 0x00000fffu);
11557 imm |= (given & 0x000f0000u) >> 4;
6576bffe 11558 func (stream, dis_style_immediate, "#%u", imm);
90ec0d68
MGD		 11559 value_in_comment = imm;
11560 }
11561 break;
11562
c19d1205
ZW		 11563 case 'S':
11564 {
11565 unsigned int reg = (given & 0x0000000fu);
11566 unsigned int stp = (given & 0x00000030u) >> 4;
11567 unsigned int imm = 0;
11568 imm |= (given & 0x000000c0u) >> 6;
11569 imm |= (given & 0x00007000u) >> 10;
11570
6576bffe 11571 func (stream, dis_style_register, "%s", arm_regnames[reg]);
c19d1205
ZW		 11572 switch (stp)
11573 {
11574 case 0:
11575 if (imm > 0)
6576bffe
AB		 11576 {
11577 func (stream, dis_style_text, ", ");
11578 func (stream, dis_style_sub_mnemonic, "lsl ");
11579 func (stream, dis_style_immediate, "#%u", imm);
11580 }
c19d1205
ZW		 11581 break;
11582
11583 case 1:
11584 if (imm == 0)
11585 imm = 32;
6576bffe
AB		 11586 func (stream, dis_style_text, ", ");
11587 func (stream, dis_style_sub_mnemonic, "lsr ");
11588 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11589 break;
11590
11591 case 2:
11592 if (imm == 0)
11593 imm = 32;
6576bffe
AB		 11594 func (stream, dis_style_text, ", ");
11595 func (stream, dis_style_sub_mnemonic, "asr ");
11596 func (stream, dis_style_immediate, "#%u", imm);
c19d1205
ZW		 11597 break;
11598
11599 case 3:
11600 if (imm == 0)
6576bffe
AB		 11601 {
11602 func (stream, dis_style_text, ", ");
11603 func (stream, dis_style_sub_mnemonic, "rrx");
11604 }
c19d1205 11605 else
6576bffe
AB		 11606 {
11607 func (stream, dis_style_text, ", ");
11608 func (stream, dis_style_sub_mnemonic, "ror ");
11609 func (stream, dis_style_immediate, "#%u", imm);
11610 }
c19d1205
ZW		 11611 }
11612 }
11613 break;
11614
11615 case 'a':
11616 {
11617 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11618 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11619 unsigned int op = (given & 0x00000f00) >> 8;
11620 unsigned int i12 = (given & 0x00000fff);
11621 unsigned int i8 = (given & 0x000000ff);
78933a4a 11622 bool writeback = false, postind = false;
f8b960bc 11623 bfd_vma offset = 0;
c19d1205 11624
6576bffe
AB		 11625 func (stream, dis_style_text, "[");
11626 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
05413229
NC		 11627 if (U) /* 12-bit positive immediate offset. */
11628 {
11629 offset = i12;
11630 if (Rn != 15)
11631 value_in_comment = offset;
11632 }
11633 else if (Rn == 15) /* 12-bit negative immediate offset. */
11634 offset = - (int) i12;
11635 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11636 {
11637 unsigned int Rm = (i8 & 0x0f);
11638 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11639
6576bffe
AB		 11640 func (stream, dis_style_text, ", ");
11641 func (stream, dis_style_register, "%s",
11642 arm_regnames[Rm]);
c19d1205 11643 if (sh)
6576bffe
AB		 11644 {
11645 func (stream, dis_style_text, ", ");
11646 func (stream, dis_style_sub_mnemonic, "lsl ");
11647 func (stream, dis_style_immediate, "#%u", sh);
11648 }
11649 func (stream, dis_style_text, "]");
c19d1205
ZW		 11650 break;
11651 }
11652 else switch (op)
11653 {
05413229 11654 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11655 offset = i8;
11656 break;
11657
05413229 11658 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11659 offset = -i8;
11660 break;
11661
05413229 11662 case 0xF: /* 8-bit + preindex with wb. */
c19d1205 11663 offset = i8;
78933a4a 11664 writeback = true;
c19d1205
ZW		 11665 break;
11666
05413229 11667 case 0xD: /* 8-bit - preindex with wb. */
c19d1205 11668 offset = -i8;
78933a4a 11669 writeback = true;
c19d1205
ZW		 11670 break;
11671
05413229 11672 case 0xB: /* 8-bit + postindex. */
c19d1205 11673 offset = i8;
78933a4a 11674 postind = true;
c19d1205
ZW		 11675 break;
11676
05413229 11677 case 0x9: /* 8-bit - postindex. */
c19d1205 11678 offset = -i8;
78933a4a 11679 postind = true;
c19d1205
ZW		 11680 break;
11681
11682 default:
6576bffe 11683 func (stream, dis_style_text, ", <undefined>]");
c19d1205
ZW		 11684 goto skip;
11685 }
11686
11687 if (postind)
6576bffe
AB		 11688 {
11689 func (stream, dis_style_text, "], ");
11690 func (stream, dis_style_immediate, "#%d", (int) offset);
11691 }
c19d1205
ZW		 11692 else
11693 {
11694 if (offset)
6576bffe
AB		 11695 {
11696 func (stream, dis_style_text, ", ");
11697 func (stream, dis_style_immediate, "#%d",
11698 (int) offset);
11699 }
11700 func (stream, dis_style_text, writeback ? "]!" : "]");
c19d1205
ZW		 11701 }
11702
11703 if (Rn == 15)
11704 {
6576bffe 11705 func (stream, dis_style_comment_start, "\t@ ");
c19d1205
ZW		 11706 info->print_address_func (((pc + 4) & ~3) + offset, info);
11707 }
11708 }
11709 skip:
11710 break;
11711
11712 case 'A':
11713 {
c1e26897
NC		 11714 unsigned int U = ! NEGATIVE_BIT_SET;
11715 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11716 unsigned int Rn = (given & 0x000f0000) >> 16;
11717 unsigned int off = (given & 0x000000ff);
11718
6576bffe
AB		 11719 func (stream, dis_style_text, "[");
11720 func (stream, dis_style_register, "%s", arm_regnames[Rn]);
c1e26897
NC		 11721
11722 if (PRE_BIT_SET)
c19d1205
ZW		 11723 {
11724 if (off || !U)
05413229 11725 {
6576bffe
AB		 11726 func (stream, dis_style_text, ", ");
11727 func (stream, dis_style_immediate, "#%c%u",
11728 U ? '+' : '-', off * 4);
fe50e98c 11729 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11730 }
6576bffe 11731 func (stream, dis_style_text, "]");
c19d1205 11732 if (W)
6576bffe 11733 func (stream, dis_style_text, "!");
c19d1205
ZW		 11734 }
11735 else
11736 {
6576bffe 11737 func (stream, dis_style_text, "], ");
c19d1205 11738 if (W)
05413229 11739 {
6576bffe
AB		 11740 func (stream, dis_style_immediate, "#%c%u",
11741 U ? '+' : '-', off * 4);
fe50e98c 11742 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11743 }
c19d1205 11744 else
fe56b6ce 11745 {
6576bffe
AB		 11746 func (stream, dis_style_text, "{");
11747 func (stream, dis_style_immediate, "%u", off);
11748 func (stream, dis_style_text, "}");
fe56b6ce
NC		 11749 value_in_comment = off;
11750 }
c19d1205
ZW		 11751 }
11752 }
11753 break;
11754
11755 case 'w':
11756 {
11757 unsigned int Sbit = (given & 0x01000000) >> 24;
11758 unsigned int type = (given & 0x00600000) >> 21;
05413229 11759
c19d1205
ZW		 11760 switch (type)
11761 {
6576bffe
AB		 11762 case 0:
11763 func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11764 break;
11765 case 1:
11766 func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11767 break;
c19d1205
ZW		 11768 case 2:
11769 if (Sbit)
6576bffe 11770 func (stream, dis_style_text, "??");
c19d1205
ZW		 11771 break;
11772 case 3:
6576bffe 11773 func (stream, dis_style_text, "??");
c19d1205
ZW		 11774 break;
11775 }
11776 }
11777 break;
11778
4b5a202f 11779 case 'n':
78933a4a 11780 is_clrm = true;
4b5a202f 11781 /* Fall through. */
c19d1205
ZW		 11782 case 'm':
11783 {
11784 int started = 0;
11785 int reg;
11786
6576bffe 11787 func (stream, dis_style_text, "{");
c19d1205
ZW		 11788 for (reg = 0; reg < 16; reg++)
11789 if ((given & (1 << reg)) != 0)
11790 {
11791 if (started)
6576bffe 11792 func (stream, dis_style_text, ", ");
c19d1205 11793 started = 1;
4b5a202f 11794 if (is_clrm && reg == 13)
6576bffe
AB		 11795 func (stream, dis_style_text, "(invalid: %s)",
11796 arm_regnames[reg]);
4b5a202f 11797 else if (is_clrm && reg == 15)
6576bffe 11798 func (stream, dis_style_register, "%s", "APSR");
4b5a202f 11799 else
6576bffe
AB		 11800 func (stream, dis_style_register, "%s",
11801 arm_regnames[reg]);
c19d1205 11802 }
6576bffe 11803 func (stream, dis_style_text, "}");
c19d1205
ZW		 11804 }
11805 break;
11806
11807 case 'E':
11808 {
11809 unsigned int msb = (given & 0x0000001f);
11810 unsigned int lsb = 0;
fe56b6ce 11811
c19d1205
ZW		 11812 lsb |= (given & 0x000000c0u) >> 6;
11813 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11814 func (stream, dis_style_immediate, "#%u", lsb);
11815 func (stream, dis_style_text, ", ");
11816 func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
c19d1205
ZW		 11817 }
11818 break;
11819
11820 case 'F':
11821 {
11822 unsigned int width = (given & 0x0000001f) + 1;
11823 unsigned int lsb = 0;
fe56b6ce 11824
c19d1205
ZW		 11825 lsb |= (given & 0x000000c0u) >> 6;
11826 lsb |= (given & 0x00007000u) >> 10;
6576bffe
AB		 11827 func (stream, dis_style_immediate, "#%u", lsb);
11828 func (stream, dis_style_text, ", ");
11829 func (stream, dis_style_immediate, "#%u", width);
c19d1205
ZW		 11830 }
11831 break;
11832
e12437dc
AV		 11833 case 'G':
11834 {
11835 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
6576bffe 11836 func (stream, dis_style_immediate, "%x", boff);
e12437dc
AV		 11837 }
11838 break;
11839
e5d6e09e
AV		 11840 case 'W':
11841 {
11842 unsigned int immA = (given & 0x001f0000u) >> 16;
11843 unsigned int immB = (given & 0x000007feu) >> 1;
11844 unsigned int immC = (given & 0x00000800u) >> 11;
11845 bfd_vma offset = 0;
11846
11847 offset |= immA << 12;
11848 offset |= immB << 2;
11849 offset |= immC << 1;
11850 /* Sign extend. */
11851 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11852
11853 info->print_address_func (pc + 4 + offset, info);
11854 }
11855 break;
11856
1caf72a5
AV		 11857 case 'Y':
11858 {
11859 unsigned int immA = (given & 0x007f0000u) >> 16;
11860 unsigned int immB = (given & 0x000007feu) >> 1;
11861 unsigned int immC = (given & 0x00000800u) >> 11;
11862 bfd_vma offset = 0;
11863
11864 offset |= immA << 12;
11865 offset |= immB << 2;
11866 offset |= immC << 1;
11867 /* Sign extend. */
11868 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11869
11870 info->print_address_func (pc + 4 + offset, info);
11871 }
11872 break;
11873
1889da70
AV		 11874 case 'Z':
11875 {
11876 unsigned int immA = (given & 0x00010000u) >> 16;
11877 unsigned int immB = (given & 0x000007feu) >> 1;
11878 unsigned int immC = (given & 0x00000800u) >> 11;
11879 bfd_vma offset = 0;
11880
11881 offset |= immA << 12;
11882 offset |= immB << 2;
11883 offset |= immC << 1;
11884 /* Sign extend. */
11885 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11886
11887 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11888
11889 unsigned int T = (given & 0x00020000u) >> 17;
11890 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11891 unsigned int boffset = (T == 1) ? 4 : 2;
6576bffe
AB		 11892 func (stream, dis_style_text, ", ");
11893 func (stream, dis_style_immediate, "%x",
11894 endoffset + boffset);
1889da70
AV		 11895 }
11896 break;
11897
60f993ce
AV		 11898 case 'Q':
11899 {
11900 unsigned int immh = (given & 0x000007feu) >> 1;
11901 unsigned int imml = (given & 0x00000800u) >> 11;
11902 bfd_vma imm32 = 0;
11903
11904 imm32 |= immh << 2;
11905 imm32 |= imml << 1;
11906
11907 info->print_address_func (pc + 4 + imm32, info);
11908 }
11909 break;
11910
11911 case 'P':
11912 {
11913 unsigned int immh = (given & 0x000007feu) >> 1;
11914 unsigned int imml = (given & 0x00000800u) >> 11;
11915 bfd_vma imm32 = 0;
11916
11917 imm32 |= immh << 2;
11918 imm32 |= imml << 1;
11919
11920 info->print_address_func (pc + 4 - imm32, info);
11921 }
11922 break;
11923
c19d1205
ZW		 11924 case 'b':
11925 {
11926 unsigned int S = (given & 0x04000000u) >> 26;
11927 unsigned int J1 = (given & 0x00002000u) >> 13;
11928 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11929 bfd_vma offset = 0;
c19d1205
ZW		 11930
11931 offset |= !S << 20;
11932 offset |= J2 << 19;
11933 offset |= J1 << 18;
11934 offset |= (given & 0x003f0000) >> 4;
11935 offset |= (given & 0x000007ff) << 1;
11936 offset -= (1 << 20);
11937
1d67fe3b
TT		 11938 bfd_vma target = pc + 4 + offset;
11939 info->print_address_func (target, info);
11940
11941 /* Fill in instruction information. */
11942 info->insn_info_valid = 1;
11943 info->insn_type = dis_branch;
11944 info->target = target;
c19d1205
ZW		 11945 }
11946 break;
11947
11948 case 'B':
11949 {
11950 unsigned int S = (given & 0x04000000u) >> 26;
11951 unsigned int I1 = (given & 0x00002000u) >> 13;
11952 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11953 bfd_vma offset = 0;
c19d1205
ZW		 11954
11955 offset |= !S << 24;
11956 offset |= !(I1 ^ S) << 23;
11957 offset |= !(I2 ^ S) << 22;
11958 offset |= (given & 0x03ff0000u) >> 4;
11959 offset |= (given & 0x000007ffu) << 1;
11960 offset -= (1 << 24);
36b0c57d 11961 offset += pc + 4;
c19d1205 11962
36b0c57d
PB		 11963 /* BLX target addresses are always word aligned. */
11964 if ((given & 0x00001000u) == 0)
11965 offset &= ~2u;
11966
11967 info->print_address_func (offset, info);
1d67fe3b
TT		 11968
11969 /* Fill in instruction information. */
11970 info->insn_info_valid = 1;
11971 info->insn_type = dis_branch;
11972 info->target = offset;
c19d1205
ZW		 11973 }
11974 break;
11975
11976 case 's':
11977 {
11978 unsigned int shift = 0;
fe56b6ce 11979
c19d1205
ZW		 11980 shift |= (given & 0x000000c0u) >> 6;
11981 shift |= (given & 0x00007000u) >> 10;
c1e26897 11982 if (WRITEBACK_BIT_SET)
6576bffe
AB		 11983 {
11984 func (stream, dis_style_text, ", ");
11985 func (stream, dis_style_sub_mnemonic, "asr ");
11986 func (stream, dis_style_immediate, "#%u", shift);
11987 }
c19d1205 11988 else if (shift)
6576bffe
AB		 11989 {
11990 func (stream, dis_style_text, ", ");
11991 func (stream, dis_style_sub_mnemonic, "lsl ");
11992 func (stream, dis_style_immediate, "#%u", shift);
11993 }
c19d1205
ZW		 11994 /* else print nothing - lsl #0 */
11995 }
11996 break;
11997
11998 case 'R':
11999 {
12000 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 12001
c19d1205 12002 if (rot)
6576bffe
AB		 12003 {
12004 func (stream, dis_style_text, ", ");
12005 func (stream, dis_style_sub_mnemonic, "ror ");
12006 func (stream, dis_style_immediate, "#%u", rot * 8);
12007 }
c19d1205
ZW		 12008 }
12009 break;
12010
62b3e311 12011 case 'U':
43e65147 12012 if ((given & 0xf0) == 0x60)
62b3e311 12013 {
52e7f43d
RE		 12014 switch (given & 0xf)
12015 {
6576bffe
AB		 12016 case 0xf:
12017 func (stream, dis_style_sub_mnemonic, "sy");
12018 break;
12019 default:
12020 func (stream, dis_style_immediate, "#%d",
12021 (int) given & 0xf);
12022 break;
52e7f43d 12023 }
62b3e311 12024 }
43e65147 12025 else
52e7f43d 12026 {
e797f7e0
MGD		 12027 const char * opt = data_barrier_option (given & 0xf);
12028 if (opt != NULL)
6576bffe 12029 func (stream, dis_style_sub_mnemonic, "%s", opt);
e797f7e0 12030 else
6576bffe
AB		 12031 func (stream, dis_style_immediate, "#%d",
12032 (int) given & 0xf);
52e7f43d 12033 }
62b3e311
PB		 12034 break;
12035
12036 case 'C':
12037 if ((given & 0xff) == 0)
12038 {
6576bffe
AB		 12039 func (stream, dis_style_register, "%cPSR_",
12040 (given & 0x100000) ? 'S' : 'C');
12041
62b3e311 12042 if (given & 0x800)
6576bffe 12043 func (stream, dis_style_register, "f");
62b3e311 12044 if (given & 0x400)
6576bffe 12045 func (stream, dis_style_register, "s");
62b3e311 12046 if (given & 0x200)
6576bffe 12047 func (stream, dis_style_register, "x");
62b3e311 12048 if (given & 0x100)
6576bffe 12049 func (stream, dis_style_register, "c");
62b3e311 12050 }
90ec0d68
MGD		 12051 else if ((given & 0x20) == 0x20)
12052 {
12053 char const* name;
12054 unsigned sysm = (given & 0xf00) >> 8;
12055
12056 sysm |= (given & 0x30);
12057 sysm |= (given & 0x00100000) >> 14;
12058 name = banked_regname (sysm);
43e65147 12059
90ec0d68 12060 if (name != NULL)
6576bffe 12061 func (stream, dis_style_register, "%s", name);
90ec0d68 12062 else
6576bffe
AB		 12063 func (stream, dis_style_text,
12064 "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 12065 }
62b3e311
PB		 12066 else
12067 {
6576bffe
AB		 12068 func (stream, dis_style_register, "%s",
12069 psr_name (given & 0xff));
62b3e311
PB		 12070 }
12071 break;
12072
12073 case 'D':
90ec0d68
MGD		 12074 if (((given & 0xff) == 0)
12075 || ((given & 0x20) == 0x20))
12076 {
12077 char const* name;
12078 unsigned sm = (given & 0xf0000) >> 16;
12079
12080 sm |= (given & 0x30);
12081 sm |= (given & 0x00100000) >> 14;
12082 name = banked_regname (sm);
12083
12084 if (name != NULL)
6576bffe 12085 func (stream, dis_style_register, "%s", name);
90ec0d68 12086 else
6576bffe
AB		 12087 func (stream, dis_style_text,
12088 "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 12089 }
62b3e311 12090 else
6576bffe
AB		 12091 func (stream, dis_style_register, "%s",
12092 psr_name (given & 0xff));
62b3e311
PB		 12093 break;
12094
c19d1205
ZW		 12095 case '0': case '1': case '2': case '3': case '4':
12096 case '5': case '6': case '7': case '8': case '9':
12097 {
16980d0b
JB		 12098 int width;
12099 unsigned long val;
c19d1205 12100
16980d0b 12101 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 12102
c19d1205
ZW		 12103 switch (*c)
12104 {
d052b9b7
AV		 12105 case 's':
12106 if (val <= 3)
6576bffe
AB		 12107 func (stream, dis_style_mnemonic, "%s",
12108 mve_vec_sizename[val]);
d052b9b7 12109 else
6576bffe 12110 func (stream, dis_style_text, "<undef size>");
d052b9b7
AV		 12111 break;
12112
05413229 12113 case 'd':
6576bffe 12114 func (stream, base_style, "%lu", val);
05413229
NC		 12115 value_in_comment = val;
12116 break;
ff4a8d2b 12117
f0fba320 12118 case 'D':
6576bffe 12119 func (stream, dis_style_immediate, "%lu", val + 1);
f0fba320
RL		 12120 value_in_comment = val + 1;
12121 break;
12122
05413229 12123 case 'W':
6576bffe 12124 func (stream, dis_style_immediate, "%lu", val * 4);
05413229
NC		 12125 value_in_comment = val * 4;
12126 break;
ff4a8d2b 12127
f1c7f421
AV		 12128 case 'S':
12129 if (val == 13)
78933a4a 12130 is_unpredictable = true;
f1c7f421 12131 /* Fall through. */
ff4a8d2b
NC		 12132 case 'R':
12133 if (val == 15)
78933a4a 12134 is_unpredictable = true;
ff4a8d2b
NC		 12135 /* Fall through. */
12136 case 'r':
6576bffe
AB		 12137 func (stream, dis_style_register, "%s",
12138 arm_regnames[val]);
ff4a8d2b 12139 break;
c19d1205
ZW		 12140
12141 case 'c':
6576bffe 12142 func (stream, base_style, "%s", arm_conditional[val]);
c19d1205
ZW		 12143 break;
12144
12145 case '\'':
c19d1205 12146 c++;
16980d0b 12147 if (val == ((1ul << width) - 1))
6576bffe 12148 func (stream, base_style, "%c", *c);
c19d1205 12149 break;
43e65147 12150
c19d1205 12151 case '`':
c19d1205 12152 c++;
16980d0b 12153 if (val == 0)
6576bffe 12154 func (stream, dis_style_immediate, "%c", *c);
c19d1205
ZW		 12155 break;
12156
12157 case '?':
6576bffe
AB		 12158 func (stream, dis_style_mnemonic, "%c",
12159 c[(1 << width) - (int) val]);
16980d0b 12160 c += 1 << width;
c19d1205 12161 break;
43e65147 12162
0bb027fd 12163 case 'x':
6576bffe
AB		 12164 func (stream, dis_style_immediate, "0x%lx",
12165 val & 0xffffffffUL);
0bb027fd 12166 break;
c19d1205
ZW		 12167
12168 default:
12169 abort ();
12170 }
12171 }
12172 break;
12173
32a94698
NC		 12174 case 'L':
12175 /* PR binutils/12534
12176 If we have a PC relative offset in an LDRD or STRD
12177 instructions then display the decoded address. */
12178 if (((given >> 16) & 0xf) == 0xf)
12179 {
12180 bfd_vma offset = (given & 0xff) * 4;
12181
12182 if ((given & (1 << 23)) == 0)
12183 offset = - offset;
6576bffe 12184 func (stream, dis_style_comment_start, "\t@ ");
32a94698
NC		 12185 info->print_address_func ((pc & ~3) + 4 + offset, info);
12186 }
12187 break;
12188
c19d1205
ZW		 12189 default:
12190 abort ();
12191 }
12192 }
05413229
NC		 12193
12194 if (value_in_comment > 32 || value_in_comment < -16)
6576bffe
AB		 12195 func (stream, dis_style_comment_start, "\t@ 0x%lx",
12196 value_in_comment);
ff4a8d2b
NC		 12197
12198 if (is_unpredictable)
6576bffe 12199 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 12200
4a5329c6 12201 return;
c19d1205 12202 }
252b5132 12203
58efb6c0 12204 /* No match. */
6576bffe
AB		 12205 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
12206 (unsigned) given);
0b347048 12207 return;
252b5132
RH		 12208}
12209
e821645d
DJ		 12210/* Print data bytes on INFO->STREAM. */
12211
12212static void
fe56b6ce
NC		 12213print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
12214 struct disassemble_info *info,
e821645d
DJ		 12215 long given)
12216{
6576bffe
AB		 12217 fprintf_styled_ftype func = info->fprintf_styled_func;
12218
e821645d
DJ		 12219 switch (info->bytes_per_chunk)
12220 {
12221 case 1:
6576bffe
AB		 12222 func (info->stream, dis_style_assembler_directive, ".byte");
12223 func (info->stream, dis_style_text, "\t");
12224 func (info->stream, dis_style_immediate, "0x%02lx", given);
e821645d
DJ		 12225 break;
12226 case 2:
6576bffe
AB		 12227 func (info->stream, dis_style_assembler_directive, ".short");
12228 func (info->stream, dis_style_text, "\t");
12229 func (info->stream, dis_style_immediate, "0x%04lx", given);
e821645d
DJ		 12230 break;
12231 case 4:
6576bffe
AB		 12232 func (info->stream, dis_style_assembler_directive, ".word");
12233 func (info->stream, dis_style_text, "\t");
12234 func (info->stream, dis_style_immediate, "0x%08lx", given);
e821645d
DJ		 12235 break;
12236 default:
12237 abort ();
12238 }
12239}
12240
22a398e1 12241/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 12242 being displayed in symbol relative addresses.
12243
12244 Also disallow private symbol, with __tagsym$$ prefix,
12245 from ARM RVCT toolchain being displayed. */
22a398e1 12246
78933a4a 12247bool
22a398e1
NC		 12248arm_symbol_is_valid (asymbol * sym,
12249 struct disassemble_info * info ATTRIBUTE_UNUSED)
12250{
12251 const char * name;
43e65147 12252
22a398e1 12253 if (sym == NULL)
78933a4a 12254 return false;
22a398e1
NC		 12255
12256 name = bfd_asymbol_name (sym);
12257
d8282f0e 12258 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 12259}
12260
65b48a81 12261/* Parse the string of disassembler options. */
baf0cc5e 12262
65b48a81 12263static void
f995bbe8 12264parse_arm_disassembler_options (const char *options)
dd92f639 12265{
f995bbe8 12266 const char *opt;
b34976b6 12267
cad152f2 12268 force_thumb = false;
65b48a81 12269 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 12270 {
08dedd66 12271 if (startswith (opt, "reg-names-"))
65b48a81
PB		 12272 {
12273 unsigned int i;
12274 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12275 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
12276 {
12277 regname_selected = i;
12278 break;
12279 }
b34976b6 12280
65b48a81 12281 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 12282 /* xgettext: c-format */
12283 opcodes_error_handler (_("unrecognised register name set: %s"),
12284 opt);
65b48a81 12285 }
08dedd66 12286 else if (startswith (opt, "force-thumb"))
65b48a81 12287 force_thumb = 1;
08dedd66 12288 else if (startswith (opt, "no-force-thumb"))
65b48a81 12289 force_thumb = 0;
08dedd66 12290 else if (startswith (opt, "coproc"))
4934a27c
MM		 12291 {
12292 const char *procptr = opt + sizeof ("coproc") - 1;
12293 char *endptr;
12294 uint8_t coproc_number = strtol (procptr, &endptr, 10);
12295 if (endptr != procptr + 1 || coproc_number > 7)
12296 {
12297 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
12298 opt);
12299 continue;
12300 }
12301 if (*endptr != '=')
12302 {
12303 opcodes_error_handler (_("coproc must have an argument: %s"),
12304 opt);
12305 continue;
12306 }
12307 endptr += 1;
08dedd66 12308 if (startswith (endptr, "generic"))
4934a27c 12309 cde_coprocs &= ~(1 << coproc_number);
08dedd66
ML		 12310 else if (startswith (endptr, "cde")
12311 || startswith (endptr, "CDE"))
4934a27c
MM		 12312 cde_coprocs |= (1 << coproc_number);
12313 else
12314 {
12315 opcodes_error_handler (
12316 _("coprocN argument takes options \"generic\","
12317 " \"cde\", or \"CDE\": %s"), opt);
12318 }
12319 }
65b48a81 12320 else
a6743a54
AM		 12321 /* xgettext: c-format */
12322 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 12323 }
b34976b6 12324
dd92f639
NC		 12325 return;
12326}
12327
78933a4a 12328static bool
5bc5ae88
RL		 12329mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12330 enum map_type *map_symbol);
12331
c22aaad1
PB		 12332/* Search back through the insn stream to determine if this instruction is
12333 conditionally executed. */
fe56b6ce 12334
c22aaad1 12335static void
fe56b6ce
NC		 12336find_ifthen_state (bfd_vma pc,
12337 struct disassemble_info *info,
78933a4a 12338 bool little)
c22aaad1
PB		 12339{
12340 unsigned char b[2];
12341 unsigned int insn;
12342 int status;
12343 /* COUNT is twice the number of instructions seen. It will be odd if we
12344 just crossed an instruction boundary. */
12345 int count;
12346 int it_count;
12347 unsigned int seen_it;
12348 bfd_vma addr;
12349
12350 ifthen_address = pc;
12351 ifthen_state = 0;
12352
12353 addr = pc;
12354 count = 1;
12355 it_count = 0;
12356 seen_it = 0;
12357 /* Scan backwards looking for IT instructions, keeping track of where
12358 instruction boundaries are. We don't know if something is actually an
12359 IT instruction until we find a definite instruction boundary. */
12360 for (;;)
12361 {
fe56b6ce 12362 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 12363 {
12364 /* A symbol must be on an instruction boundary, and will not
12365 be within an IT block. */
12366 if (seen_it && (count & 1))
12367 break;
12368
12369 return;
12370 }
12371 addr -= 2;
fe56b6ce 12372 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 12373 if (status)
12374 return;
12375
12376 if (little)
12377 insn = (b[0]) | (b[1] << 8);
12378 else
12379 insn = (b[1]) | (b[0] << 8);
12380 if (seen_it)
12381 {
12382 if ((insn & 0xf800) < 0xe800)
12383 {
12384 /* Addr + 2 is an instruction boundary. See if this matches
12385 the expected boundary based on the position of the last
12386 IT candidate. */
12387 if (count & 1)
12388 break;
12389 seen_it = 0;
12390 }
12391 }
12392 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12393 {
5bc5ae88 12394 enum map_type type = MAP_ARM;
78933a4a 12395 bool found = mapping_symbol_for_insn (addr, info, &type);
5bc5ae88
RL		 12396
12397 if (!found || (found && type == MAP_THUMB))
12398 {
12399 /* This could be an IT instruction. */
12400 seen_it = insn;
12401 it_count = count >> 1;
12402 }
c22aaad1
PB		 12403 }
12404 if ((insn & 0xf800) >= 0xe800)
12405 count++;
12406 else
12407 count = (count + 2) | 1;
12408 /* IT blocks contain at most 4 instructions. */
12409 if (count >= 8 && !seen_it)
12410 return;
12411 }
12412 /* We found an IT instruction. */
12413 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12414 if ((ifthen_state & 0xf) == 0)
12415 ifthen_state = 0;
12416}
12417
b0e28b39
DJ		 12418/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12419 mapping symbol. */
12420
12421static int
77186045
NC		 12422is_mapping_symbol (struct disassemble_info *info,
12423 int n,
b0e28b39
DJ		 12424 enum map_type *map_type)
12425{
77186045 12426 const char *name = bfd_asymbol_name (info->symtab[n]);
b0e28b39 12427
77186045
NC		 12428 if (name[0] == '$'
12429 && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
b0e28b39
DJ		 12430 && (name[2] == 0 || name[2] == '.'))
12431 {
12432 *map_type = ((name[1] == 'a') ? MAP_ARM
12433 : (name[1] == 't') ? MAP_THUMB
12434 : MAP_DATA);
78933a4a 12435 return true;
b0e28b39
DJ		 12436 }
12437
78933a4a 12438 return false;
b0e28b39
DJ		 12439}
12440
12441/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12442 Returns nonzero if *MAP_TYPE was set. */
12443
12444static int
12445get_map_sym_type (struct disassemble_info *info,
12446 int n,
12447 enum map_type *map_type)
12448{
12449 /* If the symbol is in a different section, ignore it. */
12450 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12451 return false;
b0e28b39
DJ		 12452
12453 return is_mapping_symbol (info, n, map_type);
12454}
12455
12456/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 12457 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 12458
12459static int
fe56b6ce
NC		 12460get_sym_code_type (struct disassemble_info *info,
12461 int n,
e821645d 12462 enum map_type *map_type)
2087ad84
PB		 12463{
12464 elf_symbol_type *es;
12465 unsigned int type;
77186045 12466 asymbol * sym;
b0e28b39
DJ		 12467
12468 /* If the symbol is in a different section, ignore it. */
12469 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 12470 return false;
2087ad84 12471
77186045
NC		 12472 /* PR 30230: Reject non-ELF symbols, eg synthetic ones. */
12473 sym = info->symtab[n];
12474 if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12475 return false;
12476
12477 es = (elf_symbol_type *) sym;
2087ad84
PB		 12478 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12479
12480 /* If the symbol has function type then use that. */
34e77a92 12481 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 12482 {
39d911fc
TP		 12483 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12484 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 12485 *map_type = MAP_THUMB;
12486 else
12487 *map_type = MAP_ARM;
78933a4a 12488 return true;
2087ad84
PB		 12489 }
12490
78933a4a 12491 return false;
2087ad84
PB		 12492}
12493
5bc5ae88
RL		 12494/* Search the mapping symbol state for instruction at pc. This is only
12495 applicable for elf target.
12496
12497 There is an assumption Here, info->private_data contains the correct AND
12498 up-to-date information about current scan process. The information will be
12499 used to speed this search process.
12500
12501 Return TRUE if the mapping state can be determined, and map_symbol
12502 will be updated accordingly. Otherwise, return FALSE. */
12503
78933a4a 12504static bool
5bc5ae88
RL		 12505mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12506 enum map_type *map_symbol)
12507{
796d6298
TC		 12508 bfd_vma addr, section_vma = 0;
12509 int n, last_sym = -1;
78933a4a
AM		 12510 bool found = false;
12511 bool can_use_search_opt_p = false;
796d6298 12512
76a95fac
LM		 12513 /* Sanity check. */
12514 if (info == NULL)
12515 return false;
12516
796d6298
TC		 12517 /* Default to DATA. A text section is required by the ABI to contain an
12518 INSN mapping symbol at the start. A data section has no such
12519 requirement, hence if no mapping symbol is found the section must
12520 contain only data. This however isn't very useful if the user has
12521 fully stripped the binaries. If this is the case use the section
12522 attributes to determine the default. If we have no section default to
12523 INSN as well, as we may be disassembling some raw bytes on a baremetal
12524 HEX file or similar. */
12525 enum map_type type = MAP_DATA;
12526 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12527 type = MAP_ARM;
5bc5ae88
RL		 12528 struct arm_private_data *private_data;
12529
76a95fac 12530 if (info->private_data == NULL || info->symtab == NULL
4eeb0013 12531 || info->symtab_size == 0
5bc5ae88 12532 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
78933a4a 12533 return false;
5bc5ae88
RL		 12534
12535 private_data = info->private_data;
5bc5ae88 12536
796d6298 12537 /* First, look for mapping symbols. */
4eeb0013
AM		 12538 if (pc <= private_data->last_mapping_addr)
12539 private_data->last_mapping_sym = -1;
12540
12541 /* Start scanning at the start of the function, or wherever
12542 we finished last time. */
12543 n = info->symtab_pos + 1;
12544
12545 /* If the last stop offset is different from the current one it means we
12546 are disassembling a different glob of bytes. As such the optimization
12547 would not be safe and we should start over. */
12548 can_use_search_opt_p
12549 = (private_data->last_mapping_sym >= 0
12550 && info->stop_offset == private_data->last_stop_offset);
12551
12552 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12553 n = private_data->last_mapping_sym;
12554
12555 /* Look down while we haven't passed the location being disassembled.
12556 The reason for this is that there's no defined order between a symbol
12557 and an mapping symbol that may be at the same address. We may have to
12558 look at least one position ahead. */
12559 for (; n < info->symtab_size; n++)
12560 {
12561 addr = bfd_asymbol_value (info->symtab[n]);
12562 if (addr > pc)
12563 break;
12564 if (get_map_sym_type (info, n, &type))
12565 {
12566 last_sym = n;
12567 found = true;
12568 }
12569 }
5bc5ae88 12570
4eeb0013
AM		 12571 if (!found)
12572 {
12573 n = info->symtab_pos;
12574 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12575 n = private_data->last_mapping_sym;
12576
12577 /* No mapping symbol found at this address. Look backwards
12578 for a preceeding one, but don't go pass the section start
12579 otherwise a data section with no mapping symbol can pick up
12580 a text mapping symbol of a preceeding section. The documentation
12581 says section can be NULL, in which case we will seek up all the
12582 way to the top. */
12583 if (info->section)
12584 section_vma = info->section->vma;
12585
12586 for (; n >= 0; n--)
12587 {
12588 addr = bfd_asymbol_value (info->symtab[n]);
12589 if (addr < section_vma)
12590 break;
796d6298 12591
4eeb0013
AM		 12592 if (get_map_sym_type (info, n, &type))
12593 {
12594 last_sym = n;
12595 found = true;
12596 break;
12597 }
12598 }
12599 }
796d6298
TC		 12600
12601 /* If no mapping symbol was found, try looking up without a mapping
12602 symbol. This is done by walking up from the current PC to the nearest
12603 symbol. We don't actually have to loop here since symtab_pos will
12604 contain the nearest symbol already. */
12605 if (!found)
5bc5ae88 12606 {
796d6298
TC		 12607 n = info->symtab_pos;
12608 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 12609 {
796d6298 12610 last_sym = n;
78933a4a 12611 found = true;
5bc5ae88
RL		 12612 }
12613 }
12614
796d6298
TC		 12615 private_data->last_mapping_sym = last_sym;
12616 private_data->last_type = type;
12617 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 12618
12619 *map_symbol = type;
12620 return found;
12621}
12622
0313a2b8
NC		 12623/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12624 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 12625 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 12626
12627 FIXME: This could more efficiently implemented as a constant array,
12628 although it would also be less robust. */
12629
12630static void
12631select_arm_features (unsigned long mach,
12632 arm_feature_set * features)
12633{
c0c468d5
TP		 12634 arm_feature_set arch_fset;
12635 const arm_feature_set fpu_any = FPU_ANY;
12636
1af1dd51
MW		 12637#undef ARM_SET_FEATURES
12638#define ARM_SET_FEATURES(FSET) \
12639 { \
12640 const arm_feature_set fset = FSET; \
c0c468d5 12641 arch_fset = fset; \
1af1dd51 12642 }
823d2571 12643
c0c468d5
TP		 12644 /* When several architecture versions share the same bfd_mach_arm_XXX value
12645 the most featureful is chosen. */
0313a2b8
NC		 12646 switch (mach)
12647 {
c0c468d5
TP		 12648 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
12649 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12650 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
12651 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12652 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
12653 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12654 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
12655 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12656 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12657 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 12658 case bfd_mach_arm_ep9312:
c0c468d5
TP		 12659 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
12660 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 12661 break;
c0c468d5
TP		 12662 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12663 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12664 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12665 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
12666 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12667 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12668 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12669 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12670 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12671 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12672 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12673 case bfd_mach_arm_8:
12674 {
aab2c27d
MM		 12675 /* Add bits for extensions that Armv8.6-A recognizes. */
12676 arm_feature_set armv8_6_ext_fset
0632eeea 12677 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 12678 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12679 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 12680 break;
12681 }
12682 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12683 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12684 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12685 case bfd_mach_arm_8_1M_MAIN:
12686 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12687 arm_feature_set mve_all
12688 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12689 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12690 force_thumb = 1;
12691 break;
3197e593 12692 case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
c0c468d5 12693 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12694 extensions, with the exception of MVE as that clashes with NEON. */
12695 case bfd_mach_arm_unknown:
3197e593 12696 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
2da2eaf4 12697 break;
0313a2b8
NC		 12698 default:
12699 abort ();
12700 }
1af1dd51 12701#undef ARM_SET_FEATURES
c0c468d5
TP		 12702
12703 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12704 and thus on bfd_mach_arm_XXX value. Therefore for a given
12705 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12706 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12707}
12708
12709
58efb6c0
NC		 12710/* NOTE: There are no checks in these routines that
12711 the relevant number of data bytes exist. */
baf0cc5e 12712
58efb6c0 12713static int
78933a4a 12714print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
252b5132 12715{
c19d1205 12716 unsigned char b[4];
2480b6fa 12717 unsigned long given;
78933a4a
AM		 12718 int status;
12719 int is_thumb = false;
12720 int is_data = false;
12721 int little_code;
e821645d 12722 unsigned int size = 4;
78933a4a
AM		 12723 void (*printer) (bfd_vma, struct disassemble_info *, long);
12724 bool found = false;
b0e28b39 12725 struct arm_private_data *private_data;
58efb6c0 12726
1d67fe3b
TT		 12727 /* Clear instruction information field. */
12728 info->insn_info_valid = 0;
12729 info->branch_delay_insns = 0;
12730 info->data_size = 0;
12731 info->insn_type = dis_noninsn;
12732 info->target = 0;
12733 info->target2 = 0;
12734
dd92f639
NC		 12735 if (info->disassembler_options)
12736 {
65b48a81 12737 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12738
58efb6c0 12739 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12740 info->disassembler_options = NULL;
12741 }
b34976b6 12742
0313a2b8
NC		 12743 /* PR 10288: Control which instructions will be disassembled. */
12744 if (info->private_data == NULL)
12745 {
b0e28b39 12746 static struct arm_private_data private;
0313a2b8
NC		 12747
12748 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12749 /* If the user did not use the -m command line switch then default to
12750 disassembling all types of ARM instruction.
43e65147 12751
0313a2b8
NC		 12752 The info->mach value has to be ignored as this will be based on
12753 the default archictecture for the target and/or hints in the notes
12754 section, but it will never be greater than the current largest arm
12755 machine value (iWMMXt2), which is only equivalent to the V5TE
12756 architecture. ARM architectures have advanced beyond the machine
12757 value encoding, and these newer architectures would be ignored if
12758 the machine value was used.
12759
12760 Ie the -m switch is used to restrict which instructions will be
12761 disassembled. If it is necessary to use the -m switch to tell
12762 objdump that an ARM binary is being disassembled, eg because the
12763 input is a raw binary file, but it is also desired to disassemble
12764 all ARM instructions then use "-marm". This will select the
12765 "unknown" arm architecture which is compatible with any ARM
12766 instruction. */
12767 info->mach = bfd_mach_arm_unknown;
12768
12769 /* Compute the architecture bitmask from the machine number.
12770 Note: This assumes that the machine number will not change
12771 during disassembly.... */
b0e28b39 12772 select_arm_features (info->mach, & private.features);
0313a2b8 12773
1fbaefec
PB		 12774 private.last_mapping_sym = -1;
12775 private.last_mapping_addr = 0;
796d6298 12776 private.last_stop_offset = 0;
b0e28b39
DJ		 12777
12778 info->private_data = & private;
0313a2b8 12779 }
b0e28b39
DJ		 12780
12781 private_data = info->private_data;
12782
bd2e2557
SS		 12783 /* Decide if our code is going to be little-endian, despite what the
12784 function argument might say. */
12785 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12786
b0e28b39
DJ		 12787 /* For ELF, consult the symbol table to determine what kind of code
12788 or data we have. */
8977d4b2 12789 if (info->symtab_size != 0
e821645d
DJ		 12790 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12791 {
12792 bfd_vma addr;
796d6298 12793 int n;
e821645d 12794 int last_sym = -1;
b0e28b39 12795 enum map_type type = MAP_ARM;
e821645d 12796
796d6298
TC		 12797 found = mapping_symbol_for_insn (pc, info, &type);
12798 last_sym = private_data->last_mapping_sym;
e821645d 12799
1fbaefec
PB		 12800 is_thumb = (private_data->last_type == MAP_THUMB);
12801 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12802
e821645d
DJ		 12803 /* Look a little bit ahead to see if we should print out
12804 two or four bytes of data. If there's a symbol,
12805 mapping or otherwise, after two bytes then don't
12806 print more. */
12807 if (is_data)
12808 {
12809 size = 4 - (pc & 3);
12810 for (n = last_sym + 1; n < info->symtab_size; n++)
12811 {
12812 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12813 if (addr > pc
12814 && (info->section == NULL
12815 || info->section == info->symtab[n]->section))
e821645d
DJ		 12816 {
12817 if (addr - pc < size)
12818 size = addr - pc;
12819 break;
12820 }
12821 }
12822 /* If the next symbol is after three bytes, we need to
12823 print only part of the data, so that we can use either
12824 .byte or .short. */
12825 if (size == 3)
12826 size = (pc & 1) ? 1 : 2;
12827 }
12828 }
12829
12830 if (info->symbols != NULL)
252b5132 12831 {
5876e06d
NC		 12832 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12833 {
2f0ca46a 12834 coff_symbol_type * cs;
b34976b6 12835
5876e06d
NC		 12836 cs = coffsymbol (*info->symbols);
12837 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12838 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12839 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12840 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12841 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12842 }
e821645d
DJ		 12843 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12844 && !found)
5876e06d 12845 {
2087ad84
PB		 12846 /* If no mapping symbol has been found then fall back to the type
12847 of the function symbol. */
e821645d
DJ		 12848 elf_symbol_type * es;
12849 unsigned int type;
2087ad84 12850
e821645d
DJ		 12851 es = *(elf_symbol_type **)(info->symbols);
12852 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12853
39d911fc
TP		 12854 is_thumb =
12855 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12856 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12857 }
e49d43ff
TG		 12858 else if (bfd_asymbol_flavour (*info->symbols)
12859 == bfd_target_mach_o_flavour)
12860 {
12861 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12862
12863 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12864 }
5876e06d 12865 }
b34976b6 12866
e821645d 12867 if (force_thumb)
78933a4a 12868 is_thumb = true;
e821645d 12869
b8f9ee44
CL		 12870 if (is_data)
12871 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12872 else
12873 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12874
c19d1205 12875 info->bytes_per_line = 4;
252b5132 12876
1316c8b3
NC		 12877 /* PR 10263: Disassemble data if requested to do so by the user. */
12878 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12879 {
12880 int i;
12881
1316c8b3 12882 /* Size was already set above. */
e821645d
DJ		 12883 info->bytes_per_chunk = size;
12884 printer = print_insn_data;
12885
fe56b6ce 12886 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12887 given = 0;
12888 if (little)
12889 for (i = size - 1; i >= 0; i--)
12890 given = b[i] | (given << 8);
12891 else
12892 for (i = 0; i < (int) size; i++)
12893 given = b[i] | (given << 8);
12894 }
12895 else if (!is_thumb)
252b5132 12896 {
c19d1205
ZW		 12897 /* In ARM mode endianness is a straightforward issue: the instruction
12898 is four bytes long and is either ordered 0123 or 3210. */
12899 printer = print_insn_arm;
12900 info->bytes_per_chunk = 4;
4a5329c6 12901 size = 4;
c19d1205 12902
0313a2b8 12903 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12904 if (little_code)
2480b6fa 12905 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12906 else
2480b6fa 12907 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12908 }
58efb6c0 12909 else
252b5132 12910 {
c19d1205
ZW		 12911 /* In Thumb mode we have the additional wrinkle of two
12912 instruction lengths. Fortunately, the bits that determine
12913 the length of the current instruction are always to be found
12914 in the first two bytes. */
4a5329c6 12915 printer = print_insn_thumb16;
c19d1205 12916 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12917 size = 2;
12918
fe56b6ce 12919 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12920 if (little_code)
9a2ff3f5
AM		 12921 given = (b[0]) | (b[1] << 8);
12922 else
12923 given = (b[1]) | (b[0] << 8);
12924
c19d1205 12925 if (!status)
252b5132 12926 {
c19d1205
ZW		 12927 /* These bit patterns signal a four-byte Thumb
12928 instruction. */
12929 if ((given & 0xF800) == 0xF800
12930 || (given & 0xF800) == 0xF000
12931 || (given & 0xF800) == 0xE800)
252b5132 12932 {
0313a2b8 12933 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12934 if (little_code)
c19d1205 12935 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12936 else
c19d1205
ZW		 12937 given = (b[1]) | (b[0] << 8) | (given << 16);
12938
12939 printer = print_insn_thumb32;
4a5329c6 12940 size = 4;
252b5132 12941 }
252b5132 12942 }
c22aaad1
PB		 12943
12944 if (ifthen_address != pc)
0313a2b8 12945 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12946
12947 if (ifthen_state)
12948 {
12949 if ((ifthen_state & 0xf) == 0x8)
12950 ifthen_next_state = 0;
12951 else
12952 ifthen_next_state = (ifthen_state & 0xe0)
12953 | ((ifthen_state & 0xf) << 1);
12954 }
252b5132 12955 }
b34976b6 12956
c19d1205
ZW		 12957 if (status)
12958 {
12959 info->memory_error_func (status, pc, info);
12960 return -1;
12961 }
6a56ec7e
NC		 12962 if (info->flags & INSN_HAS_RELOC)
12963 /* If the instruction has a reloc associated with it, then
12964 the offset field in the instruction will actually be the
12965 addend for the reloc. (We are using REL type relocs).
12966 In such cases, we can ignore the pc when computing
12967 addresses, since the addend is not currently pc-relative. */
12968 pc = 0;
b34976b6 12969
4a5329c6 12970 printer (pc, info, given);
c22aaad1
PB		 12971
12972 if (is_thumb)
12973 {
12974 ifthen_state = ifthen_next_state;
12975 ifthen_address += size;
12976 }
4a5329c6 12977 return size;
252b5132
RH		 12978}
12979
12980int
4a5329c6 12981print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12982{
bd2e2557
SS		 12983 /* Detect BE8-ness and record it in the disassembler info. */
12984 if (info->flavour == bfd_target_elf_flavour
12985 && info->section != NULL
12986 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12987 info->endian_code = BFD_ENDIAN_LITTLE;
12988
78933a4a 12989 return print_insn (pc, info, false);
58efb6c0 12990}
01c7f630 12991
58efb6c0 12992int
4a5329c6 12993print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12994{
78933a4a 12995 return print_insn (pc, info, true);
58efb6c0 12996}
252b5132 12997
471b9d15 12998const disasm_options_and_args_t *
65b48a81
PB		 12999disassembler_options_arm (void)
13000{
471b9d15 13001 static disasm_options_and_args_t *opts_and_args;
65b48a81 13002
471b9d15 13003 if (opts_and_args == NULL)
65b48a81 13004 {
471b9d15 13005 disasm_options_t *opts;
65b48a81 13006 unsigned int i;
471b9d15
MR		 13007
13008 opts_and_args = XNEW (disasm_options_and_args_t);
13009 opts_and_args->args = NULL;
13010
13011 opts = &opts_and_args->options;
65b48a81
PB		 13012 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
13013 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 13014 opts->arg = NULL;
65b48a81
PB		 13015 for (i = 0; i < NUM_ARM_OPTIONS; i++)
13016 {
13017 opts->name[i] = regnames[i].name;
13018 if (regnames[i].description != NULL)
13019 opts->description[i] = _(regnames[i].description);
13020 else
13021 opts->description[i] = NULL;
13022 }
13023 /* The array we return must be NULL terminated. */
13024 opts->name[i] = NULL;
13025 opts->description[i] = NULL;
13026 }
13027
471b9d15 13028 return opts_and_args;
65b48a81
PB		 13029}
13030
58efb6c0 13031void
4a5329c6 13032print_arm_disassembler_options (FILE *stream)
58efb6c0 13033{
65b48a81 13034 unsigned int i, max_len = 0;
58efb6c0
NC		 13035 fprintf (stream, _("\n\
13036The following ARM specific disassembler options are supported for use with\n\
13037the -M switch:\n"));
b34976b6 13038
65b48a81
PB		 13039 for (i = 0; i < NUM_ARM_OPTIONS; i++)
13040 {
13041 unsigned int len = strlen (regnames[i].name);
13042 if (max_len < len)
13043 max_len = len;
13044 }
58efb6c0 13045
65b48a81
PB		 13046 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
13047 fprintf (stream, " %s%*c %s\n",
13048 regnames[i].name,
13049 (int)(max_len - strlen (regnames[i].name)), ' ',
13050 _(regnames[i].description));
252b5132 13051}
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