rearnsha [Fri, 18 Oct 2019 19:04:22 +0000 (19:04 +0000)]
[arm] Improve code generation for addvsi4.
Similar to the improvements for uaddvsi4, this patch improves the code
generation for addvsi4 to handle immediates and to add alternatives
that better target thumb2. To do this we separate out the expansion
of uaddvsi4 from that of uaddvdi4 and then add an additional pattern
to handle constants. Also, while doing this I've fixed the incorrect
usage of NE instead of COMPARE in the generated RTL.
* config/arm/arm.md (addv<mode>4): Delete.
(addvsi4): New pattern. Handle immediate values that the architecture
supports.
(addvdi4): New pattern.
(addsi3_compareV): Rename to ...
(addsi3_compareV_reg): ... this. Add constraints for thumb2 variants
and use COMPARE rather than NE.
(addsi3_compareV_imm): New pattern.
* config/arm/arm.c (arm_select_cc_mode): Return CC_Vmode for
a signed-overflow check.
rearnsha [Fri, 18 Oct 2019 19:04:15 +0000 (19:04 +0000)]
[arm] Early expansion of uaddvdi4.
This code borrows strongly on the uaddvti4 expansion for aarch64 since
the principles are similar. Firstly, if the one of the low words of
the expansion is 0, we can simply copy the other low word to the
destination and use uaddvsi4 for the upper word. If that doesn't work
we have to handle three possible cases for the upper work (the lower
word is simply an add-with-carry operation as for adddi3): zero in the
upper word, some other constant and a register (each has a different
canonicalization). We use CC_ADCmode (a new CC mode variant) to
describe the cases as the introduction of the carry means we can
no-longer use the normal overflow trick of comparing the sum against
one of the operands.
* config/arm/arm-modes.def (CC_ADC): New CC mode.
* config/arm/arm.c (arm_select_cc_mode): Detect selection of
CC_ADCmode.
(maybe_get_arm_condition_code): Handle CC_ADCmode.
* config/arm/arm.md (uaddvdi4): Early expansion of unsigned addition
with overflow.
(addsi3_cin_cout_reg, addsi3_cin_cout_imm, addsi3_cin_cout_0): New
expand patterns.
(addsi3_cin_cout_reg_insn, addsi3_cin_cout_0_insn): New insn patterns
(addsi3_cin_cout_imm_insn): Likewise.
(adddi3_compareC): Delete insn.
* config/arm/predicates.md (arm_carry_operation): Handle CC_ADCmode.
rearnsha [Fri, 18 Oct 2019 19:04:06 +0000 (19:04 +0000)]
[arm] Handle immediate values in uaddvsi4
The uaddv patterns in the arm back-end do not currenty handle immediates
during expansion. This patch adds this support for uaddvsi4. It's really
a stepping-stone towards early expansion of uaddvdi4, but it complete and
a useful change in its own right.
Whilst making this change I also observed that we really had two patterns
that did exactly the same thing, but with slightly different properties;
consequently I've cleaned up all of the add-and-compare patterns to bring
some consistency.
* config/arm/arm.md (adddi3): Call gen_addsi3_compare_op1.
* (uaddv<mode>4): Delete expansion pattern.
(uaddvsi4): New pattern.
(uaddvdi4): Likewise.
(addsi3_compareC): Delete pattern, change callers to use
addsi3_compare_op1.
(addsi3_compare_op1): No-longer anonymous. Clean up constraints to
reduce the number of alternatives and re-work type attribute handling.
(addsi3_compare_op2): Clean up constraints to reduce the number of
alternatives and re-work type attribute handling.
(compare_addsi2_op0): Likewise.
(compare_addsi2_op1): Likewise.
rearnsha [Fri, 18 Oct 2019 19:03:58 +0000 (19:03 +0000)]
[arm] Cleanup dead code - old support for DImode comparisons
Now that all the major patterns for DImode have been converted to
early expansion, we can safely clean up some dead code for the old way
of handling DImode.
* config/arm/arm-modes.def (CC_NCV, CC_CZ): Delete CC modes.
* config/arm/arm.c (arm_select_cc_mode): Remove old selection code
for DImode operands.
(arm_gen_dicompare_reg): Remove unreachable expansion code.
(maybe_get_arm_condition_code): Remove support for CC_CZmode and
CC_NCVmode.
* config/arm/arm.md (arm_cmpdi_insn): Delete.
(arm_cmpdi_unsigned): Delete.
rearnsha [Fri, 18 Oct 2019 19:03:50 +0000 (19:03 +0000)]
[arm] Handle some constant comparisons using rsbs+rscs
In a small number of cases it is preferable to handle comparisons with
constants using the sequence
RSBS tmp, Xlo, constlo
RSCS tmp, Xhi, consthi
which allows us to handle a small number of LE/GT/LEU/GEU cases when
changing the code to use LT/GE/LTU/GEU would make the constant more
expensive. Sadly, we cannot do this on Thumb, since we need RSC, so we
now always use the incremented constant in that case since normally that
still works out cheaper than forcing the entire constant into a register.
Further investigation has also shown that the canonicalization of a
reverse subtract and compare is valid for signed as well as unsigned value,
so we relax the restriction on selecting CC_RSBmode to allow all types
of compare.
* config/arm/arm.c (arm_const_double_prefer_rsbs_rsc): New function.
(arm_canonicalize_comparison): For GT/LE/GTU/GEU, use the constant
unchanged only if that will be cheaper.
(arm_select_cc_mode): Recognize a swapped comparison that will
be regenerated using RSBS or RSCS. Relax restriction on selecting
CC_RSBmode.
(arm_gen_dicompare_reg): Handle LE/GT/LEU/GEU comparisons against
a constant.
(arm_gen_compare_reg): Handle compare (CONST, X) when the mode
is CC_RSBmode.
(maybe_get_arm_condition_code): CC_RSBmode now returns the same codes
as CCmode.
* config/arm/arm.md (rsb_imm_compare_scratch): New pattern.
(rscsi3_<CC_EXTEND>out_scratch): New pattern.
rearnsha [Fri, 18 Oct 2019 19:03:43 +0000 (19:03 +0000)]
[arm] early split most DImode comparison operations.
This patch does most of the work for early splitting the DImode
comparisons. We now handle EQ, NE, LT, GE, LTU and GEU during early
expansion, in addition to EQ and NE, for which the expansion has now
been reworked to use a standard conditional-compare pattern already in
the back-end.
To handle this we introduce two new condition flag modes that are used
when comparing the upper words of decomposed DImode values: one for
signed, and one for unsigned comparisons. CC_Bmode (B for Borrow) is
essentially the inverse of CC_Cmode and is used when the carry flag is
set by a subtraction of unsigned values.
* config/arm/arm-modes.def (CC_NV, CC_B): New CC modes.
* config/arm/arm.c (arm_select_cc_mode): Recognize constructs that
need these modes.
(arm_gen_dicompare_reg): New code to early expand the sub-operations
of EQ, NE, LT, GE, LTU and GEU.
* config/arm/iterators.md (CC_EXTEND): New code attribute.
* config/arm/predicates.md (arm_adcimm_operand): New predicate..
* config/arm/arm.md (cmpsi3_carryin_<CC_EXTEND>out): New pattern.
(cmpsi3_imm_carryin_<CC_EXTEND>out): Likewise.
(cmpsi3_0_carryin_<CC_EXTEND>out): Likewise.
rearnsha [Fri, 18 Oct 2019 19:03:35 +0000 (19:03 +0000)]
[arm] Improve handling of DImode comparisions against constants.
In almost all cases it is better to handle inequality handling against constants
by transforming comparisons of the form (reg <GE/LT/GEU/LTU> const) into
(reg <GT/LE/GTU/LEU> (const+1)). However, there are many cases that we could
handle but currently failed to do so because we forced the constant into a
register too early in the pattern expansion. To permit this to be done we need
to defer forcing the constant into a register until after we've had the chance
to do the transform - in some cases that may even mean that we no-longer need
to force the constant into a register at all. For example, on Arm, the case:
_Bool f8 (unsigned long long a) { return a > 0xffffffff; }
Which although not yet completely optimal, is certainly better than
previously.
* config/arm/arm.md (cbranchdi4): Accept reg_or_int_operand for
operand 2.
(cstoredi4): Similarly, but for operand 3.
* config/arm/arm.c (arm_canoncialize_comparison): Allow canonicalization
of unsigned compares with a constant on Arm. Prefer using const+1 and
adjusting the comparison over swapping the operands whenever the
original constant was not valid.
(arm_gen_dicompare_reg): If Y is not a valid operand, force it to a
register here.
(arm_validize_comparison): Do not force invalid DImode operands to
registers here.
rearnsha [Fri, 18 Oct 2019 19:03:27 +0000 (19:03 +0000)]
[arm] Early split simple DImode equality comparisons
This is the first step of early splitting all the DImode comparison
operations. We start by factoring the DImode handling out of
arm_gen_compare_reg into its own function.
Simple DImode equality comparisions (such as equality with zero, or
equality with a constant that is zero in one of the two word values
that it comprises) can be done using a single subtract followed by an
ORRS instruction. This avoids the need for conditional execution.
For example, (r0 != 5) can be written as
SUB Rt, R0, #5
ORRS Rt, Rt, R1
The ORRS is now expanded using an SImode pattern that already exists
in the MD file and this gives the register allocator more freedom to
select registers (consecutive pairs are no-longer required).
Furthermore, we can then delete the arm_cmpdi_zero pattern as it is
no-longer required. We use SUB for the value adjustment as this has a
generally more flexible range of immediates than XOR and what's more
has the opportunity to be relaxed in thumb2 to a 16-bit SUBS
instruction.
* config/arm/arm.c (arm_select_cc_mode): For DImode equality tests
return CC_Zmode if comparing against a constant where one word is
zero.
(arm_gen_compare_reg): Split DImode handling to ...
(arm_gen_dicompare_reg): ... here. Handle equality comparisons
against simple constants.
* config/arm/arm.md (arm_cmpdi_zero): Delete pattern.
rearnsha [Fri, 18 Oct 2019 19:03:19 +0000 (19:03 +0000)]
[arm] Add alternative canonicalizations for subtract-with-carry + shift
This patch adds a couple of alternative canonicalizations to allow
combine to match a subtract-with-carry operation when one of the operands
is shifted first. The most common case of this is when combining a
sign-extend of one operand with a long-long value during subtraction.
The RSC variant is only enabled for Arm, the SBC variant for any 32-bit
compilation.
* config/arm/arm.md (subsi3_carryin_shift_alt): New pattern.
(rsbsi3_carryin_shift_alt): Likewise.
rearnsha [Fri, 18 Oct 2019 19:03:11 +0000 (19:03 +0000)]
[arm] Implement negscc using SBC when appropriate.
When the carry flag is appropriately set by a comprison, negscc
patterns can expand into a simple SBC of a register with itself. This
means we can convert two conditional instructions into a single
non-conditional instruction. Furthermore, in Thumb2 we can avoid the
need for an IT instruction as well. This patch also fixes the remaining
testcase that we initially XFAILed in the first patch of this series.
gcc:
* config/arm/arm.md (negscc_borrow): New pattern.
(mov_negscc): Don't split if the insn would match negscc_borrow.
* config/arm/thumb2.md (thumb2_mov_negscc): Likewise.
(thumb2_mov_negscc_strict_it): Likewise.
The costs are all correct, but we really don't want this combination
to take place. The original costs contain an insn that is a simple
move of one pseudo register to another and it is extremely likely that
register allocation will eliminate this insn entirely. On the other
hand, the resulting sequence really does expand into a sequence that
costs 12 (ie 3 insns).
We don't want to prevent combine from eliminating such moves, as this
can expose more combine opportunities, but we shouldn't rate them as
profitable in themselves. We can do this be adjusting the costs
slightly so that the benefit of eliminating such a simple insn is
reduced.
We only do this before register allocation; after allocation we give
such insns their full cost.
* config/arm/arm.c (arm_insn_cost): New function.
(TARGET_INSN_COST): Override default definition.
rearnsha [Fri, 18 Oct 2019 19:02:50 +0000 (19:02 +0000)]
[arm] Correct cost calculations involving borrow for subtracts.
The rtx_cost calculations when a borrow operation was being performed were
not being calculated correctly. The borrow is free as part of the
subtract-with-carry instructions. This patch recognizes the various
idioms that can describe this and returns the correct costs.
* config/arm/arm.c (arm_rtx_costs_internal, case MINUS): Handle
borrow operations.
rearnsha [Fri, 18 Oct 2019 19:02:43 +0000 (19:02 +0000)]
[arm] Correctly cost addition with a carry-in
The cost routine for Arm and Thumb2 was not recognising the idioms that
describe the addition with carry, this results in the instructions
appearing more expensive than they really are, which occasionally can lead
to poor choices by combine. Recognising all the possible variants is
a little trickier than normal because the expressions can become complex
enough that this is no single canonical from.
* config/arm/arm.c (strip_carry_operation): New function.
(arm_rtx_costs_internal, case PLUS): Handle addtion with carry-in
for SImode.
rearnsha [Fri, 18 Oct 2019 19:02:35 +0000 (19:02 +0000)]
[arm] Introduce arm_carry_operation
An earlier patch introduced arm_borrow_operation, this one introduces
the carry variant, which is the same except that the logic of the
carry-setting is inverted. Having done this we can now match more
cases where the carry flag is propagated from comparisons with
different modes without having to define even more patterns. A few
small changes to the expand patterns are required to directly create
the carry representation.
The iterators LTUGEU is no-longer needed and removed, as is the code
attribute 'cnb'.
Finally, we fix a long-standing bug which was probably inert before:
in Thumb2 a shift with ADC can only be by an immediate amount;
register-specified shifts are not permitted.
* config/arm/predicates.md (arm_carry_operation): New special
predicate.
* config/arm/iterators.md (LTUGEU): Delete iterator.
(cnb): Delete code attribute.
(optab): Delete ltu and geu elements.
* config/arm/arm.md (addsi3_carryin): Renamed from
addsi3_carryin_<optab>. Remove iterator and use arm_carry_operand.
(add0si3_carryin): Similarly, but from add0si3_carryin_<optab>.
(addsi3_carryin_alt2): Similarly, but from addsi3_carryin_alt2_<optab>.
(addsi3_carryin_clobercc): Similarly.
(addsi3_carryin_shift): Similarly. Do not allow register shifts in
Thumb2 state.
rearnsha [Fri, 18 Oct 2019 19:02:28 +0000 (19:02 +0000)]
[arm] Remove redundant DImode subtract patterns
Now that we early split DImode subtracts, the patterns to emit the
original and to match zero-extend with subtraction or negation are
no-longer useful.
rearnsha [Fri, 18 Oct 2019 19:02:20 +0000 (19:02 +0000)]
[arm] Early split subdi3
This patch adds early splitting of subdi3 so that the individual
operations can be seen by the optimizers, particuarly combine. This
should allow us to do at least as good a job as previously, but with
far fewer patterns in the machine description.
This is just the initial patch to add the early splitting. The
cleanups will follow later.
A special trick is used to handle the 'reverse subtract and compare'
where a register is subtracted from a constant. The natural
comparison
(COMPARE (const) (reg))
is not canonical in this case and combine will never correctly
generate it (trying to swap the order of the operands. To handle this
we write the comparison as
(COMPARE (NOT (reg)) (~const)),
which has the same result for EQ, NE, LTU, LEU, GTU and GEU, which are
all the cases we are really interested in here.
Finally, we delete the negdi2 pattern. The generic expanders will use
our new subdi3 expander if this pattern is missing and that can handle
the negate case just fine.
* config/arm/arm-modes.def (CC_RSB): New CC mode.
* config/arm/predicates.md (arm_borrow_operation): Handle CC_RSBmode.
* config/arm/arm.c (arm_select_cc_mode): Detect when we should
return CC_RSBmode.
(maybe_get_arm_condition_code): Handle CC_RSBmode.
* config/arm/arm.md (subsi3_carryin): Make this pattern available to
expand.
(subdi3): Rewrite to early-expand the sub-operations.
(rsb_im_compare): New pattern.
(negdi2): Delete.
(negdi2_insn): Delete.
(arm_negsi2): Correct type attribute to alu_imm.
(negsi2_0compare): New insn pattern.
(negsi2_carryin): New insn pattern.
rearnsha [Fri, 18 Oct 2019 19:02:05 +0000 (19:02 +0000)]
[arm] Rewrite addsi3_carryin_shift_<optab> in canonical form
The add-with-carry operation which involves a shift doesn't match at present
because it isn't matching the canonical form generated by combine. Fixing
this is simply a matter of re-ordering the operands.
* config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands
to match canonical form.
rearnsha [Fri, 18 Oct 2019 19:01:49 +0000 (19:01 +0000)]
[arm] Perform early splitting of adddi3.
This patch causes the expansion of adddi3 to split the operation
immediately for Arm and Thumb-2. This is desirable as it frees up the
register allocator to pick what ever combination of registers suits
best and reduces the number of auxiliary patterns that we need in the
back-end. Three of the testcases that we disabled earlier are already
fixed by this patch. Finally, we add a new pattern to match the
canonicalization of add-with-carry when using an immediate of zero.
gcc:
* config/arm/arm-protos.h (arm_decompose_di_binop): New prototype.
* config/arm/arm.c (arm_decompose_di_binop): New function.
* config/arm/arm.md (adddi3): Also accept any const_int for op2.
If not generating Thumb-1 code, decompose the operation into 32-bit
pieces.
* add0si_carryin_<optab>: New pattern.
rearnsha [Fri, 18 Oct 2019 19:01:40 +0000 (19:01 +0000)]
[arm] Rip out DImode addition and subtraction splits.
The first step towards early splitting of addition and subtraction at
DImode is to rip out the old patterns that are designed to propagate
DImode through the RTL optimization passes and the do late splitting.
This patch does cause some code size regressions, but it should still
execute correctly. We will progressively add back the optimizations
we had here in later patches.
A small number of tests in the Arm-specific testsuite do fail as a
result of this patch, but that's to be expected, since the
optimizations they are looking for have just been removed. I've kept
the tests, but XFAILed them for now.
One small technical change is also done in this patch as part of the
cleanup: the uaddv<mode>4 expander is changed to use LTU as the branch
comparison. This eliminates the need for CC_Cmode to recognize
somewhat bogus equality constraints.
gcc:
* arm.md (adddi3): Only accept register operands.
(arm_adddi3): Convert to simple insn with no split. Do not accept
constants.
(adddi_sesidi_di): Delete patern.
(adddi_zesidi_di): Likewise.
(uaddv<mode>4): Use LTU as condition for branch.
(adddi3_compareV): Convert to simple insn with no split.
(addsi3_compareV_upper): Delete pattern.
(adddi3_compareC): Convert to simple insn with no split. Correct
flags setting expression.
(addsi3_compareC_upper): Delete pattern.
(addsi3_compareC): Correct flags setting expression.
(subdi3_compare1): Convert to simple insn with no split.
(subsi3_carryin_compare): Delete pattern.
(arm_subdi3): Convert to simple insn with no split.
(subdi_zesidi): Delete pattern.
(subdi_di_sesidi): Delete pattern.
(subdi_zesidi_di): Delete pattern.
(subdi_sesidi_di): Delete pattern.
(subdi_zesidi_zesidi): Delete pattern.
(negvdi3): Use s_register_operand.
(negdi2_compare): Convert to simple insn with no split.
(negdi2_insn): Likewise.
(negsi2_carryin_compare): Delete pattern.
(negdi_zero_extendsidi): Delete pattern.
(arm_cmpdi_insn): Convert to simple insn with no split.
(negdi2): Don't call gen_negdi2_neon.
* config/arm/neon.md (adddi3_neon): Delete pattern.
(subdi3_neon): Delete pattern.
(negdi2_neon): Delete pattern.
(splits for negdi2_neon): Delete splits.
avieira [Fri, 18 Oct 2019 15:00:32 +0000 (15:00 +0000)]
[Arm] Fix multilibs for Armv7-R
This patch maps multilibs using -march=armv7-r+vfpv3-d16-fp16 and
-march=armv7-r+vfpv3-d16-fp16+idiv to v7+fp. This patch also adds a new
multilib for armv7-r+fp.sp and maps -march=armv7-r+fp.sp+idiv,
-march=armv7-r+vfpv3xd-fp16 and -march=armv7-r+vfpv3xd-fp16+idiv to it.
This patch also makes it so that the generated multilib header file is
regenerated if changes have been made to either t-multilib, t-aprofile or
t-rmprofile when doing incremental builds.
gcc/ChangeLog:
2019-10-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/t-multilib: Add rule to regenerate mutlilib header file
with any change to t-multilib, t-aprofile and t-rmprofile. Also add
new multilib variants and new mappings.
gcc/testsuite/ChangeLog:
2019-10-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
nathan [Fri, 18 Oct 2019 12:46:01 +0000 (12:46 +0000)]
[C++ PATCH] anon type names
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01354.html
I noticed that we use a bitfield flag to note types with names for linkage
purposes:
typedef struct {} foo;
but, we can infer this by comparing TYPE_STUB_DECL and TYPE_DECL of the
main variant. It's only checked in two places -- the C++ parser
and the objective C++ encoder.
* cp-tree.h (struct lang_type): Remove was_anonymous.
(TYPE_WAS_UNNAMED): Implement by checking TYPE_DECL &
TYPE_STUB_DECL.
* decl.c (name_unnamed_type): Don't set TYPE_WAS_UNNAMED.
prathamesh3492 [Fri, 18 Oct 2019 05:13:26 +0000 (05:13 +0000)]
2019-10-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
Richard Sandiford <richard.sandiford@arm.com>
PR target/86753
* tree-vectorizer.h (scalar_cond_masked_key): New struct,
and define hashmap traits for it.
(loop_vec_info::scalar_cond_masked_set): New member.
(vect_record_loop_mask): Adjust prototype.
* tree-vectorizer.c (scalar_cond_masked_key::get_cond_ops_from_tree):
Implement method.
* tree-vect-loop.c (vectorizable_reduction): Pass NULL as last arg to
vect_record_loop_mask.
(vectorizable_live_operation): Likewise.
(vect_record_loop_mask): New param scalar_mask. Add entry
cond, loop_mask to scalar_cond_masked_set if scalar_mask is non NULL.
* tree-vect-stmts.c (check_load_store_masking): New param scalar_mask.
Pass it as last arg to vect_record_loop_mask.
(vectorizable_call): Pass scalar_mask as last arg to
vect_record_loop_mask.
(vectorizable_store): Likewise.
(vectorizable_load): Likewise.
(vectorizable_condition): Check if another part of vectorized code
applies loop_mask to condition or to it's inverse, and if yes,
apply loop_mask to result of vector comparison.
testsuite/
* gcc.target/aarch64/sve/cond_cnot_2.c: Remove XFAIL
from { scan-assembler-not {\tsel\t}.
* gcc.target/aarch64/sve/cond_convert_1.c: Adjust to make
only one load conditional.
* gcc.target/aarch64/sve/cond_convert_4.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.
* gcc.target/aarch64/sve/vcond_4.c: Remove XFAIL's.
* gcc.target/aarch64/sve/vcond_5.c: Likewise.
iains [Thu, 17 Oct 2019 19:46:52 +0000 (19:46 +0000)]
[Darwin, PPC] Fix PR 65342.
The current Darwin load/store lo_sum patterns have neither predicate nor
constraint. This means that most parts of the backend, which rely on
recog() to validate the rtx, can produce invalid combinations/selections.
For 32bit cases this isn't a problem since we can load/store to unaligned
addresses using D-mode insns.
Conversely, for 64bit instructions that use DS mode, this can manifest as
assemble errors (for an assembler that checks the LO14 relocations), or as
crashes caused by wrong offsets (or worse, wrong content for the two LSBs).
What we want to check for "Y" on Darwin is:
- that the alignment of the Symbols' target is sufficient for DS mode
- that the offset is suitable for DS mode.
(while looking through the Mach-O PIC unspecs).
So, the patch removes the Darwin-specific lo_sum patterns (we begin using
the movdi_internal64 patterns). We also we need to extend the handling of the
mem_operand_gpr constraint to allow looking through Mach-O PIC UNSPECs in
the lo_sum cases.
jason [Thu, 17 Oct 2019 19:09:53 +0000 (19:09 +0000)]
* cp-gimplify.c (cp_gimplify_expr): Use get_initialized_tmp_var.
The comment for get_formal_tmp_var says that it shouldn't be used for
expressions whose value might change between initialization and use, and in
this case we're creating a temporary precisely because the value might
change, so we should use get_initialized_tmp_var instead.
I also noticed that many callers of get_initialized_tmp_var pass NULL for
post_p, so it seems appropriate to make it a default argument.
rguenth [Thu, 17 Oct 2019 17:30:49 +0000 (17:30 +0000)]
2019-10-17 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.
(STMT_VINFO_VEC_COND_REDUC_CODE): Likewise.
* tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not
initialize STMT_VINFO_VEC_COND_REDUC_CODE.
* tree-vect-loop.c (vect_is_simple_reduction): Set
STMT_VINFO_REDUC_CODE.
(vectorizable_reduction): Remove dead and redundant code, use
STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE.
redi [Thu, 17 Oct 2019 15:40:00 +0000 (15:40 +0000)]
Define [range.cmp] comparisons for C++20
Define std::identity, std::ranges::equal_to, std::ranges::not_equal_to,
std::ranges::greater, std::ranges::less, std::ranges::greater_equal and
std::ranges::less_equal.
* include/Makefile.am: Add new header.
* include/Makefile.in: Regenerate.
* include/bits/range_cmp.h: New header for C++20 function objects.
* include/std/functional: Include new header.
* testsuite/20_util/function_objects/identity/1.cc: New test.
* testsuite/20_util/function_objects/range.cmp/equal_to.cc: New test.
* testsuite/20_util/function_objects/range.cmp/greater.cc: New test.
* testsuite/20_util/function_objects/range.cmp/greater_equal.cc: New
test.
* testsuite/20_util/function_objects/range.cmp/less.cc: New test.
* testsuite/20_util/function_objects/range.cmp/less_equal.cc: New test.
* testsuite/20_util/function_objects/range.cmp/not_equal_to.cc: New
test.
gjl [Thu, 17 Oct 2019 15:06:22 +0000 (15:06 +0000)]
Fix breakage introduced by r276985.
* config/avr/avr.c (avr_option_override): Remove set of
PARAM_ALLOW_STORE_DATA_RACES.
* common/config/avr/avr-common.c (avr_option_optimization_table)
[OPT_LEVELS_ALL]: Turn on -fallow-store-data-races.
hjl [Thu, 17 Oct 2019 14:34:15 +0000 (14:34 +0000)]
i386: Add clear_ratio to processor_costs
i386.h has
#define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
It is impossible to have CLEAR_RATIO > 6. This patch adds clear_ratio
to processor_costs, sets it to the minimum of 6 and move_ratio in all
cost models and defines CLEAR_RATIO with clear_ratio.
* config/i386/i386.h (processor_costs): Add clear_ratio.
(CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio.
* config/i386/x86-tune-costs.h: Set clear_ratio to the minimum
of 6 and move_ratio in all cost models.
The container requirements say that for move assignment "All existing
elements of [the target] are either move assigned or destroyed". Some of
our containers currently use __make_move_if_noexcept which makes the
move depend on whether the element type is nothrow move constructible.
This is incorrect, because the standard says we must move assign, not
move or copy depending on the move constructor.
Use make_move_iterator instead so that we move unconditionally. This
ensures existing elements won't be copy assigned.
PR libstdc++/92124
* include/bits/forward_list.h
(_M_move_assign(forward_list&&, false_type)): Do not use
__make_move_if_noexcept, instead move unconditionally.
* include/bits/stl_deque.h (_M_move_assign2(deque&&, false_type)):
Likewise.
* include/bits/stl_list.h (_M_move_assign(list&&, false_type)):
Likewise.
* include/bits/stl_vector.h (_M_move_assign(vector&&, false_type)):
Likewise.
* testsuite/23_containers/vector/92124.cc: New test.
rearnsha [Thu, 17 Oct 2019 13:55:11 +0000 (13:55 +0000)]
[arm] Add default FPU for Marvell-pj4
According to GAS, the Marvell PJ4 CPU has a VFPv3-D16 floating point
unit, but GCC's CPU configuration tables omits this meaning that
-mfpu=auto will not correctly select the FPU. This patch fixes this
by adding the +fp option to the architecture specification for this
device.
* config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.
rsandifo [Thu, 17 Oct 2019 13:23:52 +0000 (13:23 +0000)]
[AArch64][SVE2] Support for EOR3 and variants of BSL
2019-10-17 Yuliang Wang <yuliang.wang@arm.com>
gcc/
* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
(aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
(aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
(aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
New combine patterns.
* config/aarch64/iterators.md (BSL_DUP): New int iterator for the
above.
(bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.
gcc/testsuite/
* gcc.target/aarch64/sve2/eor3_1.c: New test.
* gcc.target/aarch64/sve2/nlogic_1.c: As above.
* gcc.target/aarch64/sve2/nlogic_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_1.c: As above.
* gcc.target/aarch64/sve2/bitsel_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_3.c: As above.
* gcc.target/aarch64/sve2/bitsel_4.c: As above.
nathan [Thu, 17 Oct 2019 12:04:51 +0000 (12:04 +0000)]
[C++ PATCH] builtin fn creation
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01283.html
* decl.c (builtin_function_1): Merge into ...
(cxx_builtin_function): ... here. Nadger the decl before maybe
copying it. Set the context.
(cxx_builtin_function_ext_scope): Push to top level, then call
cxx_builtin_function.
wilson [Wed, 16 Oct 2019 21:01:25 +0000 (21:01 +0000)]
RISC-V: Include more registers in SIBCALL_REGS.
This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It
also adds the missing riscv_regno_to_class change.
Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions. I see about a 0.01% code size reduction for the
C and libstdc++ libraries.
gcc/
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
regs to SIBCALL_REGS.
* config/riscv/riscv.c (riscv_regno_to_class): Change argument
passing regs to SIBCALL_REGS.
msebor [Wed, 16 Oct 2019 19:24:36 +0000 (19:24 +0000)]
PR tree-optimization/83821 - local aggregate initialization defeats strlen optimization
gcc/ChangeLog:
PR tree-optimization/83821
* tree-ssa-strlen.c (maybe_invalidate): Add argument. Consider
the length of a string when available.
(handle_builtin_memset) Add argument.
(handle_store, strlen_check_and_optimize_call): Same.
(check_and_optimize_stmt): Same. Pass it to callees.
PR tree-optimization/91996
* gcc.dg/strlenopt-80.c: New test.
* gcc.dg/strlenopt-81.c: New test.
gcc/ChangeLog:
PR tree-optimization/91996
* tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
information.
(compare_nonzero_chars): Add an overload.
(count_nonzero_bytes): Add an argument. Call overload above.
Handle non-constant lengths in some range.
(handle_store): Add an argument.
(check_and_optimize_stmt): Pass an argument to handle_store.
rearnsha [Wed, 16 Oct 2019 16:44:34 +0000 (16:44 +0000)]
[arm] fix bootstrap failure due to uninitialized warning
The Arm port is failing bootstrap because GCC is now warning about an
unitialized array.
The code is complex enough that I certainly can't be sure the compiler
is wrong, so perhaps the best fix here is just to memset the entire
array before use.
* config/arm/arm.c (neon_valid_immediate): Clear bytes before use.
law [Wed, 16 Oct 2019 15:14:17 +0000 (15:14 +0000)]
* config/mips/mips.c (mips_expand_builtin_insn): Force the
operands which correspond to the same input-output register to
have the same pseudo assigned to them.
wilco [Wed, 16 Oct 2019 14:24:41 +0000 (14:24 +0000)]
[AArch64] Fix symbol offset limit
In aarch64_classify_symbol symbols are allowed large offsets on relocations.
This means the offset can use all of the +/-4GB offset, leaving no offset
available for the symbol itself. This results in relocation overflow and
link-time errors for simple expressions like &global_array + 0xffffff00.
To avoid this, unless the offset_within_block_p is true, limit the offset
to +/-1MB so that the symbol needs to be within a 3.9GB offset from its
references. For the tiny code model use a 64KB offset, allowing most of
the 1MB range for code/data between the symbol and its references.
gcc/
* config/aarch64/aarch64.c (aarch64_classify_symbol):
Apply reasonable limit to symbol offsets.
rguenth [Wed, 16 Oct 2019 14:21:06 +0000 (14:21 +0000)]
2019-10-16 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (vect_valid_reduction_input_p): Remove.
(vect_is_simple_reduction): Delay checking to
vectorizable_reduction and relax the checking.
(vectorizable_reduction): Check we have a simple use. Check
for bogus condition reductions.
* tree-vect-stmts.c (vect_transform_stmt): Make sure we
are looking at the last stmt in a pattern sequence when
filling in backedge PHI values.
* gcc.dg/vect/vect-cond-reduc-3.c: New testcase.
* gcc.dg/vect/vect-cond-reduc-4.c: Likewise.
guojiufu [Wed, 16 Oct 2019 13:35:41 +0000 (13:35 +0000)]
In PR70010, a function is marked with target(no-vsx) to disable VSX code
generation. To avoid VSX code generation, this function should not be
inlined into VSX function. To fix the bug, in the current logic when
checking whether the caller's ISA flags supports the callee's ISA flags, we
just need to add a test that enforces that the caller's ISA flags match
exactly the callee's flags, for those flags that were explicitly set in the
callee. If caller without target attribute then using options from command
line.
gcc/
2019-10-16 Peter Bergner <bergner@linux.ibm.com>
Jiufu Guo <guojiufu@linux.ibm.com>
PR target/70010
* config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if
the callee explicitly disables some isa_flags the caller is using.
gcc.testsuite/
2019-10-16 Peter Bergner <bergner@linux.ibm.com>
Jiufu Guo <guojiufu@linux.ibm.com>
PR target/70010
* gcc.target/powerpc/pr70010.c: New test.
* gcc.target/powerpc/pr70010-1.c: New test.
* gcc.target/powerpc/pr70010-2.c: New test.
* gcc.target/powerpc/pr70010-3.c: New test.
* gcc.target/powerpc/pr70010-4.c: New test.
rsandifo [Wed, 16 Oct 2019 10:53:40 +0000 (10:53 +0000)]
[AArch64] Add partial SVE vector modes
This patch adds extra vector modes that represent a half, quarter or
eighth of what an SVE vector can hold. This is useful for describing
the memory vector involved in an extending load or truncating store.
It might also be useful in future for representing "unpacked" SVE
registers, i.e. registers that contain values in the low bits of a
wider containing element.
The new modes could have the same width as an Advanced SIMD mode for
certain -msve-vector-bits=N options, so we need to ensure that they
come later in the mode list and that Advanced SIMD modes always "win".
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* genmodes.c (mode_data::order): New field.
(blank_mode): Update accordingly.
(VECTOR_MODES_WITH_PREFIX): Add an order parameter.
(make_vector_modes): Likewise.
(VECTOR_MODES): Update use accordingly.
(cmp_modes): Sort by the new order field ahead of sorting by size.
* config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI)
(VNx4QI, VNx4HI, VNx8QI): New partial vector modes.
* config/aarch64/aarch64.c (VEC_PARTIAL): New flag value.
(aarch64_classify_vector_mode): Handle the new partial modes.
(aarch64_vl_bytes): New function.
(aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR
when counting the number of registers in an SVE mode.
(aarch64_class_max_nregs): Likewise.
(aarch64_hard_regno_mode_ok): Don't allow partial vectors
in registers yet.
(aarch64_classify_address): Treat partial vectors analogously
to full vectors.
(aarch64_print_address_internal): Consolidate the printing of
MUL VL addresses, using aarch64_vl_bytes as the number of
bytes represented by "VL".
(aarch64_vector_mode_supported_p): Reject partial vector modes.
rsandifo [Wed, 16 Oct 2019 10:50:53 +0000 (10:50 +0000)]
[AArch64] Improve poly_int handling in aarch64_layout_frame
I'd used known_lt when converting these conditions to poly_int,
but on reflection that was a bad choice. The code isn't just
doing a range check; it specifically needs constants that will
fit in a certain encoding.
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Use is_constant
rather than known_lt when choosing frame layouts.
rsandifo [Wed, 16 Oct 2019 10:48:00 +0000 (10:48 +0000)]
[AArch64] Add an assert to aarch64_layout_frame
This patch adds an assert that all the individual *_adjust allocations
add up to the full frame size. With that safety net, it seemed slightly
clearer to use crtl->outgoing_args_size as the final adjustment where
appropriate, to match what's used in the comments.
This is a bit overkill on its own, but I need to add more cases for SVE.
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Assert
that all the adjustments add up to the full frame size.
Use crtl->outgoing_args_size directly as the final adjustment
where appropriate.
rsandifo [Wed, 16 Oct 2019 10:44:31 +0000 (10:44 +0000)]
[AArch64] Use frame reference in aarch64_layout_frame
Using the full path "cfun->machine->frame" in aarch64_layout_frame
led to awkward formatting in some follow-on patches, so it seemed
worth using a local reference instead.
2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Use a local
"frame" reference instead of always referring directly to
"cfun->machine->frame".
redi [Wed, 16 Oct 2019 10:26:05 +0000 (10:26 +0000)]
Only use GCC-specific __is_same_as built-in conditionally
Clang doesn't support __is_same_as but provides __is_same instead.
Restore the original implementation (pre r276891) when neither of those
built-ins is available.
* include/bits/c++config (_GLIBCXX_BUILTIN_IS_SAME_AS): Define to
one of __is_same_as or __is_same when available.
* include/std/concepts (__detail::__same_as): Use std::is_same_v.
* include/std/type_traits (is_same) [_GLIBCXX_BUILTIN_IS_SAME_AS]:
Use new macro instead of __is_same_as.
(is_same) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Restore partial
specialization.
(is_same_v) [_GLIBCXX_BUILTIN_IS_SAME_AS]: Use new macro.
(is_same_v) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Use std::is_same.
rsandifo [Wed, 16 Oct 2019 09:50:44 +0000 (09:50 +0000)]
Deal with incoming POLY_INT_CST ranges (PR92033)
This patch makes value_range_base::set convert POLY_INT_CST bounds
into the worst-case INTEGER_CST bounds. The main case in which this
gives useful ranges is a lower bound of A + B * X becoming A when B >= 0.
E.g.:
danglin [Tue, 15 Oct 2019 22:17:14 +0000 (22:17 +0000)]
* config/pa/fptr.c (_dl_read_access_allowed): Change argument to
unsigned int. Adjust callers.
(__canonicalize_funcptr_for_compare): Change plabel type to volatile
unsigned int *. Load relocation offset before function pointer.
Add barrier to ensure ordering.
iains [Tue, 15 Oct 2019 20:15:38 +0000 (20:15 +0000)]
[Darwin] Update darwin_binds_local_p.
The use of default_binds_local_p had got out of sync with the varasm
changes, this restores the call to be direct. In practice, we add some
further tests to determine local binding - but this callback is used for
the initial assessments made by default_encode_section_info().
nathan [Tue, 15 Oct 2019 12:27:21 +0000 (12:27 +0000)]
[C++ PATCH] clone_function_decl breakup
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01083.html
This patch, from the modules branch, breaks out function cloning from the
method vector updating. We have a new function, build_clones,
which does the building, returning a count of the number of clones
(2 or 3). clone_function_decl separately adds them to the method
vector, if they should be added. I suppose this could have used
FOR_EVERY_CLONE, but I went with the counting scheme.
* class.c (build_clones): Break out of clone_function_decl. Just
build the clones.
(clone_function_decl): Call build_clones, then maybe add them to
the method vector.
jozefl [Tue, 15 Oct 2019 12:24:53 +0000 (12:24 +0000)]
2019-10-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/msp430/msp430.md (zero_extendqipsi2): New.
(zero_extendqisi2): Optimize case where src register and base dst
register are the same.
(zero_extendhipsi2): Don't use 430X insn for rYs->r case.
(zero_extendpsisi2): Optimize r->m case.
Add unnamed insn patterns to catch insns combine searches for when
optimizing pointer manipulation.
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