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KVM: x86: introduce num_emulated_msrs
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 225 if (slot >= shared_msrs_global.nr)
226 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 227 shared_msrs_global.msrs[slot] = msr;
228 /* we need ensured the shared_msr_global have been updated */
229 smp_wmb();
18863bdd
AK		 230}
231EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
232
233static void kvm_shared_msr_cpu_online(void)
234{
235 unsigned i;
18863bdd
AK		 236
237 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 238 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 239}
240
8b3c3104 241int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 242{
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 245 int err;
18863bdd 246
2bf78fa7 247 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 248 return 0;
2bf78fa7 249 smsr->values[slot].curr = value;
8b3c3104
AH		 250 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
251 if (err)
252 return 1;
253
18863bdd
AK		 254 if (!smsr->registered) {
255 smsr->urn.on_user_return = kvm_on_user_return;
256 user_return_notifier_register(&smsr->urn);
257 smsr->registered = true;
258 }
8b3c3104 259 return 0;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
262
13a34e06 263static void drop_user_return_notifiers(void)
3548bab5 264{
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 267
268 if (smsr->registered)
269 kvm_on_user_return(&smsr->urn);
270}
271
6866b83e
CO		 272u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
273{
8a5a87d9 274 return vcpu->arch.apic_base;
6866b83e
CO		 275}
276EXPORT_SYMBOL_GPL(kvm_get_apic_base);
277
58cb628d
JK		 278int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
279{
280 u64 old_state = vcpu->arch.apic_base &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 new_state = msr_info->data &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
285 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
286
287 if (!msr_info->host_initiated &&
288 ((msr_info->data & reserved_bits) != 0 ||
289 new_state == X2APIC_ENABLE ||
290 (new_state == MSR_IA32_APICBASE_ENABLE &&
291 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
292 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
293 old_state == 0)))
294 return 1;
295
296 kvm_lapic_set_base(vcpu, msr_info->data);
297 return 0;
6866b83e
CO		 298}
299EXPORT_SYMBOL_GPL(kvm_set_apic_base);
300
2605fc21 301asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 302{
303 /* Fault while not rebooting. We want the trace. */
304 BUG();
305}
306EXPORT_SYMBOL_GPL(kvm_spurious_fault);
307
3fd28fce
ED		 308#define EXCPT_BENIGN 0
309#define EXCPT_CONTRIBUTORY 1
310#define EXCPT_PF 2
311
312static int exception_class(int vector)
313{
314 switch (vector) {
315 case PF_VECTOR:
316 return EXCPT_PF;
317 case DE_VECTOR:
318 case TS_VECTOR:
319 case NP_VECTOR:
320 case SS_VECTOR:
321 case GP_VECTOR:
322 return EXCPT_CONTRIBUTORY;
323 default:
324 break;
325 }
326 return EXCPT_BENIGN;
327}
328
d6e8c854
NA		 329#define EXCPT_FAULT 0
330#define EXCPT_TRAP 1
331#define EXCPT_ABORT 2
332#define EXCPT_INTERRUPT 3
333
334static int exception_type(int vector)
335{
336 unsigned int mask;
337
338 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
339 return EXCPT_INTERRUPT;
340
341 mask = 1 << vector;
342
343 /* #DB is trap, as instruction watchpoints are handled elsewhere */
344 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
345 return EXCPT_TRAP;
346
347 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
348 return EXCPT_ABORT;
349
350 /* Reserved exceptions will result in fault */
351 return EXCPT_FAULT;
352}
353
3fd28fce 354static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 355 unsigned nr, bool has_error, u32 error_code,
356 bool reinject)
3fd28fce
ED		 357{
358 u32 prev_nr;
359 int class1, class2;
360
3842d135
AK		 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
362
3fd28fce
ED		 363 if (!vcpu->arch.exception.pending) {
364 queue:
3ffb2468
NA		 365 if (has_error && !is_protmode(vcpu))
366 has_error = false;
3fd28fce
ED		 367 vcpu->arch.exception.pending = true;
368 vcpu->arch.exception.has_error_code = has_error;
369 vcpu->arch.exception.nr = nr;
370 vcpu->arch.exception.error_code = error_code;
3f0fd292 371 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 372 return;
373 }
374
375 /* to check exception */
376 prev_nr = vcpu->arch.exception.nr;
377 if (prev_nr == DF_VECTOR) {
378 /* triple fault -> shutdown */
a8eeb04a 379 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 380 return;
381 }
382 class1 = exception_class(prev_nr);
383 class2 = exception_class(nr);
384 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
385 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
386 /* generate double fault per SDM Table 5-5 */
387 vcpu->arch.exception.pending = true;
388 vcpu->arch.exception.has_error_code = true;
389 vcpu->arch.exception.nr = DF_VECTOR;
390 vcpu->arch.exception.error_code = 0;
391 } else
392 /* replace previous exception with a new one in a hope
393 that instruction re-execution will regenerate lost
394 exception */
395 goto queue;
396}
397
298101da
AK		 398void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
399{
ce7ddec4 400 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 401}
402EXPORT_SYMBOL_GPL(kvm_queue_exception);
403
ce7ddec4
JR		 404void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
405{
406 kvm_multiple_exception(vcpu, nr, false, 0, true);
407}
408EXPORT_SYMBOL_GPL(kvm_requeue_exception);
409
db8fcefa 410void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 411{
db8fcefa
AP		 412 if (err)
413 kvm_inject_gp(vcpu, 0);
414 else
415 kvm_x86_ops->skip_emulated_instruction(vcpu);
416}
417EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 418
6389ee94 419void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 420{
421 ++vcpu->stat.pf_guest;
6389ee94
AK		 422 vcpu->arch.cr2 = fault->address;
423 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 424}
27d6c865 425EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 426
ef54bcfe 427static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 428{
6389ee94
AK		 429 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
430 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 431 else
6389ee94 432 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 433
434 return fault->nested_page_fault;
d4f8cf66
JR		 435}
436
3419ffc8
SY		 437void kvm_inject_nmi(struct kvm_vcpu *vcpu)
438{
7460fb4a
AK		 439 atomic_inc(&vcpu->arch.nmi_queued);
440 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 441}
442EXPORT_SYMBOL_GPL(kvm_inject_nmi);
443
298101da
AK		 444void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
445{
ce7ddec4 446 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 447}
448EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
449
ce7ddec4
JR		 450void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
451{
452 kvm_multiple_exception(vcpu, nr, true, error_code, true);
453}
454EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
455
0a79b009
AK		 456/*
457 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
458 * a #GP and return false.
459 */
460bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 461{
0a79b009
AK		 462 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
463 return true;
464 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
465 return false;
298101da 466}
0a79b009 467EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 468
16f8a6f9
NA		 469bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
470{
471 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
472 return true;
473
474 kvm_queue_exception(vcpu, UD_VECTOR);
475 return false;
476}
477EXPORT_SYMBOL_GPL(kvm_require_dr);
478
ec92fe44
JR		 479/*
480 * This function will be used to read from the physical memory of the currently
481 * running guest. The difference to kvm_read_guest_page is that this function
482 * can read from guest physical or from the guest's guest physical memory.
483 */
484int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
485 gfn_t ngfn, void *data, int offset, int len,
486 u32 access)
487{
54987b7a 488 struct x86_exception exception;
ec92fe44
JR		 489 gfn_t real_gfn;
490 gpa_t ngpa;
491
492 ngpa = gfn_to_gpa(ngfn);
54987b7a 493 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 494 if (real_gfn == UNMAPPED_GVA)
495 return -EFAULT;
496
497 real_gfn = gpa_to_gfn(real_gfn);
498
499 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
500}
501EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
502
69b0049a 503static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 504 void *data, int offset, int len, u32 access)
505{
506 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
507 data, offset, len, access);
508}
509
a03490ed
CO		 510/*
511 * Load the pae pdptrs. Return true is they are all valid.
512 */
ff03a073 513int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 514{
515 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
516 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
517 int i;
518 int ret;
ff03a073 519 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 520
ff03a073
JR		 521 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
522 offset * sizeof(u64), sizeof(pdpte),
523 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 524 if (ret < 0) {
525 ret = 0;
526 goto out;
527 }
528 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 529 if (is_present_gpte(pdpte[i]) &&
20c466b5 530 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 624 return 0;
625}
2d3ad1f4 626EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 627
2d3ad1f4 628void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 629{
49a9b07e 630 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 631}
2d3ad1f4 632EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 633
42bdf991
MT		 634static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
635{
636 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
637 !vcpu->guest_xcr0_loaded) {
638 /* kvm_set_xcr() also depends on this */
639 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
640 vcpu->guest_xcr0_loaded = 1;
641 }
642}
643
644static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
645{
646 if (vcpu->guest_xcr0_loaded) {
647 if (vcpu->arch.xcr0 != host_xcr0)
648 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
649 vcpu->guest_xcr0_loaded = 0;
650 }
651}
652
69b0049a 653static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 654{
56c103ec
LJ		 655 u64 xcr0 = xcr;
656 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 657 u64 valid_bits;
2acf923e
DC		 658
659 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
660 if (index != XCR_XFEATURE_ENABLED_MASK)
661 return 1;
2acf923e
DC		 662 if (!(xcr0 & XSTATE_FP))
663 return 1;
664 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
665 return 1;
46c34cb0
PB		 666
667 /*
668 * Do not allow the guest to set bits that we do not support
669 * saving. However, xcr0 bit 0 is always set, even if the
670 * emulated CPU does not support XSAVE (see fx_init).
671 */
672 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
673 if (xcr0 & ~valid_bits)
2acf923e 674 return 1;
46c34cb0 675
390bd528
LJ		 676 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
677 return 1;
678
612263b3
CP		 679 if (xcr0 & XSTATE_AVX512) {
680 if (!(xcr0 & XSTATE_YMM))
681 return 1;
682 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
683 return 1;
684 }
42bdf991 685 kvm_put_guest_xcr0(vcpu);
2acf923e 686 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 687
688 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
689 kvm_update_cpuid(vcpu);
2acf923e
DC		 690 return 0;
691}
692
693int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
694{
764bcbc5
Z		 695 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
696 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 697 kvm_inject_gp(vcpu, 0);
698 return 1;
699 }
700 return 0;
701}
702EXPORT_SYMBOL_GPL(kvm_set_xcr);
703
a83b29c6 704int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 705{
fc78f519 706 unsigned long old_cr4 = kvm_read_cr4(vcpu);
edc90b7d
XG		 707 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
708 X86_CR4_SMEP | X86_CR4_SMAP;
709
0f12244f
GN		 710 if (cr4 & CR4_RESERVED_BITS)
711 return 1;
a03490ed 712
2acf923e
DC		 713 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
714 return 1;
715
c68b734f
YW		 716 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
717 return 1;
718
97ec8c06
FW		 719 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
720 return 1;
721
afcbf13f 722 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 723 return 1;
724
a03490ed 725 if (is_long_mode(vcpu)) {
0f12244f
GN		 726 if (!(cr4 & X86_CR4_PAE))
727 return 1;
a2edf57f
AK		 728 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
729 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 730 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
731 kvm_read_cr3(vcpu)))
0f12244f
GN		 732 return 1;
733
ad756a16
MJ		 734 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
735 if (!guest_cpuid_has_pcid(vcpu))
736 return 1;
737
738 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
739 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
740 return 1;
741 }
742
5e1746d6 743 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 744 return 1;
a03490ed 745
ad756a16
MJ		 746 if (((cr4 ^ old_cr4) & pdptr_bits) ||
747 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 748 kvm_mmu_reset_context(vcpu);
0f12244f 749
2acf923e 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 751 kvm_update_cpuid(vcpu);
2acf923e 752
0f12244f
GN		 753 return 0;
754}
2d3ad1f4 755EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 756
2390218b 757int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 758{
ac146235 759#ifdef CONFIG_X86_64
9d88fca7 760 cr3 &= ~CR3_PCID_INVD;
ac146235 761#endif
9d88fca7 762
9f8fe504 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 764 kvm_mmu_sync_roots(vcpu);
77c3913b 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 766 return 0;
d835dfec
AK		 767 }
768
a03490ed 769 if (is_long_mode(vcpu)) {
d9f89b88
JK		 770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 774 return 1;
a03490ed 775
0f12244f 776 vcpu->arch.cr3 = cr3;
aff48baa 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 778 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 782
eea1cff9 783int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 784{
0f12244f
GN		 785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
a03490ed
CO		 787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
ad312c7c 790 vcpu->arch.cr8 = cr8;
0f12244f
GN		 791 return 0;
792}
2d3ad1f4 793EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 794
2d3ad1f4 795unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 796{
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
ad312c7c 800 return vcpu->arch.cr8;
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 803
ae561ede
NA		 804static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805{
806 int i;
807
808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809 for (i = 0; i < KVM_NR_DB_REGS; i++)
810 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 }
813}
814
73aaf249
JK		 815static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816{
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819}
820
c8639010
JK		 821static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822{
823 unsigned long dr7;
824
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 dr7 = vcpu->arch.guest_debug_dr7;
827 else
828 dr7 = vcpu->arch.dr7;
829 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831 if (dr7 & DR7_BP_EN_MASK)
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 833}
834
6f43ed01
NA		 835static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836{
837 u64 fixed = DR6_FIXED_1;
838
839 if (!guest_cpuid_has_rtm(vcpu))
840 fixed |= DR6_RTM;
841 return fixed;
842}
843
338dbc97 844static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 vcpu->arch.db[dr] = val;
849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850 vcpu->arch.eff_db[dr] = val;
851 break;
852 case 4:
020df079
GN		 853 /* fall through */
854 case 6:
338dbc97
GN		 855 if (val & 0xffffffff00000000ULL)
856 return -1; /* #GP */
6f43ed01 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 858 kvm_update_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
020df079
GN		 861 /* fall through */
862 default: /* 7 */
338dbc97
GN		 863 if (val & 0xffffffff00000000ULL)
864 return -1; /* #GP */
020df079 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 866 kvm_update_dr7(vcpu);
020df079
GN		 867 break;
868 }
869
870 return 0;
871}
338dbc97
GN		 872
873int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874{
16f8a6f9 875 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 876 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 877 return 1;
878 }
879 return 0;
338dbc97 880}
020df079
GN		 881EXPORT_SYMBOL_GPL(kvm_set_dr);
882
16f8a6f9 883int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 884{
885 switch (dr) {
886 case 0 ... 3:
887 *val = vcpu->arch.db[dr];
888 break;
889 case 4:
020df079
GN		 890 /* fall through */
891 case 6:
73aaf249
JK		 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893 *val = vcpu->arch.dr6;
894 else
895 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 896 break;
897 case 5:
020df079
GN		 898 /* fall through */
899 default: /* 7 */
900 *val = vcpu->arch.dr7;
901 break;
902 }
338dbc97
GN		 903 return 0;
904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_get_dr);
906
022cd0e8
AK		 907bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908{
909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 u64 data;
911 int err;
912
913 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914 if (err)
915 return err;
916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918 return err;
919}
920EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
043405e1
CO		 922/*
923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925 *
926 * This list is modified at module load time to reflect the
e3267cbb 927 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 928 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
929 * may depend on host virtualization features rather than host cpu features.
043405e1 930 */
e3267cbb 931
043405e1
CO		 932static u32 msrs_to_save[] = {
933 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 934 MSR_STAR,
043405e1
CO		 935#ifdef CONFIG_X86_64
936 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
937#endif
b3897a49 938 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 939 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 940};
941
942static unsigned num_msrs_to_save;
943
62ef68bb
PB		 944static u32 emulated_msrs[] = {
945 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
946 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
947 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
948 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
949 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
950 MSR_KVM_PV_EOI_EN,
951
ba904635 952 MSR_IA32_TSC_ADJUST,
a3e06bbe 953 MSR_IA32_TSCDEADLINE,
043405e1 954 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 955 MSR_IA32_MCG_STATUS,
956 MSR_IA32_MCG_CTL,
043405e1
CO		 957};
958
62ef68bb
PB		 959static unsigned num_emulated_msrs;
960
384bb783 961bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 962{
b69e8cae 963 if (efer & efer_reserved_bits)
384bb783 964 return false;
15c4a640 965
1b2fd70c
AG		 966 if (efer & EFER_FFXSR) {
967 struct kvm_cpuid_entry2 *feat;
968
969 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 970 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 971 return false;
1b2fd70c
AG		 972 }
973
d8017474
AG		 974 if (efer & EFER_SVME) {
975 struct kvm_cpuid_entry2 *feat;
976
977 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 978 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 979 return false;
d8017474
AG		 980 }
981
384bb783
JK		 982 return true;
983}
984EXPORT_SYMBOL_GPL(kvm_valid_efer);
985
986static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
987{
988 u64 old_efer = vcpu->arch.efer;
989
990 if (!kvm_valid_efer(vcpu, efer))
991 return 1;
992
993 if (is_paging(vcpu)
994 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
995 return 1;
996
15c4a640 997 efer &= ~EFER_LMA;
f6801dff 998 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 999
a3d204e2
SY		 1000 kvm_x86_ops->set_efer(vcpu, efer);
1001
aad82703
SY		 1002 /* Update reserved bits */
1003 if ((efer ^ old_efer) & EFER_NX)
1004 kvm_mmu_reset_context(vcpu);
1005
b69e8cae 1006 return 0;
15c4a640
CO		 1007}
1008
f2b4b7dd
JR		 1009void kvm_enable_efer_bits(u64 mask)
1010{
1011 efer_reserved_bits &= ~mask;
1012}
1013EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1014
15c4a640
CO		 1015/*
1016 * Writes msr value into into the appropriate "register".
1017 * Returns 0 on success, non-0 otherwise.
1018 * Assumes vcpu_load() was already called.
1019 */
8fe8ab46 1020int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1021{
854e8bb1
NA		 1022 switch (msr->index) {
1023 case MSR_FS_BASE:
1024 case MSR_GS_BASE:
1025 case MSR_KERNEL_GS_BASE:
1026 case MSR_CSTAR:
1027 case MSR_LSTAR:
1028 if (is_noncanonical_address(msr->data))
1029 return 1;
1030 break;
1031 case MSR_IA32_SYSENTER_EIP:
1032 case MSR_IA32_SYSENTER_ESP:
1033 /*
1034 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1035 * non-canonical address is written on Intel but not on
1036 * AMD (which ignores the top 32-bits, because it does
1037 * not implement 64-bit SYSENTER).
1038 *
1039 * 64-bit code should hence be able to write a non-canonical
1040 * value on AMD. Making the address canonical ensures that
1041 * vmentry does not fail on Intel after writing a non-canonical
1042 * value, and that something deterministic happens if the guest
1043 * invokes 64-bit SYSENTER.
1044 */
1045 msr->data = get_canonical(msr->data);
1046 }
8fe8ab46 1047 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1048}
854e8bb1 1049EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1050
313a3dc7
CO		 1051/*
1052 * Adapt set_msr() to msr_io()'s calling convention
1053 */
1054static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1055{
8fe8ab46
WA		 1056 struct msr_data msr;
1057
1058 msr.data = *data;
1059 msr.index = index;
1060 msr.host_initiated = true;
1061 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1062}
1063
16e8d74d
MT		 1064#ifdef CONFIG_X86_64
1065struct pvclock_gtod_data {
1066 seqcount_t seq;
1067
1068 struct { /* extract of a clocksource struct */
1069 int vclock_mode;
1070 cycle_t cycle_last;
1071 cycle_t mask;
1072 u32 mult;
1073 u32 shift;
1074 } clock;
1075
cbcf2dd3
TG		 1076 u64 boot_ns;
1077 u64 nsec_base;
16e8d74d
MT		 1078};
1079
1080static struct pvclock_gtod_data pvclock_gtod_data;
1081
1082static void update_pvclock_gtod(struct timekeeper *tk)
1083{
1084 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1085 u64 boot_ns;
1086
876e7881 1087 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1088
1089 write_seqcount_begin(&vdata->seq);
1090
1091 /* copy pvclock gtod data */
876e7881
PZ		 1092 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1093 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1094 vdata->clock.mask = tk->tkr_mono.mask;
1095 vdata->clock.mult = tk->tkr_mono.mult;
1096 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1097
cbcf2dd3 1098 vdata->boot_ns = boot_ns;
876e7881 1099 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1100
1101 write_seqcount_end(&vdata->seq);
1102}
1103#endif
1104
bab5bb39
NK		 1105void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1106{
1107 /*
1108 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1109 * vcpu_enter_guest. This function is only called from
1110 * the physical CPU that is running vcpu.
1111 */
1112 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1113}
16e8d74d 1114
18068523
GOC		 1115static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1116{
9ed3c444
AK		 1117 int version;
1118 int r;
50d0a0f9 1119 struct pvclock_wall_clock wc;
923de3cf 1120 struct timespec boot;
18068523
GOC		 1121
1122 if (!wall_clock)
1123 return;
1124
9ed3c444
AK		 1125 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1126 if (r)
1127 return;
1128
1129 if (version & 1)
1130 ++version; /* first time write, random junk */
1131
1132 ++version;
18068523 1133
18068523
GOC		 1134 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1135
50d0a0f9
GH		 1136 /*
1137 * The guest calculates current wall clock time by adding
34c238a1 1138 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1139 * wall clock specified here. guest system time equals host
1140 * system time for us, thus we must fill in host boot time here.
1141 */
923de3cf 1142 getboottime(&boot);
50d0a0f9 1143
4b648665
BR		 1144 if (kvm->arch.kvmclock_offset) {
1145 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1146 boot = timespec_sub(boot, ts);
1147 }
50d0a0f9
GH		 1148 wc.sec = boot.tv_sec;
1149 wc.nsec = boot.tv_nsec;
1150 wc.version = version;
18068523
GOC		 1151
1152 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1153
1154 version++;
1155 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1156}
1157
50d0a0f9
GH		 1158static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1159{
1160 uint32_t quotient, remainder;
1161
1162 /* Don't try to replace with do_div(), this one calculates
1163 * "(dividend << 32) / divisor" */
1164 __asm__ ( "divl %4"
1165 : "=a" (quotient), "=d" (remainder)
1166 : "0" (0), "1" (dividend), "r" (divisor) );
1167 return quotient;
1168}
1169
5f4e3f88
ZA		 1170static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1171 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1172{
5f4e3f88 1173 uint64_t scaled64;
50d0a0f9
GH		 1174 int32_t shift = 0;
1175 uint64_t tps64;
1176 uint32_t tps32;
1177
5f4e3f88
ZA		 1178 tps64 = base_khz * 1000LL;
1179 scaled64 = scaled_khz * 1000LL;
50933623 1180 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1181 tps64 >>= 1;
1182 shift--;
1183 }
1184
1185 tps32 = (uint32_t)tps64;
50933623
JK		 1186 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1187 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1188 scaled64 >>= 1;
1189 else
1190 tps32 <<= 1;
50d0a0f9
GH		 1191 shift++;
1192 }
1193
5f4e3f88
ZA		 1194 *pshift = shift;
1195 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1196
5f4e3f88
ZA		 1197 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1198 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1199}
1200
759379dd
ZA		 1201static inline u64 get_kernel_ns(void)
1202{
bb0b5812 1203 return ktime_get_boot_ns();
50d0a0f9
GH		 1204}
1205
d828199e 1206#ifdef CONFIG_X86_64
16e8d74d 1207static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1208#endif
16e8d74d 1209
c8076604 1210static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1211static unsigned long max_tsc_khz;
c8076604 1212
cc578287 1213static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1214{
cc578287
ZA		 1215 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1216 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1217}
1218
cc578287 1219static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1220{
cc578287
ZA		 1221 u64 v = (u64)khz * (1000000 + ppm);
1222 do_div(v, 1000000);
1223 return v;
1e993611
JR		 1224}
1225
cc578287 1226static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1227{
cc578287
ZA		 1228 u32 thresh_lo, thresh_hi;
1229 int use_scaling = 0;
217fc9cf 1230
03ba32ca
MT		 1231 /* tsc_khz can be zero if TSC calibration fails */
1232 if (this_tsc_khz == 0)
1233 return;
1234
c285545f
ZA		 1235 /* Compute a scale to convert nanoseconds in TSC cycles */
1236 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1237 &vcpu->arch.virtual_tsc_shift,
1238 &vcpu->arch.virtual_tsc_mult);
1239 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1240
1241 /*
1242 * Compute the variation in TSC rate which is acceptable
1243 * within the range of tolerance and decide if the
1244 * rate being applied is within that bounds of the hardware
1245 * rate. If so, no scaling or compensation need be done.
1246 */
1247 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1248 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1249 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1250 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1251 use_scaling = 1;
1252 }
1253 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1254}
1255
1256static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1257{
e26101b1 1258 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1259 vcpu->arch.virtual_tsc_mult,
1260 vcpu->arch.virtual_tsc_shift);
e26101b1 1261 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1262 return tsc;
1263}
1264
69b0049a 1265static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1266{
1267#ifdef CONFIG_X86_64
1268 bool vcpus_matched;
b48aa97e
MT		 1269 struct kvm_arch *ka = &vcpu->kvm->arch;
1270 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1271
1272 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1273 atomic_read(&vcpu->kvm->online_vcpus));
1274
7f187922
MT		 1275 /*
1276 * Once the masterclock is enabled, always perform request in
1277 * order to update it.
1278 *
1279 * In order to enable masterclock, the host clocksource must be TSC
1280 * and the vcpus need to have matched TSCs. When that happens,
1281 * perform request to enable masterclock.
1282 */
1283 if (ka->use_master_clock ||
1284 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1285 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1286
1287 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1288 atomic_read(&vcpu->kvm->online_vcpus),
1289 ka->use_master_clock, gtod->clock.vclock_mode);
1290#endif
1291}
1292
ba904635
WA		 1293static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1294{
1295 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1296 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1297}
1298
8fe8ab46 1299void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1300{
1301 struct kvm *kvm = vcpu->kvm;
f38e098f 1302 u64 offset, ns, elapsed;
99e3e30a 1303 unsigned long flags;
02626b6a 1304 s64 usdiff;
b48aa97e 1305 bool matched;
0d3da0d2 1306 bool already_matched;
8fe8ab46 1307 u64 data = msr->data;
99e3e30a 1308
038f8c11 1309 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1310 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1311 ns = get_kernel_ns();
f38e098f 1312 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1313
03ba32ca 1314 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1315 int faulted = 0;
1316
03ba32ca
MT		 1317 /* n.b - signed multiplication and division required */
1318 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1319#ifdef CONFIG_X86_64
03ba32ca 1320 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1321#else
03ba32ca 1322 /* do_div() only does unsigned */
8915aa27
MT		 1323 asm("1: idivl %[divisor]\n"
1324 "2: xor %%edx, %%edx\n"
1325 " movl $0, %[faulted]\n"
1326 "3:\n"
1327 ".section .fixup,\"ax\"\n"
1328 "4: movl $1, %[faulted]\n"
1329 " jmp 3b\n"
1330 ".previous\n"
1331
1332 _ASM_EXTABLE(1b, 4b)
1333
1334 : "=A"(usdiff), [faulted] "=r" (faulted)
1335 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1336
5d3cb0f6 1337#endif
03ba32ca
MT		 1338 do_div(elapsed, 1000);
1339 usdiff -= elapsed;
1340 if (usdiff < 0)
1341 usdiff = -usdiff;
8915aa27
MT		 1342
1343 /* idivl overflow => difference is larger than USEC_PER_SEC */
1344 if (faulted)
1345 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1346 } else
1347 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1348
1349 /*
5d3cb0f6
ZA		 1350 * Special case: TSC write with a small delta (1 second) of virtual
1351 * cycle time against real time is interpreted as an attempt to
1352 * synchronize the CPU.
1353 *
1354 * For a reliable TSC, we can match TSC offsets, and for an unstable
1355 * TSC, we add elapsed time in this computation. We could let the
1356 * compensation code attempt to catch up if we fall behind, but
1357 * it's better to try to match offsets from the beginning.
1358 */
02626b6a 1359 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1360 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1361 if (!check_tsc_unstable()) {
e26101b1 1362 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1363 pr_debug("kvm: matched tsc offset for %llu\n", data);
1364 } else {
857e4099 1365 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1366 data += delta;
1367 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1368 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1369 }
b48aa97e 1370 matched = true;
0d3da0d2 1371 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1372 } else {
1373 /*
1374 * We split periods of matched TSC writes into generations.
1375 * For each generation, we track the original measured
1376 * nanosecond time, offset, and write, so if TSCs are in
1377 * sync, we can match exact offset, and if not, we can match
4a969980 1378 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1379 *
1380 * These values are tracked in kvm->arch.cur_xxx variables.
1381 */
1382 kvm->arch.cur_tsc_generation++;
1383 kvm->arch.cur_tsc_nsec = ns;
1384 kvm->arch.cur_tsc_write = data;
1385 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1386 matched = false;
0d3da0d2 1387 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1388 kvm->arch.cur_tsc_generation, data);
f38e098f 1389 }
e26101b1
ZA		 1390
1391 /*
1392 * We also track th most recent recorded KHZ, write and time to
1393 * allow the matching interval to be extended at each write.
1394 */
f38e098f
ZA		 1395 kvm->arch.last_tsc_nsec = ns;
1396 kvm->arch.last_tsc_write = data;
5d3cb0f6 1397 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1398
b183aa58 1399 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1400
1401 /* Keep track of which generation this VCPU has synchronized to */
1402 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1403 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1404 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1405
ba904635
WA		 1406 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1407 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1408 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1409 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1410
1411 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1412 if (!matched) {
b48aa97e 1413 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1414 } else if (!already_matched) {
1415 kvm->arch.nr_vcpus_matched_tsc++;
1416 }
b48aa97e
MT		 1417
1418 kvm_track_tsc_matching(vcpu);
1419 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1420}
e26101b1 1421
99e3e30a
ZA		 1422EXPORT_SYMBOL_GPL(kvm_write_tsc);
1423
d828199e
MT		 1424#ifdef CONFIG_X86_64
1425
1426static cycle_t read_tsc(void)
1427{
1428 cycle_t ret;
1429 u64 last;
1430
1431 /*
1432 * Empirically, a fence (of type that depends on the CPU)
1433 * before rdtsc is enough to ensure that rdtsc is ordered
1434 * with respect to loads. The various CPU manuals are unclear
1435 * as to whether rdtsc can be reordered with later loads,
1436 * but no one has ever seen it happen.
1437 */
1438 rdtsc_barrier();
1439 ret = (cycle_t)vget_cycles();
1440
1441 last = pvclock_gtod_data.clock.cycle_last;
1442
1443 if (likely(ret >= last))
1444 return ret;
1445
1446 /*
1447 * GCC likes to generate cmov here, but this branch is extremely
1448 * predictable (it's just a funciton of time and the likely is
1449 * very likely) and there's a data dependence, so force GCC
1450 * to generate a branch instead. I don't barrier() because
1451 * we don't actually need a barrier, and if this function
1452 * ever gets inlined it will generate worse code.
1453 */
1454 asm volatile ("");
1455 return last;
1456}
1457
1458static inline u64 vgettsc(cycle_t *cycle_now)
1459{
1460 long v;
1461 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1462
1463 *cycle_now = read_tsc();
1464
1465 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1466 return v * gtod->clock.mult;
1467}
1468
cbcf2dd3 1469static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1470{
cbcf2dd3 1471 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1472 unsigned long seq;
d828199e 1473 int mode;
cbcf2dd3 1474 u64 ns;
d828199e 1475
d828199e
MT		 1476 do {
1477 seq = read_seqcount_begin(&gtod->seq);
1478 mode = gtod->clock.vclock_mode;
cbcf2dd3 1479 ns = gtod->nsec_base;
d828199e
MT		 1480 ns += vgettsc(cycle_now);
1481 ns >>= gtod->clock.shift;
cbcf2dd3 1482 ns += gtod->boot_ns;
d828199e 1483 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1484 *t = ns;
d828199e
MT		 1485
1486 return mode;
1487}
1488
1489/* returns true if host is using tsc clocksource */
1490static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1491{
d828199e
MT		 1492 /* checked again under seqlock below */
1493 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1494 return false;
1495
cbcf2dd3 1496 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1497}
1498#endif
1499
1500/*
1501 *
b48aa97e
MT		 1502 * Assuming a stable TSC across physical CPUS, and a stable TSC
1503 * across virtual CPUs, the following condition is possible.
1504 * Each numbered line represents an event visible to both
d828199e
MT		 1505 * CPUs at the next numbered event.
1506 *
1507 * "timespecX" represents host monotonic time. "tscX" represents
1508 * RDTSC value.
1509 *
1510 * VCPU0 on CPU0 | VCPU1 on CPU1
1511 *
1512 * 1. read timespec0,tsc0
1513 * 2. | timespec1 = timespec0 + N
1514 * | tsc1 = tsc0 + M
1515 * 3. transition to guest | transition to guest
1516 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1517 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1518 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1519 *
1520 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1521 *
1522 * - ret0 < ret1
1523 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1524 * ...
1525 * - 0 < N - M => M < N
1526 *
1527 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1528 * always the case (the difference between two distinct xtime instances
1529 * might be smaller then the difference between corresponding TSC reads,
1530 * when updating guest vcpus pvclock areas).
1531 *
1532 * To avoid that problem, do not allow visibility of distinct
1533 * system_timestamp/tsc_timestamp values simultaneously: use a master
1534 * copy of host monotonic time values. Update that master copy
1535 * in lockstep.
1536 *
b48aa97e 1537 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1538 *
1539 */
1540
1541static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1542{
1543#ifdef CONFIG_X86_64
1544 struct kvm_arch *ka = &kvm->arch;
1545 int vclock_mode;
b48aa97e
MT		 1546 bool host_tsc_clocksource, vcpus_matched;
1547
1548 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1549 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1550
1551 /*
1552 * If the host uses TSC clock, then passthrough TSC as stable
1553 * to the guest.
1554 */
b48aa97e 1555 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1556 &ka->master_kernel_ns,
1557 &ka->master_cycle_now);
1558
16a96021 1559 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1560 && !backwards_tsc_observed
1561 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1562
d828199e
MT		 1563 if (ka->use_master_clock)
1564 atomic_set(&kvm_guest_has_master_clock, 1);
1565
1566 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1567 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1568 vcpus_matched);
d828199e
MT		 1569#endif
1570}
1571
2e762ff7
MT		 1572static void kvm_gen_update_masterclock(struct kvm *kvm)
1573{
1574#ifdef CONFIG_X86_64
1575 int i;
1576 struct kvm_vcpu *vcpu;
1577 struct kvm_arch *ka = &kvm->arch;
1578
1579 spin_lock(&ka->pvclock_gtod_sync_lock);
1580 kvm_make_mclock_inprogress_request(kvm);
1581 /* no guest entries from this point */
1582 pvclock_update_vm_gtod_copy(kvm);
1583
1584 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1585 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1586
1587 /* guest entries allowed */
1588 kvm_for_each_vcpu(i, vcpu, kvm)
1589 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1590
1591 spin_unlock(&ka->pvclock_gtod_sync_lock);
1592#endif
1593}
1594
34c238a1 1595static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1596{
d828199e 1597 unsigned long flags, this_tsc_khz;
18068523 1598 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1599 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1600 s64 kernel_ns;
d828199e 1601 u64 tsc_timestamp, host_tsc;
0b79459b 1602 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1603 u8 pvclock_flags;
d828199e
MT		 1604 bool use_master_clock;
1605
1606 kernel_ns = 0;
1607 host_tsc = 0;
18068523 1608
d828199e
MT		 1609 /*
1610 * If the host uses TSC clock, then passthrough TSC as stable
1611 * to the guest.
1612 */
1613 spin_lock(&ka->pvclock_gtod_sync_lock);
1614 use_master_clock = ka->use_master_clock;
1615 if (use_master_clock) {
1616 host_tsc = ka->master_cycle_now;
1617 kernel_ns = ka->master_kernel_ns;
1618 }
1619 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1620
1621 /* Keep irq disabled to prevent changes to the clock */
1622 local_irq_save(flags);
89cbc767 1623 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1624 if (unlikely(this_tsc_khz == 0)) {
1625 local_irq_restore(flags);
1626 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1627 return 1;
1628 }
d828199e
MT		 1629 if (!use_master_clock) {
1630 host_tsc = native_read_tsc();
1631 kernel_ns = get_kernel_ns();
1632 }
1633
1634 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1635
c285545f
ZA		 1636 /*
1637 * We may have to catch up the TSC to match elapsed wall clock
1638 * time for two reasons, even if kvmclock is used.
1639 * 1) CPU could have been running below the maximum TSC rate
1640 * 2) Broken TSC compensation resets the base at each VCPU
1641 * entry to avoid unknown leaps of TSC even when running
1642 * again on the same CPU. This may cause apparent elapsed
1643 * time to disappear, and the guest to stand still or run
1644 * very slowly.
1645 */
1646 if (vcpu->tsc_catchup) {
1647 u64 tsc = compute_guest_tsc(v, kernel_ns);
1648 if (tsc > tsc_timestamp) {
f1e2b260 1649 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1650 tsc_timestamp = tsc;
1651 }
50d0a0f9
GH		 1652 }
1653
18068523
GOC		 1654 local_irq_restore(flags);
1655
0b79459b 1656 if (!vcpu->pv_time_enabled)
c285545f 1657 return 0;
18068523 1658
e48672fa 1659 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1660 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1661 &vcpu->hv_clock.tsc_shift,
1662 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1663 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1664 }
1665
1666 /* With all the info we got, fill in the values */
1d5f066e 1667 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1668 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1669 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1670
09a0c3f1
OH		 1671 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1672 &guest_hv_clock, sizeof(guest_hv_clock))))
1673 return 0;
1674
5dca0d91
RK		 1675 /* This VCPU is paused, but it's legal for a guest to read another
1676 * VCPU's kvmclock, so we really have to follow the specification where
1677 * it says that version is odd if data is being modified, and even after
1678 * it is consistent.
1679 *
1680 * Version field updates must be kept separate. This is because
1681 * kvm_write_guest_cached might use a "rep movs" instruction, and
1682 * writes within a string instruction are weakly ordered. So there
1683 * are three writes overall.
1684 *
1685 * As a small optimization, only write the version field in the first
1686 * and third write. The vcpu->pv_time cache is still valid, because the
1687 * version field is the first in the struct.
18068523 1688 */
5dca0d91
RK		 1689 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1690
1691 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1692 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1693 &vcpu->hv_clock,
1694 sizeof(vcpu->hv_clock.version));
1695
1696 smp_wmb();
78c0337a
MT		 1697
1698 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1699 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1700
1701 if (vcpu->pvclock_set_guest_stopped_request) {
1702 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1703 vcpu->pvclock_set_guest_stopped_request = false;
1704 }
1705
b7e60c5a
MT		 1706 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1707
d828199e
MT		 1708 /* If the host uses TSC clocksource, then it is stable */
1709 if (use_master_clock)
1710 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1711
78c0337a
MT		 1712 vcpu->hv_clock.flags = pvclock_flags;
1713
ce1a5e60
DM		 1714 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1715
0b79459b
AH		 1716 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1717 &vcpu->hv_clock,
1718 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1719
1720 smp_wmb();
1721
1722 vcpu->hv_clock.version++;
1723 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1724 &vcpu->hv_clock,
1725 sizeof(vcpu->hv_clock.version));
8cfdc000 1726 return 0;
c8076604
GH		 1727}
1728
0061d53d
MT		 1729/*
1730 * kvmclock updates which are isolated to a given vcpu, such as
1731 * vcpu->cpu migration, should not allow system_timestamp from
1732 * the rest of the vcpus to remain static. Otherwise ntp frequency
1733 * correction applies to one vcpu's system_timestamp but not
1734 * the others.
1735 *
1736 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1737 * We need to rate-limit these requests though, as they can
1738 * considerably slow guests that have a large number of vcpus.
1739 * The time for a remote vcpu to update its kvmclock is bound
1740 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1741 */
1742
7e44e449
AJ		 1743#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1744
1745static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1746{
1747 int i;
7e44e449
AJ		 1748 struct delayed_work *dwork = to_delayed_work(work);
1749 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1750 kvmclock_update_work);
1751 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1752 struct kvm_vcpu *vcpu;
1753
1754 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1755 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1756 kvm_vcpu_kick(vcpu);
1757 }
1758}
1759
7e44e449
AJ		 1760static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1761{
1762 struct kvm *kvm = v->kvm;
1763
105b21bb 1764 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1765 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1766 KVMCLOCK_UPDATE_DELAY);
1767}
1768
332967a3
AJ		 1769#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1770
1771static void kvmclock_sync_fn(struct work_struct *work)
1772{
1773 struct delayed_work *dwork = to_delayed_work(work);
1774 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1775 kvmclock_sync_work);
1776 struct kvm *kvm = container_of(ka, struct kvm, arch);
1777
630994b3
MT		 1778 if (!kvmclock_periodic_sync)
1779 return;
1780
332967a3
AJ		 1781 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1782 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1783 KVMCLOCK_SYNC_PERIOD);
1784}
1785
9ba075a6
AK		 1786static bool msr_mtrr_valid(unsigned msr)
1787{
1788 switch (msr) {
1789 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1790 case MSR_MTRRfix64K_00000:
1791 case MSR_MTRRfix16K_80000:
1792 case MSR_MTRRfix16K_A0000:
1793 case MSR_MTRRfix4K_C0000:
1794 case MSR_MTRRfix4K_C8000:
1795 case MSR_MTRRfix4K_D0000:
1796 case MSR_MTRRfix4K_D8000:
1797 case MSR_MTRRfix4K_E0000:
1798 case MSR_MTRRfix4K_E8000:
1799 case MSR_MTRRfix4K_F0000:
1800 case MSR_MTRRfix4K_F8000:
1801 case MSR_MTRRdefType:
1802 case MSR_IA32_CR_PAT:
1803 return true;
1804 case 0x2f8:
1805 return true;
1806 }
1807 return false;
1808}
1809
d6289b93
MT		 1810static bool valid_pat_type(unsigned t)
1811{
1812 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1813}
1814
1815static bool valid_mtrr_type(unsigned t)
1816{
1817 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1818}
1819
4566654b 1820bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1821{
1822 int i;
fd275235 1823 u64 mask;
d6289b93
MT		 1824
1825 if (!msr_mtrr_valid(msr))
1826 return false;
1827
1828 if (msr == MSR_IA32_CR_PAT) {
1829 for (i = 0; i < 8; i++)
1830 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1831 return false;
1832 return true;
1833 } else if (msr == MSR_MTRRdefType) {
1834 if (data & ~0xcff)
1835 return false;
1836 return valid_mtrr_type(data & 0xff);
1837 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1838 for (i = 0; i < 8 ; i++)
1839 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1840 return false;
1841 return true;
1842 }
1843
1844 /* variable MTRRs */
adfb5d27
WL		 1845 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1846
fd275235 1847 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1848 if ((msr & 1) == 0) {
adfb5d27 1849 /* MTRR base */
d7a2a246
WL		 1850 if (!valid_mtrr_type(data & 0xff))
1851 return false;
1852 mask |= 0xf00;
1853 } else
1854 /* MTRR mask */
1855 mask |= 0x7ff;
1856 if (data & mask) {
1857 kvm_inject_gp(vcpu, 0);
1858 return false;
1859 }
1860
adfb5d27 1861 return true;
d6289b93 1862}
4566654b 1863EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1864
efdfe536
XG		 1865static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr)
1866{
1867 struct mtrr_state_type *mtrr_state = &vcpu->arch.mtrr_state;
1868 unsigned char mtrr_enabled = mtrr_state->enabled;
1869 gfn_t start, end, mask;
1870 int index;
1871 bool is_fixed = true;
1872
1873 if (msr == MSR_IA32_CR_PAT || !tdp_enabled ||
1874 !kvm_arch_has_noncoherent_dma(vcpu->kvm))
1875 return;
1876
1877 if (!(mtrr_enabled & 0x2) && msr != MSR_MTRRdefType)
1878 return;
1879
1880 switch (msr) {
1881 case MSR_MTRRfix64K_00000:
1882 start = 0x0;
1883 end = 0x80000;
1884 break;
1885 case MSR_MTRRfix16K_80000:
1886 start = 0x80000;
1887 end = 0xa0000;
1888 break;
1889 case MSR_MTRRfix16K_A0000:
1890 start = 0xa0000;
1891 end = 0xc0000;
1892 break;
1893 case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000:
1894 index = msr - MSR_MTRRfix4K_C0000;
1895 start = 0xc0000 + index * (32 << 10);
1896 end = start + (32 << 10);
1897 break;
1898 case MSR_MTRRdefType:
1899 is_fixed = false;
1900 start = 0x0;
1901 end = ~0ULL;
1902 break;
1903 default:
1904 /* variable range MTRRs. */
1905 is_fixed = false;
1906 index = (msr - 0x200) / 2;
1907 start = (((u64)mtrr_state->var_ranges[index].base_hi) << 32) +
1908 (mtrr_state->var_ranges[index].base_lo & PAGE_MASK);
1909 mask = (((u64)mtrr_state->var_ranges[index].mask_hi) << 32) +
1910 (mtrr_state->var_ranges[index].mask_lo & PAGE_MASK);
1911 mask |= ~0ULL << cpuid_maxphyaddr(vcpu);
1912
1913 end = ((start & mask) | ~mask) + 1;
1914 }
1915
1916 if (is_fixed && !(mtrr_enabled & 0x1))
1917 return;
1918
1919 kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end));
1920}
1921
9ba075a6
AK		 1922static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1923{
0bed3b56
SY		 1924 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1925
4566654b 1926 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1927 return 1;
1928
0bed3b56
SY		 1929 if (msr == MSR_MTRRdefType) {
1930 vcpu->arch.mtrr_state.def_type = data;
1931 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1932 } else if (msr == MSR_MTRRfix64K_00000)
1933 p[0] = data;
1934 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1935 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1936 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1937 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1938 else if (msr == MSR_IA32_CR_PAT)
1939 vcpu->arch.pat = data;
1940 else { /* Variable MTRRs */
1941 int idx, is_mtrr_mask;
1942 u64 *pt;
1943
1944 idx = (msr - 0x200) / 2;
1945 is_mtrr_mask = msr - 0x200 - 2 * idx;
1946 if (!is_mtrr_mask)
1947 pt =
1948 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1949 else
1950 pt =
1951 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1952 *pt = data;
1953 }
1954
efdfe536 1955 update_mtrr(vcpu, msr);
9ba075a6
AK		 1956 return 0;
1957}
15c4a640 1958
890ca9ae 1959static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1960{
890ca9ae
HY		 1961 u64 mcg_cap = vcpu->arch.mcg_cap;
1962 unsigned bank_num = mcg_cap & 0xff;
1963
15c4a640 1964 switch (msr) {
15c4a640 1965 case MSR_IA32_MCG_STATUS:
890ca9ae 1966 vcpu->arch.mcg_status = data;
15c4a640 1967 break;
c7ac679c 1968 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1969 if (!(mcg_cap & MCG_CTL_P))
1970 return 1;
1971 if (data != 0 && data != ~(u64)0)
1972 return -1;
1973 vcpu->arch.mcg_ctl = data;
1974 break;
1975 default:
1976 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1977 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1978 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1979 /* only 0 or all 1s can be written to IA32_MCi_CTL
1980 * some Linux kernels though clear bit 10 in bank 4 to
1981 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1982 * this to avoid an uncatched #GP in the guest
1983 */
890ca9ae 1984 if ((offset & 0x3) == 0 &&
114be429 1985 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1986 return -1;
1987 vcpu->arch.mce_banks[offset] = data;
1988 break;
1989 }
1990 return 1;
1991 }
1992 return 0;
1993}
1994
ffde22ac
ES		 1995static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1996{
1997 struct kvm *kvm = vcpu->kvm;
1998 int lm = is_long_mode(vcpu);
1999 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2000 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2001 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2002 : kvm->arch.xen_hvm_config.blob_size_32;
2003 u32 page_num = data & ~PAGE_MASK;
2004 u64 page_addr = data & PAGE_MASK;
2005 u8 *page;
2006 int r;
2007
2008 r = -E2BIG;
2009 if (page_num >= blob_size)
2010 goto out;
2011 r = -ENOMEM;
ff5c2c03
SL		 2012 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2013 if (IS_ERR(page)) {
2014 r = PTR_ERR(page);
ffde22ac 2015 goto out;
ff5c2c03 2016 }
ffde22ac
ES		 2017 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
2018 goto out_free;
2019 r = 0;
2020out_free:
2021 kfree(page);
2022out:
2023 return r;
2024}
2025
55cd8e5a
GN		 2026static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
2027{
2028 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
2029}
2030
2031static bool kvm_hv_msr_partition_wide(u32 msr)
2032{
2033 bool r = false;
2034 switch (msr) {
2035 case HV_X64_MSR_GUEST_OS_ID:
2036 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 2037 case HV_X64_MSR_REFERENCE_TSC:
2038 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 2039 r = true;
2040 break;
2041 }
2042
2043 return r;
2044}
2045
2046static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2047{
2048 struct kvm *kvm = vcpu->kvm;
2049
2050 switch (msr) {
2051 case HV_X64_MSR_GUEST_OS_ID:
2052 kvm->arch.hv_guest_os_id = data;
2053 /* setting guest os id to zero disables hypercall page */
2054 if (!kvm->arch.hv_guest_os_id)
2055 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
2056 break;
2057 case HV_X64_MSR_HYPERCALL: {
2058 u64 gfn;
2059 unsigned long addr;
2060 u8 instructions[4];
2061
2062 /* if guest os id is not set hypercall should remain disabled */
2063 if (!kvm->arch.hv_guest_os_id)
2064 break;
2065 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2066 kvm->arch.hv_hypercall = data;
2067 break;
2068 }
2069 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2070 addr = gfn_to_hva(kvm, gfn);
2071 if (kvm_is_error_hva(addr))
2072 return 1;
2073 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2074 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2075 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2076 return 1;
2077 kvm->arch.hv_hypercall = data;
b94b64c9 2078 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2079 break;
2080 }
e984097b
VR		 2081 case HV_X64_MSR_REFERENCE_TSC: {
2082 u64 gfn;
2083 HV_REFERENCE_TSC_PAGE tsc_ref;
2084 memset(&tsc_ref, 0, sizeof(tsc_ref));
2085 kvm->arch.hv_tsc_page = data;
2086 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2087 break;
2088 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2089 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2090 &tsc_ref, sizeof(tsc_ref)))
2091 return 1;
2092 mark_page_dirty(kvm, gfn);
2093 break;
2094 }
55cd8e5a 2095 default:
a737f256
CD		 2096 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2097 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2098 return 1;
2099 }
2100 return 0;
2101}
2102
2103static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2104{
10388a07
GN		 2105 switch (msr) {
2106 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2107 u64 gfn;
10388a07 2108 unsigned long addr;
55cd8e5a 2109
10388a07
GN		 2110 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2111 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2112 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2113 return 1;
10388a07
GN		 2114 break;
2115 }
b3af1e88
VR		 2116 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2117 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2118 if (kvm_is_error_hva(addr))
2119 return 1;
8b0cedff 2120 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2121 return 1;
2122 vcpu->arch.hv_vapic = data;
b3af1e88 2123 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2124 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2125 return 1;
10388a07
GN		 2126 break;
2127 }
2128 case HV_X64_MSR_EOI:
2129 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2130 case HV_X64_MSR_ICR:
2131 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2132 case HV_X64_MSR_TPR:
2133 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2134 default:
a737f256
CD		 2135 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2136 "data 0x%llx\n", msr, data);
10388a07
GN		 2137 return 1;
2138 }
2139
2140 return 0;
55cd8e5a
GN		 2141}
2142
344d9588
GN		 2143static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2144{
2145 gpa_t gpa = data & ~0x3f;
2146
4a969980 2147 /* Bits 2:5 are reserved, Should be zero */
6adba527 2148 if (data & 0x3c)
344d9588
GN		 2149 return 1;
2150
2151 vcpu->arch.apf.msr_val = data;
2152
2153 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2154 kvm_clear_async_pf_completion_queue(vcpu);
2155 kvm_async_pf_hash_reset(vcpu);
2156 return 0;
2157 }
2158
8f964525
AH		 2159 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2160 sizeof(u32)))
344d9588
GN		 2161 return 1;
2162
6adba527 2163 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2164 kvm_async_pf_wakeup_all(vcpu);
2165 return 0;
2166}
2167
12f9a48f
GC		 2168static void kvmclock_reset(struct kvm_vcpu *vcpu)
2169{
0b79459b 2170 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2171}
2172
c9aaa895
GC		 2173static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2174{
2175 u64 delta;
2176
2177 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2178 return;
2179
2180 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2181 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2182 vcpu->arch.st.accum_steal = delta;
2183}
2184
2185static void record_steal_time(struct kvm_vcpu *vcpu)
2186{
2187 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2188 return;
2189
2190 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2191 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2192 return;
2193
2194 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2195 vcpu->arch.st.steal.version += 2;
2196 vcpu->arch.st.accum_steal = 0;
2197
2198 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2199 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2200}
2201
8fe8ab46 2202int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2203{
5753785f 2204 bool pr = false;
8fe8ab46
WA		 2205 u32 msr = msr_info->index;
2206 u64 data = msr_info->data;
5753785f 2207
15c4a640 2208 switch (msr) {
2e32b719
BP		 2209 case MSR_AMD64_NB_CFG:
2210 case MSR_IA32_UCODE_REV:
2211 case MSR_IA32_UCODE_WRITE:
2212 case MSR_VM_HSAVE_PA:
2213 case MSR_AMD64_PATCH_LOADER:
2214 case MSR_AMD64_BU_CFG2:
2215 break;
2216
15c4a640 2217 case MSR_EFER:
b69e8cae 2218 return set_efer(vcpu, data);
8f1589d9
AP		 2219 case MSR_K7_HWCR:
2220 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2221 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2222 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2223 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2224 if (data != 0) {
a737f256
CD		 2225 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2226 data);
8f1589d9
AP		 2227 return 1;
2228 }
15c4a640 2229 break;
f7c6d140
AP		 2230 case MSR_FAM10H_MMIO_CONF_BASE:
2231 if (data != 0) {
a737f256
CD		 2232 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2233 "0x%llx\n", data);
f7c6d140
AP		 2234 return 1;
2235 }
15c4a640 2236 break;
b5e2fec0
AG		 2237 case MSR_IA32_DEBUGCTLMSR:
2238 if (!data) {
2239 /* We support the non-activated case already */
2240 break;
2241 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2242 /* Values other than LBR and BTF are vendor-specific,
2243 thus reserved and should throw a #GP */
2244 return 1;
2245 }
a737f256
CD		 2246 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2247 __func__, data);
b5e2fec0 2248 break;
9ba075a6
AK		 2249 case 0x200 ... 0x2ff:
2250 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2251 case MSR_IA32_APICBASE:
58cb628d 2252 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2253 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2254 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2255 case MSR_IA32_TSCDEADLINE:
2256 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2257 break;
ba904635
WA		 2258 case MSR_IA32_TSC_ADJUST:
2259 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2260 if (!msr_info->host_initiated) {
d913b904 2261 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2262 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2263 }
2264 vcpu->arch.ia32_tsc_adjust_msr = data;
2265 }
2266 break;
15c4a640 2267 case MSR_IA32_MISC_ENABLE:
ad312c7c 2268 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2269 break;
11c6bffa 2270 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2271 case MSR_KVM_WALL_CLOCK:
2272 vcpu->kvm->arch.wall_clock = data;
2273 kvm_write_wall_clock(vcpu->kvm, data);
2274 break;
11c6bffa 2275 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2276 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2277 u64 gpa_offset;
54750f2c
MT		 2278 struct kvm_arch *ka = &vcpu->kvm->arch;
2279
12f9a48f 2280 kvmclock_reset(vcpu);
18068523 2281
54750f2c
MT		 2282 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2283 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2284
2285 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2286 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2287 &vcpu->requests);
2288
2289 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2290
2291 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2292 }
2293
18068523 2294 vcpu->arch.time = data;
0061d53d 2295 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2296
2297 /* we verify if the enable bit is set... */
2298 if (!(data & 1))
2299 break;
2300
0b79459b 2301 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2302
0b79459b 2303 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2304 &vcpu->arch.pv_time, data & ~1ULL,
2305 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2306 vcpu->arch.pv_time_enabled = false;
2307 else
2308 vcpu->arch.pv_time_enabled = true;
32cad84f 2309
18068523
GOC		 2310 break;
2311 }
344d9588
GN		 2312 case MSR_KVM_ASYNC_PF_EN:
2313 if (kvm_pv_enable_async_pf(vcpu, data))
2314 return 1;
2315 break;
c9aaa895
GC		 2316 case MSR_KVM_STEAL_TIME:
2317
2318 if (unlikely(!sched_info_on()))
2319 return 1;
2320
2321 if (data & KVM_STEAL_RESERVED_MASK)
2322 return 1;
2323
2324 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2325 data & KVM_STEAL_VALID_BITS,
2326 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2327 return 1;
2328
2329 vcpu->arch.st.msr_val = data;
2330
2331 if (!(data & KVM_MSR_ENABLED))
2332 break;
2333
2334 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2335
2336 preempt_disable();
2337 accumulate_steal_time(vcpu);
2338 preempt_enable();
2339
2340 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2341
2342 break;
ae7a2a3f
MT		 2343 case MSR_KVM_PV_EOI_EN:
2344 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2345 return 1;
2346 break;
c9aaa895 2347
890ca9ae
HY		 2348 case MSR_IA32_MCG_CTL:
2349 case MSR_IA32_MCG_STATUS:
81760dcc 2350 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2351 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2352
2353 /* Performance counters are not protected by a CPUID bit,
2354 * so we should check all of them in the generic path for the sake of
2355 * cross vendor migration.
2356 * Writing a zero into the event select MSRs disables them,
2357 * which we perfectly emulate ;-). Any other value should be at least
2358 * reported, some guests depend on them.
2359 */
71db6023
AP		 2360 case MSR_K7_EVNTSEL0:
2361 case MSR_K7_EVNTSEL1:
2362 case MSR_K7_EVNTSEL2:
2363 case MSR_K7_EVNTSEL3:
2364 if (data != 0)
a737f256
CD		 2365 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2366 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2367 break;
2368 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2369 * so we ignore writes to make it happy.
2370 */
71db6023
AP		 2371 case MSR_K7_PERFCTR0:
2372 case MSR_K7_PERFCTR1:
2373 case MSR_K7_PERFCTR2:
2374 case MSR_K7_PERFCTR3:
a737f256
CD		 2375 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2376 "0x%x data 0x%llx\n", msr, data);
71db6023 2377 break;
5753785f
GN		 2378 case MSR_P6_PERFCTR0:
2379 case MSR_P6_PERFCTR1:
2380 pr = true;
2381 case MSR_P6_EVNTSEL0:
2382 case MSR_P6_EVNTSEL1:
2383 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2384 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2385
2386 if (pr || data != 0)
a737f256
CD		 2387 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2388 "0x%x data 0x%llx\n", msr, data);
5753785f 2389 break;
84e0cefa
JS		 2390 case MSR_K7_CLK_CTL:
2391 /*
2392 * Ignore all writes to this no longer documented MSR.
2393 * Writes are only relevant for old K7 processors,
2394 * all pre-dating SVM, but a recommended workaround from
4a969980 2395 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2396 * affected processor models on the command line, hence
2397 * the need to ignore the workaround.
2398 */
2399 break;
55cd8e5a
GN		 2400 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2401 if (kvm_hv_msr_partition_wide(msr)) {
2402 int r;
2403 mutex_lock(&vcpu->kvm->lock);
2404 r = set_msr_hyperv_pw(vcpu, msr, data);
2405 mutex_unlock(&vcpu->kvm->lock);
2406 return r;
2407 } else
2408 return set_msr_hyperv(vcpu, msr, data);
2409 break;
91c9c3ed 2410 case MSR_IA32_BBL_CR_CTL3:
2411 /* Drop writes to this legacy MSR -- see rdmsr
2412 * counterpart for further detail.
2413 */
a737f256 2414 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2415 break;
2b036c6b
BO		 2416 case MSR_AMD64_OSVW_ID_LENGTH:
2417 if (!guest_cpuid_has_osvw(vcpu))
2418 return 1;
2419 vcpu->arch.osvw.length = data;
2420 break;
2421 case MSR_AMD64_OSVW_STATUS:
2422 if (!guest_cpuid_has_osvw(vcpu))
2423 return 1;
2424 vcpu->arch.osvw.status = data;
2425 break;
15c4a640 2426 default:
ffde22ac
ES		 2427 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2428 return xen_hvm_config(vcpu, data);
f5132b01 2429 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2430 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2431 if (!ignore_msrs) {
a737f256
CD		 2432 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2433 msr, data);
ed85c068
AP		 2434 return 1;
2435 } else {
a737f256
CD		 2436 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2437 msr, data);
ed85c068
AP		 2438 break;
2439 }
15c4a640
CO		 2440 }
2441 return 0;
2442}
2443EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2444
2445
2446/*
2447 * Reads an msr value (of 'msr_index') into 'pdata'.
2448 * Returns 0 on success, non-0 otherwise.
2449 * Assumes vcpu_load() was already called.
2450 */
2451int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2452{
2453 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2454}
ff651cb6 2455EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2456
9ba075a6
AK		 2457static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2458{
0bed3b56
SY		 2459 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2460
9ba075a6
AK		 2461 if (!msr_mtrr_valid(msr))
2462 return 1;
2463
0bed3b56
SY		 2464 if (msr == MSR_MTRRdefType)
2465 *pdata = vcpu->arch.mtrr_state.def_type +
2466 (vcpu->arch.mtrr_state.enabled << 10);
2467 else if (msr == MSR_MTRRfix64K_00000)
2468 *pdata = p[0];
2469 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2470 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2471 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2472 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2473 else if (msr == MSR_IA32_CR_PAT)
2474 *pdata = vcpu->arch.pat;
2475 else { /* Variable MTRRs */
2476 int idx, is_mtrr_mask;
2477 u64 *pt;
2478
2479 idx = (msr - 0x200) / 2;
2480 is_mtrr_mask = msr - 0x200 - 2 * idx;
2481 if (!is_mtrr_mask)
2482 pt =
2483 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2484 else
2485 pt =
2486 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2487 *pdata = *pt;
2488 }
2489
9ba075a6
AK		 2490 return 0;
2491}
2492
890ca9ae 2493static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2494{
2495 u64 data;
890ca9ae
HY		 2496 u64 mcg_cap = vcpu->arch.mcg_cap;
2497 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2498
2499 switch (msr) {
15c4a640
CO		 2500 case MSR_IA32_P5_MC_ADDR:
2501 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2502 data = 0;
2503 break;
15c4a640 2504 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2505 data = vcpu->arch.mcg_cap;
2506 break;
c7ac679c 2507 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2508 if (!(mcg_cap & MCG_CTL_P))
2509 return 1;
2510 data = vcpu->arch.mcg_ctl;
2511 break;
2512 case MSR_IA32_MCG_STATUS:
2513 data = vcpu->arch.mcg_status;
2514 break;
2515 default:
2516 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2517 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2518 u32 offset = msr - MSR_IA32_MC0_CTL;
2519 data = vcpu->arch.mce_banks[offset];
2520 break;
2521 }
2522 return 1;
2523 }
2524 *pdata = data;
2525 return 0;
2526}
2527
55cd8e5a
GN		 2528static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2529{
2530 u64 data = 0;
2531 struct kvm *kvm = vcpu->kvm;
2532
2533 switch (msr) {
2534 case HV_X64_MSR_GUEST_OS_ID:
2535 data = kvm->arch.hv_guest_os_id;
2536 break;
2537 case HV_X64_MSR_HYPERCALL:
2538 data = kvm->arch.hv_hypercall;
2539 break;
e984097b
VR		 2540 case HV_X64_MSR_TIME_REF_COUNT: {
2541 data =
2542 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2543 break;
2544 }
2545 case HV_X64_MSR_REFERENCE_TSC:
2546 data = kvm->arch.hv_tsc_page;
2547 break;
55cd8e5a 2548 default:
a737f256 2549 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2550 return 1;
2551 }
2552
2553 *pdata = data;
2554 return 0;
2555}
2556
2557static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2558{
2559 u64 data = 0;
2560
2561 switch (msr) {
2562 case HV_X64_MSR_VP_INDEX: {
2563 int r;
2564 struct kvm_vcpu *v;
684851a1
TY		 2565 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2566 if (v == vcpu) {
55cd8e5a 2567 data = r;
684851a1
TY		 2568 break;
2569 }
2570 }
55cd8e5a
GN		 2571 break;
2572 }
10388a07
GN		 2573 case HV_X64_MSR_EOI:
2574 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2575 case HV_X64_MSR_ICR:
2576 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2577 case HV_X64_MSR_TPR:
2578 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2579 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2580 data = vcpu->arch.hv_vapic;
2581 break;
55cd8e5a 2582 default:
a737f256 2583 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2584 return 1;
2585 }
2586 *pdata = data;
2587 return 0;
2588}
2589
890ca9ae
HY		 2590int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2591{
2592 u64 data;
2593
2594 switch (msr) {
890ca9ae 2595 case MSR_IA32_PLATFORM_ID:
15c4a640 2596 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2597 case MSR_IA32_DEBUGCTLMSR:
2598 case MSR_IA32_LASTBRANCHFROMIP:
2599 case MSR_IA32_LASTBRANCHTOIP:
2600 case MSR_IA32_LASTINTFROMIP:
2601 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2602 case MSR_K8_SYSCFG:
2603 case MSR_K7_HWCR:
61a6bd67 2604 case MSR_VM_HSAVE_PA:
9e699624 2605 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2606 case MSR_K7_EVNTSEL1:
2607 case MSR_K7_EVNTSEL2:
2608 case MSR_K7_EVNTSEL3:
1f3ee616 2609 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2610 case MSR_K7_PERFCTR1:
2611 case MSR_K7_PERFCTR2:
2612 case MSR_K7_PERFCTR3:
1fdbd48c 2613 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2614 case MSR_AMD64_NB_CFG:
f7c6d140 2615 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2616 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2617 data = 0;
2618 break;
5753785f
GN		 2619 case MSR_P6_PERFCTR0:
2620 case MSR_P6_PERFCTR1:
2621 case MSR_P6_EVNTSEL0:
2622 case MSR_P6_EVNTSEL1:
2623 if (kvm_pmu_msr(vcpu, msr))
2624 return kvm_pmu_get_msr(vcpu, msr, pdata);
2625 data = 0;
2626 break;
742bc670
MT		 2627 case MSR_IA32_UCODE_REV:
2628 data = 0x100000000ULL;
2629 break;
9ba075a6
AK		 2630 case MSR_MTRRcap:
2631 data = 0x500 | KVM_NR_VAR_MTRR;
2632 break;
2633 case 0x200 ... 0x2ff:
2634 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2635 case 0xcd: /* fsb frequency */
2636 data = 3;
2637 break;
7b914098
JS		 2638 /*
2639 * MSR_EBC_FREQUENCY_ID
2640 * Conservative value valid for even the basic CPU models.
2641 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2642 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2643 * and 266MHz for model 3, or 4. Set Core Clock
2644 * Frequency to System Bus Frequency Ratio to 1 (bits
2645 * 31:24) even though these are only valid for CPU
2646 * models > 2, however guests may end up dividing or
2647 * multiplying by zero otherwise.
2648 */
2649 case MSR_EBC_FREQUENCY_ID:
2650 data = 1 << 24;
2651 break;
15c4a640
CO		 2652 case MSR_IA32_APICBASE:
2653 data = kvm_get_apic_base(vcpu);
2654 break;
0105d1a5
GN		 2655 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2656 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2657 break;
a3e06bbe
LJ		 2658 case MSR_IA32_TSCDEADLINE:
2659 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2660 break;
ba904635
WA		 2661 case MSR_IA32_TSC_ADJUST:
2662 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2663 break;
15c4a640 2664 case MSR_IA32_MISC_ENABLE:
ad312c7c 2665 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2666 break;
847f0ad8
AG		 2667 case MSR_IA32_PERF_STATUS:
2668 /* TSC increment by tick */
2669 data = 1000ULL;
2670 /* CPU multiplier */
2671 data |= (((uint64_t)4ULL) << 40);
2672 break;
15c4a640 2673 case MSR_EFER:
f6801dff 2674 data = vcpu->arch.efer;
15c4a640 2675 break;
18068523 2676 case MSR_KVM_WALL_CLOCK:
11c6bffa 2677 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2678 data = vcpu->kvm->arch.wall_clock;
2679 break;
2680 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2681 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2682 data = vcpu->arch.time;
2683 break;
344d9588
GN		 2684 case MSR_KVM_ASYNC_PF_EN:
2685 data = vcpu->arch.apf.msr_val;
2686 break;
c9aaa895
GC		 2687 case MSR_KVM_STEAL_TIME:
2688 data = vcpu->arch.st.msr_val;
2689 break;
1d92128f
MT		 2690 case MSR_KVM_PV_EOI_EN:
2691 data = vcpu->arch.pv_eoi.msr_val;
2692 break;
890ca9ae
HY		 2693 case MSR_IA32_P5_MC_ADDR:
2694 case MSR_IA32_P5_MC_TYPE:
2695 case MSR_IA32_MCG_CAP:
2696 case MSR_IA32_MCG_CTL:
2697 case MSR_IA32_MCG_STATUS:
81760dcc 2698 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2699 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2700 case MSR_K7_CLK_CTL:
2701 /*
2702 * Provide expected ramp-up count for K7. All other
2703 * are set to zero, indicating minimum divisors for
2704 * every field.
2705 *
2706 * This prevents guest kernels on AMD host with CPU
2707 * type 6, model 8 and higher from exploding due to
2708 * the rdmsr failing.
2709 */
2710 data = 0x20000000;
2711 break;
55cd8e5a
GN		 2712 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2713 if (kvm_hv_msr_partition_wide(msr)) {
2714 int r;
2715 mutex_lock(&vcpu->kvm->lock);
2716 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2717 mutex_unlock(&vcpu->kvm->lock);
2718 return r;
2719 } else
2720 return get_msr_hyperv(vcpu, msr, pdata);
2721 break;
91c9c3ed 2722 case MSR_IA32_BBL_CR_CTL3:
2723 /* This legacy MSR exists but isn't fully documented in current
2724 * silicon. It is however accessed by winxp in very narrow
2725 * scenarios where it sets bit #19, itself documented as
2726 * a "reserved" bit. Best effort attempt to source coherent
2727 * read data here should the balance of the register be
2728 * interpreted by the guest:
2729 *
2730 * L2 cache control register 3: 64GB range, 256KB size,
2731 * enabled, latency 0x1, configured
2732 */
2733 data = 0xbe702111;
2734 break;
2b036c6b
BO		 2735 case MSR_AMD64_OSVW_ID_LENGTH:
2736 if (!guest_cpuid_has_osvw(vcpu))
2737 return 1;
2738 data = vcpu->arch.osvw.length;
2739 break;
2740 case MSR_AMD64_OSVW_STATUS:
2741 if (!guest_cpuid_has_osvw(vcpu))
2742 return 1;
2743 data = vcpu->arch.osvw.status;
2744 break;
15c4a640 2745 default:
f5132b01
GN		 2746 if (kvm_pmu_msr(vcpu, msr))
2747 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2748 if (!ignore_msrs) {
a737f256 2749 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2750 return 1;
2751 } else {
a737f256 2752 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2753 data = 0;
2754 }
2755 break;
15c4a640
CO		 2756 }
2757 *pdata = data;
2758 return 0;
2759}
2760EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2761
313a3dc7
CO		 2762/*
2763 * Read or write a bunch of msrs. All parameters are kernel addresses.
2764 *
2765 * @return number of msrs set successfully.
2766 */
2767static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2768 struct kvm_msr_entry *entries,
2769 int (*do_msr)(struct kvm_vcpu *vcpu,
2770 unsigned index, u64 *data))
2771{
f656ce01 2772 int i, idx;
313a3dc7 2773
f656ce01 2774 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2775 for (i = 0; i < msrs->nmsrs; ++i)
2776 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2777 break;
f656ce01 2778 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2779
313a3dc7
CO		 2780 return i;
2781}
2782
2783/*
2784 * Read or write a bunch of msrs. Parameters are user addresses.
2785 *
2786 * @return number of msrs set successfully.
2787 */
2788static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2789 int (*do_msr)(struct kvm_vcpu *vcpu,
2790 unsigned index, u64 *data),
2791 int writeback)
2792{
2793 struct kvm_msrs msrs;
2794 struct kvm_msr_entry *entries;
2795 int r, n;
2796 unsigned size;
2797
2798 r = -EFAULT;
2799 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2800 goto out;
2801
2802 r = -E2BIG;
2803 if (msrs.nmsrs >= MAX_IO_MSRS)
2804 goto out;
2805
313a3dc7 2806 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2807 entries = memdup_user(user_msrs->entries, size);
2808 if (IS_ERR(entries)) {
2809 r = PTR_ERR(entries);
313a3dc7 2810 goto out;
ff5c2c03 2811 }
313a3dc7
CO		 2812
2813 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2814 if (r < 0)
2815 goto out_free;
2816
2817 r = -EFAULT;
2818 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2819 goto out_free;
2820
2821 r = n;
2822
2823out_free:
7a73c028 2824 kfree(entries);
313a3dc7
CO		 2825out:
2826 return r;
2827}
2828
784aa3d7 2829int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2830{
2831 int r;
2832
2833 switch (ext) {
2834 case KVM_CAP_IRQCHIP:
2835 case KVM_CAP_HLT:
2836 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2837 case KVM_CAP_SET_TSS_ADDR:
07716717 2838 case KVM_CAP_EXT_CPUID:
9c15bb1d 2839 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2840 case KVM_CAP_CLOCKSOURCE:
7837699f 2841 case KVM_CAP_PIT:
a28e4f5a 2842 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2843 case KVM_CAP_MP_STATE:
ed848624 2844 case KVM_CAP_SYNC_MMU:
a355c85c 2845 case KVM_CAP_USER_NMI:
52d939a0 2846 case KVM_CAP_REINJECT_CONTROL:
4925663a 2847 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2848 case KVM_CAP_IOEVENTFD:
f848a5a8 2849 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2850 case KVM_CAP_PIT2:
e9f42757 2851 case KVM_CAP_PIT_STATE2:
b927a3ce 2852 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2853 case KVM_CAP_XEN_HVM:
afbcf7ab 2854 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2855 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2856 case KVM_CAP_HYPERV:
10388a07 2857 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2858 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2859 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2860 case KVM_CAP_DEBUGREGS:
d2be1651 2861 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2862 case KVM_CAP_XSAVE:
344d9588 2863 case KVM_CAP_ASYNC_PF:
92a1f12d 2864 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2865 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2866 case KVM_CAP_READONLY_MEM:
5f66b620 2867 case KVM_CAP_HYPERV_TIME:
100943c5 2868 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2869 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2870 case KVM_CAP_ENABLE_CAP_VM:
2871 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2872#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2873 case KVM_CAP_ASSIGN_DEV_IRQ:
2874 case KVM_CAP_PCI_2_3:
2875#endif
018d00d2
ZX		 2876 r = 1;
2877 break;
542472b5
LV		 2878 case KVM_CAP_COALESCED_MMIO:
2879 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2880 break;
774ead3a
AK		 2881 case KVM_CAP_VAPIC:
2882 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2883 break;
f725230a 2884 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2885 r = KVM_SOFT_MAX_VCPUS;
2886 break;
2887 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2888 r = KVM_MAX_VCPUS;
2889 break;
a988b910 2890 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2891 r = KVM_USER_MEM_SLOTS;
a988b910 2892 break;
a68a6a72
MT		 2893 case KVM_CAP_PV_MMU: /* obsolete */
2894 r = 0;
2f333bcb 2895 break;
4cee4b72 2896#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2897 case KVM_CAP_IOMMU:
a1b60c1c 2898 r = iommu_present(&pci_bus_type);
62c476c7 2899 break;
4cee4b72 2900#endif
890ca9ae
HY		 2901 case KVM_CAP_MCE:
2902 r = KVM_MAX_MCE_BANKS;
2903 break;
2d5b5a66
SY		 2904 case KVM_CAP_XCRS:
2905 r = cpu_has_xsave;
2906 break;
92a1f12d
JR		 2907 case KVM_CAP_TSC_CONTROL:
2908 r = kvm_has_tsc_control;
2909 break;
018d00d2
ZX		 2910 default:
2911 r = 0;
2912 break;
2913 }
2914 return r;
2915
2916}
2917
043405e1
CO		 2918long kvm_arch_dev_ioctl(struct file *filp,
2919 unsigned int ioctl, unsigned long arg)
2920{
2921 void __user *argp = (void __user *)arg;
2922 long r;
2923
2924 switch (ioctl) {
2925 case KVM_GET_MSR_INDEX_LIST: {
2926 struct kvm_msr_list __user *user_msr_list = argp;
2927 struct kvm_msr_list msr_list;
2928 unsigned n;
2929
2930 r = -EFAULT;
2931 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2932 goto out;
2933 n = msr_list.nmsrs;
62ef68bb 2934 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2935 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2936 goto out;
2937 r = -E2BIG;
e125e7b6 2938 if (n < msr_list.nmsrs)
043405e1
CO		 2939 goto out;
2940 r = -EFAULT;
2941 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2942 num_msrs_to_save * sizeof(u32)))
2943 goto out;
e125e7b6 2944 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2945 &emulated_msrs,
62ef68bb 2946 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2947 goto out;
2948 r = 0;
2949 break;
2950 }
9c15bb1d
BP		 2951 case KVM_GET_SUPPORTED_CPUID:
2952 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2953 struct kvm_cpuid2 __user *cpuid_arg = argp;
2954 struct kvm_cpuid2 cpuid;
2955
2956 r = -EFAULT;
2957 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2958 goto out;
9c15bb1d
BP		 2959
2960 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2961 ioctl);
674eea0f
AK		 2962 if (r)
2963 goto out;
2964
2965 r = -EFAULT;
2966 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2967 goto out;
2968 r = 0;
2969 break;
2970 }
890ca9ae
HY		 2971 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2972 u64 mce_cap;
2973
2974 mce_cap = KVM_MCE_CAP_SUPPORTED;
2975 r = -EFAULT;
2976 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2977 goto out;
2978 r = 0;
2979 break;
2980 }
043405e1
CO		 2981 default:
2982 r = -EINVAL;
2983 }
2984out:
2985 return r;
2986}
2987
f5f48ee1
SY		 2988static void wbinvd_ipi(void *garbage)
2989{
2990 wbinvd();
2991}
2992
2993static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2994{
e0f0bbc5 2995 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2996}
2997
313a3dc7
CO		 2998void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2999{
f5f48ee1
SY		 3000 /* Address WBINVD may be executed by guest */
3001 if (need_emulate_wbinvd(vcpu)) {
3002 if (kvm_x86_ops->has_wbinvd_exit())
3003 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3004 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3005 smp_call_function_single(vcpu->cpu,
3006 wbinvd_ipi, NULL, 1);
3007 }
3008
313a3dc7 3009 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3010
0dd6a6ed
ZA		 3011 /* Apply any externally detected TSC adjustments (due to suspend) */
3012 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3013 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3014 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3015 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3016 }
8f6055cb 3017
48434c20 3018 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 3019 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3020 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3021 if (tsc_delta < 0)
3022 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 3023 if (check_tsc_unstable()) {
b183aa58
ZA		 3024 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
3025 vcpu->arch.last_guest_tsc);
3026 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 3027 vcpu->arch.tsc_catchup = 1;
c285545f 3028 }
d98d07ca
MT		 3029 /*
3030 * On a host with synchronized TSC, there is no need to update
3031 * kvmclock on vcpu->cpu migration
3032 */
3033 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3034 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 3035 if (vcpu->cpu != cpu)
3036 kvm_migrate_timers(vcpu);
e48672fa 3037 vcpu->cpu = cpu;
6b7d7e76 3038 }
c9aaa895
GC		 3039
3040 accumulate_steal_time(vcpu);
3041 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3042}
3043
3044void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3045{
02daab21 3046 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 3047 kvm_put_guest_fpu(vcpu);
6f526ec5 3048 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 3049}
3050
313a3dc7
CO		 3051static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3052 struct kvm_lapic_state *s)
3053{
5a71785d 3054 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 3055 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 3056
3057 return 0;
3058}
3059
3060static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3061 struct kvm_lapic_state *s)
3062{
64eb0620 3063 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 3064 update_cr8_intercept(vcpu);
313a3dc7
CO		 3065
3066 return 0;
3067}
3068
f77bc6a4
ZX		 3069static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3070 struct kvm_interrupt *irq)
3071{
02cdb50f 3072 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3073 return -EINVAL;
3074 if (irqchip_in_kernel(vcpu->kvm))
3075 return -ENXIO;
f77bc6a4 3076
66fd3f7f 3077 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3078 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3079
f77bc6a4
ZX		 3080 return 0;
3081}
3082
c4abb7c9
JK		 3083static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3084{
c4abb7c9 3085 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3086
3087 return 0;
3088}
3089
b209749f
AK		 3090static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3091 struct kvm_tpr_access_ctl *tac)
3092{
3093 if (tac->flags)
3094 return -EINVAL;
3095 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3096 return 0;
3097}
3098
890ca9ae
HY		 3099static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3100 u64 mcg_cap)
3101{
3102 int r;
3103 unsigned bank_num = mcg_cap & 0xff, bank;
3104
3105 r = -EINVAL;
a9e38c3e 3106 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3107 goto out;
3108 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3109 goto out;
3110 r = 0;
3111 vcpu->arch.mcg_cap = mcg_cap;
3112 /* Init IA32_MCG_CTL to all 1s */
3113 if (mcg_cap & MCG_CTL_P)
3114 vcpu->arch.mcg_ctl = ~(u64)0;
3115 /* Init IA32_MCi_CTL to all 1s */
3116 for (bank = 0; bank < bank_num; bank++)
3117 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3118out:
3119 return r;
3120}
3121
3122static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3123 struct kvm_x86_mce *mce)
3124{
3125 u64 mcg_cap = vcpu->arch.mcg_cap;
3126 unsigned bank_num = mcg_cap & 0xff;
3127 u64 *banks = vcpu->arch.mce_banks;
3128
3129 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3130 return -EINVAL;
3131 /*
3132 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3133 * reporting is disabled
3134 */
3135 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3136 vcpu->arch.mcg_ctl != ~(u64)0)
3137 return 0;
3138 banks += 4 * mce->bank;
3139 /*
3140 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3141 * reporting is disabled for the bank
3142 */
3143 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3144 return 0;
3145 if (mce->status & MCI_STATUS_UC) {
3146 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3147 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3148 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3149 return 0;
3150 }
3151 if (banks[1] & MCI_STATUS_VAL)
3152 mce->status |= MCI_STATUS_OVER;
3153 banks[2] = mce->addr;
3154 banks[3] = mce->misc;
3155 vcpu->arch.mcg_status = mce->mcg_status;
3156 banks[1] = mce->status;
3157 kvm_queue_exception(vcpu, MC_VECTOR);
3158 } else if (!(banks[1] & MCI_STATUS_VAL)
3159 || !(banks[1] & MCI_STATUS_UC)) {
3160 if (banks[1] & MCI_STATUS_VAL)
3161 mce->status |= MCI_STATUS_OVER;
3162 banks[2] = mce->addr;
3163 banks[3] = mce->misc;
3164 banks[1] = mce->status;
3165 } else
3166 banks[1] |= MCI_STATUS_OVER;
3167 return 0;
3168}
3169
3cfc3092
JK		 3170static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3171 struct kvm_vcpu_events *events)
3172{
7460fb4a 3173 process_nmi(vcpu);
03b82a30
JK		 3174 events->exception.injected =
3175 vcpu->arch.exception.pending &&
3176 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3177 events->exception.nr = vcpu->arch.exception.nr;
3178 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3179 events->exception.pad = 0;
3cfc3092
JK		 3180 events->exception.error_code = vcpu->arch.exception.error_code;
3181
03b82a30
JK		 3182 events->interrupt.injected =
3183 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3184 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3185 events->interrupt.soft = 0;
37ccdcbe 3186 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3187
3188 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3189 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3190 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3191 events->nmi.pad = 0;
3cfc3092 3192
66450a21 3193 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3194
dab4b911 3195 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3196 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3197 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3198}
3199
3200static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3201 struct kvm_vcpu_events *events)
3202{
dab4b911 3203 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3204 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3205 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3206 return -EINVAL;
3207
7460fb4a 3208 process_nmi(vcpu);
3cfc3092
JK		 3209 vcpu->arch.exception.pending = events->exception.injected;
3210 vcpu->arch.exception.nr = events->exception.nr;
3211 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3212 vcpu->arch.exception.error_code = events->exception.error_code;
3213
3214 vcpu->arch.interrupt.pending = events->interrupt.injected;
3215 vcpu->arch.interrupt.nr = events->interrupt.nr;
3216 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3217 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3218 kvm_x86_ops->set_interrupt_shadow(vcpu,
3219 events->interrupt.shadow);
3cfc3092
JK		 3220
3221 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3222 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3223 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3224 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3225
66450a21
JK		 3226 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3227 kvm_vcpu_has_lapic(vcpu))
3228 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3229
3842d135
AK		 3230 kvm_make_request(KVM_REQ_EVENT, vcpu);
3231
3cfc3092
JK		 3232 return 0;
3233}
3234
a1efbe77
JK		 3235static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3236 struct kvm_debugregs *dbgregs)
3237{
73aaf249
JK		 3238 unsigned long val;
3239
a1efbe77 3240 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3241 kvm_get_dr(vcpu, 6, &val);
73aaf249 3242 dbgregs->dr6 = val;
a1efbe77
JK		 3243 dbgregs->dr7 = vcpu->arch.dr7;
3244 dbgregs->flags = 0;
97e69aa6 3245 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3246}
3247
3248static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3249 struct kvm_debugregs *dbgregs)
3250{
3251 if (dbgregs->flags)
3252 return -EINVAL;
3253
a1efbe77 3254 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3255 kvm_update_dr0123(vcpu);
a1efbe77 3256 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3257 kvm_update_dr6(vcpu);
a1efbe77 3258 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3259 kvm_update_dr7(vcpu);
a1efbe77 3260
a1efbe77
JK		 3261 return 0;
3262}
3263
df1daba7
PB		 3264#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3265
3266static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3267{
3268 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3269 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3270 u64 valid;
3271
3272 /*
3273 * Copy legacy XSAVE area, to avoid complications with CPUID
3274 * leaves 0 and 1 in the loop below.
3275 */
3276 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3277
3278 /* Set XSTATE_BV */
3279 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3280
3281 /*
3282 * Copy each region from the possibly compacted offset to the
3283 * non-compacted offset.
3284 */
3285 valid = xstate_bv & ~XSTATE_FPSSE;
3286 while (valid) {
3287 u64 feature = valid & -valid;
3288 int index = fls64(feature) - 1;
3289 void *src = get_xsave_addr(xsave, feature);
3290
3291 if (src) {
3292 u32 size, offset, ecx, edx;
3293 cpuid_count(XSTATE_CPUID, index,
3294 &size, &offset, &ecx, &edx);
3295 memcpy(dest + offset, src, size);
3296 }
3297
3298 valid -= feature;
3299 }
3300}
3301
3302static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3303{
3304 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3305 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3306 u64 valid;
3307
3308 /*
3309 * Copy legacy XSAVE area, to avoid complications with CPUID
3310 * leaves 0 and 1 in the loop below.
3311 */
3312 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3313
3314 /* Set XSTATE_BV and possibly XCOMP_BV. */
3315 xsave->xsave_hdr.xstate_bv = xstate_bv;
3316 if (cpu_has_xsaves)
3317 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3318
3319 /*
3320 * Copy each region from the non-compacted offset to the
3321 * possibly compacted offset.
3322 */
3323 valid = xstate_bv & ~XSTATE_FPSSE;
3324 while (valid) {
3325 u64 feature = valid & -valid;
3326 int index = fls64(feature) - 1;
3327 void *dest = get_xsave_addr(xsave, feature);
3328
3329 if (dest) {
3330 u32 size, offset, ecx, edx;
3331 cpuid_count(XSTATE_CPUID, index,
3332 &size, &offset, &ecx, &edx);
3333 memcpy(dest, src + offset, size);
3334 } else
3335 WARN_ON_ONCE(1);
3336
3337 valid -= feature;
3338 }
3339}
3340
2d5b5a66
SY		 3341static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3342 struct kvm_xsave *guest_xsave)
3343{
4344ee98 3344 if (cpu_has_xsave) {
df1daba7
PB		 3345 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3346 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3347 } else {
2d5b5a66
SY		 3348 memcpy(guest_xsave->region,
3349 &vcpu->arch.guest_fpu.state->fxsave,
3350 sizeof(struct i387_fxsave_struct));
3351 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3352 XSTATE_FPSSE;
3353 }
3354}
3355
3356static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3357 struct kvm_xsave *guest_xsave)
3358{
3359 u64 xstate_bv =
3360 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3361
d7876f1b
PB		 3362 if (cpu_has_xsave) {
3363 /*
3364 * Here we allow setting states that are not present in
3365 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3366 * with old userspace.
3367 */
4ff41732 3368 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3369 return -EINVAL;
df1daba7 3370 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3371 } else {
2d5b5a66
SY		 3372 if (xstate_bv & ~XSTATE_FPSSE)
3373 return -EINVAL;
3374 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3375 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3376 }
3377 return 0;
3378}
3379
3380static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3381 struct kvm_xcrs *guest_xcrs)
3382{
3383 if (!cpu_has_xsave) {
3384 guest_xcrs->nr_xcrs = 0;
3385 return;
3386 }
3387
3388 guest_xcrs->nr_xcrs = 1;
3389 guest_xcrs->flags = 0;
3390 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3391 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3392}
3393
3394static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3395 struct kvm_xcrs *guest_xcrs)
3396{
3397 int i, r = 0;
3398
3399 if (!cpu_has_xsave)
3400 return -EINVAL;
3401
3402 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3403 return -EINVAL;
3404
3405 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3406 /* Only support XCR0 currently */
c67a04cb 3407 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3408 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3409 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3410 break;
3411 }
3412 if (r)
3413 r = -EINVAL;
3414 return r;
3415}
3416
1c0b28c2
EM		 3417/*
3418 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3419 * stopped by the hypervisor. This function will be called from the host only.
3420 * EINVAL is returned when the host attempts to set the flag for a guest that
3421 * does not support pv clocks.
3422 */
3423static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3424{
0b79459b 3425 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3426 return -EINVAL;
51d59c6b 3427 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3428 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3429 return 0;
3430}
3431
313a3dc7
CO		 3432long kvm_arch_vcpu_ioctl(struct file *filp,
3433 unsigned int ioctl, unsigned long arg)
3434{
3435 struct kvm_vcpu *vcpu = filp->private_data;
3436 void __user *argp = (void __user *)arg;
3437 int r;
d1ac91d8
AK		 3438 union {
3439 struct kvm_lapic_state *lapic;
3440 struct kvm_xsave *xsave;
3441 struct kvm_xcrs *xcrs;
3442 void *buffer;
3443 } u;
3444
3445 u.buffer = NULL;
313a3dc7
CO		 3446 switch (ioctl) {
3447 case KVM_GET_LAPIC: {
2204ae3c
MT		 3448 r = -EINVAL;
3449 if (!vcpu->arch.apic)
3450 goto out;
d1ac91d8 3451 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3452
b772ff36 3453 r = -ENOMEM;
d1ac91d8 3454 if (!u.lapic)
b772ff36 3455 goto out;
d1ac91d8 3456 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3457 if (r)
3458 goto out;
3459 r = -EFAULT;
d1ac91d8 3460 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3461 goto out;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_SET_LAPIC: {
2204ae3c
MT		 3466 r = -EINVAL;
3467 if (!vcpu->arch.apic)
3468 goto out;
ff5c2c03 3469 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3470 if (IS_ERR(u.lapic))
3471 return PTR_ERR(u.lapic);
ff5c2c03 3472
d1ac91d8 3473 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3474 break;
3475 }
f77bc6a4
ZX		 3476 case KVM_INTERRUPT: {
3477 struct kvm_interrupt irq;
3478
3479 r = -EFAULT;
3480 if (copy_from_user(&irq, argp, sizeof irq))
3481 goto out;
3482 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3483 break;
3484 }
c4abb7c9
JK		 3485 case KVM_NMI: {
3486 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3487 break;
3488 }
313a3dc7
CO		 3489 case KVM_SET_CPUID: {
3490 struct kvm_cpuid __user *cpuid_arg = argp;
3491 struct kvm_cpuid cpuid;
3492
3493 r = -EFAULT;
3494 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3495 goto out;
3496 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3497 break;
3498 }
07716717
DK		 3499 case KVM_SET_CPUID2: {
3500 struct kvm_cpuid2 __user *cpuid_arg = argp;
3501 struct kvm_cpuid2 cpuid;
3502
3503 r = -EFAULT;
3504 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3505 goto out;
3506 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3507 cpuid_arg->entries);
07716717
DK		 3508 break;
3509 }
3510 case KVM_GET_CPUID2: {
3511 struct kvm_cpuid2 __user *cpuid_arg = argp;
3512 struct kvm_cpuid2 cpuid;
3513
3514 r = -EFAULT;
3515 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3516 goto out;
3517 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3518 cpuid_arg->entries);
07716717
DK		 3519 if (r)
3520 goto out;
3521 r = -EFAULT;
3522 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3523 goto out;
3524 r = 0;
3525 break;
3526 }
313a3dc7
CO		 3527 case KVM_GET_MSRS:
3528 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3529 break;
3530 case KVM_SET_MSRS:
3531 r = msr_io(vcpu, argp, do_set_msr, 0);
3532 break;
b209749f
AK		 3533 case KVM_TPR_ACCESS_REPORTING: {
3534 struct kvm_tpr_access_ctl tac;
3535
3536 r = -EFAULT;
3537 if (copy_from_user(&tac, argp, sizeof tac))
3538 goto out;
3539 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3540 if (r)
3541 goto out;
3542 r = -EFAULT;
3543 if (copy_to_user(argp, &tac, sizeof tac))
3544 goto out;
3545 r = 0;
3546 break;
3547 };
b93463aa
AK		 3548 case KVM_SET_VAPIC_ADDR: {
3549 struct kvm_vapic_addr va;
3550
3551 r = -EINVAL;
3552 if (!irqchip_in_kernel(vcpu->kvm))
3553 goto out;
3554 r = -EFAULT;
3555 if (copy_from_user(&va, argp, sizeof va))
3556 goto out;
fda4e2e8 3557 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3558 break;
3559 }
890ca9ae
HY		 3560 case KVM_X86_SETUP_MCE: {
3561 u64 mcg_cap;
3562
3563 r = -EFAULT;
3564 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3565 goto out;
3566 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3567 break;
3568 }
3569 case KVM_X86_SET_MCE: {
3570 struct kvm_x86_mce mce;
3571
3572 r = -EFAULT;
3573 if (copy_from_user(&mce, argp, sizeof mce))
3574 goto out;
3575 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3576 break;
3577 }
3cfc3092
JK		 3578 case KVM_GET_VCPU_EVENTS: {
3579 struct kvm_vcpu_events events;
3580
3581 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3582
3583 r = -EFAULT;
3584 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3585 break;
3586 r = 0;
3587 break;
3588 }
3589 case KVM_SET_VCPU_EVENTS: {
3590 struct kvm_vcpu_events events;
3591
3592 r = -EFAULT;
3593 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3594 break;
3595
3596 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3597 break;
3598 }
a1efbe77
JK		 3599 case KVM_GET_DEBUGREGS: {
3600 struct kvm_debugregs dbgregs;
3601
3602 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3603
3604 r = -EFAULT;
3605 if (copy_to_user(argp, &dbgregs,
3606 sizeof(struct kvm_debugregs)))
3607 break;
3608 r = 0;
3609 break;
3610 }
3611 case KVM_SET_DEBUGREGS: {
3612 struct kvm_debugregs dbgregs;
3613
3614 r = -EFAULT;
3615 if (copy_from_user(&dbgregs, argp,
3616 sizeof(struct kvm_debugregs)))
3617 break;
3618
3619 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3620 break;
3621 }
2d5b5a66 3622 case KVM_GET_XSAVE: {
d1ac91d8 3623 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3624 r = -ENOMEM;
d1ac91d8 3625 if (!u.xsave)
2d5b5a66
SY		 3626 break;
3627
d1ac91d8 3628 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3629
3630 r = -EFAULT;
d1ac91d8 3631 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3632 break;
3633 r = 0;
3634 break;
3635 }
3636 case KVM_SET_XSAVE: {
ff5c2c03 3637 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3638 if (IS_ERR(u.xsave))
3639 return PTR_ERR(u.xsave);
2d5b5a66 3640
d1ac91d8 3641 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3642 break;
3643 }
3644 case KVM_GET_XCRS: {
d1ac91d8 3645 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3646 r = -ENOMEM;
d1ac91d8 3647 if (!u.xcrs)
2d5b5a66
SY		 3648 break;
3649
d1ac91d8 3650 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3651
3652 r = -EFAULT;
d1ac91d8 3653 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3654 sizeof(struct kvm_xcrs)))
3655 break;
3656 r = 0;
3657 break;
3658 }
3659 case KVM_SET_XCRS: {
ff5c2c03 3660 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3661 if (IS_ERR(u.xcrs))
3662 return PTR_ERR(u.xcrs);
2d5b5a66 3663
d1ac91d8 3664 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3665 break;
3666 }
92a1f12d
JR		 3667 case KVM_SET_TSC_KHZ: {
3668 u32 user_tsc_khz;
3669
3670 r = -EINVAL;
92a1f12d
JR		 3671 user_tsc_khz = (u32)arg;
3672
3673 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3674 goto out;
3675
cc578287
ZA		 3676 if (user_tsc_khz == 0)
3677 user_tsc_khz = tsc_khz;
3678
3679 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3680
3681 r = 0;
3682 goto out;
3683 }
3684 case KVM_GET_TSC_KHZ: {
cc578287 3685 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3686 goto out;
3687 }
1c0b28c2
EM		 3688 case KVM_KVMCLOCK_CTRL: {
3689 r = kvm_set_guest_paused(vcpu);
3690 goto out;
3691 }
313a3dc7
CO		 3692 default:
3693 r = -EINVAL;
3694 }
3695out:
d1ac91d8 3696 kfree(u.buffer);
313a3dc7
CO		 3697 return r;
3698}
3699
5b1c1493
CO		 3700int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3701{
3702 return VM_FAULT_SIGBUS;
3703}
3704
1fe779f8
CO		 3705static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3706{
3707 int ret;
3708
3709 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3710 return -EINVAL;
1fe779f8
CO		 3711 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3712 return ret;
3713}
3714
b927a3ce
SY		 3715static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3716 u64 ident_addr)
3717{
3718 kvm->arch.ept_identity_map_addr = ident_addr;
3719 return 0;
3720}
3721
1fe779f8
CO		 3722static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3723 u32 kvm_nr_mmu_pages)
3724{
3725 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3726 return -EINVAL;
3727
79fac95e 3728 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3729
3730 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3731 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3732
79fac95e 3733 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3734 return 0;
3735}
3736
3737static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3738{
39de71ec 3739 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3740}
3741
1fe779f8
CO		 3742static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3743{
3744 int r;
3745
3746 r = 0;
3747 switch (chip->chip_id) {
3748 case KVM_IRQCHIP_PIC_MASTER:
3749 memcpy(&chip->chip.pic,
3750 &pic_irqchip(kvm)->pics[0],
3751 sizeof(struct kvm_pic_state));
3752 break;
3753 case KVM_IRQCHIP_PIC_SLAVE:
3754 memcpy(&chip->chip.pic,
3755 &pic_irqchip(kvm)->pics[1],
3756 sizeof(struct kvm_pic_state));
3757 break;
3758 case KVM_IRQCHIP_IOAPIC:
eba0226b 3759 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3760 break;
3761 default:
3762 r = -EINVAL;
3763 break;
3764 }
3765 return r;
3766}
3767
3768static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3769{
3770 int r;
3771
3772 r = 0;
3773 switch (chip->chip_id) {
3774 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3775 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3776 memcpy(&pic_irqchip(kvm)->pics[0],
3777 &chip->chip.pic,
3778 sizeof(struct kvm_pic_state));
f4f51050 3779 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3780 break;
3781 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3782 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3783 memcpy(&pic_irqchip(kvm)->pics[1],
3784 &chip->chip.pic,
3785 sizeof(struct kvm_pic_state));
f4f51050 3786 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3787 break;
3788 case KVM_IRQCHIP_IOAPIC:
eba0226b 3789 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3790 break;
3791 default:
3792 r = -EINVAL;
3793 break;
3794 }
3795 kvm_pic_update_irq(pic_irqchip(kvm));
3796 return r;
3797}
3798
e0f63cb9
SY		 3799static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3800{
3801 int r = 0;
3802
894a9c55 3803 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3804 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3805 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3806 return r;
3807}
3808
3809static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3810{
3811 int r = 0;
3812
894a9c55 3813 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3814 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3815 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3816 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3817 return r;
3818}
3819
3820static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3821{
3822 int r = 0;
3823
3824 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3825 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3826 sizeof(ps->channels));
3827 ps->flags = kvm->arch.vpit->pit_state.flags;
3828 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3829 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3830 return r;
3831}
3832
3833static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3834{
3835 int r = 0, start = 0;
3836 u32 prev_legacy, cur_legacy;
3837 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3838 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3839 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3840 if (!prev_legacy && cur_legacy)
3841 start = 1;
3842 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3843 sizeof(kvm->arch.vpit->pit_state.channels));
3844 kvm->arch.vpit->pit_state.flags = ps->flags;
3845 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3846 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3847 return r;
3848}
3849
52d939a0
MT		 3850static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3851 struct kvm_reinject_control *control)
3852{
3853 if (!kvm->arch.vpit)
3854 return -ENXIO;
894a9c55 3855 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3856 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3857 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3858 return 0;
3859}
3860
95d4c16c 3861/**
60c34612
TY		 3862 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3863 * @kvm: kvm instance
3864 * @log: slot id and address to which we copy the log
95d4c16c 3865 *
e108ff2f
PB		 3866 * Steps 1-4 below provide general overview of dirty page logging. See
3867 * kvm_get_dirty_log_protect() function description for additional details.
3868 *
3869 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3870 * always flush the TLB (step 4) even if previous step failed and the dirty
3871 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3872 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3873 * writes will be marked dirty for next log read.
95d4c16c 3874 *
60c34612
TY		 3875 * 1. Take a snapshot of the bit and clear it if needed.
3876 * 2. Write protect the corresponding page.
e108ff2f
PB		 3877 * 3. Copy the snapshot to the userspace.
3878 * 4. Flush TLB's if needed.
5bb064dc 3879 */
60c34612 3880int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3881{
60c34612 3882 bool is_dirty = false;
e108ff2f 3883 int r;
5bb064dc 3884
79fac95e 3885 mutex_lock(&kvm->slots_lock);
5bb064dc 3886
88178fd4
KH		 3887 /*
3888 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3889 */
3890 if (kvm_x86_ops->flush_log_dirty)
3891 kvm_x86_ops->flush_log_dirty(kvm);
3892
e108ff2f 3893 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3894
3895 /*
3896 * All the TLBs can be flushed out of mmu lock, see the comments in
3897 * kvm_mmu_slot_remove_write_access().
3898 */
e108ff2f 3899 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3900 if (is_dirty)
3901 kvm_flush_remote_tlbs(kvm);
3902
79fac95e 3903 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3904 return r;
3905}
3906
aa2fbe6d
YZ		 3907int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3908 bool line_status)
23d43cf9
CD		 3909{
3910 if (!irqchip_in_kernel(kvm))
3911 return -ENXIO;
3912
3913 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3914 irq_event->irq, irq_event->level,
3915 line_status);
23d43cf9
CD		 3916 return 0;
3917}
3918
90de4a18
NA		 3919static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3920 struct kvm_enable_cap *cap)
3921{
3922 int r;
3923
3924 if (cap->flags)
3925 return -EINVAL;
3926
3927 switch (cap->cap) {
3928 case KVM_CAP_DISABLE_QUIRKS:
3929 kvm->arch.disabled_quirks = cap->args[0];
3930 r = 0;
3931 break;
3932 default:
3933 r = -EINVAL;
3934 break;
3935 }
3936 return r;
3937}
3938
1fe779f8
CO		 3939long kvm_arch_vm_ioctl(struct file *filp,
3940 unsigned int ioctl, unsigned long arg)
3941{
3942 struct kvm *kvm = filp->private_data;
3943 void __user *argp = (void __user *)arg;
367e1319 3944 int r = -ENOTTY;
f0d66275
DH		 3945 /*
3946 * This union makes it completely explicit to gcc-3.x
3947 * that these two variables' stack usage should be
3948 * combined, not added together.
3949 */
3950 union {
3951 struct kvm_pit_state ps;
e9f42757 3952 struct kvm_pit_state2 ps2;
c5ff41ce 3953 struct kvm_pit_config pit_config;
f0d66275 3954 } u;
1fe779f8
CO		 3955
3956 switch (ioctl) {
3957 case KVM_SET_TSS_ADDR:
3958 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3959 break;
b927a3ce
SY		 3960 case KVM_SET_IDENTITY_MAP_ADDR: {
3961 u64 ident_addr;
3962
3963 r = -EFAULT;
3964 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3965 goto out;
3966 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3967 break;
3968 }
1fe779f8
CO		 3969 case KVM_SET_NR_MMU_PAGES:
3970 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3971 break;
3972 case KVM_GET_NR_MMU_PAGES:
3973 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3974 break;
3ddea128
MT		 3975 case KVM_CREATE_IRQCHIP: {
3976 struct kvm_pic *vpic;
3977
3978 mutex_lock(&kvm->lock);
3979 r = -EEXIST;
3980 if (kvm->arch.vpic)
3981 goto create_irqchip_unlock;
3e515705
AK		 3982 r = -EINVAL;
3983 if (atomic_read(&kvm->online_vcpus))
3984 goto create_irqchip_unlock;
1fe779f8 3985 r = -ENOMEM;
3ddea128
MT		 3986 vpic = kvm_create_pic(kvm);
3987 if (vpic) {
1fe779f8
CO		 3988 r = kvm_ioapic_init(kvm);
3989 if (r) {
175504cd 3990 mutex_lock(&kvm->slots_lock);
72bb2fcd 3991 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3992 &vpic->dev_master);
3993 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3994 &vpic->dev_slave);
3995 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3996 &vpic->dev_eclr);
175504cd 3997 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3998 kfree(vpic);
3999 goto create_irqchip_unlock;
1fe779f8
CO		 4000 }
4001 } else
3ddea128
MT		 4002 goto create_irqchip_unlock;
4003 smp_wmb();
4004 kvm->arch.vpic = vpic;
4005 smp_wmb();
399ec807
AK		 4006 r = kvm_setup_default_irq_routing(kvm);
4007 if (r) {
175504cd 4008 mutex_lock(&kvm->slots_lock);
3ddea128 4009 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 4010 kvm_ioapic_destroy(kvm);
4011 kvm_destroy_pic(kvm);
3ddea128 4012 mutex_unlock(&kvm->irq_lock);
175504cd 4013 mutex_unlock(&kvm->slots_lock);
399ec807 4014 }
3ddea128
MT		 4015 create_irqchip_unlock:
4016 mutex_unlock(&kvm->lock);
1fe779f8 4017 break;
3ddea128 4018 }
7837699f 4019 case KVM_CREATE_PIT:
c5ff41ce
JK		 4020 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4021 goto create_pit;
4022 case KVM_CREATE_PIT2:
4023 r = -EFAULT;
4024 if (copy_from_user(&u.pit_config, argp,
4025 sizeof(struct kvm_pit_config)))
4026 goto out;
4027 create_pit:
79fac95e 4028 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 4029 r = -EEXIST;
4030 if (kvm->arch.vpit)
4031 goto create_pit_unlock;
7837699f 4032 r = -ENOMEM;
c5ff41ce 4033 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4034 if (kvm->arch.vpit)
4035 r = 0;
269e05e4 4036 create_pit_unlock:
79fac95e 4037 mutex_unlock(&kvm->slots_lock);
7837699f 4038 break;
1fe779f8
CO		 4039 case KVM_GET_IRQCHIP: {
4040 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4041 struct kvm_irqchip *chip;
1fe779f8 4042
ff5c2c03
SL		 4043 chip = memdup_user(argp, sizeof(*chip));
4044 if (IS_ERR(chip)) {
4045 r = PTR_ERR(chip);
1fe779f8 4046 goto out;
ff5c2c03
SL		 4047 }
4048
1fe779f8
CO		 4049 r = -ENXIO;
4050 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4051 goto get_irqchip_out;
4052 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4053 if (r)
f0d66275 4054 goto get_irqchip_out;
1fe779f8 4055 r = -EFAULT;
f0d66275
DH		 4056 if (copy_to_user(argp, chip, sizeof *chip))
4057 goto get_irqchip_out;
1fe779f8 4058 r = 0;
f0d66275
DH		 4059 get_irqchip_out:
4060 kfree(chip);
1fe779f8
CO		 4061 break;
4062 }
4063 case KVM_SET_IRQCHIP: {
4064 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4065 struct kvm_irqchip *chip;
1fe779f8 4066
ff5c2c03
SL		 4067 chip = memdup_user(argp, sizeof(*chip));
4068 if (IS_ERR(chip)) {
4069 r = PTR_ERR(chip);
1fe779f8 4070 goto out;
ff5c2c03
SL		 4071 }
4072
1fe779f8
CO		 4073 r = -ENXIO;
4074 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4075 goto set_irqchip_out;
4076 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4077 if (r)
f0d66275 4078 goto set_irqchip_out;
1fe779f8 4079 r = 0;
f0d66275
DH		 4080 set_irqchip_out:
4081 kfree(chip);
1fe779f8
CO		 4082 break;
4083 }
e0f63cb9 4084 case KVM_GET_PIT: {
e0f63cb9 4085 r = -EFAULT;
f0d66275 4086 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4087 goto out;
4088 r = -ENXIO;
4089 if (!kvm->arch.vpit)
4090 goto out;
f0d66275 4091 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4092 if (r)
4093 goto out;
4094 r = -EFAULT;
f0d66275 4095 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4096 goto out;
4097 r = 0;
4098 break;
4099 }
4100 case KVM_SET_PIT: {
e0f63cb9 4101 r = -EFAULT;
f0d66275 4102 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4103 goto out;
4104 r = -ENXIO;
4105 if (!kvm->arch.vpit)
4106 goto out;
f0d66275 4107 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4108 break;
4109 }
e9f42757
BK		 4110 case KVM_GET_PIT2: {
4111 r = -ENXIO;
4112 if (!kvm->arch.vpit)
4113 goto out;
4114 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4115 if (r)
4116 goto out;
4117 r = -EFAULT;
4118 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4119 goto out;
4120 r = 0;
4121 break;
4122 }
4123 case KVM_SET_PIT2: {
4124 r = -EFAULT;
4125 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4126 goto out;
4127 r = -ENXIO;
4128 if (!kvm->arch.vpit)
4129 goto out;
4130 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4131 break;
4132 }
52d939a0
MT		 4133 case KVM_REINJECT_CONTROL: {
4134 struct kvm_reinject_control control;
4135 r = -EFAULT;
4136 if (copy_from_user(&control, argp, sizeof(control)))
4137 goto out;
4138 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4139 break;
4140 }
ffde22ac
ES		 4141 case KVM_XEN_HVM_CONFIG: {
4142 r = -EFAULT;
4143 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4144 sizeof(struct kvm_xen_hvm_config)))
4145 goto out;
4146 r = -EINVAL;
4147 if (kvm->arch.xen_hvm_config.flags)
4148 goto out;
4149 r = 0;
4150 break;
4151 }
afbcf7ab 4152 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4153 struct kvm_clock_data user_ns;
4154 u64 now_ns;
4155 s64 delta;
4156
4157 r = -EFAULT;
4158 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4159 goto out;
4160
4161 r = -EINVAL;
4162 if (user_ns.flags)
4163 goto out;
4164
4165 r = 0;
395c6b0a 4166 local_irq_disable();
759379dd 4167 now_ns = get_kernel_ns();
afbcf7ab 4168 delta = user_ns.clock - now_ns;
395c6b0a 4169 local_irq_enable();
afbcf7ab 4170 kvm->arch.kvmclock_offset = delta;
2e762ff7 4171 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4172 break;
4173 }
4174 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4175 struct kvm_clock_data user_ns;
4176 u64 now_ns;
4177
395c6b0a 4178 local_irq_disable();
759379dd 4179 now_ns = get_kernel_ns();
afbcf7ab 4180 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4181 local_irq_enable();
afbcf7ab 4182 user_ns.flags = 0;
97e69aa6 4183 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4184
4185 r = -EFAULT;
4186 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4187 goto out;
4188 r = 0;
4189 break;
4190 }
90de4a18
NA		 4191 case KVM_ENABLE_CAP: {
4192 struct kvm_enable_cap cap;
afbcf7ab 4193
90de4a18
NA		 4194 r = -EFAULT;
4195 if (copy_from_user(&cap, argp, sizeof(cap)))
4196 goto out;
4197 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4198 break;
4199 }
1fe779f8 4200 default:
c274e03a 4201 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4202 }
4203out:
4204 return r;
4205}
4206
a16b043c 4207static void kvm_init_msr_list(void)
043405e1
CO		 4208{
4209 u32 dummy[2];
4210 unsigned i, j;
4211
62ef68bb 4212 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4213 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4214 continue;
93c4adc7
PB		 4215
4216 /*
4217 * Even MSRs that are valid in the host may not be exposed
4218 * to the guests in some cases. We could work around this
4219 * in VMX with the generic MSR save/load machinery, but it
4220 * is not really worthwhile since it will really only
4221 * happen with nested virtualization.
4222 */
4223 switch (msrs_to_save[i]) {
4224 case MSR_IA32_BNDCFGS:
4225 if (!kvm_x86_ops->mpx_supported())
4226 continue;
4227 break;
4228 default:
4229 break;
4230 }
4231
043405e1
CO		 4232 if (j < i)
4233 msrs_to_save[j] = msrs_to_save[i];
4234 j++;
4235 }
4236 num_msrs_to_save = j;
62ef68bb
PB		 4237
4238 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4239 switch (emulated_msrs[i]) {
4240 default:
4241 break;
4242 }
4243
4244 if (j < i)
4245 emulated_msrs[j] = emulated_msrs[i];
4246 j++;
4247 }
4248 num_emulated_msrs = j;
043405e1
CO		 4249}
4250
bda9020e
MT		 4251static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4252 const void *v)
bbd9b64e 4253{
70252a10
AK		 4254 int handled = 0;
4255 int n;
4256
4257 do {
4258 n = min(len, 8);
4259 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4260 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4261 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4262 break;
4263 handled += n;
4264 addr += n;
4265 len -= n;
4266 v += n;
4267 } while (len);
bbd9b64e 4268
70252a10 4269 return handled;
bbd9b64e
CO		 4270}
4271
bda9020e 4272static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4273{
70252a10
AK		 4274 int handled = 0;
4275 int n;
4276
4277 do {
4278 n = min(len, 8);
4279 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4280 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4281 addr, n, v))
4282 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4283 break;
4284 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4285 handled += n;
4286 addr += n;
4287 len -= n;
4288 v += n;
4289 } while (len);
bbd9b64e 4290
70252a10 4291 return handled;
bbd9b64e
CO		 4292}
4293
2dafc6c2
GN		 4294static void kvm_set_segment(struct kvm_vcpu *vcpu,
4295 struct kvm_segment *var, int seg)
4296{
4297 kvm_x86_ops->set_segment(vcpu, var, seg);
4298}
4299
4300void kvm_get_segment(struct kvm_vcpu *vcpu,
4301 struct kvm_segment *var, int seg)
4302{
4303 kvm_x86_ops->get_segment(vcpu, var, seg);
4304}
4305
54987b7a
PB		 4306gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4307 struct x86_exception *exception)
02f59dc9
JR		 4308{
4309 gpa_t t_gpa;
02f59dc9
JR		 4310
4311 BUG_ON(!mmu_is_nested(vcpu));
4312
4313 /* NPT walks are always user-walks */
4314 access |= PFERR_USER_MASK;
54987b7a 4315 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4316
4317 return t_gpa;
4318}
4319
ab9ae313
AK		 4320gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4321 struct x86_exception *exception)
1871c602
GN		 4322{
4323 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4324 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4325}
4326
ab9ae313
AK		 4327 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4328 struct x86_exception *exception)
1871c602
GN		 4329{
4330 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4331 access |= PFERR_FETCH_MASK;
ab9ae313 4332 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4333}
4334
ab9ae313
AK		 4335gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4336 struct x86_exception *exception)
1871c602
GN		 4337{
4338 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4339 access |= PFERR_WRITE_MASK;
ab9ae313 4340 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4341}
4342
4343/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4344gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4345 struct x86_exception *exception)
1871c602 4346{
ab9ae313 4347 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4348}
4349
4350static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4351 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4352 struct x86_exception *exception)
bbd9b64e
CO		 4353{
4354 void *data = val;
10589a46 4355 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4356
4357 while (bytes) {
14dfe855 4358 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4359 exception);
bbd9b64e 4360 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4361 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4362 int ret;
4363
bcc55cba 4364 if (gpa == UNMAPPED_GVA)
ab9ae313 4365 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4366 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4367 offset, toread);
10589a46 4368 if (ret < 0) {
c3cd7ffa 4369 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4370 goto out;
4371 }
bbd9b64e 4372
77c2002e
IE		 4373 bytes -= toread;
4374 data += toread;
4375 addr += toread;
bbd9b64e 4376 }
10589a46 4377out:
10589a46 4378 return r;
bbd9b64e 4379}
77c2002e 4380
1871c602 4381/* used for instruction fetching */
0f65dd70
AK		 4382static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4383 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4384 struct x86_exception *exception)
1871c602 4385{
0f65dd70 4386 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4387 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4388 unsigned offset;
4389 int ret;
0f65dd70 4390
44583cba
PB		 4391 /* Inline kvm_read_guest_virt_helper for speed. */
4392 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4393 exception);
4394 if (unlikely(gpa == UNMAPPED_GVA))
4395 return X86EMUL_PROPAGATE_FAULT;
4396
4397 offset = addr & (PAGE_SIZE-1);
4398 if (WARN_ON(offset + bytes > PAGE_SIZE))
4399 bytes = (unsigned)PAGE_SIZE - offset;
4400 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4401 offset, bytes);
4402 if (unlikely(ret < 0))
4403 return X86EMUL_IO_NEEDED;
4404
4405 return X86EMUL_CONTINUE;
1871c602
GN		 4406}
4407
064aea77 4408int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4409 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4410 struct x86_exception *exception)
1871c602 4411{
0f65dd70 4412 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4413 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4414
1871c602 4415 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4416 exception);
1871c602 4417}
064aea77 4418EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4419
0f65dd70
AK		 4420static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4421 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4422 struct x86_exception *exception)
1871c602 4423{
0f65dd70 4424 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4425 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4426}
4427
6a4d7550 4428int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4429 gva_t addr, void *val,
2dafc6c2 4430 unsigned int bytes,
bcc55cba 4431 struct x86_exception *exception)
77c2002e 4432{
0f65dd70 4433 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4434 void *data = val;
4435 int r = X86EMUL_CONTINUE;
4436
4437 while (bytes) {
14dfe855
JR		 4438 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4439 PFERR_WRITE_MASK,
ab9ae313 4440 exception);
77c2002e
IE		 4441 unsigned offset = addr & (PAGE_SIZE-1);
4442 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4443 int ret;
4444
bcc55cba 4445 if (gpa == UNMAPPED_GVA)
ab9ae313 4446 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4447 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4448 if (ret < 0) {
c3cd7ffa 4449 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4450 goto out;
4451 }
4452
4453 bytes -= towrite;
4454 data += towrite;
4455 addr += towrite;
4456 }
4457out:
4458 return r;
4459}
6a4d7550 4460EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4461
af7cc7d1
XG		 4462static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4463 gpa_t *gpa, struct x86_exception *exception,
4464 bool write)
4465{
97d64b78
AK		 4466 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4467 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4468
97d64b78 4469 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4470 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4471 vcpu->arch.access, access)) {
bebb106a
XG		 4472 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4473 (gva & (PAGE_SIZE - 1));
4f022648 4474 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4475 return 1;
4476 }
4477
af7cc7d1
XG		 4478 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4479
4480 if (*gpa == UNMAPPED_GVA)
4481 return -1;
4482
4483 /* For APIC access vmexit */
4484 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4485 return 1;
4486
4f022648
XG		 4487 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4488 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4489 return 1;
4f022648 4490 }
bebb106a 4491
af7cc7d1
XG		 4492 return 0;
4493}
4494
3200f405 4495int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4496 const void *val, int bytes)
bbd9b64e
CO		 4497{
4498 int ret;
4499
4500 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4501 if (ret < 0)
bbd9b64e 4502 return 0;
f57f2ef5 4503 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4504 return 1;
4505}
4506
77d197b2
XG		 4507struct read_write_emulator_ops {
4508 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4509 int bytes);
4510 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4511 void *val, int bytes);
4512 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4513 int bytes, void *val);
4514 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4515 void *val, int bytes);
4516 bool write;
4517};
4518
4519static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4520{
4521 if (vcpu->mmio_read_completed) {
77d197b2 4522 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4523 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4524 vcpu->mmio_read_completed = 0;
4525 return 1;
4526 }
4527
4528 return 0;
4529}
4530
4531static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4532 void *val, int bytes)
4533{
4534 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4535}
4536
4537static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4538 void *val, int bytes)
4539{
4540 return emulator_write_phys(vcpu, gpa, val, bytes);
4541}
4542
4543static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4544{
4545 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4546 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4547}
4548
4549static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4550 void *val, int bytes)
4551{
4552 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4553 return X86EMUL_IO_NEEDED;
4554}
4555
4556static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4557 void *val, int bytes)
4558{
f78146b0
AK		 4559 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4560
87da7e66 4561 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4562 return X86EMUL_CONTINUE;
4563}
4564
0fbe9b0b 4565static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4566 .read_write_prepare = read_prepare,
4567 .read_write_emulate = read_emulate,
4568 .read_write_mmio = vcpu_mmio_read,
4569 .read_write_exit_mmio = read_exit_mmio,
4570};
4571
0fbe9b0b 4572static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4573 .read_write_emulate = write_emulate,
4574 .read_write_mmio = write_mmio,
4575 .read_write_exit_mmio = write_exit_mmio,
4576 .write = true,
4577};
4578
22388a3c
XG		 4579static int emulator_read_write_onepage(unsigned long addr, void *val,
4580 unsigned int bytes,
4581 struct x86_exception *exception,
4582 struct kvm_vcpu *vcpu,
0fbe9b0b 4583 const struct read_write_emulator_ops *ops)
bbd9b64e 4584{
af7cc7d1
XG		 4585 gpa_t gpa;
4586 int handled, ret;
22388a3c 4587 bool write = ops->write;
f78146b0 4588 struct kvm_mmio_fragment *frag;
10589a46 4589
22388a3c 4590 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4591
af7cc7d1 4592 if (ret < 0)
bbd9b64e 4593 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4594
4595 /* For APIC access vmexit */
af7cc7d1 4596 if (ret)
bbd9b64e
CO		 4597 goto mmio;
4598
22388a3c 4599 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4600 return X86EMUL_CONTINUE;
4601
4602mmio:
4603 /*
4604 * Is this MMIO handled locally?
4605 */
22388a3c 4606 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4607 if (handled == bytes)
bbd9b64e 4608 return X86EMUL_CONTINUE;
bbd9b64e 4609
70252a10
AK		 4610 gpa += handled;
4611 bytes -= handled;
4612 val += handled;
4613
87da7e66
XG		 4614 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4615 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4616 frag->gpa = gpa;
4617 frag->data = val;
4618 frag->len = bytes;
f78146b0 4619 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4620}
4621
52eb5a6d
XL		 4622static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4623 unsigned long addr,
22388a3c
XG		 4624 void *val, unsigned int bytes,
4625 struct x86_exception *exception,
0fbe9b0b 4626 const struct read_write_emulator_ops *ops)
bbd9b64e 4627{
0f65dd70 4628 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4629 gpa_t gpa;
4630 int rc;
4631
4632 if (ops->read_write_prepare &&
4633 ops->read_write_prepare(vcpu, val, bytes))
4634 return X86EMUL_CONTINUE;
4635
4636 vcpu->mmio_nr_fragments = 0;
0f65dd70 4637
bbd9b64e
CO		 4638 /* Crossing a page boundary? */
4639 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4640 int now;
bbd9b64e
CO		 4641
4642 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4643 rc = emulator_read_write_onepage(addr, val, now, exception,
4644 vcpu, ops);
4645
bbd9b64e
CO		 4646 if (rc != X86EMUL_CONTINUE)
4647 return rc;
4648 addr += now;
bac15531
NA		 4649 if (ctxt->mode != X86EMUL_MODE_PROT64)
4650 addr = (u32)addr;
bbd9b64e
CO		 4651 val += now;
4652 bytes -= now;
4653 }
22388a3c 4654
f78146b0
AK		 4655 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4656 vcpu, ops);
4657 if (rc != X86EMUL_CONTINUE)
4658 return rc;
4659
4660 if (!vcpu->mmio_nr_fragments)
4661 return rc;
4662
4663 gpa = vcpu->mmio_fragments[0].gpa;
4664
4665 vcpu->mmio_needed = 1;
4666 vcpu->mmio_cur_fragment = 0;
4667
87da7e66 4668 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4669 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4670 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4671 vcpu->run->mmio.phys_addr = gpa;
4672
4673 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4674}
4675
4676static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4677 unsigned long addr,
4678 void *val,
4679 unsigned int bytes,
4680 struct x86_exception *exception)
4681{
4682 return emulator_read_write(ctxt, addr, val, bytes,
4683 exception, &read_emultor);
4684}
4685
52eb5a6d 4686static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4687 unsigned long addr,
4688 const void *val,
4689 unsigned int bytes,
4690 struct x86_exception *exception)
4691{
4692 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4693 exception, &write_emultor);
bbd9b64e 4694}
bbd9b64e 4695
daea3e73
AK		 4696#define CMPXCHG_TYPE(t, ptr, old, new) \
4697 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4698
4699#ifdef CONFIG_X86_64
4700# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4701#else
4702# define CMPXCHG64(ptr, old, new) \
9749a6c0 4703 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4704#endif
4705
0f65dd70
AK		 4706static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4707 unsigned long addr,
bbd9b64e
CO		 4708 const void *old,
4709 const void *new,
4710 unsigned int bytes,
0f65dd70 4711 struct x86_exception *exception)
bbd9b64e 4712{
0f65dd70 4713 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4714 gpa_t gpa;
4715 struct page *page;
4716 char *kaddr;
4717 bool exchanged;
2bacc55c 4718
daea3e73
AK		 4719 /* guests cmpxchg8b have to be emulated atomically */
4720 if (bytes > 8 || (bytes & (bytes - 1)))
4721 goto emul_write;
10589a46 4722
daea3e73 4723 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4724
daea3e73
AK		 4725 if (gpa == UNMAPPED_GVA ||
4726 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4727 goto emul_write;
2bacc55c 4728
daea3e73
AK		 4729 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4730 goto emul_write;
72dc67a6 4731
daea3e73 4732 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4733 if (is_error_page(page))
c19b8bd6 4734 goto emul_write;
72dc67a6 4735
8fd75e12 4736 kaddr = kmap_atomic(page);
daea3e73
AK		 4737 kaddr += offset_in_page(gpa);
4738 switch (bytes) {
4739 case 1:
4740 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4741 break;
4742 case 2:
4743 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4744 break;
4745 case 4:
4746 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4747 break;
4748 case 8:
4749 exchanged = CMPXCHG64(kaddr, old, new);
4750 break;
4751 default:
4752 BUG();
2bacc55c 4753 }
8fd75e12 4754 kunmap_atomic(kaddr);
daea3e73
AK		 4755 kvm_release_page_dirty(page);
4756
4757 if (!exchanged)
4758 return X86EMUL_CMPXCHG_FAILED;
4759
d3714010 4760 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4761 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4762
4763 return X86EMUL_CONTINUE;
4a5f48f6 4764
3200f405 4765emul_write:
daea3e73 4766 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4767
0f65dd70 4768 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4769}
4770
cf8f70bf
GN		 4771static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4772{
4773 /* TODO: String I/O for in kernel device */
4774 int r;
4775
4776 if (vcpu->arch.pio.in)
e32edf4f 4777 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4778 vcpu->arch.pio.size, pd);
4779 else
e32edf4f 4780 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4781 vcpu->arch.pio.port, vcpu->arch.pio.size,
4782 pd);
4783 return r;
4784}
4785
6f6fbe98
XG		 4786static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4787 unsigned short port, void *val,
4788 unsigned int count, bool in)
cf8f70bf 4789{
cf8f70bf 4790 vcpu->arch.pio.port = port;
6f6fbe98 4791 vcpu->arch.pio.in = in;
7972995b 4792 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4793 vcpu->arch.pio.size = size;
4794
4795 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4796 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4797 return 1;
4798 }
4799
4800 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4801 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4802 vcpu->run->io.size = size;
4803 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4804 vcpu->run->io.count = count;
4805 vcpu->run->io.port = port;
4806
4807 return 0;
4808}
4809
6f6fbe98
XG		 4810static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4811 int size, unsigned short port, void *val,
4812 unsigned int count)
cf8f70bf 4813{
ca1d4a9e 4814 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4815 int ret;
ca1d4a9e 4816
6f6fbe98
XG		 4817 if (vcpu->arch.pio.count)
4818 goto data_avail;
cf8f70bf 4819
6f6fbe98
XG		 4820 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4821 if (ret) {
4822data_avail:
4823 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4824 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4825 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4826 return 1;
4827 }
4828
cf8f70bf
GN		 4829 return 0;
4830}
4831
6f6fbe98
XG		 4832static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4833 int size, unsigned short port,
4834 const void *val, unsigned int count)
4835{
4836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4837
4838 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4839 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4840 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4841}
4842
bbd9b64e
CO		 4843static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4844{
4845 return kvm_x86_ops->get_segment_base(vcpu, seg);
4846}
4847
3cb16fe7 4848static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4849{
3cb16fe7 4850 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4851}
4852
5cb56059 4853int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4854{
4855 if (!need_emulate_wbinvd(vcpu))
4856 return X86EMUL_CONTINUE;
4857
4858 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4859 int cpu = get_cpu();
4860
4861 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4862 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4863 wbinvd_ipi, NULL, 1);
2eec7343 4864 put_cpu();
f5f48ee1 4865 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4866 } else
4867 wbinvd();
f5f48ee1
SY		 4868 return X86EMUL_CONTINUE;
4869}
5cb56059
JS		 4870
4871int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4872{
4873 kvm_x86_ops->skip_emulated_instruction(vcpu);
4874 return kvm_emulate_wbinvd_noskip(vcpu);
4875}
f5f48ee1
SY		 4876EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4877
5cb56059
JS		 4878
4879
bcaf5cc5
AK		 4880static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4881{
5cb56059 4882 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4883}
4884
52eb5a6d
XL		 4885static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4886 unsigned long *dest)
bbd9b64e 4887{
16f8a6f9 4888 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4889}
4890
52eb5a6d
XL		 4891static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4892 unsigned long value)
bbd9b64e 4893{
338dbc97 4894
717746e3 4895 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4896}
4897
52a46617 4898static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4899{
52a46617 4900 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4901}
4902
717746e3 4903static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4904{
717746e3 4905 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4906 unsigned long value;
4907
4908 switch (cr) {
4909 case 0:
4910 value = kvm_read_cr0(vcpu);
4911 break;
4912 case 2:
4913 value = vcpu->arch.cr2;
4914 break;
4915 case 3:
9f8fe504 4916 value = kvm_read_cr3(vcpu);
52a46617
GN		 4917 break;
4918 case 4:
4919 value = kvm_read_cr4(vcpu);
4920 break;
4921 case 8:
4922 value = kvm_get_cr8(vcpu);
4923 break;
4924 default:
a737f256 4925 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4926 return 0;
4927 }
4928
4929 return value;
4930}
4931
717746e3 4932static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4933{
717746e3 4934 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4935 int res = 0;
4936
52a46617
GN		 4937 switch (cr) {
4938 case 0:
49a9b07e 4939 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4940 break;
4941 case 2:
4942 vcpu->arch.cr2 = val;
4943 break;
4944 case 3:
2390218b 4945 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4946 break;
4947 case 4:
a83b29c6 4948 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4949 break;
4950 case 8:
eea1cff9 4951 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4952 break;
4953 default:
a737f256 4954 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4955 res = -1;
52a46617 4956 }
0f12244f
GN		 4957
4958 return res;
52a46617
GN		 4959}
4960
717746e3 4961static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4962{
717746e3 4963 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4964}
4965
4bff1e86 4966static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4967{
4bff1e86 4968 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4969}
4970
4bff1e86 4971static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4972{
4bff1e86 4973 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4974}
4975
1ac9d0cf
AK		 4976static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4977{
4978 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4979}
4980
4981static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4982{
4983 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4984}
4985
4bff1e86
AK		 4986static unsigned long emulator_get_cached_segment_base(
4987 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4988{
4bff1e86 4989 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4990}
4991
1aa36616
AK		 4992static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4993 struct desc_struct *desc, u32 *base3,
4994 int seg)
2dafc6c2
GN		 4995{
4996 struct kvm_segment var;
4997
4bff1e86 4998 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4999 *selector = var.selector;
2dafc6c2 5000
378a8b09
GN		 5001 if (var.unusable) {
5002 memset(desc, 0, sizeof(*desc));
2dafc6c2 5003 return false;
378a8b09 5004 }
2dafc6c2
GN		 5005
5006 if (var.g)
5007 var.limit >>= 12;
5008 set_desc_limit(desc, var.limit);
5009 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5010#ifdef CONFIG_X86_64
5011 if (base3)
5012 *base3 = var.base >> 32;
5013#endif
2dafc6c2
GN		 5014 desc->type = var.type;
5015 desc->s = var.s;
5016 desc->dpl = var.dpl;
5017 desc->p = var.present;
5018 desc->avl = var.avl;
5019 desc->l = var.l;
5020 desc->d = var.db;
5021 desc->g = var.g;
5022
5023 return true;
5024}
5025
1aa36616
AK		 5026static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5027 struct desc_struct *desc, u32 base3,
5028 int seg)
2dafc6c2 5029{
4bff1e86 5030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5031 struct kvm_segment var;
5032
1aa36616 5033 var.selector = selector;
2dafc6c2 5034 var.base = get_desc_base(desc);
5601d05b
GN		 5035#ifdef CONFIG_X86_64
5036 var.base |= ((u64)base3) << 32;
5037#endif
2dafc6c2
GN		 5038 var.limit = get_desc_limit(desc);
5039 if (desc->g)
5040 var.limit = (var.limit << 12) | 0xfff;
5041 var.type = desc->type;
2dafc6c2
GN		 5042 var.dpl = desc->dpl;
5043 var.db = desc->d;
5044 var.s = desc->s;
5045 var.l = desc->l;
5046 var.g = desc->g;
5047 var.avl = desc->avl;
5048 var.present = desc->p;
5049 var.unusable = !var.present;
5050 var.padding = 0;
5051
5052 kvm_set_segment(vcpu, &var, seg);
5053 return;
5054}
5055
717746e3
AK		 5056static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5057 u32 msr_index, u64 *pdata)
5058{
5059 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
5060}
5061
5062static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5063 u32 msr_index, u64 data)
5064{
8fe8ab46
WA		 5065 struct msr_data msr;
5066
5067 msr.data = data;
5068 msr.index = msr_index;
5069 msr.host_initiated = false;
5070 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5071}
5072
67f4d428
NA		 5073static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5074 u32 pmc)
5075{
5076 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
5077}
5078
222d21aa
AK		 5079static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5080 u32 pmc, u64 *pdata)
5081{
5082 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
5083}
5084
6c3287f7
AK		 5085static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5086{
5087 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5088}
5089
5037f6f3
AK		 5090static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5091{
5092 preempt_disable();
5197b808 5093 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5094 /*
5095 * CR0.TS may reference the host fpu state, not the guest fpu state,
5096 * so it may be clear at this point.
5097 */
5098 clts();
5099}
5100
5101static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5102{
5103 preempt_enable();
5104}
5105
2953538e 5106static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5107 struct x86_instruction_info *info,
c4f035c6
AK		 5108 enum x86_intercept_stage stage)
5109{
2953538e 5110 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5111}
5112
0017f93a 5113static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5114 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5115{
0017f93a 5116 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5117}
5118
dd856efa
AK		 5119static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5120{
5121 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5122}
5123
5124static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5125{
5126 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5127}
5128
801806d9
NA		 5129static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5130{
5131 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5132}
5133
0225fb50 5134static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5135 .read_gpr = emulator_read_gpr,
5136 .write_gpr = emulator_write_gpr,
1871c602 5137 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5138 .write_std = kvm_write_guest_virt_system,
1871c602 5139 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5140 .read_emulated = emulator_read_emulated,
5141 .write_emulated = emulator_write_emulated,
5142 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5143 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5144 .pio_in_emulated = emulator_pio_in_emulated,
5145 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5146 .get_segment = emulator_get_segment,
5147 .set_segment = emulator_set_segment,
5951c442 5148 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5149 .get_gdt = emulator_get_gdt,
160ce1f1 5150 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5151 .set_gdt = emulator_set_gdt,
5152 .set_idt = emulator_set_idt,
52a46617
GN		 5153 .get_cr = emulator_get_cr,
5154 .set_cr = emulator_set_cr,
9c537244 5155 .cpl = emulator_get_cpl,
35aa5375
GN		 5156 .get_dr = emulator_get_dr,
5157 .set_dr = emulator_set_dr,
717746e3
AK		 5158 .set_msr = emulator_set_msr,
5159 .get_msr = emulator_get_msr,
67f4d428 5160 .check_pmc = emulator_check_pmc,
222d21aa 5161 .read_pmc = emulator_read_pmc,
6c3287f7 5162 .halt = emulator_halt,
bcaf5cc5 5163 .wbinvd = emulator_wbinvd,
d6aa1000 5164 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5165 .get_fpu = emulator_get_fpu,
5166 .put_fpu = emulator_put_fpu,
c4f035c6 5167 .intercept = emulator_intercept,
bdb42f5a 5168 .get_cpuid = emulator_get_cpuid,
801806d9 5169 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5170};
5171
95cb2295
GN		 5172static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5173{
37ccdcbe 5174 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5175 /*
5176 * an sti; sti; sequence only disable interrupts for the first
5177 * instruction. So, if the last instruction, be it emulated or
5178 * not, left the system with the INT_STI flag enabled, it
5179 * means that the last instruction is an sti. We should not
5180 * leave the flag on in this case. The same goes for mov ss
5181 */
37ccdcbe
PB		 5182 if (int_shadow & mask)
5183 mask = 0;
6addfc42 5184 if (unlikely(int_shadow || mask)) {
95cb2295 5185 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5186 if (!mask)
5187 kvm_make_request(KVM_REQ_EVENT, vcpu);
5188 }
95cb2295
GN		 5189}
5190
ef54bcfe 5191static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5192{
5193 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5194 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5195 return kvm_propagate_fault(vcpu, &ctxt->exception);
5196
5197 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5198 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5199 ctxt->exception.error_code);
54b8486f 5200 else
da9cb575 5201 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5202 return false;
54b8486f
GN		 5203}
5204
8ec4722d
MG		 5205static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5206{
adf52235 5207 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5208 int cs_db, cs_l;
5209
8ec4722d
MG		 5210 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5211
adf52235
TY		 5212 ctxt->eflags = kvm_get_rflags(vcpu);
5213 ctxt->eip = kvm_rip_read(vcpu);
5214 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5215 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5216 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5217 cs_db ? X86EMUL_MODE_PROT32 :
5218 X86EMUL_MODE_PROT16;
5219 ctxt->guest_mode = is_guest_mode(vcpu);
5220
dd856efa 5221 init_decode_cache(ctxt);
7ae441ea 5222 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5223}
5224
71f9833b 5225int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5226{
9d74191a 5227 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5228 int ret;
5229
5230 init_emulate_ctxt(vcpu);
5231
9dac77fa
AK		 5232 ctxt->op_bytes = 2;
5233 ctxt->ad_bytes = 2;
5234 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5235 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5236
5237 if (ret != X86EMUL_CONTINUE)
5238 return EMULATE_FAIL;
5239
9dac77fa 5240 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5241 kvm_rip_write(vcpu, ctxt->eip);
5242 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5243
5244 if (irq == NMI_VECTOR)
7460fb4a 5245 vcpu->arch.nmi_pending = 0;
63995653
MG		 5246 else
5247 vcpu->arch.interrupt.pending = false;
5248
5249 return EMULATE_DONE;
5250}
5251EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5252
6d77dbfc
GN		 5253static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5254{
fc3a9157
JR		 5255 int r = EMULATE_DONE;
5256
6d77dbfc
GN		 5257 ++vcpu->stat.insn_emulation_fail;
5258 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5259 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5260 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5261 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5262 vcpu->run->internal.ndata = 0;
5263 r = EMULATE_FAIL;
5264 }
6d77dbfc 5265 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5266
5267 return r;
6d77dbfc
GN		 5268}
5269
93c05d3e 5270static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5271 bool write_fault_to_shadow_pgtable,
5272 int emulation_type)
a6f177ef 5273{
95b3cf69 5274 gpa_t gpa = cr2;
8e3d9d06 5275 pfn_t pfn;
a6f177ef 5276
991eebf9
GN		 5277 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5278 return false;
5279
95b3cf69
XG		 5280 if (!vcpu->arch.mmu.direct_map) {
5281 /*
5282 * Write permission should be allowed since only
5283 * write access need to be emulated.
5284 */
5285 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5286
95b3cf69
XG		 5287 /*
5288 * If the mapping is invalid in guest, let cpu retry
5289 * it to generate fault.
5290 */
5291 if (gpa == UNMAPPED_GVA)
5292 return true;
5293 }
a6f177ef 5294
8e3d9d06
XG		 5295 /*
5296 * Do not retry the unhandleable instruction if it faults on the
5297 * readonly host memory, otherwise it will goto a infinite loop:
5298 * retry instruction -> write #PF -> emulation fail -> retry
5299 * instruction -> ...
5300 */
5301 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5302
5303 /*
5304 * If the instruction failed on the error pfn, it can not be fixed,
5305 * report the error to userspace.
5306 */
5307 if (is_error_noslot_pfn(pfn))
5308 return false;
5309
5310 kvm_release_pfn_clean(pfn);
5311
5312 /* The instructions are well-emulated on direct mmu. */
5313 if (vcpu->arch.mmu.direct_map) {
5314 unsigned int indirect_shadow_pages;
5315
5316 spin_lock(&vcpu->kvm->mmu_lock);
5317 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5318 spin_unlock(&vcpu->kvm->mmu_lock);
5319
5320 if (indirect_shadow_pages)
5321 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5322
a6f177ef 5323 return true;
8e3d9d06 5324 }
a6f177ef 5325
95b3cf69
XG		 5326 /*
5327 * if emulation was due to access to shadowed page table
5328 * and it failed try to unshadow page and re-enter the
5329 * guest to let CPU execute the instruction.
5330 */
5331 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5332
5333 /*
5334 * If the access faults on its page table, it can not
5335 * be fixed by unprotecting shadow page and it should
5336 * be reported to userspace.
5337 */
5338 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5339}
5340
1cb3f3ae
XG		 5341static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5342 unsigned long cr2, int emulation_type)
5343{
5344 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5345 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5346
5347 last_retry_eip = vcpu->arch.last_retry_eip;
5348 last_retry_addr = vcpu->arch.last_retry_addr;
5349
5350 /*
5351 * If the emulation is caused by #PF and it is non-page_table
5352 * writing instruction, it means the VM-EXIT is caused by shadow
5353 * page protected, we can zap the shadow page and retry this
5354 * instruction directly.
5355 *
5356 * Note: if the guest uses a non-page-table modifying instruction
5357 * on the PDE that points to the instruction, then we will unmap
5358 * the instruction and go to an infinite loop. So, we cache the
5359 * last retried eip and the last fault address, if we meet the eip
5360 * and the address again, we can break out of the potential infinite
5361 * loop.
5362 */
5363 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5364
5365 if (!(emulation_type & EMULTYPE_RETRY))
5366 return false;
5367
5368 if (x86_page_table_writing_insn(ctxt))
5369 return false;
5370
5371 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5372 return false;
5373
5374 vcpu->arch.last_retry_eip = ctxt->eip;
5375 vcpu->arch.last_retry_addr = cr2;
5376
5377 if (!vcpu->arch.mmu.direct_map)
5378 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5379
22368028 5380 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5381
5382 return true;
5383}
5384
716d51ab
GN		 5385static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5386static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5387
4a1e10d5
PB		 5388static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5389 unsigned long *db)
5390{
5391 u32 dr6 = 0;
5392 int i;
5393 u32 enable, rwlen;
5394
5395 enable = dr7;
5396 rwlen = dr7 >> 16;
5397 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5398 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5399 dr6 |= (1 << i);
5400 return dr6;
5401}
5402
6addfc42 5403static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5404{
5405 struct kvm_run *kvm_run = vcpu->run;
5406
5407 /*
6addfc42
PB		 5408 * rflags is the old, "raw" value of the flags. The new value has
5409 * not been saved yet.
663f4c61
PB		 5410 *
5411 * This is correct even for TF set by the guest, because "the
5412 * processor will not generate this exception after the instruction
5413 * that sets the TF flag".
5414 */
663f4c61
PB		 5415 if (unlikely(rflags & X86_EFLAGS_TF)) {
5416 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5417 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5418 DR6_RTM;
663f4c61
PB		 5419 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5420 kvm_run->debug.arch.exception = DB_VECTOR;
5421 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5422 *r = EMULATE_USER_EXIT;
5423 } else {
5424 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5425 /*
5426 * "Certain debug exceptions may clear bit 0-3. The
5427 * remaining contents of the DR6 register are never
5428 * cleared by the processor".
5429 */
5430 vcpu->arch.dr6 &= ~15;
6f43ed01 5431 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5432 kvm_queue_exception(vcpu, DB_VECTOR);
5433 }
5434 }
5435}
5436
4a1e10d5
PB		 5437static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5438{
4a1e10d5
PB		 5439 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5440 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5441 struct kvm_run *kvm_run = vcpu->run;
5442 unsigned long eip = kvm_get_linear_rip(vcpu);
5443 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5444 vcpu->arch.guest_debug_dr7,
5445 vcpu->arch.eff_db);
5446
5447 if (dr6 != 0) {
6f43ed01 5448 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5449 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5450 kvm_run->debug.arch.exception = DB_VECTOR;
5451 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5452 *r = EMULATE_USER_EXIT;
5453 return true;
5454 }
5455 }
5456
4161a569
NA		 5457 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5458 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5459 unsigned long eip = kvm_get_linear_rip(vcpu);
5460 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5461 vcpu->arch.dr7,
5462 vcpu->arch.db);
5463
5464 if (dr6 != 0) {
5465 vcpu->arch.dr6 &= ~15;
6f43ed01 5466 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5467 kvm_queue_exception(vcpu, DB_VECTOR);
5468 *r = EMULATE_DONE;
5469 return true;
5470 }
5471 }
5472
5473 return false;
5474}
5475
51d8b661
AP		 5476int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5477 unsigned long cr2,
dc25e89e
AP		 5478 int emulation_type,
5479 void *insn,
5480 int insn_len)
bbd9b64e 5481{
95cb2295 5482 int r;
9d74191a 5483 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5484 bool writeback = true;
93c05d3e 5485 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5486
93c05d3e
XG		 5487 /*
5488 * Clear write_fault_to_shadow_pgtable here to ensure it is
5489 * never reused.
5490 */
5491 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5492 kvm_clear_exception_queue(vcpu);
8d7d8102 5493
571008da 5494 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5495 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5496
5497 /*
5498 * We will reenter on the same instruction since
5499 * we do not set complete_userspace_io. This does not
5500 * handle watchpoints yet, those would be handled in
5501 * the emulate_ops.
5502 */
5503 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5504 return r;
5505
9d74191a
TY		 5506 ctxt->interruptibility = 0;
5507 ctxt->have_exception = false;
e0ad0b47 5508 ctxt->exception.vector = -1;
9d74191a 5509 ctxt->perm_ok = false;
bbd9b64e 5510
b51e974f 5511 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5512
9d74191a 5513 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5514
e46479f8 5515 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5516 ++vcpu->stat.insn_emulation;
1d2887e2 5517 if (r != EMULATION_OK) {
4005996e
AK		 5518 if (emulation_type & EMULTYPE_TRAP_UD)
5519 return EMULATE_FAIL;
991eebf9
GN		 5520 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5521 emulation_type))
bbd9b64e 5522 return EMULATE_DONE;
6d77dbfc
GN		 5523 if (emulation_type & EMULTYPE_SKIP)
5524 return EMULATE_FAIL;
5525 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5526 }
5527 }
5528
ba8afb6b 5529 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5530 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5531 if (ctxt->eflags & X86_EFLAGS_RF)
5532 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5533 return EMULATE_DONE;
5534 }
5535
1cb3f3ae
XG		 5536 if (retry_instruction(ctxt, cr2, emulation_type))
5537 return EMULATE_DONE;
5538
7ae441ea 5539 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5540 changes registers values during IO operation */
7ae441ea
GN		 5541 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5542 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5543 emulator_invalidate_register_cache(ctxt);
7ae441ea 5544 }
4d2179e1 5545
5cd21917 5546restart:
9d74191a 5547 r = x86_emulate_insn(ctxt);
bbd9b64e 5548
775fde86
JR		 5549 if (r == EMULATION_INTERCEPTED)
5550 return EMULATE_DONE;
5551
d2ddd1c4 5552 if (r == EMULATION_FAILED) {
991eebf9
GN		 5553 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5554 emulation_type))
c3cd7ffa
GN		 5555 return EMULATE_DONE;
5556
6d77dbfc 5557 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5558 }
5559
9d74191a 5560 if (ctxt->have_exception) {
d2ddd1c4 5561 r = EMULATE_DONE;
ef54bcfe
PB		 5562 if (inject_emulated_exception(vcpu))
5563 return r;
d2ddd1c4 5564 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5565 if (!vcpu->arch.pio.in) {
5566 /* FIXME: return into emulator if single-stepping. */
3457e419 5567 vcpu->arch.pio.count = 0;
0912c977 5568 } else {
7ae441ea 5569 writeback = false;
716d51ab
GN		 5570 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5571 }
ac0a48c3 5572 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5573 } else if (vcpu->mmio_needed) {
5574 if (!vcpu->mmio_is_write)
5575 writeback = false;
ac0a48c3 5576 r = EMULATE_USER_EXIT;
716d51ab 5577 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5578 } else if (r == EMULATION_RESTART)
5cd21917 5579 goto restart;
d2ddd1c4
GN		 5580 else
5581 r = EMULATE_DONE;
f850e2e6 5582
7ae441ea 5583 if (writeback) {
6addfc42 5584 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5585 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5586 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5587 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5588 if (r == EMULATE_DONE)
6addfc42 5589 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5590 if (!ctxt->have_exception ||
5591 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5592 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5593
5594 /*
5595 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5596 * do nothing, and it will be requested again as soon as
5597 * the shadow expires. But we still need to check here,
5598 * because POPF has no interrupt shadow.
5599 */
5600 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5601 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5602 } else
5603 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5604
5605 return r;
de7d789a 5606}
51d8b661 5607EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5608
cf8f70bf 5609int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5610{
cf8f70bf 5611 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5612 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5613 size, port, &val, 1);
cf8f70bf 5614 /* do not return to emulator after return from userspace */
7972995b 5615 vcpu->arch.pio.count = 0;
de7d789a
CO		 5616 return ret;
5617}
cf8f70bf 5618EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5619
8cfdc000
ZA		 5620static void tsc_bad(void *info)
5621{
0a3aee0d 5622 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5623}
5624
5625static void tsc_khz_changed(void *data)
c8076604 5626{
8cfdc000
ZA		 5627 struct cpufreq_freqs *freq = data;
5628 unsigned long khz = 0;
5629
5630 if (data)
5631 khz = freq->new;
5632 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5633 khz = cpufreq_quick_get(raw_smp_processor_id());
5634 if (!khz)
5635 khz = tsc_khz;
0a3aee0d 5636 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5637}
5638
c8076604
GH		 5639static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5640 void *data)
5641{
5642 struct cpufreq_freqs *freq = data;
5643 struct kvm *kvm;
5644 struct kvm_vcpu *vcpu;
5645 int i, send_ipi = 0;
5646
8cfdc000
ZA		 5647 /*
5648 * We allow guests to temporarily run on slowing clocks,
5649 * provided we notify them after, or to run on accelerating
5650 * clocks, provided we notify them before. Thus time never
5651 * goes backwards.
5652 *
5653 * However, we have a problem. We can't atomically update
5654 * the frequency of a given CPU from this function; it is
5655 * merely a notifier, which can be called from any CPU.
5656 * Changing the TSC frequency at arbitrary points in time
5657 * requires a recomputation of local variables related to
5658 * the TSC for each VCPU. We must flag these local variables
5659 * to be updated and be sure the update takes place with the
5660 * new frequency before any guests proceed.
5661 *
5662 * Unfortunately, the combination of hotplug CPU and frequency
5663 * change creates an intractable locking scenario; the order
5664 * of when these callouts happen is undefined with respect to
5665 * CPU hotplug, and they can race with each other. As such,
5666 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5667 * undefined; you can actually have a CPU frequency change take
5668 * place in between the computation of X and the setting of the
5669 * variable. To protect against this problem, all updates of
5670 * the per_cpu tsc_khz variable are done in an interrupt
5671 * protected IPI, and all callers wishing to update the value
5672 * must wait for a synchronous IPI to complete (which is trivial
5673 * if the caller is on the CPU already). This establishes the
5674 * necessary total order on variable updates.
5675 *
5676 * Note that because a guest time update may take place
5677 * anytime after the setting of the VCPU's request bit, the
5678 * correct TSC value must be set before the request. However,
5679 * to ensure the update actually makes it to any guest which
5680 * starts running in hardware virtualization between the set
5681 * and the acquisition of the spinlock, we must also ping the
5682 * CPU after setting the request bit.
5683 *
5684 */
5685
c8076604
GH		 5686 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5687 return 0;
5688 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5689 return 0;
8cfdc000
ZA		 5690
5691 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5692
2f303b74 5693 spin_lock(&kvm_lock);
c8076604 5694 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5695 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5696 if (vcpu->cpu != freq->cpu)
5697 continue;
c285545f 5698 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5699 if (vcpu->cpu != smp_processor_id())
8cfdc000 5700 send_ipi = 1;
c8076604
GH		 5701 }
5702 }
2f303b74 5703 spin_unlock(&kvm_lock);
c8076604
GH		 5704
5705 if (freq->old < freq->new && send_ipi) {
5706 /*
5707 * We upscale the frequency. Must make the guest
5708 * doesn't see old kvmclock values while running with
5709 * the new frequency, otherwise we risk the guest sees
5710 * time go backwards.
5711 *
5712 * In case we update the frequency for another cpu
5713 * (which might be in guest context) send an interrupt
5714 * to kick the cpu out of guest context. Next time
5715 * guest context is entered kvmclock will be updated,
5716 * so the guest will not see stale values.
5717 */
8cfdc000 5718 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5719 }
5720 return 0;
5721}
5722
5723static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5724 .notifier_call = kvmclock_cpufreq_notifier
5725};
5726
5727static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5728 unsigned long action, void *hcpu)
5729{
5730 unsigned int cpu = (unsigned long)hcpu;
5731
5732 switch (action) {
5733 case CPU_ONLINE:
5734 case CPU_DOWN_FAILED:
5735 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5736 break;
5737 case CPU_DOWN_PREPARE:
5738 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5739 break;
5740 }
5741 return NOTIFY_OK;
5742}
5743
5744static struct notifier_block kvmclock_cpu_notifier_block = {
5745 .notifier_call = kvmclock_cpu_notifier,
5746 .priority = -INT_MAX
c8076604
GH		 5747};
5748
b820cc0c
ZA		 5749static void kvm_timer_init(void)
5750{
5751 int cpu;
5752
c285545f 5753 max_tsc_khz = tsc_khz;
460dd42e
SB		 5754
5755 cpu_notifier_register_begin();
b820cc0c 5756 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5757#ifdef CONFIG_CPU_FREQ
5758 struct cpufreq_policy policy;
5759 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5760 cpu = get_cpu();
5761 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5762 if (policy.cpuinfo.max_freq)
5763 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5764 put_cpu();
c285545f 5765#endif
b820cc0c
ZA		 5766 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5767 CPUFREQ_TRANSITION_NOTIFIER);
5768 }
c285545f 5769 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5770 for_each_online_cpu(cpu)
5771 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5772
5773 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5774 cpu_notifier_register_done();
5775
b820cc0c
ZA		 5776}
5777
ff9d07a0
ZY		 5778static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5779
f5132b01 5780int kvm_is_in_guest(void)
ff9d07a0 5781{
086c9855 5782 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5783}
5784
5785static int kvm_is_user_mode(void)
5786{
5787 int user_mode = 3;
dcf46b94 5788
086c9855
AS		 5789 if (__this_cpu_read(current_vcpu))
5790 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5791
ff9d07a0
ZY		 5792 return user_mode != 0;
5793}
5794
5795static unsigned long kvm_get_guest_ip(void)
5796{
5797 unsigned long ip = 0;
dcf46b94 5798
086c9855
AS		 5799 if (__this_cpu_read(current_vcpu))
5800 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5801
ff9d07a0
ZY		 5802 return ip;
5803}
5804
5805static struct perf_guest_info_callbacks kvm_guest_cbs = {
5806 .is_in_guest = kvm_is_in_guest,
5807 .is_user_mode = kvm_is_user_mode,
5808 .get_guest_ip = kvm_get_guest_ip,
5809};
5810
5811void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5812{
086c9855 5813 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5814}
5815EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5816
5817void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5818{
086c9855 5819 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5820}
5821EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5822
ce88decf
XG		 5823static void kvm_set_mmio_spte_mask(void)
5824{
5825 u64 mask;
5826 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5827
5828 /*
5829 * Set the reserved bits and the present bit of an paging-structure
5830 * entry to generate page fault with PFER.RSV = 1.
5831 */
885032b9 5832 /* Mask the reserved physical address bits. */
d1431483 5833 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5834
5835 /* Bit 62 is always reserved for 32bit host. */
5836 mask |= 0x3ull << 62;
5837
5838 /* Set the present bit. */
ce88decf
XG		 5839 mask |= 1ull;
5840
5841#ifdef CONFIG_X86_64
5842 /*
5843 * If reserved bit is not supported, clear the present bit to disable
5844 * mmio page fault.
5845 */
5846 if (maxphyaddr == 52)
5847 mask &= ~1ull;
5848#endif
5849
5850 kvm_mmu_set_mmio_spte_mask(mask);
5851}
5852
16e8d74d
MT		 5853#ifdef CONFIG_X86_64
5854static void pvclock_gtod_update_fn(struct work_struct *work)
5855{
d828199e
MT		 5856 struct kvm *kvm;
5857
5858 struct kvm_vcpu *vcpu;
5859 int i;
5860
2f303b74 5861 spin_lock(&kvm_lock);
d828199e
MT		 5862 list_for_each_entry(kvm, &vm_list, vm_list)
5863 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5864 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5865 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5866 spin_unlock(&kvm_lock);
16e8d74d
MT		 5867}
5868
5869static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5870
5871/*
5872 * Notification about pvclock gtod data update.
5873 */
5874static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5875 void *priv)
5876{
5877 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5878 struct timekeeper *tk = priv;
5879
5880 update_pvclock_gtod(tk);
5881
5882 /* disable master clock if host does not trust, or does not
5883 * use, TSC clocksource
5884 */
5885 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5886 atomic_read(&kvm_guest_has_master_clock) != 0)
5887 queue_work(system_long_wq, &pvclock_gtod_work);
5888
5889 return 0;
5890}
5891
5892static struct notifier_block pvclock_gtod_notifier = {
5893 .notifier_call = pvclock_gtod_notify,
5894};
5895#endif
5896
f8c16bba 5897int kvm_arch_init(void *opaque)
043405e1 5898{
b820cc0c 5899 int r;
6b61edf7 5900 struct kvm_x86_ops *ops = opaque;
f8c16bba 5901
f8c16bba
ZX		 5902 if (kvm_x86_ops) {
5903 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5904 r = -EEXIST;
5905 goto out;
f8c16bba
ZX		 5906 }
5907
5908 if (!ops->cpu_has_kvm_support()) {
5909 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5910 r = -EOPNOTSUPP;
5911 goto out;
f8c16bba
ZX		 5912 }
5913 if (ops->disabled_by_bios()) {
5914 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5915 r = -EOPNOTSUPP;
5916 goto out;
f8c16bba
ZX		 5917 }
5918
013f6a5d
MT		 5919 r = -ENOMEM;
5920 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5921 if (!shared_msrs) {
5922 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5923 goto out;
5924 }
5925
97db56ce
AK		 5926 r = kvm_mmu_module_init();
5927 if (r)
013f6a5d 5928 goto out_free_percpu;
97db56ce 5929
ce88decf 5930 kvm_set_mmio_spte_mask();
97db56ce 5931
f8c16bba 5932 kvm_x86_ops = ops;
920c8377 5933
7b52345e 5934 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5935 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5936
b820cc0c 5937 kvm_timer_init();
c8076604 5938
ff9d07a0
ZY		 5939 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5940
2acf923e
DC		 5941 if (cpu_has_xsave)
5942 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5943
c5cc421b 5944 kvm_lapic_init();
16e8d74d
MT		 5945#ifdef CONFIG_X86_64
5946 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5947#endif
5948
f8c16bba 5949 return 0;
56c6d28a 5950
013f6a5d
MT		 5951out_free_percpu:
5952 free_percpu(shared_msrs);
56c6d28a 5953out:
56c6d28a 5954 return r;
043405e1 5955}
8776e519 5956
f8c16bba
ZX		 5957void kvm_arch_exit(void)
5958{
ff9d07a0
ZY		 5959 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5960
888d256e
JK		 5961 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5962 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5963 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5964 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5965#ifdef CONFIG_X86_64
5966 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5967#endif
f8c16bba 5968 kvm_x86_ops = NULL;
56c6d28a 5969 kvm_mmu_module_exit();
013f6a5d 5970 free_percpu(shared_msrs);
56c6d28a 5971}
f8c16bba 5972
5cb56059 5973int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5974{
5975 ++vcpu->stat.halt_exits;
5976 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5977 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5978 return 1;
5979 } else {
5980 vcpu->run->exit_reason = KVM_EXIT_HLT;
5981 return 0;
5982 }
5983}
5cb56059
JS		 5984EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5985
5986int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5987{
5988 kvm_x86_ops->skip_emulated_instruction(vcpu);
5989 return kvm_vcpu_halt(vcpu);
5990}
8776e519
HB		 5991EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5992
55cd8e5a
GN		 5993int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5994{
5995 u64 param, ingpa, outgpa, ret;
5996 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5997 bool fast, longmode;
55cd8e5a
GN		 5998
5999 /*
6000 * hypercall generates UD from non zero cpl and real mode
6001 * per HYPER-V spec
6002 */
3eeb3288 6003 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 6004 kvm_queue_exception(vcpu, UD_VECTOR);
6005 return 0;
6006 }
6007
a449c7aa 6008 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 6009
6010 if (!longmode) {
ccd46936
GN		 6011 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
6012 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
6013 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
6014 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
6015 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
6016 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 6017 }
6018#ifdef CONFIG_X86_64
6019 else {
6020 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
6021 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
6022 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
6023 }
6024#endif
6025
6026 code = param & 0xffff;
6027 fast = (param >> 16) & 0x1;
6028 rep_cnt = (param >> 32) & 0xfff;
6029 rep_idx = (param >> 48) & 0xfff;
6030
6031 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
6032
c25bc163
GN		 6033 switch (code) {
6034 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
6035 kvm_vcpu_on_spin(vcpu);
6036 break;
6037 default:
6038 res = HV_STATUS_INVALID_HYPERCALL_CODE;
6039 break;
6040 }
55cd8e5a
GN		 6041
6042 ret = res | (((u64)rep_done & 0xfff) << 32);
6043 if (longmode) {
6044 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6045 } else {
6046 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
6047 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
6048 }
6049
6050 return 1;
6051}
6052
6aef266c
SV		 6053/*
6054 * kvm_pv_kick_cpu_op: Kick a vcpu.
6055 *
6056 * @apicid - apicid of vcpu to be kicked.
6057 */
6058static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6059{
24d2166b 6060 struct kvm_lapic_irq lapic_irq;
6aef266c 6061
24d2166b
R		 6062 lapic_irq.shorthand = 0;
6063 lapic_irq.dest_mode = 0;
6064 lapic_irq.dest_id = apicid;
93bbf0b8 6065 lapic_irq.msi_redir_hint = false;
6aef266c 6066
24d2166b 6067 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6068 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6069}
6070
8776e519
HB		 6071int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6072{
6073 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6074 int op_64_bit, r = 1;
8776e519 6075
5cb56059
JS		 6076 kvm_x86_ops->skip_emulated_instruction(vcpu);
6077
55cd8e5a
GN		 6078 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6079 return kvm_hv_hypercall(vcpu);
6080
5fdbf976
MT		 6081 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6082 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6083 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6084 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6085 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6086
229456fc 6087 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6088
a449c7aa
NA		 6089 op_64_bit = is_64_bit_mode(vcpu);
6090 if (!op_64_bit) {
8776e519
HB		 6091 nr &= 0xFFFFFFFF;
6092 a0 &= 0xFFFFFFFF;
6093 a1 &= 0xFFFFFFFF;
6094 a2 &= 0xFFFFFFFF;
6095 a3 &= 0xFFFFFFFF;
6096 }
6097
07708c4a
JK		 6098 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6099 ret = -KVM_EPERM;
6100 goto out;
6101 }
6102
8776e519 6103 switch (nr) {
b93463aa
AK		 6104 case KVM_HC_VAPIC_POLL_IRQ:
6105 ret = 0;
6106 break;
6aef266c
SV		 6107 case KVM_HC_KICK_CPU:
6108 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6109 ret = 0;
6110 break;
8776e519
HB		 6111 default:
6112 ret = -KVM_ENOSYS;
6113 break;
6114 }
07708c4a 6115out:
a449c7aa
NA		 6116 if (!op_64_bit)
6117 ret = (u32)ret;
5fdbf976 6118 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6119 ++vcpu->stat.hypercalls;
2f333bcb 6120 return r;
8776e519
HB		 6121}
6122EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6123
b6785def 6124static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6125{
d6aa1000 6126 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6127 char instruction[3];
5fdbf976 6128 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6129
8776e519 6130 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6131
9d74191a 6132 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6133}
6134
b6c7a5dc
HB		 6135/*
6136 * Check if userspace requested an interrupt window, and that the
6137 * interrupt window is open.
6138 *
6139 * No need to exit to userspace if we already have an interrupt queued.
6140 */
851ba692 6141static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6142{
8061823a 6143 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6144 vcpu->run->request_interrupt_window &&
5df56646 6145 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6146}
6147
851ba692 6148static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6149{
851ba692
AK		 6150 struct kvm_run *kvm_run = vcpu->run;
6151
91586a3b 6152 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6153 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6154 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6155 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6156 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6157 else
b6c7a5dc 6158 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6159 kvm_arch_interrupt_allowed(vcpu) &&
6160 !kvm_cpu_has_interrupt(vcpu) &&
6161 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6162}
6163
95ba8273
GN		 6164static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6165{
6166 int max_irr, tpr;
6167
6168 if (!kvm_x86_ops->update_cr8_intercept)
6169 return;
6170
88c808fd
AK		 6171 if (!vcpu->arch.apic)
6172 return;
6173
8db3baa2
GN		 6174 if (!vcpu->arch.apic->vapic_addr)
6175 max_irr = kvm_lapic_find_highest_irr(vcpu);
6176 else
6177 max_irr = -1;
95ba8273
GN		 6178
6179 if (max_irr != -1)
6180 max_irr >>= 4;
6181
6182 tpr = kvm_lapic_get_cr8(vcpu);
6183
6184 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6185}
6186
b6b8a145 6187static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6188{
b6b8a145
JK		 6189 int r;
6190
95ba8273 6191 /* try to reinject previous events if any */
b59bb7bd 6192 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6193 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6194 vcpu->arch.exception.has_error_code,
6195 vcpu->arch.exception.error_code);
d6e8c854
NA		 6196
6197 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6198 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6199 X86_EFLAGS_RF);
6200
6bdf0662
NA		 6201 if (vcpu->arch.exception.nr == DB_VECTOR &&
6202 (vcpu->arch.dr7 & DR7_GD)) {
6203 vcpu->arch.dr7 &= ~DR7_GD;
6204 kvm_update_dr7(vcpu);
6205 }
6206
b59bb7bd
GN		 6207 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6208 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6209 vcpu->arch.exception.error_code,
6210 vcpu->arch.exception.reinject);
b6b8a145 6211 return 0;
b59bb7bd
GN		 6212 }
6213
95ba8273
GN		 6214 if (vcpu->arch.nmi_injected) {
6215 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6216 return 0;
95ba8273
GN		 6217 }
6218
6219 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6220 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6221 return 0;
6222 }
6223
6224 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6225 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6226 if (r != 0)
6227 return r;
95ba8273
GN		 6228 }
6229
6230 /* try to inject new event if pending */
6231 if (vcpu->arch.nmi_pending) {
6232 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6233 --vcpu->arch.nmi_pending;
95ba8273
GN		 6234 vcpu->arch.nmi_injected = true;
6235 kvm_x86_ops->set_nmi(vcpu);
6236 }
c7c9c56c 6237 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6238 /*
6239 * Because interrupts can be injected asynchronously, we are
6240 * calling check_nested_events again here to avoid a race condition.
6241 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6242 * proposal and current concerns. Perhaps we should be setting
6243 * KVM_REQ_EVENT only on certain events and not unconditionally?
6244 */
6245 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6246 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6247 if (r != 0)
6248 return r;
6249 }
95ba8273 6250 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6251 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6252 false);
6253 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6254 }
6255 }
b6b8a145 6256 return 0;
95ba8273
GN		 6257}
6258
7460fb4a
AK		 6259static void process_nmi(struct kvm_vcpu *vcpu)
6260{
6261 unsigned limit = 2;
6262
6263 /*
6264 * x86 is limited to one NMI running, and one NMI pending after it.
6265 * If an NMI is already in progress, limit further NMIs to just one.
6266 * Otherwise, allow two (and we'll inject the first one immediately).
6267 */
6268 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6269 limit = 1;
6270
6271 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6272 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6273 kvm_make_request(KVM_REQ_EVENT, vcpu);
6274}
6275
3d81bc7e 6276static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6277{
6278 u64 eoi_exit_bitmap[4];
cf9e65b7 6279 u32 tmr[8];
c7c9c56c 6280
3d81bc7e
YZ		 6281 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6282 return;
c7c9c56c
YZ		 6283
6284 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6285 memset(tmr, 0, 32);
c7c9c56c 6286
cf9e65b7 6287 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6288 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6289 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6290}
6291
a70656b6
RK		 6292static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6293{
6294 ++vcpu->stat.tlb_flush;
6295 kvm_x86_ops->tlb_flush(vcpu);
6296}
6297
4256f43f
TC		 6298void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6299{
c24ae0dc
TC		 6300 struct page *page = NULL;
6301
f439ed27
PB		 6302 if (!irqchip_in_kernel(vcpu->kvm))
6303 return;
6304
4256f43f
TC		 6305 if (!kvm_x86_ops->set_apic_access_page_addr)
6306 return;
6307
c24ae0dc 6308 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6309 if (is_error_page(page))
6310 return;
c24ae0dc
TC		 6311 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6312
6313 /*
6314 * Do not pin apic access page in memory, the MMU notifier
6315 * will call us again if it is migrated or swapped out.
6316 */
6317 put_page(page);
4256f43f
TC		 6318}
6319EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6320
fe71557a
TC		 6321void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6322 unsigned long address)
6323{
c24ae0dc
TC		 6324 /*
6325 * The physical address of apic access page is stored in the VMCS.
6326 * Update it when it becomes invalid.
6327 */
6328 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6329 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6330}
6331
9357d939 6332/*
362c698f 6333 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6334 * exiting to the userspace. Otherwise, the value will be returned to the
6335 * userspace.
6336 */
851ba692 6337static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6338{
6339 int r;
6a8b1d13 6340 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6341 vcpu->run->request_interrupt_window;
730dca42 6342 bool req_immediate_exit = false;
b6c7a5dc 6343
3e007509 6344 if (vcpu->requests) {
a8eeb04a 6345 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6346 kvm_mmu_unload(vcpu);
a8eeb04a 6347 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6348 __kvm_migrate_timers(vcpu);
d828199e
MT		 6349 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6350 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6351 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6352 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6353 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6354 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6355 if (unlikely(r))
6356 goto out;
6357 }
a8eeb04a 6358 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6359 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6360 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6361 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6362 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6363 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6364 r = 0;
6365 goto out;
6366 }
a8eeb04a 6367 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6368 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6369 r = 0;
6370 goto out;
6371 }
a8eeb04a 6372 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6373 vcpu->fpu_active = 0;
6374 kvm_x86_ops->fpu_deactivate(vcpu);
6375 }
af585b92
GN		 6376 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6377 /* Page is swapped out. Do synthetic halt */
6378 vcpu->arch.apf.halted = true;
6379 r = 1;
6380 goto out;
6381 }
c9aaa895
GC		 6382 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6383 record_steal_time(vcpu);
7460fb4a
AK		 6384 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6385 process_nmi(vcpu);
f5132b01
GN		 6386 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6387 kvm_handle_pmu_event(vcpu);
6388 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6389 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6390 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6391 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6392 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6393 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6394 }
b93463aa 6395
b463a6f7 6396 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6397 kvm_apic_accept_events(vcpu);
6398 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6399 r = 1;
6400 goto out;
6401 }
6402
b6b8a145
JK		 6403 if (inject_pending_event(vcpu, req_int_win) != 0)
6404 req_immediate_exit = true;
b463a6f7 6405 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6406 else if (vcpu->arch.nmi_pending)
c9a7953f 6407 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6408 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6409 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6410
6411 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6412 /*
6413 * Update architecture specific hints for APIC
6414 * virtual interrupt delivery.
6415 */
6416 if (kvm_x86_ops->hwapic_irr_update)
6417 kvm_x86_ops->hwapic_irr_update(vcpu,
6418 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6419 update_cr8_intercept(vcpu);
6420 kvm_lapic_sync_to_vapic(vcpu);
6421 }
6422 }
6423
d8368af8
AK		 6424 r = kvm_mmu_reload(vcpu);
6425 if (unlikely(r)) {
d905c069 6426 goto cancel_injection;
d8368af8
AK		 6427 }
6428
b6c7a5dc
HB		 6429 preempt_disable();
6430
6431 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6432 if (vcpu->fpu_active)
6433 kvm_load_guest_fpu(vcpu);
2acf923e 6434 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6435
6b7e2d09
XG		 6436 vcpu->mode = IN_GUEST_MODE;
6437
01b71917
MT		 6438 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6439
6b7e2d09
XG		 6440 /* We should set ->mode before check ->requests,
6441 * see the comment in make_all_cpus_request.
6442 */
01b71917 6443 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6444
d94e1dc9 6445 local_irq_disable();
32f88400 6446
6b7e2d09 6447 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6448 || need_resched() || signal_pending(current)) {
6b7e2d09 6449 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6450 smp_wmb();
6c142801
AK		 6451 local_irq_enable();
6452 preempt_enable();
01b71917 6453 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6454 r = 1;
d905c069 6455 goto cancel_injection;
6c142801
AK		 6456 }
6457
d6185f20
NHE		 6458 if (req_immediate_exit)
6459 smp_send_reschedule(vcpu->cpu);
6460
ccf73aaf 6461 __kvm_guest_enter();
b6c7a5dc 6462
42dbaa5a 6463 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6464 set_debugreg(0, 7);
6465 set_debugreg(vcpu->arch.eff_db[0], 0);
6466 set_debugreg(vcpu->arch.eff_db[1], 1);
6467 set_debugreg(vcpu->arch.eff_db[2], 2);
6468 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6469 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6470 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6471 }
b6c7a5dc 6472
229456fc 6473 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6474 wait_lapic_expire(vcpu);
851ba692 6475 kvm_x86_ops->run(vcpu);
b6c7a5dc 6476
c77fb5fe
PB		 6477 /*
6478 * Do this here before restoring debug registers on the host. And
6479 * since we do this before handling the vmexit, a DR access vmexit
6480 * can (a) read the correct value of the debug registers, (b) set
6481 * KVM_DEBUGREG_WONT_EXIT again.
6482 */
6483 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6484 int i;
6485
6486 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6487 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6488 for (i = 0; i < KVM_NR_DB_REGS; i++)
6489 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6490 }
6491
24f1e32c
FW		 6492 /*
6493 * If the guest has used debug registers, at least dr7
6494 * will be disabled while returning to the host.
6495 * If we don't have active breakpoints in the host, we don't
6496 * care about the messed up debug address registers. But if
6497 * we have some of them active, restore the old state.
6498 */
59d8eb53 6499 if (hw_breakpoint_active())
24f1e32c 6500 hw_breakpoint_restore();
42dbaa5a 6501
886b470c
MT		 6502 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6503 native_read_tsc());
1d5f066e 6504
6b7e2d09 6505 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6506 smp_wmb();
a547c6db
YZ		 6507
6508 /* Interrupt is enabled by handle_external_intr() */
6509 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6510
6511 ++vcpu->stat.exits;
6512
6513 /*
6514 * We must have an instruction between local_irq_enable() and
6515 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6516 * the interrupt shadow. The stat.exits increment will do nicely.
6517 * But we need to prevent reordering, hence this barrier():
6518 */
6519 barrier();
6520
6521 kvm_guest_exit();
6522
6523 preempt_enable();
6524
f656ce01 6525 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6526
b6c7a5dc
HB		 6527 /*
6528 * Profile KVM exit RIPs:
6529 */
6530 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6531 unsigned long rip = kvm_rip_read(vcpu);
6532 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6533 }
6534
cc578287
ZA		 6535 if (unlikely(vcpu->arch.tsc_always_catchup))
6536 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6537
5cfb1d5a
MT		 6538 if (vcpu->arch.apic_attention)
6539 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6540
851ba692 6541 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6542 return r;
6543
6544cancel_injection:
6545 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6546 if (unlikely(vcpu->arch.apic_attention))
6547 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6548out:
6549 return r;
6550}
b6c7a5dc 6551
362c698f
PB		 6552static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6553{
9c8fd1ba
PB		 6554 if (!kvm_arch_vcpu_runnable(vcpu)) {
6555 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6556 kvm_vcpu_block(vcpu);
6557 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6558 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6559 return 1;
6560 }
362c698f
PB		 6561
6562 kvm_apic_accept_events(vcpu);
6563 switch(vcpu->arch.mp_state) {
6564 case KVM_MP_STATE_HALTED:
6565 vcpu->arch.pv.pv_unhalted = false;
6566 vcpu->arch.mp_state =
6567 KVM_MP_STATE_RUNNABLE;
6568 case KVM_MP_STATE_RUNNABLE:
6569 vcpu->arch.apf.halted = false;
6570 break;
6571 case KVM_MP_STATE_INIT_RECEIVED:
6572 break;
6573 default:
6574 return -EINTR;
6575 break;
6576 }
6577 return 1;
6578}
09cec754 6579
362c698f 6580static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6581{
6582 int r;
f656ce01 6583 struct kvm *kvm = vcpu->kvm;
d7690175 6584
f656ce01 6585 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6586
362c698f 6587 for (;;) {
af585b92
GN		 6588 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6589 !vcpu->arch.apf.halted)
851ba692 6590 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6591 else
6592 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6593 if (r <= 0)
6594 break;
6595
6596 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6597 if (kvm_cpu_has_pending_timer(vcpu))
6598 kvm_inject_pending_timer_irqs(vcpu);
6599
851ba692 6600 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6601 r = -EINTR;
851ba692 6602 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6603 ++vcpu->stat.request_irq_exits;
362c698f 6604 break;
09cec754 6605 }
af585b92
GN		 6606
6607 kvm_check_async_pf_completion(vcpu);
6608
09cec754
GN		 6609 if (signal_pending(current)) {
6610 r = -EINTR;
851ba692 6611 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6612 ++vcpu->stat.signal_exits;
362c698f 6613 break;
09cec754
GN		 6614 }
6615 if (need_resched()) {
f656ce01 6616 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6617 cond_resched();
f656ce01 6618 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6619 }
b6c7a5dc
HB		 6620 }
6621
f656ce01 6622 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6623
6624 return r;
6625}
6626
716d51ab
GN		 6627static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6628{
6629 int r;
6630 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6631 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6632 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6633 if (r != EMULATE_DONE)
6634 return 0;
6635 return 1;
6636}
6637
6638static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6639{
6640 BUG_ON(!vcpu->arch.pio.count);
6641
6642 return complete_emulated_io(vcpu);
6643}
6644
f78146b0
AK		 6645/*
6646 * Implements the following, as a state machine:
6647 *
6648 * read:
6649 * for each fragment
87da7e66
XG		 6650 * for each mmio piece in the fragment
6651 * write gpa, len
6652 * exit
6653 * copy data
f78146b0
AK		 6654 * execute insn
6655 *
6656 * write:
6657 * for each fragment
87da7e66
XG		 6658 * for each mmio piece in the fragment
6659 * write gpa, len
6660 * copy data
6661 * exit
f78146b0 6662 */
716d51ab 6663static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6664{
6665 struct kvm_run *run = vcpu->run;
f78146b0 6666 struct kvm_mmio_fragment *frag;
87da7e66 6667 unsigned len;
5287f194 6668
716d51ab 6669 BUG_ON(!vcpu->mmio_needed);
5287f194 6670
716d51ab 6671 /* Complete previous fragment */
87da7e66
XG		 6672 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6673 len = min(8u, frag->len);
716d51ab 6674 if (!vcpu->mmio_is_write)
87da7e66
XG		 6675 memcpy(frag->data, run->mmio.data, len);
6676
6677 if (frag->len <= 8) {
6678 /* Switch to the next fragment. */
6679 frag++;
6680 vcpu->mmio_cur_fragment++;
6681 } else {
6682 /* Go forward to the next mmio piece. */
6683 frag->data += len;
6684 frag->gpa += len;
6685 frag->len -= len;
6686 }
6687
a08d3b3b 6688 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6689 vcpu->mmio_needed = 0;
0912c977
PB		 6690
6691 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6692 if (vcpu->mmio_is_write)
716d51ab
GN		 6693 return 1;
6694 vcpu->mmio_read_completed = 1;
6695 return complete_emulated_io(vcpu);
6696 }
87da7e66 6697
716d51ab
GN		 6698 run->exit_reason = KVM_EXIT_MMIO;
6699 run->mmio.phys_addr = frag->gpa;
6700 if (vcpu->mmio_is_write)
87da7e66
XG		 6701 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6702 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6703 run->mmio.is_write = vcpu->mmio_is_write;
6704 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6705 return 0;
5287f194
AK		 6706}
6707
716d51ab 6708
b6c7a5dc
HB		 6709int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6710{
6711 int r;
6712 sigset_t sigsaved;
6713
e5c30142
AK		 6714 if (!tsk_used_math(current) && init_fpu(current))
6715 return -ENOMEM;
6716
ac9f6dc0
AK		 6717 if (vcpu->sigset_active)
6718 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6719
a4535290 6720 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6721 kvm_vcpu_block(vcpu);
66450a21 6722 kvm_apic_accept_events(vcpu);
d7690175 6723 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6724 r = -EAGAIN;
6725 goto out;
b6c7a5dc
HB		 6726 }
6727
b6c7a5dc 6728 /* re-sync apic's tpr */
eea1cff9
AP		 6729 if (!irqchip_in_kernel(vcpu->kvm)) {
6730 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6731 r = -EINVAL;
6732 goto out;
6733 }
6734 }
b6c7a5dc 6735
716d51ab
GN		 6736 if (unlikely(vcpu->arch.complete_userspace_io)) {
6737 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6738 vcpu->arch.complete_userspace_io = NULL;
6739 r = cui(vcpu);
6740 if (r <= 0)
6741 goto out;
6742 } else
6743 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6744
362c698f 6745 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6746
6747out:
f1d86e46 6748 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6749 if (vcpu->sigset_active)
6750 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6751
b6c7a5dc
HB		 6752 return r;
6753}
6754
6755int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6756{
7ae441ea
GN		 6757 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6758 /*
6759 * We are here if userspace calls get_regs() in the middle of
6760 * instruction emulation. Registers state needs to be copied
4a969980 6761 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6762 * that usually, but some bad designed PV devices (vmware
6763 * backdoor interface) need this to work
6764 */
dd856efa 6765 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6766 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6767 }
5fdbf976
MT		 6768 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6769 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6770 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6771 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6772 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6773 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6774 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6775 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6776#ifdef CONFIG_X86_64
5fdbf976
MT		 6777 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6778 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6779 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6780 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6781 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6782 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6783 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6784 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6785#endif
6786
5fdbf976 6787 regs->rip = kvm_rip_read(vcpu);
91586a3b 6788 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6789
b6c7a5dc
HB		 6790 return 0;
6791}
6792
6793int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6794{
7ae441ea
GN		 6795 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6796 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6797
5fdbf976
MT		 6798 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6799 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6800 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6801 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6802 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6803 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6804 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6805 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6806#ifdef CONFIG_X86_64
5fdbf976
MT		 6807 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6808 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6809 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6810 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6811 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6812 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6813 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6814 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6815#endif
6816
5fdbf976 6817 kvm_rip_write(vcpu, regs->rip);
91586a3b 6818 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6819
b4f14abd
JK		 6820 vcpu->arch.exception.pending = false;
6821
3842d135
AK		 6822 kvm_make_request(KVM_REQ_EVENT, vcpu);
6823
b6c7a5dc
HB		 6824 return 0;
6825}
6826
b6c7a5dc
HB		 6827void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6828{
6829 struct kvm_segment cs;
6830
3e6e0aab 6831 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6832 *db = cs.db;
6833 *l = cs.l;
6834}
6835EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6836
6837int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6838 struct kvm_sregs *sregs)
6839{
89a27f4d 6840 struct desc_ptr dt;
b6c7a5dc 6841
3e6e0aab
GT		 6842 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6843 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6844 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6845 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6846 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6847 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6848
3e6e0aab
GT		 6849 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6850 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6851
6852 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6853 sregs->idt.limit = dt.size;
6854 sregs->idt.base = dt.address;
b6c7a5dc 6855 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6856 sregs->gdt.limit = dt.size;
6857 sregs->gdt.base = dt.address;
b6c7a5dc 6858
4d4ec087 6859 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6860 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6861 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6862 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6863 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6864 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6865 sregs->apic_base = kvm_get_apic_base(vcpu);
6866
923c61bb 6867 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6868
36752c9b 6869 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6870 set_bit(vcpu->arch.interrupt.nr,
6871 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6872
b6c7a5dc
HB		 6873 return 0;
6874}
6875
62d9f0db
MT		 6876int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6877 struct kvm_mp_state *mp_state)
6878{
66450a21 6879 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6880 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6881 vcpu->arch.pv.pv_unhalted)
6882 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6883 else
6884 mp_state->mp_state = vcpu->arch.mp_state;
6885
62d9f0db
MT		 6886 return 0;
6887}
6888
6889int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6890 struct kvm_mp_state *mp_state)
6891{
66450a21
JK		 6892 if (!kvm_vcpu_has_lapic(vcpu) &&
6893 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6894 return -EINVAL;
6895
6896 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6897 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6898 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6899 } else
6900 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6901 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6902 return 0;
6903}
6904
7f3d35fd
KW		 6905int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6906 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6907{
9d74191a 6908 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6909 int ret;
e01c2426 6910
8ec4722d 6911 init_emulate_ctxt(vcpu);
c697518a 6912
7f3d35fd 6913 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6914 has_error_code, error_code);
c697518a 6915
c697518a 6916 if (ret)
19d04437 6917 return EMULATE_FAIL;
37817f29 6918
9d74191a
TY		 6919 kvm_rip_write(vcpu, ctxt->eip);
6920 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6921 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6922 return EMULATE_DONE;
37817f29
IE		 6923}
6924EXPORT_SYMBOL_GPL(kvm_task_switch);
6925
b6c7a5dc
HB		 6926int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6927 struct kvm_sregs *sregs)
6928{
58cb628d 6929 struct msr_data apic_base_msr;
b6c7a5dc 6930 int mmu_reset_needed = 0;
63f42e02 6931 int pending_vec, max_bits, idx;
89a27f4d 6932 struct desc_ptr dt;
b6c7a5dc 6933
6d1068b3
PM		 6934 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6935 return -EINVAL;
6936
89a27f4d
GN		 6937 dt.size = sregs->idt.limit;
6938 dt.address = sregs->idt.base;
b6c7a5dc 6939 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6940 dt.size = sregs->gdt.limit;
6941 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6942 kvm_x86_ops->set_gdt(vcpu, &dt);
6943
ad312c7c 6944 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6945 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6946 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6947 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6948
2d3ad1f4 6949 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6950
f6801dff 6951 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6952 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6953 apic_base_msr.data = sregs->apic_base;
6954 apic_base_msr.host_initiated = true;
6955 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6956
4d4ec087 6957 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6958 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6959 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6960
fc78f519 6961 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6962 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6963 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6964 kvm_update_cpuid(vcpu);
63f42e02
XG		 6965
6966 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6967 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6968 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6969 mmu_reset_needed = 1;
6970 }
63f42e02 6971 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6972
6973 if (mmu_reset_needed)
6974 kvm_mmu_reset_context(vcpu);
6975
a50abc3b 6976 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6977 pending_vec = find_first_bit(
6978 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6979 if (pending_vec < max_bits) {
66fd3f7f 6980 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6981 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6982 }
6983
3e6e0aab
GT		 6984 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6985 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6986 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6987 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6988 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6989 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6990
3e6e0aab
GT		 6991 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6992 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6993
5f0269f5
ME		 6994 update_cr8_intercept(vcpu);
6995
9c3e4aab 6996 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6997 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6998 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6999 !is_protmode(vcpu))
9c3e4aab
MT		 7000 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7001
3842d135
AK		 7002 kvm_make_request(KVM_REQ_EVENT, vcpu);
7003
b6c7a5dc
HB		 7004 return 0;
7005}
7006
d0bfb940
JK		 7007int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7008 struct kvm_guest_debug *dbg)
b6c7a5dc 7009{
355be0b9 7010 unsigned long rflags;
ae675ef0 7011 int i, r;
b6c7a5dc 7012
4f926bf2
JK		 7013 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7014 r = -EBUSY;
7015 if (vcpu->arch.exception.pending)
2122ff5e 7016 goto out;
4f926bf2
JK		 7017 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7018 kvm_queue_exception(vcpu, DB_VECTOR);
7019 else
7020 kvm_queue_exception(vcpu, BP_VECTOR);
7021 }
7022
91586a3b
JK		 7023 /*
7024 * Read rflags as long as potentially injected trace flags are still
7025 * filtered out.
7026 */
7027 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7028
7029 vcpu->guest_debug = dbg->control;
7030 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7031 vcpu->guest_debug = 0;
7032
7033 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7034 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7035 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7036 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7037 } else {
7038 for (i = 0; i < KVM_NR_DB_REGS; i++)
7039 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7040 }
c8639010 7041 kvm_update_dr7(vcpu);
ae675ef0 7042
f92653ee
JK		 7043 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7044 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7045 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7046
91586a3b
JK		 7047 /*
7048 * Trigger an rflags update that will inject or remove the trace
7049 * flags.
7050 */
7051 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7052
c8639010 7053 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7054
4f926bf2 7055 r = 0;
d0bfb940 7056
2122ff5e 7057out:
b6c7a5dc
HB		 7058
7059 return r;
7060}
7061
8b006791
ZX		 7062/*
7063 * Translate a guest virtual address to a guest physical address.
7064 */
7065int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7066 struct kvm_translation *tr)
7067{
7068 unsigned long vaddr = tr->linear_address;
7069 gpa_t gpa;
f656ce01 7070 int idx;
8b006791 7071
f656ce01 7072 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7073 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7074 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7075 tr->physical_address = gpa;
7076 tr->valid = gpa != UNMAPPED_GVA;
7077 tr->writeable = 1;
7078 tr->usermode = 0;
8b006791
ZX		 7079
7080 return 0;
7081}
7082
d0752060
HB		 7083int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7084{
98918833
SY		 7085 struct i387_fxsave_struct *fxsave =
7086 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7087
d0752060
HB		 7088 memcpy(fpu->fpr, fxsave->st_space, 128);
7089 fpu->fcw = fxsave->cwd;
7090 fpu->fsw = fxsave->swd;
7091 fpu->ftwx = fxsave->twd;
7092 fpu->last_opcode = fxsave->fop;
7093 fpu->last_ip = fxsave->rip;
7094 fpu->last_dp = fxsave->rdp;
7095 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7096
d0752060
HB		 7097 return 0;
7098}
7099
7100int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7101{
98918833
SY		 7102 struct i387_fxsave_struct *fxsave =
7103 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7104
d0752060
HB		 7105 memcpy(fxsave->st_space, fpu->fpr, 128);
7106 fxsave->cwd = fpu->fcw;
7107 fxsave->swd = fpu->fsw;
7108 fxsave->twd = fpu->ftwx;
7109 fxsave->fop = fpu->last_opcode;
7110 fxsave->rip = fpu->last_ip;
7111 fxsave->rdp = fpu->last_dp;
7112 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7113
d0752060
HB		 7114 return 0;
7115}
7116
d28bc9dd 7117int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7118{
10ab25cd
JK		 7119 int err;
7120
7121 err = fpu_alloc(&vcpu->arch.guest_fpu);
7122 if (err)
7123 return err;
7124
d28bc9dd
NA		 7125 if (!init_event)
7126 fpu_finit(&vcpu->arch.guest_fpu);
7127
df1daba7
PB		 7128 if (cpu_has_xsaves)
7129 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7130 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7131
2acf923e
DC		 7132 /*
7133 * Ensure guest xcr0 is valid for loading
7134 */
7135 vcpu->arch.xcr0 = XSTATE_FP;
7136
ad312c7c 7137 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7138
7139 return 0;
d0752060
HB		 7140}
7141EXPORT_SYMBOL_GPL(fx_init);
7142
98918833
SY		 7143static void fx_free(struct kvm_vcpu *vcpu)
7144{
7145 fpu_free(&vcpu->arch.guest_fpu);
7146}
7147
d0752060
HB		 7148void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7149{
2608d7a1 7150 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7151 return;
7152
2acf923e
DC		 7153 /*
7154 * Restore all possible states in the guest,
7155 * and assume host would use all available bits.
7156 * Guest xcr0 would be loaded later.
7157 */
7158 kvm_put_guest_xcr0(vcpu);
d0752060 7159 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7160 __kernel_fpu_begin();
98918833 7161 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7162 trace_kvm_fpu(1);
d0752060 7163}
d0752060
HB		 7164
7165void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7166{
2acf923e
DC		 7167 kvm_put_guest_xcr0(vcpu);
7168
653f52c3
RR		 7169 if (!vcpu->guest_fpu_loaded) {
7170 vcpu->fpu_counter = 0;
d0752060 7171 return;
653f52c3 7172 }
d0752060
HB		 7173
7174 vcpu->guest_fpu_loaded = 0;
98918833 7175 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7176 __kernel_fpu_end();
f096ed85 7177 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7178 /*
7179 * If using eager FPU mode, or if the guest is a frequent user
7180 * of the FPU, just leave the FPU active for next time.
7181 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7182 * the FPU in bursts will revert to loading it on demand.
7183 */
a9b4fb7e 7184 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7185 if (++vcpu->fpu_counter < 5)
7186 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7187 }
0c04851c 7188 trace_kvm_fpu(0);
d0752060 7189}
e9b11c17
ZX		 7190
7191void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7192{
12f9a48f 7193 kvmclock_reset(vcpu);
7f1ea208 7194
f5f48ee1 7195 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7196 fx_free(vcpu);
e9b11c17
ZX		 7197 kvm_x86_ops->vcpu_free(vcpu);
7198}
7199
7200struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7201 unsigned int id)
7202{
c447e76b
LL		 7203 struct kvm_vcpu *vcpu;
7204
6755bae8
ZA		 7205 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7206 printk_once(KERN_WARNING
7207 "kvm: SMP vm created on host with unstable TSC; "
7208 "guest TSC will not be reliable\n");
c447e76b
LL		 7209
7210 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7211
7212 /*
7213 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7214 * deactivated soon if it doesn't.
7215 */
7216 kvm_x86_ops->fpu_activate(vcpu);
7217 return vcpu;
26e5215f 7218}
e9b11c17 7219
26e5215f
AK		 7220int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7221{
7222 int r;
e9b11c17 7223
0bed3b56 7224 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7225 r = vcpu_load(vcpu);
7226 if (r)
7227 return r;
d28bc9dd 7228 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7229 kvm_mmu_setup(vcpu);
e9b11c17 7230 vcpu_put(vcpu);
e9b11c17 7231
26e5215f 7232 return r;
e9b11c17
ZX		 7233}
7234
31928aa5 7235void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7236{
8fe8ab46 7237 struct msr_data msr;
332967a3 7238 struct kvm *kvm = vcpu->kvm;
42897d86 7239
31928aa5
DD		 7240 if (vcpu_load(vcpu))
7241 return;
8fe8ab46
WA		 7242 msr.data = 0x0;
7243 msr.index = MSR_IA32_TSC;
7244 msr.host_initiated = true;
7245 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7246 vcpu_put(vcpu);
7247
630994b3
MT		 7248 if (!kvmclock_periodic_sync)
7249 return;
7250
332967a3
AJ		 7251 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7252 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7253}
7254
d40ccc62 7255void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7256{
9fc77441 7257 int r;
344d9588
GN		 7258 vcpu->arch.apf.msr_val = 0;
7259
9fc77441
MT		 7260 r = vcpu_load(vcpu);
7261 BUG_ON(r);
e9b11c17
ZX		 7262 kvm_mmu_unload(vcpu);
7263 vcpu_put(vcpu);
7264
98918833 7265 fx_free(vcpu);
e9b11c17
ZX		 7266 kvm_x86_ops->vcpu_free(vcpu);
7267}
7268
d28bc9dd 7269void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7270{
e69fab5d
PB		 7271 vcpu->arch.hflags = 0;
7272
7460fb4a
AK		 7273 atomic_set(&vcpu->arch.nmi_queued, 0);
7274 vcpu->arch.nmi_pending = 0;
448fa4a9 7275 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7276 kvm_clear_interrupt_queue(vcpu);
7277 kvm_clear_exception_queue(vcpu);
448fa4a9 7278
42dbaa5a 7279 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7280 kvm_update_dr0123(vcpu);
6f43ed01 7281 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7282 kvm_update_dr6(vcpu);
42dbaa5a 7283 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7284 kvm_update_dr7(vcpu);
42dbaa5a 7285
1119022c
NA		 7286 vcpu->arch.cr2 = 0;
7287
3842d135 7288 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7289 vcpu->arch.apf.msr_val = 0;
c9aaa895 7290 vcpu->arch.st.msr_val = 0;
3842d135 7291
12f9a48f
GC		 7292 kvmclock_reset(vcpu);
7293
af585b92
GN		 7294 kvm_clear_async_pf_completion_queue(vcpu);
7295 kvm_async_pf_hash_reset(vcpu);
7296 vcpu->arch.apf.halted = false;
3842d135 7297
d28bc9dd
NA		 7298 if (!init_event)
7299 kvm_pmu_reset(vcpu);
f5132b01 7300
66f7b72e
JS		 7301 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7302 vcpu->arch.regs_avail = ~0;
7303 vcpu->arch.regs_dirty = ~0;
7304
d28bc9dd 7305 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7306}
7307
2b4a273b 7308void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7309{
7310 struct kvm_segment cs;
7311
7312 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7313 cs.selector = vector << 8;
7314 cs.base = vector << 12;
7315 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7316 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7317}
7318
13a34e06 7319int kvm_arch_hardware_enable(void)
e9b11c17 7320{
ca84d1a2
ZA		 7321 struct kvm *kvm;
7322 struct kvm_vcpu *vcpu;
7323 int i;
0dd6a6ed
ZA		 7324 int ret;
7325 u64 local_tsc;
7326 u64 max_tsc = 0;
7327 bool stable, backwards_tsc = false;
18863bdd
AK		 7328
7329 kvm_shared_msr_cpu_online();
13a34e06 7330 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7331 if (ret != 0)
7332 return ret;
7333
7334 local_tsc = native_read_tsc();
7335 stable = !check_tsc_unstable();
7336 list_for_each_entry(kvm, &vm_list, vm_list) {
7337 kvm_for_each_vcpu(i, vcpu, kvm) {
7338 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7339 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7340 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7341 backwards_tsc = true;
7342 if (vcpu->arch.last_host_tsc > max_tsc)
7343 max_tsc = vcpu->arch.last_host_tsc;
7344 }
7345 }
7346 }
7347
7348 /*
7349 * Sometimes, even reliable TSCs go backwards. This happens on
7350 * platforms that reset TSC during suspend or hibernate actions, but
7351 * maintain synchronization. We must compensate. Fortunately, we can
7352 * detect that condition here, which happens early in CPU bringup,
7353 * before any KVM threads can be running. Unfortunately, we can't
7354 * bring the TSCs fully up to date with real time, as we aren't yet far
7355 * enough into CPU bringup that we know how much real time has actually
7356 * elapsed; our helper function, get_kernel_ns() will be using boot
7357 * variables that haven't been updated yet.
7358 *
7359 * So we simply find the maximum observed TSC above, then record the
7360 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7361 * the adjustment will be applied. Note that we accumulate
7362 * adjustments, in case multiple suspend cycles happen before some VCPU
7363 * gets a chance to run again. In the event that no KVM threads get a
7364 * chance to run, we will miss the entire elapsed period, as we'll have
7365 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7366 * loose cycle time. This isn't too big a deal, since the loss will be
7367 * uniform across all VCPUs (not to mention the scenario is extremely
7368 * unlikely). It is possible that a second hibernate recovery happens
7369 * much faster than a first, causing the observed TSC here to be
7370 * smaller; this would require additional padding adjustment, which is
7371 * why we set last_host_tsc to the local tsc observed here.
7372 *
7373 * N.B. - this code below runs only on platforms with reliable TSC,
7374 * as that is the only way backwards_tsc is set above. Also note
7375 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7376 * have the same delta_cyc adjustment applied if backwards_tsc
7377 * is detected. Note further, this adjustment is only done once,
7378 * as we reset last_host_tsc on all VCPUs to stop this from being
7379 * called multiple times (one for each physical CPU bringup).
7380 *
4a969980 7381 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7382 * will be compensated by the logic in vcpu_load, which sets the TSC to
7383 * catchup mode. This will catchup all VCPUs to real time, but cannot
7384 * guarantee that they stay in perfect synchronization.
7385 */
7386 if (backwards_tsc) {
7387 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7388 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7389 list_for_each_entry(kvm, &vm_list, vm_list) {
7390 kvm_for_each_vcpu(i, vcpu, kvm) {
7391 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7392 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7393 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7394 }
7395
7396 /*
7397 * We have to disable TSC offset matching.. if you were
7398 * booting a VM while issuing an S4 host suspend....
7399 * you may have some problem. Solving this issue is
7400 * left as an exercise to the reader.
7401 */
7402 kvm->arch.last_tsc_nsec = 0;
7403 kvm->arch.last_tsc_write = 0;
7404 }
7405
7406 }
7407 return 0;
e9b11c17
ZX		 7408}
7409
13a34e06 7410void kvm_arch_hardware_disable(void)
e9b11c17 7411{
13a34e06
RK		 7412 kvm_x86_ops->hardware_disable();
7413 drop_user_return_notifiers();
e9b11c17
ZX		 7414}
7415
7416int kvm_arch_hardware_setup(void)
7417{
9e9c3fe4
NA		 7418 int r;
7419
7420 r = kvm_x86_ops->hardware_setup();
7421 if (r != 0)
7422 return r;
7423
7424 kvm_init_msr_list();
7425 return 0;
e9b11c17
ZX		 7426}
7427
7428void kvm_arch_hardware_unsetup(void)
7429{
7430 kvm_x86_ops->hardware_unsetup();
7431}
7432
7433void kvm_arch_check_processor_compat(void *rtn)
7434{
7435 kvm_x86_ops->check_processor_compatibility(rtn);
7436}
7437
3e515705
AK		 7438bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7439{
7440 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7441}
7442
54e9818f
GN		 7443struct static_key kvm_no_apic_vcpu __read_mostly;
7444
e9b11c17
ZX		 7445int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7446{
7447 struct page *page;
7448 struct kvm *kvm;
7449 int r;
7450
7451 BUG_ON(vcpu->kvm == NULL);
7452 kvm = vcpu->kvm;
7453
6aef266c 7454 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7455 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7456 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7457 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7458 else
a4535290 7459 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7460
7461 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7462 if (!page) {
7463 r = -ENOMEM;
7464 goto fail;
7465 }
ad312c7c 7466 vcpu->arch.pio_data = page_address(page);
e9b11c17 7467
cc578287 7468 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7469
e9b11c17
ZX		 7470 r = kvm_mmu_create(vcpu);
7471 if (r < 0)
7472 goto fail_free_pio_data;
7473
7474 if (irqchip_in_kernel(kvm)) {
7475 r = kvm_create_lapic(vcpu);
7476 if (r < 0)
7477 goto fail_mmu_destroy;
54e9818f
GN		 7478 } else
7479 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7480
890ca9ae
HY		 7481 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7482 GFP_KERNEL);
7483 if (!vcpu->arch.mce_banks) {
7484 r = -ENOMEM;
443c39bc 7485 goto fail_free_lapic;
890ca9ae
HY		 7486 }
7487 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7488
f1797359
WY		 7489 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7490 r = -ENOMEM;
f5f48ee1 7491 goto fail_free_mce_banks;
f1797359 7492 }
f5f48ee1 7493
d28bc9dd 7494 r = fx_init(vcpu, false);
66f7b72e
JS		 7495 if (r)
7496 goto fail_free_wbinvd_dirty_mask;
7497
ba904635 7498 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7499 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7500
7501 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7502 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7503
5a4f55cd
EK		 7504 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7505
74545705
RK		 7506 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7507
af585b92 7508 kvm_async_pf_hash_reset(vcpu);
f5132b01 7509 kvm_pmu_init(vcpu);
af585b92 7510
e9b11c17 7511 return 0;
66f7b72e
JS		 7512fail_free_wbinvd_dirty_mask:
7513 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7514fail_free_mce_banks:
7515 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7516fail_free_lapic:
7517 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7518fail_mmu_destroy:
7519 kvm_mmu_destroy(vcpu);
7520fail_free_pio_data:
ad312c7c 7521 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7522fail:
7523 return r;
7524}
7525
7526void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7527{
f656ce01
MT		 7528 int idx;
7529
f5132b01 7530 kvm_pmu_destroy(vcpu);
36cb93fd 7531 kfree(vcpu->arch.mce_banks);
e9b11c17 7532 kvm_free_lapic(vcpu);
f656ce01 7533 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7534 kvm_mmu_destroy(vcpu);
f656ce01 7535 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7536 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7537 if (!irqchip_in_kernel(vcpu->kvm))
7538 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7539}
d19a9cd2 7540
e790d9ef
RK		 7541void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7542{
ae97a3b8 7543 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7544}
7545
e08b9637 7546int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7547{
e08b9637
CO		 7548 if (type)
7549 return -EINVAL;
7550
6ef768fa 7551 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7552 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7553 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7554 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7555 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7556
5550af4d
SY		 7557 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7558 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7559 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7560 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7561 &kvm->arch.irq_sources_bitmap);
5550af4d 7562
038f8c11 7563 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7564 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7565 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7566
7567 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7568
7e44e449 7569 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7570 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7571
d89f5eff 7572 return 0;
d19a9cd2
ZX		 7573}
7574
7575static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7576{
9fc77441
MT		 7577 int r;
7578 r = vcpu_load(vcpu);
7579 BUG_ON(r);
d19a9cd2
ZX		 7580 kvm_mmu_unload(vcpu);
7581 vcpu_put(vcpu);
7582}
7583
7584static void kvm_free_vcpus(struct kvm *kvm)
7585{
7586 unsigned int i;
988a2cae 7587 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7588
7589 /*
7590 * Unpin any mmu pages first.
7591 */
af585b92
GN		 7592 kvm_for_each_vcpu(i, vcpu, kvm) {
7593 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7594 kvm_unload_vcpu_mmu(vcpu);
af585b92 7595 }
988a2cae
GN		 7596 kvm_for_each_vcpu(i, vcpu, kvm)
7597 kvm_arch_vcpu_free(vcpu);
7598
7599 mutex_lock(&kvm->lock);
7600 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7601 kvm->vcpus[i] = NULL;
d19a9cd2 7602
988a2cae
GN		 7603 atomic_set(&kvm->online_vcpus, 0);
7604 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7605}
7606
ad8ba2cd
SY		 7607void kvm_arch_sync_events(struct kvm *kvm)
7608{
332967a3 7609 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7610 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7611 kvm_free_all_assigned_devices(kvm);
aea924f6 7612 kvm_free_pit(kvm);
ad8ba2cd
SY		 7613}
7614
d19a9cd2
ZX		 7615void kvm_arch_destroy_vm(struct kvm *kvm)
7616{
27469d29
AH		 7617 if (current->mm == kvm->mm) {
7618 /*
7619 * Free memory regions allocated on behalf of userspace,
7620 * unless the the memory map has changed due to process exit
7621 * or fd copying.
7622 */
7623 struct kvm_userspace_memory_region mem;
7624 memset(&mem, 0, sizeof(mem));
7625 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7626 kvm_set_memory_region(kvm, &mem);
7627
7628 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7629 kvm_set_memory_region(kvm, &mem);
7630
7631 mem.slot = TSS_PRIVATE_MEMSLOT;
7632 kvm_set_memory_region(kvm, &mem);
7633 }
6eb55818 7634 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7635 kfree(kvm->arch.vpic);
7636 kfree(kvm->arch.vioapic);
d19a9cd2 7637 kvm_free_vcpus(kvm);
1e08ec4a 7638 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7639}
0de10343 7640
5587027c 7641void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7642 struct kvm_memory_slot *dont)
7643{
7644 int i;
7645
d89cc617
TY		 7646 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7647 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7648 kvfree(free->arch.rmap[i]);
d89cc617 7649 free->arch.rmap[i] = NULL;
77d11309 7650 }
d89cc617
TY		 7651 if (i == 0)
7652 continue;
7653
7654 if (!dont || free->arch.lpage_info[i - 1] !=
7655 dont->arch.lpage_info[i - 1]) {
548ef284 7656 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7657 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7658 }
7659 }
7660}
7661
5587027c
AK		 7662int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7663 unsigned long npages)
db3fe4eb
TY		 7664{
7665 int i;
7666
d89cc617 7667 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7668 unsigned long ugfn;
7669 int lpages;
d89cc617 7670 int level = i + 1;
db3fe4eb
TY		 7671
7672 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7673 slot->base_gfn, level) + 1;
7674
d89cc617
TY		 7675 slot->arch.rmap[i] =
7676 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7677 if (!slot->arch.rmap[i])
77d11309 7678 goto out_free;
d89cc617
TY		 7679 if (i == 0)
7680 continue;
77d11309 7681
d89cc617
TY		 7682 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7683 sizeof(*slot->arch.lpage_info[i - 1]));
7684 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7685 goto out_free;
7686
7687 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7688 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7689 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7690 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7691 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7692 /*
7693 * If the gfn and userspace address are not aligned wrt each
7694 * other, or if explicitly asked to, disable large page
7695 * support for this slot
7696 */
7697 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7698 !kvm_largepages_enabled()) {
7699 unsigned long j;
7700
7701 for (j = 0; j < lpages; ++j)
d89cc617 7702 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7703 }
7704 }
7705
7706 return 0;
7707
7708out_free:
d89cc617 7709 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7710 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7711 slot->arch.rmap[i] = NULL;
7712 if (i == 0)
7713 continue;
7714
548ef284 7715 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7716 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7717 }
7718 return -ENOMEM;
7719}
7720
15f46015 7721void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7722{
e6dff7d1
TY		 7723 /*
7724 * memslots->generation has been incremented.
7725 * mmio generation may have reached its maximum value.
7726 */
7727 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7728}
7729
f7784b8e
MT		 7730int kvm_arch_prepare_memory_region(struct kvm *kvm,
7731 struct kvm_memory_slot *memslot,
09170a49 7732 const struct kvm_userspace_memory_region *mem,
7b6195a9 7733 enum kvm_mr_change change)
0de10343 7734{
7a905b14
TY		 7735 /*
7736 * Only private memory slots need to be mapped here since
7737 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7738 */
7b6195a9 7739 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7740 unsigned long userspace_addr;
604b38ac 7741
7a905b14
TY		 7742 /*
7743 * MAP_SHARED to prevent internal slot pages from being moved
7744 * by fork()/COW.
7745 */
7b6195a9 7746 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7747 PROT_READ | PROT_WRITE,
7748 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7749
7a905b14
TY		 7750 if (IS_ERR((void *)userspace_addr))
7751 return PTR_ERR((void *)userspace_addr);
604b38ac 7752
7a905b14 7753 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7754 }
7755
f7784b8e
MT		 7756 return 0;
7757}
7758
88178fd4
KH		 7759static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7760 struct kvm_memory_slot *new)
7761{
7762 /* Still write protect RO slot */
7763 if (new->flags & KVM_MEM_READONLY) {
7764 kvm_mmu_slot_remove_write_access(kvm, new);
7765 return;
7766 }
7767
7768 /*
7769 * Call kvm_x86_ops dirty logging hooks when they are valid.
7770 *
7771 * kvm_x86_ops->slot_disable_log_dirty is called when:
7772 *
7773 * - KVM_MR_CREATE with dirty logging is disabled
7774 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7775 *
7776 * The reason is, in case of PML, we need to set D-bit for any slots
7777 * with dirty logging disabled in order to eliminate unnecessary GPA
7778 * logging in PML buffer (and potential PML buffer full VMEXT). This
7779 * guarantees leaving PML enabled during guest's lifetime won't have
7780 * any additonal overhead from PML when guest is running with dirty
7781 * logging disabled for memory slots.
7782 *
7783 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7784 * to dirty logging mode.
7785 *
7786 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7787 *
7788 * In case of write protect:
7789 *
7790 * Write protect all pages for dirty logging.
7791 *
7792 * All the sptes including the large sptes which point to this
7793 * slot are set to readonly. We can not create any new large
7794 * spte on this slot until the end of the logging.
7795 *
7796 * See the comments in fast_page_fault().
7797 */
7798 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7799 if (kvm_x86_ops->slot_enable_log_dirty)
7800 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7801 else
7802 kvm_mmu_slot_remove_write_access(kvm, new);
7803 } else {
7804 if (kvm_x86_ops->slot_disable_log_dirty)
7805 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7806 }
7807}
7808
f7784b8e 7809void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7810 const struct kvm_userspace_memory_region *mem,
8482644a 7811 const struct kvm_memory_slot *old,
f36f3f28 7812 const struct kvm_memory_slot *new,
8482644a 7813 enum kvm_mr_change change)
f7784b8e 7814{
8482644a 7815 int nr_mmu_pages = 0;
f7784b8e 7816
f36f3f28 7817 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7818 int ret;
7819
8482644a
TY		 7820 ret = vm_munmap(old->userspace_addr,
7821 old->npages * PAGE_SIZE);
f7784b8e
MT		 7822 if (ret < 0)
7823 printk(KERN_WARNING
7824 "kvm_vm_ioctl_set_memory_region: "
7825 "failed to munmap memory\n");
7826 }
7827
48c0e4e9
XG		 7828 if (!kvm->arch.n_requested_mmu_pages)
7829 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7830
48c0e4e9 7831 if (nr_mmu_pages)
0de10343 7832 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7833
3ea3b7fa
WL		 7834 /*
7835 * Dirty logging tracks sptes in 4k granularity, meaning that large
7836 * sptes have to be split. If live migration is successful, the guest
7837 * in the source machine will be destroyed and large sptes will be
7838 * created in the destination. However, if the guest continues to run
7839 * in the source machine (for example if live migration fails), small
7840 * sptes will remain around and cause bad performance.
7841 *
7842 * Scan sptes if dirty logging has been stopped, dropping those
7843 * which can be collapsed into a single large-page spte. Later
7844 * page faults will create the large-page sptes.
7845 */
7846 if ((change != KVM_MR_DELETE) &&
7847 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7848 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7849 kvm_mmu_zap_collapsible_sptes(kvm, new);
7850
c972f3b1 7851 /*
88178fd4 7852 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7853 *
88178fd4
KH		 7854 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7855 * been zapped so no dirty logging staff is needed for old slot. For
7856 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7857 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7858 *
7859 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7860 */
88178fd4 7861 if (change != KVM_MR_DELETE)
f36f3f28 7862 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7863}
1d737c8a 7864
2df72e9b 7865void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7866{
6ca18b69 7867 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7868}
7869
2df72e9b
MT		 7870void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7871 struct kvm_memory_slot *slot)
7872{
6ca18b69 7873 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7874}
7875
1d737c8a
ZX		 7876int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7877{
b6b8a145
JK		 7878 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7879 kvm_x86_ops->check_nested_events(vcpu, false);
7880
af585b92
GN		 7881 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7882 !vcpu->arch.apf.halted)
7883 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7884 || kvm_apic_has_events(vcpu)
6aef266c 7885 || vcpu->arch.pv.pv_unhalted
7460fb4a 7886 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7887 (kvm_arch_interrupt_allowed(vcpu) &&
7888 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7889}
5736199a 7890
b6d33834 7891int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7892{
b6d33834 7893 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7894}
78646121
GN		 7895
7896int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7897{
7898 return kvm_x86_ops->interrupt_allowed(vcpu);
7899}
229456fc 7900
82b32774 7901unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7902{
82b32774
NA		 7903 if (is_64_bit_mode(vcpu))
7904 return kvm_rip_read(vcpu);
7905 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7906 kvm_rip_read(vcpu));
7907}
7908EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7909
82b32774
NA		 7910bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7911{
7912 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7913}
7914EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7915
94fe45da
JK		 7916unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7917{
7918 unsigned long rflags;
7919
7920 rflags = kvm_x86_ops->get_rflags(vcpu);
7921 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7922 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7923 return rflags;
7924}
7925EXPORT_SYMBOL_GPL(kvm_get_rflags);
7926
6addfc42 7927static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7928{
7929 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7930 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7931 rflags |= X86_EFLAGS_TF;
94fe45da 7932 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7933}
7934
7935void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7936{
7937 __kvm_set_rflags(vcpu, rflags);
3842d135 7938 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7939}
7940EXPORT_SYMBOL_GPL(kvm_set_rflags);
7941
56028d08
GN		 7942void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7943{
7944 int r;
7945
fb67e14f 7946 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7947 work->wakeup_all)
56028d08
GN		 7948 return;
7949
7950 r = kvm_mmu_reload(vcpu);
7951 if (unlikely(r))
7952 return;
7953
fb67e14f
XG		 7954 if (!vcpu->arch.mmu.direct_map &&
7955 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7956 return;
7957
56028d08
GN		 7958 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7959}
7960
af585b92
GN		 7961static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7962{
7963 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7964}
7965
7966static inline u32 kvm_async_pf_next_probe(u32 key)
7967{
7968 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7969}
7970
7971static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7972{
7973 u32 key = kvm_async_pf_hash_fn(gfn);
7974
7975 while (vcpu->arch.apf.gfns[key] != ~0)
7976 key = kvm_async_pf_next_probe(key);
7977
7978 vcpu->arch.apf.gfns[key] = gfn;
7979}
7980
7981static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7982{
7983 int i;
7984 u32 key = kvm_async_pf_hash_fn(gfn);
7985
7986 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7987 (vcpu->arch.apf.gfns[key] != gfn &&
7988 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7989 key = kvm_async_pf_next_probe(key);
7990
7991 return key;
7992}
7993
7994bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7995{
7996 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7997}
7998
7999static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8000{
8001 u32 i, j, k;
8002
8003 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8004 while (true) {
8005 vcpu->arch.apf.gfns[i] = ~0;
8006 do {
8007 j = kvm_async_pf_next_probe(j);
8008 if (vcpu->arch.apf.gfns[j] == ~0)
8009 return;
8010 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8011 /*
8012 * k lies cyclically in ]i,j]
8013 * | i.k.j |
8014 * |....j i.k.| or |.k..j i...|
8015 */
8016 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8017 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8018 i = j;
8019 }
8020}
8021
7c90705b
GN		 8022static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8023{
8024
8025 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8026 sizeof(val));
8027}
8028
af585b92
GN		 8029void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8030 struct kvm_async_pf *work)
8031{
6389ee94
AK		 8032 struct x86_exception fault;
8033
7c90705b 8034 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8035 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8036
8037 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8038 (vcpu->arch.apf.send_user_only &&
8039 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8040 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8041 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8042 fault.vector = PF_VECTOR;
8043 fault.error_code_valid = true;
8044 fault.error_code = 0;
8045 fault.nested_page_fault = false;
8046 fault.address = work->arch.token;
8047 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8048 }
af585b92
GN		 8049}
8050
8051void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8052 struct kvm_async_pf *work)
8053{
6389ee94
AK		 8054 struct x86_exception fault;
8055
7c90705b 8056 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8057 if (work->wakeup_all)
7c90705b
GN		 8058 work->arch.token = ~0; /* broadcast wakeup */
8059 else
8060 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8061
8062 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8063 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8064 fault.vector = PF_VECTOR;
8065 fault.error_code_valid = true;
8066 fault.error_code = 0;
8067 fault.nested_page_fault = false;
8068 fault.address = work->arch.token;
8069 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8070 }
e6d53e3b 8071 vcpu->arch.apf.halted = false;
a4fa1635 8072 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8073}
8074
8075bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8076{
8077 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8078 return true;
8079 else
8080 return !kvm_event_needs_reinjection(vcpu) &&
8081 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8082}
8083
e0f0bbc5
AW		 8084void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8085{
8086 atomic_inc(&kvm->arch.noncoherent_dma_count);
8087}
8088EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8089
8090void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8091{
8092 atomic_dec(&kvm->arch.noncoherent_dma_count);
8093}
8094EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8095
8096bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8097{
8098 return atomic_read(&kvm->arch.noncoherent_dma_count);
8099}
8100EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8101
229456fc
MT		 8102EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8103EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8104EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8105EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8106EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8107EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8108EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8109EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8110EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8111EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8112EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8113EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8114EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8115EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8116EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git