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Fix hash section entry size to match ELF standard. Override for alpha-linux.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
673388c0
AC		 1Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
2
3 * mips.igen (MxC1, DMxC1): Fix printf formatting.
4
4c0deff4
NC		 52000-05-24 Michael Hayes <mhayes@cygnus.com>
6
7 * mips.igen (do_dmultx): Fix typo.
8
eb2d80b4
AC		 9Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
10
11 * configure: Regenerated to track ../common/aclocal.m4 changes.
12
dd37a34b
AC		 13Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
14
15 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
16
4c0deff4
NC		 172000-04-12 Frank Ch. Eigler <fche@redhat.com>
18
19 * sim-main.h (GPR_CLEAR): Define macro.
20
e30db738
AC		 21Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
22
23 * interp.c (decode_coproc): Output long using %lx and not %s.
24
cb7450ea
FCE		 252000-03-21 Frank Ch. Eigler <fche@redhat.com>
26
27 * interp.c (sim_open): Sort & extend dummy memory regions for
28 --board=jmr3904 for eCos.
29
a3027dd7
FCE		 302000-03-02 Frank Ch. Eigler <fche@redhat.com>
31
32 * configure: Regenerated.
33
34Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
35
36 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
37 calls, conditional on the simulator being in verbose mode.
38
dfcd3bfb
JM		 39Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
40
41 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
42 cache don't get ReservedInstruction traps.
43
c2d11a7d
JM		 441999-11-29 Mark Salter <msalter@cygnus.com>
45
46 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
47 to clear status bits in sdisr register. This is how the hardware works.
48
49 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
50 being used by cygmon.
51
4ce44c66
JM		 521999-11-11 Andrew Haley <aph@cygnus.com>
53
54 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
55 instructions.
56
cff3e48b
JM		 57Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
58
59 * mips.igen (MULT): Correct previous mis-applied patch.
60
d4f3574e
SS		 61Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
62
63 * mips.igen (delayslot32): Handle sequence like
64 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
65 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
66 (MULT): Actually pass the third register...
67
681999-09-03 Mark Salter <msalter@cygnus.com>
69
70 * interp.c (sim_open): Added more memory aliases for additional
71 hardware being touched by cygmon on jmr3904 board.
72
73Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
74
75 * configure: Regenerated to track ../common/aclocal.m4 changes.
76
a0b3c4fd
JM		 77Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
78
79 * interp.c (sim_store_register): Handle case where client - GDB -
80 specifies that a 4 byte register is 8 bytes in size.
81 (sim_fetch_register): Ditto.
82
adf40b2e
JM		 831999-07-14 Frank Ch. Eigler <fche@cygnus.com>
84
85 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
86 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
87 (idt_monitor_base): Base address for IDT monitor traps.
88 (pmon_monitor_base): Ditto for PMON.
89 (lsipmon_monitor_base): Ditto for LSI PMON.
90 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
91 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
92 (sim_firmware_command): New function.
93 (mips_option_handler): Call it for OPTION_FIRMWARE.
94 (sim_open): Allocate memory for idt_monitor region. If "--board"
95 option was given, add no monitor by default. Add BREAK hooks only if
96 monitors are also there.
97
43e526b9
JM		 98Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
99
100 * interp.c (sim_monitor): Flush output before reading input.
101
102Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
103
104 * tconfig.in (SIM_HANDLES_LMA): Always define.
105
106Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
107
108 From Mark Salter <msalter@cygnus.com>:
109 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
110 (sim_open): Add setup for BSP board.
111
9846de1b
JM		 112Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
113
114 * mips.igen (MULT, MULTU): Add syntax for two operand version.
115 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
116 them as unimplemented.
117
cd0fc7c3
SS		 1181999-05-08 Felix Lee <flee@cygnus.com>
119
120 * configure: Regenerated to track ../common/aclocal.m4 changes.
121
7a292a7a
SS		 1221999-04-21 Frank Ch. Eigler <fche@cygnus.com>
123
124 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
125
126Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
127
128 * configure.in: Any mips64vr5*-*-* target should have
129 -DTARGET_ENABLE_FR=1.
130 (default_endian): Any mips64vr*el-*-* target should default to
131 LITTLE_ENDIAN.
132 * configure: Re-generate.
133
1341999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
135
136 * mips.igen (ldl): Extend from _16_, not 32.
137
138Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
139
140 * interp.c (sim_store_register): Force registers written to by GDB
141 into an un-interpreted state.
142
c906108c
SS		 1431999-02-05 Frank Ch. Eigler <fche@cygnus.com>
144
145 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
146 CPU, start periodic background I/O polls.
147 (tx3904sio_poll): New function: periodic I/O poller.
148
1491998-12-30 Frank Ch. Eigler <fche@cygnus.com>
150
151 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
152
153Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
154
155 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
156 case statement.
157
1581998-12-29 Frank Ch. Eigler <fche@cygnus.com>
159
160 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
161 (load_word): Call SIM_CORE_SIGNAL hook on error.
162 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
163 starting. For exception dispatching, pass PC instead of NULL_CIA.
164 (decode_coproc): Use COP0_BADVADDR to store faulting address.
165 * sim-main.h (COP0_BADVADDR): Define.
166 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
167 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
168 (_sim_cpu): Add exc_* fields to store register value snapshots.
169 * mips.igen (*): Replace memory-related SignalException* calls
170 with references to SIM_CORE_SIGNAL hook.
171
172 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
173 fix.
174 * sim-main.c (*): Minor warning cleanups.
175
1761998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
177
178 * m16.igen (DADDIU5): Correct type-o.
179
180Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
181
182 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
183 variables.
184
185Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
186
187 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
188 to include path.
189 (interp.o): Add dependency on itable.h
190 (oengine.c, gencode): Delete remaining references.
191 (BUILT_SRC_FROM_GEN): Clean up.
192
1931998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
194
195 * vr4run.c: New.
196 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
197 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
198 tmp-run-hack) : New.
199 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
200 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
201 Drop the "64" qualifier to get the HACK generator working.
202 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
203 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
204 qualifier to get the hack generator working.
205 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
206 (DSLL): Use do_dsll.
207 (DSLLV): Use do_dsllv.
208 (DSRA): Use do_dsra.
209 (DSRL): Use do_dsrl.
210 (DSRLV): Use do_dsrlv.
211 (BC1): Move *vr4100 to get the HACK generator working.
212 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
213 get the HACK generator working.
214 (MACC) Rename to get the HACK generator working.
215 (DMACC,MACCS,DMACCS): Add the 64.
216
2171998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
218
219 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
220 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
221
2221998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
223
224 * mips/interp.c (DEBUG): Cleanups.
225
2261998-12-10 Frank Ch. Eigler <fche@cygnus.com>
227
228 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
229 (tx3904sio_tickle): fflush after a stdout character output.
230
2311998-12-03 Frank Ch. Eigler <fche@cygnus.com>
232
233 * interp.c (sim_close): Uninstall modules.
234
235Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
236
237 * sim-main.h, interp.c (sim_monitor): Change to global
238 function.
239
240Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
241
242 * configure.in (vr4100): Only include vr4100 instructions in
243 simulator.
244 * configure: Re-generate.
245 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
246
247Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
248
249 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
250 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
251 true alternative.
252
253 * configure.in (sim_default_gen, sim_use_gen): Replace with
254 sim_gen.
255 (--enable-sim-igen): Delete config option. Always using IGEN.
256 * configure: Re-generate.
257
258 * Makefile.in (gencode): Kill, kill, kill.
259 * gencode.c: Ditto.
260
261Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
262
263 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
264 bit mips16 igen simulator.
265 * configure: Re-generate.
266
267 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
268 as part of vr4100 ISA.
269 * vr.igen: Mark all instructions as 64 bit only.
270
271Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
272
273 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
274 Pacify GCC.
275
276Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
277
278 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
279 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
280 * configure: Re-generate.
281
282 * m16.igen (BREAK): Define breakpoint instruction.
283 (JALX32): Mark instruction as mips16 and not r3900.
284 * mips.igen (C.cond.fmt): Fix typo in instruction format.
285
286 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
287
288Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
289
290 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
291 insn as a debug breakpoint.
292
293 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
294 pending.slot_size.
295 (PENDING_SCHED): Clean up trace statement.
296 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
297 (PENDING_FILL): Delay write by only one cycle.
298 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
299
300 * sim-main.c (pending_tick): Clean up trace statements. Add trace
301 of pending writes.
302 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
303 32 & 64.
304 (pending_tick): Move incrementing of index to FOR statement.
305 (pending_tick): Only update PENDING_OUT after a write has occured.
306
307 * configure.in: Add explicit mips-lsi-* target. Use gencode to
308 build simulator.
309 * configure: Re-generate.
310
311 * interp.c (sim_engine_run OLD): Delete explicit call to
312 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
313
314Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
315
316 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
317 interrupt level number to match changed SignalExceptionInterrupt
318 macro.
319
320Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
321
322 * interp.c: #include "itable.h" if WITH_IGEN.
323 (get_insn_name): New function.
324 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
325 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
326
327Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
328
329 * configure: Rebuilt to inhale new common/aclocal.m4.
330
331Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
332
333 * dv-tx3904sio.c: Include sim-assert.h.
334
335Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
336
337 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
338 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
339 Reorganize target-specific sim-hardware checks.
340 * configure: rebuilt.
341 * interp.c (sim_open): For tx39 target boards, set
342 OPERATING_ENVIRONMENT, add tx3904sio devices.
343 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
344 ROM executables. Install dv-sockser into sim-modules list.
345
346 * dv-tx3904irc.c: Compiler warning clean-up.
347 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
348 frequent hw-trace messages.
349
350Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
351
352 * vr.igen (MulAcc): Identify as a vr4100 specific function.
353
354Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
355
356 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
357
358 * vr.igen: New file.
359 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
360 * mips.igen: Define vr4100 model. Include vr.igen.
361Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
362
363 * mips.igen (check_mf_hilo): Correct check.
364
365Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
366
367 * sim-main.h (interrupt_event): Add prototype.
368
369 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
370 register_ptr, register_value.
371 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
372
373 * sim-main.h (tracefh): Make extern.
374
375Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
376
377 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
378 Reduce unnecessarily high timer event frequency.
379 * dv-tx3904cpu.c: Ditto for interrupt event.
380
381Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
382
383 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
384 to allay warnings.
385 (interrupt_event): Made non-static.
386
387 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
388 interchange of configuration values for external vs. internal
389 clock dividers.
390
391Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
392
393 * mips.igen (BREAK): Moved code to here for
394 simulator-reserved break instructions.
395 * gencode.c (build_instruction): Ditto.
396 * interp.c (signal_exception): Code moved from here. Non-
397 reserved instructions now use exception vector, rather
398 than halting sim.
399 * sim-main.h: Moved magic constants to here.
400
401Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
402
403 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
404 register upon non-zero interrupt event level, clear upon zero
405 event value.
406 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
407 by passing zero event value.
408 (*_io_{read,write}_buffer): Endianness fixes.
409 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
410 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
411
412 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
413 serial I/O and timer module at base address 0xFFFF0000.
414
415Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
416
417 * mips.igen (SWC1) : Correct the handling of ReverseEndian
418 and BigEndianCPU.
419
420Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
421
422 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
423 parts.
424 * configure: Update.
425
426Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
427
428 * dv-tx3904tmr.c: New file - implements tx3904 timer.
429 * dv-tx3904{irc,cpu}.c: Mild reformatting.
430 * configure.in: Include tx3904tmr in hw_device list.
431 * configure: Rebuilt.
432 * interp.c (sim_open): Instantiate three timer instances.
433 Fix address typo of tx3904irc instance.
434
435Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
436
437 * interp.c (signal_exception): SystemCall exception now uses
438 the exception vector.
439
440Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
441
442 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
443 to allay warnings.
444
445Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
446
447 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
448
449Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
450
451 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
452
453 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
454 sim-main.h. Declare a struct hw_descriptor instead of struct
455 hw_device_descriptor.
456
457Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
458
459 * mips.igen (do_store_left, do_load_left): Compute nr of left and
460 right bits and then re-align left hand bytes to correct byte
461 lanes. Fix incorrect computation in do_store_left when loading
462 bytes from second word.
463
464Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
465
466 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
467 * interp.c (sim_open): Only create a device tree when HW is
468 enabled.
469
470 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
471 * interp.c (signal_exception): Ditto.
472
473Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
474
475 * gencode.c: Mark BEGEZALL as LIKELY.
476
477Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
478
479 * sim-main.h (ALU32_END): Sign extend 32 bit results.
480 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
481
482Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
483
484 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
485 modules. Recognize TX39 target with "mips*tx39" pattern.
486 * configure: Rebuilt.
487 * sim-main.h (*): Added many macros defining bits in
488 TX39 control registers.
489 (SignalInterrupt): Send actual PC instead of NULL.
490 (SignalNMIReset): New exception type.
491 * interp.c (board): New variable for future use to identify
492 a particular board being simulated.
493 (mips_option_handler,mips_options): Added "--board" option.
494 (interrupt_event): Send actual PC.
495 (sim_open): Make memory layout conditional on board setting.
496 (signal_exception): Initial implementation of hardware interrupt
497 handling. Accept another break instruction variant for simulator
498 exit.
499 (decode_coproc): Implement RFE instruction for TX39.
500 (mips.igen): Decode RFE instruction as such.
501 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
502 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
503 bbegin to implement memory map.
504 * dv-tx3904cpu.c: New file.
505 * dv-tx3904irc.c: New file.
506
507Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
508
509 * mips.igen (check_mt_hilo): Create a separate r3900 version.
510
511Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
512
513 * tx.igen (madd,maddu): Replace calls to check_op_hilo
514 with calls to check_div_hilo.
515
516Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
517
518 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
519 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
520 Add special r3900 version of do_mult_hilo.
521 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
522 with calls to check_mult_hilo.
523 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
524 with calls to check_div_hilo.
525
526Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
527
528 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
529 Document a replacement.
530
531Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
532
533 * interp.c (sim_monitor): Make mon_printf work.
534
535Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
536
537 * sim-main.h (INSN_NAME): New arg `cpu'.
538
539Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
540
541 * configure: Regenerated to track ../common/aclocal.m4 changes.
542
543Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
544
545 * configure: Regenerated to track ../common/aclocal.m4 changes.
546 * config.in: Ditto.
547
548Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
549
550 * acconfig.h: New file.
551 * configure.in: Reverted change of Apr 24; use sinclude again.
552
553Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
554
555 * configure: Regenerated to track ../common/aclocal.m4 changes.
556 * config.in: Ditto.
557
558Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
559
560 * configure.in: Don't call sinclude.
561
562Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
563
564 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
565
566Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
567
568 * mips.igen (ERET): Implement.
569
570 * interp.c (decode_coproc): Return sign-extended EPC.
571
572 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
573
574 * interp.c (signal_exception): Do not ignore Trap.
575 (signal_exception): On TRAP, restart at exception address.
576 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
577 (signal_exception): Update.
578 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
579 so that TRAP instructions are caught.
580
581Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
582
583 * sim-main.h (struct hilo_access, struct hilo_history): Define,
584 contains HI/LO access history.
585 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
586 (HIACCESS, LOACCESS): Delete, replace with
587 (HIHISTORY, LOHISTORY): New macros.
588 (CHECKHILO): Delete all, moved to mips.igen
589
590 * gencode.c (build_instruction): Do not generate checks for
591 correct HI/LO register usage.
592
593 * interp.c (old_engine_run): Delete checks for correct HI/LO
594 register usage.
595
596 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
597 check_mf_cycles): New functions.
598 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
599 do_divu, domultx, do_mult, do_multu): Use.
600
601 * tx.igen ("madd", "maddu"): Use.
602
603Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
604
605 * mips.igen (DSRAV): Use function do_dsrav.
606 (SRAV): Use new function do_srav.
607
608 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
609 (B): Sign extend 11 bit immediate.
610 (EXT-B*): Shift 16 bit immediate left by 1.
611 (ADDIU*): Don't sign extend immediate value.
612
613Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
614
615 * m16run.c (sim_engine_run): Restore CIA after handling an event.
616
617 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
618 functions.
619
620 * mips.igen (delayslot32, nullify_next_insn): New functions.
621 (m16.igen): Always include.
622 (do_*): Add more tracing.
623
624 * m16.igen (delayslot16): Add NIA argument, could be called by a
625 32 bit MIPS16 instruction.
626
627 * interp.c (ifetch16): Move function from here.
628 * sim-main.c (ifetch16): To here.
629
630 * sim-main.c (ifetch16, ifetch32): Update to match current
631 implementations of LH, LW.
632 (signal_exception): Don't print out incorrect hex value of illegal
633 instruction.
634
635Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
636
637 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
638 instruction.
639
640 * m16.igen: Implement MIPS16 instructions.
641
642 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
643 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
644 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
645 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
646 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
647 bodies of corresponding code from 32 bit insn to these. Also used
648 by MIPS16 versions of functions.
649
650 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
651 (IMEM16): Drop NR argument from macro.
652
653Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
654
655 * Makefile.in (SIM_OBJS): Add sim-main.o.
656
657 * sim-main.h (address_translation, load_memory, store_memory,
658 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
659 as INLINE_SIM_MAIN.
660 (pr_addr, pr_uword64): Declare.
661 (sim-main.c): Include when H_REVEALS_MODULE_P.
662
663 * interp.c (address_translation, load_memory, store_memory,
664 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
665 from here.
666 * sim-main.c: To here. Fix compilation problems.
667
668 * configure.in: Enable inlining.
669 * configure: Re-config.
670
671Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
672
673 * configure: Regenerated to track ../common/aclocal.m4 changes.
674
675Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
676
677 * mips.igen: Include tx.igen.
678 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
679 * tx.igen: New file, contains MADD and MADDU.
680
681 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
682 the hardwired constant `7'.
683 (store_memory): Ditto.
684 (LOADDRMASK): Move definition to sim-main.h.
685
686 mips.igen (MTC0): Enable for r3900.
687 (ADDU): Add trace.
688
689 mips.igen (do_load_byte): Delete.
690 (do_load, do_store, do_load_left, do_load_write, do_store_left,
691 do_store_right): New functions.
692 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
693
694 configure.in: Let the tx39 use igen again.
695 configure: Update.
696
697Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
698
699 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
700 not an address sized quantity. Return zero for cache sizes.
701
702Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
703
704 * mips.igen (r3900): r3900 does not support 64 bit integer
705 operations.
706
707Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
708
709 * configure.in (mipstx39*-*-*): Use gencode simulator rather
710 than igen one.
711 * configure : Rebuild.
712
713Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * configure: Regenerated to track ../common/aclocal.m4 changes.
716
717Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
718
719 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
720
721Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
722
723 * configure: Regenerated to track ../common/aclocal.m4 changes.
724 * config.in: Regenerated to track ../common/aclocal.m4 changes.
725
726Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
727
728 * configure: Regenerated to track ../common/aclocal.m4 changes.
729
730Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
731
732 * interp.c (Max, Min): Comment out functions. Not yet used.
733
734Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
735
736 * configure: Regenerated to track ../common/aclocal.m4 changes.
737
738Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
739
740 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
741 configurable settings for stand-alone simulator.
742
743 * configure.in: Added X11 search, just in case.
744
745 * configure: Regenerated.
746
747Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
748
749 * interp.c (sim_write, sim_read, load_memory, store_memory):
750 Replace sim_core_*_map with read_map, write_map, exec_map resp.
751
752Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * sim-main.h (GETFCC): Return an unsigned value.
755
756Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
757
758 * mips.igen (DIV): Fix check for -1 / MIN_INT.
759 (DADD): Result destination is RD not RT.
760
761Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
762
763 * sim-main.h (HIACCESS, LOACCESS): Always define.
764
765 * mdmx.igen (Maxi, Mini): Rename Max, Min.
766
767 * interp.c (sim_info): Delete.
768
769Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
770
771 * interp.c (DECLARE_OPTION_HANDLER): Use it.
772 (mips_option_handler): New argument `cpu'.
773 (sim_open): Update call to sim_add_option_table.
774
775Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * mips.igen (CxC1): Add tracing.
778
779Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
780
781 * sim-main.h (Max, Min): Declare.
782
783 * interp.c (Max, Min): New functions.
784
785 * mips.igen (BC1): Add tracing.
786
787Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
788
789 * interp.c Added memory map for stack in vr4100
790
791Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
792
793 * interp.c (load_memory): Add missing "break"'s.
794
795Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
796
797 * interp.c (sim_store_register, sim_fetch_register): Pass in
798 length parameter. Return -1.
799
800Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
801
802 * interp.c: Added hardware init hook, fixed warnings.
803
804Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
805
806 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
807
808Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
809
810 * interp.c (ifetch16): New function.
811
812 * sim-main.h (IMEM32): Rename IMEM.
813 (IMEM16_IMMED): Define.
814 (IMEM16): Define.
815 (DELAY_SLOT): Update.
816
817 * m16run.c (sim_engine_run): New file.
818
819 * m16.igen: All instructions except LB.
820 (LB): Call do_load_byte.
821 * mips.igen (do_load_byte): New function.
822 (LB): Call do_load_byte.
823
824 * mips.igen: Move spec for insn bit size and high bit from here.
825 * Makefile.in (tmp-igen, tmp-m16): To here.
826
827 * m16.dc: New file, decode mips16 instructions.
828
829 * Makefile.in (SIM_NO_ALL): Define.
830 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
831
832Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
833
834 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
835 point unit to 32 bit registers.
836 * configure: Re-generate.
837
838Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
839
840 * configure.in (sim_use_gen): Make IGEN the default simulator
841 generator for generic 32 and 64 bit mips targets.
842 * configure: Re-generate.
843
844Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
845
846 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
847 bitsize.
848
849 * interp.c (sim_fetch_register, sim_store_register): Read/write
850 FGR from correct location.
851 (sim_open): Set size of FGR's according to
852 WITH_TARGET_FLOATING_POINT_BITSIZE.
853
854 * sim-main.h (FGR): Store floating point registers in a separate
855 array.
856
857Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
858
859 * configure: Regenerated to track ../common/aclocal.m4 changes.
860
861Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
862
863 * interp.c (ColdReset): Call PENDING_INVALIDATE.
864
865 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
866
867 * interp.c (pending_tick): New function. Deliver pending writes.
868
869 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
870 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
871 it can handle mixed sized quantites and single bits.
872
873Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
874
875 * interp.c (oengine.h): Do not include when building with IGEN.
876 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
877 (sim_info): Ditto for PROCESSOR_64BIT.
878 (sim_monitor): Replace ut_reg with unsigned_word.
879 (*): Ditto for t_reg.
880 (LOADDRMASK): Define.
881 (sim_open): Remove defunct check that host FP is IEEE compliant,
882 using software to emulate floating point.
883 (value_fpr, ...): Always compile, was conditional on HASFPU.
884
885Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
886
887 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
888 size.
889
890 * interp.c (SD, CPU): Define.
891 (mips_option_handler): Set flags in each CPU.
892 (interrupt_event): Assume CPU 0 is the one being iterrupted.
893 (sim_close): Do not clear STATE, deleted anyway.
894 (sim_write, sim_read): Assume CPU zero's vm should be used for
895 data transfers.
896 (sim_create_inferior): Set the PC for all processors.
897 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
898 argument.
899 (mips16_entry): Pass correct nr of args to store_word, load_word.
900 (ColdReset): Cold reset all cpu's.
901 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
902 (sim_monitor, load_memory, store_memory, signal_exception): Use
903 `CPU' instead of STATE_CPU.
904
905
906 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
907 SD or CPU_.
908
909 * sim-main.h (signal_exception): Add sim_cpu arg.
910 (SignalException*): Pass both SD and CPU to signal_exception.
911 * interp.c (signal_exception): Update.
912
913 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
914 Ditto
915 (sync_operation, prefetch, cache_op, store_memory, load_memory,
916 address_translation): Ditto
917 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
918
919Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * configure: Regenerated to track ../common/aclocal.m4 changes.
922
923Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
924
925 * interp.c (sim_engine_run): Add `nr_cpus' argument.
926
927 * mips.igen (model): Map processor names onto BFD name.
928
929 * sim-main.h (CPU_CIA): Delete.
930 (SET_CIA, GET_CIA): Define
931
932Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
933
934 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
935 regiser.
936
937 * configure.in (default_endian): Configure a big-endian simulator
938 by default.
939 * configure: Re-generate.
940
941Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
942
943 * configure: Regenerated to track ../common/aclocal.m4 changes.
944
945Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
946
947 * interp.c (sim_monitor): Handle Densan monitor outbyte
948 and inbyte functions.
949
9501997-12-29 Felix Lee <flee@cygnus.com>
951
952 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
953
954Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
955
956 * Makefile.in (tmp-igen): Arrange for $zero to always be
957 reset to zero after every instruction.
958
959Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
960
961 * configure: Regenerated to track ../common/aclocal.m4 changes.
962 * config.in: Ditto.
963
964Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
965
966 * mips.igen (MSUB): Fix to work like MADD.
967 * gencode.c (MSUB): Similarly.
968
969Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
970
971 * configure: Regenerated to track ../common/aclocal.m4 changes.
972
973Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
974
975 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
976
977Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
978
979 * sim-main.h (sim-fpu.h): Include.
980
981 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
982 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
983 using host independant sim_fpu module.
984
985Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
986
987 * interp.c (signal_exception): Report internal errors with SIGABRT
988 not SIGQUIT.
989
990 * sim-main.h (C0_CONFIG): New register.
991 (signal.h): No longer include.
992
993 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
994
995Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
996
997 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
998
999Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1000
1001 * mips.igen: Tag vr5000 instructions.
1002 (ANDI): Was missing mipsIV model, fix assembler syntax.
1003 (do_c_cond_fmt): New function.
1004 (C.cond.fmt): Handle mips I-III which do not support CC field
1005 separatly.
1006 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1007 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1008 in IV3.2 spec.
1009 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1010 vr5000 which saves LO in a GPR separatly.
1011
1012 * configure.in (enable-sim-igen): For vr5000, select vr5000
1013 specific instructions.
1014 * configure: Re-generate.
1015
1016Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1017
1018 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1019
1020 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1021 fmt_uninterpreted_64 bit cases to switch. Convert to
1022 fmt_formatted,
1023
1024 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1025
1026 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1027 as specified in IV3.2 spec.
1028 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1029
1030Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1031
1032 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1033 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1034 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1035 PENDING_FILL versions of instructions. Simplify.
1036 (X): New function.
1037 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1038 instructions.
1039 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1040 a signed value.
1041 (MTHI, MFHI): Disable code checking HI-LO.
1042
1043 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1044 global.
1045 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1046
1047Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1048
1049 * gencode.c (build_mips16_operands): Replace IPC with cia.
1050
1051 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1052 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1053 IPC to `cia'.
1054 (UndefinedResult): Replace function with macro/function
1055 combination.
1056 (sim_engine_run): Don't save PC in IPC.
1057
1058 * sim-main.h (IPC): Delete.
1059
1060
1061 * interp.c (signal_exception, store_word, load_word,
1062 address_translation, load_memory, store_memory, cache_op,
1063 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1064 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1065 current instruction address - cia - argument.
1066 (sim_read, sim_write): Call address_translation directly.
1067 (sim_engine_run): Rename variable vaddr to cia.
1068 (signal_exception): Pass cia to sim_monitor
1069
1070 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1071 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1072 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1073
1074 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1075 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1076 SIM_ASSERT.
1077
1078 * interp.c (signal_exception): Pass restart address to
1079 sim_engine_restart.
1080
1081 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1082 idecode.o): Add dependency.
1083
1084 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1085 Delete definitions
1086 (DELAY_SLOT): Update NIA not PC with branch address.
1087 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1088
1089 * mips.igen: Use CIA not PC in branch calculations.
1090 (illegal): Call SignalException.
1091 (BEQ, ADDIU): Fix assembler.
1092
1093Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1094
1095 * m16.igen (JALX): Was missing.
1096
1097 * configure.in (enable-sim-igen): New configuration option.
1098 * configure: Re-generate.
1099
1100 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1101
1102 * interp.c (load_memory, store_memory): Delete parameter RAW.
1103 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1104 bypassing {load,store}_memory.
1105
1106 * sim-main.h (ByteSwapMem): Delete definition.
1107
1108 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1109
1110 * interp.c (sim_do_command, sim_commands): Delete mips specific
1111 commands. Handled by module sim-options.
1112
1113 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1114 (WITH_MODULO_MEMORY): Define.
1115
1116 * interp.c (sim_info): Delete code printing memory size.
1117
1118 * interp.c (mips_size): Nee sim_size, delete function.
1119 (power2): Delete.
1120 (monitor, monitor_base, monitor_size): Delete global variables.
1121 (sim_open, sim_close): Delete code creating monitor and other
1122 memory regions. Use sim-memopts module, via sim_do_commandf, to
1123 manage memory regions.
1124 (load_memory, store_memory): Use sim-core for memory model.
1125
1126 * interp.c (address_translation): Delete all memory map code
1127 except line forcing 32 bit addresses.
1128
1129Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1130
1131 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1132 trace options.
1133
1134 * interp.c (logfh, logfile): Delete globals.
1135 (sim_open, sim_close): Delete code opening & closing log file.
1136 (mips_option_handler): Delete -l and -n options.
1137 (OPTION mips_options): Ditto.
1138
1139 * interp.c (OPTION mips_options): Rename option trace to dinero.
1140 (mips_option_handler): Update.
1141
1142Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1143
1144 * interp.c (fetch_str): New function.
1145 (sim_monitor): Rewrite using sim_read & sim_write.
1146 (sim_open): Check magic number.
1147 (sim_open): Write monitor vectors into memory using sim_write.
1148 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1149 (sim_read, sim_write): Simplify - transfer data one byte at a
1150 time.
1151 (load_memory, store_memory): Clarify meaning of parameter RAW.
1152
1153 * sim-main.h (isHOST): Defete definition.
1154 (isTARGET): Mark as depreciated.
1155 (address_translation): Delete parameter HOST.
1156
1157 * interp.c (address_translation): Delete parameter HOST.
1158
1159Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1160
1161 * mips.igen:
1162
1163 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1164 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1165
1166Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1167
1168 * mips.igen: Add model filter field to records.
1169
1170Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1171
1172 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1173
1174 interp.c (sim_engine_run): Do not compile function sim_engine_run
1175 when WITH_IGEN == 1.
1176
1177 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1178 target architecture.
1179
1180 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1181 igen. Replace with configuration variables sim_igen_flags /
1182 sim_m16_flags.
1183
1184 * m16.igen: New file. Copy mips16 insns here.
1185 * mips.igen: From here.
1186
1187Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1188
1189 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1190 to top.
1191 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1192
1193Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1194
1195 * gencode.c (build_instruction): Follow sim_write's lead in using
1196 BigEndianMem instead of !ByteSwapMem.
1197
1198Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1199
1200 * configure.in (sim_gen): Dependent on target, select type of
1201 generator. Always select old style generator.
1202
1203 configure: Re-generate.
1204
1205 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1206 targets.
1207 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1208 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1209 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1210 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1211 SIM_@sim_gen@_*, set by autoconf.
1212
1213Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1214
1215 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1216
1217 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1218 CURRENT_FLOATING_POINT instead.
1219
1220 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1221 (address_translation): Raise exception InstructionFetch when
1222 translation fails and isINSTRUCTION.
1223
1224 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1225 sim_engine_run): Change type of of vaddr and paddr to
1226 address_word.
1227 (address_translation, prefetch, load_memory, store_memory,
1228 cache_op): Change type of vAddr and pAddr to address_word.
1229
1230 * gencode.c (build_instruction): Change type of vaddr and paddr to
1231 address_word.
1232
1233Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1234
1235 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1236 macro to obtain result of ALU op.
1237
1238Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * interp.c (sim_info): Call profile_print.
1241
1242Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1243
1244 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1245
1246 * sim-main.h (WITH_PROFILE): Do not define, defined in
1247 common/sim-config.h. Use sim-profile module.
1248 (simPROFILE): Delete defintion.
1249
1250 * interp.c (PROFILE): Delete definition.
1251 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1252 (sim_close): Delete code writing profile histogram.
1253 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1254 Delete.
1255 (sim_engine_run): Delete code profiling the PC.
1256
1257Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1260
1261 * interp.c (sim_monitor): Make register pointers of type
1262 unsigned_word*.
1263
1264 * sim-main.h: Make registers of type unsigned_word not
1265 signed_word.
1266
1267Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1268
1269 * interp.c (sync_operation): Rename from SyncOperation, make
1270 global, add SD argument.
1271 (prefetch): Rename from Prefetch, make global, add SD argument.
1272 (decode_coproc): Make global.
1273
1274 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1275
1276 * gencode.c (build_instruction): Generate DecodeCoproc not
1277 decode_coproc calls.
1278
1279 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1280 (SizeFGR): Move to sim-main.h
1281 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1282 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1283 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1284 sim-main.h.
1285 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1286 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1287 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1288 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1289 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1290 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1291
1292 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1293 exception.
1294 (sim-alu.h): Include.
1295 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1296 (sim_cia): Typedef to instruction_address.
1297
1298Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1299
1300 * Makefile.in (interp.o): Rename generated file engine.c to
1301 oengine.c.
1302
1303 * interp.c: Update.
1304
1305Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1306
1307 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1308
1309Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1310
1311 * gencode.c (build_instruction): For "FPSQRT", output correct
1312 number of arguments to Recip.
1313
1314Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * Makefile.in (interp.o): Depends on sim-main.h
1317
1318 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1319
1320 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1321 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1322 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1323 STATE, DSSTATE): Define
1324 (GPR, FGRIDX, ..): Define.
1325
1326 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1327 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1328 (GPR, FGRIDX, ...): Delete macros.
1329
1330 * interp.c: Update names to match defines from sim-main.h
1331
1332Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1333
1334 * interp.c (sim_monitor): Add SD argument.
1335 (sim_warning): Delete. Replace calls with calls to
1336 sim_io_eprintf.
1337 (sim_error): Delete. Replace calls with sim_io_error.
1338 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1339 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1340 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1341 argument.
1342 (mips_size): Rename from sim_size. Add SD argument.
1343
1344 * interp.c (simulator): Delete global variable.
1345 (callback): Delete global variable.
1346 (mips_option_handler, sim_open, sim_write, sim_read,
1347 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1348 sim_size,sim_monitor): Use sim_io_* not callback->*.
1349 (sim_open): ZALLOC simulator struct.
1350 (PROFILE): Do not define.
1351
1352Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1353
1354 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1355 support.h with corresponding code.
1356
1357 * sim-main.h (word64, uword64), support.h: Move definition to
1358 sim-main.h.
1359 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1360
1361 * support.h: Delete
1362 * Makefile.in: Update dependencies
1363 * interp.c: Do not include.
1364
1365Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1366
1367 * interp.c (address_translation, load_memory, store_memory,
1368 cache_op): Rename to from AddressTranslation et.al., make global,
1369 add SD argument
1370
1371 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1372 CacheOp): Define.
1373
1374 * interp.c (SignalException): Rename to signal_exception, make
1375 global.
1376
1377 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1378
1379 * sim-main.h (SignalException, SignalExceptionInterrupt,
1380 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1381 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1382 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1383 Define.
1384
1385 * interp.c, support.h: Use.
1386
1387Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1388
1389 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1390 to value_fpr / store_fpr. Add SD argument.
1391 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1392 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1393
1394 * sim-main.h (ValueFPR, StoreFPR): Define.
1395
1396Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1397
1398 * interp.c (sim_engine_run): Check consistency between configure
1399 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1400 and HASFPU.
1401
1402 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1403 (mips_fpu): Configure WITH_FLOATING_POINT.
1404 (mips_endian): Configure WITH_TARGET_ENDIAN.
1405 * configure: Update.
1406
1407Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1408
1409 * configure: Regenerated to track ../common/aclocal.m4 changes.
1410
1411Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1412
1413 * configure: Regenerated.
1414
1415Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1416
1417 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1418
1419Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * gencode.c (print_igen_insn_models): Assume certain architectures
1422 include all mips* instructions.
1423 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1424 instruction.
1425
1426 * Makefile.in (tmp.igen): Add target. Generate igen input from
1427 gencode file.
1428
1429 * gencode.c (FEATURE_IGEN): Define.
1430 (main): Add --igen option. Generate output in igen format.
1431 (process_instructions): Format output according to igen option.
1432 (print_igen_insn_format): New function.
1433 (print_igen_insn_models): New function.
1434 (process_instructions): Only issue warnings and ignore
1435 instructions when no FEATURE_IGEN.
1436
1437Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1438
1439 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1440 MIPS targets.
1441
1442Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * configure: Regenerated to track ../common/aclocal.m4 changes.
1445
1446Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1449 SIM_RESERVED_BITS): Delete, moved to common.
1450 (SIM_EXTRA_CFLAGS): Update.
1451
1452Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1453
1454 * configure.in: Configure non-strict memory alignment.
1455 * configure: Regenerated to track ../common/aclocal.m4 changes.
1456
1457Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1458
1459 * configure: Regenerated to track ../common/aclocal.m4 changes.
1460
1461Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1462
1463 * gencode.c (SDBBP,DERET): Added (3900) insns.
1464 (RFE): Turn on for 3900.
1465 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1466 (dsstate): Made global.
1467 (SUBTARGET_R3900): Added.
1468 (CANCELDELAYSLOT): New.
1469 (SignalException): Ignore SystemCall rather than ignore and
1470 terminate. Add DebugBreakPoint handling.
1471 (decode_coproc): New insns RFE, DERET; and new registers Debug
1472 and DEPC protected by SUBTARGET_R3900.
1473 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1474 bits explicitly.
1475 * Makefile.in,configure.in: Add mips subtarget option.
1476 * configure: Update.
1477
1478Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1479
1480 * gencode.c: Add r3900 (tx39).
1481
1482
1483Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1484
1485 * gencode.c (build_instruction): Don't need to subtract 4 for
1486 JALR, just 2.
1487
1488Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1489
1490 * interp.c: Correct some HASFPU problems.
1491
1492Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1493
1494 * configure: Regenerated to track ../common/aclocal.m4 changes.
1495
1496Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1497
1498 * interp.c (mips_options): Fix samples option short form, should
1499 be `x'.
1500
1501Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * interp.c (sim_info): Enable info code. Was just returning.
1504
1505Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1506
1507 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1508 MFC0.
1509
1510Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1511
1512 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1513 constants.
1514 (build_instruction): Ditto for LL.
1515
1516Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1517
1518 * configure: Regenerated to track ../common/aclocal.m4 changes.
1519
1520Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * configure: Regenerated to track ../common/aclocal.m4 changes.
1523 * config.in: Ditto.
1524
1525Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1526
1527 * interp.c (sim_open): Add call to sim_analyze_program, update
1528 call to sim_config.
1529
1530Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1531
1532 * interp.c (sim_kill): Delete.
1533 (sim_create_inferior): Add ABFD argument. Set PC from same.
1534 (sim_load): Move code initializing trap handlers from here.
1535 (sim_open): To here.
1536 (sim_load): Delete, use sim-hload.c.
1537
1538 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1539
1540Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1541
1542 * configure: Regenerated to track ../common/aclocal.m4 changes.
1543 * config.in: Ditto.
1544
1545Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1546
1547 * interp.c (sim_open): Add ABFD argument.
1548 (sim_load): Move call to sim_config from here.
1549 (sim_open): To here. Check return status.
1550
1551Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1552
1553 * gencode.c (build_instruction): Two arg MADD should
1554 not assign result to $0.
1555
1556Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1557
1558 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1559 * sim/mips/configure.in: Regenerate.
1560
1561Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1562
1563 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1564 signed8, unsigned8 et.al. types.
1565
1566 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1567 hosts when selecting subreg.
1568
1569Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1570
1571 * interp.c (sim_engine_run): Reset the ZERO register to zero
1572 regardless of FEATURE_WARN_ZERO.
1573 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1574
1575Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1578 (SignalException): For BreakPoints ignore any mode bits and just
1579 save the PC.
1580 (SignalException): Always set the CAUSE register.
1581
1582Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583
1584 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1585 exception has been taken.
1586
1587 * interp.c: Implement the ERET and mt/f sr instructions.
1588
1589Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1590
1591 * interp.c (SignalException): Don't bother restarting an
1592 interrupt.
1593
1594Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595
1596 * interp.c (SignalException): Really take an interrupt.
1597 (interrupt_event): Only deliver interrupts when enabled.
1598
1599Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1600
1601 * interp.c (sim_info): Only print info when verbose.
1602 (sim_info) Use sim_io_printf for output.
1603
1604Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605
1606 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1607 mips architectures.
1608
1609Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1610
1611 * interp.c (sim_do_command): Check for common commands if a
1612 simulator specific command fails.
1613
1614Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1615
1616 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1617 and simBE when DEBUG is defined.
1618
1619Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1620
1621 * interp.c (interrupt_event): New function. Pass exception event
1622 onto exception handler.
1623
1624 * configure.in: Check for stdlib.h.
1625 * configure: Regenerate.
1626
1627 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1628 variable declaration.
1629 (build_instruction): Initialize memval1.
1630 (build_instruction): Add UNUSED attribute to byte, bigend,
1631 reverse.
1632 (build_operands): Ditto.
1633
1634 * interp.c: Fix GCC warnings.
1635 (sim_get_quit_code): Delete.
1636
1637 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1638 * Makefile.in: Ditto.
1639 * configure: Re-generate.
1640
1641 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1642
1643Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1644
1645 * interp.c (mips_option_handler): New function parse argumes using
1646 sim-options.
1647 (myname): Replace with STATE_MY_NAME.
1648 (sim_open): Delete check for host endianness - performed by
1649 sim_config.
1650 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1651 (sim_open): Move much of the initialization from here.
1652 (sim_load): To here. After the image has been loaded and
1653 endianness set.
1654 (sim_open): Move ColdReset from here.
1655 (sim_create_inferior): To here.
1656 (sim_open): Make FP check less dependant on host endianness.
1657
1658 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1659 run.
1660 * interp.c (sim_set_callbacks): Delete.
1661
1662 * interp.c (membank, membank_base, membank_size): Replace with
1663 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1664 (sim_open): Remove call to callback->init. gdb/run do this.
1665
1666 * interp.c: Update
1667
1668 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1669
1670 * interp.c (big_endian_p): Delete, replaced by
1671 current_target_byte_order.
1672
1673Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1674
1675 * interp.c (host_read_long, host_read_word, host_swap_word,
1676 host_swap_long): Delete. Using common sim-endian.
1677 (sim_fetch_register, sim_store_register): Use H2T.
1678 (pipeline_ticks): Delete. Handled by sim-events.
1679 (sim_info): Update.
1680 (sim_engine_run): Update.
1681
1682Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1683
1684 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1685 reason from here.
1686 (SignalException): To here. Signal using sim_engine_halt.
1687 (sim_stop_reason): Delete, moved to common.
1688
1689Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1690
1691 * interp.c (sim_open): Add callback argument.
1692 (sim_set_callbacks): Delete SIM_DESC argument.
1693 (sim_size): Ditto.
1694
1695Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696
1697 * Makefile.in (SIM_OBJS): Add common modules.
1698
1699 * interp.c (sim_set_callbacks): Also set SD callback.
1700 (set_endianness, xfer_*, swap_*): Delete.
1701 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1702 Change to functions using sim-endian macros.
1703 (control_c, sim_stop): Delete, use common version.
1704 (simulate): Convert into.
1705 (sim_engine_run): This function.
1706 (sim_resume): Delete.
1707
1708 * interp.c (simulation): New variable - the simulator object.
1709 (sim_kind): Delete global - merged into simulation.
1710 (sim_load): Cleanup. Move PC assignment from here.
1711 (sim_create_inferior): To here.
1712
1713 * sim-main.h: New file.
1714 * interp.c (sim-main.h): Include.
1715
1716Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1717
1718 * configure: Regenerated to track ../common/aclocal.m4 changes.
1719
1720Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1721
1722 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1723
1724Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1725
1726 * gencode.c (build_instruction): DIV instructions: check
1727 for division by zero and integer overflow before using
1728 host's division operation.
1729
1730Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1731
1732 * Makefile.in (SIM_OBJS): Add sim-load.o.
1733 * interp.c: #include bfd.h.
1734 (target_byte_order): Delete.
1735 (sim_kind, myname, big_endian_p): New static locals.
1736 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1737 after argument parsing. Recognize -E arg, set endianness accordingly.
1738 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1739 load file into simulator. Set PC from bfd.
1740 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1741 (set_endianness): Use big_endian_p instead of target_byte_order.
1742
1743Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744
1745 * interp.c (sim_size): Delete prototype - conflicts with
1746 definition in remote-sim.h. Correct definition.
1747
1748Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1749
1750 * configure: Regenerated to track ../common/aclocal.m4 changes.
1751 * config.in: Ditto.
1752
1753Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1754
1755 * interp.c (sim_open): New arg `kind'.
1756
1757 * configure: Regenerated to track ../common/aclocal.m4 changes.
1758
1759Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1760
1761 * configure: Regenerated to track ../common/aclocal.m4 changes.
1762
1763Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1764
1765 * interp.c (sim_open): Set optind to 0 before calling getopt.
1766
1767Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1768
1769 * configure: Regenerated to track ../common/aclocal.m4 changes.
1770
1771Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1772
1773 * interp.c : Replace uses of pr_addr with pr_uword64
1774 where the bit length is always 64 independent of SIM_ADDR.
1775 (pr_uword64) : added.
1776
1777Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1778
1779 * configure: Re-generate.
1780
1781Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1782
1783 * configure: Regenerate to track ../common/aclocal.m4 changes.
1784
1785Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1786
1787 * interp.c (sim_open): New SIM_DESC result. Argument is now
1788 in argv form.
1789 (other sim_*): New SIM_DESC argument.
1790
1791Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1792
1793 * interp.c: Fix printing of addresses for non-64-bit targets.
1794 (pr_addr): Add function to print address based on size.
1795
1796Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1797
1798 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1799
1800Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1801
1802 * gencode.c (build_mips16_operands): Correct computation of base
1803 address for extended PC relative instruction.
1804
1805Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1806
1807 * interp.c (mips16_entry): Add support for floating point cases.
1808 (SignalException): Pass floating point cases to mips16_entry.
1809 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1810 registers.
1811 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1812 or fmt_word.
1813 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1814 and then set the state to fmt_uninterpreted.
1815 (COP_SW): Temporarily set the state to fmt_word while calling
1816 ValueFPR.
1817
1818Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1819
1820 * gencode.c (build_instruction): The high order may be set in the
1821 comparison flags at any ISA level, not just ISA 4.
1822
1823Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1824
1825 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1826 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1827 * configure.in: sinclude ../common/aclocal.m4.
1828 * configure: Regenerated.
1829
1830Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1831
1832 * configure: Rebuild after change to aclocal.m4.
1833
1834Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1835
1836 * configure configure.in Makefile.in: Update to new configure
1837 scheme which is more compatible with WinGDB builds.
1838 * configure.in: Improve comment on how to run autoconf.
1839 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1840 * Makefile.in: Use autoconf substitution to install common
1841 makefile fragment.
1842
1843Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1844
1845 * gencode.c (build_instruction): Use BigEndianCPU instead of
1846 ByteSwapMem.
1847
1848Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1849
1850 * interp.c (sim_monitor): Make output to stdout visible in
1851 wingdb's I/O log window.
1852
1853Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1854
1855 * support.h: Undo previous change to SIGTRAP
1856 and SIGQUIT values.
1857
1858Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1859
1860 * interp.c (store_word, load_word): New static functions.
1861 (mips16_entry): New static function.
1862 (SignalException): Look for mips16 entry and exit instructions.
1863 (simulate): Use the correct index when setting fpr_state after
1864 doing a pending move.
1865
1866Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1867
1868 * interp.c: Fix byte-swapping code throughout to work on
1869 both little- and big-endian hosts.
1870
1871Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1872
1873 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1874 with gdb/config/i386/xm-windows.h.
1875
1876Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1877
1878 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1879 that messes up arithmetic shifts.
1880
1881Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1882
1883 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1884 SIGTRAP and SIGQUIT for _WIN32.
1885
1886Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1887
1888 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1889 force a 64 bit multiplication.
1890 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1891 destination register is 0, since that is the default mips16 nop
1892 instruction.
1893
1894Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1895
1896 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1897 (build_endian_shift): Don't check proc64.
1898 (build_instruction): Always set memval to uword64. Cast op2 to
1899 uword64 when shifting it left in memory instructions. Always use
1900 the same code for stores--don't special case proc64.
1901
1902 * gencode.c (build_mips16_operands): Fix base PC value for PC
1903 relative operands.
1904 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1905 jal instruction.
1906 * interp.c (simJALDELAYSLOT): Define.
1907 (JALDELAYSLOT): Define.
1908 (INDELAYSLOT, INJALDELAYSLOT): Define.
1909 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1910
1911Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1912
1913 * interp.c (sim_open): add flush_cache as a PMON routine
1914 (sim_monitor): handle flush_cache by ignoring it
1915
1916Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1917
1918 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1919 BigEndianMem.
1920 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1921 (BigEndianMem): Rename to ByteSwapMem and change sense.
1922 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1923 BigEndianMem references to !ByteSwapMem.
1924 (set_endianness): New function, with prototype.
1925 (sim_open): Call set_endianness.
1926 (sim_info): Use simBE instead of BigEndianMem.
1927 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1928 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1929 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1930 ifdefs, keeping the prototype declaration.
1931 (swap_word): Rewrite correctly.
1932 (ColdReset): Delete references to CONFIG. Delete endianness related
1933 code; moved to set_endianness.
1934
1935Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1936
1937 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1938 * interp.c (CHECKHILO): Define away.
1939 (simSIGINT): New macro.
1940 (membank_size): Increase from 1MB to 2MB.
1941 (control_c): New function.
1942 (sim_resume): Rename parameter signal to signal_number. Add local
1943 variable prev. Call signal before and after simulate.
1944 (sim_stop_reason): Add simSIGINT support.
1945 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1946 functions always.
1947 (sim_warning): Delete call to SignalException. Do call printf_filtered
1948 if logfh is NULL.
1949 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1950 a call to sim_warning.
1951
1952Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1953
1954 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1955 16 bit instructions.
1956
1957Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1958
1959 Add support for mips16 (16 bit MIPS implementation):
1960 * gencode.c (inst_type): Add mips16 instruction encoding types.
1961 (GETDATASIZEINSN): Define.
1962 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1963 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1964 mtlo.
1965 (MIPS16_DECODE): New table, for mips16 instructions.
1966 (bitmap_val): New static function.
1967 (struct mips16_op): Define.
1968 (mips16_op_table): New table, for mips16 operands.
1969 (build_mips16_operands): New static function.
1970 (process_instructions): If PC is odd, decode a mips16
1971 instruction. Break out instruction handling into new
1972 build_instruction function.
1973 (build_instruction): New static function, broken out of
1974 process_instructions. Check modifiers rather than flags for SHIFT
1975 bit count and m[ft]{hi,lo} direction.
1976 (usage): Pass program name to fprintf.
1977 (main): Remove unused variable this_option_optind. Change
1978 ``*loptarg++'' to ``loptarg++''.
1979 (my_strtoul): Parenthesize && within ||.
1980 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1981 (simulate): If PC is odd, fetch a 16 bit instruction, and
1982 increment PC by 2 rather than 4.
1983 * configure.in: Add case for mips16*-*-*.
1984 * configure: Rebuild.
1985
1986Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1987
1988 * interp.c: Allow -t to enable tracing in standalone simulator.
1989 Fix garbage output in trace file and error messages.
1990
1991Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1992
1993 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1994 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1995 * configure.in: Simplify using macros in ../common/aclocal.m4.
1996 * configure: Regenerated.
1997 * tconfig.in: New file.
1998
1999Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2000
2001 * interp.c: Fix bugs in 64-bit port.
2002 Use ansi function declarations for msvc compiler.
2003 Initialize and test file pointer in trace code.
2004 Prevent duplicate definition of LAST_EMED_REGNUM.
2005
2006Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2007
2008 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2009
2010Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2011
2012 * interp.c (SignalException): Check for explicit terminating
2013 breakpoint value.
2014 * gencode.c: Pass instruction value through SignalException()
2015 calls for Trap, Breakpoint and Syscall.
2016
2017Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2018
2019 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2020 only used on those hosts that provide it.
2021 * configure.in: Add sqrt() to list of functions to be checked for.
2022 * config.in: Re-generated.
2023 * configure: Re-generated.
2024
2025Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2026
2027 * gencode.c (process_instructions): Call build_endian_shift when
2028 expanding STORE RIGHT, to fix swr.
2029 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2030 clear the high bits.
2031 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2032 Fix float to int conversions to produce signed values.
2033
2034Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2035
2036 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2037 (process_instructions): Correct handling of nor instruction.
2038 Correct shift count for 32 bit shift instructions. Correct sign
2039 extension for arithmetic shifts to not shift the number of bits in
2040 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2041 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2042 Fix madd.
2043 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2044 It's OK to have a mult follow a mult. What's not OK is to have a
2045 mult follow an mfhi.
2046 (Convert): Comment out incorrect rounding code.
2047
2048Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2049
2050 * interp.c (sim_monitor): Improved monitor printf
2051 simulation. Tidied up simulator warnings, and added "--log" option
2052 for directing warning message output.
2053 * gencode.c: Use sim_warning() rather than WARNING macro.
2054
2055Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2056
2057 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2058 getopt1.o, rather than on gencode.c. Link objects together.
2059 Don't link against -liberty.
2060 (gencode.o, getopt.o, getopt1.o): New targets.
2061 * gencode.c: Include <ctype.h> and "ansidecl.h".
2062 (AND): Undefine after including "ansidecl.h".
2063 (ULONG_MAX): Define if not defined.
2064 (OP_*): Don't define macros; now defined in opcode/mips.h.
2065 (main): Call my_strtoul rather than strtoul.
2066 (my_strtoul): New static function.
2067
2068Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2069
2070 * gencode.c (process_instructions): Generate word64 and uword64
2071 instead of `long long' and `unsigned long long' data types.
2072 * interp.c: #include sysdep.h to get signals, and define default
2073 for SIGBUS.
2074 * (Convert): Work around for Visual-C++ compiler bug with type
2075 conversion.
2076 * support.h: Make things compile under Visual-C++ by using
2077 __int64 instead of `long long'. Change many refs to long long
2078 into word64/uword64 typedefs.
2079
2080Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2081
2082 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2083 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2084 (docdir): Removed.
2085 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2086 (AC_PROG_INSTALL): Added.
2087 (AC_PROG_CC): Moved to before configure.host call.
2088 * configure: Rebuilt.
2089
2090Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2091
2092 * configure.in: Define @SIMCONF@ depending on mips target.
2093 * configure: Rebuild.
2094 * Makefile.in (run): Add @SIMCONF@ to control simulator
2095 construction.
2096 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2097 * interp.c: Remove some debugging, provide more detailed error
2098 messages, update memory accesses to use LOADDRMASK.
2099
2100Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2101
2102 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2103 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2104 stamp-h.
2105 * configure: Rebuild.
2106 * config.in: New file, generated by autoheader.
2107 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2108 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2109 HAVE_ANINT and HAVE_AINT, as appropriate.
2110 * Makefile.in (run): Use @LIBS@ rather than -lm.
2111 (interp.o): Depend upon config.h.
2112 (Makefile): Just rebuild Makefile.
2113 (clean): Remove stamp-h.
2114 (mostlyclean): Make the same as clean, not as distclean.
2115 (config.h, stamp-h): New targets.
2116
2117Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2118
2119 * interp.c (ColdReset): Fix boolean test. Make all simulator
2120 globals static.
2121
2122Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2123
2124 * interp.c (xfer_direct_word, xfer_direct_long,
2125 swap_direct_word, swap_direct_long, xfer_big_word,
2126 xfer_big_long, xfer_little_word, xfer_little_long,
2127 swap_word,swap_long): Added.
2128 * interp.c (ColdReset): Provide function indirection to
2129 host<->simulated_target transfer routines.
2130 * interp.c (sim_store_register, sim_fetch_register): Updated to
2131 make use of indirected transfer routines.
2132
2133Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2134
2135 * gencode.c (process_instructions): Ensure FP ABS instruction
2136 recognised.
2137 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2138 system call support.
2139
2140Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2141
2142 * interp.c (sim_do_command): Complain if callback structure not
2143 initialised.
2144
2145Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2146
2147 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2148 support for Sun hosts.
2149 * Makefile.in (gencode): Ensure the host compiler and libraries
2150 used for cross-hosted build.
2151
2152Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2153
2154 * interp.c, gencode.c: Some more (TODO) tidying.
2155
2156Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2157
2158 * gencode.c, interp.c: Replaced explicit long long references with
2159 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2160 * support.h (SET64LO, SET64HI): Macros added.
2161
2162Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2163
2164 * configure: Regenerate with autoconf 2.7.
2165
2166Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2167
2168 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2169 * support.h: Remove superfluous "1" from #if.
2170 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2171
2172Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2173
2174 * interp.c (StoreFPR): Control UndefinedResult() call on
2175 WARN_RESULT manifest.
2176
2177Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2178
2179 * gencode.c: Tidied instruction decoding, and added FP instruction
2180 support.
2181
2182 * interp.c: Added dineroIII, and BSD profiling support. Also
2183 run-time FP handling.
2184
2185Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2186
2187 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2188 gencode.c, interp.c, support.h: created.
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