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2001-02-19 Fernando Nasser <fnasser@redhat.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
56b48a7a
CD		 12001-02-08 Ben Elliston <bje@redhat.com>
2
3 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
4 (store_memory): Likewise, pass cia to sim_core_write*.
5
d3ee60d9
FCE		 62000-10-19 Frank Ch. Eigler <fche@redhat.com>
7
8 On advice from Chris G. Demetriou <cgd@sibyte.com>:
9 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
10
071da002
AC		 11Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
12
13 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
14 * Makefile.in: Don't delete *.igen when cleaning directory.
15
a28c02cd
AC		 16Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
17
18 * m16.igen (break): Call SignalException not sim_engine_halt.
19
80ee11fa
AC		 20Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
21
22 From Jason Eckhardt:
23 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
24
673388c0
AC		 25Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
26
27 * mips.igen (MxC1, DMxC1): Fix printf formatting.
28
4c0deff4
NC		 292000-05-24 Michael Hayes <mhayes@cygnus.com>
30
31 * mips.igen (do_dmultx): Fix typo.
32
eb2d80b4
AC		 33Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
34
35 * configure: Regenerated to track ../common/aclocal.m4 changes.
36
dd37a34b
AC		 37Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
38
39 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
40
4c0deff4
NC		 412000-04-12 Frank Ch. Eigler <fche@redhat.com>
42
43 * sim-main.h (GPR_CLEAR): Define macro.
44
e30db738
AC		 45Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
46
47 * interp.c (decode_coproc): Output long using %lx and not %s.
48
cb7450ea
FCE		 492000-03-21 Frank Ch. Eigler <fche@redhat.com>
50
51 * interp.c (sim_open): Sort & extend dummy memory regions for
52 --board=jmr3904 for eCos.
53
a3027dd7
FCE		 542000-03-02 Frank Ch. Eigler <fche@redhat.com>
55
56 * configure: Regenerated.
57
58Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
59
60 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
61 calls, conditional on the simulator being in verbose mode.
62
dfcd3bfb
JM		 63Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
64
65 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
66 cache don't get ReservedInstruction traps.
67
c2d11a7d
JM		 681999-11-29 Mark Salter <msalter@cygnus.com>
69
70 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
71 to clear status bits in sdisr register. This is how the hardware works.
72
73 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
74 being used by cygmon.
75
4ce44c66
JM		 761999-11-11 Andrew Haley <aph@cygnus.com>
77
78 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
79 instructions.
80
cff3e48b
JM		 81Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
82
83 * mips.igen (MULT): Correct previous mis-applied patch.
84
d4f3574e
SS		 85Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
86
87 * mips.igen (delayslot32): Handle sequence like
88 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
89 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
90 (MULT): Actually pass the third register...
91
921999-09-03 Mark Salter <msalter@cygnus.com>
93
94 * interp.c (sim_open): Added more memory aliases for additional
95 hardware being touched by cygmon on jmr3904 board.
96
97Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
98
99 * configure: Regenerated to track ../common/aclocal.m4 changes.
100
a0b3c4fd
JM		 101Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
102
103 * interp.c (sim_store_register): Handle case where client - GDB -
104 specifies that a 4 byte register is 8 bytes in size.
105 (sim_fetch_register): Ditto.
106
adf40b2e
JM		 1071999-07-14 Frank Ch. Eigler <fche@cygnus.com>
108
109 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
110 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
111 (idt_monitor_base): Base address for IDT monitor traps.
112 (pmon_monitor_base): Ditto for PMON.
113 (lsipmon_monitor_base): Ditto for LSI PMON.
114 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
115 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
116 (sim_firmware_command): New function.
117 (mips_option_handler): Call it for OPTION_FIRMWARE.
118 (sim_open): Allocate memory for idt_monitor region. If "--board"
119 option was given, add no monitor by default. Add BREAK hooks only if
120 monitors are also there.
121
43e526b9
JM		 122Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
123
124 * interp.c (sim_monitor): Flush output before reading input.
125
126Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
127
128 * tconfig.in (SIM_HANDLES_LMA): Always define.
129
130Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
131
132 From Mark Salter <msalter@cygnus.com>:
133 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
134 (sim_open): Add setup for BSP board.
135
9846de1b
JM		 136Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
137
138 * mips.igen (MULT, MULTU): Add syntax for two operand version.
139 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
140 them as unimplemented.
141
cd0fc7c3
SS		 1421999-05-08 Felix Lee <flee@cygnus.com>
143
144 * configure: Regenerated to track ../common/aclocal.m4 changes.
145
7a292a7a
SS		 1461999-04-21 Frank Ch. Eigler <fche@cygnus.com>
147
148 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
149
150Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
151
152 * configure.in: Any mips64vr5*-*-* target should have
153 -DTARGET_ENABLE_FR=1.
154 (default_endian): Any mips64vr*el-*-* target should default to
155 LITTLE_ENDIAN.
156 * configure: Re-generate.
157
1581999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
159
160 * mips.igen (ldl): Extend from _16_, not 32.
161
162Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
163
164 * interp.c (sim_store_register): Force registers written to by GDB
165 into an un-interpreted state.
166
c906108c
SS		 1671999-02-05 Frank Ch. Eigler <fche@cygnus.com>
168
169 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
170 CPU, start periodic background I/O polls.
171 (tx3904sio_poll): New function: periodic I/O poller.
172
1731998-12-30 Frank Ch. Eigler <fche@cygnus.com>
174
175 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
176
177Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
178
179 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
180 case statement.
181
1821998-12-29 Frank Ch. Eigler <fche@cygnus.com>
183
184 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
185 (load_word): Call SIM_CORE_SIGNAL hook on error.
186 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
187 starting. For exception dispatching, pass PC instead of NULL_CIA.
188 (decode_coproc): Use COP0_BADVADDR to store faulting address.
189 * sim-main.h (COP0_BADVADDR): Define.
190 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
191 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
192 (_sim_cpu): Add exc_* fields to store register value snapshots.
193 * mips.igen (*): Replace memory-related SignalException* calls
194 with references to SIM_CORE_SIGNAL hook.
195
196 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
197 fix.
198 * sim-main.c (*): Minor warning cleanups.
199
2001998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
201
202 * m16.igen (DADDIU5): Correct type-o.
203
204Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
205
206 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
207 variables.
208
209Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
210
211 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
212 to include path.
213 (interp.o): Add dependency on itable.h
214 (oengine.c, gencode): Delete remaining references.
215 (BUILT_SRC_FROM_GEN): Clean up.
216
2171998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
218
219 * vr4run.c: New.
220 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
221 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
222 tmp-run-hack) : New.
223 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
224 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
225 Drop the "64" qualifier to get the HACK generator working.
226 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
227 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
228 qualifier to get the hack generator working.
229 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
230 (DSLL): Use do_dsll.
231 (DSLLV): Use do_dsllv.
232 (DSRA): Use do_dsra.
233 (DSRL): Use do_dsrl.
234 (DSRLV): Use do_dsrlv.
235 (BC1): Move *vr4100 to get the HACK generator working.
236 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
237 get the HACK generator working.
238 (MACC) Rename to get the HACK generator working.
239 (DMACC,MACCS,DMACCS): Add the 64.
240
2411998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
242
243 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
244 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
245
2461998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
247
248 * mips/interp.c (DEBUG): Cleanups.
249
2501998-12-10 Frank Ch. Eigler <fche@cygnus.com>
251
252 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
253 (tx3904sio_tickle): fflush after a stdout character output.
254
2551998-12-03 Frank Ch. Eigler <fche@cygnus.com>
256
257 * interp.c (sim_close): Uninstall modules.
258
259Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
260
261 * sim-main.h, interp.c (sim_monitor): Change to global
262 function.
263
264Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
265
266 * configure.in (vr4100): Only include vr4100 instructions in
267 simulator.
268 * configure: Re-generate.
269 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
270
271Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
272
273 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
274 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
275 true alternative.
276
277 * configure.in (sim_default_gen, sim_use_gen): Replace with
278 sim_gen.
279 (--enable-sim-igen): Delete config option. Always using IGEN.
280 * configure: Re-generate.
281
282 * Makefile.in (gencode): Kill, kill, kill.
283 * gencode.c: Ditto.
284
285Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
286
287 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
288 bit mips16 igen simulator.
289 * configure: Re-generate.
290
291 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
292 as part of vr4100 ISA.
293 * vr.igen: Mark all instructions as 64 bit only.
294
295Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
296
297 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
298 Pacify GCC.
299
300Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
301
302 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
303 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
304 * configure: Re-generate.
305
306 * m16.igen (BREAK): Define breakpoint instruction.
307 (JALX32): Mark instruction as mips16 and not r3900.
308 * mips.igen (C.cond.fmt): Fix typo in instruction format.
309
310 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
311
312Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
313
314 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
315 insn as a debug breakpoint.
316
317 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
318 pending.slot_size.
319 (PENDING_SCHED): Clean up trace statement.
320 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
321 (PENDING_FILL): Delay write by only one cycle.
322 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
323
324 * sim-main.c (pending_tick): Clean up trace statements. Add trace
325 of pending writes.
326 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
327 32 & 64.
328 (pending_tick): Move incrementing of index to FOR statement.
329 (pending_tick): Only update PENDING_OUT after a write has occured.
330
331 * configure.in: Add explicit mips-lsi-* target. Use gencode to
332 build simulator.
333 * configure: Re-generate.
334
335 * interp.c (sim_engine_run OLD): Delete explicit call to
336 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
337
338Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
339
340 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
341 interrupt level number to match changed SignalExceptionInterrupt
342 macro.
343
344Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
345
346 * interp.c: #include "itable.h" if WITH_IGEN.
347 (get_insn_name): New function.
348 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
349 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
350
351Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
352
353 * configure: Rebuilt to inhale new common/aclocal.m4.
354
355Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
356
357 * dv-tx3904sio.c: Include sim-assert.h.
358
359Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
360
361 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
362 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
363 Reorganize target-specific sim-hardware checks.
364 * configure: rebuilt.
365 * interp.c (sim_open): For tx39 target boards, set
366 OPERATING_ENVIRONMENT, add tx3904sio devices.
367 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
368 ROM executables. Install dv-sockser into sim-modules list.
369
370 * dv-tx3904irc.c: Compiler warning clean-up.
371 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
372 frequent hw-trace messages.
373
374Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
375
376 * vr.igen (MulAcc): Identify as a vr4100 specific function.
377
378Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
379
380 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
381
382 * vr.igen: New file.
383 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
384 * mips.igen: Define vr4100 model. Include vr.igen.
385Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
386
387 * mips.igen (check_mf_hilo): Correct check.
388
389Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
390
391 * sim-main.h (interrupt_event): Add prototype.
392
393 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
394 register_ptr, register_value.
395 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
396
397 * sim-main.h (tracefh): Make extern.
398
399Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
400
401 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
402 Reduce unnecessarily high timer event frequency.
403 * dv-tx3904cpu.c: Ditto for interrupt event.
404
405Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
406
407 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
408 to allay warnings.
409 (interrupt_event): Made non-static.
410
411 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
412 interchange of configuration values for external vs. internal
413 clock dividers.
414
415Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
416
417 * mips.igen (BREAK): Moved code to here for
418 simulator-reserved break instructions.
419 * gencode.c (build_instruction): Ditto.
420 * interp.c (signal_exception): Code moved from here. Non-
421 reserved instructions now use exception vector, rather
422 than halting sim.
423 * sim-main.h: Moved magic constants to here.
424
425Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
426
427 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
428 register upon non-zero interrupt event level, clear upon zero
429 event value.
430 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
431 by passing zero event value.
432 (*_io_{read,write}_buffer): Endianness fixes.
433 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
434 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
435
436 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
437 serial I/O and timer module at base address 0xFFFF0000.
438
439Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
440
441 * mips.igen (SWC1) : Correct the handling of ReverseEndian
442 and BigEndianCPU.
443
444Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
445
446 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
447 parts.
448 * configure: Update.
449
450Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
451
452 * dv-tx3904tmr.c: New file - implements tx3904 timer.
453 * dv-tx3904{irc,cpu}.c: Mild reformatting.
454 * configure.in: Include tx3904tmr in hw_device list.
455 * configure: Rebuilt.
456 * interp.c (sim_open): Instantiate three timer instances.
457 Fix address typo of tx3904irc instance.
458
459Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
460
461 * interp.c (signal_exception): SystemCall exception now uses
462 the exception vector.
463
464Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
465
466 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
467 to allay warnings.
468
469Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
470
471 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
472
473Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
474
475 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
476
477 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
478 sim-main.h. Declare a struct hw_descriptor instead of struct
479 hw_device_descriptor.
480
481Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
482
483 * mips.igen (do_store_left, do_load_left): Compute nr of left and
484 right bits and then re-align left hand bytes to correct byte
485 lanes. Fix incorrect computation in do_store_left when loading
486 bytes from second word.
487
488Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
489
490 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
491 * interp.c (sim_open): Only create a device tree when HW is
492 enabled.
493
494 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
495 * interp.c (signal_exception): Ditto.
496
497Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
498
499 * gencode.c: Mark BEGEZALL as LIKELY.
500
501Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
502
503 * sim-main.h (ALU32_END): Sign extend 32 bit results.
504 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
505
506Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
507
508 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
509 modules. Recognize TX39 target with "mips*tx39" pattern.
510 * configure: Rebuilt.
511 * sim-main.h (*): Added many macros defining bits in
512 TX39 control registers.
513 (SignalInterrupt): Send actual PC instead of NULL.
514 (SignalNMIReset): New exception type.
515 * interp.c (board): New variable for future use to identify
516 a particular board being simulated.
517 (mips_option_handler,mips_options): Added "--board" option.
518 (interrupt_event): Send actual PC.
519 (sim_open): Make memory layout conditional on board setting.
520 (signal_exception): Initial implementation of hardware interrupt
521 handling. Accept another break instruction variant for simulator
522 exit.
523 (decode_coproc): Implement RFE instruction for TX39.
524 (mips.igen): Decode RFE instruction as such.
525 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
526 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
527 bbegin to implement memory map.
528 * dv-tx3904cpu.c: New file.
529 * dv-tx3904irc.c: New file.
530
531Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
532
533 * mips.igen (check_mt_hilo): Create a separate r3900 version.
534
535Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
536
537 * tx.igen (madd,maddu): Replace calls to check_op_hilo
538 with calls to check_div_hilo.
539
540Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
541
542 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
543 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
544 Add special r3900 version of do_mult_hilo.
545 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
546 with calls to check_mult_hilo.
547 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
548 with calls to check_div_hilo.
549
550Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
551
552 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
553 Document a replacement.
554
555Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
556
557 * interp.c (sim_monitor): Make mon_printf work.
558
559Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
560
561 * sim-main.h (INSN_NAME): New arg `cpu'.
562
563Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
564
565 * configure: Regenerated to track ../common/aclocal.m4 changes.
566
567Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
568
569 * configure: Regenerated to track ../common/aclocal.m4 changes.
570 * config.in: Ditto.
571
572Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
573
574 * acconfig.h: New file.
575 * configure.in: Reverted change of Apr 24; use sinclude again.
576
577Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
578
579 * configure: Regenerated to track ../common/aclocal.m4 changes.
580 * config.in: Ditto.
581
582Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
583
584 * configure.in: Don't call sinclude.
585
586Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
587
588 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
589
590Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
591
592 * mips.igen (ERET): Implement.
593
594 * interp.c (decode_coproc): Return sign-extended EPC.
595
596 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
597
598 * interp.c (signal_exception): Do not ignore Trap.
599 (signal_exception): On TRAP, restart at exception address.
600 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
601 (signal_exception): Update.
602 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
603 so that TRAP instructions are caught.
604
605Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
606
607 * sim-main.h (struct hilo_access, struct hilo_history): Define,
608 contains HI/LO access history.
609 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
610 (HIACCESS, LOACCESS): Delete, replace with
611 (HIHISTORY, LOHISTORY): New macros.
612 (CHECKHILO): Delete all, moved to mips.igen
613
614 * gencode.c (build_instruction): Do not generate checks for
615 correct HI/LO register usage.
616
617 * interp.c (old_engine_run): Delete checks for correct HI/LO
618 register usage.
619
620 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
621 check_mf_cycles): New functions.
622 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
623 do_divu, domultx, do_mult, do_multu): Use.
624
625 * tx.igen ("madd", "maddu"): Use.
626
627Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
628
629 * mips.igen (DSRAV): Use function do_dsrav.
630 (SRAV): Use new function do_srav.
631
632 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
633 (B): Sign extend 11 bit immediate.
634 (EXT-B*): Shift 16 bit immediate left by 1.
635 (ADDIU*): Don't sign extend immediate value.
636
637Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
638
639 * m16run.c (sim_engine_run): Restore CIA after handling an event.
640
641 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
642 functions.
643
644 * mips.igen (delayslot32, nullify_next_insn): New functions.
645 (m16.igen): Always include.
646 (do_*): Add more tracing.
647
648 * m16.igen (delayslot16): Add NIA argument, could be called by a
649 32 bit MIPS16 instruction.
650
651 * interp.c (ifetch16): Move function from here.
652 * sim-main.c (ifetch16): To here.
653
654 * sim-main.c (ifetch16, ifetch32): Update to match current
655 implementations of LH, LW.
656 (signal_exception): Don't print out incorrect hex value of illegal
657 instruction.
658
659Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
660
661 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
662 instruction.
663
664 * m16.igen: Implement MIPS16 instructions.
665
666 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
667 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
668 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
669 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
670 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
671 bodies of corresponding code from 32 bit insn to these. Also used
672 by MIPS16 versions of functions.
673
674 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
675 (IMEM16): Drop NR argument from macro.
676
677Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
678
679 * Makefile.in (SIM_OBJS): Add sim-main.o.
680
681 * sim-main.h (address_translation, load_memory, store_memory,
682 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
683 as INLINE_SIM_MAIN.
684 (pr_addr, pr_uword64): Declare.
685 (sim-main.c): Include when H_REVEALS_MODULE_P.
686
687 * interp.c (address_translation, load_memory, store_memory,
688 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
689 from here.
690 * sim-main.c: To here. Fix compilation problems.
691
692 * configure.in: Enable inlining.
693 * configure: Re-config.
694
695Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
696
697 * configure: Regenerated to track ../common/aclocal.m4 changes.
698
699Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
700
701 * mips.igen: Include tx.igen.
702 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
703 * tx.igen: New file, contains MADD and MADDU.
704
705 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
706 the hardwired constant `7'.
707 (store_memory): Ditto.
708 (LOADDRMASK): Move definition to sim-main.h.
709
710 mips.igen (MTC0): Enable for r3900.
711 (ADDU): Add trace.
712
713 mips.igen (do_load_byte): Delete.
714 (do_load, do_store, do_load_left, do_load_write, do_store_left,
715 do_store_right): New functions.
716 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
717
718 configure.in: Let the tx39 use igen again.
719 configure: Update.
720
721Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
722
723 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
724 not an address sized quantity. Return zero for cache sizes.
725
726Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
727
728 * mips.igen (r3900): r3900 does not support 64 bit integer
729 operations.
730
731Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
732
733 * configure.in (mipstx39*-*-*): Use gencode simulator rather
734 than igen one.
735 * configure : Rebuild.
736
737Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
738
739 * configure: Regenerated to track ../common/aclocal.m4 changes.
740
741Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
742
743 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
744
745Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
746
747 * configure: Regenerated to track ../common/aclocal.m4 changes.
748 * config.in: Regenerated to track ../common/aclocal.m4 changes.
749
750Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
751
752 * configure: Regenerated to track ../common/aclocal.m4 changes.
753
754Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
755
756 * interp.c (Max, Min): Comment out functions. Not yet used.
757
758Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
759
760 * configure: Regenerated to track ../common/aclocal.m4 changes.
761
762Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
763
764 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
765 configurable settings for stand-alone simulator.
766
767 * configure.in: Added X11 search, just in case.
768
769 * configure: Regenerated.
770
771Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
772
773 * interp.c (sim_write, sim_read, load_memory, store_memory):
774 Replace sim_core_*_map with read_map, write_map, exec_map resp.
775
776Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
777
778 * sim-main.h (GETFCC): Return an unsigned value.
779
780Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
781
782 * mips.igen (DIV): Fix check for -1 / MIN_INT.
783 (DADD): Result destination is RD not RT.
784
785Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
786
787 * sim-main.h (HIACCESS, LOACCESS): Always define.
788
789 * mdmx.igen (Maxi, Mini): Rename Max, Min.
790
791 * interp.c (sim_info): Delete.
792
793Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
794
795 * interp.c (DECLARE_OPTION_HANDLER): Use it.
796 (mips_option_handler): New argument `cpu'.
797 (sim_open): Update call to sim_add_option_table.
798
799Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
800
801 * mips.igen (CxC1): Add tracing.
802
803Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
804
805 * sim-main.h (Max, Min): Declare.
806
807 * interp.c (Max, Min): New functions.
808
809 * mips.igen (BC1): Add tracing.
810
811Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
812
813 * interp.c Added memory map for stack in vr4100
814
815Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
816
817 * interp.c (load_memory): Add missing "break"'s.
818
819Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
820
821 * interp.c (sim_store_register, sim_fetch_register): Pass in
822 length parameter. Return -1.
823
824Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
825
826 * interp.c: Added hardware init hook, fixed warnings.
827
828Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
829
830 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
831
832Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
833
834 * interp.c (ifetch16): New function.
835
836 * sim-main.h (IMEM32): Rename IMEM.
837 (IMEM16_IMMED): Define.
838 (IMEM16): Define.
839 (DELAY_SLOT): Update.
840
841 * m16run.c (sim_engine_run): New file.
842
843 * m16.igen: All instructions except LB.
844 (LB): Call do_load_byte.
845 * mips.igen (do_load_byte): New function.
846 (LB): Call do_load_byte.
847
848 * mips.igen: Move spec for insn bit size and high bit from here.
849 * Makefile.in (tmp-igen, tmp-m16): To here.
850
851 * m16.dc: New file, decode mips16 instructions.
852
853 * Makefile.in (SIM_NO_ALL): Define.
854 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
855
856Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
857
858 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
859 point unit to 32 bit registers.
860 * configure: Re-generate.
861
862Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
863
864 * configure.in (sim_use_gen): Make IGEN the default simulator
865 generator for generic 32 and 64 bit mips targets.
866 * configure: Re-generate.
867
868Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
869
870 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
871 bitsize.
872
873 * interp.c (sim_fetch_register, sim_store_register): Read/write
874 FGR from correct location.
875 (sim_open): Set size of FGR's according to
876 WITH_TARGET_FLOATING_POINT_BITSIZE.
877
878 * sim-main.h (FGR): Store floating point registers in a separate
879 array.
880
881Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
882
883 * configure: Regenerated to track ../common/aclocal.m4 changes.
884
885Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
886
887 * interp.c (ColdReset): Call PENDING_INVALIDATE.
888
889 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
890
891 * interp.c (pending_tick): New function. Deliver pending writes.
892
893 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
894 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
895 it can handle mixed sized quantites and single bits.
896
897Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
898
899 * interp.c (oengine.h): Do not include when building with IGEN.
900 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
901 (sim_info): Ditto for PROCESSOR_64BIT.
902 (sim_monitor): Replace ut_reg with unsigned_word.
903 (*): Ditto for t_reg.
904 (LOADDRMASK): Define.
905 (sim_open): Remove defunct check that host FP is IEEE compliant,
906 using software to emulate floating point.
907 (value_fpr, ...): Always compile, was conditional on HASFPU.
908
909Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
910
911 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
912 size.
913
914 * interp.c (SD, CPU): Define.
915 (mips_option_handler): Set flags in each CPU.
916 (interrupt_event): Assume CPU 0 is the one being iterrupted.
917 (sim_close): Do not clear STATE, deleted anyway.
918 (sim_write, sim_read): Assume CPU zero's vm should be used for
919 data transfers.
920 (sim_create_inferior): Set the PC for all processors.
921 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
922 argument.
923 (mips16_entry): Pass correct nr of args to store_word, load_word.
924 (ColdReset): Cold reset all cpu's.
925 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
926 (sim_monitor, load_memory, store_memory, signal_exception): Use
927 `CPU' instead of STATE_CPU.
928
929
930 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
931 SD or CPU_.
932
933 * sim-main.h (signal_exception): Add sim_cpu arg.
934 (SignalException*): Pass both SD and CPU to signal_exception.
935 * interp.c (signal_exception): Update.
936
937 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
938 Ditto
939 (sync_operation, prefetch, cache_op, store_memory, load_memory,
940 address_translation): Ditto
941 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
942
943Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
944
945 * configure: Regenerated to track ../common/aclocal.m4 changes.
946
947Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
948
949 * interp.c (sim_engine_run): Add `nr_cpus' argument.
950
951 * mips.igen (model): Map processor names onto BFD name.
952
953 * sim-main.h (CPU_CIA): Delete.
954 (SET_CIA, GET_CIA): Define
955
956Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
957
958 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
959 regiser.
960
961 * configure.in (default_endian): Configure a big-endian simulator
962 by default.
963 * configure: Re-generate.
964
965Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
966
967 * configure: Regenerated to track ../common/aclocal.m4 changes.
968
969Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
970
971 * interp.c (sim_monitor): Handle Densan monitor outbyte
972 and inbyte functions.
973
9741997-12-29 Felix Lee <flee@cygnus.com>
975
976 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
977
978Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
979
980 * Makefile.in (tmp-igen): Arrange for $zero to always be
981 reset to zero after every instruction.
982
983Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
984
985 * configure: Regenerated to track ../common/aclocal.m4 changes.
986 * config.in: Ditto.
987
988Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
989
990 * mips.igen (MSUB): Fix to work like MADD.
991 * gencode.c (MSUB): Similarly.
992
993Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
994
995 * configure: Regenerated to track ../common/aclocal.m4 changes.
996
997Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
998
999 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1000
1001Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1002
1003 * sim-main.h (sim-fpu.h): Include.
1004
1005 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1006 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1007 using host independant sim_fpu module.
1008
1009Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1010
1011 * interp.c (signal_exception): Report internal errors with SIGABRT
1012 not SIGQUIT.
1013
1014 * sim-main.h (C0_CONFIG): New register.
1015 (signal.h): No longer include.
1016
1017 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1018
1019Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1020
1021 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1022
1023Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1024
1025 * mips.igen: Tag vr5000 instructions.
1026 (ANDI): Was missing mipsIV model, fix assembler syntax.
1027 (do_c_cond_fmt): New function.
1028 (C.cond.fmt): Handle mips I-III which do not support CC field
1029 separatly.
1030 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1031 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1032 in IV3.2 spec.
1033 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1034 vr5000 which saves LO in a GPR separatly.
1035
1036 * configure.in (enable-sim-igen): For vr5000, select vr5000
1037 specific instructions.
1038 * configure: Re-generate.
1039
1040Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1041
1042 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1043
1044 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1045 fmt_uninterpreted_64 bit cases to switch. Convert to
1046 fmt_formatted,
1047
1048 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1049
1050 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1051 as specified in IV3.2 spec.
1052 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1053
1054Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1055
1056 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1057 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1058 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1059 PENDING_FILL versions of instructions. Simplify.
1060 (X): New function.
1061 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1062 instructions.
1063 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1064 a signed value.
1065 (MTHI, MFHI): Disable code checking HI-LO.
1066
1067 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1068 global.
1069 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1070
1071Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1072
1073 * gencode.c (build_mips16_operands): Replace IPC with cia.
1074
1075 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1076 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1077 IPC to `cia'.
1078 (UndefinedResult): Replace function with macro/function
1079 combination.
1080 (sim_engine_run): Don't save PC in IPC.
1081
1082 * sim-main.h (IPC): Delete.
1083
1084
1085 * interp.c (signal_exception, store_word, load_word,
1086 address_translation, load_memory, store_memory, cache_op,
1087 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1088 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1089 current instruction address - cia - argument.
1090 (sim_read, sim_write): Call address_translation directly.
1091 (sim_engine_run): Rename variable vaddr to cia.
1092 (signal_exception): Pass cia to sim_monitor
1093
1094 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1095 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1096 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1097
1098 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1099 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1100 SIM_ASSERT.
1101
1102 * interp.c (signal_exception): Pass restart address to
1103 sim_engine_restart.
1104
1105 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1106 idecode.o): Add dependency.
1107
1108 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1109 Delete definitions
1110 (DELAY_SLOT): Update NIA not PC with branch address.
1111 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1112
1113 * mips.igen: Use CIA not PC in branch calculations.
1114 (illegal): Call SignalException.
1115 (BEQ, ADDIU): Fix assembler.
1116
1117Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1118
1119 * m16.igen (JALX): Was missing.
1120
1121 * configure.in (enable-sim-igen): New configuration option.
1122 * configure: Re-generate.
1123
1124 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1125
1126 * interp.c (load_memory, store_memory): Delete parameter RAW.
1127 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1128 bypassing {load,store}_memory.
1129
1130 * sim-main.h (ByteSwapMem): Delete definition.
1131
1132 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1133
1134 * interp.c (sim_do_command, sim_commands): Delete mips specific
1135 commands. Handled by module sim-options.
1136
1137 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1138 (WITH_MODULO_MEMORY): Define.
1139
1140 * interp.c (sim_info): Delete code printing memory size.
1141
1142 * interp.c (mips_size): Nee sim_size, delete function.
1143 (power2): Delete.
1144 (monitor, monitor_base, monitor_size): Delete global variables.
1145 (sim_open, sim_close): Delete code creating monitor and other
1146 memory regions. Use sim-memopts module, via sim_do_commandf, to
1147 manage memory regions.
1148 (load_memory, store_memory): Use sim-core for memory model.
1149
1150 * interp.c (address_translation): Delete all memory map code
1151 except line forcing 32 bit addresses.
1152
1153Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1154
1155 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1156 trace options.
1157
1158 * interp.c (logfh, logfile): Delete globals.
1159 (sim_open, sim_close): Delete code opening & closing log file.
1160 (mips_option_handler): Delete -l and -n options.
1161 (OPTION mips_options): Ditto.
1162
1163 * interp.c (OPTION mips_options): Rename option trace to dinero.
1164 (mips_option_handler): Update.
1165
1166Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1167
1168 * interp.c (fetch_str): New function.
1169 (sim_monitor): Rewrite using sim_read & sim_write.
1170 (sim_open): Check magic number.
1171 (sim_open): Write monitor vectors into memory using sim_write.
1172 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1173 (sim_read, sim_write): Simplify - transfer data one byte at a
1174 time.
1175 (load_memory, store_memory): Clarify meaning of parameter RAW.
1176
1177 * sim-main.h (isHOST): Defete definition.
1178 (isTARGET): Mark as depreciated.
1179 (address_translation): Delete parameter HOST.
1180
1181 * interp.c (address_translation): Delete parameter HOST.
1182
1183Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1184
1185 * mips.igen:
1186
1187 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1188 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1189
1190Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 * mips.igen: Add model filter field to records.
1193
1194Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1195
1196 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1197
1198 interp.c (sim_engine_run): Do not compile function sim_engine_run
1199 when WITH_IGEN == 1.
1200
1201 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1202 target architecture.
1203
1204 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1205 igen. Replace with configuration variables sim_igen_flags /
1206 sim_m16_flags.
1207
1208 * m16.igen: New file. Copy mips16 insns here.
1209 * mips.igen: From here.
1210
1211Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1212
1213 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1214 to top.
1215 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1216
1217Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1218
1219 * gencode.c (build_instruction): Follow sim_write's lead in using
1220 BigEndianMem instead of !ByteSwapMem.
1221
1222Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1223
1224 * configure.in (sim_gen): Dependent on target, select type of
1225 generator. Always select old style generator.
1226
1227 configure: Re-generate.
1228
1229 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1230 targets.
1231 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1232 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1233 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1234 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1235 SIM_@sim_gen@_*, set by autoconf.
1236
1237Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1238
1239 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1240
1241 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1242 CURRENT_FLOATING_POINT instead.
1243
1244 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1245 (address_translation): Raise exception InstructionFetch when
1246 translation fails and isINSTRUCTION.
1247
1248 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1249 sim_engine_run): Change type of of vaddr and paddr to
1250 address_word.
1251 (address_translation, prefetch, load_memory, store_memory,
1252 cache_op): Change type of vAddr and pAddr to address_word.
1253
1254 * gencode.c (build_instruction): Change type of vaddr and paddr to
1255 address_word.
1256
1257Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1260 macro to obtain result of ALU op.
1261
1262Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * interp.c (sim_info): Call profile_print.
1265
1266Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1267
1268 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1269
1270 * sim-main.h (WITH_PROFILE): Do not define, defined in
1271 common/sim-config.h. Use sim-profile module.
1272 (simPROFILE): Delete defintion.
1273
1274 * interp.c (PROFILE): Delete definition.
1275 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1276 (sim_close): Delete code writing profile histogram.
1277 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1278 Delete.
1279 (sim_engine_run): Delete code profiling the PC.
1280
1281Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1284
1285 * interp.c (sim_monitor): Make register pointers of type
1286 unsigned_word*.
1287
1288 * sim-main.h: Make registers of type unsigned_word not
1289 signed_word.
1290
1291Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1292
1293 * interp.c (sync_operation): Rename from SyncOperation, make
1294 global, add SD argument.
1295 (prefetch): Rename from Prefetch, make global, add SD argument.
1296 (decode_coproc): Make global.
1297
1298 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1299
1300 * gencode.c (build_instruction): Generate DecodeCoproc not
1301 decode_coproc calls.
1302
1303 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1304 (SizeFGR): Move to sim-main.h
1305 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1306 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1307 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1308 sim-main.h.
1309 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1310 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1311 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1312 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1313 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1314 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1315
1316 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1317 exception.
1318 (sim-alu.h): Include.
1319 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1320 (sim_cia): Typedef to instruction_address.
1321
1322Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1323
1324 * Makefile.in (interp.o): Rename generated file engine.c to
1325 oengine.c.
1326
1327 * interp.c: Update.
1328
1329Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1330
1331 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1332
1333Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334
1335 * gencode.c (build_instruction): For "FPSQRT", output correct
1336 number of arguments to Recip.
1337
1338Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1339
1340 * Makefile.in (interp.o): Depends on sim-main.h
1341
1342 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1343
1344 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1345 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1346 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1347 STATE, DSSTATE): Define
1348 (GPR, FGRIDX, ..): Define.
1349
1350 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1351 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1352 (GPR, FGRIDX, ...): Delete macros.
1353
1354 * interp.c: Update names to match defines from sim-main.h
1355
1356Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1357
1358 * interp.c (sim_monitor): Add SD argument.
1359 (sim_warning): Delete. Replace calls with calls to
1360 sim_io_eprintf.
1361 (sim_error): Delete. Replace calls with sim_io_error.
1362 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1363 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1364 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1365 argument.
1366 (mips_size): Rename from sim_size. Add SD argument.
1367
1368 * interp.c (simulator): Delete global variable.
1369 (callback): Delete global variable.
1370 (mips_option_handler, sim_open, sim_write, sim_read,
1371 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1372 sim_size,sim_monitor): Use sim_io_* not callback->*.
1373 (sim_open): ZALLOC simulator struct.
1374 (PROFILE): Do not define.
1375
1376Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1377
1378 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1379 support.h with corresponding code.
1380
1381 * sim-main.h (word64, uword64), support.h: Move definition to
1382 sim-main.h.
1383 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1384
1385 * support.h: Delete
1386 * Makefile.in: Update dependencies
1387 * interp.c: Do not include.
1388
1389Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390
1391 * interp.c (address_translation, load_memory, store_memory,
1392 cache_op): Rename to from AddressTranslation et.al., make global,
1393 add SD argument
1394
1395 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1396 CacheOp): Define.
1397
1398 * interp.c (SignalException): Rename to signal_exception, make
1399 global.
1400
1401 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1402
1403 * sim-main.h (SignalException, SignalExceptionInterrupt,
1404 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1405 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1406 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1407 Define.
1408
1409 * interp.c, support.h: Use.
1410
1411Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1412
1413 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1414 to value_fpr / store_fpr. Add SD argument.
1415 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1416 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1417
1418 * sim-main.h (ValueFPR, StoreFPR): Define.
1419
1420Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1421
1422 * interp.c (sim_engine_run): Check consistency between configure
1423 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1424 and HASFPU.
1425
1426 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1427 (mips_fpu): Configure WITH_FLOATING_POINT.
1428 (mips_endian): Configure WITH_TARGET_ENDIAN.
1429 * configure: Update.
1430
1431Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1432
1433 * configure: Regenerated to track ../common/aclocal.m4 changes.
1434
1435Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1436
1437 * configure: Regenerated.
1438
1439Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1440
1441 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1442
1443Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1444
1445 * gencode.c (print_igen_insn_models): Assume certain architectures
1446 include all mips* instructions.
1447 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1448 instruction.
1449
1450 * Makefile.in (tmp.igen): Add target. Generate igen input from
1451 gencode file.
1452
1453 * gencode.c (FEATURE_IGEN): Define.
1454 (main): Add --igen option. Generate output in igen format.
1455 (process_instructions): Format output according to igen option.
1456 (print_igen_insn_format): New function.
1457 (print_igen_insn_models): New function.
1458 (process_instructions): Only issue warnings and ignore
1459 instructions when no FEATURE_IGEN.
1460
1461Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1462
1463 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1464 MIPS targets.
1465
1466Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1467
1468 * configure: Regenerated to track ../common/aclocal.m4 changes.
1469
1470Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1471
1472 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1473 SIM_RESERVED_BITS): Delete, moved to common.
1474 (SIM_EXTRA_CFLAGS): Update.
1475
1476Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * configure.in: Configure non-strict memory alignment.
1479 * configure: Regenerated to track ../common/aclocal.m4 changes.
1480
1481Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482
1483 * configure: Regenerated to track ../common/aclocal.m4 changes.
1484
1485Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1486
1487 * gencode.c (SDBBP,DERET): Added (3900) insns.
1488 (RFE): Turn on for 3900.
1489 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1490 (dsstate): Made global.
1491 (SUBTARGET_R3900): Added.
1492 (CANCELDELAYSLOT): New.
1493 (SignalException): Ignore SystemCall rather than ignore and
1494 terminate. Add DebugBreakPoint handling.
1495 (decode_coproc): New insns RFE, DERET; and new registers Debug
1496 and DEPC protected by SUBTARGET_R3900.
1497 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1498 bits explicitly.
1499 * Makefile.in,configure.in: Add mips subtarget option.
1500 * configure: Update.
1501
1502Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1503
1504 * gencode.c: Add r3900 (tx39).
1505
1506
1507Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1508
1509 * gencode.c (build_instruction): Don't need to subtract 4 for
1510 JALR, just 2.
1511
1512Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1513
1514 * interp.c: Correct some HASFPU problems.
1515
1516Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * configure: Regenerated to track ../common/aclocal.m4 changes.
1519
1520Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * interp.c (mips_options): Fix samples option short form, should
1523 be `x'.
1524
1525Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1526
1527 * interp.c (sim_info): Enable info code. Was just returning.
1528
1529Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530
1531 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1532 MFC0.
1533
1534Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1535
1536 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1537 constants.
1538 (build_instruction): Ditto for LL.
1539
1540Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1541
1542 * configure: Regenerated to track ../common/aclocal.m4 changes.
1543
1544Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * configure: Regenerated to track ../common/aclocal.m4 changes.
1547 * config.in: Ditto.
1548
1549Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1550
1551 * interp.c (sim_open): Add call to sim_analyze_program, update
1552 call to sim_config.
1553
1554Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1555
1556 * interp.c (sim_kill): Delete.
1557 (sim_create_inferior): Add ABFD argument. Set PC from same.
1558 (sim_load): Move code initializing trap handlers from here.
1559 (sim_open): To here.
1560 (sim_load): Delete, use sim-hload.c.
1561
1562 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1563
1564Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1565
1566 * configure: Regenerated to track ../common/aclocal.m4 changes.
1567 * config.in: Ditto.
1568
1569Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1570
1571 * interp.c (sim_open): Add ABFD argument.
1572 (sim_load): Move call to sim_config from here.
1573 (sim_open): To here. Check return status.
1574
1575Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1576
1577 * gencode.c (build_instruction): Two arg MADD should
1578 not assign result to $0.
1579
1580Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1581
1582 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1583 * sim/mips/configure.in: Regenerate.
1584
1585Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1586
1587 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1588 signed8, unsigned8 et.al. types.
1589
1590 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1591 hosts when selecting subreg.
1592
1593Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1594
1595 * interp.c (sim_engine_run): Reset the ZERO register to zero
1596 regardless of FEATURE_WARN_ZERO.
1597 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1598
1599Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1600
1601 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1602 (SignalException): For BreakPoints ignore any mode bits and just
1603 save the PC.
1604 (SignalException): Always set the CAUSE register.
1605
1606Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1607
1608 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1609 exception has been taken.
1610
1611 * interp.c: Implement the ERET and mt/f sr instructions.
1612
1613Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * interp.c (SignalException): Don't bother restarting an
1616 interrupt.
1617
1618Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1619
1620 * interp.c (SignalException): Really take an interrupt.
1621 (interrupt_event): Only deliver interrupts when enabled.
1622
1623Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1624
1625 * interp.c (sim_info): Only print info when verbose.
1626 (sim_info) Use sim_io_printf for output.
1627
1628Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1631 mips architectures.
1632
1633Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1634
1635 * interp.c (sim_do_command): Check for common commands if a
1636 simulator specific command fails.
1637
1638Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1639
1640 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1641 and simBE when DEBUG is defined.
1642
1643Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1644
1645 * interp.c (interrupt_event): New function. Pass exception event
1646 onto exception handler.
1647
1648 * configure.in: Check for stdlib.h.
1649 * configure: Regenerate.
1650
1651 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1652 variable declaration.
1653 (build_instruction): Initialize memval1.
1654 (build_instruction): Add UNUSED attribute to byte, bigend,
1655 reverse.
1656 (build_operands): Ditto.
1657
1658 * interp.c: Fix GCC warnings.
1659 (sim_get_quit_code): Delete.
1660
1661 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1662 * Makefile.in: Ditto.
1663 * configure: Re-generate.
1664
1665 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1666
1667Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1668
1669 * interp.c (mips_option_handler): New function parse argumes using
1670 sim-options.
1671 (myname): Replace with STATE_MY_NAME.
1672 (sim_open): Delete check for host endianness - performed by
1673 sim_config.
1674 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1675 (sim_open): Move much of the initialization from here.
1676 (sim_load): To here. After the image has been loaded and
1677 endianness set.
1678 (sim_open): Move ColdReset from here.
1679 (sim_create_inferior): To here.
1680 (sim_open): Make FP check less dependant on host endianness.
1681
1682 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1683 run.
1684 * interp.c (sim_set_callbacks): Delete.
1685
1686 * interp.c (membank, membank_base, membank_size): Replace with
1687 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1688 (sim_open): Remove call to callback->init. gdb/run do this.
1689
1690 * interp.c: Update
1691
1692 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1693
1694 * interp.c (big_endian_p): Delete, replaced by
1695 current_target_byte_order.
1696
1697Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1698
1699 * interp.c (host_read_long, host_read_word, host_swap_word,
1700 host_swap_long): Delete. Using common sim-endian.
1701 (sim_fetch_register, sim_store_register): Use H2T.
1702 (pipeline_ticks): Delete. Handled by sim-events.
1703 (sim_info): Update.
1704 (sim_engine_run): Update.
1705
1706Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1707
1708 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1709 reason from here.
1710 (SignalException): To here. Signal using sim_engine_halt.
1711 (sim_stop_reason): Delete, moved to common.
1712
1713Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1714
1715 * interp.c (sim_open): Add callback argument.
1716 (sim_set_callbacks): Delete SIM_DESC argument.
1717 (sim_size): Ditto.
1718
1719Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * Makefile.in (SIM_OBJS): Add common modules.
1722
1723 * interp.c (sim_set_callbacks): Also set SD callback.
1724 (set_endianness, xfer_*, swap_*): Delete.
1725 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1726 Change to functions using sim-endian macros.
1727 (control_c, sim_stop): Delete, use common version.
1728 (simulate): Convert into.
1729 (sim_engine_run): This function.
1730 (sim_resume): Delete.
1731
1732 * interp.c (simulation): New variable - the simulator object.
1733 (sim_kind): Delete global - merged into simulation.
1734 (sim_load): Cleanup. Move PC assignment from here.
1735 (sim_create_inferior): To here.
1736
1737 * sim-main.h: New file.
1738 * interp.c (sim-main.h): Include.
1739
1740Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1741
1742 * configure: Regenerated to track ../common/aclocal.m4 changes.
1743
1744Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1745
1746 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1747
1748Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1749
1750 * gencode.c (build_instruction): DIV instructions: check
1751 for division by zero and integer overflow before using
1752 host's division operation.
1753
1754Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1755
1756 * Makefile.in (SIM_OBJS): Add sim-load.o.
1757 * interp.c: #include bfd.h.
1758 (target_byte_order): Delete.
1759 (sim_kind, myname, big_endian_p): New static locals.
1760 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1761 after argument parsing. Recognize -E arg, set endianness accordingly.
1762 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1763 load file into simulator. Set PC from bfd.
1764 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1765 (set_endianness): Use big_endian_p instead of target_byte_order.
1766
1767Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1768
1769 * interp.c (sim_size): Delete prototype - conflicts with
1770 definition in remote-sim.h. Correct definition.
1771
1772Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1773
1774 * configure: Regenerated to track ../common/aclocal.m4 changes.
1775 * config.in: Ditto.
1776
1777Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1778
1779 * interp.c (sim_open): New arg `kind'.
1780
1781 * configure: Regenerated to track ../common/aclocal.m4 changes.
1782
1783Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1784
1785 * configure: Regenerated to track ../common/aclocal.m4 changes.
1786
1787Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1788
1789 * interp.c (sim_open): Set optind to 0 before calling getopt.
1790
1791Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1792
1793 * configure: Regenerated to track ../common/aclocal.m4 changes.
1794
1795Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1796
1797 * interp.c : Replace uses of pr_addr with pr_uword64
1798 where the bit length is always 64 independent of SIM_ADDR.
1799 (pr_uword64) : added.
1800
1801Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1802
1803 * configure: Re-generate.
1804
1805Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1806
1807 * configure: Regenerate to track ../common/aclocal.m4 changes.
1808
1809Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1810
1811 * interp.c (sim_open): New SIM_DESC result. Argument is now
1812 in argv form.
1813 (other sim_*): New SIM_DESC argument.
1814
1815Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1816
1817 * interp.c: Fix printing of addresses for non-64-bit targets.
1818 (pr_addr): Add function to print address based on size.
1819
1820Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1821
1822 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1823
1824Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1825
1826 * gencode.c (build_mips16_operands): Correct computation of base
1827 address for extended PC relative instruction.
1828
1829Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1830
1831 * interp.c (mips16_entry): Add support for floating point cases.
1832 (SignalException): Pass floating point cases to mips16_entry.
1833 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1834 registers.
1835 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1836 or fmt_word.
1837 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1838 and then set the state to fmt_uninterpreted.
1839 (COP_SW): Temporarily set the state to fmt_word while calling
1840 ValueFPR.
1841
1842Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1843
1844 * gencode.c (build_instruction): The high order may be set in the
1845 comparison flags at any ISA level, not just ISA 4.
1846
1847Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1848
1849 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1850 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1851 * configure.in: sinclude ../common/aclocal.m4.
1852 * configure: Regenerated.
1853
1854Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1855
1856 * configure: Rebuild after change to aclocal.m4.
1857
1858Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1859
1860 * configure configure.in Makefile.in: Update to new configure
1861 scheme which is more compatible with WinGDB builds.
1862 * configure.in: Improve comment on how to run autoconf.
1863 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1864 * Makefile.in: Use autoconf substitution to install common
1865 makefile fragment.
1866
1867Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1868
1869 * gencode.c (build_instruction): Use BigEndianCPU instead of
1870 ByteSwapMem.
1871
1872Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1873
1874 * interp.c (sim_monitor): Make output to stdout visible in
1875 wingdb's I/O log window.
1876
1877Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1878
1879 * support.h: Undo previous change to SIGTRAP
1880 and SIGQUIT values.
1881
1882Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1883
1884 * interp.c (store_word, load_word): New static functions.
1885 (mips16_entry): New static function.
1886 (SignalException): Look for mips16 entry and exit instructions.
1887 (simulate): Use the correct index when setting fpr_state after
1888 doing a pending move.
1889
1890Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1891
1892 * interp.c: Fix byte-swapping code throughout to work on
1893 both little- and big-endian hosts.
1894
1895Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1896
1897 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1898 with gdb/config/i386/xm-windows.h.
1899
1900Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1901
1902 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1903 that messes up arithmetic shifts.
1904
1905Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1906
1907 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1908 SIGTRAP and SIGQUIT for _WIN32.
1909
1910Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1911
1912 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1913 force a 64 bit multiplication.
1914 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1915 destination register is 0, since that is the default mips16 nop
1916 instruction.
1917
1918Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1919
1920 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1921 (build_endian_shift): Don't check proc64.
1922 (build_instruction): Always set memval to uword64. Cast op2 to
1923 uword64 when shifting it left in memory instructions. Always use
1924 the same code for stores--don't special case proc64.
1925
1926 * gencode.c (build_mips16_operands): Fix base PC value for PC
1927 relative operands.
1928 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1929 jal instruction.
1930 * interp.c (simJALDELAYSLOT): Define.
1931 (JALDELAYSLOT): Define.
1932 (INDELAYSLOT, INJALDELAYSLOT): Define.
1933 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1934
1935Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1936
1937 * interp.c (sim_open): add flush_cache as a PMON routine
1938 (sim_monitor): handle flush_cache by ignoring it
1939
1940Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1941
1942 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1943 BigEndianMem.
1944 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1945 (BigEndianMem): Rename to ByteSwapMem and change sense.
1946 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1947 BigEndianMem references to !ByteSwapMem.
1948 (set_endianness): New function, with prototype.
1949 (sim_open): Call set_endianness.
1950 (sim_info): Use simBE instead of BigEndianMem.
1951 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1952 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1953 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1954 ifdefs, keeping the prototype declaration.
1955 (swap_word): Rewrite correctly.
1956 (ColdReset): Delete references to CONFIG. Delete endianness related
1957 code; moved to set_endianness.
1958
1959Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1960
1961 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1962 * interp.c (CHECKHILO): Define away.
1963 (simSIGINT): New macro.
1964 (membank_size): Increase from 1MB to 2MB.
1965 (control_c): New function.
1966 (sim_resume): Rename parameter signal to signal_number. Add local
1967 variable prev. Call signal before and after simulate.
1968 (sim_stop_reason): Add simSIGINT support.
1969 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1970 functions always.
1971 (sim_warning): Delete call to SignalException. Do call printf_filtered
1972 if logfh is NULL.
1973 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1974 a call to sim_warning.
1975
1976Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1977
1978 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1979 16 bit instructions.
1980
1981Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1982
1983 Add support for mips16 (16 bit MIPS implementation):
1984 * gencode.c (inst_type): Add mips16 instruction encoding types.
1985 (GETDATASIZEINSN): Define.
1986 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1987 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1988 mtlo.
1989 (MIPS16_DECODE): New table, for mips16 instructions.
1990 (bitmap_val): New static function.
1991 (struct mips16_op): Define.
1992 (mips16_op_table): New table, for mips16 operands.
1993 (build_mips16_operands): New static function.
1994 (process_instructions): If PC is odd, decode a mips16
1995 instruction. Break out instruction handling into new
1996 build_instruction function.
1997 (build_instruction): New static function, broken out of
1998 process_instructions. Check modifiers rather than flags for SHIFT
1999 bit count and m[ft]{hi,lo} direction.
2000 (usage): Pass program name to fprintf.
2001 (main): Remove unused variable this_option_optind. Change
2002 ``*loptarg++'' to ``loptarg++''.
2003 (my_strtoul): Parenthesize && within ||.
2004 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2005 (simulate): If PC is odd, fetch a 16 bit instruction, and
2006 increment PC by 2 rather than 4.
2007 * configure.in: Add case for mips16*-*-*.
2008 * configure: Rebuild.
2009
2010Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2011
2012 * interp.c: Allow -t to enable tracing in standalone simulator.
2013 Fix garbage output in trace file and error messages.
2014
2015Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2016
2017 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2018 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2019 * configure.in: Simplify using macros in ../common/aclocal.m4.
2020 * configure: Regenerated.
2021 * tconfig.in: New file.
2022
2023Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2024
2025 * interp.c: Fix bugs in 64-bit port.
2026 Use ansi function declarations for msvc compiler.
2027 Initialize and test file pointer in trace code.
2028 Prevent duplicate definition of LAST_EMED_REGNUM.
2029
2030Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2031
2032 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2033
2034Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2035
2036 * interp.c (SignalException): Check for explicit terminating
2037 breakpoint value.
2038 * gencode.c: Pass instruction value through SignalException()
2039 calls for Trap, Breakpoint and Syscall.
2040
2041Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2042
2043 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2044 only used on those hosts that provide it.
2045 * configure.in: Add sqrt() to list of functions to be checked for.
2046 * config.in: Re-generated.
2047 * configure: Re-generated.
2048
2049Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2050
2051 * gencode.c (process_instructions): Call build_endian_shift when
2052 expanding STORE RIGHT, to fix swr.
2053 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2054 clear the high bits.
2055 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2056 Fix float to int conversions to produce signed values.
2057
2058Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2059
2060 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2061 (process_instructions): Correct handling of nor instruction.
2062 Correct shift count for 32 bit shift instructions. Correct sign
2063 extension for arithmetic shifts to not shift the number of bits in
2064 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2065 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2066 Fix madd.
2067 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2068 It's OK to have a mult follow a mult. What's not OK is to have a
2069 mult follow an mfhi.
2070 (Convert): Comment out incorrect rounding code.
2071
2072Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2073
2074 * interp.c (sim_monitor): Improved monitor printf
2075 simulation. Tidied up simulator warnings, and added "--log" option
2076 for directing warning message output.
2077 * gencode.c: Use sim_warning() rather than WARNING macro.
2078
2079Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2080
2081 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2082 getopt1.o, rather than on gencode.c. Link objects together.
2083 Don't link against -liberty.
2084 (gencode.o, getopt.o, getopt1.o): New targets.
2085 * gencode.c: Include <ctype.h> and "ansidecl.h".
2086 (AND): Undefine after including "ansidecl.h".
2087 (ULONG_MAX): Define if not defined.
2088 (OP_*): Don't define macros; now defined in opcode/mips.h.
2089 (main): Call my_strtoul rather than strtoul.
2090 (my_strtoul): New static function.
2091
2092Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2093
2094 * gencode.c (process_instructions): Generate word64 and uword64
2095 instead of `long long' and `unsigned long long' data types.
2096 * interp.c: #include sysdep.h to get signals, and define default
2097 for SIGBUS.
2098 * (Convert): Work around for Visual-C++ compiler bug with type
2099 conversion.
2100 * support.h: Make things compile under Visual-C++ by using
2101 __int64 instead of `long long'. Change many refs to long long
2102 into word64/uword64 typedefs.
2103
2104Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2105
2106 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2107 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2108 (docdir): Removed.
2109 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2110 (AC_PROG_INSTALL): Added.
2111 (AC_PROG_CC): Moved to before configure.host call.
2112 * configure: Rebuilt.
2113
2114Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2115
2116 * configure.in: Define @SIMCONF@ depending on mips target.
2117 * configure: Rebuild.
2118 * Makefile.in (run): Add @SIMCONF@ to control simulator
2119 construction.
2120 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2121 * interp.c: Remove some debugging, provide more detailed error
2122 messages, update memory accesses to use LOADDRMASK.
2123
2124Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2125
2126 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2127 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2128 stamp-h.
2129 * configure: Rebuild.
2130 * config.in: New file, generated by autoheader.
2131 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2132 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2133 HAVE_ANINT and HAVE_AINT, as appropriate.
2134 * Makefile.in (run): Use @LIBS@ rather than -lm.
2135 (interp.o): Depend upon config.h.
2136 (Makefile): Just rebuild Makefile.
2137 (clean): Remove stamp-h.
2138 (mostlyclean): Make the same as clean, not as distclean.
2139 (config.h, stamp-h): New targets.
2140
2141Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2142
2143 * interp.c (ColdReset): Fix boolean test. Make all simulator
2144 globals static.
2145
2146Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2147
2148 * interp.c (xfer_direct_word, xfer_direct_long,
2149 swap_direct_word, swap_direct_long, xfer_big_word,
2150 xfer_big_long, xfer_little_word, xfer_little_long,
2151 swap_word,swap_long): Added.
2152 * interp.c (ColdReset): Provide function indirection to
2153 host<->simulated_target transfer routines.
2154 * interp.c (sim_store_register, sim_fetch_register): Updated to
2155 make use of indirected transfer routines.
2156
2157Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2158
2159 * gencode.c (process_instructions): Ensure FP ABS instruction
2160 recognised.
2161 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2162 system call support.
2163
2164Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2165
2166 * interp.c (sim_do_command): Complain if callback structure not
2167 initialised.
2168
2169Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2170
2171 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2172 support for Sun hosts.
2173 * Makefile.in (gencode): Ensure the host compiler and libraries
2174 used for cross-hosted build.
2175
2176Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2177
2178 * interp.c, gencode.c: Some more (TODO) tidying.
2179
2180Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2181
2182 * gencode.c, interp.c: Replaced explicit long long references with
2183 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2184 * support.h (SET64LO, SET64HI): Macros added.
2185
2186Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2187
2188 * configure: Regenerate with autoconf 2.7.
2189
2190Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2191
2192 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2193 * support.h: Remove superfluous "1" from #if.
2194 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2195
2196Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2197
2198 * interp.c (StoreFPR): Control UndefinedResult() call on
2199 WARN_RESULT manifest.
2200
2201Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2202
2203 * gencode.c: Tidied instruction decoding, and added FP instruction
2204 support.
2205
2206 * interp.c: Added dineroIII, and BSD profiling support. Also
2207 run-time FP handling.
2208
2209Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2210
2211 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2212 gencode.c, interp.c, support.h: created.
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