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2001-11-17 Fred Fish <fnf@redhat.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
9e52972e
FF		 12001-11-17 Fred Fish <fnf@redhat.com>
2
3 * sim-main.h (float_operation): Move enum declaration outside
4 of _sim_cpu struct declaration.
5
c0efbca4
JB		 62001-04-12 Jim Blandy <jimb@redhat.com>
7
8 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
9 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
10 set of the FCSR.
11 * sim-main.h (COCIDX): Remove definition; this isn't supported by
12 PENDING_FILL, and you can get the intended effect gracefully by
13 calling PENDING_SCHED directly.
14
fb891446
BE		 152001-02-23 Ben Elliston <bje@redhat.com>
16
17 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
18 already defined elsewhere.
19
8030f857
BE		 202001-02-19 Ben Elliston <bje@redhat.com>
21
22 * sim-main.h (sim_monitor): Return an int.
23 * interp.c (sim_monitor): Add return values.
24 (signal_exception): Handle error conditions from sim_monitor.
25
56b48a7a
CD		 262001-02-08 Ben Elliston <bje@redhat.com>
27
28 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
29 (store_memory): Likewise, pass cia to sim_core_write*.
30
d3ee60d9
FCE		 312000-10-19 Frank Ch. Eigler <fche@redhat.com>
32
33 On advice from Chris G. Demetriou <cgd@sibyte.com>:
34 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
35
071da002
AC		 36Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
37
38 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
39 * Makefile.in: Don't delete *.igen when cleaning directory.
40
a28c02cd
AC		 41Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
42
43 * m16.igen (break): Call SignalException not sim_engine_halt.
44
80ee11fa
AC		 45Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
46
47 From Jason Eckhardt:
48 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
49
673388c0
AC		 50Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
51
52 * mips.igen (MxC1, DMxC1): Fix printf formatting.
53
4c0deff4
NC		 542000-05-24 Michael Hayes <mhayes@cygnus.com>
55
56 * mips.igen (do_dmultx): Fix typo.
57
eb2d80b4
AC		 58Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
59
60 * configure: Regenerated to track ../common/aclocal.m4 changes.
61
dd37a34b
AC		 62Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
63
64 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
65
4c0deff4
NC		 662000-04-12 Frank Ch. Eigler <fche@redhat.com>
67
68 * sim-main.h (GPR_CLEAR): Define macro.
69
e30db738
AC		 70Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
71
72 * interp.c (decode_coproc): Output long using %lx and not %s.
73
cb7450ea
FCE		 742000-03-21 Frank Ch. Eigler <fche@redhat.com>
75
76 * interp.c (sim_open): Sort & extend dummy memory regions for
77 --board=jmr3904 for eCos.
78
a3027dd7
FCE		 792000-03-02 Frank Ch. Eigler <fche@redhat.com>
80
81 * configure: Regenerated.
82
83Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
84
85 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
86 calls, conditional on the simulator being in verbose mode.
87
dfcd3bfb
JM		 88Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
89
90 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
91 cache don't get ReservedInstruction traps.
92
c2d11a7d
JM		 931999-11-29 Mark Salter <msalter@cygnus.com>
94
95 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
96 to clear status bits in sdisr register. This is how the hardware works.
97
98 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
99 being used by cygmon.
100
4ce44c66
JM		 1011999-11-11 Andrew Haley <aph@cygnus.com>
102
103 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
104 instructions.
105
cff3e48b
JM		 106Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
107
108 * mips.igen (MULT): Correct previous mis-applied patch.
109
d4f3574e
SS		 110Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
111
112 * mips.igen (delayslot32): Handle sequence like
113 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
114 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
115 (MULT): Actually pass the third register...
116
1171999-09-03 Mark Salter <msalter@cygnus.com>
118
119 * interp.c (sim_open): Added more memory aliases for additional
120 hardware being touched by cygmon on jmr3904 board.
121
122Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
123
124 * configure: Regenerated to track ../common/aclocal.m4 changes.
125
a0b3c4fd
JM		 126Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
127
128 * interp.c (sim_store_register): Handle case where client - GDB -
129 specifies that a 4 byte register is 8 bytes in size.
130 (sim_fetch_register): Ditto.
131
adf40b2e
JM		 1321999-07-14 Frank Ch. Eigler <fche@cygnus.com>
133
134 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
135 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
136 (idt_monitor_base): Base address for IDT monitor traps.
137 (pmon_monitor_base): Ditto for PMON.
138 (lsipmon_monitor_base): Ditto for LSI PMON.
139 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
140 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
141 (sim_firmware_command): New function.
142 (mips_option_handler): Call it for OPTION_FIRMWARE.
143 (sim_open): Allocate memory for idt_monitor region. If "--board"
144 option was given, add no monitor by default. Add BREAK hooks only if
145 monitors are also there.
146
43e526b9
JM		 147Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
148
149 * interp.c (sim_monitor): Flush output before reading input.
150
151Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
152
153 * tconfig.in (SIM_HANDLES_LMA): Always define.
154
155Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
156
157 From Mark Salter <msalter@cygnus.com>:
158 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
159 (sim_open): Add setup for BSP board.
160
9846de1b
JM		 161Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
162
163 * mips.igen (MULT, MULTU): Add syntax for two operand version.
164 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
165 them as unimplemented.
166
cd0fc7c3
SS		 1671999-05-08 Felix Lee <flee@cygnus.com>
168
169 * configure: Regenerated to track ../common/aclocal.m4 changes.
170
7a292a7a
SS		 1711999-04-21 Frank Ch. Eigler <fche@cygnus.com>
172
173 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
174
175Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
176
177 * configure.in: Any mips64vr5*-*-* target should have
178 -DTARGET_ENABLE_FR=1.
179 (default_endian): Any mips64vr*el-*-* target should default to
180 LITTLE_ENDIAN.
181 * configure: Re-generate.
182
1831999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
184
185 * mips.igen (ldl): Extend from _16_, not 32.
186
187Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
188
189 * interp.c (sim_store_register): Force registers written to by GDB
190 into an un-interpreted state.
191
c906108c
SS		 1921999-02-05 Frank Ch. Eigler <fche@cygnus.com>
193
194 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
195 CPU, start periodic background I/O polls.
196 (tx3904sio_poll): New function: periodic I/O poller.
197
1981998-12-30 Frank Ch. Eigler <fche@cygnus.com>
199
200 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
201
202Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
203
204 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
205 case statement.
206
2071998-12-29 Frank Ch. Eigler <fche@cygnus.com>
208
209 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
210 (load_word): Call SIM_CORE_SIGNAL hook on error.
211 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
212 starting. For exception dispatching, pass PC instead of NULL_CIA.
213 (decode_coproc): Use COP0_BADVADDR to store faulting address.
214 * sim-main.h (COP0_BADVADDR): Define.
215 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
216 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
217 (_sim_cpu): Add exc_* fields to store register value snapshots.
218 * mips.igen (*): Replace memory-related SignalException* calls
219 with references to SIM_CORE_SIGNAL hook.
220
221 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
222 fix.
223 * sim-main.c (*): Minor warning cleanups.
224
2251998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
226
227 * m16.igen (DADDIU5): Correct type-o.
228
229Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
230
231 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
232 variables.
233
234Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
235
236 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
237 to include path.
238 (interp.o): Add dependency on itable.h
239 (oengine.c, gencode): Delete remaining references.
240 (BUILT_SRC_FROM_GEN): Clean up.
241
2421998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
243
244 * vr4run.c: New.
245 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
246 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
247 tmp-run-hack) : New.
248 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
249 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
250 Drop the "64" qualifier to get the HACK generator working.
251 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
252 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
253 qualifier to get the hack generator working.
254 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
255 (DSLL): Use do_dsll.
256 (DSLLV): Use do_dsllv.
257 (DSRA): Use do_dsra.
258 (DSRL): Use do_dsrl.
259 (DSRLV): Use do_dsrlv.
260 (BC1): Move *vr4100 to get the HACK generator working.
261 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
262 get the HACK generator working.
263 (MACC) Rename to get the HACK generator working.
264 (DMACC,MACCS,DMACCS): Add the 64.
265
2661998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
267
268 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
269 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
270
2711998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
272
273 * mips/interp.c (DEBUG): Cleanups.
274
2751998-12-10 Frank Ch. Eigler <fche@cygnus.com>
276
277 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
278 (tx3904sio_tickle): fflush after a stdout character output.
279
2801998-12-03 Frank Ch. Eigler <fche@cygnus.com>
281
282 * interp.c (sim_close): Uninstall modules.
283
284Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
285
286 * sim-main.h, interp.c (sim_monitor): Change to global
287 function.
288
289Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
290
291 * configure.in (vr4100): Only include vr4100 instructions in
292 simulator.
293 * configure: Re-generate.
294 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
295
296Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
297
298 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
299 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
300 true alternative.
301
302 * configure.in (sim_default_gen, sim_use_gen): Replace with
303 sim_gen.
304 (--enable-sim-igen): Delete config option. Always using IGEN.
305 * configure: Re-generate.
306
307 * Makefile.in (gencode): Kill, kill, kill.
308 * gencode.c: Ditto.
309
310Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
311
312 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
313 bit mips16 igen simulator.
314 * configure: Re-generate.
315
316 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
317 as part of vr4100 ISA.
318 * vr.igen: Mark all instructions as 64 bit only.
319
320Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
321
322 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
323 Pacify GCC.
324
325Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
326
327 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
328 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
329 * configure: Re-generate.
330
331 * m16.igen (BREAK): Define breakpoint instruction.
332 (JALX32): Mark instruction as mips16 and not r3900.
333 * mips.igen (C.cond.fmt): Fix typo in instruction format.
334
335 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
336
337Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
338
339 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
340 insn as a debug breakpoint.
341
342 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
343 pending.slot_size.
344 (PENDING_SCHED): Clean up trace statement.
345 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
346 (PENDING_FILL): Delay write by only one cycle.
347 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
348
349 * sim-main.c (pending_tick): Clean up trace statements. Add trace
350 of pending writes.
351 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
352 32 & 64.
353 (pending_tick): Move incrementing of index to FOR statement.
354 (pending_tick): Only update PENDING_OUT after a write has occured.
355
356 * configure.in: Add explicit mips-lsi-* target. Use gencode to
357 build simulator.
358 * configure: Re-generate.
359
360 * interp.c (sim_engine_run OLD): Delete explicit call to
361 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
362
363Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
364
365 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
366 interrupt level number to match changed SignalExceptionInterrupt
367 macro.
368
369Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
370
371 * interp.c: #include "itable.h" if WITH_IGEN.
372 (get_insn_name): New function.
373 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
374 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
375
376Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
377
378 * configure: Rebuilt to inhale new common/aclocal.m4.
379
380Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
381
382 * dv-tx3904sio.c: Include sim-assert.h.
383
384Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
385
386 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
387 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
388 Reorganize target-specific sim-hardware checks.
389 * configure: rebuilt.
390 * interp.c (sim_open): For tx39 target boards, set
391 OPERATING_ENVIRONMENT, add tx3904sio devices.
392 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
393 ROM executables. Install dv-sockser into sim-modules list.
394
395 * dv-tx3904irc.c: Compiler warning clean-up.
396 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
397 frequent hw-trace messages.
398
399Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
400
401 * vr.igen (MulAcc): Identify as a vr4100 specific function.
402
403Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
404
405 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
406
407 * vr.igen: New file.
408 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
409 * mips.igen: Define vr4100 model. Include vr.igen.
410Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
411
412 * mips.igen (check_mf_hilo): Correct check.
413
414Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
415
416 * sim-main.h (interrupt_event): Add prototype.
417
418 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
419 register_ptr, register_value.
420 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
421
422 * sim-main.h (tracefh): Make extern.
423
424Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
425
426 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
427 Reduce unnecessarily high timer event frequency.
428 * dv-tx3904cpu.c: Ditto for interrupt event.
429
430Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
431
432 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
433 to allay warnings.
434 (interrupt_event): Made non-static.
435
436 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
437 interchange of configuration values for external vs. internal
438 clock dividers.
439
440Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
441
442 * mips.igen (BREAK): Moved code to here for
443 simulator-reserved break instructions.
444 * gencode.c (build_instruction): Ditto.
445 * interp.c (signal_exception): Code moved from here. Non-
446 reserved instructions now use exception vector, rather
447 than halting sim.
448 * sim-main.h: Moved magic constants to here.
449
450Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
451
452 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
453 register upon non-zero interrupt event level, clear upon zero
454 event value.
455 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
456 by passing zero event value.
457 (*_io_{read,write}_buffer): Endianness fixes.
458 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
459 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
460
461 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
462 serial I/O and timer module at base address 0xFFFF0000.
463
464Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
465
466 * mips.igen (SWC1) : Correct the handling of ReverseEndian
467 and BigEndianCPU.
468
469Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
470
471 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
472 parts.
473 * configure: Update.
474
475Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
476
477 * dv-tx3904tmr.c: New file - implements tx3904 timer.
478 * dv-tx3904{irc,cpu}.c: Mild reformatting.
479 * configure.in: Include tx3904tmr in hw_device list.
480 * configure: Rebuilt.
481 * interp.c (sim_open): Instantiate three timer instances.
482 Fix address typo of tx3904irc instance.
483
484Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
485
486 * interp.c (signal_exception): SystemCall exception now uses
487 the exception vector.
488
489Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
490
491 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
492 to allay warnings.
493
494Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
495
496 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
497
498Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
499
500 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
501
502 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
503 sim-main.h. Declare a struct hw_descriptor instead of struct
504 hw_device_descriptor.
505
506Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
507
508 * mips.igen (do_store_left, do_load_left): Compute nr of left and
509 right bits and then re-align left hand bytes to correct byte
510 lanes. Fix incorrect computation in do_store_left when loading
511 bytes from second word.
512
513Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
514
515 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
516 * interp.c (sim_open): Only create a device tree when HW is
517 enabled.
518
519 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
520 * interp.c (signal_exception): Ditto.
521
522Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
523
524 * gencode.c: Mark BEGEZALL as LIKELY.
525
526Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
527
528 * sim-main.h (ALU32_END): Sign extend 32 bit results.
529 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
530
531Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
532
533 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
534 modules. Recognize TX39 target with "mips*tx39" pattern.
535 * configure: Rebuilt.
536 * sim-main.h (*): Added many macros defining bits in
537 TX39 control registers.
538 (SignalInterrupt): Send actual PC instead of NULL.
539 (SignalNMIReset): New exception type.
540 * interp.c (board): New variable for future use to identify
541 a particular board being simulated.
542 (mips_option_handler,mips_options): Added "--board" option.
543 (interrupt_event): Send actual PC.
544 (sim_open): Make memory layout conditional on board setting.
545 (signal_exception): Initial implementation of hardware interrupt
546 handling. Accept another break instruction variant for simulator
547 exit.
548 (decode_coproc): Implement RFE instruction for TX39.
549 (mips.igen): Decode RFE instruction as such.
550 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
551 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
552 bbegin to implement memory map.
553 * dv-tx3904cpu.c: New file.
554 * dv-tx3904irc.c: New file.
555
556Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
557
558 * mips.igen (check_mt_hilo): Create a separate r3900 version.
559
560Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
561
562 * tx.igen (madd,maddu): Replace calls to check_op_hilo
563 with calls to check_div_hilo.
564
565Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
566
567 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
568 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
569 Add special r3900 version of do_mult_hilo.
570 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
571 with calls to check_mult_hilo.
572 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
573 with calls to check_div_hilo.
574
575Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
576
577 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
578 Document a replacement.
579
580Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
581
582 * interp.c (sim_monitor): Make mon_printf work.
583
584Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
585
586 * sim-main.h (INSN_NAME): New arg `cpu'.
587
588Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
589
590 * configure: Regenerated to track ../common/aclocal.m4 changes.
591
592Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
593
594 * configure: Regenerated to track ../common/aclocal.m4 changes.
595 * config.in: Ditto.
596
597Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
598
599 * acconfig.h: New file.
600 * configure.in: Reverted change of Apr 24; use sinclude again.
601
602Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
603
604 * configure: Regenerated to track ../common/aclocal.m4 changes.
605 * config.in: Ditto.
606
607Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
608
609 * configure.in: Don't call sinclude.
610
611Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
612
613 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
614
615Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
616
617 * mips.igen (ERET): Implement.
618
619 * interp.c (decode_coproc): Return sign-extended EPC.
620
621 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
622
623 * interp.c (signal_exception): Do not ignore Trap.
624 (signal_exception): On TRAP, restart at exception address.
625 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
626 (signal_exception): Update.
627 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
628 so that TRAP instructions are caught.
629
630Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
631
632 * sim-main.h (struct hilo_access, struct hilo_history): Define,
633 contains HI/LO access history.
634 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
635 (HIACCESS, LOACCESS): Delete, replace with
636 (HIHISTORY, LOHISTORY): New macros.
637 (CHECKHILO): Delete all, moved to mips.igen
638
639 * gencode.c (build_instruction): Do not generate checks for
640 correct HI/LO register usage.
641
642 * interp.c (old_engine_run): Delete checks for correct HI/LO
643 register usage.
644
645 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
646 check_mf_cycles): New functions.
647 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
648 do_divu, domultx, do_mult, do_multu): Use.
649
650 * tx.igen ("madd", "maddu"): Use.
651
652Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
653
654 * mips.igen (DSRAV): Use function do_dsrav.
655 (SRAV): Use new function do_srav.
656
657 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
658 (B): Sign extend 11 bit immediate.
659 (EXT-B*): Shift 16 bit immediate left by 1.
660 (ADDIU*): Don't sign extend immediate value.
661
662Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
663
664 * m16run.c (sim_engine_run): Restore CIA after handling an event.
665
666 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
667 functions.
668
669 * mips.igen (delayslot32, nullify_next_insn): New functions.
670 (m16.igen): Always include.
671 (do_*): Add more tracing.
672
673 * m16.igen (delayslot16): Add NIA argument, could be called by a
674 32 bit MIPS16 instruction.
675
676 * interp.c (ifetch16): Move function from here.
677 * sim-main.c (ifetch16): To here.
678
679 * sim-main.c (ifetch16, ifetch32): Update to match current
680 implementations of LH, LW.
681 (signal_exception): Don't print out incorrect hex value of illegal
682 instruction.
683
684Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
685
686 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
687 instruction.
688
689 * m16.igen: Implement MIPS16 instructions.
690
691 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
692 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
693 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
694 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
695 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
696 bodies of corresponding code from 32 bit insn to these. Also used
697 by MIPS16 versions of functions.
698
699 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
700 (IMEM16): Drop NR argument from macro.
701
702Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
703
704 * Makefile.in (SIM_OBJS): Add sim-main.o.
705
706 * sim-main.h (address_translation, load_memory, store_memory,
707 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
708 as INLINE_SIM_MAIN.
709 (pr_addr, pr_uword64): Declare.
710 (sim-main.c): Include when H_REVEALS_MODULE_P.
711
712 * interp.c (address_translation, load_memory, store_memory,
713 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
714 from here.
715 * sim-main.c: To here. Fix compilation problems.
716
717 * configure.in: Enable inlining.
718 * configure: Re-config.
719
720Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
721
722 * configure: Regenerated to track ../common/aclocal.m4 changes.
723
724Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
725
726 * mips.igen: Include tx.igen.
727 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
728 * tx.igen: New file, contains MADD and MADDU.
729
730 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
731 the hardwired constant `7'.
732 (store_memory): Ditto.
733 (LOADDRMASK): Move definition to sim-main.h.
734
735 mips.igen (MTC0): Enable for r3900.
736 (ADDU): Add trace.
737
738 mips.igen (do_load_byte): Delete.
739 (do_load, do_store, do_load_left, do_load_write, do_store_left,
740 do_store_right): New functions.
741 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
742
743 configure.in: Let the tx39 use igen again.
744 configure: Update.
745
746Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
747
748 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
749 not an address sized quantity. Return zero for cache sizes.
750
751Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
752
753 * mips.igen (r3900): r3900 does not support 64 bit integer
754 operations.
755
756Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
757
758 * configure.in (mipstx39*-*-*): Use gencode simulator rather
759 than igen one.
760 * configure : Rebuild.
761
762Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
763
764 * configure: Regenerated to track ../common/aclocal.m4 changes.
765
766Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
767
768 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
769
770Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
771
772 * configure: Regenerated to track ../common/aclocal.m4 changes.
773 * config.in: Regenerated to track ../common/aclocal.m4 changes.
774
775Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * configure: Regenerated to track ../common/aclocal.m4 changes.
778
779Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
780
781 * interp.c (Max, Min): Comment out functions. Not yet used.
782
783Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
784
785 * configure: Regenerated to track ../common/aclocal.m4 changes.
786
787Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
788
789 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
790 configurable settings for stand-alone simulator.
791
792 * configure.in: Added X11 search, just in case.
793
794 * configure: Regenerated.
795
796Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
797
798 * interp.c (sim_write, sim_read, load_memory, store_memory):
799 Replace sim_core_*_map with read_map, write_map, exec_map resp.
800
801Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
802
803 * sim-main.h (GETFCC): Return an unsigned value.
804
805Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
806
807 * mips.igen (DIV): Fix check for -1 / MIN_INT.
808 (DADD): Result destination is RD not RT.
809
810Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
811
812 * sim-main.h (HIACCESS, LOACCESS): Always define.
813
814 * mdmx.igen (Maxi, Mini): Rename Max, Min.
815
816 * interp.c (sim_info): Delete.
817
818Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
819
820 * interp.c (DECLARE_OPTION_HANDLER): Use it.
821 (mips_option_handler): New argument `cpu'.
822 (sim_open): Update call to sim_add_option_table.
823
824Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
825
826 * mips.igen (CxC1): Add tracing.
827
828Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
829
830 * sim-main.h (Max, Min): Declare.
831
832 * interp.c (Max, Min): New functions.
833
834 * mips.igen (BC1): Add tracing.
835
836Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
837
838 * interp.c Added memory map for stack in vr4100
839
840Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
841
842 * interp.c (load_memory): Add missing "break"'s.
843
844Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
845
846 * interp.c (sim_store_register, sim_fetch_register): Pass in
847 length parameter. Return -1.
848
849Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
850
851 * interp.c: Added hardware init hook, fixed warnings.
852
853Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
854
855 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
856
857Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
858
859 * interp.c (ifetch16): New function.
860
861 * sim-main.h (IMEM32): Rename IMEM.
862 (IMEM16_IMMED): Define.
863 (IMEM16): Define.
864 (DELAY_SLOT): Update.
865
866 * m16run.c (sim_engine_run): New file.
867
868 * m16.igen: All instructions except LB.
869 (LB): Call do_load_byte.
870 * mips.igen (do_load_byte): New function.
871 (LB): Call do_load_byte.
872
873 * mips.igen: Move spec for insn bit size and high bit from here.
874 * Makefile.in (tmp-igen, tmp-m16): To here.
875
876 * m16.dc: New file, decode mips16 instructions.
877
878 * Makefile.in (SIM_NO_ALL): Define.
879 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
880
881Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
882
883 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
884 point unit to 32 bit registers.
885 * configure: Re-generate.
886
887Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
888
889 * configure.in (sim_use_gen): Make IGEN the default simulator
890 generator for generic 32 and 64 bit mips targets.
891 * configure: Re-generate.
892
893Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
894
895 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
896 bitsize.
897
898 * interp.c (sim_fetch_register, sim_store_register): Read/write
899 FGR from correct location.
900 (sim_open): Set size of FGR's according to
901 WITH_TARGET_FLOATING_POINT_BITSIZE.
902
903 * sim-main.h (FGR): Store floating point registers in a separate
904 array.
905
906Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
907
908 * configure: Regenerated to track ../common/aclocal.m4 changes.
909
910Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
911
912 * interp.c (ColdReset): Call PENDING_INVALIDATE.
913
914 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
915
916 * interp.c (pending_tick): New function. Deliver pending writes.
917
918 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
919 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
920 it can handle mixed sized quantites and single bits.
921
922Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
923
924 * interp.c (oengine.h): Do not include when building with IGEN.
925 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
926 (sim_info): Ditto for PROCESSOR_64BIT.
927 (sim_monitor): Replace ut_reg with unsigned_word.
928 (*): Ditto for t_reg.
929 (LOADDRMASK): Define.
930 (sim_open): Remove defunct check that host FP is IEEE compliant,
931 using software to emulate floating point.
932 (value_fpr, ...): Always compile, was conditional on HASFPU.
933
934Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
935
936 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
937 size.
938
939 * interp.c (SD, CPU): Define.
940 (mips_option_handler): Set flags in each CPU.
941 (interrupt_event): Assume CPU 0 is the one being iterrupted.
942 (sim_close): Do not clear STATE, deleted anyway.
943 (sim_write, sim_read): Assume CPU zero's vm should be used for
944 data transfers.
945 (sim_create_inferior): Set the PC for all processors.
946 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
947 argument.
948 (mips16_entry): Pass correct nr of args to store_word, load_word.
949 (ColdReset): Cold reset all cpu's.
950 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
951 (sim_monitor, load_memory, store_memory, signal_exception): Use
952 `CPU' instead of STATE_CPU.
953
954
955 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
956 SD or CPU_.
957
958 * sim-main.h (signal_exception): Add sim_cpu arg.
959 (SignalException*): Pass both SD and CPU to signal_exception.
960 * interp.c (signal_exception): Update.
961
962 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
963 Ditto
964 (sync_operation, prefetch, cache_op, store_memory, load_memory,
965 address_translation): Ditto
966 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
967
968Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
969
970 * configure: Regenerated to track ../common/aclocal.m4 changes.
971
972Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
973
974 * interp.c (sim_engine_run): Add `nr_cpus' argument.
975
976 * mips.igen (model): Map processor names onto BFD name.
977
978 * sim-main.h (CPU_CIA): Delete.
979 (SET_CIA, GET_CIA): Define
980
981Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
982
983 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
984 regiser.
985
986 * configure.in (default_endian): Configure a big-endian simulator
987 by default.
988 * configure: Re-generate.
989
990Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
991
992 * configure: Regenerated to track ../common/aclocal.m4 changes.
993
994Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
995
996 * interp.c (sim_monitor): Handle Densan monitor outbyte
997 and inbyte functions.
998
9991997-12-29 Felix Lee <flee@cygnus.com>
1000
1001 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1002
1003Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1004
1005 * Makefile.in (tmp-igen): Arrange for $zero to always be
1006 reset to zero after every instruction.
1007
1008Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1009
1010 * configure: Regenerated to track ../common/aclocal.m4 changes.
1011 * config.in: Ditto.
1012
1013Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1014
1015 * mips.igen (MSUB): Fix to work like MADD.
1016 * gencode.c (MSUB): Similarly.
1017
1018Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1019
1020 * configure: Regenerated to track ../common/aclocal.m4 changes.
1021
1022Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1023
1024 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1025
1026Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1027
1028 * sim-main.h (sim-fpu.h): Include.
1029
1030 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1031 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1032 using host independant sim_fpu module.
1033
1034Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1035
1036 * interp.c (signal_exception): Report internal errors with SIGABRT
1037 not SIGQUIT.
1038
1039 * sim-main.h (C0_CONFIG): New register.
1040 (signal.h): No longer include.
1041
1042 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1043
1044Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1045
1046 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1047
1048Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1049
1050 * mips.igen: Tag vr5000 instructions.
1051 (ANDI): Was missing mipsIV model, fix assembler syntax.
1052 (do_c_cond_fmt): New function.
1053 (C.cond.fmt): Handle mips I-III which do not support CC field
1054 separatly.
1055 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1056 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1057 in IV3.2 spec.
1058 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1059 vr5000 which saves LO in a GPR separatly.
1060
1061 * configure.in (enable-sim-igen): For vr5000, select vr5000
1062 specific instructions.
1063 * configure: Re-generate.
1064
1065Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1066
1067 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1068
1069 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1070 fmt_uninterpreted_64 bit cases to switch. Convert to
1071 fmt_formatted,
1072
1073 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1074
1075 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1076 as specified in IV3.2 spec.
1077 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1078
1079Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1080
1081 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1082 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1083 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1084 PENDING_FILL versions of instructions. Simplify.
1085 (X): New function.
1086 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1087 instructions.
1088 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1089 a signed value.
1090 (MTHI, MFHI): Disable code checking HI-LO.
1091
1092 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1093 global.
1094 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1095
1096Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1097
1098 * gencode.c (build_mips16_operands): Replace IPC with cia.
1099
1100 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1101 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1102 IPC to `cia'.
1103 (UndefinedResult): Replace function with macro/function
1104 combination.
1105 (sim_engine_run): Don't save PC in IPC.
1106
1107 * sim-main.h (IPC): Delete.
1108
1109
1110 * interp.c (signal_exception, store_word, load_word,
1111 address_translation, load_memory, store_memory, cache_op,
1112 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1113 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1114 current instruction address - cia - argument.
1115 (sim_read, sim_write): Call address_translation directly.
1116 (sim_engine_run): Rename variable vaddr to cia.
1117 (signal_exception): Pass cia to sim_monitor
1118
1119 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1120 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1121 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1122
1123 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1124 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1125 SIM_ASSERT.
1126
1127 * interp.c (signal_exception): Pass restart address to
1128 sim_engine_restart.
1129
1130 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1131 idecode.o): Add dependency.
1132
1133 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1134 Delete definitions
1135 (DELAY_SLOT): Update NIA not PC with branch address.
1136 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1137
1138 * mips.igen: Use CIA not PC in branch calculations.
1139 (illegal): Call SignalException.
1140 (BEQ, ADDIU): Fix assembler.
1141
1142Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1143
1144 * m16.igen (JALX): Was missing.
1145
1146 * configure.in (enable-sim-igen): New configuration option.
1147 * configure: Re-generate.
1148
1149 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1150
1151 * interp.c (load_memory, store_memory): Delete parameter RAW.
1152 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1153 bypassing {load,store}_memory.
1154
1155 * sim-main.h (ByteSwapMem): Delete definition.
1156
1157 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1158
1159 * interp.c (sim_do_command, sim_commands): Delete mips specific
1160 commands. Handled by module sim-options.
1161
1162 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1163 (WITH_MODULO_MEMORY): Define.
1164
1165 * interp.c (sim_info): Delete code printing memory size.
1166
1167 * interp.c (mips_size): Nee sim_size, delete function.
1168 (power2): Delete.
1169 (monitor, monitor_base, monitor_size): Delete global variables.
1170 (sim_open, sim_close): Delete code creating monitor and other
1171 memory regions. Use sim-memopts module, via sim_do_commandf, to
1172 manage memory regions.
1173 (load_memory, store_memory): Use sim-core for memory model.
1174
1175 * interp.c (address_translation): Delete all memory map code
1176 except line forcing 32 bit addresses.
1177
1178Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1179
1180 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1181 trace options.
1182
1183 * interp.c (logfh, logfile): Delete globals.
1184 (sim_open, sim_close): Delete code opening & closing log file.
1185 (mips_option_handler): Delete -l and -n options.
1186 (OPTION mips_options): Ditto.
1187
1188 * interp.c (OPTION mips_options): Rename option trace to dinero.
1189 (mips_option_handler): Update.
1190
1191Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1192
1193 * interp.c (fetch_str): New function.
1194 (sim_monitor): Rewrite using sim_read & sim_write.
1195 (sim_open): Check magic number.
1196 (sim_open): Write monitor vectors into memory using sim_write.
1197 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1198 (sim_read, sim_write): Simplify - transfer data one byte at a
1199 time.
1200 (load_memory, store_memory): Clarify meaning of parameter RAW.
1201
1202 * sim-main.h (isHOST): Defete definition.
1203 (isTARGET): Mark as depreciated.
1204 (address_translation): Delete parameter HOST.
1205
1206 * interp.c (address_translation): Delete parameter HOST.
1207
1208Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1209
1210 * mips.igen:
1211
1212 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1213 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1214
1215Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1216
1217 * mips.igen: Add model filter field to records.
1218
1219Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1220
1221 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1222
1223 interp.c (sim_engine_run): Do not compile function sim_engine_run
1224 when WITH_IGEN == 1.
1225
1226 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1227 target architecture.
1228
1229 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1230 igen. Replace with configuration variables sim_igen_flags /
1231 sim_m16_flags.
1232
1233 * m16.igen: New file. Copy mips16 insns here.
1234 * mips.igen: From here.
1235
1236Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1237
1238 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1239 to top.
1240 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1241
1242Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1243
1244 * gencode.c (build_instruction): Follow sim_write's lead in using
1245 BigEndianMem instead of !ByteSwapMem.
1246
1247Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1248
1249 * configure.in (sim_gen): Dependent on target, select type of
1250 generator. Always select old style generator.
1251
1252 configure: Re-generate.
1253
1254 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1255 targets.
1256 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1257 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1258 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1259 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1260 SIM_@sim_gen@_*, set by autoconf.
1261
1262Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1265
1266 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1267 CURRENT_FLOATING_POINT instead.
1268
1269 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1270 (address_translation): Raise exception InstructionFetch when
1271 translation fails and isINSTRUCTION.
1272
1273 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1274 sim_engine_run): Change type of of vaddr and paddr to
1275 address_word.
1276 (address_translation, prefetch, load_memory, store_memory,
1277 cache_op): Change type of vAddr and pAddr to address_word.
1278
1279 * gencode.c (build_instruction): Change type of vaddr and paddr to
1280 address_word.
1281
1282Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1283
1284 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1285 macro to obtain result of ALU op.
1286
1287Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1288
1289 * interp.c (sim_info): Call profile_print.
1290
1291Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1292
1293 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1294
1295 * sim-main.h (WITH_PROFILE): Do not define, defined in
1296 common/sim-config.h. Use sim-profile module.
1297 (simPROFILE): Delete defintion.
1298
1299 * interp.c (PROFILE): Delete definition.
1300 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1301 (sim_close): Delete code writing profile histogram.
1302 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1303 Delete.
1304 (sim_engine_run): Delete code profiling the PC.
1305
1306Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1307
1308 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1309
1310 * interp.c (sim_monitor): Make register pointers of type
1311 unsigned_word*.
1312
1313 * sim-main.h: Make registers of type unsigned_word not
1314 signed_word.
1315
1316Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1317
1318 * interp.c (sync_operation): Rename from SyncOperation, make
1319 global, add SD argument.
1320 (prefetch): Rename from Prefetch, make global, add SD argument.
1321 (decode_coproc): Make global.
1322
1323 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1324
1325 * gencode.c (build_instruction): Generate DecodeCoproc not
1326 decode_coproc calls.
1327
1328 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1329 (SizeFGR): Move to sim-main.h
1330 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1331 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1332 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1333 sim-main.h.
1334 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1335 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1336 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1337 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1338 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1339 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1340
1341 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1342 exception.
1343 (sim-alu.h): Include.
1344 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1345 (sim_cia): Typedef to instruction_address.
1346
1347Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1348
1349 * Makefile.in (interp.o): Rename generated file engine.c to
1350 oengine.c.
1351
1352 * interp.c: Update.
1353
1354Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1355
1356 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1357
1358Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1359
1360 * gencode.c (build_instruction): For "FPSQRT", output correct
1361 number of arguments to Recip.
1362
1363Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1364
1365 * Makefile.in (interp.o): Depends on sim-main.h
1366
1367 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1368
1369 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1370 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1371 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1372 STATE, DSSTATE): Define
1373 (GPR, FGRIDX, ..): Define.
1374
1375 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1376 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1377 (GPR, FGRIDX, ...): Delete macros.
1378
1379 * interp.c: Update names to match defines from sim-main.h
1380
1381Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1382
1383 * interp.c (sim_monitor): Add SD argument.
1384 (sim_warning): Delete. Replace calls with calls to
1385 sim_io_eprintf.
1386 (sim_error): Delete. Replace calls with sim_io_error.
1387 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1388 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1389 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1390 argument.
1391 (mips_size): Rename from sim_size. Add SD argument.
1392
1393 * interp.c (simulator): Delete global variable.
1394 (callback): Delete global variable.
1395 (mips_option_handler, sim_open, sim_write, sim_read,
1396 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1397 sim_size,sim_monitor): Use sim_io_* not callback->*.
1398 (sim_open): ZALLOC simulator struct.
1399 (PROFILE): Do not define.
1400
1401Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1404 support.h with corresponding code.
1405
1406 * sim-main.h (word64, uword64), support.h: Move definition to
1407 sim-main.h.
1408 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1409
1410 * support.h: Delete
1411 * Makefile.in: Update dependencies
1412 * interp.c: Do not include.
1413
1414Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * interp.c (address_translation, load_memory, store_memory,
1417 cache_op): Rename to from AddressTranslation et.al., make global,
1418 add SD argument
1419
1420 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1421 CacheOp): Define.
1422
1423 * interp.c (SignalException): Rename to signal_exception, make
1424 global.
1425
1426 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1427
1428 * sim-main.h (SignalException, SignalExceptionInterrupt,
1429 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1430 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1431 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1432 Define.
1433
1434 * interp.c, support.h: Use.
1435
1436Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437
1438 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1439 to value_fpr / store_fpr. Add SD argument.
1440 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1441 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1442
1443 * sim-main.h (ValueFPR, StoreFPR): Define.
1444
1445Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * interp.c (sim_engine_run): Check consistency between configure
1448 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1449 and HASFPU.
1450
1451 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1452 (mips_fpu): Configure WITH_FLOATING_POINT.
1453 (mips_endian): Configure WITH_TARGET_ENDIAN.
1454 * configure: Update.
1455
1456Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1457
1458 * configure: Regenerated to track ../common/aclocal.m4 changes.
1459
1460Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1461
1462 * configure: Regenerated.
1463
1464Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1465
1466 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1467
1468Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1469
1470 * gencode.c (print_igen_insn_models): Assume certain architectures
1471 include all mips* instructions.
1472 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1473 instruction.
1474
1475 * Makefile.in (tmp.igen): Add target. Generate igen input from
1476 gencode file.
1477
1478 * gencode.c (FEATURE_IGEN): Define.
1479 (main): Add --igen option. Generate output in igen format.
1480 (process_instructions): Format output according to igen option.
1481 (print_igen_insn_format): New function.
1482 (print_igen_insn_models): New function.
1483 (process_instructions): Only issue warnings and ignore
1484 instructions when no FEATURE_IGEN.
1485
1486Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1489 MIPS targets.
1490
1491Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1492
1493 * configure: Regenerated to track ../common/aclocal.m4 changes.
1494
1495Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1496
1497 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1498 SIM_RESERVED_BITS): Delete, moved to common.
1499 (SIM_EXTRA_CFLAGS): Update.
1500
1501Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * configure.in: Configure non-strict memory alignment.
1504 * configure: Regenerated to track ../common/aclocal.m4 changes.
1505
1506Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * configure: Regenerated to track ../common/aclocal.m4 changes.
1509
1510Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1511
1512 * gencode.c (SDBBP,DERET): Added (3900) insns.
1513 (RFE): Turn on for 3900.
1514 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1515 (dsstate): Made global.
1516 (SUBTARGET_R3900): Added.
1517 (CANCELDELAYSLOT): New.
1518 (SignalException): Ignore SystemCall rather than ignore and
1519 terminate. Add DebugBreakPoint handling.
1520 (decode_coproc): New insns RFE, DERET; and new registers Debug
1521 and DEPC protected by SUBTARGET_R3900.
1522 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1523 bits explicitly.
1524 * Makefile.in,configure.in: Add mips subtarget option.
1525 * configure: Update.
1526
1527Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1528
1529 * gencode.c: Add r3900 (tx39).
1530
1531
1532Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1533
1534 * gencode.c (build_instruction): Don't need to subtract 4 for
1535 JALR, just 2.
1536
1537Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1538
1539 * interp.c: Correct some HASFPU problems.
1540
1541Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * configure: Regenerated to track ../common/aclocal.m4 changes.
1544
1545Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1546
1547 * interp.c (mips_options): Fix samples option short form, should
1548 be `x'.
1549
1550Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * interp.c (sim_info): Enable info code. Was just returning.
1553
1554Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1555
1556 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1557 MFC0.
1558
1559Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560
1561 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1562 constants.
1563 (build_instruction): Ditto for LL.
1564
1565Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1566
1567 * configure: Regenerated to track ../common/aclocal.m4 changes.
1568
1569Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1570
1571 * configure: Regenerated to track ../common/aclocal.m4 changes.
1572 * config.in: Ditto.
1573
1574Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1575
1576 * interp.c (sim_open): Add call to sim_analyze_program, update
1577 call to sim_config.
1578
1579Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1580
1581 * interp.c (sim_kill): Delete.
1582 (sim_create_inferior): Add ABFD argument. Set PC from same.
1583 (sim_load): Move code initializing trap handlers from here.
1584 (sim_open): To here.
1585 (sim_load): Delete, use sim-hload.c.
1586
1587 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1588
1589Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1590
1591 * configure: Regenerated to track ../common/aclocal.m4 changes.
1592 * config.in: Ditto.
1593
1594Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595
1596 * interp.c (sim_open): Add ABFD argument.
1597 (sim_load): Move call to sim_config from here.
1598 (sim_open): To here. Check return status.
1599
1600Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1601
1602 * gencode.c (build_instruction): Two arg MADD should
1603 not assign result to $0.
1604
1605Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1606
1607 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1608 * sim/mips/configure.in: Regenerate.
1609
1610Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1611
1612 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1613 signed8, unsigned8 et.al. types.
1614
1615 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1616 hosts when selecting subreg.
1617
1618Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1619
1620 * interp.c (sim_engine_run): Reset the ZERO register to zero
1621 regardless of FEATURE_WARN_ZERO.
1622 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1623
1624Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625
1626 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1627 (SignalException): For BreakPoints ignore any mode bits and just
1628 save the PC.
1629 (SignalException): Always set the CAUSE register.
1630
1631Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1634 exception has been taken.
1635
1636 * interp.c: Implement the ERET and mt/f sr instructions.
1637
1638Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1639
1640 * interp.c (SignalException): Don't bother restarting an
1641 interrupt.
1642
1643Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1644
1645 * interp.c (SignalException): Really take an interrupt.
1646 (interrupt_event): Only deliver interrupts when enabled.
1647
1648Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * interp.c (sim_info): Only print info when verbose.
1651 (sim_info) Use sim_io_printf for output.
1652
1653Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1656 mips architectures.
1657
1658Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1659
1660 * interp.c (sim_do_command): Check for common commands if a
1661 simulator specific command fails.
1662
1663Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1664
1665 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1666 and simBE when DEBUG is defined.
1667
1668Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1669
1670 * interp.c (interrupt_event): New function. Pass exception event
1671 onto exception handler.
1672
1673 * configure.in: Check for stdlib.h.
1674 * configure: Regenerate.
1675
1676 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1677 variable declaration.
1678 (build_instruction): Initialize memval1.
1679 (build_instruction): Add UNUSED attribute to byte, bigend,
1680 reverse.
1681 (build_operands): Ditto.
1682
1683 * interp.c: Fix GCC warnings.
1684 (sim_get_quit_code): Delete.
1685
1686 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1687 * Makefile.in: Ditto.
1688 * configure: Re-generate.
1689
1690 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1691
1692Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1693
1694 * interp.c (mips_option_handler): New function parse argumes using
1695 sim-options.
1696 (myname): Replace with STATE_MY_NAME.
1697 (sim_open): Delete check for host endianness - performed by
1698 sim_config.
1699 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1700 (sim_open): Move much of the initialization from here.
1701 (sim_load): To here. After the image has been loaded and
1702 endianness set.
1703 (sim_open): Move ColdReset from here.
1704 (sim_create_inferior): To here.
1705 (sim_open): Make FP check less dependant on host endianness.
1706
1707 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1708 run.
1709 * interp.c (sim_set_callbacks): Delete.
1710
1711 * interp.c (membank, membank_base, membank_size): Replace with
1712 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1713 (sim_open): Remove call to callback->init. gdb/run do this.
1714
1715 * interp.c: Update
1716
1717 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1718
1719 * interp.c (big_endian_p): Delete, replaced by
1720 current_target_byte_order.
1721
1722Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1723
1724 * interp.c (host_read_long, host_read_word, host_swap_word,
1725 host_swap_long): Delete. Using common sim-endian.
1726 (sim_fetch_register, sim_store_register): Use H2T.
1727 (pipeline_ticks): Delete. Handled by sim-events.
1728 (sim_info): Update.
1729 (sim_engine_run): Update.
1730
1731Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1732
1733 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1734 reason from here.
1735 (SignalException): To here. Signal using sim_engine_halt.
1736 (sim_stop_reason): Delete, moved to common.
1737
1738Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1739
1740 * interp.c (sim_open): Add callback argument.
1741 (sim_set_callbacks): Delete SIM_DESC argument.
1742 (sim_size): Ditto.
1743
1744Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1745
1746 * Makefile.in (SIM_OBJS): Add common modules.
1747
1748 * interp.c (sim_set_callbacks): Also set SD callback.
1749 (set_endianness, xfer_*, swap_*): Delete.
1750 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1751 Change to functions using sim-endian macros.
1752 (control_c, sim_stop): Delete, use common version.
1753 (simulate): Convert into.
1754 (sim_engine_run): This function.
1755 (sim_resume): Delete.
1756
1757 * interp.c (simulation): New variable - the simulator object.
1758 (sim_kind): Delete global - merged into simulation.
1759 (sim_load): Cleanup. Move PC assignment from here.
1760 (sim_create_inferior): To here.
1761
1762 * sim-main.h: New file.
1763 * interp.c (sim-main.h): Include.
1764
1765Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1766
1767 * configure: Regenerated to track ../common/aclocal.m4 changes.
1768
1769Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1770
1771 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1772
1773Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1774
1775 * gencode.c (build_instruction): DIV instructions: check
1776 for division by zero and integer overflow before using
1777 host's division operation.
1778
1779Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1780
1781 * Makefile.in (SIM_OBJS): Add sim-load.o.
1782 * interp.c: #include bfd.h.
1783 (target_byte_order): Delete.
1784 (sim_kind, myname, big_endian_p): New static locals.
1785 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1786 after argument parsing. Recognize -E arg, set endianness accordingly.
1787 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1788 load file into simulator. Set PC from bfd.
1789 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1790 (set_endianness): Use big_endian_p instead of target_byte_order.
1791
1792Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1793
1794 * interp.c (sim_size): Delete prototype - conflicts with
1795 definition in remote-sim.h. Correct definition.
1796
1797Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1798
1799 * configure: Regenerated to track ../common/aclocal.m4 changes.
1800 * config.in: Ditto.
1801
1802Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1803
1804 * interp.c (sim_open): New arg `kind'.
1805
1806 * configure: Regenerated to track ../common/aclocal.m4 changes.
1807
1808Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1809
1810 * configure: Regenerated to track ../common/aclocal.m4 changes.
1811
1812Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1813
1814 * interp.c (sim_open): Set optind to 0 before calling getopt.
1815
1816Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1817
1818 * configure: Regenerated to track ../common/aclocal.m4 changes.
1819
1820Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1821
1822 * interp.c : Replace uses of pr_addr with pr_uword64
1823 where the bit length is always 64 independent of SIM_ADDR.
1824 (pr_uword64) : added.
1825
1826Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1827
1828 * configure: Re-generate.
1829
1830Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1831
1832 * configure: Regenerate to track ../common/aclocal.m4 changes.
1833
1834Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1835
1836 * interp.c (sim_open): New SIM_DESC result. Argument is now
1837 in argv form.
1838 (other sim_*): New SIM_DESC argument.
1839
1840Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1841
1842 * interp.c: Fix printing of addresses for non-64-bit targets.
1843 (pr_addr): Add function to print address based on size.
1844
1845Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1846
1847 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1848
1849Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1850
1851 * gencode.c (build_mips16_operands): Correct computation of base
1852 address for extended PC relative instruction.
1853
1854Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1855
1856 * interp.c (mips16_entry): Add support for floating point cases.
1857 (SignalException): Pass floating point cases to mips16_entry.
1858 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1859 registers.
1860 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1861 or fmt_word.
1862 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1863 and then set the state to fmt_uninterpreted.
1864 (COP_SW): Temporarily set the state to fmt_word while calling
1865 ValueFPR.
1866
1867Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1868
1869 * gencode.c (build_instruction): The high order may be set in the
1870 comparison flags at any ISA level, not just ISA 4.
1871
1872Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1873
1874 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1875 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1876 * configure.in: sinclude ../common/aclocal.m4.
1877 * configure: Regenerated.
1878
1879Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1880
1881 * configure: Rebuild after change to aclocal.m4.
1882
1883Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1884
1885 * configure configure.in Makefile.in: Update to new configure
1886 scheme which is more compatible with WinGDB builds.
1887 * configure.in: Improve comment on how to run autoconf.
1888 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1889 * Makefile.in: Use autoconf substitution to install common
1890 makefile fragment.
1891
1892Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1893
1894 * gencode.c (build_instruction): Use BigEndianCPU instead of
1895 ByteSwapMem.
1896
1897Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1898
1899 * interp.c (sim_monitor): Make output to stdout visible in
1900 wingdb's I/O log window.
1901
1902Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1903
1904 * support.h: Undo previous change to SIGTRAP
1905 and SIGQUIT values.
1906
1907Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1908
1909 * interp.c (store_word, load_word): New static functions.
1910 (mips16_entry): New static function.
1911 (SignalException): Look for mips16 entry and exit instructions.
1912 (simulate): Use the correct index when setting fpr_state after
1913 doing a pending move.
1914
1915Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1916
1917 * interp.c: Fix byte-swapping code throughout to work on
1918 both little- and big-endian hosts.
1919
1920Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1921
1922 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1923 with gdb/config/i386/xm-windows.h.
1924
1925Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1926
1927 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1928 that messes up arithmetic shifts.
1929
1930Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1931
1932 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1933 SIGTRAP and SIGQUIT for _WIN32.
1934
1935Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1936
1937 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1938 force a 64 bit multiplication.
1939 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1940 destination register is 0, since that is the default mips16 nop
1941 instruction.
1942
1943Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1944
1945 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1946 (build_endian_shift): Don't check proc64.
1947 (build_instruction): Always set memval to uword64. Cast op2 to
1948 uword64 when shifting it left in memory instructions. Always use
1949 the same code for stores--don't special case proc64.
1950
1951 * gencode.c (build_mips16_operands): Fix base PC value for PC
1952 relative operands.
1953 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1954 jal instruction.
1955 * interp.c (simJALDELAYSLOT): Define.
1956 (JALDELAYSLOT): Define.
1957 (INDELAYSLOT, INJALDELAYSLOT): Define.
1958 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1959
1960Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1961
1962 * interp.c (sim_open): add flush_cache as a PMON routine
1963 (sim_monitor): handle flush_cache by ignoring it
1964
1965Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1966
1967 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1968 BigEndianMem.
1969 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1970 (BigEndianMem): Rename to ByteSwapMem and change sense.
1971 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1972 BigEndianMem references to !ByteSwapMem.
1973 (set_endianness): New function, with prototype.
1974 (sim_open): Call set_endianness.
1975 (sim_info): Use simBE instead of BigEndianMem.
1976 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1977 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1978 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1979 ifdefs, keeping the prototype declaration.
1980 (swap_word): Rewrite correctly.
1981 (ColdReset): Delete references to CONFIG. Delete endianness related
1982 code; moved to set_endianness.
1983
1984Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1985
1986 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1987 * interp.c (CHECKHILO): Define away.
1988 (simSIGINT): New macro.
1989 (membank_size): Increase from 1MB to 2MB.
1990 (control_c): New function.
1991 (sim_resume): Rename parameter signal to signal_number. Add local
1992 variable prev. Call signal before and after simulate.
1993 (sim_stop_reason): Add simSIGINT support.
1994 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1995 functions always.
1996 (sim_warning): Delete call to SignalException. Do call printf_filtered
1997 if logfh is NULL.
1998 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1999 a call to sim_warning.
2000
2001Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2002
2003 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2004 16 bit instructions.
2005
2006Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2007
2008 Add support for mips16 (16 bit MIPS implementation):
2009 * gencode.c (inst_type): Add mips16 instruction encoding types.
2010 (GETDATASIZEINSN): Define.
2011 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2012 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2013 mtlo.
2014 (MIPS16_DECODE): New table, for mips16 instructions.
2015 (bitmap_val): New static function.
2016 (struct mips16_op): Define.
2017 (mips16_op_table): New table, for mips16 operands.
2018 (build_mips16_operands): New static function.
2019 (process_instructions): If PC is odd, decode a mips16
2020 instruction. Break out instruction handling into new
2021 build_instruction function.
2022 (build_instruction): New static function, broken out of
2023 process_instructions. Check modifiers rather than flags for SHIFT
2024 bit count and m[ft]{hi,lo} direction.
2025 (usage): Pass program name to fprintf.
2026 (main): Remove unused variable this_option_optind. Change
2027 ``*loptarg++'' to ``loptarg++''.
2028 (my_strtoul): Parenthesize && within ||.
2029 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2030 (simulate): If PC is odd, fetch a 16 bit instruction, and
2031 increment PC by 2 rather than 4.
2032 * configure.in: Add case for mips16*-*-*.
2033 * configure: Rebuild.
2034
2035Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2036
2037 * interp.c: Allow -t to enable tracing in standalone simulator.
2038 Fix garbage output in trace file and error messages.
2039
2040Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2041
2042 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2043 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2044 * configure.in: Simplify using macros in ../common/aclocal.m4.
2045 * configure: Regenerated.
2046 * tconfig.in: New file.
2047
2048Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2049
2050 * interp.c: Fix bugs in 64-bit port.
2051 Use ansi function declarations for msvc compiler.
2052 Initialize and test file pointer in trace code.
2053 Prevent duplicate definition of LAST_EMED_REGNUM.
2054
2055Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2056
2057 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2058
2059Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2060
2061 * interp.c (SignalException): Check for explicit terminating
2062 breakpoint value.
2063 * gencode.c: Pass instruction value through SignalException()
2064 calls for Trap, Breakpoint and Syscall.
2065
2066Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2067
2068 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2069 only used on those hosts that provide it.
2070 * configure.in: Add sqrt() to list of functions to be checked for.
2071 * config.in: Re-generated.
2072 * configure: Re-generated.
2073
2074Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2075
2076 * gencode.c (process_instructions): Call build_endian_shift when
2077 expanding STORE RIGHT, to fix swr.
2078 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2079 clear the high bits.
2080 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2081 Fix float to int conversions to produce signed values.
2082
2083Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2084
2085 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2086 (process_instructions): Correct handling of nor instruction.
2087 Correct shift count for 32 bit shift instructions. Correct sign
2088 extension for arithmetic shifts to not shift the number of bits in
2089 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2090 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2091 Fix madd.
2092 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2093 It's OK to have a mult follow a mult. What's not OK is to have a
2094 mult follow an mfhi.
2095 (Convert): Comment out incorrect rounding code.
2096
2097Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2098
2099 * interp.c (sim_monitor): Improved monitor printf
2100 simulation. Tidied up simulator warnings, and added "--log" option
2101 for directing warning message output.
2102 * gencode.c: Use sim_warning() rather than WARNING macro.
2103
2104Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2105
2106 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2107 getopt1.o, rather than on gencode.c. Link objects together.
2108 Don't link against -liberty.
2109 (gencode.o, getopt.o, getopt1.o): New targets.
2110 * gencode.c: Include <ctype.h> and "ansidecl.h".
2111 (AND): Undefine after including "ansidecl.h".
2112 (ULONG_MAX): Define if not defined.
2113 (OP_*): Don't define macros; now defined in opcode/mips.h.
2114 (main): Call my_strtoul rather than strtoul.
2115 (my_strtoul): New static function.
2116
2117Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2118
2119 * gencode.c (process_instructions): Generate word64 and uword64
2120 instead of `long long' and `unsigned long long' data types.
2121 * interp.c: #include sysdep.h to get signals, and define default
2122 for SIGBUS.
2123 * (Convert): Work around for Visual-C++ compiler bug with type
2124 conversion.
2125 * support.h: Make things compile under Visual-C++ by using
2126 __int64 instead of `long long'. Change many refs to long long
2127 into word64/uword64 typedefs.
2128
2129Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2130
2131 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2132 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2133 (docdir): Removed.
2134 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2135 (AC_PROG_INSTALL): Added.
2136 (AC_PROG_CC): Moved to before configure.host call.
2137 * configure: Rebuilt.
2138
2139Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2140
2141 * configure.in: Define @SIMCONF@ depending on mips target.
2142 * configure: Rebuild.
2143 * Makefile.in (run): Add @SIMCONF@ to control simulator
2144 construction.
2145 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2146 * interp.c: Remove some debugging, provide more detailed error
2147 messages, update memory accesses to use LOADDRMASK.
2148
2149Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2150
2151 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2152 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2153 stamp-h.
2154 * configure: Rebuild.
2155 * config.in: New file, generated by autoheader.
2156 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2157 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2158 HAVE_ANINT and HAVE_AINT, as appropriate.
2159 * Makefile.in (run): Use @LIBS@ rather than -lm.
2160 (interp.o): Depend upon config.h.
2161 (Makefile): Just rebuild Makefile.
2162 (clean): Remove stamp-h.
2163 (mostlyclean): Make the same as clean, not as distclean.
2164 (config.h, stamp-h): New targets.
2165
2166Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2167
2168 * interp.c (ColdReset): Fix boolean test. Make all simulator
2169 globals static.
2170
2171Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2172
2173 * interp.c (xfer_direct_word, xfer_direct_long,
2174 swap_direct_word, swap_direct_long, xfer_big_word,
2175 xfer_big_long, xfer_little_word, xfer_little_long,
2176 swap_word,swap_long): Added.
2177 * interp.c (ColdReset): Provide function indirection to
2178 host<->simulated_target transfer routines.
2179 * interp.c (sim_store_register, sim_fetch_register): Updated to
2180 make use of indirected transfer routines.
2181
2182Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2183
2184 * gencode.c (process_instructions): Ensure FP ABS instruction
2185 recognised.
2186 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2187 system call support.
2188
2189Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2190
2191 * interp.c (sim_do_command): Complain if callback structure not
2192 initialised.
2193
2194Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2195
2196 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2197 support for Sun hosts.
2198 * Makefile.in (gencode): Ensure the host compiler and libraries
2199 used for cross-hosted build.
2200
2201Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2202
2203 * interp.c, gencode.c: Some more (TODO) tidying.
2204
2205Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2206
2207 * gencode.c, interp.c: Replaced explicit long long references with
2208 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2209 * support.h (SET64LO, SET64HI): Macros added.
2210
2211Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2212
2213 * configure: Regenerate with autoconf 2.7.
2214
2215Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2216
2217 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2218 * support.h: Remove superfluous "1" from #if.
2219 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2220
2221Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2222
2223 * interp.c (StoreFPR): Control UndefinedResult() call on
2224 WARN_RESULT manifest.
2225
2226Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2227
2228 * gencode.c: Tidied instruction decoding, and added FP instruction
2229 support.
2230
2231 * interp.c: Added dineroIII, and BSD profiling support. Also
2232 run-time FP handling.
2233
2234Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2235
2236 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2237 gencode.c, interp.c, support.h: created.
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