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* cleanup
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d3ee60d9
FCE		 12000-10-19 Frank Ch. Eigler <fche@redhat.com>
2
3 On advice from Chris G. Demetriou <cgd@sibyte.com>:
4 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
5
071da002
AC		 6Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
7
8 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
9 * Makefile.in: Don't delete *.igen when cleaning directory.
10
a28c02cd
AC		 11Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
12
13 * m16.igen (break): Call SignalException not sim_engine_halt.
14
80ee11fa
AC		 15Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
16
17 From Jason Eckhardt:
18 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
19
673388c0
AC		 20Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
21
22 * mips.igen (MxC1, DMxC1): Fix printf formatting.
23
4c0deff4
NC		 242000-05-24 Michael Hayes <mhayes@cygnus.com>
25
26 * mips.igen (do_dmultx): Fix typo.
27
eb2d80b4
AC		 28Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
29
30 * configure: Regenerated to track ../common/aclocal.m4 changes.
31
dd37a34b
AC		 32Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
33
34 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
35
4c0deff4
NC		 362000-04-12 Frank Ch. Eigler <fche@redhat.com>
37
38 * sim-main.h (GPR_CLEAR): Define macro.
39
e30db738
AC		 40Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
41
42 * interp.c (decode_coproc): Output long using %lx and not %s.
43
cb7450ea
FCE		 442000-03-21 Frank Ch. Eigler <fche@redhat.com>
45
46 * interp.c (sim_open): Sort & extend dummy memory regions for
47 --board=jmr3904 for eCos.
48
a3027dd7
FCE		 492000-03-02 Frank Ch. Eigler <fche@redhat.com>
50
51 * configure: Regenerated.
52
53Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
54
55 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
56 calls, conditional on the simulator being in verbose mode.
57
dfcd3bfb
JM		 58Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
59
60 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
61 cache don't get ReservedInstruction traps.
62
c2d11a7d
JM		 631999-11-29 Mark Salter <msalter@cygnus.com>
64
65 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
66 to clear status bits in sdisr register. This is how the hardware works.
67
68 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
69 being used by cygmon.
70
4ce44c66
JM		 711999-11-11 Andrew Haley <aph@cygnus.com>
72
73 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
74 instructions.
75
cff3e48b
JM		 76Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
77
78 * mips.igen (MULT): Correct previous mis-applied patch.
79
d4f3574e
SS		 80Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
81
82 * mips.igen (delayslot32): Handle sequence like
83 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
84 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
85 (MULT): Actually pass the third register...
86
871999-09-03 Mark Salter <msalter@cygnus.com>
88
89 * interp.c (sim_open): Added more memory aliases for additional
90 hardware being touched by cygmon on jmr3904 board.
91
92Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
93
94 * configure: Regenerated to track ../common/aclocal.m4 changes.
95
a0b3c4fd
JM		 96Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
97
98 * interp.c (sim_store_register): Handle case where client - GDB -
99 specifies that a 4 byte register is 8 bytes in size.
100 (sim_fetch_register): Ditto.
101
adf40b2e
JM		 1021999-07-14 Frank Ch. Eigler <fche@cygnus.com>
103
104 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
105 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
106 (idt_monitor_base): Base address for IDT monitor traps.
107 (pmon_monitor_base): Ditto for PMON.
108 (lsipmon_monitor_base): Ditto for LSI PMON.
109 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
110 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
111 (sim_firmware_command): New function.
112 (mips_option_handler): Call it for OPTION_FIRMWARE.
113 (sim_open): Allocate memory for idt_monitor region. If "--board"
114 option was given, add no monitor by default. Add BREAK hooks only if
115 monitors are also there.
116
43e526b9
JM		 117Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
118
119 * interp.c (sim_monitor): Flush output before reading input.
120
121Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
122
123 * tconfig.in (SIM_HANDLES_LMA): Always define.
124
125Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
126
127 From Mark Salter <msalter@cygnus.com>:
128 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
129 (sim_open): Add setup for BSP board.
130
9846de1b
JM		 131Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
132
133 * mips.igen (MULT, MULTU): Add syntax for two operand version.
134 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
135 them as unimplemented.
136
cd0fc7c3
SS		 1371999-05-08 Felix Lee <flee@cygnus.com>
138
139 * configure: Regenerated to track ../common/aclocal.m4 changes.
140
7a292a7a
SS		 1411999-04-21 Frank Ch. Eigler <fche@cygnus.com>
142
143 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
144
145Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
146
147 * configure.in: Any mips64vr5*-*-* target should have
148 -DTARGET_ENABLE_FR=1.
149 (default_endian): Any mips64vr*el-*-* target should default to
150 LITTLE_ENDIAN.
151 * configure: Re-generate.
152
1531999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
154
155 * mips.igen (ldl): Extend from _16_, not 32.
156
157Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
158
159 * interp.c (sim_store_register): Force registers written to by GDB
160 into an un-interpreted state.
161
c906108c
SS		 1621999-02-05 Frank Ch. Eigler <fche@cygnus.com>
163
164 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
165 CPU, start periodic background I/O polls.
166 (tx3904sio_poll): New function: periodic I/O poller.
167
1681998-12-30 Frank Ch. Eigler <fche@cygnus.com>
169
170 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
171
172Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
173
174 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
175 case statement.
176
1771998-12-29 Frank Ch. Eigler <fche@cygnus.com>
178
179 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
180 (load_word): Call SIM_CORE_SIGNAL hook on error.
181 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
182 starting. For exception dispatching, pass PC instead of NULL_CIA.
183 (decode_coproc): Use COP0_BADVADDR to store faulting address.
184 * sim-main.h (COP0_BADVADDR): Define.
185 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
186 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
187 (_sim_cpu): Add exc_* fields to store register value snapshots.
188 * mips.igen (*): Replace memory-related SignalException* calls
189 with references to SIM_CORE_SIGNAL hook.
190
191 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
192 fix.
193 * sim-main.c (*): Minor warning cleanups.
194
1951998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
196
197 * m16.igen (DADDIU5): Correct type-o.
198
199Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
200
201 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
202 variables.
203
204Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
205
206 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
207 to include path.
208 (interp.o): Add dependency on itable.h
209 (oengine.c, gencode): Delete remaining references.
210 (BUILT_SRC_FROM_GEN): Clean up.
211
2121998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
213
214 * vr4run.c: New.
215 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
216 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
217 tmp-run-hack) : New.
218 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
219 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
220 Drop the "64" qualifier to get the HACK generator working.
221 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
222 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
223 qualifier to get the hack generator working.
224 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
225 (DSLL): Use do_dsll.
226 (DSLLV): Use do_dsllv.
227 (DSRA): Use do_dsra.
228 (DSRL): Use do_dsrl.
229 (DSRLV): Use do_dsrlv.
230 (BC1): Move *vr4100 to get the HACK generator working.
231 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
232 get the HACK generator working.
233 (MACC) Rename to get the HACK generator working.
234 (DMACC,MACCS,DMACCS): Add the 64.
235
2361998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
237
238 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
239 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
240
2411998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
242
243 * mips/interp.c (DEBUG): Cleanups.
244
2451998-12-10 Frank Ch. Eigler <fche@cygnus.com>
246
247 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
248 (tx3904sio_tickle): fflush after a stdout character output.
249
2501998-12-03 Frank Ch. Eigler <fche@cygnus.com>
251
252 * interp.c (sim_close): Uninstall modules.
253
254Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
255
256 * sim-main.h, interp.c (sim_monitor): Change to global
257 function.
258
259Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
260
261 * configure.in (vr4100): Only include vr4100 instructions in
262 simulator.
263 * configure: Re-generate.
264 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
265
266Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
267
268 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
269 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
270 true alternative.
271
272 * configure.in (sim_default_gen, sim_use_gen): Replace with
273 sim_gen.
274 (--enable-sim-igen): Delete config option. Always using IGEN.
275 * configure: Re-generate.
276
277 * Makefile.in (gencode): Kill, kill, kill.
278 * gencode.c: Ditto.
279
280Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
281
282 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
283 bit mips16 igen simulator.
284 * configure: Re-generate.
285
286 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
287 as part of vr4100 ISA.
288 * vr.igen: Mark all instructions as 64 bit only.
289
290Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
291
292 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
293 Pacify GCC.
294
295Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
296
297 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
298 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
299 * configure: Re-generate.
300
301 * m16.igen (BREAK): Define breakpoint instruction.
302 (JALX32): Mark instruction as mips16 and not r3900.
303 * mips.igen (C.cond.fmt): Fix typo in instruction format.
304
305 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
306
307Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
308
309 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
310 insn as a debug breakpoint.
311
312 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
313 pending.slot_size.
314 (PENDING_SCHED): Clean up trace statement.
315 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
316 (PENDING_FILL): Delay write by only one cycle.
317 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
318
319 * sim-main.c (pending_tick): Clean up trace statements. Add trace
320 of pending writes.
321 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
322 32 & 64.
323 (pending_tick): Move incrementing of index to FOR statement.
324 (pending_tick): Only update PENDING_OUT after a write has occured.
325
326 * configure.in: Add explicit mips-lsi-* target. Use gencode to
327 build simulator.
328 * configure: Re-generate.
329
330 * interp.c (sim_engine_run OLD): Delete explicit call to
331 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
332
333Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
334
335 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
336 interrupt level number to match changed SignalExceptionInterrupt
337 macro.
338
339Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
340
341 * interp.c: #include "itable.h" if WITH_IGEN.
342 (get_insn_name): New function.
343 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
344 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
345
346Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
347
348 * configure: Rebuilt to inhale new common/aclocal.m4.
349
350Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
351
352 * dv-tx3904sio.c: Include sim-assert.h.
353
354Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
355
356 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
357 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
358 Reorganize target-specific sim-hardware checks.
359 * configure: rebuilt.
360 * interp.c (sim_open): For tx39 target boards, set
361 OPERATING_ENVIRONMENT, add tx3904sio devices.
362 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
363 ROM executables. Install dv-sockser into sim-modules list.
364
365 * dv-tx3904irc.c: Compiler warning clean-up.
366 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
367 frequent hw-trace messages.
368
369Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
370
371 * vr.igen (MulAcc): Identify as a vr4100 specific function.
372
373Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
374
375 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
376
377 * vr.igen: New file.
378 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
379 * mips.igen: Define vr4100 model. Include vr.igen.
380Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
381
382 * mips.igen (check_mf_hilo): Correct check.
383
384Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
385
386 * sim-main.h (interrupt_event): Add prototype.
387
388 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
389 register_ptr, register_value.
390 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
391
392 * sim-main.h (tracefh): Make extern.
393
394Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
395
396 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
397 Reduce unnecessarily high timer event frequency.
398 * dv-tx3904cpu.c: Ditto for interrupt event.
399
400Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
401
402 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
403 to allay warnings.
404 (interrupt_event): Made non-static.
405
406 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
407 interchange of configuration values for external vs. internal
408 clock dividers.
409
410Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
411
412 * mips.igen (BREAK): Moved code to here for
413 simulator-reserved break instructions.
414 * gencode.c (build_instruction): Ditto.
415 * interp.c (signal_exception): Code moved from here. Non-
416 reserved instructions now use exception vector, rather
417 than halting sim.
418 * sim-main.h: Moved magic constants to here.
419
420Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
421
422 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
423 register upon non-zero interrupt event level, clear upon zero
424 event value.
425 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
426 by passing zero event value.
427 (*_io_{read,write}_buffer): Endianness fixes.
428 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
429 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
430
431 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
432 serial I/O and timer module at base address 0xFFFF0000.
433
434Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
435
436 * mips.igen (SWC1) : Correct the handling of ReverseEndian
437 and BigEndianCPU.
438
439Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
440
441 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
442 parts.
443 * configure: Update.
444
445Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
446
447 * dv-tx3904tmr.c: New file - implements tx3904 timer.
448 * dv-tx3904{irc,cpu}.c: Mild reformatting.
449 * configure.in: Include tx3904tmr in hw_device list.
450 * configure: Rebuilt.
451 * interp.c (sim_open): Instantiate three timer instances.
452 Fix address typo of tx3904irc instance.
453
454Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
455
456 * interp.c (signal_exception): SystemCall exception now uses
457 the exception vector.
458
459Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
460
461 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
462 to allay warnings.
463
464Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
465
466 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
467
468Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
469
470 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
471
472 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
473 sim-main.h. Declare a struct hw_descriptor instead of struct
474 hw_device_descriptor.
475
476Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
477
478 * mips.igen (do_store_left, do_load_left): Compute nr of left and
479 right bits and then re-align left hand bytes to correct byte
480 lanes. Fix incorrect computation in do_store_left when loading
481 bytes from second word.
482
483Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
484
485 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
486 * interp.c (sim_open): Only create a device tree when HW is
487 enabled.
488
489 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
490 * interp.c (signal_exception): Ditto.
491
492Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
493
494 * gencode.c: Mark BEGEZALL as LIKELY.
495
496Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
497
498 * sim-main.h (ALU32_END): Sign extend 32 bit results.
499 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
500
501Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
502
503 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
504 modules. Recognize TX39 target with "mips*tx39" pattern.
505 * configure: Rebuilt.
506 * sim-main.h (*): Added many macros defining bits in
507 TX39 control registers.
508 (SignalInterrupt): Send actual PC instead of NULL.
509 (SignalNMIReset): New exception type.
510 * interp.c (board): New variable for future use to identify
511 a particular board being simulated.
512 (mips_option_handler,mips_options): Added "--board" option.
513 (interrupt_event): Send actual PC.
514 (sim_open): Make memory layout conditional on board setting.
515 (signal_exception): Initial implementation of hardware interrupt
516 handling. Accept another break instruction variant for simulator
517 exit.
518 (decode_coproc): Implement RFE instruction for TX39.
519 (mips.igen): Decode RFE instruction as such.
520 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
521 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
522 bbegin to implement memory map.
523 * dv-tx3904cpu.c: New file.
524 * dv-tx3904irc.c: New file.
525
526Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
527
528 * mips.igen (check_mt_hilo): Create a separate r3900 version.
529
530Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
531
532 * tx.igen (madd,maddu): Replace calls to check_op_hilo
533 with calls to check_div_hilo.
534
535Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
536
537 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
538 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
539 Add special r3900 version of do_mult_hilo.
540 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
541 with calls to check_mult_hilo.
542 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
543 with calls to check_div_hilo.
544
545Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
546
547 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
548 Document a replacement.
549
550Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
551
552 * interp.c (sim_monitor): Make mon_printf work.
553
554Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
555
556 * sim-main.h (INSN_NAME): New arg `cpu'.
557
558Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
559
560 * configure: Regenerated to track ../common/aclocal.m4 changes.
561
562Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
563
564 * configure: Regenerated to track ../common/aclocal.m4 changes.
565 * config.in: Ditto.
566
567Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
568
569 * acconfig.h: New file.
570 * configure.in: Reverted change of Apr 24; use sinclude again.
571
572Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
573
574 * configure: Regenerated to track ../common/aclocal.m4 changes.
575 * config.in: Ditto.
576
577Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
578
579 * configure.in: Don't call sinclude.
580
581Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
582
583 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
584
585Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
586
587 * mips.igen (ERET): Implement.
588
589 * interp.c (decode_coproc): Return sign-extended EPC.
590
591 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
592
593 * interp.c (signal_exception): Do not ignore Trap.
594 (signal_exception): On TRAP, restart at exception address.
595 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
596 (signal_exception): Update.
597 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
598 so that TRAP instructions are caught.
599
600Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
601
602 * sim-main.h (struct hilo_access, struct hilo_history): Define,
603 contains HI/LO access history.
604 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
605 (HIACCESS, LOACCESS): Delete, replace with
606 (HIHISTORY, LOHISTORY): New macros.
607 (CHECKHILO): Delete all, moved to mips.igen
608
609 * gencode.c (build_instruction): Do not generate checks for
610 correct HI/LO register usage.
611
612 * interp.c (old_engine_run): Delete checks for correct HI/LO
613 register usage.
614
615 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
616 check_mf_cycles): New functions.
617 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
618 do_divu, domultx, do_mult, do_multu): Use.
619
620 * tx.igen ("madd", "maddu"): Use.
621
622Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
623
624 * mips.igen (DSRAV): Use function do_dsrav.
625 (SRAV): Use new function do_srav.
626
627 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
628 (B): Sign extend 11 bit immediate.
629 (EXT-B*): Shift 16 bit immediate left by 1.
630 (ADDIU*): Don't sign extend immediate value.
631
632Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
633
634 * m16run.c (sim_engine_run): Restore CIA after handling an event.
635
636 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
637 functions.
638
639 * mips.igen (delayslot32, nullify_next_insn): New functions.
640 (m16.igen): Always include.
641 (do_*): Add more tracing.
642
643 * m16.igen (delayslot16): Add NIA argument, could be called by a
644 32 bit MIPS16 instruction.
645
646 * interp.c (ifetch16): Move function from here.
647 * sim-main.c (ifetch16): To here.
648
649 * sim-main.c (ifetch16, ifetch32): Update to match current
650 implementations of LH, LW.
651 (signal_exception): Don't print out incorrect hex value of illegal
652 instruction.
653
654Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
655
656 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
657 instruction.
658
659 * m16.igen: Implement MIPS16 instructions.
660
661 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
662 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
663 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
664 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
665 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
666 bodies of corresponding code from 32 bit insn to these. Also used
667 by MIPS16 versions of functions.
668
669 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
670 (IMEM16): Drop NR argument from macro.
671
672Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
673
674 * Makefile.in (SIM_OBJS): Add sim-main.o.
675
676 * sim-main.h (address_translation, load_memory, store_memory,
677 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
678 as INLINE_SIM_MAIN.
679 (pr_addr, pr_uword64): Declare.
680 (sim-main.c): Include when H_REVEALS_MODULE_P.
681
682 * interp.c (address_translation, load_memory, store_memory,
683 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
684 from here.
685 * sim-main.c: To here. Fix compilation problems.
686
687 * configure.in: Enable inlining.
688 * configure: Re-config.
689
690Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
691
692 * configure: Regenerated to track ../common/aclocal.m4 changes.
693
694Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
695
696 * mips.igen: Include tx.igen.
697 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
698 * tx.igen: New file, contains MADD and MADDU.
699
700 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
701 the hardwired constant `7'.
702 (store_memory): Ditto.
703 (LOADDRMASK): Move definition to sim-main.h.
704
705 mips.igen (MTC0): Enable for r3900.
706 (ADDU): Add trace.
707
708 mips.igen (do_load_byte): Delete.
709 (do_load, do_store, do_load_left, do_load_write, do_store_left,
710 do_store_right): New functions.
711 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
712
713 configure.in: Let the tx39 use igen again.
714 configure: Update.
715
716Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
717
718 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
719 not an address sized quantity. Return zero for cache sizes.
720
721Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
722
723 * mips.igen (r3900): r3900 does not support 64 bit integer
724 operations.
725
726Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
727
728 * configure.in (mipstx39*-*-*): Use gencode simulator rather
729 than igen one.
730 * configure : Rebuild.
731
732Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
733
734 * configure: Regenerated to track ../common/aclocal.m4 changes.
735
736Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
737
738 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
739
740Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
741
742 * configure: Regenerated to track ../common/aclocal.m4 changes.
743 * config.in: Regenerated to track ../common/aclocal.m4 changes.
744
745Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
746
747 * configure: Regenerated to track ../common/aclocal.m4 changes.
748
749Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
750
751 * interp.c (Max, Min): Comment out functions. Not yet used.
752
753Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
754
755 * configure: Regenerated to track ../common/aclocal.m4 changes.
756
757Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
758
759 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
760 configurable settings for stand-alone simulator.
761
762 * configure.in: Added X11 search, just in case.
763
764 * configure: Regenerated.
765
766Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
767
768 * interp.c (sim_write, sim_read, load_memory, store_memory):
769 Replace sim_core_*_map with read_map, write_map, exec_map resp.
770
771Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
772
773 * sim-main.h (GETFCC): Return an unsigned value.
774
775Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * mips.igen (DIV): Fix check for -1 / MIN_INT.
778 (DADD): Result destination is RD not RT.
779
780Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
781
782 * sim-main.h (HIACCESS, LOACCESS): Always define.
783
784 * mdmx.igen (Maxi, Mini): Rename Max, Min.
785
786 * interp.c (sim_info): Delete.
787
788Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
789
790 * interp.c (DECLARE_OPTION_HANDLER): Use it.
791 (mips_option_handler): New argument `cpu'.
792 (sim_open): Update call to sim_add_option_table.
793
794Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
795
796 * mips.igen (CxC1): Add tracing.
797
798Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
799
800 * sim-main.h (Max, Min): Declare.
801
802 * interp.c (Max, Min): New functions.
803
804 * mips.igen (BC1): Add tracing.
805
806Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
807
808 * interp.c Added memory map for stack in vr4100
809
810Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
811
812 * interp.c (load_memory): Add missing "break"'s.
813
814Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
815
816 * interp.c (sim_store_register, sim_fetch_register): Pass in
817 length parameter. Return -1.
818
819Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
820
821 * interp.c: Added hardware init hook, fixed warnings.
822
823Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
824
825 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
826
827Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
828
829 * interp.c (ifetch16): New function.
830
831 * sim-main.h (IMEM32): Rename IMEM.
832 (IMEM16_IMMED): Define.
833 (IMEM16): Define.
834 (DELAY_SLOT): Update.
835
836 * m16run.c (sim_engine_run): New file.
837
838 * m16.igen: All instructions except LB.
839 (LB): Call do_load_byte.
840 * mips.igen (do_load_byte): New function.
841 (LB): Call do_load_byte.
842
843 * mips.igen: Move spec for insn bit size and high bit from here.
844 * Makefile.in (tmp-igen, tmp-m16): To here.
845
846 * m16.dc: New file, decode mips16 instructions.
847
848 * Makefile.in (SIM_NO_ALL): Define.
849 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
850
851Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
852
853 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
854 point unit to 32 bit registers.
855 * configure: Re-generate.
856
857Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
858
859 * configure.in (sim_use_gen): Make IGEN the default simulator
860 generator for generic 32 and 64 bit mips targets.
861 * configure: Re-generate.
862
863Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
864
865 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
866 bitsize.
867
868 * interp.c (sim_fetch_register, sim_store_register): Read/write
869 FGR from correct location.
870 (sim_open): Set size of FGR's according to
871 WITH_TARGET_FLOATING_POINT_BITSIZE.
872
873 * sim-main.h (FGR): Store floating point registers in a separate
874 array.
875
876Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
877
878 * configure: Regenerated to track ../common/aclocal.m4 changes.
879
880Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
881
882 * interp.c (ColdReset): Call PENDING_INVALIDATE.
883
884 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
885
886 * interp.c (pending_tick): New function. Deliver pending writes.
887
888 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
889 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
890 it can handle mixed sized quantites and single bits.
891
892Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
893
894 * interp.c (oengine.h): Do not include when building with IGEN.
895 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
896 (sim_info): Ditto for PROCESSOR_64BIT.
897 (sim_monitor): Replace ut_reg with unsigned_word.
898 (*): Ditto for t_reg.
899 (LOADDRMASK): Define.
900 (sim_open): Remove defunct check that host FP is IEEE compliant,
901 using software to emulate floating point.
902 (value_fpr, ...): Always compile, was conditional on HASFPU.
903
904Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
905
906 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
907 size.
908
909 * interp.c (SD, CPU): Define.
910 (mips_option_handler): Set flags in each CPU.
911 (interrupt_event): Assume CPU 0 is the one being iterrupted.
912 (sim_close): Do not clear STATE, deleted anyway.
913 (sim_write, sim_read): Assume CPU zero's vm should be used for
914 data transfers.
915 (sim_create_inferior): Set the PC for all processors.
916 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
917 argument.
918 (mips16_entry): Pass correct nr of args to store_word, load_word.
919 (ColdReset): Cold reset all cpu's.
920 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
921 (sim_monitor, load_memory, store_memory, signal_exception): Use
922 `CPU' instead of STATE_CPU.
923
924
925 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
926 SD or CPU_.
927
928 * sim-main.h (signal_exception): Add sim_cpu arg.
929 (SignalException*): Pass both SD and CPU to signal_exception.
930 * interp.c (signal_exception): Update.
931
932 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
933 Ditto
934 (sync_operation, prefetch, cache_op, store_memory, load_memory,
935 address_translation): Ditto
936 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
937
938Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
939
940 * configure: Regenerated to track ../common/aclocal.m4 changes.
941
942Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
943
944 * interp.c (sim_engine_run): Add `nr_cpus' argument.
945
946 * mips.igen (model): Map processor names onto BFD name.
947
948 * sim-main.h (CPU_CIA): Delete.
949 (SET_CIA, GET_CIA): Define
950
951Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
952
953 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
954 regiser.
955
956 * configure.in (default_endian): Configure a big-endian simulator
957 by default.
958 * configure: Re-generate.
959
960Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
961
962 * configure: Regenerated to track ../common/aclocal.m4 changes.
963
964Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
965
966 * interp.c (sim_monitor): Handle Densan monitor outbyte
967 and inbyte functions.
968
9691997-12-29 Felix Lee <flee@cygnus.com>
970
971 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
972
973Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
974
975 * Makefile.in (tmp-igen): Arrange for $zero to always be
976 reset to zero after every instruction.
977
978Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
979
980 * configure: Regenerated to track ../common/aclocal.m4 changes.
981 * config.in: Ditto.
982
983Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
984
985 * mips.igen (MSUB): Fix to work like MADD.
986 * gencode.c (MSUB): Similarly.
987
988Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
989
990 * configure: Regenerated to track ../common/aclocal.m4 changes.
991
992Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
993
994 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
995
996Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
997
998 * sim-main.h (sim-fpu.h): Include.
999
1000 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1001 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1002 using host independant sim_fpu module.
1003
1004Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1005
1006 * interp.c (signal_exception): Report internal errors with SIGABRT
1007 not SIGQUIT.
1008
1009 * sim-main.h (C0_CONFIG): New register.
1010 (signal.h): No longer include.
1011
1012 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1013
1014Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1015
1016 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1017
1018Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1019
1020 * mips.igen: Tag vr5000 instructions.
1021 (ANDI): Was missing mipsIV model, fix assembler syntax.
1022 (do_c_cond_fmt): New function.
1023 (C.cond.fmt): Handle mips I-III which do not support CC field
1024 separatly.
1025 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1026 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1027 in IV3.2 spec.
1028 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1029 vr5000 which saves LO in a GPR separatly.
1030
1031 * configure.in (enable-sim-igen): For vr5000, select vr5000
1032 specific instructions.
1033 * configure: Re-generate.
1034
1035Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1036
1037 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1038
1039 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1040 fmt_uninterpreted_64 bit cases to switch. Convert to
1041 fmt_formatted,
1042
1043 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1044
1045 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1046 as specified in IV3.2 spec.
1047 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1048
1049Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1050
1051 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1052 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1053 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1054 PENDING_FILL versions of instructions. Simplify.
1055 (X): New function.
1056 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1057 instructions.
1058 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1059 a signed value.
1060 (MTHI, MFHI): Disable code checking HI-LO.
1061
1062 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1063 global.
1064 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1065
1066Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1067
1068 * gencode.c (build_mips16_operands): Replace IPC with cia.
1069
1070 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1071 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1072 IPC to `cia'.
1073 (UndefinedResult): Replace function with macro/function
1074 combination.
1075 (sim_engine_run): Don't save PC in IPC.
1076
1077 * sim-main.h (IPC): Delete.
1078
1079
1080 * interp.c (signal_exception, store_word, load_word,
1081 address_translation, load_memory, store_memory, cache_op,
1082 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1083 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1084 current instruction address - cia - argument.
1085 (sim_read, sim_write): Call address_translation directly.
1086 (sim_engine_run): Rename variable vaddr to cia.
1087 (signal_exception): Pass cia to sim_monitor
1088
1089 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1090 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1091 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1092
1093 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1094 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1095 SIM_ASSERT.
1096
1097 * interp.c (signal_exception): Pass restart address to
1098 sim_engine_restart.
1099
1100 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1101 idecode.o): Add dependency.
1102
1103 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1104 Delete definitions
1105 (DELAY_SLOT): Update NIA not PC with branch address.
1106 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1107
1108 * mips.igen: Use CIA not PC in branch calculations.
1109 (illegal): Call SignalException.
1110 (BEQ, ADDIU): Fix assembler.
1111
1112Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * m16.igen (JALX): Was missing.
1115
1116 * configure.in (enable-sim-igen): New configuration option.
1117 * configure: Re-generate.
1118
1119 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1120
1121 * interp.c (load_memory, store_memory): Delete parameter RAW.
1122 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1123 bypassing {load,store}_memory.
1124
1125 * sim-main.h (ByteSwapMem): Delete definition.
1126
1127 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1128
1129 * interp.c (sim_do_command, sim_commands): Delete mips specific
1130 commands. Handled by module sim-options.
1131
1132 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1133 (WITH_MODULO_MEMORY): Define.
1134
1135 * interp.c (sim_info): Delete code printing memory size.
1136
1137 * interp.c (mips_size): Nee sim_size, delete function.
1138 (power2): Delete.
1139 (monitor, monitor_base, monitor_size): Delete global variables.
1140 (sim_open, sim_close): Delete code creating monitor and other
1141 memory regions. Use sim-memopts module, via sim_do_commandf, to
1142 manage memory regions.
1143 (load_memory, store_memory): Use sim-core for memory model.
1144
1145 * interp.c (address_translation): Delete all memory map code
1146 except line forcing 32 bit addresses.
1147
1148Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1149
1150 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1151 trace options.
1152
1153 * interp.c (logfh, logfile): Delete globals.
1154 (sim_open, sim_close): Delete code opening & closing log file.
1155 (mips_option_handler): Delete -l and -n options.
1156 (OPTION mips_options): Ditto.
1157
1158 * interp.c (OPTION mips_options): Rename option trace to dinero.
1159 (mips_option_handler): Update.
1160
1161Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1162
1163 * interp.c (fetch_str): New function.
1164 (sim_monitor): Rewrite using sim_read & sim_write.
1165 (sim_open): Check magic number.
1166 (sim_open): Write monitor vectors into memory using sim_write.
1167 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1168 (sim_read, sim_write): Simplify - transfer data one byte at a
1169 time.
1170 (load_memory, store_memory): Clarify meaning of parameter RAW.
1171
1172 * sim-main.h (isHOST): Defete definition.
1173 (isTARGET): Mark as depreciated.
1174 (address_translation): Delete parameter HOST.
1175
1176 * interp.c (address_translation): Delete parameter HOST.
1177
1178Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1179
1180 * mips.igen:
1181
1182 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1183 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1184
1185Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1186
1187 * mips.igen: Add model filter field to records.
1188
1189Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1190
1191 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1192
1193 interp.c (sim_engine_run): Do not compile function sim_engine_run
1194 when WITH_IGEN == 1.
1195
1196 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1197 target architecture.
1198
1199 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1200 igen. Replace with configuration variables sim_igen_flags /
1201 sim_m16_flags.
1202
1203 * m16.igen: New file. Copy mips16 insns here.
1204 * mips.igen: From here.
1205
1206Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1207
1208 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1209 to top.
1210 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1211
1212Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1213
1214 * gencode.c (build_instruction): Follow sim_write's lead in using
1215 BigEndianMem instead of !ByteSwapMem.
1216
1217Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1218
1219 * configure.in (sim_gen): Dependent on target, select type of
1220 generator. Always select old style generator.
1221
1222 configure: Re-generate.
1223
1224 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1225 targets.
1226 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1227 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1228 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1229 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1230 SIM_@sim_gen@_*, set by autoconf.
1231
1232Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1233
1234 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1235
1236 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1237 CURRENT_FLOATING_POINT instead.
1238
1239 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1240 (address_translation): Raise exception InstructionFetch when
1241 translation fails and isINSTRUCTION.
1242
1243 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1244 sim_engine_run): Change type of of vaddr and paddr to
1245 address_word.
1246 (address_translation, prefetch, load_memory, store_memory,
1247 cache_op): Change type of vAddr and pAddr to address_word.
1248
1249 * gencode.c (build_instruction): Change type of vaddr and paddr to
1250 address_word.
1251
1252Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1253
1254 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1255 macro to obtain result of ALU op.
1256
1257Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * interp.c (sim_info): Call profile_print.
1260
1261Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1262
1263 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1264
1265 * sim-main.h (WITH_PROFILE): Do not define, defined in
1266 common/sim-config.h. Use sim-profile module.
1267 (simPROFILE): Delete defintion.
1268
1269 * interp.c (PROFILE): Delete definition.
1270 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1271 (sim_close): Delete code writing profile histogram.
1272 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1273 Delete.
1274 (sim_engine_run): Delete code profiling the PC.
1275
1276Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1277
1278 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1279
1280 * interp.c (sim_monitor): Make register pointers of type
1281 unsigned_word*.
1282
1283 * sim-main.h: Make registers of type unsigned_word not
1284 signed_word.
1285
1286Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1287
1288 * interp.c (sync_operation): Rename from SyncOperation, make
1289 global, add SD argument.
1290 (prefetch): Rename from Prefetch, make global, add SD argument.
1291 (decode_coproc): Make global.
1292
1293 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1294
1295 * gencode.c (build_instruction): Generate DecodeCoproc not
1296 decode_coproc calls.
1297
1298 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1299 (SizeFGR): Move to sim-main.h
1300 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1301 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1302 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1303 sim-main.h.
1304 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1305 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1306 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1307 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1308 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1309 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1310
1311 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1312 exception.
1313 (sim-alu.h): Include.
1314 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1315 (sim_cia): Typedef to instruction_address.
1316
1317Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1318
1319 * Makefile.in (interp.o): Rename generated file engine.c to
1320 oengine.c.
1321
1322 * interp.c: Update.
1323
1324Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1325
1326 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1327
1328Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329
1330 * gencode.c (build_instruction): For "FPSQRT", output correct
1331 number of arguments to Recip.
1332
1333Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334
1335 * Makefile.in (interp.o): Depends on sim-main.h
1336
1337 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1338
1339 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1340 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1341 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1342 STATE, DSSTATE): Define
1343 (GPR, FGRIDX, ..): Define.
1344
1345 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1346 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1347 (GPR, FGRIDX, ...): Delete macros.
1348
1349 * interp.c: Update names to match defines from sim-main.h
1350
1351Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1352
1353 * interp.c (sim_monitor): Add SD argument.
1354 (sim_warning): Delete. Replace calls with calls to
1355 sim_io_eprintf.
1356 (sim_error): Delete. Replace calls with sim_io_error.
1357 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1358 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1359 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1360 argument.
1361 (mips_size): Rename from sim_size. Add SD argument.
1362
1363 * interp.c (simulator): Delete global variable.
1364 (callback): Delete global variable.
1365 (mips_option_handler, sim_open, sim_write, sim_read,
1366 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1367 sim_size,sim_monitor): Use sim_io_* not callback->*.
1368 (sim_open): ZALLOC simulator struct.
1369 (PROFILE): Do not define.
1370
1371Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1372
1373 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1374 support.h with corresponding code.
1375
1376 * sim-main.h (word64, uword64), support.h: Move definition to
1377 sim-main.h.
1378 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1379
1380 * support.h: Delete
1381 * Makefile.in: Update dependencies
1382 * interp.c: Do not include.
1383
1384Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * interp.c (address_translation, load_memory, store_memory,
1387 cache_op): Rename to from AddressTranslation et.al., make global,
1388 add SD argument
1389
1390 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1391 CacheOp): Define.
1392
1393 * interp.c (SignalException): Rename to signal_exception, make
1394 global.
1395
1396 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1397
1398 * sim-main.h (SignalException, SignalExceptionInterrupt,
1399 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1400 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1401 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1402 Define.
1403
1404 * interp.c, support.h: Use.
1405
1406Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1407
1408 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1409 to value_fpr / store_fpr. Add SD argument.
1410 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1411 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1412
1413 * sim-main.h (ValueFPR, StoreFPR): Define.
1414
1415Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1416
1417 * interp.c (sim_engine_run): Check consistency between configure
1418 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1419 and HASFPU.
1420
1421 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1422 (mips_fpu): Configure WITH_FLOATING_POINT.
1423 (mips_endian): Configure WITH_TARGET_ENDIAN.
1424 * configure: Update.
1425
1426Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * configure: Regenerated to track ../common/aclocal.m4 changes.
1429
1430Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1431
1432 * configure: Regenerated.
1433
1434Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1435
1436 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1437
1438Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * gencode.c (print_igen_insn_models): Assume certain architectures
1441 include all mips* instructions.
1442 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1443 instruction.
1444
1445 * Makefile.in (tmp.igen): Add target. Generate igen input from
1446 gencode file.
1447
1448 * gencode.c (FEATURE_IGEN): Define.
1449 (main): Add --igen option. Generate output in igen format.
1450 (process_instructions): Format output according to igen option.
1451 (print_igen_insn_format): New function.
1452 (print_igen_insn_models): New function.
1453 (process_instructions): Only issue warnings and ignore
1454 instructions when no FEATURE_IGEN.
1455
1456Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1457
1458 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1459 MIPS targets.
1460
1461Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1462
1463 * configure: Regenerated to track ../common/aclocal.m4 changes.
1464
1465Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1466
1467 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1468 SIM_RESERVED_BITS): Delete, moved to common.
1469 (SIM_EXTRA_CFLAGS): Update.
1470
1471Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * configure.in: Configure non-strict memory alignment.
1474 * configure: Regenerated to track ../common/aclocal.m4 changes.
1475
1476Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * configure: Regenerated to track ../common/aclocal.m4 changes.
1479
1480Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1481
1482 * gencode.c (SDBBP,DERET): Added (3900) insns.
1483 (RFE): Turn on for 3900.
1484 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1485 (dsstate): Made global.
1486 (SUBTARGET_R3900): Added.
1487 (CANCELDELAYSLOT): New.
1488 (SignalException): Ignore SystemCall rather than ignore and
1489 terminate. Add DebugBreakPoint handling.
1490 (decode_coproc): New insns RFE, DERET; and new registers Debug
1491 and DEPC protected by SUBTARGET_R3900.
1492 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1493 bits explicitly.
1494 * Makefile.in,configure.in: Add mips subtarget option.
1495 * configure: Update.
1496
1497Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1498
1499 * gencode.c: Add r3900 (tx39).
1500
1501
1502Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1503
1504 * gencode.c (build_instruction): Don't need to subtract 4 for
1505 JALR, just 2.
1506
1507Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1508
1509 * interp.c: Correct some HASFPU problems.
1510
1511Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * configure: Regenerated to track ../common/aclocal.m4 changes.
1514
1515Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * interp.c (mips_options): Fix samples option short form, should
1518 be `x'.
1519
1520Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * interp.c (sim_info): Enable info code. Was just returning.
1523
1524Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1527 MFC0.
1528
1529Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530
1531 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1532 constants.
1533 (build_instruction): Ditto for LL.
1534
1535Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1536
1537 * configure: Regenerated to track ../common/aclocal.m4 changes.
1538
1539Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * configure: Regenerated to track ../common/aclocal.m4 changes.
1542 * config.in: Ditto.
1543
1544Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * interp.c (sim_open): Add call to sim_analyze_program, update
1547 call to sim_config.
1548
1549Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1550
1551 * interp.c (sim_kill): Delete.
1552 (sim_create_inferior): Add ABFD argument. Set PC from same.
1553 (sim_load): Move code initializing trap handlers from here.
1554 (sim_open): To here.
1555 (sim_load): Delete, use sim-hload.c.
1556
1557 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1558
1559Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560
1561 * configure: Regenerated to track ../common/aclocal.m4 changes.
1562 * config.in: Ditto.
1563
1564Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1565
1566 * interp.c (sim_open): Add ABFD argument.
1567 (sim_load): Move call to sim_config from here.
1568 (sim_open): To here. Check return status.
1569
1570Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1571
1572 * gencode.c (build_instruction): Two arg MADD should
1573 not assign result to $0.
1574
1575Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1576
1577 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1578 * sim/mips/configure.in: Regenerate.
1579
1580Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1581
1582 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1583 signed8, unsigned8 et.al. types.
1584
1585 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1586 hosts when selecting subreg.
1587
1588Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1589
1590 * interp.c (sim_engine_run): Reset the ZERO register to zero
1591 regardless of FEATURE_WARN_ZERO.
1592 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1593
1594Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595
1596 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1597 (SignalException): For BreakPoints ignore any mode bits and just
1598 save the PC.
1599 (SignalException): Always set the CAUSE register.
1600
1601Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1602
1603 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1604 exception has been taken.
1605
1606 * interp.c: Implement the ERET and mt/f sr instructions.
1607
1608Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1609
1610 * interp.c (SignalException): Don't bother restarting an
1611 interrupt.
1612
1613Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * interp.c (SignalException): Really take an interrupt.
1616 (interrupt_event): Only deliver interrupts when enabled.
1617
1618Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1619
1620 * interp.c (sim_info): Only print info when verbose.
1621 (sim_info) Use sim_io_printf for output.
1622
1623Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1624
1625 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1626 mips architectures.
1627
1628Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 * interp.c (sim_do_command): Check for common commands if a
1631 simulator specific command fails.
1632
1633Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1634
1635 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1636 and simBE when DEBUG is defined.
1637
1638Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1639
1640 * interp.c (interrupt_event): New function. Pass exception event
1641 onto exception handler.
1642
1643 * configure.in: Check for stdlib.h.
1644 * configure: Regenerate.
1645
1646 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1647 variable declaration.
1648 (build_instruction): Initialize memval1.
1649 (build_instruction): Add UNUSED attribute to byte, bigend,
1650 reverse.
1651 (build_operands): Ditto.
1652
1653 * interp.c: Fix GCC warnings.
1654 (sim_get_quit_code): Delete.
1655
1656 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1657 * Makefile.in: Ditto.
1658 * configure: Re-generate.
1659
1660 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1661
1662Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663
1664 * interp.c (mips_option_handler): New function parse argumes using
1665 sim-options.
1666 (myname): Replace with STATE_MY_NAME.
1667 (sim_open): Delete check for host endianness - performed by
1668 sim_config.
1669 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1670 (sim_open): Move much of the initialization from here.
1671 (sim_load): To here. After the image has been loaded and
1672 endianness set.
1673 (sim_open): Move ColdReset from here.
1674 (sim_create_inferior): To here.
1675 (sim_open): Make FP check less dependant on host endianness.
1676
1677 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1678 run.
1679 * interp.c (sim_set_callbacks): Delete.
1680
1681 * interp.c (membank, membank_base, membank_size): Replace with
1682 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1683 (sim_open): Remove call to callback->init. gdb/run do this.
1684
1685 * interp.c: Update
1686
1687 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1688
1689 * interp.c (big_endian_p): Delete, replaced by
1690 current_target_byte_order.
1691
1692Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1693
1694 * interp.c (host_read_long, host_read_word, host_swap_word,
1695 host_swap_long): Delete. Using common sim-endian.
1696 (sim_fetch_register, sim_store_register): Use H2T.
1697 (pipeline_ticks): Delete. Handled by sim-events.
1698 (sim_info): Update.
1699 (sim_engine_run): Update.
1700
1701Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702
1703 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1704 reason from here.
1705 (SignalException): To here. Signal using sim_engine_halt.
1706 (sim_stop_reason): Delete, moved to common.
1707
1708Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1709
1710 * interp.c (sim_open): Add callback argument.
1711 (sim_set_callbacks): Delete SIM_DESC argument.
1712 (sim_size): Ditto.
1713
1714Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715
1716 * Makefile.in (SIM_OBJS): Add common modules.
1717
1718 * interp.c (sim_set_callbacks): Also set SD callback.
1719 (set_endianness, xfer_*, swap_*): Delete.
1720 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1721 Change to functions using sim-endian macros.
1722 (control_c, sim_stop): Delete, use common version.
1723 (simulate): Convert into.
1724 (sim_engine_run): This function.
1725 (sim_resume): Delete.
1726
1727 * interp.c (simulation): New variable - the simulator object.
1728 (sim_kind): Delete global - merged into simulation.
1729 (sim_load): Cleanup. Move PC assignment from here.
1730 (sim_create_inferior): To here.
1731
1732 * sim-main.h: New file.
1733 * interp.c (sim-main.h): Include.
1734
1735Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1736
1737 * configure: Regenerated to track ../common/aclocal.m4 changes.
1738
1739Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1740
1741 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1742
1743Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1744
1745 * gencode.c (build_instruction): DIV instructions: check
1746 for division by zero and integer overflow before using
1747 host's division operation.
1748
1749Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1750
1751 * Makefile.in (SIM_OBJS): Add sim-load.o.
1752 * interp.c: #include bfd.h.
1753 (target_byte_order): Delete.
1754 (sim_kind, myname, big_endian_p): New static locals.
1755 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1756 after argument parsing. Recognize -E arg, set endianness accordingly.
1757 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1758 load file into simulator. Set PC from bfd.
1759 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1760 (set_endianness): Use big_endian_p instead of target_byte_order.
1761
1762Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1763
1764 * interp.c (sim_size): Delete prototype - conflicts with
1765 definition in remote-sim.h. Correct definition.
1766
1767Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1768
1769 * configure: Regenerated to track ../common/aclocal.m4 changes.
1770 * config.in: Ditto.
1771
1772Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1773
1774 * interp.c (sim_open): New arg `kind'.
1775
1776 * configure: Regenerated to track ../common/aclocal.m4 changes.
1777
1778Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1779
1780 * configure: Regenerated to track ../common/aclocal.m4 changes.
1781
1782Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1783
1784 * interp.c (sim_open): Set optind to 0 before calling getopt.
1785
1786Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1787
1788 * configure: Regenerated to track ../common/aclocal.m4 changes.
1789
1790Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1791
1792 * interp.c : Replace uses of pr_addr with pr_uword64
1793 where the bit length is always 64 independent of SIM_ADDR.
1794 (pr_uword64) : added.
1795
1796Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1797
1798 * configure: Re-generate.
1799
1800Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1801
1802 * configure: Regenerate to track ../common/aclocal.m4 changes.
1803
1804Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1805
1806 * interp.c (sim_open): New SIM_DESC result. Argument is now
1807 in argv form.
1808 (other sim_*): New SIM_DESC argument.
1809
1810Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1811
1812 * interp.c: Fix printing of addresses for non-64-bit targets.
1813 (pr_addr): Add function to print address based on size.
1814
1815Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1816
1817 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1818
1819Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1820
1821 * gencode.c (build_mips16_operands): Correct computation of base
1822 address for extended PC relative instruction.
1823
1824Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1825
1826 * interp.c (mips16_entry): Add support for floating point cases.
1827 (SignalException): Pass floating point cases to mips16_entry.
1828 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1829 registers.
1830 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1831 or fmt_word.
1832 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1833 and then set the state to fmt_uninterpreted.
1834 (COP_SW): Temporarily set the state to fmt_word while calling
1835 ValueFPR.
1836
1837Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1838
1839 * gencode.c (build_instruction): The high order may be set in the
1840 comparison flags at any ISA level, not just ISA 4.
1841
1842Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1843
1844 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1845 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1846 * configure.in: sinclude ../common/aclocal.m4.
1847 * configure: Regenerated.
1848
1849Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1850
1851 * configure: Rebuild after change to aclocal.m4.
1852
1853Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1854
1855 * configure configure.in Makefile.in: Update to new configure
1856 scheme which is more compatible with WinGDB builds.
1857 * configure.in: Improve comment on how to run autoconf.
1858 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1859 * Makefile.in: Use autoconf substitution to install common
1860 makefile fragment.
1861
1862Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1863
1864 * gencode.c (build_instruction): Use BigEndianCPU instead of
1865 ByteSwapMem.
1866
1867Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1868
1869 * interp.c (sim_monitor): Make output to stdout visible in
1870 wingdb's I/O log window.
1871
1872Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1873
1874 * support.h: Undo previous change to SIGTRAP
1875 and SIGQUIT values.
1876
1877Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1878
1879 * interp.c (store_word, load_word): New static functions.
1880 (mips16_entry): New static function.
1881 (SignalException): Look for mips16 entry and exit instructions.
1882 (simulate): Use the correct index when setting fpr_state after
1883 doing a pending move.
1884
1885Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1886
1887 * interp.c: Fix byte-swapping code throughout to work on
1888 both little- and big-endian hosts.
1889
1890Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1891
1892 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1893 with gdb/config/i386/xm-windows.h.
1894
1895Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1896
1897 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1898 that messes up arithmetic shifts.
1899
1900Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1901
1902 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1903 SIGTRAP and SIGQUIT for _WIN32.
1904
1905Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1906
1907 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1908 force a 64 bit multiplication.
1909 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1910 destination register is 0, since that is the default mips16 nop
1911 instruction.
1912
1913Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1914
1915 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1916 (build_endian_shift): Don't check proc64.
1917 (build_instruction): Always set memval to uword64. Cast op2 to
1918 uword64 when shifting it left in memory instructions. Always use
1919 the same code for stores--don't special case proc64.
1920
1921 * gencode.c (build_mips16_operands): Fix base PC value for PC
1922 relative operands.
1923 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1924 jal instruction.
1925 * interp.c (simJALDELAYSLOT): Define.
1926 (JALDELAYSLOT): Define.
1927 (INDELAYSLOT, INJALDELAYSLOT): Define.
1928 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1929
1930Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1931
1932 * interp.c (sim_open): add flush_cache as a PMON routine
1933 (sim_monitor): handle flush_cache by ignoring it
1934
1935Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1936
1937 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1938 BigEndianMem.
1939 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1940 (BigEndianMem): Rename to ByteSwapMem and change sense.
1941 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1942 BigEndianMem references to !ByteSwapMem.
1943 (set_endianness): New function, with prototype.
1944 (sim_open): Call set_endianness.
1945 (sim_info): Use simBE instead of BigEndianMem.
1946 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1947 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1948 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1949 ifdefs, keeping the prototype declaration.
1950 (swap_word): Rewrite correctly.
1951 (ColdReset): Delete references to CONFIG. Delete endianness related
1952 code; moved to set_endianness.
1953
1954Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1955
1956 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1957 * interp.c (CHECKHILO): Define away.
1958 (simSIGINT): New macro.
1959 (membank_size): Increase from 1MB to 2MB.
1960 (control_c): New function.
1961 (sim_resume): Rename parameter signal to signal_number. Add local
1962 variable prev. Call signal before and after simulate.
1963 (sim_stop_reason): Add simSIGINT support.
1964 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1965 functions always.
1966 (sim_warning): Delete call to SignalException. Do call printf_filtered
1967 if logfh is NULL.
1968 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1969 a call to sim_warning.
1970
1971Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1972
1973 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1974 16 bit instructions.
1975
1976Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1977
1978 Add support for mips16 (16 bit MIPS implementation):
1979 * gencode.c (inst_type): Add mips16 instruction encoding types.
1980 (GETDATASIZEINSN): Define.
1981 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1982 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1983 mtlo.
1984 (MIPS16_DECODE): New table, for mips16 instructions.
1985 (bitmap_val): New static function.
1986 (struct mips16_op): Define.
1987 (mips16_op_table): New table, for mips16 operands.
1988 (build_mips16_operands): New static function.
1989 (process_instructions): If PC is odd, decode a mips16
1990 instruction. Break out instruction handling into new
1991 build_instruction function.
1992 (build_instruction): New static function, broken out of
1993 process_instructions. Check modifiers rather than flags for SHIFT
1994 bit count and m[ft]{hi,lo} direction.
1995 (usage): Pass program name to fprintf.
1996 (main): Remove unused variable this_option_optind. Change
1997 ``*loptarg++'' to ``loptarg++''.
1998 (my_strtoul): Parenthesize && within ||.
1999 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2000 (simulate): If PC is odd, fetch a 16 bit instruction, and
2001 increment PC by 2 rather than 4.
2002 * configure.in: Add case for mips16*-*-*.
2003 * configure: Rebuild.
2004
2005Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2006
2007 * interp.c: Allow -t to enable tracing in standalone simulator.
2008 Fix garbage output in trace file and error messages.
2009
2010Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2011
2012 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2013 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2014 * configure.in: Simplify using macros in ../common/aclocal.m4.
2015 * configure: Regenerated.
2016 * tconfig.in: New file.
2017
2018Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2019
2020 * interp.c: Fix bugs in 64-bit port.
2021 Use ansi function declarations for msvc compiler.
2022 Initialize and test file pointer in trace code.
2023 Prevent duplicate definition of LAST_EMED_REGNUM.
2024
2025Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2026
2027 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2028
2029Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2030
2031 * interp.c (SignalException): Check for explicit terminating
2032 breakpoint value.
2033 * gencode.c: Pass instruction value through SignalException()
2034 calls for Trap, Breakpoint and Syscall.
2035
2036Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2037
2038 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2039 only used on those hosts that provide it.
2040 * configure.in: Add sqrt() to list of functions to be checked for.
2041 * config.in: Re-generated.
2042 * configure: Re-generated.
2043
2044Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2045
2046 * gencode.c (process_instructions): Call build_endian_shift when
2047 expanding STORE RIGHT, to fix swr.
2048 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2049 clear the high bits.
2050 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2051 Fix float to int conversions to produce signed values.
2052
2053Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2054
2055 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2056 (process_instructions): Correct handling of nor instruction.
2057 Correct shift count for 32 bit shift instructions. Correct sign
2058 extension for arithmetic shifts to not shift the number of bits in
2059 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2060 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2061 Fix madd.
2062 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2063 It's OK to have a mult follow a mult. What's not OK is to have a
2064 mult follow an mfhi.
2065 (Convert): Comment out incorrect rounding code.
2066
2067Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2068
2069 * interp.c (sim_monitor): Improved monitor printf
2070 simulation. Tidied up simulator warnings, and added "--log" option
2071 for directing warning message output.
2072 * gencode.c: Use sim_warning() rather than WARNING macro.
2073
2074Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2075
2076 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2077 getopt1.o, rather than on gencode.c. Link objects together.
2078 Don't link against -liberty.
2079 (gencode.o, getopt.o, getopt1.o): New targets.
2080 * gencode.c: Include <ctype.h> and "ansidecl.h".
2081 (AND): Undefine after including "ansidecl.h".
2082 (ULONG_MAX): Define if not defined.
2083 (OP_*): Don't define macros; now defined in opcode/mips.h.
2084 (main): Call my_strtoul rather than strtoul.
2085 (my_strtoul): New static function.
2086
2087Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2088
2089 * gencode.c (process_instructions): Generate word64 and uword64
2090 instead of `long long' and `unsigned long long' data types.
2091 * interp.c: #include sysdep.h to get signals, and define default
2092 for SIGBUS.
2093 * (Convert): Work around for Visual-C++ compiler bug with type
2094 conversion.
2095 * support.h: Make things compile under Visual-C++ by using
2096 __int64 instead of `long long'. Change many refs to long long
2097 into word64/uword64 typedefs.
2098
2099Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2100
2101 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2102 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2103 (docdir): Removed.
2104 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2105 (AC_PROG_INSTALL): Added.
2106 (AC_PROG_CC): Moved to before configure.host call.
2107 * configure: Rebuilt.
2108
2109Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2110
2111 * configure.in: Define @SIMCONF@ depending on mips target.
2112 * configure: Rebuild.
2113 * Makefile.in (run): Add @SIMCONF@ to control simulator
2114 construction.
2115 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2116 * interp.c: Remove some debugging, provide more detailed error
2117 messages, update memory accesses to use LOADDRMASK.
2118
2119Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2120
2121 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2122 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2123 stamp-h.
2124 * configure: Rebuild.
2125 * config.in: New file, generated by autoheader.
2126 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2127 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2128 HAVE_ANINT and HAVE_AINT, as appropriate.
2129 * Makefile.in (run): Use @LIBS@ rather than -lm.
2130 (interp.o): Depend upon config.h.
2131 (Makefile): Just rebuild Makefile.
2132 (clean): Remove stamp-h.
2133 (mostlyclean): Make the same as clean, not as distclean.
2134 (config.h, stamp-h): New targets.
2135
2136Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2137
2138 * interp.c (ColdReset): Fix boolean test. Make all simulator
2139 globals static.
2140
2141Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2142
2143 * interp.c (xfer_direct_word, xfer_direct_long,
2144 swap_direct_word, swap_direct_long, xfer_big_word,
2145 xfer_big_long, xfer_little_word, xfer_little_long,
2146 swap_word,swap_long): Added.
2147 * interp.c (ColdReset): Provide function indirection to
2148 host<->simulated_target transfer routines.
2149 * interp.c (sim_store_register, sim_fetch_register): Updated to
2150 make use of indirected transfer routines.
2151
2152Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2153
2154 * gencode.c (process_instructions): Ensure FP ABS instruction
2155 recognised.
2156 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2157 system call support.
2158
2159Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2160
2161 * interp.c (sim_do_command): Complain if callback structure not
2162 initialised.
2163
2164Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2165
2166 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2167 support for Sun hosts.
2168 * Makefile.in (gencode): Ensure the host compiler and libraries
2169 used for cross-hosted build.
2170
2171Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2172
2173 * interp.c, gencode.c: Some more (TODO) tidying.
2174
2175Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2176
2177 * gencode.c, interp.c: Replaced explicit long long references with
2178 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2179 * support.h (SET64LO, SET64HI): Macros added.
2180
2181Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2182
2183 * configure: Regenerate with autoconf 2.7.
2184
2185Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2186
2187 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2188 * support.h: Remove superfluous "1" from #if.
2189 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2190
2191Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2192
2193 * interp.c (StoreFPR): Control UndefinedResult() call on
2194 WARN_RESULT manifest.
2195
2196Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2197
2198 * gencode.c: Tidied instruction decoding, and added FP instruction
2199 support.
2200
2201 * interp.c: Added dineroIII, and BSD profiling support. Also
2202 run-time FP handling.
2203
2204Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2205
2206 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2207 gencode.c, interp.c, support.h: created.
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