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target/sparc: Drop ifdef around get_asi and friends
[thirdparty/qemu.git] / target / sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
5650b549 10 version 2.1 of the License, or (at your option) any later version.
7a3f1944
FB		 11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
dcb32f1d 27#include "tcg/tcg-op.h"
7a3f1944 28
2ef6175a 29#include "exec/helper-gen.h"
a7812ae4 30
c5e6ccdf 31#include "exec/translator.h"
508127e2 32#include "exec/log.h"
0cc1f4bf 33#include "asi.h"
a7e30d84 34
d53106c9
RH		 35#define HELPER_H "helper.h"
36#include "exec/helper-info.c.inc"
37#undef HELPER_H
a7e30d84 38
668bb9b7
RH		 39#ifdef TARGET_SPARC64
40# define gen_helper_rdpsr(D, E) qemu_build_not_reached()
86b82fe0 41# define gen_helper_rett(E) qemu_build_not_reached()
0faef01b 42# define gen_helper_power_down(E) qemu_build_not_reached()
25524734 43# define gen_helper_wrpsr(E, S) qemu_build_not_reached()
668bb9b7 44#else
0faef01b 45# define gen_helper_clear_softint(E, S) qemu_build_not_reached()
8f75b8a4 46# define gen_helper_done(E) qemu_build_not_reached()
e8325dc0 47# define gen_helper_flushw(E) qemu_build_not_reached()
af25071c 48# define gen_helper_rdccr(D, E) qemu_build_not_reached()
5d617bfb 49# define gen_helper_rdcwp(D, E) qemu_build_not_reached()
25524734 50# define gen_helper_restored(E) qemu_build_not_reached()
8f75b8a4 51# define gen_helper_retry(E) qemu_build_not_reached()
25524734 52# define gen_helper_saved(E) qemu_build_not_reached()
4ee85ea9 53# define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached()
0faef01b 54# define gen_helper_set_softint(E, S) qemu_build_not_reached()
af25071c 55# define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached()
9422278e 56# define gen_helper_tick_set_count(P, S) qemu_build_not_reached()
bb97f2f5 57# define gen_helper_tick_set_limit(P, S) qemu_build_not_reached()
4ee85ea9 58# define gen_helper_udivx(D, E, A, B) qemu_build_not_reached()
0faef01b 59# define gen_helper_wrccr(E, S) qemu_build_not_reached()
9422278e
RH		 60# define gen_helper_wrcwp(E, S) qemu_build_not_reached()
61# define gen_helper_wrgl(E, S) qemu_build_not_reached()
0faef01b 62# define gen_helper_write_softint(E, S) qemu_build_not_reached()
9422278e
RH		 63# define gen_helper_wrpil(E, S) qemu_build_not_reached()
64# define gen_helper_wrpstate(E, S) qemu_build_not_reached()
668bb9b7 65# define MAXTL_MASK 0
af25071c
RH		 66#endif
67
633c4283
RH		 68/* Dynamic PC, must exit to main loop. */
69#define DYNAMIC_PC 1
70/* Dynamic PC, one of two values according to jump_pc[T2]. */
71#define JUMP_PC 2
72/* Dynamic PC, may lookup next TB. */
73#define DYNAMIC_PC_LOOKUP 3
72cbca10 74
46bb0137
MCA		 75#define DISAS_EXIT DISAS_TARGET_0
76
1a2fb1c0 77/* global register indexes */
1bcea73e 78static TCGv_ptr cpu_regwptr;
25517f99
PB		 79static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
80static TCGv_i32 cpu_cc_op;
a7812ae4 81static TCGv_i32 cpu_psr;
d2dc4069
RH		 82static TCGv cpu_fsr, cpu_pc, cpu_npc;
83static TCGv cpu_regs[32];
255e1fcb 84static TCGv cpu_y;
255e1fcb 85static TCGv cpu_tbr;
5793f2a4 86static TCGv cpu_cond;
dc99a3f2 87#ifdef TARGET_SPARC64
a6d567e5 88static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 89static TCGv cpu_gsr;
255e1fcb 90#else
af25071c
RH		 91# define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; })
92# define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; })
dc99a3f2 93#endif
714547bb 94/* Floating point registers */
30038fd8 95static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 96
af25071c
RH		 97#define env_field_offsetof(X) offsetof(CPUSPARCState, X)
98#ifdef TARGET_SPARC64
cd6269f7 99# define env32_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
af25071c
RH		 100# define env64_field_offsetof(X) env_field_offsetof(X)
101#else
cd6269f7 102# define env32_field_offsetof(X) env_field_offsetof(X)
af25071c
RH		 103# define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
104#endif
105
186e7890
RH		 106typedef struct DisasDelayException {
107 struct DisasDelayException *next;
108 TCGLabel *lab;
109 TCGv_i32 excp;
110 /* Saved state at parent insn. */
111 target_ulong pc;
112 target_ulong npc;
113} DisasDelayException;
114
7a3f1944 115typedef struct DisasContext {
af00be49 116 DisasContextBase base;
0f8a249a
BS		 117 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
118 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 119 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
e8af50a3 120 int mem_idx;
c9b459aa
AT		 121 bool fpu_enabled;
122 bool address_mask_32bit;
c9b459aa
AT		 123#ifndef CONFIG_USER_ONLY
124 bool supervisor;
125#ifdef TARGET_SPARC64
126 bool hypervisor;
127#endif
128#endif
129
8393617c 130 uint32_t cc_op; /* current CC operation */
5578ceab 131 sparc_def_t *def;
a6d567e5 132#ifdef TARGET_SPARC64
f9c816c0 133 int fprs_dirty;
a6d567e5
RH		 134 int asi;
135#endif
186e7890 136 DisasDelayException *delay_excp_list;
7a3f1944
FB		 137} DisasContext;
138
416fcaea
RH		 139typedef struct {
140 TCGCond cond;
141 bool is_bool;
416fcaea
RH		 142 TCGv c1, c2;
143} DisasCompare;
144
3475187d 145// This function uses non-native bit order
dc1a6971
BS		 146#define GET_FIELD(X, FROM, TO) \
147 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 148
3475187d 149// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 150#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 151 GET_FIELD(X, 31 - (TO), 31 - (FROM))
152
153#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 154#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 155
156#ifdef TARGET_SPARC64
0387d928 157#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 158#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 159#else
c185970a 160#define DFPREG(r) (r & 0x1e)
1f587329 161#define QFPREG(r) (r & 0x1c)
3475187d
FB		 162#endif
163
b158a785
BS		 164#define UA2005_HTRAP_MASK 0xff
165#define V8_TRAP_MASK 0x7f
166
3475187d
FB		 167static int sign_extend(int x, int len)
168{
169 len = 32 - len;
170 return (x << len) >> len;
171}
172
7a3f1944
FB		 173#define IS_IMM (insn & (1<<13))
174
0c2e96c1 175static void gen_update_fprs_dirty(DisasContext *dc, int rd)
141ae5c1
RH		 176{
177#if defined(TARGET_SPARC64)
f9c816c0
RH		 178 int bit = (rd < 32) ? 1 : 2;
179 /* If we know we've already set this bit within the TB,
180 we can avoid setting it again. */
181 if (!(dc->fprs_dirty & bit)) {
182 dc->fprs_dirty |= bit;
183 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
184 }
141ae5c1
RH		 185#endif
186}
187
ff07ec83 188/* floating point registers moves */
208ae657
RH		 189static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
190{
36ab4623 191 TCGv_i32 ret = tcg_temp_new_i32();
30038fd8 192 if (src & 1) {
dc41aa7d 193 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 194 } else {
dc41aa7d 195 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 196 }
dc41aa7d 197 return ret;
208ae657
RH		 198}
199
200static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
201{
8e7bbc75
RH		 202 TCGv_i64 t = tcg_temp_new_i64();
203
204 tcg_gen_extu_i32_i64(t, v);
30038fd8
RH		 205 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
206 (dst & 1 ? 0 : 32), 32);
f9c816c0 207 gen_update_fprs_dirty(dc, dst);
208ae657
RH		 208}
209
ba5f5179 210static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 211{
36ab4623 212 return tcg_temp_new_i32();
208ae657
RH		 213}
214
96eda024
RH		 215static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
216{
96eda024 217 src = DFPREG(src);
30038fd8 218 return cpu_fpr[src / 2];
96eda024
RH		 219}
220
221static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
222{
223 dst = DFPREG(dst);
30038fd8 224 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
f9c816c0 225 gen_update_fprs_dirty(dc, dst);
96eda024
RH		 226}
227
3886b8a3 228static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 229{
3886b8a3 230 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 231}
232
ff07ec83
BS		 233static void gen_op_load_fpr_QT0(unsigned int src)
234{
ad75a51e 235 tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 236 offsetof(CPU_QuadU, ll.upper));
ad75a51e 237 tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 238 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 239}
240
241static void gen_op_load_fpr_QT1(unsigned int src)
242{
ad75a51e 243 tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt1) +
30038fd8 244 offsetof(CPU_QuadU, ll.upper));
ad75a51e 245 tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt1) +
30038fd8 246 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 247}
248
249static void gen_op_store_QT0_fpr(unsigned int dst)
250{
ad75a51e 251 tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 252 offsetof(CPU_QuadU, ll.upper));
ad75a51e 253 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 254 offsetof(CPU_QuadU, ll.lower));
ff07ec83 255}
1f587329 256
f939ffe5
RH		 257static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
258 TCGv_i64 v1, TCGv_i64 v2)
259{
260 dst = QFPREG(dst);
261
262 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
263 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
264 gen_update_fprs_dirty(dc, dst);
265}
266
ac11f776 267#ifdef TARGET_SPARC64
f939ffe5
RH		 268static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
269{
270 src = QFPREG(src);
271 return cpu_fpr[src / 2];
272}
273
274static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
275{
276 src = QFPREG(src);
277 return cpu_fpr[src / 2 + 1];
278}
279
f9c816c0 280static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
ac11f776
RH		 281{
282 rd = QFPREG(rd);
283 rs = QFPREG(rs);
284
30038fd8
RH		 285 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
286 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
f9c816c0 287 gen_update_fprs_dirty(dc, rd);
ac11f776
RH		 288}
289#endif
290
81ad8ba2
BS		 291/* moves */
292#ifdef CONFIG_USER_ONLY
3475187d 293#define supervisor(dc) 0
e9ebed4d 294#define hypervisor(dc) 0
3475187d 295#else
81ad8ba2 296#ifdef TARGET_SPARC64
c9b459aa
AT		 297#define hypervisor(dc) (dc->hypervisor)
298#define supervisor(dc) (dc->supervisor | dc->hypervisor)
6f27aba6 299#else
c9b459aa 300#define supervisor(dc) (dc->supervisor)
668bb9b7 301#define hypervisor(dc) 0
3475187d 302#endif
81ad8ba2
BS		 303#endif
304
b1bc09ea
RH		 305#if !defined(TARGET_SPARC64)
306# define AM_CHECK(dc) false
307#elif defined(TARGET_ABI32)
308# define AM_CHECK(dc) true
309#elif defined(CONFIG_USER_ONLY)
310# define AM_CHECK(dc) false
1a2fb1c0 311#else
b1bc09ea 312# define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 313#endif
3391c818 314
0c2e96c1 315static void gen_address_mask(DisasContext *dc, TCGv addr)
2cade6a3 316{
b1bc09ea 317 if (AM_CHECK(dc)) {
2cade6a3 318 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
b1bc09ea 319 }
2cade6a3
BS		 320}
321
23ada1b1
RH		 322static target_ulong address_mask_i(DisasContext *dc, target_ulong addr)
323{
324 return AM_CHECK(dc) ? (uint32_t)addr : addr;
325}
326
0c2e96c1 327static TCGv gen_load_gpr(DisasContext *dc, int reg)
88023616 328{
d2dc4069
RH		 329 if (reg > 0) {
330 assert(reg < 32);
331 return cpu_regs[reg];
332 } else {
52123f14 333 TCGv t = tcg_temp_new();
d2dc4069 334 tcg_gen_movi_tl(t, 0);
88023616 335 return t;
88023616
RH		 336 }
337}
338
0c2e96c1 339static void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
88023616
RH		 340{
341 if (reg > 0) {
d2dc4069
RH		 342 assert(reg < 32);
343 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 344 }
345}
346
0c2e96c1 347static TCGv gen_dest_gpr(DisasContext *dc, int reg)
88023616 348{
d2dc4069
RH		 349 if (reg > 0) {
350 assert(reg < 32);
351 return cpu_regs[reg];
88023616 352 } else {
52123f14 353 return tcg_temp_new();
88023616
RH		 354 }
355}
356
5645aa2e 357static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc)
90aa39a1 358{
5645aa2e
RH		 359 return translator_use_goto_tb(&s->base, pc) &&
360 translator_use_goto_tb(&s->base, npc);
90aa39a1
SF		 361}
362
5645aa2e
RH		 363static void gen_goto_tb(DisasContext *s, int tb_num,
364 target_ulong pc, target_ulong npc)
6e256c93 365{
90aa39a1 366 if (use_goto_tb(s, pc, npc)) {
6e256c93 367 /* jump to same page: we can use a direct jump */
57fec1fe 368 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 369 tcg_gen_movi_tl(cpu_pc, pc);
370 tcg_gen_movi_tl(cpu_npc, npc);
07ea28b4 371 tcg_gen_exit_tb(s->base.tb, tb_num);
6e256c93 372 } else {
f67ccb2f 373 /* jump to another page: we can use an indirect jump */
2f5680ee
BS		 374 tcg_gen_movi_tl(cpu_pc, pc);
375 tcg_gen_movi_tl(cpu_npc, npc);
f67ccb2f 376 tcg_gen_lookup_and_goto_ptr();
6e256c93
FB		 377 }
378}
379
19f329ad 380// XXX suboptimal
0c2e96c1 381static void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 382{
8911f501 383 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 384 tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
19f329ad
BS		 385}
386
0c2e96c1 387static void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 388{
8911f501 389 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 390 tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
19f329ad
BS		 391}
392
0c2e96c1 393static void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 394{
8911f501 395 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 396 tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
19f329ad
BS		 397}
398
0c2e96c1 399static void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 400{
8911f501 401 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 402 tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
19f329ad
BS		 403}
404
0c2e96c1 405static void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 406{
4af984a7 407 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 408 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 409 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 410 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 411}
412
70c48285 413static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 414{
70c48285
RH		 415 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
416
417 /* Carry is computed from a previous add: (dst < src) */
418#if TARGET_LONG_BITS == 64
419 cc_src1_32 = tcg_temp_new_i32();
420 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 421 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
422 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 423#else
424 cc_src1_32 = cpu_cc_dst;
425 cc_src2_32 = cpu_cc_src;
426#endif
427
428 carry_32 = tcg_temp_new_i32();
429 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
430
70c48285 431 return carry_32;
41d72852
BS		 432}
433
70c48285 434static TCGv_i32 gen_sub32_carry32(void)
41d72852 435{
70c48285
RH		 436 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
437
438 /* Carry is computed from a previous borrow: (src1 < src2) */
439#if TARGET_LONG_BITS == 64
440 cc_src1_32 = tcg_temp_new_i32();
441 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 442 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
443 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 444#else
445 cc_src1_32 = cpu_cc_src;
446 cc_src2_32 = cpu_cc_src2;
447#endif
448
449 carry_32 = tcg_temp_new_i32();
450 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
451
70c48285
RH		 452 return carry_32;
453}
454
420a187d
RH		 455static void gen_op_addc_int(TCGv dst, TCGv src1, TCGv src2,
456 TCGv_i32 carry_32, bool update_cc)
70c48285 457{
420a187d 458 tcg_gen_add_tl(dst, src1, src2);
70c48285 459
420a187d
RH		 460#ifdef TARGET_SPARC64
461 TCGv carry = tcg_temp_new();
462 tcg_gen_extu_i32_tl(carry, carry_32);
463 tcg_gen_add_tl(dst, dst, carry);
464#else
465 tcg_gen_add_i32(dst, dst, carry_32);
466#endif
70c48285 467
420a187d
RH		 468 if (update_cc) {
469 tcg_debug_assert(dst == cpu_cc_dst);
470 tcg_gen_mov_tl(cpu_cc_src, src1);
471 tcg_gen_mov_tl(cpu_cc_src2, src2);
472 }
473}
70c48285 474
420a187d
RH		 475static void gen_op_addc_int_add(TCGv dst, TCGv src1, TCGv src2, bool update_cc)
476{
477 TCGv discard;
70c48285 478
420a187d
RH		 479 if (TARGET_LONG_BITS == 64) {
480 gen_op_addc_int(dst, src1, src2, gen_add32_carry32(), update_cc);
481 return;
70c48285
RH		 482 }
483
420a187d
RH		 484 /*
485 * We can re-use the host's hardware carry generation by using
486 * an ADD2 opcode. We discard the low part of the output.
487 * Ideally we'd combine this operation with the add that
488 * generated the carry in the first place.
489 */
490 discard = tcg_temp_new();
491 tcg_gen_add2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
70c48285 492
70c48285 493 if (update_cc) {
420a187d 494 tcg_debug_assert(dst == cpu_cc_dst);
70c48285
RH		 495 tcg_gen_mov_tl(cpu_cc_src, src1);
496 tcg_gen_mov_tl(cpu_cc_src2, src2);
70c48285 497 }
dc99a3f2
BS		 498}
499
420a187d
RH		 500static void gen_op_addc_add(TCGv dst, TCGv src1, TCGv src2)
501{
502 gen_op_addc_int_add(dst, src1, src2, false);
503}
504
505static void gen_op_addccc_add(TCGv dst, TCGv src1, TCGv src2)
506{
507 gen_op_addc_int_add(dst, src1, src2, true);
508}
509
510static void gen_op_addc_sub(TCGv dst, TCGv src1, TCGv src2)
511{
512 gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), false);
513}
514
515static void gen_op_addccc_sub(TCGv dst, TCGv src1, TCGv src2)
516{
517 gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), true);
518}
519
520static void gen_op_addc_int_generic(TCGv dst, TCGv src1, TCGv src2,
521 bool update_cc)
522{
523 TCGv_i32 carry_32 = tcg_temp_new_i32();
524 gen_helper_compute_C_icc(carry_32, tcg_env);
525 gen_op_addc_int(dst, src1, src2, carry_32, update_cc);
526}
527
528static void gen_op_addc_generic(TCGv dst, TCGv src1, TCGv src2)
529{
530 gen_op_addc_int_generic(dst, src1, src2, false);
531}
532
533static void gen_op_addccc_generic(TCGv dst, TCGv src1, TCGv src2)
534{
535 gen_op_addc_int_generic(dst, src1, src2, true);
536}
537
0c2e96c1 538static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 539{
4af984a7 540 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 541 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 542 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 543 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 544}
545
dfebb950
RH		 546static void gen_op_subc_int(TCGv dst, TCGv src1, TCGv src2,
547 TCGv_i32 carry_32, bool update_cc)
41d72852 548{
70c48285 549 TCGv carry;
41d72852 550
70c48285
RH		 551#if TARGET_LONG_BITS == 64
552 carry = tcg_temp_new();
553 tcg_gen_extu_i32_i64(carry, carry_32);
554#else
555 carry = carry_32;
556#endif
557
558 tcg_gen_sub_tl(dst, src1, src2);
559 tcg_gen_sub_tl(dst, dst, carry);
560
70c48285 561 if (update_cc) {
dfebb950 562 tcg_debug_assert(dst == cpu_cc_dst);
70c48285
RH		 563 tcg_gen_mov_tl(cpu_cc_src, src1);
564 tcg_gen_mov_tl(cpu_cc_src2, src2);
70c48285 565 }
dc99a3f2
BS		 566}
567
dfebb950
RH		 568static void gen_op_subc_add(TCGv dst, TCGv src1, TCGv src2)
569{
570 gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), false);
571}
572
573static void gen_op_subccc_add(TCGv dst, TCGv src1, TCGv src2)
574{
575 gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), true);
576}
577
578static void gen_op_subc_int_sub(TCGv dst, TCGv src1, TCGv src2, bool update_cc)
579{
580 TCGv discard;
581
582 if (TARGET_LONG_BITS == 64) {
583 gen_op_subc_int(dst, src1, src2, gen_sub32_carry32(), update_cc);
584 return;
585 }
586
587 /*
588 * We can re-use the host's hardware carry generation by using
589 * a SUB2 opcode. We discard the low part of the output.
590 */
591 discard = tcg_temp_new();
592 tcg_gen_sub2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
593
594 if (update_cc) {
595 tcg_debug_assert(dst == cpu_cc_dst);
596 tcg_gen_mov_tl(cpu_cc_src, src1);
597 tcg_gen_mov_tl(cpu_cc_src2, src2);
598 }
599}
600
601static void gen_op_subc_sub(TCGv dst, TCGv src1, TCGv src2)
602{
603 gen_op_subc_int_sub(dst, src1, src2, false);
604}
605
606static void gen_op_subccc_sub(TCGv dst, TCGv src1, TCGv src2)
607{
608 gen_op_subc_int_sub(dst, src1, src2, true);
609}
610
611static void gen_op_subc_int_generic(TCGv dst, TCGv src1, TCGv src2,
612 bool update_cc)
613{
614 TCGv_i32 carry_32 = tcg_temp_new_i32();
615
616 gen_helper_compute_C_icc(carry_32, tcg_env);
617 gen_op_subc_int(dst, src1, src2, carry_32, update_cc);
618}
619
620static void gen_op_subc_generic(TCGv dst, TCGv src1, TCGv src2)
621{
622 gen_op_subc_int_generic(dst, src1, src2, false);
623}
624
625static void gen_op_subccc_generic(TCGv dst, TCGv src1, TCGv src2)
626{
627 gen_op_subc_int_generic(dst, src1, src2, true);
628}
629
0c2e96c1 630static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 631{
de9e9d9f 632 TCGv r_temp, zero, t0;
d9bdab86 633
a7812ae4 634 r_temp = tcg_temp_new();
de9e9d9f 635 t0 = tcg_temp_new();
d9bdab86
BS		 636
637 /* old op:
638 if (!(env->y & 1))
639 T1 = 0;
640 */
00ab7e61 641 zero = tcg_constant_tl(0);
72ccba79 642 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 643 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 644 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 645 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
646 zero, cpu_cc_src2);
d9bdab86
BS		 647
648 // b2 = T0 & 1;
649 // env->y = (b2 << 31) | (env->y >> 1);
0b1183e3 650 tcg_gen_extract_tl(t0, cpu_y, 1, 31);
08d64e0d 651 tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
d9bdab86
BS		 652
653 // b1 = N ^ V;
de9e9d9f 654 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 655 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 656 tcg_gen_xor_tl(t0, t0, r_temp);
d9bdab86
BS		 657
658 // T0 = (b1 << 31) | (T0 >> 1);
659 // src1 = T0;
de9e9d9f 660 tcg_gen_shli_tl(t0, t0, 31);
6f551262 661 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f 662 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
d9bdab86 663
5c6a0628 664 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 665
5c6a0628 666 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 667}
668
0c2e96c1 669static void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 670{
528692a8 671#if TARGET_LONG_BITS == 32
fb170183 672 if (sign_ext) {
528692a8 673 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 674 } else {
528692a8 675 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 676 }
528692a8
RH		 677#else
678 TCGv t0 = tcg_temp_new_i64();
679 TCGv t1 = tcg_temp_new_i64();
fb170183 680
528692a8
RH		 681 if (sign_ext) {
682 tcg_gen_ext32s_i64(t0, src1);
683 tcg_gen_ext32s_i64(t1, src2);
684 } else {
685 tcg_gen_ext32u_i64(t0, src1);
686 tcg_gen_ext32u_i64(t1, src2);
687 }
fb170183 688
528692a8 689 tcg_gen_mul_i64(dst, t0, t1);
528692a8
RH		 690 tcg_gen_shri_i64(cpu_y, dst, 32);
691#endif
8879d139
BS		 692}
693
0c2e96c1 694static void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 695{
fb170183
IK		 696 /* zero-extend truncated operands before multiplication */
697 gen_op_multiply(dst, src1, src2, 0);
698}
8879d139 699
0c2e96c1 700static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
fb170183
IK		 701{
702 /* sign-extend truncated operands before multiplication */
703 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 704}
705
4ee85ea9
RH		 706static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2)
707{
708 gen_helper_udivx(dst, tcg_env, src1, src2);
709}
710
711static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
712{
713 gen_helper_sdivx(dst, tcg_env, src1, src2);
714}
715
c2636853
RH		 716static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
717{
718 gen_helper_udiv(dst, tcg_env, src1, src2);
719}
720
721static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
722{
723 gen_helper_sdiv(dst, tcg_env, src1, src2);
724}
725
726static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2)
727{
728 gen_helper_udiv_cc(dst, tcg_env, src1, src2);
729}
730
731static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
732{
733 gen_helper_sdiv_cc(dst, tcg_env, src1, src2);
734}
735
a9aba13d
RH		 736static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2)
737{
738 gen_helper_taddcctv(dst, tcg_env, src1, src2);
739}
740
741static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2)
742{
743 gen_helper_tsubcctv(dst, tcg_env, src1, src2);
744}
745
9c6ec5bc
RH		 746static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2)
747{
748 tcg_gen_ctpop_tl(dst, src2);
749}
750
19f329ad 751// 1
0c2e96c1 752static void gen_op_eval_ba(TCGv dst)
19f329ad
BS		 753{
754 tcg_gen_movi_tl(dst, 1);
755}
756
757// Z
0c2e96c1 758static void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 759{
760 gen_mov_reg_Z(dst, src);
761}
762
763// Z | (N ^ V)
0c2e96c1 764static void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 765{
de9e9d9f
RH		 766 TCGv t0 = tcg_temp_new();
767 gen_mov_reg_N(t0, src);
19f329ad 768 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 769 tcg_gen_xor_tl(dst, dst, t0);
770 gen_mov_reg_Z(t0, src);
771 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 772}
773
774// N ^ V
0c2e96c1 775static void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 776{
de9e9d9f
RH		 777 TCGv t0 = tcg_temp_new();
778 gen_mov_reg_V(t0, src);
19f329ad 779 gen_mov_reg_N(dst, src);
de9e9d9f 780 tcg_gen_xor_tl(dst, dst, t0);
19f329ad
BS		 781}
782
783// C | Z
0c2e96c1 784static void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 785{
de9e9d9f
RH		 786 TCGv t0 = tcg_temp_new();
787 gen_mov_reg_Z(t0, src);
19f329ad 788 gen_mov_reg_C(dst, src);
de9e9d9f 789 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 790}
791
792// C
0c2e96c1 793static void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 794{
795 gen_mov_reg_C(dst, src);
796}
797
798// V
0c2e96c1 799static void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 800{
801 gen_mov_reg_V(dst, src);
802}
803
804// 0
0c2e96c1 805static void gen_op_eval_bn(TCGv dst)
19f329ad
BS		 806{
807 tcg_gen_movi_tl(dst, 0);
808}
809
810// N
0c2e96c1 811static void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 812{
813 gen_mov_reg_N(dst, src);
814}
815
816// !Z
0c2e96c1 817static void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 818{
819 gen_mov_reg_Z(dst, src);
820 tcg_gen_xori_tl(dst, dst, 0x1);
821}
822
823// !(Z | (N ^ V))
0c2e96c1 824static void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 825{
de9e9d9f 826 gen_op_eval_ble(dst, src);
19f329ad
BS		 827 tcg_gen_xori_tl(dst, dst, 0x1);
828}
829
830// !(N ^ V)
0c2e96c1 831static void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 832{
de9e9d9f 833 gen_op_eval_bl(dst, src);
19f329ad
BS		 834 tcg_gen_xori_tl(dst, dst, 0x1);
835}
836
837// !(C | Z)
0c2e96c1 838static void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 839{
de9e9d9f 840 gen_op_eval_bleu(dst, src);
19f329ad
BS		 841 tcg_gen_xori_tl(dst, dst, 0x1);
842}
843
844// !C
0c2e96c1 845static void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 846{
847 gen_mov_reg_C(dst, src);
848 tcg_gen_xori_tl(dst, dst, 0x1);
849}
850
851// !N
0c2e96c1 852static void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 853{
854 gen_mov_reg_N(dst, src);
855 tcg_gen_xori_tl(dst, dst, 0x1);
856}
857
858// !V
0c2e96c1 859static void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 860{
861 gen_mov_reg_V(dst, src);
862 tcg_gen_xori_tl(dst, dst, 0x1);
863}
864
865/*
866 FPSR bit field FCC1 | FCC0:
867 0 =
868 1 <
869 2 >
870 3 unordered
871*/
0c2e96c1 872static void gen_mov_reg_FCC0(TCGv reg, TCGv src,
19f329ad
BS		 873 unsigned int fcc_offset)
874{
ba6a9d8c 875 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 876 tcg_gen_andi_tl(reg, reg, 0x1);
877}
878
0c2e96c1 879static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset)
19f329ad 880{
ba6a9d8c 881 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 882 tcg_gen_andi_tl(reg, reg, 0x1);
883}
884
885// !0: FCC0 | FCC1
0c2e96c1 886static void gen_op_eval_fbne(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 887{
de9e9d9f 888 TCGv t0 = tcg_temp_new();
19f329ad 889 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 890 gen_mov_reg_FCC1(t0, src, fcc_offset);
891 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 892}
893
894// 1 or 2: FCC0 ^ FCC1
0c2e96c1 895static void gen_op_eval_fblg(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 896{
de9e9d9f 897 TCGv t0 = tcg_temp_new();
19f329ad 898 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 899 gen_mov_reg_FCC1(t0, src, fcc_offset);
900 tcg_gen_xor_tl(dst, dst, t0);
19f329ad
BS		 901}
902
903// 1 or 3: FCC0
0c2e96c1 904static void gen_op_eval_fbul(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 905{
906 gen_mov_reg_FCC0(dst, src, fcc_offset);
907}
908
909// 1: FCC0 & !FCC1
0c2e96c1 910static void gen_op_eval_fbl(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 911{
de9e9d9f 912 TCGv t0 = tcg_temp_new();
19f329ad 913 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 914 gen_mov_reg_FCC1(t0, src, fcc_offset);
915 tcg_gen_andc_tl(dst, dst, t0);
19f329ad
BS		 916}
917
918// 2 or 3: FCC1
0c2e96c1 919static void gen_op_eval_fbug(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 920{
921 gen_mov_reg_FCC1(dst, src, fcc_offset);
922}
923
924// 2: !FCC0 & FCC1
0c2e96c1 925static void gen_op_eval_fbg(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 926{
de9e9d9f 927 TCGv t0 = tcg_temp_new();
19f329ad 928 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 929 gen_mov_reg_FCC1(t0, src, fcc_offset);
930 tcg_gen_andc_tl(dst, t0, dst);
19f329ad
BS		 931}
932
933// 3: FCC0 & FCC1
0c2e96c1 934static void gen_op_eval_fbu(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 935{
de9e9d9f 936 TCGv t0 = tcg_temp_new();
19f329ad 937 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 938 gen_mov_reg_FCC1(t0, src, fcc_offset);
939 tcg_gen_and_tl(dst, dst, t0);
19f329ad
BS		 940}
941
942// 0: !(FCC0 | FCC1)
0c2e96c1 943static void gen_op_eval_fbe(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 944{
de9e9d9f 945 TCGv t0 = tcg_temp_new();
19f329ad 946 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 947 gen_mov_reg_FCC1(t0, src, fcc_offset);
948 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 949 tcg_gen_xori_tl(dst, dst, 0x1);
950}
951
952// 0 or 3: !(FCC0 ^ FCC1)
0c2e96c1 953static void gen_op_eval_fbue(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 954{
de9e9d9f 955 TCGv t0 = tcg_temp_new();
19f329ad 956 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 957 gen_mov_reg_FCC1(t0, src, fcc_offset);
958 tcg_gen_xor_tl(dst, dst, t0);
19f329ad
BS		 959 tcg_gen_xori_tl(dst, dst, 0x1);
960}
961
962// 0 or 2: !FCC0
0c2e96c1 963static void gen_op_eval_fbge(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 964{
965 gen_mov_reg_FCC0(dst, src, fcc_offset);
966 tcg_gen_xori_tl(dst, dst, 0x1);
967}
968
969// !1: !(FCC0 & !FCC1)
0c2e96c1 970static void gen_op_eval_fbuge(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 971{
de9e9d9f 972 TCGv t0 = tcg_temp_new();
19f329ad 973 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 974 gen_mov_reg_FCC1(t0, src, fcc_offset);
975 tcg_gen_andc_tl(dst, dst, t0);
19f329ad
BS		 976 tcg_gen_xori_tl(dst, dst, 0x1);
977}
978
979// 0 or 1: !FCC1
0c2e96c1 980static void gen_op_eval_fble(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 981{
982 gen_mov_reg_FCC1(dst, src, fcc_offset);
983 tcg_gen_xori_tl(dst, dst, 0x1);
984}
985
986// !2: !(!FCC0 & FCC1)
0c2e96c1 987static void gen_op_eval_fbule(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 988{
de9e9d9f 989 TCGv t0 = tcg_temp_new();
19f329ad 990 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 991 gen_mov_reg_FCC1(t0, src, fcc_offset);
992 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 993 tcg_gen_xori_tl(dst, dst, 0x1);
19f329ad
BS		 994}
995
996// !3: !(FCC0 & FCC1)
0c2e96c1 997static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 998{
de9e9d9f 999 TCGv t0 = tcg_temp_new();
19f329ad 1000 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 1001 gen_mov_reg_FCC1(t0, src, fcc_offset);
1002 tcg_gen_and_tl(dst, dst, t0);
19f329ad
BS		 1003 tcg_gen_xori_tl(dst, dst, 0x1);
1004}
1005
0c2e96c1
RH		 1006static void gen_branch2(DisasContext *dc, target_ulong pc1,
1007 target_ulong pc2, TCGv r_cond)
83469015 1008{
42a268c2 1009 TCGLabel *l1 = gen_new_label();
83469015 1010
cb63669a 1011 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1012
6e256c93 1013 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1014
1015 gen_set_label(l1);
6e256c93 1016 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1017}
1018
0c2e96c1 1019static void gen_generic_branch(DisasContext *dc)
83469015 1020{
00ab7e61
RH		 1021 TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]);
1022 TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]);
1023 TCGv zero = tcg_constant_tl(0);
19f329ad 1024
61316742 1025 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015
FB		 1026}
1027
4af984a7
BS		 1028/* call this function before using the condition register as it may
1029 have been set for a jump */
0c2e96c1 1030static void flush_cond(DisasContext *dc)
83469015
FB		 1031{
1032 if (dc->npc == JUMP_PC) {
2e655fe7 1033 gen_generic_branch(dc);
99c82c47 1034 dc->npc = DYNAMIC_PC_LOOKUP;
83469015
FB		 1035 }
1036}
1037
0c2e96c1 1038static void save_npc(DisasContext *dc)
72cbca10 1039{
633c4283
RH		 1040 if (dc->npc & 3) {
1041 switch (dc->npc) {
1042 case JUMP_PC:
1043 gen_generic_branch(dc);
99c82c47 1044 dc->npc = DYNAMIC_PC_LOOKUP;
633c4283
RH		 1045 break;
1046 case DYNAMIC_PC:
1047 case DYNAMIC_PC_LOOKUP:
1048 break;
1049 default:
1050 g_assert_not_reached();
1051 }
1052 } else {
2f5680ee 1053 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1054 }
1055}
1056
0c2e96c1 1057static void update_psr(DisasContext *dc)
72cbca10 1058{
cfa90513
BS		 1059 if (dc->cc_op != CC_OP_FLAGS) {
1060 dc->cc_op = CC_OP_FLAGS;
ad75a51e 1061 gen_helper_compute_psr(tcg_env);
cfa90513 1062 }
20132b96
RH		 1063}
1064
0c2e96c1 1065static void save_state(DisasContext *dc)
20132b96
RH		 1066{
1067 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1068 save_npc(dc);
72cbca10
FB		 1069}
1070
4fbe0067
RH		 1071static void gen_exception(DisasContext *dc, int which)
1072{
4fbe0067 1073 save_state(dc);
ad75a51e 1074 gen_helper_raise_exception(tcg_env, tcg_constant_i32(which));
af00be49 1075 dc->base.is_jmp = DISAS_NORETURN;
4fbe0067
RH		 1076}
1077
186e7890 1078static TCGLabel *delay_exceptionv(DisasContext *dc, TCGv_i32 excp)
35e94905 1079{
186e7890
RH		 1080 DisasDelayException *e = g_new0(DisasDelayException, 1);
1081
1082 e->next = dc->delay_excp_list;
1083 dc->delay_excp_list = e;
1084
1085 e->lab = gen_new_label();
1086 e->excp = excp;
1087 e->pc = dc->pc;
1088 /* Caller must have used flush_cond before branch. */
1089 assert(e->npc != JUMP_PC);
1090 e->npc = dc->npc;
1091
1092 return e->lab;
1093}
1094
1095static TCGLabel *delay_exception(DisasContext *dc, int excp)
1096{
1097 return delay_exceptionv(dc, tcg_constant_i32(excp));
1098}
1099
1100static void gen_check_align(DisasContext *dc, TCGv addr, int mask)
1101{
1102 TCGv t = tcg_temp_new();
1103 TCGLabel *lab;
1104
1105 tcg_gen_andi_tl(t, addr, mask);
1106
1107 flush_cond(dc);
1108 lab = delay_exception(dc, TT_UNALIGNED);
1109 tcg_gen_brcondi_tl(TCG_COND_NE, t, 0, lab);
35e94905
RH		 1110}
1111
0c2e96c1 1112static void gen_mov_pc_npc(DisasContext *dc)
0bee699e 1113{
633c4283
RH		 1114 if (dc->npc & 3) {
1115 switch (dc->npc) {
1116 case JUMP_PC:
1117 gen_generic_branch(dc);
1118 tcg_gen_mov_tl(cpu_pc, cpu_npc);
99c82c47 1119 dc->pc = DYNAMIC_PC_LOOKUP;
633c4283
RH		 1120 break;
1121 case DYNAMIC_PC:
1122 case DYNAMIC_PC_LOOKUP:
1123 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1124 dc->pc = dc->npc;
1125 break;
1126 default:
1127 g_assert_not_reached();
1128 }
0bee699e
FB		 1129 } else {
1130 dc->pc = dc->npc;
1131 }
1132}
1133
0c2e96c1 1134static void gen_op_next_insn(void)
38bc628b 1135{
48d5c82b
BS		 1136 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1137 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1138}
1139
2a484ecf 1140static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1141 DisasContext *dc)
19f329ad 1142{
2a484ecf 1143 static int subcc_cond[16] = {
96b5a3d3 1144 TCG_COND_NEVER,
2a484ecf
RH		 1145 TCG_COND_EQ,
1146 TCG_COND_LE,
1147 TCG_COND_LT,
1148 TCG_COND_LEU,
1149 TCG_COND_LTU,
1150 -1, /* neg */
1151 -1, /* overflow */
96b5a3d3 1152 TCG_COND_ALWAYS,
2a484ecf
RH		 1153 TCG_COND_NE,
1154 TCG_COND_GT,
1155 TCG_COND_GE,
1156 TCG_COND_GTU,
1157 TCG_COND_GEU,
1158 -1, /* pos */
1159 -1, /* no overflow */
1160 };
1161
96b5a3d3
RH		 1162 static int logic_cond[16] = {
1163 TCG_COND_NEVER,
1164 TCG_COND_EQ, /* eq: Z */
1165 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1166 TCG_COND_LT, /* lt: N ^ V -> N */
1167 TCG_COND_EQ, /* leu: C | Z -> Z */
1168 TCG_COND_NEVER, /* ltu: C -> 0 */
1169 TCG_COND_LT, /* neg: N */
1170 TCG_COND_NEVER, /* vs: V -> 0 */
1171 TCG_COND_ALWAYS,
1172 TCG_COND_NE, /* ne: !Z */
1173 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1174 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1175 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1176 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1177 TCG_COND_GE, /* pos: !N */
1178 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1179 };
1180
a7812ae4 1181 TCGv_i32 r_src;
416fcaea
RH		 1182 TCGv r_dst;
1183
3475187d 1184#ifdef TARGET_SPARC64
2a484ecf 1185 if (xcc) {
dc99a3f2 1186 r_src = cpu_xcc;
2a484ecf 1187 } else {
dc99a3f2 1188 r_src = cpu_psr;
2a484ecf 1189 }
3475187d 1190#else
dc99a3f2 1191 r_src = cpu_psr;
3475187d 1192#endif
2a484ecf 1193
8393617c 1194 switch (dc->cc_op) {
96b5a3d3
RH		 1195 case CC_OP_LOGIC:
1196 cmp->cond = logic_cond[cond];
1197 do_compare_dst_0:
1198 cmp->is_bool = false;
00ab7e61 1199 cmp->c2 = tcg_constant_tl(0);
96b5a3d3
RH		 1200#ifdef TARGET_SPARC64
1201 if (!xcc) {
96b5a3d3
RH		 1202 cmp->c1 = tcg_temp_new();
1203 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1204 break;
1205 }
1206#endif
96b5a3d3
RH		 1207 cmp->c1 = cpu_cc_dst;
1208 break;
1209
2a484ecf
RH		 1210 case CC_OP_SUB:
1211 switch (cond) {
1212 case 6: /* neg */
1213 case 14: /* pos */
1214 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1215 goto do_compare_dst_0;
2a484ecf 1216
2a484ecf
RH		 1217 case 7: /* overflow */
1218 case 15: /* !overflow */
1219 goto do_dynamic;
1220
1221 default:
1222 cmp->cond = subcc_cond[cond];
1223 cmp->is_bool = false;
1224#ifdef TARGET_SPARC64
1225 if (!xcc) {
1226 /* Note that sign-extension works for unsigned compares as
1227 long as both operands are sign-extended. */
2a484ecf
RH		 1228 cmp->c1 = tcg_temp_new();
1229 cmp->c2 = tcg_temp_new();
1230 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1231 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1232 break;
2a484ecf
RH		 1233 }
1234#endif
2a484ecf
RH		 1235 cmp->c1 = cpu_cc_src;
1236 cmp->c2 = cpu_cc_src2;
1237 break;
1238 }
8393617c 1239 break;
2a484ecf 1240
8393617c 1241 default:
2a484ecf 1242 do_dynamic:
ad75a51e 1243 gen_helper_compute_psr(tcg_env);
8393617c 1244 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1245 /* FALLTHRU */
1246
1247 case CC_OP_FLAGS:
1248 /* We're going to generate a boolean result. */
1249 cmp->cond = TCG_COND_NE;
1250 cmp->is_bool = true;
2a484ecf 1251 cmp->c1 = r_dst = tcg_temp_new();
00ab7e61 1252 cmp->c2 = tcg_constant_tl(0);
2a484ecf
RH		 1253
1254 switch (cond) {
1255 case 0x0:
1256 gen_op_eval_bn(r_dst);
1257 break;
1258 case 0x1:
1259 gen_op_eval_be(r_dst, r_src);
1260 break;
1261 case 0x2:
1262 gen_op_eval_ble(r_dst, r_src);
1263 break;
1264 case 0x3:
1265 gen_op_eval_bl(r_dst, r_src);
1266 break;
1267 case 0x4:
1268 gen_op_eval_bleu(r_dst, r_src);
1269 break;
1270 case 0x5:
1271 gen_op_eval_bcs(r_dst, r_src);
1272 break;
1273 case 0x6:
1274 gen_op_eval_bneg(r_dst, r_src);
1275 break;
1276 case 0x7:
1277 gen_op_eval_bvs(r_dst, r_src);
1278 break;
1279 case 0x8:
1280 gen_op_eval_ba(r_dst);
1281 break;
1282 case 0x9:
1283 gen_op_eval_bne(r_dst, r_src);
1284 break;
1285 case 0xa:
1286 gen_op_eval_bg(r_dst, r_src);
1287 break;
1288 case 0xb:
1289 gen_op_eval_bge(r_dst, r_src);
1290 break;
1291 case 0xc:
1292 gen_op_eval_bgu(r_dst, r_src);
1293 break;
1294 case 0xd:
1295 gen_op_eval_bcc(r_dst, r_src);
1296 break;
1297 case 0xe:
1298 gen_op_eval_bpos(r_dst, r_src);
1299 break;
1300 case 0xf:
1301 gen_op_eval_bvc(r_dst, r_src);
1302 break;
1303 }
19f329ad
BS		 1304 break;
1305 }
1306}
7a3f1944 1307
416fcaea 1308static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1309{
19f329ad 1310 unsigned int offset;
416fcaea
RH		 1311 TCGv r_dst;
1312
1313 /* For now we still generate a straight boolean result. */
1314 cmp->cond = TCG_COND_NE;
1315 cmp->is_bool = true;
416fcaea 1316 cmp->c1 = r_dst = tcg_temp_new();
00ab7e61 1317 cmp->c2 = tcg_constant_tl(0);
19f329ad 1318
19f329ad
BS		 1319 switch (cc) {
1320 default:
1321 case 0x0:
1322 offset = 0;
1323 break;
1324 case 0x1:
1325 offset = 32 - 10;
1326 break;
1327 case 0x2:
1328 offset = 34 - 10;
1329 break;
1330 case 0x3:
1331 offset = 36 - 10;
1332 break;
1333 }
1334
1335 switch (cond) {
1336 case 0x0:
1337 gen_op_eval_bn(r_dst);
1338 break;
1339 case 0x1:
87e92502 1340 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1341 break;
1342 case 0x2:
87e92502 1343 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1344 break;
1345 case 0x3:
87e92502 1346 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1347 break;
1348 case 0x4:
87e92502 1349 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1350 break;
1351 case 0x5:
87e92502 1352 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1353 break;
1354 case 0x6:
87e92502 1355 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1356 break;
1357 case 0x7:
87e92502 1358 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1359 break;
1360 case 0x8:
1361 gen_op_eval_ba(r_dst);
1362 break;
1363 case 0x9:
87e92502 1364 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1365 break;
1366 case 0xa:
87e92502 1367 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1368 break;
1369 case 0xb:
87e92502 1370 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1371 break;
1372 case 0xc:
87e92502 1373 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1374 break;
1375 case 0xd:
87e92502 1376 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1377 break;
1378 case 0xe:
87e92502 1379 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1380 break;
1381 case 0xf:
87e92502 1382 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1383 break;
1384 }
e8af50a3 1385}
00f219bf
BS		 1386
1387// Inverted logic
ab9ffe98
RH		 1388static const TCGCond gen_tcg_cond_reg[8] = {
1389 TCG_COND_NEVER, /* reserved */
00f219bf
BS		 1390 TCG_COND_NE,
1391 TCG_COND_GT,
1392 TCG_COND_GE,
ab9ffe98 1393 TCG_COND_NEVER, /* reserved */
00f219bf
BS		 1394 TCG_COND_EQ,
1395 TCG_COND_LE,
1396 TCG_COND_LT,
1397};
19f329ad 1398
416fcaea
RH		 1399static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1400{
1401 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1402 cmp->is_bool = false;
416fcaea 1403 cmp->c1 = r_src;
00ab7e61 1404 cmp->c2 = tcg_constant_tl(0);
416fcaea
RH		 1405}
1406
3475187d 1407#ifdef TARGET_SPARC64
0c2e96c1 1408static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1409{
714547bb
BS		 1410 switch (fccno) {
1411 case 0:
ad75a51e 1412 gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1413 break;
1414 case 1:
ad75a51e 1415 gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1416 break;
1417 case 2:
ad75a51e 1418 gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1419 break;
1420 case 3:
ad75a51e 1421 gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1422 break;
1423 }
7e8c2b6c
BS		 1424}
1425
0c2e96c1 1426static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1427{
a7812ae4
PB		 1428 switch (fccno) {
1429 case 0:
ad75a51e 1430 gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1431 break;
1432 case 1:
ad75a51e 1433 gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1434 break;
1435 case 2:
ad75a51e 1436 gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1437 break;
1438 case 3:
ad75a51e 1439 gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1440 break;
1441 }
7e8c2b6c
BS		 1442}
1443
0c2e96c1 1444static void gen_op_fcmpq(int fccno)
7e8c2b6c 1445{
a7812ae4
PB		 1446 switch (fccno) {
1447 case 0:
ad75a51e 1448 gen_helper_fcmpq(cpu_fsr, tcg_env);
a7812ae4
PB		 1449 break;
1450 case 1:
ad75a51e 1451 gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env);
a7812ae4
PB		 1452 break;
1453 case 2:
ad75a51e 1454 gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env);
a7812ae4
PB		 1455 break;
1456 case 3:
ad75a51e 1457 gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env);
a7812ae4
PB		 1458 break;
1459 }
7e8c2b6c 1460}
7e8c2b6c 1461
0c2e96c1 1462static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1463{
714547bb
BS		 1464 switch (fccno) {
1465 case 0:
ad75a51e 1466 gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1467 break;
1468 case 1:
ad75a51e 1469 gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1470 break;
1471 case 2:
ad75a51e 1472 gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1473 break;
1474 case 3:
ad75a51e 1475 gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1476 break;
1477 }
7e8c2b6c
BS		 1478}
1479
0c2e96c1 1480static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1481{
a7812ae4
PB		 1482 switch (fccno) {
1483 case 0:
ad75a51e 1484 gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1485 break;
1486 case 1:
ad75a51e 1487 gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1488 break;
1489 case 2:
ad75a51e 1490 gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1491 break;
1492 case 3:
ad75a51e 1493 gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1494 break;
1495 }
7e8c2b6c
BS		 1496}
1497
0c2e96c1 1498static void gen_op_fcmpeq(int fccno)
7e8c2b6c 1499{
a7812ae4
PB		 1500 switch (fccno) {
1501 case 0:
ad75a51e 1502 gen_helper_fcmpeq(cpu_fsr, tcg_env);
a7812ae4
PB		 1503 break;
1504 case 1:
ad75a51e 1505 gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env);
a7812ae4
PB		 1506 break;
1507 case 2:
ad75a51e 1508 gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env);
a7812ae4
PB		 1509 break;
1510 case 3:
ad75a51e 1511 gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env);
a7812ae4
PB		 1512 break;
1513 }
7e8c2b6c 1514}
7e8c2b6c
BS		 1515
1516#else
1517
0c2e96c1 1518static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1519{
ad75a51e 1520 gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1521}
1522
0c2e96c1 1523static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1524{
ad75a51e 1525 gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1526}
1527
0c2e96c1 1528static void gen_op_fcmpq(int fccno)
7e8c2b6c 1529{
ad75a51e 1530 gen_helper_fcmpq(cpu_fsr, tcg_env);
7e8c2b6c 1531}
7e8c2b6c 1532
0c2e96c1 1533static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1534{
ad75a51e 1535 gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1536}
1537
0c2e96c1 1538static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1539{
ad75a51e 1540 gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1541}
1542
0c2e96c1 1543static void gen_op_fcmpeq(int fccno)
7e8c2b6c 1544{
ad75a51e 1545 gen_helper_fcmpeq(cpu_fsr, tcg_env);
7e8c2b6c
BS		 1546}
1547#endif
1548
4fbe0067 1549static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1550{
47ad35f1 1551 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1552 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1553 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1554}
1555
5b12f1e8 1556static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1557{
1558#if !defined(CONFIG_USER_ONLY)
1559 if (!dc->fpu_enabled) {
4fbe0067 1560 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1561 return 1;
1562 }
1563#endif
1564 return 0;
1565}
1566
0c2e96c1 1567static void gen_op_clear_ieee_excp_and_FTT(void)
7e8c2b6c 1568{
47ad35f1 1569 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1570}
1571
0c2e96c1 1572static void gen_fop_FF(DisasContext *dc, int rd, int rs,
61f17f6e
RH		 1573 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1574{
1575 TCGv_i32 dst, src;
1576
61f17f6e 1577 src = gen_load_fpr_F(dc, rs);
ba5f5179 1578 dst = gen_dest_fpr_F(dc);
61f17f6e 1579
ad75a51e
RH		 1580 gen(dst, tcg_env, src);
1581 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1582
61f17f6e
RH		 1583 gen_store_fpr_F(dc, rd, dst);
1584}
1585
0c2e96c1
RH		 1586static void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1587 void (*gen)(TCGv_i32, TCGv_i32))
61f17f6e
RH		 1588{
1589 TCGv_i32 dst, src;
1590
1591 src = gen_load_fpr_F(dc, rs);
ba5f5179 1592 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1593
1594 gen(dst, src);
1595
1596 gen_store_fpr_F(dc, rd, dst);
1597}
1598
0c2e96c1 1599static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
61f17f6e
RH		 1600 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1601{
1602 TCGv_i32 dst, src1, src2;
1603
61f17f6e
RH		 1604 src1 = gen_load_fpr_F(dc, rs1);
1605 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1606 dst = gen_dest_fpr_F(dc);
61f17f6e 1607
ad75a51e
RH		 1608 gen(dst, tcg_env, src1, src2);
1609 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1610
61f17f6e
RH		 1611 gen_store_fpr_F(dc, rd, dst);
1612}
1613
1614#ifdef TARGET_SPARC64
0c2e96c1
RH		 1615static void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1616 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
61f17f6e
RH		 1617{
1618 TCGv_i32 dst, src1, src2;
1619
1620 src1 = gen_load_fpr_F(dc, rs1);
1621 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1622 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1623
1624 gen(dst, src1, src2);
1625
1626 gen_store_fpr_F(dc, rd, dst);
1627}
1628#endif
1629
0c2e96c1
RH		 1630static void gen_fop_DD(DisasContext *dc, int rd, int rs,
1631 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
61f17f6e
RH		 1632{
1633 TCGv_i64 dst, src;
1634
61f17f6e 1635 src = gen_load_fpr_D(dc, rs);
3886b8a3 1636 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1637
ad75a51e
RH		 1638 gen(dst, tcg_env, src);
1639 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1640
61f17f6e
RH		 1641 gen_store_fpr_D(dc, rd, dst);
1642}
1643
1644#ifdef TARGET_SPARC64
0c2e96c1
RH		 1645static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1646 void (*gen)(TCGv_i64, TCGv_i64))
61f17f6e
RH		 1647{
1648 TCGv_i64 dst, src;
1649
1650 src = gen_load_fpr_D(dc, rs);
3886b8a3 1651 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1652
1653 gen(dst, src);
1654
1655 gen_store_fpr_D(dc, rd, dst);
1656}
1657#endif
1658
0c2e96c1 1659static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
61f17f6e
RH		 1660 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1661{
1662 TCGv_i64 dst, src1, src2;
1663
61f17f6e
RH		 1664 src1 = gen_load_fpr_D(dc, rs1);
1665 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1666 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1667
ad75a51e
RH		 1668 gen(dst, tcg_env, src1, src2);
1669 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1670
61f17f6e
RH		 1671 gen_store_fpr_D(dc, rd, dst);
1672}
1673
1674#ifdef TARGET_SPARC64
0c2e96c1
RH		 1675static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1676 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
61f17f6e
RH		 1677{
1678 TCGv_i64 dst, src1, src2;
1679
1680 src1 = gen_load_fpr_D(dc, rs1);
1681 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1682 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1683
1684 gen(dst, src1, src2);
1685
1686 gen_store_fpr_D(dc, rd, dst);
1687}
f888300b 1688
0c2e96c1
RH		 1689static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1690 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
2dedf314
RH		 1691{
1692 TCGv_i64 dst, src1, src2;
1693
1694 src1 = gen_load_fpr_D(dc, rs1);
1695 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1696 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1697
1698 gen(dst, cpu_gsr, src1, src2);
1699
1700 gen_store_fpr_D(dc, rd, dst);
1701}
1702
0c2e96c1
RH		 1703static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1704 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
f888300b
RH		 1705{
1706 TCGv_i64 dst, src0, src1, src2;
1707
1708 src1 = gen_load_fpr_D(dc, rs1);
1709 src2 = gen_load_fpr_D(dc, rs2);
1710 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1711 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1712
1713 gen(dst, src0, src1, src2);
1714
1715 gen_store_fpr_D(dc, rd, dst);
1716}
61f17f6e
RH		 1717#endif
1718
0c2e96c1
RH		 1719static void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1720 void (*gen)(TCGv_ptr))
61f17f6e 1721{
61f17f6e
RH		 1722 gen_op_load_fpr_QT1(QFPREG(rs));
1723
ad75a51e
RH		 1724 gen(tcg_env);
1725 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1726
61f17f6e 1727 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1728 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1729}
1730
1731#ifdef TARGET_SPARC64
0c2e96c1
RH		 1732static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1733 void (*gen)(TCGv_ptr))
61f17f6e
RH		 1734{
1735 gen_op_load_fpr_QT1(QFPREG(rs));
1736
ad75a51e 1737 gen(tcg_env);
61f17f6e
RH		 1738
1739 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1740 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1741}
1742#endif
1743
0c2e96c1
RH		 1744static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1745 void (*gen)(TCGv_ptr))
61f17f6e 1746{
61f17f6e
RH		 1747 gen_op_load_fpr_QT0(QFPREG(rs1));
1748 gen_op_load_fpr_QT1(QFPREG(rs2));
1749
ad75a51e
RH		 1750 gen(tcg_env);
1751 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1752
61f17f6e 1753 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1754 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1755}
1756
0c2e96c1 1757static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
61f17f6e
RH		 1758 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1759{
1760 TCGv_i64 dst;
1761 TCGv_i32 src1, src2;
1762
61f17f6e
RH		 1763 src1 = gen_load_fpr_F(dc, rs1);
1764 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1765 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1766
ad75a51e
RH		 1767 gen(dst, tcg_env, src1, src2);
1768 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1769
61f17f6e
RH		 1770 gen_store_fpr_D(dc, rd, dst);
1771}
1772
0c2e96c1
RH		 1773static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1774 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
61f17f6e
RH		 1775{
1776 TCGv_i64 src1, src2;
1777
61f17f6e
RH		 1778 src1 = gen_load_fpr_D(dc, rs1);
1779 src2 = gen_load_fpr_D(dc, rs2);
1780
ad75a51e
RH		 1781 gen(tcg_env, src1, src2);
1782 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1783
61f17f6e 1784 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1785 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1786}
1787
1788#ifdef TARGET_SPARC64
0c2e96c1
RH		 1789static void gen_fop_DF(DisasContext *dc, int rd, int rs,
1790 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
61f17f6e
RH		 1791{
1792 TCGv_i64 dst;
1793 TCGv_i32 src;
1794
61f17f6e 1795 src = gen_load_fpr_F(dc, rs);
3886b8a3 1796 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1797
ad75a51e
RH		 1798 gen(dst, tcg_env, src);
1799 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1800
61f17f6e
RH		 1801 gen_store_fpr_D(dc, rd, dst);
1802}
1803#endif
1804
0c2e96c1
RH		 1805static void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1806 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
61f17f6e
RH		 1807{
1808 TCGv_i64 dst;
1809 TCGv_i32 src;
1810
1811 src = gen_load_fpr_F(dc, rs);
3886b8a3 1812 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1813
ad75a51e 1814 gen(dst, tcg_env, src);
61f17f6e
RH		 1815
1816 gen_store_fpr_D(dc, rd, dst);
1817}
1818
0c2e96c1
RH		 1819static void gen_fop_FD(DisasContext *dc, int rd, int rs,
1820 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
61f17f6e
RH		 1821{
1822 TCGv_i32 dst;
1823 TCGv_i64 src;
1824
61f17f6e 1825 src = gen_load_fpr_D(dc, rs);
ba5f5179 1826 dst = gen_dest_fpr_F(dc);
61f17f6e 1827
ad75a51e
RH		 1828 gen(dst, tcg_env, src);
1829 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1830
61f17f6e
RH		 1831 gen_store_fpr_F(dc, rd, dst);
1832}
1833
0c2e96c1
RH		 1834static void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1835 void (*gen)(TCGv_i32, TCGv_ptr))
61f17f6e
RH		 1836{
1837 TCGv_i32 dst;
1838
61f17f6e 1839 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1840 dst = gen_dest_fpr_F(dc);
61f17f6e 1841
ad75a51e
RH		 1842 gen(dst, tcg_env);
1843 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1844
61f17f6e
RH		 1845 gen_store_fpr_F(dc, rd, dst);
1846}
1847
0c2e96c1
RH		 1848static void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1849 void (*gen)(TCGv_i64, TCGv_ptr))
61f17f6e
RH		 1850{
1851 TCGv_i64 dst;
1852
61f17f6e 1853 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1854 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1855
ad75a51e
RH		 1856 gen(dst, tcg_env);
1857 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1858
61f17f6e
RH		 1859 gen_store_fpr_D(dc, rd, dst);
1860}
1861
0c2e96c1
RH		 1862static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1863 void (*gen)(TCGv_ptr, TCGv_i32))
61f17f6e
RH		 1864{
1865 TCGv_i32 src;
1866
1867 src = gen_load_fpr_F(dc, rs);
1868
ad75a51e 1869 gen(tcg_env, src);
61f17f6e
RH		 1870
1871 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1872 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1873}
1874
0c2e96c1
RH		 1875static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1876 void (*gen)(TCGv_ptr, TCGv_i64))
61f17f6e
RH		 1877{
1878 TCGv_i64 src;
1879
1880 src = gen_load_fpr_D(dc, rs);
1881
ad75a51e 1882 gen(tcg_env, src);
61f17f6e
RH		 1883
1884 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1885 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1886}
1887
4fb554bc 1888static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
14776ab5 1889 TCGv addr, int mmu_idx, MemOp memop)
4fb554bc 1890{
4fb554bc 1891 gen_address_mask(dc, addr);
316b6783 1892 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN);
4fb554bc
RH		 1893}
1894
fbb4bbb6
RH		 1895static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
1896{
00ab7e61 1897 TCGv m1 = tcg_constant_tl(0xff);
fbb4bbb6 1898 gen_address_mask(dc, addr);
da1bcae6 1899 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
fbb4bbb6
RH		 1900}
1901
1a2fb1c0 1902/* asi moves */
7ec1e5ea
RH		 1903typedef enum {
1904 GET_ASI_HELPER,
1905 GET_ASI_EXCP,
f0913be0 1906 GET_ASI_DIRECT,
e4dc0052 1907 GET_ASI_DTWINX,
ca5ce572
RH		 1908 GET_ASI_BLOCK,
1909 GET_ASI_SHORT,
34810610
RH		 1910 GET_ASI_BCOPY,
1911 GET_ASI_BFILL,
7ec1e5ea
RH		 1912} ASIType;
1913
1914typedef struct {
1915 ASIType type;
a6d567e5 1916 int asi;
f0913be0 1917 int mem_idx;
14776ab5 1918 MemOp memop;
7ec1e5ea 1919} DisasASI;
1a2fb1c0 1920
811cc0b0
RH		 1921/*
1922 * Build DisasASI.
1923 * For asi == -1, treat as non-asi.
1924 * For ask == -2, treat as immediate offset (v8 error, v9 %asi).
1925 */
1926static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop)
7ec1e5ea 1927{
7ec1e5ea 1928 ASIType type = GET_ASI_HELPER;
f0913be0 1929 int mem_idx = dc->mem_idx;
7ec1e5ea 1930
811cc0b0
RH		 1931 if (asi == -1) {
1932 /* Artificial "non-asi" case. */
1933 type = GET_ASI_DIRECT;
1934 goto done;
1935 }
1936
7ec1e5ea
RH		 1937#ifndef TARGET_SPARC64
1938 /* Before v9, all asis are immediate and privileged. */
811cc0b0 1939 if (asi < 0) {
22e70060 1940 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 1941 type = GET_ASI_EXCP;
1942 } else if (supervisor(dc)
1943 /* Note that LEON accepts ASI_USERDATA in user mode, for
1944 use with CASA. Also note that previous versions of
0cc1f4bf
RH		 1945 QEMU allowed (and old versions of gcc emitted) ASI_P
1946 for LEON, which is incorrect. */
1947 || (asi == ASI_USERDATA
7ec1e5ea 1948 && (dc->def->features & CPU_FEATURE_CASA))) {
f0913be0
RH		 1949 switch (asi) {
1950 case ASI_USERDATA: /* User data access */
1951 mem_idx = MMU_USER_IDX;
1952 type = GET_ASI_DIRECT;
1953 break;
1954 case ASI_KERNELDATA: /* Supervisor data access */
1955 mem_idx = MMU_KERNEL_IDX;
1956 type = GET_ASI_DIRECT;
1957 break;
7f87c905
RH		 1958 case ASI_M_BYPASS: /* MMU passthrough */
1959 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1960 mem_idx = MMU_PHYS_IDX;
1961 type = GET_ASI_DIRECT;
1962 break;
34810610
RH		 1963 case ASI_M_BCOPY: /* Block copy, sta access */
1964 mem_idx = MMU_KERNEL_IDX;
1965 type = GET_ASI_BCOPY;
1966 break;
1967 case ASI_M_BFILL: /* Block fill, stda access */
1968 mem_idx = MMU_KERNEL_IDX;
1969 type = GET_ASI_BFILL;
1970 break;
f0913be0 1971 }
6e10f37c
KF		 1972
1973 /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the
1974 * permissions check in get_physical_address(..).
1975 */
1976 mem_idx = (dc->mem_idx == MMU_PHYS_IDX) ? MMU_PHYS_IDX : mem_idx;
1a2fb1c0 1977 } else {
7ec1e5ea
RH		 1978 gen_exception(dc, TT_PRIV_INSN);
1979 type = GET_ASI_EXCP;
1980 }
1981#else
811cc0b0 1982 if (asi < 0) {
7ec1e5ea 1983 asi = dc->asi;
1a2fb1c0 1984 }
f0913be0
RH		 1985 /* With v9, all asis below 0x80 are privileged. */
1986 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
1987 down that bit into DisasContext. For the moment that's ok,
1988 since the direct implementations below doesn't have any ASIs
1989 in the restricted [0x30, 0x7f] range, and the check will be
1990 done properly in the helper. */
1991 if (!supervisor(dc) && asi < 0x80) {
1992 gen_exception(dc, TT_PRIV_ACT);
1993 type = GET_ASI_EXCP;
1994 } else {
1995 switch (asi) {
7f87c905
RH		 1996 case ASI_REAL: /* Bypass */
1997 case ASI_REAL_IO: /* Bypass, non-cacheable */
1998 case ASI_REAL_L: /* Bypass LE */
1999 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2000 case ASI_TWINX_REAL: /* Real address, twinx */
2001 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
34a6e13d
RH		 2002 case ASI_QUAD_LDD_PHYS:
2003 case ASI_QUAD_LDD_PHYS_L:
7f87c905
RH		 2004 mem_idx = MMU_PHYS_IDX;
2005 break;
f0913be0
RH		 2006 case ASI_N: /* Nucleus */
2007 case ASI_NL: /* Nucleus LE */
e4dc0052
RH		 2008 case ASI_TWINX_N:
2009 case ASI_TWINX_NL:
34a6e13d
RH		 2010 case ASI_NUCLEUS_QUAD_LDD:
2011 case ASI_NUCLEUS_QUAD_LDD_L:
9a10756d 2012 if (hypervisor(dc)) {
84f8f587 2013 mem_idx = MMU_PHYS_IDX;
9a10756d
AT		 2014 } else {
2015 mem_idx = MMU_NUCLEUS_IDX;
2016 }
f0913be0
RH		 2017 break;
2018 case ASI_AIUP: /* As if user primary */
2019 case ASI_AIUPL: /* As if user primary LE */
e4dc0052
RH		 2020 case ASI_TWINX_AIUP:
2021 case ASI_TWINX_AIUP_L:
ca5ce572
RH		 2022 case ASI_BLK_AIUP_4V:
2023 case ASI_BLK_AIUP_L_4V:
2024 case ASI_BLK_AIUP:
2025 case ASI_BLK_AIUPL:
f0913be0
RH		 2026 mem_idx = MMU_USER_IDX;
2027 break;
2028 case ASI_AIUS: /* As if user secondary */
2029 case ASI_AIUSL: /* As if user secondary LE */
e4dc0052
RH		 2030 case ASI_TWINX_AIUS:
2031 case ASI_TWINX_AIUS_L:
ca5ce572
RH		 2032 case ASI_BLK_AIUS_4V:
2033 case ASI_BLK_AIUS_L_4V:
2034 case ASI_BLK_AIUS:
2035 case ASI_BLK_AIUSL:
f0913be0
RH		 2036 mem_idx = MMU_USER_SECONDARY_IDX;
2037 break;
2038 case ASI_S: /* Secondary */
2039 case ASI_SL: /* Secondary LE */
e4dc0052
RH		 2040 case ASI_TWINX_S:
2041 case ASI_TWINX_SL:
ca5ce572
RH		 2042 case ASI_BLK_COMMIT_S:
2043 case ASI_BLK_S:
2044 case ASI_BLK_SL:
2045 case ASI_FL8_S:
2046 case ASI_FL8_SL:
2047 case ASI_FL16_S:
2048 case ASI_FL16_SL:
f0913be0
RH		 2049 if (mem_idx == MMU_USER_IDX) {
2050 mem_idx = MMU_USER_SECONDARY_IDX;
2051 } else if (mem_idx == MMU_KERNEL_IDX) {
2052 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2053 }
2054 break;
2055 case ASI_P: /* Primary */
2056 case ASI_PL: /* Primary LE */
e4dc0052
RH		 2057 case ASI_TWINX_P:
2058 case ASI_TWINX_PL:
ca5ce572
RH		 2059 case ASI_BLK_COMMIT_P:
2060 case ASI_BLK_P:
2061 case ASI_BLK_PL:
2062 case ASI_FL8_P:
2063 case ASI_FL8_PL:
2064 case ASI_FL16_P:
2065 case ASI_FL16_PL:
f0913be0
RH		 2066 break;
2067 }
2068 switch (asi) {
7f87c905
RH		 2069 case ASI_REAL:
2070 case ASI_REAL_IO:
2071 case ASI_REAL_L:
2072 case ASI_REAL_IO_L:
f0913be0
RH		 2073 case ASI_N:
2074 case ASI_NL:
2075 case ASI_AIUP:
2076 case ASI_AIUPL:
2077 case ASI_AIUS:
2078 case ASI_AIUSL:
2079 case ASI_S:
2080 case ASI_SL:
2081 case ASI_P:
2082 case ASI_PL:
2083 type = GET_ASI_DIRECT;
2084 break;
7f87c905
RH		 2085 case ASI_TWINX_REAL:
2086 case ASI_TWINX_REAL_L:
e4dc0052
RH		 2087 case ASI_TWINX_N:
2088 case ASI_TWINX_NL:
2089 case ASI_TWINX_AIUP:
2090 case ASI_TWINX_AIUP_L:
2091 case ASI_TWINX_AIUS:
2092 case ASI_TWINX_AIUS_L:
2093 case ASI_TWINX_P:
2094 case ASI_TWINX_PL:
2095 case ASI_TWINX_S:
2096 case ASI_TWINX_SL:
34a6e13d
RH		 2097 case ASI_QUAD_LDD_PHYS:
2098 case ASI_QUAD_LDD_PHYS_L:
2099 case ASI_NUCLEUS_QUAD_LDD:
2100 case ASI_NUCLEUS_QUAD_LDD_L:
e4dc0052
RH		 2101 type = GET_ASI_DTWINX;
2102 break;
ca5ce572
RH		 2103 case ASI_BLK_COMMIT_P:
2104 case ASI_BLK_COMMIT_S:
2105 case ASI_BLK_AIUP_4V:
2106 case ASI_BLK_AIUP_L_4V:
2107 case ASI_BLK_AIUP:
2108 case ASI_BLK_AIUPL:
2109 case ASI_BLK_AIUS_4V:
2110 case ASI_BLK_AIUS_L_4V:
2111 case ASI_BLK_AIUS:
2112 case ASI_BLK_AIUSL:
2113 case ASI_BLK_S:
2114 case ASI_BLK_SL:
2115 case ASI_BLK_P:
2116 case ASI_BLK_PL:
2117 type = GET_ASI_BLOCK;
2118 break;
2119 case ASI_FL8_S:
2120 case ASI_FL8_SL:
2121 case ASI_FL8_P:
2122 case ASI_FL8_PL:
2123 memop = MO_UB;
2124 type = GET_ASI_SHORT;
2125 break;
2126 case ASI_FL16_S:
2127 case ASI_FL16_SL:
2128 case ASI_FL16_P:
2129 case ASI_FL16_PL:
2130 memop = MO_TEUW;
2131 type = GET_ASI_SHORT;
2132 break;
f0913be0
RH		 2133 }
2134 /* The little-endian asis all have bit 3 set. */
2135 if (asi & 8) {
2136 memop ^= MO_BSWAP;
2137 }
2138 }
7ec1e5ea
RH		 2139#endif
2140
811cc0b0 2141 done:
f0913be0 2142 return (DisasASI){ type, asi, mem_idx, memop };
0425bee5
BS		 2143}
2144
811cc0b0
RH		 2145static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
2146{
2147 int asi = IS_IMM ? -2 : GET_FIELD(insn, 19, 26);
2148 return resolve_asi(dc, asi, memop);
2149}
2150
a76779ee
RH		 2151#if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2152static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a,
2153 TCGv_i32 asi, TCGv_i32 mop)
2154{
2155 g_assert_not_reached();
2156}
2157
2158static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r,
2159 TCGv_i32 asi, TCGv_i32 mop)
2160{
2161 g_assert_not_reached();
2162}
2163#endif
2164
2165static void __attribute__((unused))
2166gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop)
0425bee5 2167{
f0913be0 2168 DisasASI da = get_asi(dc, insn, memop);
0425bee5 2169
7ec1e5ea
RH		 2170 switch (da.type) {
2171 case GET_ASI_EXCP:
2172 break;
e4dc0052
RH		 2173 case GET_ASI_DTWINX: /* Reserved for ldda. */
2174 gen_exception(dc, TT_ILL_INSN);
2175 break;
f0913be0
RH		 2176 case GET_ASI_DIRECT:
2177 gen_address_mask(dc, addr);
316b6783 2178 tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN);
f0913be0 2179 break;
7ec1e5ea
RH		 2180 default:
2181 {
00ab7e61 2182 TCGv_i32 r_asi = tcg_constant_i32(da.asi);
316b6783 2183 TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
7ec1e5ea
RH		 2184
2185 save_state(dc);
22e70060 2186#ifdef TARGET_SPARC64
ad75a51e 2187 gen_helper_ld_asi(dst, tcg_env, addr, r_asi, r_mop);
22e70060 2188#else
7ec1e5ea
RH		 2189 {
2190 TCGv_i64 t64 = tcg_temp_new_i64();
ad75a51e 2191 gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
7ec1e5ea 2192 tcg_gen_trunc_i64_tl(dst, t64);
7ec1e5ea 2193 }
22e70060 2194#endif
7ec1e5ea
RH		 2195 }
2196 break;
2197 }
1a2fb1c0
BS		 2198}
2199
a76779ee
RH		 2200static void __attribute__((unused))
2201gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
1a2fb1c0 2202{
f0913be0 2203 DisasASI da = get_asi(dc, insn, memop);
1a2fb1c0 2204
7ec1e5ea
RH		 2205 switch (da.type) {
2206 case GET_ASI_EXCP:
2207 break;
e4dc0052 2208 case GET_ASI_DTWINX: /* Reserved for stda. */
3390537b 2209#ifndef TARGET_SPARC64
e4dc0052
RH		 2210 gen_exception(dc, TT_ILL_INSN);
2211 break;
3390537b
AT		 2212#else
2213 if (!(dc->def->features & CPU_FEATURE_HYPV)) {
2214 /* Pre OpenSPARC CPUs don't have these */
2215 gen_exception(dc, TT_ILL_INSN);
2216 return;
2217 }
2218 /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
2219 * are ST_BLKINIT_ ASIs */
3390537b 2220#endif
fc0cd867 2221 /* fall through */
f0913be0
RH		 2222 case GET_ASI_DIRECT:
2223 gen_address_mask(dc, addr);
316b6783 2224 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN);
f0913be0 2225 break;
34810610
RH		 2226#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
2227 case GET_ASI_BCOPY:
2228 /* Copy 32 bytes from the address in SRC to ADDR. */
2229 /* ??? The original qemu code suggests 4-byte alignment, dropping
2230 the low bits, but the only place I can see this used is in the
2231 Linux kernel with 32 byte alignment, which would make more sense
2232 as a cacheline-style operation. */
2233 {
2234 TCGv saddr = tcg_temp_new();
2235 TCGv daddr = tcg_temp_new();
00ab7e61 2236 TCGv four = tcg_constant_tl(4);
34810610
RH		 2237 TCGv_i32 tmp = tcg_temp_new_i32();
2238 int i;
2239
2240 tcg_gen_andi_tl(saddr, src, -4);
2241 tcg_gen_andi_tl(daddr, addr, -4);
2242 for (i = 0; i < 32; i += 4) {
2243 /* Since the loads and stores are paired, allow the
2244 copy to happen in the host endianness. */
2245 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
2246 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
2247 tcg_gen_add_tl(saddr, saddr, four);
2248 tcg_gen_add_tl(daddr, daddr, four);
2249 }
34810610
RH		 2250 }
2251 break;
2252#endif
7ec1e5ea
RH		 2253 default:
2254 {
00ab7e61 2255 TCGv_i32 r_asi = tcg_constant_i32(da.asi);
316b6783 2256 TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
7ec1e5ea
RH		 2257
2258 save_state(dc);
22e70060 2259#ifdef TARGET_SPARC64
ad75a51e 2260 gen_helper_st_asi(tcg_env, addr, src, r_asi, r_mop);
22e70060 2261#else
7ec1e5ea
RH		 2262 {
2263 TCGv_i64 t64 = tcg_temp_new_i64();
2264 tcg_gen_extu_tl_i64(t64, src);
ad75a51e 2265 gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
7ec1e5ea 2266 }
22e70060 2267#endif
7ec1e5ea
RH		 2268
2269 /* A write to a TLB register may alter page maps. End the TB. */
2270 dc->npc = DYNAMIC_PC;
2271 }
2272 break;
2273 }
1a2fb1c0
BS		 2274}
2275
a76779ee
RH		 2276static void __attribute__((unused))
2277gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2278{
f0913be0 2279 DisasASI da = get_asi(dc, insn, MO_TEUL);
22e70060 2280
7ec1e5ea
RH		 2281 switch (da.type) {
2282 case GET_ASI_EXCP:
2283 break;
4fb554bc
RH		 2284 case GET_ASI_DIRECT:
2285 gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
2286 break;
7ec1e5ea 2287 default:
4fb554bc
RH		 2288 /* ??? Should be DAE_invalid_asi. */
2289 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2290 break;
2291 }
1a2fb1c0
BS		 2292}
2293
a76779ee
RH		 2294static void __attribute__((unused))
2295gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
22e70060 2296{
f0913be0 2297 DisasASI da = get_asi(dc, insn, MO_TEUL);
5a7267b6 2298 TCGv oldv;
22e70060 2299
7268adeb
RH		 2300 switch (da.type) {
2301 case GET_ASI_EXCP:
7ec1e5ea 2302 return;
7268adeb 2303 case GET_ASI_DIRECT:
7268adeb 2304 oldv = tcg_temp_new();
5a7267b6 2305 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
316b6783 2306 da.mem_idx, da.memop | MO_ALIGN);
7268adeb 2307 gen_store_gpr(dc, rd, oldv);
7268adeb
RH		 2308 break;
2309 default:
2310 /* ??? Should be DAE_invalid_asi. */
2311 gen_exception(dc, TT_DATA_ACCESS);
2312 break;
7ec1e5ea 2313 }
22e70060
RH		 2314}
2315
a76779ee
RH		 2316static void __attribute__((unused))
2317gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
22e70060 2318{
f0913be0 2319 DisasASI da = get_asi(dc, insn, MO_UB);
22e70060 2320
7ec1e5ea
RH		 2321 switch (da.type) {
2322 case GET_ASI_EXCP:
2323 break;
fbb4bbb6
RH		 2324 case GET_ASI_DIRECT:
2325 gen_ldstub(dc, dst, addr, da.mem_idx);
2326 break;
7ec1e5ea 2327 default:
3db010c3
RH		 2328 /* ??? In theory, this should be raise DAE_invalid_asi.
2329 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
af00be49 2330 if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
ad75a51e 2331 gen_helper_exit_atomic(tcg_env);
3db010c3 2332 } else {
00ab7e61
RH		 2333 TCGv_i32 r_asi = tcg_constant_i32(da.asi);
2334 TCGv_i32 r_mop = tcg_constant_i32(MO_UB);
3db010c3
RH		 2335 TCGv_i64 s64, t64;
2336
2337 save_state(dc);
2338 t64 = tcg_temp_new_i64();
ad75a51e 2339 gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
3db010c3 2340
00ab7e61 2341 s64 = tcg_constant_i64(0xff);
ad75a51e 2342 gen_helper_st_asi(tcg_env, addr, s64, r_asi, r_mop);
3db010c3
RH		 2343
2344 tcg_gen_trunc_i64_tl(dst, t64);
3db010c3
RH		 2345
2346 /* End the TB. */
2347 dc->npc = DYNAMIC_PC;
2348 }
7ec1e5ea
RH		 2349 break;
2350 }
22e70060 2351}
22e70060 2352
a76779ee
RH		 2353static void __attribute__((unused))
2354gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
1a2fb1c0 2355{
fc313c64 2356 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
7705091c 2357 TCGv_i32 d32;
cb21b4da 2358 TCGv_i64 d64;
1a2fb1c0 2359
7ec1e5ea
RH		 2360 switch (da.type) {
2361 case GET_ASI_EXCP:
2362 break;
7705091c
RH		 2363
2364 case GET_ASI_DIRECT:
2365 gen_address_mask(dc, addr);
2366 switch (size) {
2367 case 4:
2368 d32 = gen_dest_fpr_F(dc);
316b6783 2369 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
7705091c
RH		 2370 gen_store_fpr_F(dc, rd, d32);
2371 break;
2372 case 8:
cb21b4da
RH		 2373 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2374 da.memop | MO_ALIGN_4);
7705091c
RH		 2375 break;
2376 case 16:
cb21b4da
RH		 2377 d64 = tcg_temp_new_i64();
2378 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
7705091c 2379 tcg_gen_addi_tl(addr, addr, 8);
cb21b4da
RH		 2380 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2381 da.memop | MO_ALIGN_4);
2382 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
7705091c
RH		 2383 break;
2384 default:
2385 g_assert_not_reached();
2386 }
2387 break;
2388
ca5ce572
RH		 2389 case GET_ASI_BLOCK:
2390 /* Valid for lddfa on aligned registers only. */
2391 if (size == 8 && (rd & 7) == 0) {
14776ab5 2392 MemOp memop;
ca5ce572
RH		 2393 TCGv eight;
2394 int i;
2395
ca5ce572
RH		 2396 gen_address_mask(dc, addr);
2397
80883227
RH		 2398 /* The first operation checks required alignment. */
2399 memop = da.memop | MO_ALIGN_64;
00ab7e61 2400 eight = tcg_constant_tl(8);
ca5ce572
RH		 2401 for (i = 0; ; ++i) {
2402 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2403 da.mem_idx, memop);
ca5ce572
RH		 2404 if (i == 7) {
2405 break;
2406 }
2407 tcg_gen_add_tl(addr, addr, eight);
80883227 2408 memop = da.memop;
ca5ce572 2409 }
ca5ce572
RH		 2410 } else {
2411 gen_exception(dc, TT_ILL_INSN);
2412 }
2413 break;
2414
2415 case GET_ASI_SHORT:
2416 /* Valid for lddfa only. */
2417 if (size == 8) {
2418 gen_address_mask(dc, addr);
316b6783
RH		 2419 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2420 da.memop | MO_ALIGN);
ca5ce572
RH		 2421 } else {
2422 gen_exception(dc, TT_ILL_INSN);
2423 }
2424 break;
2425
7ec1e5ea
RH		 2426 default:
2427 {
00ab7e61 2428 TCGv_i32 r_asi = tcg_constant_i32(da.asi);
316b6783 2429 TCGv_i32 r_mop = tcg_constant_i32(da.memop | MO_ALIGN);
7ec1e5ea
RH		 2430
2431 save_state(dc);
f2fe396f
RH		 2432 /* According to the table in the UA2011 manual, the only
2433 other asis that are valid for ldfa/lddfa/ldqfa are
2434 the NO_FAULT asis. We still need a helper for these,
2435 but we can just use the integer asi helper for them. */
2436 switch (size) {
2437 case 4:
cb21b4da 2438 d64 = tcg_temp_new_i64();
ad75a51e 2439 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
cb21b4da
RH		 2440 d32 = gen_dest_fpr_F(dc);
2441 tcg_gen_extrl_i64_i32(d32, d64);
cb21b4da 2442 gen_store_fpr_F(dc, rd, d32);
f2fe396f
RH		 2443 break;
2444 case 8:
ad75a51e 2445 gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r_mop);
f2fe396f
RH		 2446 break;
2447 case 16:
cb21b4da 2448 d64 = tcg_temp_new_i64();
ad75a51e 2449 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
f2fe396f 2450 tcg_gen_addi_tl(addr, addr, 8);
ad75a51e 2451 gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r_mop);
cb21b4da 2452 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
f2fe396f
RH		 2453 break;
2454 default:
2455 g_assert_not_reached();
2456 }
7ec1e5ea
RH		 2457 }
2458 break;
2459 }
1a2fb1c0
BS		 2460}
2461
a76779ee
RH		 2462static void __attribute__((unused))
2463gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
1a2fb1c0 2464{
fc313c64 2465 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
7705091c 2466 TCGv_i32 d32;
1a2fb1c0 2467
7ec1e5ea
RH		 2468 switch (da.type) {
2469 case GET_ASI_EXCP:
2470 break;
7705091c
RH		 2471
2472 case GET_ASI_DIRECT:
2473 gen_address_mask(dc, addr);
2474 switch (size) {
2475 case 4:
2476 d32 = gen_load_fpr_F(dc, rd);
316b6783 2477 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
7705091c
RH		 2478 break;
2479 case 8:
cb21b4da
RH		 2480 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2481 da.memop | MO_ALIGN_4);
7705091c
RH		 2482 break;
2483 case 16:
cb21b4da
RH		 2484 /* Only 4-byte alignment required. However, it is legal for the
2485 cpu to signal the alignment fault, and the OS trap handler is
2486 required to fix it up. Requiring 16-byte alignment here avoids
2487 having to probe the second page before performing the first
2488 write. */
f939ffe5
RH		 2489 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2490 da.memop | MO_ALIGN_16);
7705091c
RH		 2491 tcg_gen_addi_tl(addr, addr, 8);
2492 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2493 break;
2494 default:
2495 g_assert_not_reached();
2496 }
2497 break;
2498
ca5ce572
RH		 2499 case GET_ASI_BLOCK:
2500 /* Valid for stdfa on aligned registers only. */
2501 if (size == 8 && (rd & 7) == 0) {
14776ab5 2502 MemOp memop;
ca5ce572
RH		 2503 TCGv eight;
2504 int i;
2505
ca5ce572
RH		 2506 gen_address_mask(dc, addr);
2507
80883227
RH		 2508 /* The first operation checks required alignment. */
2509 memop = da.memop | MO_ALIGN_64;
00ab7e61 2510 eight = tcg_constant_tl(8);
ca5ce572
RH		 2511 for (i = 0; ; ++i) {
2512 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2513 da.mem_idx, memop);
ca5ce572
RH		 2514 if (i == 7) {
2515 break;
2516 }
2517 tcg_gen_add_tl(addr, addr, eight);
80883227 2518 memop = da.memop;
ca5ce572 2519 }
ca5ce572
RH		 2520 } else {
2521 gen_exception(dc, TT_ILL_INSN);
2522 }
2523 break;
2524
2525 case GET_ASI_SHORT:
2526 /* Valid for stdfa only. */
2527 if (size == 8) {
2528 gen_address_mask(dc, addr);
316b6783
RH		 2529 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2530 da.memop | MO_ALIGN);
ca5ce572
RH		 2531 } else {
2532 gen_exception(dc, TT_ILL_INSN);
2533 }
2534 break;
2535
7ec1e5ea 2536 default:
f2fe396f
RH		 2537 /* According to the table in the UA2011 manual, the only
2538 other asis that are valid for ldfa/lddfa/ldqfa are
2539 the PST* asis, which aren't currently handled. */
2540 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2541 break;
2542 }
1a2fb1c0
BS		 2543}
2544
a76779ee
RH		 2545static void __attribute__((unused))
2546gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2547{
fc313c64 2548 DisasASI da = get_asi(dc, insn, MO_TEUQ);
a76779ee
RH		 2549 TCGv hi = gen_dest_gpr(dc, rd);
2550 TCGv lo = gen_dest_gpr(dc, rd + 1);
1a2fb1c0 2551
7ec1e5ea
RH		 2552 switch (da.type) {
2553 case GET_ASI_EXCP:
e4dc0052
RH		 2554 return;
2555
2556 case GET_ASI_DTWINX:
a76779ee 2557 assert(TARGET_LONG_BITS == 64);
e4dc0052 2558 gen_address_mask(dc, addr);
a76779ee 2559 tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052 2560 tcg_gen_addi_tl(addr, addr, 8);
a76779ee 2561 tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop);
7ec1e5ea 2562 break;
e4dc0052
RH		 2563
2564 case GET_ASI_DIRECT:
2565 {
2566 TCGv_i64 tmp = tcg_temp_new_i64();
2567
2568 gen_address_mask(dc, addr);
316b6783 2569 tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN);
e4dc0052
RH		 2570
2571 /* Note that LE ldda acts as if each 32-bit register
2572 result is byte swapped. Having just performed one
2573 64-bit bswap, we need now to swap the writebacks. */
2574 if ((da.memop & MO_BSWAP) == MO_TE) {
a76779ee 2575 tcg_gen_extr_i64_tl(lo, hi, tmp);
e4dc0052 2576 } else {
a76779ee 2577 tcg_gen_extr_i64_tl(hi, lo, tmp);
e4dc0052 2578 }
e4dc0052
RH		 2579 }
2580 break;
2581
7ec1e5ea 2582 default:
918d9a2c
RH		 2583 /* ??? In theory we've handled all of the ASIs that are valid
2584 for ldda, and this should raise DAE_invalid_asi. However,
2585 real hardware allows others. This can be seen with e.g.
2586 FreeBSD 10.3 wrt ASI_IC_TAG. */
7ec1e5ea 2587 {
00ab7e61
RH		 2588 TCGv_i32 r_asi = tcg_constant_i32(da.asi);
2589 TCGv_i32 r_mop = tcg_constant_i32(da.memop);
918d9a2c 2590 TCGv_i64 tmp = tcg_temp_new_i64();
7ec1e5ea
RH		 2591
2592 save_state(dc);
ad75a51e 2593 gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop);
3f4288eb 2594
918d9a2c
RH		 2595 /* See above. */
2596 if ((da.memop & MO_BSWAP) == MO_TE) {
a76779ee 2597 tcg_gen_extr_i64_tl(lo, hi, tmp);
918d9a2c 2598 } else {
a76779ee 2599 tcg_gen_extr_i64_tl(hi, lo, tmp);
918d9a2c 2600 }
7ec1e5ea
RH		 2601 }
2602 break;
2603 }
e4dc0052
RH		 2604
2605 gen_store_gpr(dc, rd, hi);
2606 gen_store_gpr(dc, rd + 1, lo);
0425bee5
BS		 2607}
2608
a76779ee
RH		 2609static void __attribute__((unused))
2610gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
0425bee5 2611{
fc313c64 2612 DisasASI da = get_asi(dc, insn, MO_TEUQ);
c7785e16 2613 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2614
7ec1e5ea
RH		 2615 switch (da.type) {
2616 case GET_ASI_EXCP:
2617 break;
e4dc0052
RH		 2618
2619 case GET_ASI_DTWINX:
a76779ee 2620 assert(TARGET_LONG_BITS == 64);
e4dc0052 2621 gen_address_mask(dc, addr);
a76779ee 2622 tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052 2623 tcg_gen_addi_tl(addr, addr, 8);
a76779ee 2624 tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop);
e4dc0052
RH		 2625 break;
2626
2627 case GET_ASI_DIRECT:
2628 {
2629 TCGv_i64 t64 = tcg_temp_new_i64();
2630
2631 /* Note that LE stda acts as if each 32-bit register result is
2632 byte swapped. We will perform one 64-bit LE store, so now
2633 we must swap the order of the construction. */
2634 if ((da.memop & MO_BSWAP) == MO_TE) {
a76779ee 2635 tcg_gen_concat_tl_i64(t64, lo, hi);
e4dc0052 2636 } else {
a76779ee 2637 tcg_gen_concat_tl_i64(t64, hi, lo);
e4dc0052
RH		 2638 }
2639 gen_address_mask(dc, addr);
316b6783 2640 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
e4dc0052
RH		 2641 }
2642 break;
2643
a76779ee
RH		 2644 case GET_ASI_BFILL:
2645 assert(TARGET_LONG_BITS == 32);
2646 /* Store 32 bytes of T64 to ADDR. */
2647 /* ??? The original qemu code suggests 8-byte alignment, dropping
2648 the low bits, but the only place I can see this used is in the
2649 Linux kernel with 32 byte alignment, which would make more sense
2650 as a cacheline-style operation. */
2651 {
2652 TCGv_i64 t64 = tcg_temp_new_i64();
2653 TCGv d_addr = tcg_temp_new();
2654 TCGv eight = tcg_constant_tl(8);
2655 int i;
2656
2657 tcg_gen_concat_tl_i64(t64, lo, hi);
2658 tcg_gen_andi_tl(d_addr, addr, -8);
2659 for (i = 0; i < 32; i += 8) {
2660 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
2661 tcg_gen_add_tl(d_addr, d_addr, eight);
2662 }
2663 }
2664 break;
2665
7ec1e5ea 2666 default:
918d9a2c
RH		 2667 /* ??? In theory we've handled all of the ASIs that are valid
2668 for stda, and this should raise DAE_invalid_asi. */
7ec1e5ea 2669 {
00ab7e61
RH		 2670 TCGv_i32 r_asi = tcg_constant_i32(da.asi);
2671 TCGv_i32 r_mop = tcg_constant_i32(da.memop);
918d9a2c 2672 TCGv_i64 t64 = tcg_temp_new_i64();
7ec1e5ea 2673
918d9a2c
RH		 2674 /* See above. */
2675 if ((da.memop & MO_BSWAP) == MO_TE) {
a76779ee 2676 tcg_gen_concat_tl_i64(t64, lo, hi);
918d9a2c 2677 } else {
a76779ee 2678 tcg_gen_concat_tl_i64(t64, hi, lo);
918d9a2c 2679 }
7ec1e5ea 2680
918d9a2c 2681 save_state(dc);
ad75a51e 2682 gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
7ec1e5ea
RH		 2683 }
2684 break;
2685 }
1a2fb1c0
BS		 2686}
2687
a76779ee
RH		 2688static void __attribute__((unused))
2689gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
1a2fb1c0 2690{
fc313c64 2691 DisasASI da = get_asi(dc, insn, MO_TEUQ);
5a7267b6 2692 TCGv oldv;
1a2fb1c0 2693
7268adeb
RH		 2694 switch (da.type) {
2695 case GET_ASI_EXCP:
7ec1e5ea 2696 return;
7268adeb
RH		 2697 case GET_ASI_DIRECT:
2698 oldv = tcg_temp_new();
5a7267b6 2699 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
316b6783 2700 da.mem_idx, da.memop | MO_ALIGN);
7268adeb 2701 gen_store_gpr(dc, rd, oldv);
7268adeb
RH		 2702 break;
2703 default:
2704 /* ??? Should be DAE_invalid_asi. */
2705 gen_exception(dc, TT_DATA_ACCESS);
2706 break;
2707 }
1a2fb1c0
BS		 2708}
2709
9d1d4e34 2710static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2711{
9d1d4e34
RH		 2712 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2713 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2714}
2715
8194f35a 2716#ifdef TARGET_SPARC64
7e480893
RH		 2717static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2718{
2719 TCGv_i32 c32, zero, dst, s1, s2;
2720
2721 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2722 or fold the comparison down to 32 bits and use movcond_i32. Choose
2723 the later. */
2724 c32 = tcg_temp_new_i32();
2725 if (cmp->is_bool) {
ecc7b3aa 2726 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2727 } else {
2728 TCGv_i64 c64 = tcg_temp_new_i64();
2729 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2730 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2731 }
2732
2733 s1 = gen_load_fpr_F(dc, rs);
2734 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2735 dst = gen_dest_fpr_F(dc);
00ab7e61 2736 zero = tcg_constant_i32(0);
7e480893
RH		 2737
2738 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2739
7e480893
RH		 2740 gen_store_fpr_F(dc, rd, dst);
2741}
2742
2743static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2744{
3886b8a3 2745 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2746 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2747 gen_load_fpr_D(dc, rs),
2748 gen_load_fpr_D(dc, rd));
2749 gen_store_fpr_D(dc, rd, dst);
2750}
2751
2752static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2753{
2754 int qd = QFPREG(rd);
2755 int qs = QFPREG(rs);
2756
2757 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2758 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2759 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2760 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2761
f9c816c0 2762 gen_update_fprs_dirty(dc, qd);
7e480893
RH		 2763}
2764
5d617bfb 2765static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
8194f35a 2766{
b551ec04 2767 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2768
2769 /* load env->tl into r_tl */
ad75a51e 2770 tcg_gen_ld_i32(r_tl, tcg_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2771
2772 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2773 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2774
2775 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2776 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
ad75a51e 2777 tcg_gen_addi_ptr(r_tsptr, tcg_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2778
2779 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2780 {
2781 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2782 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2783 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
b551ec04 2784 }
8194f35a 2785}
6c073553
RH		 2786
2787static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2788 int width, bool cc, bool left)
2789{
905a83de 2790 TCGv lo1, lo2;
6c073553
RH		 2791 uint64_t amask, tabl, tabr;
2792 int shift, imask, omask;
2793
2794 if (cc) {
2795 tcg_gen_mov_tl(cpu_cc_src, s1);
2796 tcg_gen_mov_tl(cpu_cc_src2, s2);
2797 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2798 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2799 dc->cc_op = CC_OP_SUB;
2800 }
2801
2802 /* Theory of operation: there are two tables, left and right (not to
2803 be confused with the left and right versions of the opcode). These
2804 are indexed by the low 3 bits of the inputs. To make things "easy",
2805 these tables are loaded into two constants, TABL and TABR below.
2806 The operation index = (input & imask) << shift calculates the index
2807 into the constant, while val = (table >> index) & omask calculates
2808 the value we're looking for. */
2809 switch (width) {
2810 case 8:
2811 imask = 0x7;
2812 shift = 3;
2813 omask = 0xff;
2814 if (left) {
2815 tabl = 0x80c0e0f0f8fcfeffULL;
2816 tabr = 0xff7f3f1f0f070301ULL;
2817 } else {
2818 tabl = 0x0103070f1f3f7fffULL;
2819 tabr = 0xfffefcf8f0e0c080ULL;
2820 }
2821 break;
2822 case 16:
2823 imask = 0x6;
2824 shift = 1;
2825 omask = 0xf;
2826 if (left) {
2827 tabl = 0x8cef;
2828 tabr = 0xf731;
2829 } else {
2830 tabl = 0x137f;
2831 tabr = 0xfec8;
2832 }
2833 break;
2834 case 32:
2835 imask = 0x4;
2836 shift = 0;
2837 omask = 0x3;
2838 if (left) {
2839 tabl = (2 << 2) | 3;
2840 tabr = (3 << 2) | 1;
2841 } else {
2842 tabl = (1 << 2) | 3;
2843 tabr = (3 << 2) | 2;
2844 }
2845 break;
2846 default:
2847 abort();
2848 }
2849
2850 lo1 = tcg_temp_new();
2851 lo2 = tcg_temp_new();
2852 tcg_gen_andi_tl(lo1, s1, imask);
2853 tcg_gen_andi_tl(lo2, s2, imask);
2854 tcg_gen_shli_tl(lo1, lo1, shift);
2855 tcg_gen_shli_tl(lo2, lo2, shift);
2856
905a83de
RH		 2857 tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
2858 tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
e3ebbade 2859 tcg_gen_andi_tl(lo1, lo1, omask);
6c073553
RH		 2860 tcg_gen_andi_tl(lo2, lo2, omask);
2861
2862 amask = -8;
2863 if (AM_CHECK(dc)) {
2864 amask &= 0xffffffffULL;
2865 }
2866 tcg_gen_andi_tl(s1, s1, amask);
2867 tcg_gen_andi_tl(s2, s2, amask);
2868
e3ebbade
RH		 2869 /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
2870 tcg_gen_and_tl(lo2, lo2, lo1);
2871 tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2);
6c073553 2872}
add545ab
RH		 2873
2874static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2875{
2876 TCGv tmp = tcg_temp_new();
2877
2878 tcg_gen_add_tl(tmp, s1, s2);
2879 tcg_gen_andi_tl(dst, tmp, -8);
2880 if (left) {
2881 tcg_gen_neg_tl(tmp, tmp);
2882 }
2883 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
add545ab 2884}
50c796f9
RH		 2885
2886static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2887{
2888 TCGv t1, t2, shift;
2889
2890 t1 = tcg_temp_new();
2891 t2 = tcg_temp_new();
2892 shift = tcg_temp_new();
2893
2894 tcg_gen_andi_tl(shift, gsr, 7);
2895 tcg_gen_shli_tl(shift, shift, 3);
2896 tcg_gen_shl_tl(t1, s1, shift);
2897
2898 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2899 shift of (up to 63) followed by a constant shift of 1. */
2900 tcg_gen_xori_tl(shift, shift, 63);
2901 tcg_gen_shr_tl(t2, s2, shift);
2902 tcg_gen_shri_tl(t2, t2, 1);
2903
2904 tcg_gen_or_tl(dst, t1, t2);
50c796f9 2905}
8194f35a
IK		 2906#endif
2907
878cc677
RH		 2908/* Include the auto-generated decoder. */
2909#include "decode-insns.c.inc"
2910
2911#define TRANS(NAME, AVAIL, FUNC, ...) \
2912 static bool trans_##NAME(DisasContext *dc, arg_##NAME *a) \
2913 { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); }
2914
2915#define avail_ALL(C) true
2916#ifdef TARGET_SPARC64
2917# define avail_32(C) false
af25071c 2918# define avail_ASR17(C) false
c2636853 2919# define avail_DIV(C) true
b5372650 2920# define avail_MUL(C) true
0faef01b 2921# define avail_POWERDOWN(C) false
878cc677 2922# define avail_64(C) true
5d617bfb 2923# define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
af25071c 2924# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
878cc677
RH		 2925#else
2926# define avail_32(C) true
af25071c 2927# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
c2636853 2928# define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV)
b5372650 2929# define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
0faef01b 2930# define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN)
878cc677 2931# define avail_64(C) false
5d617bfb 2932# define avail_GL(C) false
af25071c 2933# define avail_HYPV(C) false
878cc677
RH		 2934#endif
2935
2936/* Default case for non jump instructions. */
2937static bool advance_pc(DisasContext *dc)
2938{
2939 if (dc->npc & 3) {
2940 switch (dc->npc) {
2941 case DYNAMIC_PC:
2942 case DYNAMIC_PC_LOOKUP:
2943 dc->pc = dc->npc;
2944 gen_op_next_insn();
2945 break;
2946 case JUMP_PC:
2947 /* we can do a static jump */
2948 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
2949 dc->base.is_jmp = DISAS_NORETURN;
2950 break;
2951 default:
2952 g_assert_not_reached();
2953 }
2954 } else {
2955 dc->pc = dc->npc;
2956 dc->npc = dc->npc + 4;
2957 }
2958 return true;
2959}
2960
6d2a0768
RH		 2961/*
2962 * Major opcodes 00 and 01 -- branches, call, and sethi
2963 */
2964
276567aa
RH		 2965static bool advance_jump_uncond_never(DisasContext *dc, bool annul)
2966{
2967 if (annul) {
2968 dc->pc = dc->npc + 4;
2969 dc->npc = dc->pc + 4;
2970 } else {
2971 dc->pc = dc->npc;
2972 dc->npc = dc->pc + 4;
2973 }
2974 return true;
2975}
2976
2977static bool advance_jump_uncond_always(DisasContext *dc, bool annul,
2978 target_ulong dest)
2979{
2980 if (annul) {
2981 dc->pc = dest;
2982 dc->npc = dest + 4;
2983 } else {
2984 dc->pc = dc->npc;
2985 dc->npc = dest;
2986 tcg_gen_mov_tl(cpu_pc, cpu_npc);
2987 }
2988 return true;
2989}
2990
9d4e2bc7
RH		 2991static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp,
2992 bool annul, target_ulong dest)
276567aa 2993{
6b3e4cc6
RH		 2994 target_ulong npc = dc->npc;
2995
276567aa 2996 if (annul) {
6b3e4cc6
RH		 2997 TCGLabel *l1 = gen_new_label();
2998
9d4e2bc7 2999 tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1);
6b3e4cc6
RH		 3000 gen_goto_tb(dc, 0, npc, dest);
3001 gen_set_label(l1);
3002 gen_goto_tb(dc, 1, npc + 4, npc + 8);
3003
3004 dc->base.is_jmp = DISAS_NORETURN;
276567aa 3005 } else {
6b3e4cc6
RH		 3006 if (npc & 3) {
3007 switch (npc) {
3008 case DYNAMIC_PC:
3009 case DYNAMIC_PC_LOOKUP:
3010 tcg_gen_mov_tl(cpu_pc, cpu_npc);
3011 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
9d4e2bc7
RH		 3012 tcg_gen_movcond_tl(cmp->cond, cpu_npc,
3013 cmp->c1, cmp->c2,
6b3e4cc6
RH		 3014 tcg_constant_tl(dest), cpu_npc);
3015 dc->pc = npc;
3016 break;
3017 default:
3018 g_assert_not_reached();
3019 }
3020 } else {
3021 dc->pc = npc;
3022 dc->jump_pc[0] = dest;
3023 dc->jump_pc[1] = npc + 4;
3024 dc->npc = JUMP_PC;
9d4e2bc7
RH		 3025 if (cmp->is_bool) {
3026 tcg_gen_mov_tl(cpu_cond, cmp->c1);
3027 } else {
3028 tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
3029 }
6b3e4cc6 3030 }
276567aa
RH		 3031 }
3032 return true;
3033}
3034
af25071c
RH		 3035static bool raise_priv(DisasContext *dc)
3036{
3037 gen_exception(dc, TT_PRIV_INSN);
3038 return true;
3039}
3040
276567aa
RH		 3041static bool do_bpcc(DisasContext *dc, arg_bcc *a)
3042{
3043 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
1ea9c62a 3044 DisasCompare cmp;
276567aa
RH		 3045
3046 switch (a->cond) {
3047 case 0x0:
3048 return advance_jump_uncond_never(dc, a->a);
3049 case 0x8:
3050 return advance_jump_uncond_always(dc, a->a, target);
3051 default:
3052 flush_cond(dc);
1ea9c62a
RH		 3053
3054 gen_compare(&cmp, a->cc, a->cond, dc);
9d4e2bc7 3055 return advance_jump_cond(dc, &cmp, a->a, target);
276567aa
RH		 3056 }
3057}
3058
3059TRANS(Bicc, ALL, do_bpcc, a)
3060TRANS(BPcc, 64, do_bpcc, a)
3061
45196ea4
RH		 3062static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
3063{
3064 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
d5471936 3065 DisasCompare cmp;
45196ea4
RH		 3066
3067 if (gen_trap_ifnofpu(dc)) {
3068 return true;
3069 }
3070 switch (a->cond) {
3071 case 0x0:
3072 return advance_jump_uncond_never(dc, a->a);
3073 case 0x8:
3074 return advance_jump_uncond_always(dc, a->a, target);
3075 default:
3076 flush_cond(dc);
d5471936
RH		 3077
3078 gen_fcompare(&cmp, a->cc, a->cond);
9d4e2bc7 3079 return advance_jump_cond(dc, &cmp, a->a, target);
45196ea4
RH		 3080 }
3081}
3082
3083TRANS(FBPfcc, 64, do_fbpfcc, a)
3084TRANS(FBfcc, ALL, do_fbpfcc, a)
3085
ab9ffe98
RH		 3086static bool trans_BPr(DisasContext *dc, arg_BPr *a)
3087{
3088 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
3089 DisasCompare cmp;
3090
3091 if (!avail_64(dc)) {
3092 return false;
3093 }
3094 if (gen_tcg_cond_reg[a->cond] == TCG_COND_NEVER) {
3095 return false;
3096 }
3097
3098 flush_cond(dc);
3099 gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
9d4e2bc7 3100 return advance_jump_cond(dc, &cmp, a->a, target);
ab9ffe98
RH		 3101}
3102
23ada1b1
RH		 3103static bool trans_CALL(DisasContext *dc, arg_CALL *a)
3104{
3105 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
3106
3107 gen_store_gpr(dc, 15, tcg_constant_tl(dc->pc));
3108 gen_mov_pc_npc(dc);
3109 dc->npc = target;
3110 return true;
3111}
3112
45196ea4
RH		 3113static bool trans_NCP(DisasContext *dc, arg_NCP *a)
3114{
3115 /*
3116 * For sparc32, always generate the no-coprocessor exception.
3117 * For sparc64, always generate illegal instruction.
3118 */
3119#ifdef TARGET_SPARC64
3120 return false;
3121#else
3122 gen_exception(dc, TT_NCP_INSN);
3123 return true;
3124#endif
3125}
3126
6d2a0768
RH		 3127static bool trans_SETHI(DisasContext *dc, arg_SETHI *a)
3128{
3129 /* Special-case %g0 because that's the canonical nop. */
3130 if (a->rd) {
3131 gen_store_gpr(dc, a->rd, tcg_constant_tl((uint32_t)a->i << 10));
3132 }
3133 return advance_pc(dc);
3134}
3135
0faef01b
RH		 3136/*
3137 * Major Opcode 10 -- integer, floating-point, vis, and system insns.
3138 */
3139
30376636
RH		 3140static bool do_tcc(DisasContext *dc, int cond, int cc,
3141 int rs1, bool imm, int rs2_or_imm)
3142{
3143 int mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3144 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3145 DisasCompare cmp;
3146 TCGLabel *lab;
3147 TCGv_i32 trap;
3148
3149 /* Trap never. */
3150 if (cond == 0) {
3151 return advance_pc(dc);
3152 }
3153
3154 /*
3155 * Immediate traps are the most common case. Since this value is
3156 * live across the branch, it really pays to evaluate the constant.
3157 */
3158 if (rs1 == 0 && (imm || rs2_or_imm == 0)) {
3159 trap = tcg_constant_i32((rs2_or_imm & mask) + TT_TRAP);
3160 } else {
3161 trap = tcg_temp_new_i32();
3162 tcg_gen_trunc_tl_i32(trap, gen_load_gpr(dc, rs1));
3163 if (imm) {
3164 tcg_gen_addi_i32(trap, trap, rs2_or_imm);
3165 } else {
3166 TCGv_i32 t2 = tcg_temp_new_i32();
3167 tcg_gen_trunc_tl_i32(t2, gen_load_gpr(dc, rs2_or_imm));
3168 tcg_gen_add_i32(trap, trap, t2);
3169 }
3170 tcg_gen_andi_i32(trap, trap, mask);
3171 tcg_gen_addi_i32(trap, trap, TT_TRAP);
3172 }
3173
3174 /* Trap always. */
3175 if (cond == 8) {
3176 save_state(dc);
3177 gen_helper_raise_exception(tcg_env, trap);
3178 dc->base.is_jmp = DISAS_NORETURN;
3179 return true;
3180 }
3181
3182 /* Conditional trap. */
3183 flush_cond(dc);
3184 lab = delay_exceptionv(dc, trap);
3185 gen_compare(&cmp, cc, cond, dc);
3186 tcg_gen_brcond_tl(cmp.cond, cmp.c1, cmp.c2, lab);
3187
3188 return advance_pc(dc);
3189}
3190
3191static bool trans_Tcc_r(DisasContext *dc, arg_Tcc_r *a)
3192{
3193 if (avail_32(dc) && a->cc) {
3194 return false;
3195 }
3196 return do_tcc(dc, a->cond, a->cc, a->rs1, false, a->rs2);
3197}
3198
3199static bool trans_Tcc_i_v7(DisasContext *dc, arg_Tcc_i_v7 *a)
3200{
3201 if (avail_64(dc)) {
3202 return false;
3203 }
3204 return do_tcc(dc, a->cond, 0, a->rs1, true, a->i);
3205}
3206
3207static bool trans_Tcc_i_v9(DisasContext *dc, arg_Tcc_i_v9 *a)
3208{
3209 if (avail_32(dc)) {
3210 return false;
3211 }
3212 return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i);
3213}
3214
af25071c
RH		 3215static bool trans_STBAR(DisasContext *dc, arg_STBAR *a)
3216{
3217 tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
3218 return advance_pc(dc);
3219}
3220
3221static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a)
3222{
3223 if (avail_32(dc)) {
3224 return false;
3225 }
3226 if (a->mmask) {
3227 /* Note TCG_MO_* was modeled on sparc64, so mmask matches. */
3228 tcg_gen_mb(a->mmask | TCG_BAR_SC);
3229 }
3230 if (a->cmask) {
3231 /* For #Sync, etc, end the TB to recognize interrupts. */
3232 dc->base.is_jmp = DISAS_EXIT;
3233 }
3234 return advance_pc(dc);
3235}
3236
3237static bool do_rd_special(DisasContext *dc, bool priv, int rd,
3238 TCGv (*func)(DisasContext *, TCGv))
3239{
3240 if (!priv) {
3241 return raise_priv(dc);
3242 }
3243 gen_store_gpr(dc, rd, func(dc, gen_dest_gpr(dc, rd)));
3244 return advance_pc(dc);
3245}
3246
3247static TCGv do_rdy(DisasContext *dc, TCGv dst)
3248{
3249 return cpu_y;
3250}
3251
3252static bool trans_RDY(DisasContext *dc, arg_RDY *a)
3253{
3254 /*
3255 * TODO: Need a feature bit for sparcv8. In the meantime, treat all
3256 * 32-bit cpus like sparcv7, which ignores the rs1 field.
3257 * This matches after all other ASR, so Leon3 Asr17 is handled first.
3258 */
3259 if (avail_64(dc) && a->rs1 != 0) {
3260 return false;
3261 }
3262 return do_rd_special(dc, true, a->rd, do_rdy);
3263}
3264
3265static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
3266{
3267 uint32_t val;
3268
3269 /*
3270 * TODO: There are many more fields to be filled,
3271 * some of which are writable.
3272 */
3273 val = dc->def->nwindows - 1; /* [4:0] NWIN */
3274 val |= 1 << 8; /* [8] V8 */
3275
3276 return tcg_constant_tl(val);
3277}
3278
3279TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
3280
3281static TCGv do_rdccr(DisasContext *dc, TCGv dst)
3282{
3283 update_psr(dc);
3284 gen_helper_rdccr(dst, tcg_env);
3285 return dst;
3286}
3287
3288TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr)
3289
3290static TCGv do_rdasi(DisasContext *dc, TCGv dst)
3291{
3292#ifdef TARGET_SPARC64
3293 return tcg_constant_tl(dc->asi);
3294#else
3295 qemu_build_not_reached();
3296#endif
3297}
3298
3299TRANS(RDASI, 64, do_rd_special, true, a->rd, do_rdasi)
3300
3301static TCGv do_rdtick(DisasContext *dc, TCGv dst)
3302{
3303 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3304
3305 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
3306 if (translator_io_start(&dc->base)) {
3307 dc->base.is_jmp = DISAS_EXIT;
3308 }
3309 gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
3310 tcg_constant_i32(dc->mem_idx));
3311 return dst;
3312}
3313
3314/* TODO: non-priv access only allowed when enabled. */
3315TRANS(RDTICK, 64, do_rd_special, true, a->rd, do_rdtick)
3316
3317static TCGv do_rdpc(DisasContext *dc, TCGv dst)
3318{
3319 return tcg_constant_tl(address_mask_i(dc, dc->pc));
3320}
3321
3322TRANS(RDPC, 64, do_rd_special, true, a->rd, do_rdpc)
3323
3324static TCGv do_rdfprs(DisasContext *dc, TCGv dst)
3325{
3326 tcg_gen_ext_i32_tl(dst, cpu_fprs);
3327 return dst;
3328}
3329
3330TRANS(RDFPRS, 64, do_rd_special, true, a->rd, do_rdfprs)
3331
3332static TCGv do_rdgsr(DisasContext *dc, TCGv dst)
3333{
3334 gen_trap_ifnofpu(dc);
3335 return cpu_gsr;
3336}
3337
3338TRANS(RDGSR, 64, do_rd_special, true, a->rd, do_rdgsr)
3339
3340static TCGv do_rdsoftint(DisasContext *dc, TCGv dst)
3341{
3342 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(softint));
3343 return dst;
3344}
3345
3346TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a->rd, do_rdsoftint)
3347
3348static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst)
3349{
577efa45
RH		 3350 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(tick_cmpr));
3351 return dst;
af25071c
RH		 3352}
3353
3354/* TODO: non-priv access only allowed when enabled. */
3355TRANS(RDTICK_CMPR, 64, do_rd_special, true, a->rd, do_rdtick_cmpr)
3356
3357static TCGv do_rdstick(DisasContext *dc, TCGv dst)
3358{
3359 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3360
3361 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick));
3362 if (translator_io_start(&dc->base)) {
3363 dc->base.is_jmp = DISAS_EXIT;
3364 }
3365 gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
3366 tcg_constant_i32(dc->mem_idx));
3367 return dst;
3368}
3369
3370/* TODO: non-priv access only allowed when enabled. */
3371TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rdstick)
3372
3373static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst)
3374{
577efa45
RH		 3375 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(stick_cmpr));
3376 return dst;
af25071c
RH		 3377}
3378
3379/* TODO: supervisor access only allowed when enabled by hypervisor. */
3380TRANS(RDSTICK_CMPR, 64, do_rd_special, supervisor(dc), a->rd, do_rdstick_cmpr)
3381
3382/*
3383 * UltraSPARC-T1 Strand status.
3384 * HYPV check maybe not enough, UA2005 & UA2007 describe
3385 * this ASR as impl. dep
3386 */
3387static TCGv do_rdstrand_status(DisasContext *dc, TCGv dst)
3388{
3389 return tcg_constant_tl(1);
3390}
3391
3392TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status)
3393
668bb9b7
RH		 3394static TCGv do_rdpsr(DisasContext *dc, TCGv dst)
3395{
3396 update_psr(dc);
3397 gen_helper_rdpsr(dst, tcg_env);
3398 return dst;
3399}
3400
3401TRANS(RDPSR, 32, do_rd_special, supervisor(dc), a->rd, do_rdpsr)
3402
3403static TCGv do_rdhpstate(DisasContext *dc, TCGv dst)
3404{
3405 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hpstate));
3406 return dst;
3407}
3408
3409TRANS(RDHPR_hpstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhpstate)
3410
3411static TCGv do_rdhtstate(DisasContext *dc, TCGv dst)
3412{
3413 TCGv_i32 tl = tcg_temp_new_i32();
3414 TCGv_ptr tp = tcg_temp_new_ptr();
3415
3416 tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl));
3417 tcg_gen_andi_i32(tl, tl, MAXTL_MASK);
3418 tcg_gen_shli_i32(tl, tl, 3);
3419 tcg_gen_ext_i32_ptr(tp, tl);
3420 tcg_gen_add_ptr(tp, tp, tcg_env);
3421
3422 tcg_gen_ld_tl(dst, tp, env64_field_offsetof(htstate));
3423 return dst;
3424}
3425
3426TRANS(RDHPR_htstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtstate)
3427
3428static TCGv do_rdhintp(DisasContext *dc, TCGv dst)
3429{
2da789de
RH		 3430 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hintp));
3431 return dst;
668bb9b7
RH		 3432}
3433
3434TRANS(RDHPR_hintp, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhintp)
3435
3436static TCGv do_rdhtba(DisasContext *dc, TCGv dst)
3437{
2da789de
RH		 3438 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(htba));
3439 return dst;
668bb9b7
RH		 3440}
3441
3442TRANS(RDHPR_htba, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtba)
3443
3444static TCGv do_rdhver(DisasContext *dc, TCGv dst)
3445{
2da789de
RH		 3446 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hver));
3447 return dst;
668bb9b7
RH		 3448}
3449
3450TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhver)
3451
3452static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst)
3453{
577efa45
RH		 3454 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hstick_cmpr));
3455 return dst;
668bb9b7
RH		 3456}
3457
3458TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd,
3459 do_rdhstick_cmpr)
3460
5d617bfb
RH		 3461static TCGv do_rdwim(DisasContext *dc, TCGv dst)
3462{
cd6269f7
RH		 3463 tcg_gen_ld_tl(dst, tcg_env, env32_field_offsetof(wim));
3464 return dst;
5d617bfb
RH		 3465}
3466
3467TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim)
3468
3469static TCGv do_rdtpc(DisasContext *dc, TCGv dst)
3470{
3471#ifdef TARGET_SPARC64
3472 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3473
3474 gen_load_trap_state_at_tl(r_tsptr);
3475 tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tpc));
3476 return dst;
3477#else
3478 qemu_build_not_reached();
3479#endif
3480}
3481
3482TRANS(RDPR_tpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtpc)
3483
3484static TCGv do_rdtnpc(DisasContext *dc, TCGv dst)
3485{
3486#ifdef TARGET_SPARC64
3487 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3488
3489 gen_load_trap_state_at_tl(r_tsptr);
3490 tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tnpc));
3491 return dst;
3492#else
3493 qemu_build_not_reached();
3494#endif
3495}
3496
3497TRANS(RDPR_tnpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtnpc)
3498
3499static TCGv do_rdtstate(DisasContext *dc, TCGv dst)
3500{
3501#ifdef TARGET_SPARC64
3502 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3503
3504 gen_load_trap_state_at_tl(r_tsptr);
3505 tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tstate));
3506 return dst;
3507#else
3508 qemu_build_not_reached();
3509#endif
3510}
3511
3512TRANS(RDPR_tstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdtstate)
3513
3514static TCGv do_rdtt(DisasContext *dc, TCGv dst)
3515{
3516#ifdef TARGET_SPARC64
3517 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3518
3519 gen_load_trap_state_at_tl(r_tsptr);
3520 tcg_gen_ld32s_tl(dst, r_tsptr, offsetof(trap_state, tt));
3521 return dst;
3522#else
3523 qemu_build_not_reached();
3524#endif
3525}
3526
3527TRANS(RDPR_tt, 64, do_rd_special, supervisor(dc), a->rd, do_rdtt)
3528TRANS(RDPR_tick, 64, do_rd_special, supervisor(dc), a->rd, do_rdtick)
3529
3530static TCGv do_rdtba(DisasContext *dc, TCGv dst)
3531{
3532 return cpu_tbr;
3533}
3534
e8325dc0 3535TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba)
5d617bfb
RH		 3536TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba)
3537
3538static TCGv do_rdpstate(DisasContext *dc, TCGv dst)
3539{
3540 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(pstate));
3541 return dst;
3542}
3543
3544TRANS(RDPR_pstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdpstate)
3545
3546static TCGv do_rdtl(DisasContext *dc, TCGv dst)
3547{
3548 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(tl));
3549 return dst;
3550}
3551
3552TRANS(RDPR_tl, 64, do_rd_special, supervisor(dc), a->rd, do_rdtl)
3553
3554static TCGv do_rdpil(DisasContext *dc, TCGv dst)
3555{
3556 tcg_gen_ld32s_tl(dst, tcg_env, env_field_offsetof(psrpil));
3557 return dst;
3558}
3559
3560TRANS(RDPR_pil, 64, do_rd_special, supervisor(dc), a->rd, do_rdpil)
3561
3562static TCGv do_rdcwp(DisasContext *dc, TCGv dst)
3563{
3564 gen_helper_rdcwp(dst, tcg_env);
3565 return dst;
3566}
3567
3568TRANS(RDPR_cwp, 64, do_rd_special, supervisor(dc), a->rd, do_rdcwp)
3569
3570static TCGv do_rdcansave(DisasContext *dc, TCGv dst)
3571{
3572 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cansave));
3573 return dst;
3574}
3575
3576TRANS(RDPR_cansave, 64, do_rd_special, supervisor(dc), a->rd, do_rdcansave)
3577
3578static TCGv do_rdcanrestore(DisasContext *dc, TCGv dst)
3579{
3580 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(canrestore));
3581 return dst;
3582}
3583
3584TRANS(RDPR_canrestore, 64, do_rd_special, supervisor(dc), a->rd,
3585 do_rdcanrestore)
3586
3587static TCGv do_rdcleanwin(DisasContext *dc, TCGv dst)
3588{
3589 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cleanwin));
3590 return dst;
3591}
3592
3593TRANS(RDPR_cleanwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdcleanwin)
3594
3595static TCGv do_rdotherwin(DisasContext *dc, TCGv dst)
3596{
3597 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(otherwin));
3598 return dst;
3599}
3600
3601TRANS(RDPR_otherwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdotherwin)
3602
3603static TCGv do_rdwstate(DisasContext *dc, TCGv dst)
3604{
3605 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(wstate));
3606 return dst;
3607}
3608
3609TRANS(RDPR_wstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdwstate)
3610
3611static TCGv do_rdgl(DisasContext *dc, TCGv dst)
3612{
3613 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(gl));
3614 return dst;
3615}
3616
3617TRANS(RDPR_gl, GL, do_rd_special, supervisor(dc), a->rd, do_rdgl)
3618
3619/* UA2005 strand status */
3620static TCGv do_rdssr(DisasContext *dc, TCGv dst)
3621{
2da789de
RH		 3622 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(ssr));
3623 return dst;
5d617bfb
RH		 3624}
3625
3626TRANS(RDPR_strand_status, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdssr)
3627
3628static TCGv do_rdver(DisasContext *dc, TCGv dst)
3629{
2da789de
RH		 3630 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(version));
3631 return dst;
5d617bfb
RH		 3632}
3633
3634TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver)
3635
e8325dc0
RH		 3636static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a)
3637{
3638 if (avail_64(dc)) {
3639 gen_helper_flushw(tcg_env);
3640 return advance_pc(dc);
3641 }
3642 return false;
3643}
3644
0faef01b
RH		 3645static bool do_wr_special(DisasContext *dc, arg_r_r_ri *a, bool priv,
3646 void (*func)(DisasContext *, TCGv))
3647{
3648 TCGv src;
3649
3650 /* For simplicity, we under-decoded the rs2 form. */
3651 if (!a->imm && (a->rs2_or_imm & ~0x1f)) {
3652 return false;
3653 }
3654 if (!priv) {
3655 return raise_priv(dc);
3656 }
3657
3658 if (a->rs1 == 0 && (a->imm || a->rs2_or_imm == 0)) {
3659 src = tcg_constant_tl(a->rs2_or_imm);
3660 } else {
3661 TCGv src1 = gen_load_gpr(dc, a->rs1);
3662 if (a->rs2_or_imm == 0) {
3663 src = src1;
3664 } else {
3665 src = tcg_temp_new();
3666 if (a->imm) {
3667 tcg_gen_xori_tl(src, src1, a->rs2_or_imm);
3668 } else {
3669 tcg_gen_xor_tl(src, src1, gen_load_gpr(dc, a->rs2_or_imm));
3670 }
3671 }
3672 }
3673 func(dc, src);
3674 return advance_pc(dc);
3675}
3676
3677static void do_wry(DisasContext *dc, TCGv src)
3678{
3679 tcg_gen_ext32u_tl(cpu_y, src);
3680}
3681
3682TRANS(WRY, ALL, do_wr_special, a, true, do_wry)
3683
3684static void do_wrccr(DisasContext *dc, TCGv src)
3685{
3686 gen_helper_wrccr(tcg_env, src);
3687}
3688
3689TRANS(WRCCR, 64, do_wr_special, a, true, do_wrccr)
3690
3691static void do_wrasi(DisasContext *dc, TCGv src)
3692{
3693 TCGv tmp = tcg_temp_new();
3694
3695 tcg_gen_ext8u_tl(tmp, src);
3696 tcg_gen_st32_tl(tmp, tcg_env, env64_field_offsetof(asi));
3697 /* End TB to notice changed ASI. */
3698 dc->base.is_jmp = DISAS_EXIT;
3699}
3700
3701TRANS(WRASI, 64, do_wr_special, a, true, do_wrasi)
3702
3703static void do_wrfprs(DisasContext *dc, TCGv src)
3704{
3705#ifdef TARGET_SPARC64
3706 tcg_gen_trunc_tl_i32(cpu_fprs, src);
3707 dc->fprs_dirty = 0;
3708 dc->base.is_jmp = DISAS_EXIT;
3709#else
3710 qemu_build_not_reached();
3711#endif
3712}
3713
3714TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
3715
3716static void do_wrgsr(DisasContext *dc, TCGv src)
3717{
3718 gen_trap_ifnofpu(dc);
3719 tcg_gen_mov_tl(cpu_gsr, src);
3720}
3721
3722TRANS(WRGSR, 64, do_wr_special, a, true, do_wrgsr)
3723
3724static void do_wrsoftint_set(DisasContext *dc, TCGv src)
3725{
3726 gen_helper_set_softint(tcg_env, src);
3727}
3728
3729TRANS(WRSOFTINT_SET, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_set)
3730
3731static void do_wrsoftint_clr(DisasContext *dc, TCGv src)
3732{
3733 gen_helper_clear_softint(tcg_env, src);
3734}
3735
3736TRANS(WRSOFTINT_CLR, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_clr)
3737
3738static void do_wrsoftint(DisasContext *dc, TCGv src)
3739{
3740 gen_helper_write_softint(tcg_env, src);
3741}
3742
3743TRANS(WRSOFTINT, 64, do_wr_special, a, supervisor(dc), do_wrsoftint)
3744
3745static void do_wrtick_cmpr(DisasContext *dc, TCGv src)
3746{
0faef01b
RH		 3747 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3748
577efa45
RH		 3749 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(tick_cmpr));
3750 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
0faef01b 3751 translator_io_start(&dc->base);
577efa45 3752 gen_helper_tick_set_limit(r_tickptr, src);
0faef01b
RH		 3753 /* End TB to handle timer interrupt */
3754 dc->base.is_jmp = DISAS_EXIT;
0faef01b
RH		 3755}
3756
3757TRANS(WRTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrtick_cmpr)
3758
3759static void do_wrstick(DisasContext *dc, TCGv src)
3760{
3761#ifdef TARGET_SPARC64
3762 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3763
3764 tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick));
3765 translator_io_start(&dc->base);
3766 gen_helper_tick_set_count(r_tickptr, src);
3767 /* End TB to handle timer interrupt */
3768 dc->base.is_jmp = DISAS_EXIT;
3769#else
3770 qemu_build_not_reached();
3771#endif
3772}
3773
3774TRANS(WRSTICK, 64, do_wr_special, a, supervisor(dc), do_wrstick)
3775
3776static void do_wrstick_cmpr(DisasContext *dc, TCGv src)
3777{
0faef01b
RH		 3778 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3779
577efa45
RH		 3780 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(stick_cmpr));
3781 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick));
0faef01b 3782 translator_io_start(&dc->base);
577efa45 3783 gen_helper_tick_set_limit(r_tickptr, src);
0faef01b
RH		 3784 /* End TB to handle timer interrupt */
3785 dc->base.is_jmp = DISAS_EXIT;
0faef01b
RH		 3786}
3787
3788TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrstick_cmpr)
3789
3790static void do_wrpowerdown(DisasContext *dc, TCGv src)
3791{
3792 save_state(dc);
3793 gen_helper_power_down(tcg_env);
3794}
3795
3796TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown)
3797
25524734
RH		 3798static void do_wrpsr(DisasContext *dc, TCGv src)
3799{
3800 gen_helper_wrpsr(tcg_env, src);
3801 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3802 dc->cc_op = CC_OP_FLAGS;
3803 dc->base.is_jmp = DISAS_EXIT;
3804}
3805
3806TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
3807
9422278e
RH		 3808static void do_wrwim(DisasContext *dc, TCGv src)
3809{
3810 target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows);
cd6269f7
RH		 3811 TCGv tmp = tcg_temp_new();
3812
3813 tcg_gen_andi_tl(tmp, src, mask);
3814 tcg_gen_st_tl(tmp, tcg_env, env32_field_offsetof(wim));
9422278e
RH		 3815}
3816
3817TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim)
3818
3819static void do_wrtpc(DisasContext *dc, TCGv src)
3820{
3821#ifdef TARGET_SPARC64
3822 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3823
3824 gen_load_trap_state_at_tl(r_tsptr);
3825 tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tpc));
3826#else
3827 qemu_build_not_reached();
3828#endif
3829}
3830
3831TRANS(WRPR_tpc, 64, do_wr_special, a, supervisor(dc), do_wrtpc)
3832
3833static void do_wrtnpc(DisasContext *dc, TCGv src)
3834{
3835#ifdef TARGET_SPARC64
3836 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3837
3838 gen_load_trap_state_at_tl(r_tsptr);
3839 tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tnpc));
3840#else
3841 qemu_build_not_reached();
3842#endif
3843}
3844
3845TRANS(WRPR_tnpc, 64, do_wr_special, a, supervisor(dc), do_wrtnpc)
3846
3847static void do_wrtstate(DisasContext *dc, TCGv src)
3848{
3849#ifdef TARGET_SPARC64
3850 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3851
3852 gen_load_trap_state_at_tl(r_tsptr);
3853 tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tstate));
3854#else
3855 qemu_build_not_reached();
3856#endif
3857}
3858
3859TRANS(WRPR_tstate, 64, do_wr_special, a, supervisor(dc), do_wrtstate)
3860
3861static void do_wrtt(DisasContext *dc, TCGv src)
3862{
3863#ifdef TARGET_SPARC64
3864 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3865
3866 gen_load_trap_state_at_tl(r_tsptr);
3867 tcg_gen_st32_tl(src, r_tsptr, offsetof(trap_state, tt));
3868#else
3869 qemu_build_not_reached();
3870#endif
3871}
3872
3873TRANS(WRPR_tt, 64, do_wr_special, a, supervisor(dc), do_wrtt)
3874
3875static void do_wrtick(DisasContext *dc, TCGv src)
3876{
3877 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3878
3879 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
3880 translator_io_start(&dc->base);
3881 gen_helper_tick_set_count(r_tickptr, src);
3882 /* End TB to handle timer interrupt */
3883 dc->base.is_jmp = DISAS_EXIT;
3884}
3885
3886TRANS(WRPR_tick, 64, do_wr_special, a, supervisor(dc), do_wrtick)
3887
3888static void do_wrtba(DisasContext *dc, TCGv src)
3889{
3890 tcg_gen_mov_tl(cpu_tbr, src);
3891}
3892
3893TRANS(WRPR_tba, 64, do_wr_special, a, supervisor(dc), do_wrtba)
3894
3895static void do_wrpstate(DisasContext *dc, TCGv src)
3896{
3897 save_state(dc);
3898 if (translator_io_start(&dc->base)) {
3899 dc->base.is_jmp = DISAS_EXIT;
3900 }
3901 gen_helper_wrpstate(tcg_env, src);
3902 dc->npc = DYNAMIC_PC;
3903}
3904
3905TRANS(WRPR_pstate, 64, do_wr_special, a, supervisor(dc), do_wrpstate)
3906
3907static void do_wrtl(DisasContext *dc, TCGv src)
3908{
3909 save_state(dc);
3910 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(tl));
3911 dc->npc = DYNAMIC_PC;
3912}
3913
3914TRANS(WRPR_tl, 64, do_wr_special, a, supervisor(dc), do_wrtl)
3915
3916static void do_wrpil(DisasContext *dc, TCGv src)
3917{
3918 if (translator_io_start(&dc->base)) {
3919 dc->base.is_jmp = DISAS_EXIT;
3920 }
3921 gen_helper_wrpil(tcg_env, src);
3922}
3923
3924TRANS(WRPR_pil, 64, do_wr_special, a, supervisor(dc), do_wrpil)
3925
3926static void do_wrcwp(DisasContext *dc, TCGv src)
3927{
3928 gen_helper_wrcwp(tcg_env, src);
3929}
3930
3931TRANS(WRPR_cwp, 64, do_wr_special, a, supervisor(dc), do_wrcwp)
3932
3933static void do_wrcansave(DisasContext *dc, TCGv src)
3934{
3935 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cansave));
3936}
3937
3938TRANS(WRPR_cansave, 64, do_wr_special, a, supervisor(dc), do_wrcansave)
3939
3940static void do_wrcanrestore(DisasContext *dc, TCGv src)
3941{
3942 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(canrestore));
3943}
3944
3945TRANS(WRPR_canrestore, 64, do_wr_special, a, supervisor(dc), do_wrcanrestore)
3946
3947static void do_wrcleanwin(DisasContext *dc, TCGv src)
3948{
3949 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cleanwin));
3950}
3951
3952TRANS(WRPR_cleanwin, 64, do_wr_special, a, supervisor(dc), do_wrcleanwin)
3953
3954static void do_wrotherwin(DisasContext *dc, TCGv src)
3955{
3956 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(otherwin));
3957}
3958
3959TRANS(WRPR_otherwin, 64, do_wr_special, a, supervisor(dc), do_wrotherwin)
3960
3961static void do_wrwstate(DisasContext *dc, TCGv src)
3962{
3963 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(wstate));
3964}
3965
3966TRANS(WRPR_wstate, 64, do_wr_special, a, supervisor(dc), do_wrwstate)
3967
3968static void do_wrgl(DisasContext *dc, TCGv src)
3969{
3970 gen_helper_wrgl(tcg_env, src);
3971}
3972
3973TRANS(WRPR_gl, GL, do_wr_special, a, supervisor(dc), do_wrgl)
3974
3975/* UA2005 strand status */
3976static void do_wrssr(DisasContext *dc, TCGv src)
3977{
2da789de 3978 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(ssr));
9422278e
RH		 3979}
3980
3981TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr)
3982
bb97f2f5
RH		 3983TRANS(WRTBR, 32, do_wr_special, a, supervisor(dc), do_wrtba)
3984
3985static void do_wrhpstate(DisasContext *dc, TCGv src)
3986{
3987 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hpstate));
3988 dc->base.is_jmp = DISAS_EXIT;
3989}
3990
3991TRANS(WRHPR_hpstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhpstate)
3992
3993static void do_wrhtstate(DisasContext *dc, TCGv src)
3994{
3995 TCGv_i32 tl = tcg_temp_new_i32();
3996 TCGv_ptr tp = tcg_temp_new_ptr();
3997
3998 tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl));
3999 tcg_gen_andi_i32(tl, tl, MAXTL_MASK);
4000 tcg_gen_shli_i32(tl, tl, 3);
4001 tcg_gen_ext_i32_ptr(tp, tl);
4002 tcg_gen_add_ptr(tp, tp, tcg_env);
4003
4004 tcg_gen_st_tl(src, tp, env64_field_offsetof(htstate));
4005}
4006
4007TRANS(WRHPR_htstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtstate)
4008
4009static void do_wrhintp(DisasContext *dc, TCGv src)
4010{
2da789de 4011 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hintp));
bb97f2f5
RH		 4012}
4013
4014TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp)
4015
4016static void do_wrhtba(DisasContext *dc, TCGv src)
4017{
2da789de 4018 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(htba));
bb97f2f5
RH		 4019}
4020
4021TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba)
4022
4023static void do_wrhstick_cmpr(DisasContext *dc, TCGv src)
4024{
4025 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
4026
577efa45 4027 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hstick_cmpr));
bb97f2f5
RH		 4028 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(hstick));
4029 translator_io_start(&dc->base);
577efa45 4030 gen_helper_tick_set_limit(r_tickptr, src);
bb97f2f5
RH		 4031 /* End TB to handle timer interrupt */
4032 dc->base.is_jmp = DISAS_EXIT;
4033}
4034
4035TRANS(WRHPR_hstick_cmpr, HYPV, do_wr_special, a, hypervisor(dc),
4036 do_wrhstick_cmpr)
4037
25524734
RH		 4038static bool do_saved_restored(DisasContext *dc, bool saved)
4039{
4040 if (!supervisor(dc)) {
4041 return raise_priv(dc);
4042 }
4043 if (saved) {
4044 gen_helper_saved(tcg_env);
4045 } else {
4046 gen_helper_restored(tcg_env);
4047 }
4048 return advance_pc(dc);
4049}
4050
4051TRANS(SAVED, 64, do_saved_restored, true)
4052TRANS(RESTORED, 64, do_saved_restored, false)
4053
d3825800
RH		 4054static bool trans_NOP(DisasContext *dc, arg_NOP *a)
4055{
4056 return advance_pc(dc);
4057}
4058
0faef01b
RH		 4059static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
4060{
4061 /*
4062 * TODO: Need a feature bit for sparcv8.
4063 * In the meantime, treat all 32-bit cpus like sparcv7.
4064 */
4065 if (avail_32(dc)) {
4066 return advance_pc(dc);
4067 }
4068 return false;
4069}
4070
428881de
RH		 4071static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
4072 void (*func)(TCGv, TCGv, TCGv),
4073 void (*funci)(TCGv, TCGv, target_long))
4074{
4075 TCGv dst, src1;
4076
4077 /* For simplicity, we under-decoded the rs2 form. */
4078 if (!a->imm && a->rs2_or_imm & ~0x1f) {
4079 return false;
4080 }
4081
4082 if (a->cc) {
4083 dst = cpu_cc_dst;
4084 } else {
4085 dst = gen_dest_gpr(dc, a->rd);
4086 }
4087 src1 = gen_load_gpr(dc, a->rs1);
4088
4089 if (a->imm || a->rs2_or_imm == 0) {
4090 if (funci) {
4091 funci(dst, src1, a->rs2_or_imm);
4092 } else {
4093 func(dst, src1, tcg_constant_tl(a->rs2_or_imm));
4094 }
4095 } else {
4096 func(dst, src1, cpu_regs[a->rs2_or_imm]);
4097 }
4098 gen_store_gpr(dc, a->rd, dst);
4099
4100 if (a->cc) {
4101 tcg_gen_movi_i32(cpu_cc_op, cc_op);
4102 dc->cc_op = cc_op;
4103 }
4104 return advance_pc(dc);
4105}
4106
4107static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
4108 void (*func)(TCGv, TCGv, TCGv),
4109 void (*funci)(TCGv, TCGv, target_long),
4110 void (*func_cc)(TCGv, TCGv, TCGv))
4111{
4112 if (a->cc) {
22188d7d 4113 assert(cc_op >= 0);
428881de
RH		 4114 return do_arith_int(dc, a, cc_op, func_cc, NULL);
4115 }
4116 return do_arith_int(dc, a, cc_op, func, funci);
4117}
4118
4119static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a,
4120 void (*func)(TCGv, TCGv, TCGv),
4121 void (*funci)(TCGv, TCGv, target_long))
4122{
4123 return do_arith_int(dc, a, CC_OP_LOGIC, func, funci);
4124}
4125
4126TRANS(ADD, ALL, do_arith, a, CC_OP_ADD,
4127 tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc)
4128TRANS(SUB, ALL, do_arith, a, CC_OP_SUB,
4129 tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc)
4130
a9aba13d
RH		 4131TRANS(TADDcc, ALL, do_arith, a, CC_OP_TADD, NULL, NULL, gen_op_add_cc)
4132TRANS(TSUBcc, ALL, do_arith, a, CC_OP_TSUB, NULL, NULL, gen_op_sub_cc)
4133TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcctv)
4134TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcctv)
4135
428881de
RH		 4136TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
4137TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
4138TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
4139TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL)
4140TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL)
4141
22188d7d 4142TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL)
b5372650
RH		 4143TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL)
4144TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
22188d7d 4145
4ee85ea9
RH		 4146TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL)
4147TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL)
c2636853
RH		 4148TRANS(UDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_udiv, NULL, gen_op_udivcc)
4149TRANS(SDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_sdiv, NULL, gen_op_sdivcc)
4ee85ea9 4150
9c6ec5bc
RH		 4151/* TODO: Should have feature bit -- comes in with UltraSparc T2. */
4152TRANS(POPC, 64, do_arith, a, -1, gen_op_popc, NULL, NULL)
4153
428881de
RH		 4154static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
4155{
4156 /* OR with %g0 is the canonical alias for MOV. */
4157 if (!a->cc && a->rs1 == 0) {
4158 if (a->imm || a->rs2_or_imm == 0) {
4159 gen_store_gpr(dc, a->rd, tcg_constant_tl(a->rs2_or_imm));
4160 } else if (a->rs2_or_imm & ~0x1f) {
4161 /* For simplicity, we under-decoded the rs2 form. */
4162 return false;
4163 } else {
4164 gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]);
4165 }
4166 return advance_pc(dc);
4167 }
4168 return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
4169}
4170
420a187d
RH		 4171static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a)
4172{
4173 switch (dc->cc_op) {
4174 case CC_OP_DIV:
4175 case CC_OP_LOGIC:
4176 /* Carry is known to be zero. Fall back to plain ADD. */
4177 return do_arith(dc, a, CC_OP_ADD,
4178 tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc);
4179 case CC_OP_ADD:
4180 case CC_OP_TADD:
4181 case CC_OP_TADDTV:
4182 return do_arith(dc, a, CC_OP_ADDX,
4183 gen_op_addc_add, NULL, gen_op_addccc_add);
4184 case CC_OP_SUB:
4185 case CC_OP_TSUB:
4186 case CC_OP_TSUBTV:
4187 return do_arith(dc, a, CC_OP_ADDX,
4188 gen_op_addc_sub, NULL, gen_op_addccc_sub);
4189 default:
4190 return do_arith(dc, a, CC_OP_ADDX,
4191 gen_op_addc_generic, NULL, gen_op_addccc_generic);
4192 }
4193}
4194
dfebb950
RH		 4195static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a)
4196{
4197 switch (dc->cc_op) {
4198 case CC_OP_DIV:
4199 case CC_OP_LOGIC:
4200 /* Carry is known to be zero. Fall back to plain SUB. */
4201 return do_arith(dc, a, CC_OP_SUB,
4202 tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc);
4203 case CC_OP_ADD:
4204 case CC_OP_TADD:
4205 case CC_OP_TADDTV:
4206 return do_arith(dc, a, CC_OP_SUBX,
4207 gen_op_subc_add, NULL, gen_op_subccc_add);
4208 case CC_OP_SUB:
4209 case CC_OP_TSUB:
4210 case CC_OP_TSUBTV:
4211 return do_arith(dc, a, CC_OP_SUBX,
4212 gen_op_subc_sub, NULL, gen_op_subccc_sub);
4213 default:
4214 return do_arith(dc, a, CC_OP_SUBX,
4215 gen_op_subc_generic, NULL, gen_op_subccc_generic);
4216 }
4217}
4218
a9aba13d
RH		 4219static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a)
4220{
4221 update_psr(dc);
4222 return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc);
4223}
4224
5fc546ee
RH		 4225static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
4226{
4227 TCGv dst, src1, src2;
4228
4229 /* Reject 64-bit shifts for sparc32. */
4230 if (avail_32(dc) && a->x) {
4231 return false;
4232 }
4233
4234 src2 = tcg_temp_new();
4235 tcg_gen_andi_tl(src2, gen_load_gpr(dc, a->rs2), a->x ? 63 : 31);
4236 src1 = gen_load_gpr(dc, a->rs1);
4237 dst = gen_dest_gpr(dc, a->rd);
4238
4239 if (l) {
4240 tcg_gen_shl_tl(dst, src1, src2);
4241 if (!a->x) {
4242 tcg_gen_ext32u_tl(dst, dst);
4243 }
4244 } else if (u) {
4245 if (!a->x) {
4246 tcg_gen_ext32u_tl(dst, src1);
4247 src1 = dst;
4248 }
4249 tcg_gen_shr_tl(dst, src1, src2);
4250 } else {
4251 if (!a->x) {
4252 tcg_gen_ext32s_tl(dst, src1);
4253 src1 = dst;
4254 }
4255 tcg_gen_sar_tl(dst, src1, src2);
4256 }
4257 gen_store_gpr(dc, a->rd, dst);
4258 return advance_pc(dc);
4259}
4260
4261TRANS(SLL_r, ALL, do_shift_r, a, true, true)
4262TRANS(SRL_r, ALL, do_shift_r, a, false, true)
4263TRANS(SRA_r, ALL, do_shift_r, a, false, false)
4264
4265static bool do_shift_i(DisasContext *dc, arg_shifti *a, bool l, bool u)
4266{
4267 TCGv dst, src1;
4268
4269 /* Reject 64-bit shifts for sparc32. */
4270 if (avail_32(dc) && (a->x || a->i >= 32)) {
4271 return false;
4272 }
4273
4274 src1 = gen_load_gpr(dc, a->rs1);
4275 dst = gen_dest_gpr(dc, a->rd);
4276
4277 if (avail_32(dc) || a->x) {
4278 if (l) {
4279 tcg_gen_shli_tl(dst, src1, a->i);
4280 } else if (u) {
4281 tcg_gen_shri_tl(dst, src1, a->i);
4282 } else {
4283 tcg_gen_sari_tl(dst, src1, a->i);
4284 }
4285 } else {
4286 if (l) {
4287 tcg_gen_deposit_z_tl(dst, src1, a->i, 32 - a->i);
4288 } else if (u) {
4289 tcg_gen_extract_tl(dst, src1, a->i, 32 - a->i);
4290 } else {
4291 tcg_gen_sextract_tl(dst, src1, a->i, 32 - a->i);
4292 }
4293 }
4294 gen_store_gpr(dc, a->rd, dst);
4295 return advance_pc(dc);
4296}
4297
4298TRANS(SLL_i, ALL, do_shift_i, a, true, true)
4299TRANS(SRL_i, ALL, do_shift_i, a, false, true)
4300TRANS(SRA_i, ALL, do_shift_i, a, false, false)
4301
fb4ed7aa
RH		 4302static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm)
4303{
4304 /* For simplicity, we under-decoded the rs2 form. */
4305 if (!imm && rs2_or_imm & ~0x1f) {
4306 return NULL;
4307 }
4308 if (imm || rs2_or_imm == 0) {
4309 return tcg_constant_tl(rs2_or_imm);
4310 } else {
4311 return cpu_regs[rs2_or_imm];
4312 }
4313}
4314
4315static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv src2)
4316{
4317 TCGv dst = gen_load_gpr(dc, rd);
4318
4319 tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst);
4320 gen_store_gpr(dc, rd, dst);
4321 return advance_pc(dc);
4322}
4323
4324static bool trans_MOVcc(DisasContext *dc, arg_MOVcc *a)
4325{
4326 TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4327 DisasCompare cmp;
4328
4329 if (src2 == NULL) {
4330 return false;
4331 }
4332 gen_compare(&cmp, a->cc, a->cond, dc);
4333 return do_mov_cond(dc, &cmp, a->rd, src2);
4334}
4335
4336static bool trans_MOVfcc(DisasContext *dc, arg_MOVfcc *a)
4337{
4338 TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4339 DisasCompare cmp;
4340
4341 if (src2 == NULL) {
4342 return false;
4343 }
4344 gen_fcompare(&cmp, a->cc, a->cond);
4345 return do_mov_cond(dc, &cmp, a->rd, src2);
4346}
4347
4348static bool trans_MOVR(DisasContext *dc, arg_MOVR *a)
4349{
4350 TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4351 DisasCompare cmp;
4352
4353 if (src2 == NULL) {
4354 return false;
4355 }
4356 gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
4357 return do_mov_cond(dc, &cmp, a->rd, src2);
4358}
4359
86b82fe0
RH		 4360static bool do_add_special(DisasContext *dc, arg_r_r_ri *a,
4361 bool (*func)(DisasContext *dc, int rd, TCGv src))
4362{
4363 TCGv src1, sum;
4364
4365 /* For simplicity, we under-decoded the rs2 form. */
4366 if (!a->imm && a->rs2_or_imm & ~0x1f) {
4367 return false;
4368 }
4369
4370 /*
4371 * Always load the sum into a new temporary.
4372 * This is required to capture the value across a window change,
4373 * e.g. SAVE and RESTORE, and may be optimized away otherwise.
4374 */
4375 sum = tcg_temp_new();
4376 src1 = gen_load_gpr(dc, a->rs1);
4377 if (a->imm || a->rs2_or_imm == 0) {
4378 tcg_gen_addi_tl(sum, src1, a->rs2_or_imm);
4379 } else {
4380 tcg_gen_add_tl(sum, src1, cpu_regs[a->rs2_or_imm]);
4381 }
4382 return func(dc, a->rd, sum);
4383}
4384
4385static bool do_jmpl(DisasContext *dc, int rd, TCGv src)
4386{
4387 /*
4388 * Preserve pc across advance, so that we can delay
4389 * the writeback to rd until after src is consumed.
4390 */
4391 target_ulong cur_pc = dc->pc;
4392
4393 gen_check_align(dc, src, 3);
4394
4395 gen_mov_pc_npc(dc);
4396 tcg_gen_mov_tl(cpu_npc, src);
4397 gen_address_mask(dc, cpu_npc);
4398 gen_store_gpr(dc, rd, tcg_constant_tl(cur_pc));
4399
4400 dc->npc = DYNAMIC_PC_LOOKUP;
4401 return true;
4402}
4403
4404TRANS(JMPL, ALL, do_add_special, a, do_jmpl)
4405
4406static bool do_rett(DisasContext *dc, int rd, TCGv src)
4407{
4408 if (!supervisor(dc)) {
4409 return raise_priv(dc);
4410 }
4411
4412 gen_check_align(dc, src, 3);
4413
4414 gen_mov_pc_npc(dc);
4415 tcg_gen_mov_tl(cpu_npc, src);
4416 gen_helper_rett(tcg_env);
4417
4418 dc->npc = DYNAMIC_PC;
4419 return true;
4420}
4421
4422TRANS(RETT, 32, do_add_special, a, do_rett)
4423
4424static bool do_return(DisasContext *dc, int rd, TCGv src)
4425{
4426 gen_check_align(dc, src, 3);
4427
4428 gen_mov_pc_npc(dc);
4429 tcg_gen_mov_tl(cpu_npc, src);
4430 gen_address_mask(dc, cpu_npc);
4431
4432 gen_helper_restore(tcg_env);
4433 dc->npc = DYNAMIC_PC_LOOKUP;
4434 return true;
4435}
4436
4437TRANS(RETURN, 64, do_add_special, a, do_return)
4438
d3825800
RH		 4439static bool do_save(DisasContext *dc, int rd, TCGv src)
4440{
4441 gen_helper_save(tcg_env);
4442 gen_store_gpr(dc, rd, src);
4443 return advance_pc(dc);
4444}
4445
4446TRANS(SAVE, ALL, do_add_special, a, do_save)
4447
4448static bool do_restore(DisasContext *dc, int rd, TCGv src)
4449{
4450 gen_helper_restore(tcg_env);
4451 gen_store_gpr(dc, rd, src);
4452 return advance_pc(dc);
4453}
4454
4455TRANS(RESTORE, ALL, do_add_special, a, do_restore)
4456
8f75b8a4
RH		 4457static bool do_done_retry(DisasContext *dc, bool done)
4458{
4459 if (!supervisor(dc)) {
4460 return raise_priv(dc);
4461 }
4462 dc->npc = DYNAMIC_PC;
4463 dc->pc = DYNAMIC_PC;
4464 translator_io_start(&dc->base);
4465 if (done) {
4466 gen_helper_done(tcg_env);
4467 } else {
4468 gen_helper_retry(tcg_env);
4469 }
4470 return true;
4471}
4472
4473TRANS(DONE, 64, do_done_retry, true)
4474TRANS(RETRY, 64, do_done_retry, false)
4475
64a88d5d 4476#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 4477 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 4478 goto illegal_insn;
4479#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 4480 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 4481 goto nfpu_insn;
4482
0bee699e 4483/* before an instruction, dc->pc must be static */
878cc677 4484static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cf495bcf 4485{
0184e266 4486 unsigned int opc, rs1, rs2, rd;
8f75b8a4
RH		 4487 TCGv cpu_src1;
4488 TCGv cpu_src2 __attribute__((unused));
208ae657 4489 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 4490 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 4491 target_long simm;
7a3f1944 4492
cf495bcf 4493 opc = GET_FIELD(insn, 0, 1);
cf495bcf 4494 rd = GET_FIELD(insn, 2, 6);
6ae20372 4495
cf495bcf 4496 switch (opc) {
6d2a0768
RH		 4497 case 0:
4498 goto illegal_insn; /* in decodetree */
23ada1b1
RH		 4499 case 1:
4500 g_assert_not_reached(); /* in decodetree */
0f8a249a
BS		 4501 case 2: /* FPU & Logical Operations */
4502 {
8f75b8a4 4503 unsigned int xop = GET_FIELD(insn, 7, 12);
af25071c 4504 TCGv cpu_dst __attribute__((unused)) = tcg_temp_new();
5793f2a4 4505
af25071c 4506 if (xop == 0x34) { /* FPU Operations */
5b12f1e8 4507 if (gen_trap_ifnofpu(dc)) {
a80dde08 4508 goto jmp_insn;
5b12f1e8 4509 }
0f8a249a 4510 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 4511 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 4512 rs2 = GET_FIELD(insn, 27, 31);
4513 xop = GET_FIELD(insn, 18, 26);
02c79d78 4514
0f8a249a 4515 switch (xop) {
dc1a6971 4516 case 0x1: /* fmovs */
208ae657
RH		 4517 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4518 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 4519 break;
4520 case 0x5: /* fnegs */
61f17f6e 4521 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 4522 break;
4523 case 0x9: /* fabss */
61f17f6e 4524 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 4525 break;
4526 case 0x29: /* fsqrts */
61f17f6e 4527 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 4528 break;
4529 case 0x2a: /* fsqrtd */
61f17f6e 4530 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 4531 break;
4532 case 0x2b: /* fsqrtq */
4533 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4534 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 4535 break;
4536 case 0x41: /* fadds */
61f17f6e 4537 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 4538 break;
4539 case 0x42: /* faddd */
61f17f6e 4540 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 4541 break;
4542 case 0x43: /* faddq */
4543 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4544 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 4545 break;
4546 case 0x45: /* fsubs */
61f17f6e 4547 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 4548 break;
4549 case 0x46: /* fsubd */
61f17f6e 4550 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 4551 break;
4552 case 0x47: /* fsubq */
4553 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4554 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 4555 break;
4556 case 0x49: /* fmuls */
61f17f6e 4557 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 4558 break;
4559 case 0x4a: /* fmuld */
61f17f6e 4560 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 4561 break;
4562 case 0x4b: /* fmulq */
4563 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4564 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 4565 break;
4566 case 0x4d: /* fdivs */
61f17f6e 4567 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 4568 break;
4569 case 0x4e: /* fdivd */
61f17f6e 4570 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 4571 break;
4572 case 0x4f: /* fdivq */
4573 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4574 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 4575 break;
4576 case 0x69: /* fsmuld */
4577 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 4578 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 4579 break;
4580 case 0x6e: /* fdmulq */
4581 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4582 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 4583 break;
4584 case 0xc4: /* fitos */
61f17f6e 4585 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 4586 break;
4587 case 0xc6: /* fdtos */
61f17f6e 4588 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 4589 break;
4590 case 0xc7: /* fqtos */
4591 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4592 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 4593 break;
4594 case 0xc8: /* fitod */
61f17f6e 4595 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 4596 break;
4597 case 0xc9: /* fstod */
61f17f6e 4598 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 4599 break;
4600 case 0xcb: /* fqtod */
4601 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4602 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 4603 break;
4604 case 0xcc: /* fitoq */
4605 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4606 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 4607 break;
4608 case 0xcd: /* fstoq */
4609 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4610 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 4611 break;
4612 case 0xce: /* fdtoq */
4613 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4614 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 4615 break;
4616 case 0xd1: /* fstoi */
61f17f6e 4617 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 4618 break;
4619 case 0xd2: /* fdtoi */
61f17f6e 4620 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 4621 break;
4622 case 0xd3: /* fqtoi */
4623 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4624 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 4625 break;
3475187d 4626#ifdef TARGET_SPARC64
dc1a6971 4627 case 0x2: /* V9 fmovd */
96eda024
RH		 4628 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4629 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 4630 break;
4631 case 0x3: /* V9 fmovq */
4632 CHECK_FPU_FEATURE(dc, FLOAT128);
f9c816c0 4633 gen_move_Q(dc, rd, rs2);
dc1a6971
BS		 4634 break;
4635 case 0x6: /* V9 fnegd */
61f17f6e 4636 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 4637 break;
4638 case 0x7: /* V9 fnegq */
4639 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4640 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 4641 break;
4642 case 0xa: /* V9 fabsd */
61f17f6e 4643 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 4644 break;
4645 case 0xb: /* V9 fabsq */
4646 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4647 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 4648 break;
4649 case 0x81: /* V9 fstox */
61f17f6e 4650 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 4651 break;
4652 case 0x82: /* V9 fdtox */
61f17f6e 4653 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 4654 break;
4655 case 0x83: /* V9 fqtox */
4656 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4657 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 4658 break;
4659 case 0x84: /* V9 fxtos */
61f17f6e 4660 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 4661 break;
4662 case 0x88: /* V9 fxtod */
61f17f6e 4663 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 4664 break;
4665 case 0x8c: /* V9 fxtoq */
4666 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4667 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 4668 break;
0f8a249a 4669#endif
dc1a6971
BS		 4670 default:
4671 goto illegal_insn;
0f8a249a
BS		 4672 }
4673 } else if (xop == 0x35) { /* FPU Operations */
3475187d 4674#ifdef TARGET_SPARC64
0f8a249a 4675 int cond;
3475187d 4676#endif
5b12f1e8 4677 if (gen_trap_ifnofpu(dc)) {
a80dde08 4678 goto jmp_insn;
5b12f1e8 4679 }
0f8a249a 4680 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 4681 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 4682 rs2 = GET_FIELD(insn, 27, 31);
4683 xop = GET_FIELD(insn, 18, 26);
dcf24905 4684
690995a6
RH		 4685#ifdef TARGET_SPARC64
4686#define FMOVR(sz) \
4687 do { \
4688 DisasCompare cmp; \
e7c8afb9 4689 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 4690 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 4691 gen_compare_reg(&cmp, cond, cpu_src1); \
4692 gen_fmov##sz(dc, &cmp, rd, rs2); \
690995a6
RH		 4693 } while (0)
4694
4695 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
4696 FMOVR(s);
0f8a249a
BS		 4697 break;
4698 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 4699 FMOVR(d);
0f8a249a
BS		 4700 break;
4701 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 4702 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 4703 FMOVR(q);
1f587329 4704 break;
0f8a249a 4705 }
690995a6 4706#undef FMOVR
0f8a249a
BS		 4707#endif
4708 switch (xop) {
3475187d 4709#ifdef TARGET_SPARC64
7e480893
RH		 4710#define FMOVCC(fcc, sz) \
4711 do { \
4712 DisasCompare cmp; \
714547bb 4713 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 4714 gen_fcompare(&cmp, fcc, cond); \
4715 gen_fmov##sz(dc, &cmp, rd, rs2); \
7e480893
RH		 4716 } while (0)
4717
0f8a249a 4718 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 4719 FMOVCC(0, s);
0f8a249a
BS		 4720 break;
4721 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 4722 FMOVCC(0, d);
0f8a249a
BS		 4723 break;
4724 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 4725 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4726 FMOVCC(0, q);
1f587329 4727 break;
0f8a249a 4728 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 4729 FMOVCC(1, s);
0f8a249a
BS		 4730 break;
4731 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 4732 FMOVCC(1, d);
0f8a249a
BS		 4733 break;
4734 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 4735 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4736 FMOVCC(1, q);
1f587329 4737 break;
0f8a249a 4738 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 4739 FMOVCC(2, s);
0f8a249a
BS		 4740 break;
4741 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 4742 FMOVCC(2, d);
0f8a249a
BS		 4743 break;
4744 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 4745 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4746 FMOVCC(2, q);
1f587329 4747 break;
0f8a249a 4748 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 4749 FMOVCC(3, s);
0f8a249a
BS		 4750 break;
4751 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 4752 FMOVCC(3, d);
0f8a249a
BS		 4753 break;
4754 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 4755 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4756 FMOVCC(3, q);
1f587329 4757 break;
7e480893
RH		 4758#undef FMOVCC
4759#define FMOVCC(xcc, sz) \
4760 do { \
4761 DisasCompare cmp; \
714547bb 4762 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 4763 gen_compare(&cmp, xcc, cond, dc); \
4764 gen_fmov##sz(dc, &cmp, rd, rs2); \
7e480893 4765 } while (0)
19f329ad 4766
0f8a249a 4767 case 0x101: /* V9 fmovscc %icc */
7e480893 4768 FMOVCC(0, s);
0f8a249a
BS		 4769 break;
4770 case 0x102: /* V9 fmovdcc %icc */
7e480893 4771 FMOVCC(0, d);
b7d69dc2 4772 break;
0f8a249a 4773 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 4774 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4775 FMOVCC(0, q);
1f587329 4776 break;
0f8a249a 4777 case 0x181: /* V9 fmovscc %xcc */
7e480893 4778 FMOVCC(1, s);
0f8a249a
BS		 4779 break;
4780 case 0x182: /* V9 fmovdcc %xcc */
7e480893 4781 FMOVCC(1, d);
0f8a249a
BS		 4782 break;
4783 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 4784 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4785 FMOVCC(1, q);
1f587329 4786 break;
7e480893 4787#undef FMOVCC
1f587329
BS		 4788#endif
4789 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 4790 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4791 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
4792 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 4793 break;
1f587329 4794 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 4795 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4796 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4797 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 4798 break;
1f587329 4799 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 4800 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 4801 gen_op_load_fpr_QT0(QFPREG(rs1));
4802 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 4803 gen_op_fcmpq(rd & 3);
1f587329 4804 break;
0f8a249a 4805 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 4806 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4807 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
4808 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 4809 break;
4810 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 4811 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4812 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4813 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 4814 break;
1f587329 4815 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 4816 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 4817 gen_op_load_fpr_QT0(QFPREG(rs1));
4818 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 4819 gen_op_fcmpeq(rd & 3);
1f587329 4820 break;
0f8a249a
BS		 4821 default:
4822 goto illegal_insn;
4823 }
d3c7e8ad 4824 } else if (xop == 0x36) {
3299908c 4825#ifdef TARGET_SPARC64
d3c7e8ad 4826 /* VIS */
3299908c
BS		 4827 int opf = GET_FIELD_SP(insn, 5, 13);
4828 rs1 = GET_FIELD(insn, 13, 17);
4829 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4830 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4831 goto jmp_insn;
5b12f1e8 4832 }
3299908c
BS		 4833
4834 switch (opf) {
e9ebed4d 4835 case 0x000: /* VIS I edge8cc */
6c073553 4836 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4837 cpu_src1 = gen_load_gpr(dc, rs1);
4838 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4839 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4840 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4841 break;
e9ebed4d 4842 case 0x001: /* VIS II edge8n */
6c073553 4843 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4844 cpu_src1 = gen_load_gpr(dc, rs1);
4845 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4846 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4847 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4848 break;
e9ebed4d 4849 case 0x002: /* VIS I edge8lcc */
6c073553 4850 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4851 cpu_src1 = gen_load_gpr(dc, rs1);
4852 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4853 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4854 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4855 break;
e9ebed4d 4856 case 0x003: /* VIS II edge8ln */
6c073553 4857 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4858 cpu_src1 = gen_load_gpr(dc, rs1);
4859 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4860 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4861 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4862 break;
e9ebed4d 4863 case 0x004: /* VIS I edge16cc */
6c073553 4864 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4865 cpu_src1 = gen_load_gpr(dc, rs1);
4866 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4867 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4868 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4869 break;
e9ebed4d 4870 case 0x005: /* VIS II edge16n */
6c073553 4871 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4872 cpu_src1 = gen_load_gpr(dc, rs1);
4873 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4874 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4875 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4876 break;
e9ebed4d 4877 case 0x006: /* VIS I edge16lcc */
6c073553 4878 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4879 cpu_src1 = gen_load_gpr(dc, rs1);
4880 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4881 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4882 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4883 break;
e9ebed4d 4884 case 0x007: /* VIS II edge16ln */
6c073553 4885 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4886 cpu_src1 = gen_load_gpr(dc, rs1);
4887 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4888 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4889 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4890 break;
e9ebed4d 4891 case 0x008: /* VIS I edge32cc */
6c073553 4892 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4893 cpu_src1 = gen_load_gpr(dc, rs1);
4894 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4895 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4896 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4897 break;
e9ebed4d 4898 case 0x009: /* VIS II edge32n */
6c073553 4899 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4900 cpu_src1 = gen_load_gpr(dc, rs1);
4901 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4902 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4903 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4904 break;
e9ebed4d 4905 case 0x00a: /* VIS I edge32lcc */
6c073553 4906 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4907 cpu_src1 = gen_load_gpr(dc, rs1);
4908 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4909 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4910 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4911 break;
e9ebed4d 4912 case 0x00b: /* VIS II edge32ln */
6c073553 4913 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4914 cpu_src1 = gen_load_gpr(dc, rs1);
4915 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4916 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4917 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4918 break;
e9ebed4d 4919 case 0x010: /* VIS I array8 */
64a88d5d 4920 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4921 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4922 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4923 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4924 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4925 break;
4926 case 0x012: /* VIS I array16 */
64a88d5d 4927 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4928 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4929 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4930 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4931 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4932 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4933 break;
4934 case 0x014: /* VIS I array32 */
64a88d5d 4935 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4936 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4937 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4938 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4939 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4940 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4941 break;
3299908c 4942 case 0x018: /* VIS I alignaddr */
64a88d5d 4943 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4944 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4945 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4946 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4947 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4948 break;
4949 case 0x01a: /* VIS I alignaddrl */
add545ab 4950 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4951 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4952 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4953 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4954 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4955 break;
4956 case 0x019: /* VIS II bmask */
793a137a 4957 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4958 cpu_src1 = gen_load_gpr(dc, rs1);
4959 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4960 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4961 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4962 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4963 break;
e9ebed4d 4964 case 0x020: /* VIS I fcmple16 */
64a88d5d 4965 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4966 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4967 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4968 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4969 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4970 break;
4971 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4972 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4973 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4974 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4975 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4976 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4977 break;
e9ebed4d 4978 case 0x024: /* VIS I fcmple32 */
64a88d5d 4979 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4980 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4981 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4982 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4983 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4984 break;
4985 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4986 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4987 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4988 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4989 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4990 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4991 break;
4992 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4993 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4994 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4995 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4996 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4997 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4998 break;
4999 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 5000 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5001 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5002 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5003 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5004 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5005 break;
5006 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 5007 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5008 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5009 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5010 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5011 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5012 break;
5013 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 5014 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5015 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5016 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5017 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5018 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5019 break;
5020 case 0x031: /* VIS I fmul8x16 */
64a88d5d 5021 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5022 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 5023 break;
5024 case 0x033: /* VIS I fmul8x16au */
64a88d5d 5025 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5026 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 5027 break;
5028 case 0x035: /* VIS I fmul8x16al */
64a88d5d 5029 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5030 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 5031 break;
5032 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 5033 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5034 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 5035 break;
5036 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 5037 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5038 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 5039 break;
5040 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 5041 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5042 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 5043 break;
5044 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 5045 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5046 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 5047 break;
5048 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 5049 CHECK_FPU_FEATURE(dc, VIS1);
5050 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
5051 break;
e9ebed4d 5052 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 5053 CHECK_FPU_FEATURE(dc, VIS1);
5054 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 5055 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 5056 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
5057 gen_store_fpr_F(dc, rd, cpu_dst_32);
5058 break;
e9ebed4d 5059 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 5060 CHECK_FPU_FEATURE(dc, VIS1);
5061 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 5062 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 5063 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
5064 gen_store_fpr_F(dc, rd, cpu_dst_32);
5065 break;
f888300b
RH		 5066 case 0x03e: /* VIS I pdist */
5067 CHECK_FPU_FEATURE(dc, VIS1);
5068 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
5069 break;
3299908c 5070 case 0x048: /* VIS I faligndata */
64a88d5d 5071 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 5072 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 5073 break;
e9ebed4d 5074 case 0x04b: /* VIS I fpmerge */
64a88d5d 5075 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5076 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 5077 break;
5078 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 5079 CHECK_FPU_FEATURE(dc, VIS2);
5080 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
5081 break;
e9ebed4d 5082 case 0x04d: /* VIS I fexpand */
64a88d5d 5083 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5084 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 5085 break;
5086 case 0x050: /* VIS I fpadd16 */
64a88d5d 5087 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5088 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 5089 break;
5090 case 0x051: /* VIS I fpadd16s */
64a88d5d 5091 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5092 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 5093 break;
5094 case 0x052: /* VIS I fpadd32 */
64a88d5d 5095 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5096 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 5097 break;
5098 case 0x053: /* VIS I fpadd32s */
64a88d5d 5099 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5100 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 5101 break;
5102 case 0x054: /* VIS I fpsub16 */
64a88d5d 5103 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5104 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 5105 break;
5106 case 0x055: /* VIS I fpsub16s */
64a88d5d 5107 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5108 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 5109 break;
5110 case 0x056: /* VIS I fpsub32 */
64a88d5d 5111 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5112 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 5113 break;
5114 case 0x057: /* VIS I fpsub32s */
64a88d5d 5115 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5116 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 5117 break;
3299908c 5118 case 0x060: /* VIS I fzero */
64a88d5d 5119 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5120 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5121 tcg_gen_movi_i64(cpu_dst_64, 0);
5122 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5123 break;
5124 case 0x061: /* VIS I fzeros */
64a88d5d 5125 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5126 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5127 tcg_gen_movi_i32(cpu_dst_32, 0);
5128 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5129 break;
e9ebed4d 5130 case 0x062: /* VIS I fnor */
64a88d5d 5131 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5132 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 5133 break;
5134 case 0x063: /* VIS I fnors */
64a88d5d 5135 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5136 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 5137 break;
5138 case 0x064: /* VIS I fandnot2 */
64a88d5d 5139 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5140 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 5141 break;
5142 case 0x065: /* VIS I fandnot2s */
64a88d5d 5143 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5144 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 5145 break;
5146 case 0x066: /* VIS I fnot2 */
64a88d5d 5147 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5148 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 5149 break;
5150 case 0x067: /* VIS I fnot2s */
64a88d5d 5151 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5152 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 5153 break;
5154 case 0x068: /* VIS I fandnot1 */
64a88d5d 5155 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5156 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 5157 break;
5158 case 0x069: /* VIS I fandnot1s */
64a88d5d 5159 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5160 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 5161 break;
5162 case 0x06a: /* VIS I fnot1 */
64a88d5d 5163 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5164 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 5165 break;
5166 case 0x06b: /* VIS I fnot1s */
64a88d5d 5167 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5168 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 5169 break;
5170 case 0x06c: /* VIS I fxor */
64a88d5d 5171 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5172 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 5173 break;
5174 case 0x06d: /* VIS I fxors */
64a88d5d 5175 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5176 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 5177 break;
5178 case 0x06e: /* VIS I fnand */
64a88d5d 5179 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5180 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 5181 break;
5182 case 0x06f: /* VIS I fnands */
64a88d5d 5183 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5184 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 5185 break;
5186 case 0x070: /* VIS I fand */
64a88d5d 5187 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5188 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 5189 break;
5190 case 0x071: /* VIS I fands */
64a88d5d 5191 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5192 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 5193 break;
5194 case 0x072: /* VIS I fxnor */
64a88d5d 5195 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5196 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 5197 break;
5198 case 0x073: /* VIS I fxnors */
64a88d5d 5199 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5200 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 5201 break;
3299908c 5202 case 0x074: /* VIS I fsrc1 */
64a88d5d 5203 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5204 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5205 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5206 break;
5207 case 0x075: /* VIS I fsrc1s */
64a88d5d 5208 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5209 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5210 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5211 break;
e9ebed4d 5212 case 0x076: /* VIS I fornot2 */
64a88d5d 5213 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5214 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 5215 break;
5216 case 0x077: /* VIS I fornot2s */
64a88d5d 5217 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5218 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 5219 break;
3299908c 5220 case 0x078: /* VIS I fsrc2 */
64a88d5d 5221 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5222 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5223 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5224 break;
5225 case 0x079: /* VIS I fsrc2s */
64a88d5d 5226 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5227 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5228 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5229 break;
e9ebed4d 5230 case 0x07a: /* VIS I fornot1 */
64a88d5d 5231 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5232 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 5233 break;
5234 case 0x07b: /* VIS I fornot1s */
64a88d5d 5235 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5236 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 5237 break;
5238 case 0x07c: /* VIS I for */
64a88d5d 5239 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5240 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 5241 break;
5242 case 0x07d: /* VIS I fors */
64a88d5d 5243 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5244 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 5245 break;
3299908c 5246 case 0x07e: /* VIS I fone */
64a88d5d 5247 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5248 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5249 tcg_gen_movi_i64(cpu_dst_64, -1);
5250 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5251 break;
5252 case 0x07f: /* VIS I fones */
64a88d5d 5253 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5254 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5255 tcg_gen_movi_i32(cpu_dst_32, -1);
5256 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5257 break;
e9ebed4d
BS		 5258 case 0x080: /* VIS I shutdown */
5259 case 0x081: /* VIS II siam */
5260 // XXX
5261 goto illegal_insn;
3299908c
BS		 5262 default:
5263 goto illegal_insn;
5264 }
fcc72045 5265#endif
0f8a249a 5266 } else {
8f75b8a4 5267 goto illegal_insn; /* in decodetree */
cf495bcf 5268 }
0f8a249a
BS		 5269 }
5270 break;
5271 case 3: /* load/store instructions */
5272 {
5273 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 5274 /* ??? gen_address_mask prevents us from using a source
5275 register directly. Always generate a temporary. */
52123f14 5276 TCGv cpu_addr = tcg_temp_new();
9322a4bf 5277
5e6ed439
RH		 5278 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5279 if (xop == 0x3c || xop == 0x3e) {
5280 /* V9 casa/casxa : no offset */
71817e48 5281 } else if (IS_IMM) { /* immediate */
67526b20 5282 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 5283 if (simm != 0) {
5284 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5285 }
0f8a249a
BS		 5286 } else { /* register */
5287 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5288 if (rs2 != 0) {
5e6ed439 5289 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 5290 }
0f8a249a 5291 }
2f2ecb83
BS		 5292 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5293 (xop > 0x17 && xop <= 0x1d ) ||
5294 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 5295 TCGv cpu_val = gen_dest_gpr(dc, rd);
5296
0f8a249a 5297 switch (xop) {
b89e94af 5298 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 5299 gen_address_mask(dc, cpu_addr);
08149118 5300 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5301 dc->mem_idx, MO_TEUL | MO_ALIGN);
0f8a249a 5302 break;
b89e94af 5303 case 0x1: /* ldub, load unsigned byte */
2cade6a3 5304 gen_address_mask(dc, cpu_addr);
08149118
RH		 5305 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
5306 dc->mem_idx, MO_UB);
0f8a249a 5307 break;
b89e94af 5308 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 5309 gen_address_mask(dc, cpu_addr);
08149118 5310 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5311 dc->mem_idx, MO_TEUW | MO_ALIGN);
0f8a249a 5312 break;
b89e94af 5313 case 0x3: /* ldd, load double word */
0f8a249a 5314 if (rd & 1)
d4218d99 5315 goto illegal_insn;
1a2fb1c0 5316 else {
abcc7191 5317 TCGv_i64 t64;
2ea815ca 5318
2cade6a3 5319 gen_address_mask(dc, cpu_addr);
abcc7191 5320 t64 = tcg_temp_new_i64();
08149118 5321 tcg_gen_qemu_ld_i64(t64, cpu_addr,
316b6783 5322 dc->mem_idx, MO_TEUQ | MO_ALIGN);
de9e9d9f
RH		 5323 tcg_gen_trunc_i64_tl(cpu_val, t64);
5324 tcg_gen_ext32u_tl(cpu_val, cpu_val);
5325 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 5326 tcg_gen_shri_i64(t64, t64, 32);
5327 tcg_gen_trunc_i64_tl(cpu_val, t64);
de9e9d9f 5328 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 5329 }
0f8a249a 5330 break;
b89e94af 5331 case 0x9: /* ldsb, load signed byte */
2cade6a3 5332 gen_address_mask(dc, cpu_addr);
08149118 5333 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB);
0f8a249a 5334 break;
b89e94af 5335 case 0xa: /* ldsh, load signed halfword */
2cade6a3 5336 gen_address_mask(dc, cpu_addr);
08149118 5337 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5338 dc->mem_idx, MO_TESW | MO_ALIGN);
0f8a249a 5339 break;
fbb4bbb6
RH		 5340 case 0xd: /* ldstub */
5341 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5342 break;
de9e9d9f
RH		 5343 case 0x0f:
5344 /* swap, swap register with memory. Also atomically */
4fb554bc
RH		 5345 cpu_src1 = gen_load_gpr(dc, rd);
5346 gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5347 dc->mem_idx, MO_TEUL);
0f8a249a 5348 break;
3475187d 5349#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5350 case 0x10: /* lda, V9 lduwa, load word alternate */
1d65b0f5 5351 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
0f8a249a 5352 break;
b89e94af 5353 case 0x11: /* lduba, load unsigned byte alternate */
1d65b0f5 5354 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
0f8a249a 5355 break;
b89e94af 5356 case 0x12: /* lduha, load unsigned halfword alternate */
1d65b0f5 5357 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
0f8a249a 5358 break;
b89e94af 5359 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 5360 if (rd & 1) {
d4218d99 5361 goto illegal_insn;
7ec1e5ea 5362 }
e4dc0052 5363 gen_ldda_asi(dc, cpu_addr, insn, rd);
db166940 5364 goto skip_move;
b89e94af 5365 case 0x19: /* ldsba, load signed byte alternate */
1d65b0f5 5366 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
0f8a249a 5367 break;
b89e94af 5368 case 0x1a: /* ldsha, load signed halfword alternate */
1d65b0f5 5369 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
0f8a249a
BS		 5370 break;
5371 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 5372 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 5373 break;
b89e94af 5374 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 5375 atomically */
06828032 5376 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 5377 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 5378 break;
3475187d
FB		 5379#endif
5380#ifdef TARGET_SPARC64
0f8a249a 5381 case 0x08: /* V9 ldsw */
2cade6a3 5382 gen_address_mask(dc, cpu_addr);
08149118 5383 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5384 dc->mem_idx, MO_TESL | MO_ALIGN);
0f8a249a
BS		 5385 break;
5386 case 0x0b: /* V9 ldx */
2cade6a3 5387 gen_address_mask(dc, cpu_addr);
08149118 5388 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5389 dc->mem_idx, MO_TEUQ | MO_ALIGN);
0f8a249a
BS		 5390 break;
5391 case 0x18: /* V9 ldswa */
1d65b0f5 5392 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
0f8a249a
BS		 5393 break;
5394 case 0x1b: /* V9 ldxa */
fc313c64 5395 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
0f8a249a
BS		 5396 break;
5397 case 0x2d: /* V9 prefetch, no effect */
5398 goto skip_move;
5399 case 0x30: /* V9 ldfa */
5b12f1e8 5400 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5401 goto jmp_insn;
5402 }
22e70060 5403 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
f9c816c0 5404 gen_update_fprs_dirty(dc, rd);
81ad8ba2 5405 goto skip_move;
0f8a249a 5406 case 0x33: /* V9 lddfa */
5b12f1e8 5407 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5408 goto jmp_insn;
5409 }
22e70060 5410 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
f9c816c0 5411 gen_update_fprs_dirty(dc, DFPREG(rd));
81ad8ba2 5412 goto skip_move;
0f8a249a
BS		 5413 case 0x3d: /* V9 prefetcha, no effect */
5414 goto skip_move;
5415 case 0x32: /* V9 ldqfa */
64a88d5d 5416 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5417 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5418 goto jmp_insn;
5419 }
22e70060 5420 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
f9c816c0 5421 gen_update_fprs_dirty(dc, QFPREG(rd));
1f587329 5422 goto skip_move;
0f8a249a
BS		 5423#endif
5424 default:
5425 goto illegal_insn;
5426 }
97ea2859 5427 gen_store_gpr(dc, rd, cpu_val);
db166940 5428#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 5429 skip_move: ;
3475187d 5430#endif
0f8a249a 5431 } else if (xop >= 0x20 && xop < 0x24) {
5b12f1e8 5432 if (gen_trap_ifnofpu(dc)) {
a80dde08 5433 goto jmp_insn;
5b12f1e8 5434 }
0f8a249a 5435 switch (xop) {
b89e94af 5436 case 0x20: /* ldf, load fpreg */
2cade6a3 5437 gen_address_mask(dc, cpu_addr);
ba5f5179 5438 cpu_dst_32 = gen_dest_fpr_F(dc);
cb21b4da 5439 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
316b6783 5440 dc->mem_idx, MO_TEUL | MO_ALIGN);
208ae657 5441 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 5442 break;
3a3b925d
BS		 5443 case 0x21: /* ldfsr, V9 ldxfsr */
5444#ifdef TARGET_SPARC64
2cade6a3 5445 gen_address_mask(dc, cpu_addr);
3a3b925d 5446 if (rd == 1) {
abcc7191 5447 TCGv_i64 t64 = tcg_temp_new_i64();
cb21b4da 5448 tcg_gen_qemu_ld_i64(t64, cpu_addr,
316b6783 5449 dc->mem_idx, MO_TEUQ | MO_ALIGN);
ad75a51e 5450 gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, t64);
f8641947 5451 break;
fe987e23 5452 }
f8641947 5453#endif
36ab4623 5454 cpu_dst_32 = tcg_temp_new_i32();
cb21b4da 5455 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
316b6783 5456 dc->mem_idx, MO_TEUL | MO_ALIGN);
ad75a51e 5457 gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32);
0f8a249a 5458 break;
b89e94af 5459 case 0x22: /* ldqf, load quad fpreg */
f939ffe5
RH		 5460 CHECK_FPU_FEATURE(dc, FLOAT128);
5461 gen_address_mask(dc, cpu_addr);
5462 cpu_src1_64 = tcg_temp_new_i64();
cb21b4da 5463 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
fc313c64 5464 MO_TEUQ | MO_ALIGN_4);
f939ffe5
RH		 5465 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5466 cpu_src2_64 = tcg_temp_new_i64();
cb21b4da 5467 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
fc313c64 5468 MO_TEUQ | MO_ALIGN_4);
f939ffe5 5469 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
1f587329 5470 break;
b89e94af 5471 case 0x23: /* lddf, load double fpreg */
03fb8cfc 5472 gen_address_mask(dc, cpu_addr);
3886b8a3 5473 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
cb21b4da 5474 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
fc313c64 5475 MO_TEUQ | MO_ALIGN_4);
03fb8cfc 5476 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 5477 break;
5478 default:
5479 goto illegal_insn;
5480 }
dc1a6971 5481 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 5482 xop == 0xe || xop == 0x1e) {
81634eea
RH		 5483 TCGv cpu_val = gen_load_gpr(dc, rd);
5484
0f8a249a 5485 switch (xop) {
b89e94af 5486 case 0x4: /* st, store word */
2cade6a3 5487 gen_address_mask(dc, cpu_addr);
08149118 5488 tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
316b6783 5489 dc->mem_idx, MO_TEUL | MO_ALIGN);
0f8a249a 5490 break;
b89e94af 5491 case 0x5: /* stb, store byte */
2cade6a3 5492 gen_address_mask(dc, cpu_addr);
08149118 5493 tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB);
0f8a249a 5494 break;
b89e94af 5495 case 0x6: /* sth, store halfword */
2cade6a3 5496 gen_address_mask(dc, cpu_addr);
08149118 5497 tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
316b6783 5498 dc->mem_idx, MO_TEUW | MO_ALIGN);
0f8a249a 5499 break;
b89e94af 5500 case 0x7: /* std, store double word */
0f8a249a 5501 if (rd & 1)
d4218d99 5502 goto illegal_insn;
1a2fb1c0 5503 else {
abcc7191 5504 TCGv_i64 t64;
81634eea 5505 TCGv lo;
1a2fb1c0 5506
2cade6a3 5507 gen_address_mask(dc, cpu_addr);
81634eea 5508 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5509 t64 = tcg_temp_new_i64();
5510 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
08149118 5511 tcg_gen_qemu_st_i64(t64, cpu_addr,
316b6783 5512 dc->mem_idx, MO_TEUQ | MO_ALIGN);
7fa76c0b 5513 }
0f8a249a 5514 break;
3475187d 5515#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5516 case 0x14: /* sta, V9 stwa, store word alternate */
1d65b0f5 5517 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
d39c0b99 5518 break;
b89e94af 5519 case 0x15: /* stba, store byte alternate */
1d65b0f5 5520 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
d39c0b99 5521 break;
b89e94af 5522 case 0x16: /* stha, store halfword alternate */
1d65b0f5 5523 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
d39c0b99 5524 break;
b89e94af 5525 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5526 if (rd & 1) {
0f8a249a 5527 goto illegal_insn;
1a2fb1c0 5528 }
7ec1e5ea 5529 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5530 break;
e80cfcfc 5531#endif
3475187d 5532#ifdef TARGET_SPARC64
0f8a249a 5533 case 0x0e: /* V9 stx */
2cade6a3 5534 gen_address_mask(dc, cpu_addr);
08149118 5535 tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
316b6783 5536 dc->mem_idx, MO_TEUQ | MO_ALIGN);
0f8a249a
BS		 5537 break;
5538 case 0x1e: /* V9 stxa */
fc313c64 5539 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
0f8a249a 5540 break;
3475187d 5541#endif
0f8a249a
BS		 5542 default:
5543 goto illegal_insn;
5544 }
5545 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5546 if (gen_trap_ifnofpu(dc)) {
a80dde08 5547 goto jmp_insn;
5b12f1e8 5548 }
0f8a249a 5549 switch (xop) {
b89e94af 5550 case 0x24: /* stf, store fpreg */
cb21b4da
RH		 5551 gen_address_mask(dc, cpu_addr);
5552 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5553 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
316b6783 5554 dc->mem_idx, MO_TEUL | MO_ALIGN);
0f8a249a
BS		 5555 break;
5556 case 0x25: /* stfsr, V9 stxfsr */
f8641947 5557 {
3a3b925d 5558#ifdef TARGET_SPARC64
f8641947
RH		 5559 gen_address_mask(dc, cpu_addr);
5560 if (rd == 1) {
08149118 5561 tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
316b6783 5562 dc->mem_idx, MO_TEUQ | MO_ALIGN);
f8641947
RH		 5563 break;
5564 }
3a3b925d 5565#endif
08149118 5566 tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
316b6783 5567 dc->mem_idx, MO_TEUL | MO_ALIGN);
f8641947 5568 }
0f8a249a 5569 break;
1f587329
BS		 5570 case 0x26:
5571#ifdef TARGET_SPARC64
1f587329 5572 /* V9 stqf, store quad fpreg */
f939ffe5
RH		 5573 CHECK_FPU_FEATURE(dc, FLOAT128);
5574 gen_address_mask(dc, cpu_addr);
5575 /* ??? While stqf only requires 4-byte alignment, it is
5576 legal for the cpu to signal the unaligned exception.
5577 The OS trap handler is then required to fix it up.
5578 For qemu, this avoids having to probe the second page
5579 before performing the first write. */
5580 cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5581 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
fc313c64 5582 dc->mem_idx, MO_TEUQ | MO_ALIGN_16);
f939ffe5
RH		 5583 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5584 cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5585 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
fc313c64 5586 dc->mem_idx, MO_TEUQ);
1f587329 5587 break;
1f587329
BS		 5588#else /* !TARGET_SPARC64 */
5589 /* stdfq, store floating point queue */
5590#if defined(CONFIG_USER_ONLY)
5591 goto illegal_insn;
5592#else
0f8a249a
BS		 5593 if (!supervisor(dc))
5594 goto priv_insn;
5b12f1e8 5595 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5596 goto jmp_insn;
5b12f1e8 5597 }
0f8a249a 5598 goto nfq_insn;
1f587329 5599#endif
0f8a249a 5600#endif
b89e94af 5601 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5602 gen_address_mask(dc, cpu_addr);
5603 cpu_src1_64 = gen_load_fpr_D(dc, rd);
cb21b4da 5604 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
fc313c64 5605 MO_TEUQ | MO_ALIGN_4);
0f8a249a
BS		 5606 break;
5607 default:
5608 goto illegal_insn;
5609 }
5610 } else if (xop > 0x33 && xop < 0x3f) {
5611 switch (xop) {
a4d17f19 5612#ifdef TARGET_SPARC64
0f8a249a 5613 case 0x34: /* V9 stfa */
5b12f1e8 5614 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5615 goto jmp_insn;
5616 }
22e70060 5617 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5618 break;
1f587329 5619 case 0x36: /* V9 stqfa */
2ea815ca 5620 {
2ea815ca 5621 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5622 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5623 goto jmp_insn;
5624 }
22e70060 5625 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5626 }
1f587329 5627 break;
0f8a249a 5628 case 0x37: /* V9 stdfa */
5b12f1e8 5629 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5630 goto jmp_insn;
5631 }
22e70060 5632 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5633 break;
0f8a249a 5634 case 0x3e: /* V9 casxa */
a4273524
RH		 5635 rs2 = GET_FIELD(insn, 27, 31);
5636 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5637 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5638 break;
16c358e9
SH		 5639#endif
5640#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5641 case 0x3c: /* V9 or LEON3 casa */
5642#ifndef TARGET_SPARC64
5643 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5644#endif
5645 rs2 = GET_FIELD(insn, 27, 31);
5646 cpu_src2 = gen_load_gpr(dc, rs2);
5647 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5648 break;
0f8a249a
BS		 5649#endif
5650 default:
5651 goto illegal_insn;
5652 }
a4273524 5653 } else {
0f8a249a 5654 goto illegal_insn;
a4273524 5655 }
0f8a249a
BS		 5656 }
5657 break;
cf495bcf 5658 }
878cc677 5659 advance_pc(dc);
e80cfcfc 5660 jmp_insn:
a6ca81cb 5661 return;
cf495bcf 5662 illegal_insn:
4fbe0067 5663 gen_exception(dc, TT_ILL_INSN);
a6ca81cb 5664 return;
8f75b8a4 5665#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
e8af50a3 5666 priv_insn:
4fbe0067 5667 gen_exception(dc, TT_PRIV_INSN);
a6ca81cb 5668 return;
64a88d5d 5669#endif
e80cfcfc 5670 nfpu_insn:
4fbe0067 5671 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
a6ca81cb 5672 return;
64a88d5d 5673#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5674 nfq_insn:
4fbe0067 5675 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
a6ca81cb 5676 return;
9143e598 5677#endif
7a3f1944
FB		 5678}
5679
6e61bc94 5680static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7a3f1944 5681{
6e61bc94 5682 DisasContext *dc = container_of(dcbase, DisasContext, base);
b77af26e 5683 CPUSPARCState *env = cpu_env(cs);
6e61bc94 5684 int bound;
af00be49
EC		 5685
5686 dc->pc = dc->base.pc_first;
6e61bc94 5687 dc->npc = (target_ulong)dc->base.tb->cs_base;
8393617c 5688 dc->cc_op = CC_OP_DYNAMIC;
6e61bc94 5689 dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
576e1c4c 5690 dc->def = &env->def;
6e61bc94
EC		 5691 dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
5692 dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
c9b459aa 5693#ifndef CONFIG_USER_ONLY
6e61bc94 5694 dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
c9b459aa 5695#endif
a6d567e5 5696#ifdef TARGET_SPARC64
f9c816c0 5697 dc->fprs_dirty = 0;
6e61bc94 5698 dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
c9b459aa 5699#ifndef CONFIG_USER_ONLY
6e61bc94 5700 dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
c9b459aa 5701#endif
a6d567e5 5702#endif
6e61bc94
EC		 5703 /*
5704 * if we reach a page boundary, we stop generation so that the
5705 * PC of a TT_TFAULT exception is always in the right page
5706 */
5707 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
5708 dc->base.max_insns = MIN(dc->base.max_insns, bound);
5709}
cf495bcf 5710
6e61bc94
EC		 5711static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
5712{
5713}
190ce7fb 5714
6e61bc94
EC		 5715static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
5716{
5717 DisasContext *dc = container_of(dcbase, DisasContext, base);
633c4283 5718 target_ulong npc = dc->npc;
667b8e29 5719
633c4283
RH		 5720 if (npc & 3) {
5721 switch (npc) {
5722 case JUMP_PC:
5723 assert(dc->jump_pc[1] == dc->pc + 4);
5724 npc = dc->jump_pc[0] | JUMP_PC;
5725 break;
5726 case DYNAMIC_PC:
5727 case DYNAMIC_PC_LOOKUP:
5728 npc = DYNAMIC_PC;
5729 break;
5730 default:
5731 g_assert_not_reached();
5732 }
6e61bc94 5733 }
633c4283 5734 tcg_gen_insn_start(dc->pc, npc);
6e61bc94 5735}
b933066a 5736
6e61bc94
EC		 5737static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
5738{
5739 DisasContext *dc = container_of(dcbase, DisasContext, base);
b77af26e 5740 CPUSPARCState *env = cpu_env(cs);
6e61bc94 5741 unsigned int insn;
0f8a249a 5742
4e116893 5743 insn = translator_ldl(env, &dc->base, dc->pc);
6e61bc94 5744 dc->base.pc_next += 4;
878cc677
RH		 5745
5746 if (!decode(dc, insn)) {
5747 disas_sparc_legacy(dc, insn);
5748 }
e80cfcfc 5749
6e61bc94
EC		 5750 if (dc->base.is_jmp == DISAS_NORETURN) {
5751 return;
5752 }
5753 if (dc->pc != dc->base.pc_next) {
5754 dc->base.is_jmp = DISAS_TOO_MANY;
b09b2fd3 5755 }
6e61bc94
EC		 5756}
5757
5758static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
5759{
5760 DisasContext *dc = container_of(dcbase, DisasContext, base);
186e7890 5761 DisasDelayException *e, *e_next;
633c4283 5762 bool may_lookup;
6e61bc94 5763
46bb0137
MCA		 5764 switch (dc->base.is_jmp) {
5765 case DISAS_NEXT:
5766 case DISAS_TOO_MANY:
633c4283 5767 if (((dc->pc | dc->npc) & 3) == 0) {
72cbca10 5768 /* static PC and NPC: we can use direct chaining */
2f5680ee 5769 gen_goto_tb(dc, 0, dc->pc, dc->npc);
633c4283
RH		 5770 break;
5771 }
5772
930f1865 5773 may_lookup = true;
633c4283
RH		 5774 if (dc->pc & 3) {
5775 switch (dc->pc) {
5776 case DYNAMIC_PC_LOOKUP:
633c4283
RH		 5777 break;
5778 case DYNAMIC_PC:
5779 may_lookup = false;
5780 break;
5781 default:
5782 g_assert_not_reached();
b09b2fd3 5783 }
633c4283
RH		 5784 } else {
5785 tcg_gen_movi_tl(cpu_pc, dc->pc);
633c4283
RH		 5786 }
5787
930f1865
RH		 5788 if (dc->npc & 3) {
5789 switch (dc->npc) {
5790 case JUMP_PC:
5791 gen_generic_branch(dc);
5792 break;
5793 case DYNAMIC_PC:
5794 may_lookup = false;
5795 break;
5796 case DYNAMIC_PC_LOOKUP:
5797 break;
5798 default:
5799 g_assert_not_reached();
5800 }
5801 } else {
5802 tcg_gen_movi_tl(cpu_npc, dc->npc);
5803 }
633c4283
RH		 5804 if (may_lookup) {
5805 tcg_gen_lookup_and_goto_ptr();
5806 } else {
07ea28b4 5807 tcg_gen_exit_tb(NULL, 0);
72cbca10 5808 }
46bb0137
MCA		 5809 break;
5810
5811 case DISAS_NORETURN:
5812 break;
5813
5814 case DISAS_EXIT:
5815 /* Exit TB */
5816 save_state(dc);
5817 tcg_gen_exit_tb(NULL, 0);
5818 break;
5819
5820 default:
5821 g_assert_not_reached();
72cbca10 5822 }
186e7890
RH		 5823
5824 for (e = dc->delay_excp_list; e ; e = e_next) {
5825 gen_set_label(e->lab);
5826
5827 tcg_gen_movi_tl(cpu_pc, e->pc);
5828 if (e->npc % 4 == 0) {
5829 tcg_gen_movi_tl(cpu_npc, e->npc);
5830 }
5831 gen_helper_raise_exception(tcg_env, e->excp);
5832
5833 e_next = e->next;
5834 g_free(e);
5835 }
6e61bc94
EC		 5836}
5837
8eb806a7
RH		 5838static void sparc_tr_disas_log(const DisasContextBase *dcbase,
5839 CPUState *cpu, FILE *logfile)
6e61bc94 5840{
8eb806a7
RH		 5841 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
5842 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
6e61bc94
EC		 5843}
5844
5845static const TranslatorOps sparc_tr_ops = {
5846 .init_disas_context = sparc_tr_init_disas_context,
5847 .tb_start = sparc_tr_tb_start,
5848 .insn_start = sparc_tr_insn_start,
6e61bc94
EC		 5849 .translate_insn = sparc_tr_translate_insn,
5850 .tb_stop = sparc_tr_tb_stop,
5851 .disas_log = sparc_tr_disas_log,
5852};
5853
597f9b2d 5854void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
306c8721 5855 target_ulong pc, void *host_pc)
6e61bc94
EC		 5856{
5857 DisasContext dc = {};
5858
306c8721 5859 translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base);
7a3f1944
FB		 5860}
5861
55c3ceef 5862void sparc_tcg_init(void)
e80cfcfc 5863{
d2dc4069 5864 static const char gregnames[32][4] = {
0ea63844 5865 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5866 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5867 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5868 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5869 };
0ea63844 5870 static const char fregnames[32][4] = {
30038fd8
RH		 5871 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5872 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5873 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5874 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5875 };
aaed909a 5876
0ea63844 5877 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5878#ifdef TARGET_SPARC64
0ea63844 5879 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5880 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
0ea63844
RH		 5881#endif
5882 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5883 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5884 };
5885
5886 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5887#ifdef TARGET_SPARC64
5888 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
1a2fb1c0 5889#endif
0ea63844
RH		 5890 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5891 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5892 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5893 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5894 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5895 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5896 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5897 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
0ea63844 5898 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
0ea63844
RH		 5899 };
5900
5901 unsigned int i;
5902
ad75a51e 5903 cpu_regwptr = tcg_global_mem_new_ptr(tcg_env,
0ea63844
RH		 5904 offsetof(CPUSPARCState, regwptr),
5905 "regwptr");
5906
5907 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
ad75a51e 5908 *r32[i].ptr = tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i].name);
0ea63844
RH		 5909 }
5910
5911 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
ad75a51e 5912 *rtl[i].ptr = tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].name);
0ea63844
RH		 5913 }
5914
f764718d 5915 cpu_regs[0] = NULL;
0ea63844 5916 for (i = 1; i < 8; ++i) {
ad75a51e 5917 cpu_regs[i] = tcg_global_mem_new(tcg_env,
d2dc4069
RH		 5918 offsetof(CPUSPARCState, gregs[i]),
5919 gregnames[i]);
5920 }
5921
5922 for (i = 8; i < 32; ++i) {
5923 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5924 (i - 8) * sizeof(target_ulong),
5925 gregnames[i]);
0ea63844
RH		 5926 }
5927
5928 for (i = 0; i < TARGET_DPREGS; i++) {
ad75a51e 5929 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
0ea63844
RH		 5930 offsetof(CPUSPARCState, fpr[i]),
5931 fregnames[i]);
1a2fb1c0 5932 }
658138bc 5933}
d2856f1a 5934
f36aaa53
RH		 5935void sparc_restore_state_to_opc(CPUState *cs,
5936 const TranslationBlock *tb,
5937 const uint64_t *data)
d2856f1a 5938{
f36aaa53
RH		 5939 SPARCCPU *cpu = SPARC_CPU(cs);
5940 CPUSPARCState *env = &cpu->env;
bad729e2
RH		 5941 target_ulong pc = data[0];
5942 target_ulong npc = data[1];
5943
5944 env->pc = pc;
6c42444f 5945 if (npc == DYNAMIC_PC) {
d2856f1a 5946 /* dynamic NPC: already stored */
6c42444f 5947 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5948 /* jump PC: use 'cond' and the jump targets of the translation */
5949 if (env->cond) {
6c42444f 5950 env->npc = npc & ~3;
d7da2a10 5951 } else {
6c42444f 5952 env->npc = pc + 4;
d7da2a10 5953 }
d2856f1a
AJ		 5954 } else {
5955 env->npc = npc;
5956 }
5957}
Mirror of https://git.qemu.org/git/qemu.git