[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25469
	* z80-dis.c: Add support for GBZ80 opcodes.

2020-02-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.

2020-02-03  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-02-01  Alan Modra  <amodra@gmail.com>

	* frv-ibld.c: Regenerate.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	(OP_E_memory): Replace xmm_mdq_mode case label by
	vex_scalar_w_dq_mode one.
	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	(intel_operand_size): Drop vex_w_dq_mode case label.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	(dis386): Use them to replace C2/C3 table entries.
	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	* i386-tbl.h: Re-generate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	forms.
	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_dp): Make unsigned.

2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
	    Jan Beulich  <jbeulich@suse.com>

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.

2020-01-27  Tamar Christina  <tamar.christina@arm.com>

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (sysret): Drop DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	Dword.
	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	* i386-tbl.h: Re-generate.

2020-01-20  Nick Clifton  <nickc@redhat.com>

	* po/de.po: Updated German translation.
	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	* po/uk.po: Updated Ukranian translation.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* hppa-dis.c (fput_const): Remove useless cast.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* arm-dis.c (print_insn_arm): Wrap 'T' value.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.
	* po/opcodes.pot: Regenerate.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	Binutils 2.34 branch created.

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.

2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: Drop stale comment from XOP section.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	(extractps): Add VexWIG to SSE2AVX forms.
	* i386-tbl.h: Re-generate.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	Size64 from and use VexW1 on SSE2AVX forms.
	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	* i386-tbl.h: Re-generate.

2020-01-15  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.

2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25377
	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.

2020-01-14  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.

2020-01-13  Thomas Troeger  <tstroege@gmx.de>

	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

	* arc-opc.c (C_NE): Make it required.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c: Formatting.
	* score7-dis.c: Formatting.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_print_register): Remove dead code.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* fr30-ibld.c: Regenerate.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.

2020-01-09  Nick Clifton  <nickc@redhat.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.

2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.

2020-01-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (SEP_Fixup): New.
	(SEP): Define.
	(dis386_twobyte): Use it for sysenter/sysexit.
	(enum x86_64_isa): Change amd64 enumerator to value 1.
	(OP_J): Compare isa64 against intel64 instead of amd64.
	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	forms.
	* i386-tbl.h: Re-generate.

2020-01-08  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.

2020-01-07  Shahab Vahedi  <shahab@synopsys.com>

	* arc-tbl.h (llock): Use 'LLOCK' as class.
	(llockd): Likewise.
	(scond): Use 'SCOND' as class.
	(scondd): Likewise.
	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	(scondd): Likewise.

2020-01-06  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-06  Alan Modra  <amodra@gmail.com>

	PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* m32r-ibld.c: Regenerate.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Use
	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
	forms of SUDOT and USDOT.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
	uzip{1,2}.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
	FMMLA encoding.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>

	* z80-dis.c: Add support for eZ80 and Z80 instructions.

2020-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2019
\f
Copyright (C) 2020 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
9fc0b501 SB	1	2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
	2
	3	PR 25469
	4	* z80-dis.c: Add support for GBZ80 opcodes.
	5
c5d7be0c AM	6	2020-02-04 Alan Modra <amodra@gmail.com>
	7
	8	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
	9
44e4546f AM	10	2020-02-03 Alan Modra <amodra@gmail.com>
	11
	12	* m32c-ibld.c: Regenerate.
	13
b2b1453a AM	14	2020-02-01 Alan Modra <amodra@gmail.com>
	15
	16	* frv-ibld.c: Regenerate.
	17
4102be5c JB	18	2020-01-31 Jan Beulich <jbeulich@suse.com>
	19
	20	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	21	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	22	(OP_E_memory): Replace xmm_mdq_mode case label by
	23	vex_scalar_w_dq_mode one.
	24	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
	25
825bd36c JB	26	2020-01-31 Jan Beulich <jbeulich@suse.com>
	27
	28	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	29	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	30	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	31	(intel_operand_size): Drop vex_w_dq_mode case label.
	32
c3036ed0 RS	33	2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
	34
	35	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	36	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
	37
0c115f84 AM	38	2020-01-30 Alan Modra <amodra@gmail.com>
	39
	40	* m32c-ibld.c: Regenerate.
	41
bd434cc4 JM	42	2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
	43
	44	* bpf-opc.c: Regenerate.
	45
aeab2b26 JB	46	2020-01-30 Jan Beulich <jbeulich@suse.com>
	47
	48	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	49	(dis386): Use them to replace C2/C3 table entries.
	50	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	51	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	52	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	53	* i386-tbl.h: Re-generate.
	54
62b3f548 JB	55	2020-01-30 Jan Beulich <jbeulich@suse.com>
	56
	57	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	58	forms.
	59	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	60	DefaultSize.
	61	* i386-tbl.h: Re-generate.
	62
1bd8ae10 AM	63	2020-01-30 Alan Modra <amodra@gmail.com>
	64
	65	* tic4x-dis.c (tic4x_dp): Make unsigned.
	66
bc31405e L	67	2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
	68	Jan Beulich <jbeulich@suse.com>
	69
	70	PR binutils/25445
	71	* i386-dis.c (MOVSXD_Fixup): New function.
	72	(movsxd_mode): New enum.
	73	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	74	(intel_operand_size): Handle movsxd_mode.
	75	(OP_E_register): Likewise.
	76	(OP_G): Likewise.
	77	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	78	register on movsxd. Add movsxd with 16-bit destination register
	79	for AMD64 and Intel64 ISAs.
	80	* i386-tbl.h: Regenerated.
	81
7568c93b TC	82	2020-01-27 Tamar Christina <tamar.christina@arm.com>
	83
	84	PR 25403
	85	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	86	* aarch64-asm-2.c: Regenerate
	87	* aarch64-dis-2.c: Likewise.
	88	* aarch64-opc-2.c: Likewise.
	89
c006a730 JB	90	2020-01-21 Jan Beulich <jbeulich@suse.com>
	91
	92	* i386-opc.tbl (sysret): Drop DefaultSize.
	93	* i386-tbl.h: Re-generate.
	94
c906a69a JB	95	2020-01-21 Jan Beulich <jbeulich@suse.com>
	96
	97	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	98	Dword.
	99	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	100	* i386-tbl.h: Re-generate.
	101
26916852 NC	102	2020-01-20 Nick Clifton <nickc@redhat.com>
	103
	104	* po/de.po: Updated German translation.
	105	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	106	* po/uk.po: Updated Ukranian translation.
	107
4d6cbb64 AM	108	2020-01-20 Alan Modra <amodra@gmail.com>
	109
	110	* hppa-dis.c (fput_const): Remove useless cast.
	111
2bddb71a AM	112	2020-01-20 Alan Modra <amodra@gmail.com>
	113
	114	* arm-dis.c (print_insn_arm): Wrap 'T' value.
	115
1b1bb2c6 NC	116	2020-01-18 Nick Clifton <nickc@redhat.com>
	117
	118	* configure: Regenerate.
	119	* po/opcodes.pot: Regenerate.
	120
ae774686 NC	121	2020-01-18 Nick Clifton <nickc@redhat.com>
	122
	123	Binutils 2.34 branch created.
	124
07f1f3aa CB	125	2020-01-17 Christian Biesinger <cbiesinger@google.com>
	126
	127	* opintl.h: Fix spelling error (seperate).
	128
42e04b36 L	129	2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
	130
	131	* i386-opc.tbl: Add {vex} pseudo prefix.
	132	* i386-tbl.h: Regenerated.
	133
2da2eaf4 AV	134	2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
	135
	136	PR 25376
	137	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	138	(neon_opcodes): Likewise.
	139	(select_arm_features): Make sure we enable MVE bits when selecting
	140	armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
	141	any architecture.
	142
d0849eed JB	143	2020-01-16 Jan Beulich <jbeulich@suse.com>
	144
	145	* i386-opc.tbl: Drop stale comment from XOP section.
	146
9cf70a44 JB	147	2020-01-16 Jan Beulich <jbeulich@suse.com>
	148
	149	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	150	(extractps): Add VexWIG to SSE2AVX forms.
	151	* i386-tbl.h: Re-generate.
	152
4814632e JB	153	2020-01-16 Jan Beulich <jbeulich@suse.com>
	154
	155	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	156	Size64 from and use VexW1 on SSE2AVX forms.
	157	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	158	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	159	* i386-tbl.h: Re-generate.
	160
aad09917 AM	161	2020-01-15 Alan Modra <amodra@gmail.com>
	162
	163	* tic4x-dis.c (tic4x_version): Make unsigned long.
	164	(optab, optab_special, registernames): New file scope vars.
	165	(tic4x_print_register): Set up registernames rather than
	166	malloc'd registertable.
	167	(tic4x_disassemble): Delete optable and optable_special. Use
	168	optab and optab_special instead. Throw away old optab,
	169	optab_special and registernames when info->mach changes.
	170
7a6bf3be SB	171	2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
	172
	173	PR 25377
	174	* z80-dis.c (suffix): Use .db instruction to generate double
	175	prefix.
	176
ca1eaac0 AM	177	2020-01-14 Alan Modra <amodra@gmail.com>
	178
	179	* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
	180	values to unsigned before shifting.
	181
1d67fe3b TT	182	2020-01-13 Thomas Troeger <tstroege@gmx.de>
	183
	184	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	185	flow instructions.
	186	(print_insn_thumb16, print_insn_thumb32): Likewise.
	187	(print_insn): Initialize the insn info.
	188	* i386-dis.c (print_insn): Initialize the insn info fields, and
	189	detect jumps.
	190
5e4f7e05 CZ	191	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	192
	193	* arc-opc.c (C_NE): Make it required.
	194
b9fe6b8a CZ	195	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	196
	197	* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	198	reserved register name.
	199
90dee485 AM	200	2020-01-13 Alan Modra <amodra@gmail.com>
	201
	202	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	203	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
	204
febda64f AM	205	2020-01-13 Alan Modra <amodra@gmail.com>
	206
	207	* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
	208	result of wasm_read_leb128 in a uint64_t and check that bits
	209	are not lost when copying to other locals. Use uint32_t for
	210	most locals. Use PRId64 when printing int64_t.
	211
df08b588 AM	212	2020-01-13 Alan Modra <amodra@gmail.com>
	213
	214	* score-dis.c: Formatting.
	215	* score7-dis.c: Formatting.
	216
b2c759ce AM	217	2020-01-13 Alan Modra <amodra@gmail.com>
	218
	219	* score-dis.c (print_insn_score48): Use unsigned variables for
	220	unsigned values. Don't left shift negative values.
	221	(print_insn_score32): Likewise.
	222	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
	223
5496abe1 AM	224	2020-01-13 Alan Modra <amodra@gmail.com>
	225
	226	* tic4x-dis.c (tic4x_print_register): Remove dead code.
	227
202e762b AM	228	2020-01-13 Alan Modra <amodra@gmail.com>
	229
	230	* fr30-ibld.c: Regenerate.
	231
7ef412cf AM	232	2020-01-13 Alan Modra <amodra@gmail.com>
	233
	234	* xgate-dis.c (print_insn): Don't left shift signed value.
	235	(ripBits): Formatting, use 1u.
	236
7f578b95 AM	237	2020-01-10 Alan Modra <amodra@gmail.com>
	238
	239	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	240	* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
	241
441af85b AM	242	2020-01-10 Alan Modra <amodra@gmail.com>
	243
	244	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	245	and XRREG value earlier to avoid a shift with negative exponent.
	246	* m10200-dis.c (disassemble): Similarly.
	247
bce58db4 NC	248	2020-01-09 Nick Clifton <nickc@redhat.com>
	249
	250	PR 25224
	251	* z80-dis.c (ld_ii_ii): Use correct cast.
	252
40c75bc8 SB	253	2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
	254
	255	PR 25224
	256	* z80-dis.c (ld_ii_ii): Use character constant when checking
	257	opcode byte value.
	258
d835a58b JB	259	2020-01-09 Jan Beulich <jbeulich@suse.com>
	260
	261	* i386-dis.c (SEP_Fixup): New.
	262	(SEP): Define.
	263	(dis386_twobyte): Use it for sysenter/sysexit.
	264	(enum x86_64_isa): Change amd64 enumerator to value 1.
	265	(OP_J): Compare isa64 against intel64 instead of amd64.
	266	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	267	forms.
	268	* i386-tbl.h: Re-generate.
	269
030a2e78 AM	270	2020-01-08 Alan Modra <amodra@gmail.com>
	271
	272	* z8k-dis.c: Include libiberty.h
	273	(instr_data_s): Make max_fetched unsigned.
	274	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	275	Don't exceed byte_info bounds.
	276	(output_instr): Make num_bytes unsigned.
	277	(unpack_instr): Likewise for nibl_count and loop.
	278	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	279	idx unsigned.
	280	* z8k-opc.h: Regenerate.
	281
bb82aefe SV	282	2020-01-07 Shahab Vahedi <shahab@synopsys.com>
	283
	284	* arc-tbl.h (llock): Use 'LLOCK' as class.
	285	(llockd): Likewise.
	286	(scond): Use 'SCOND' as class.
	287	(scondd): Likewise.
	288	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	289	(scondd): Likewise.
	290
cc6aa1a6 AM	291	2020-01-06 Alan Modra <amodra@gmail.com>
	292
	293	* m32c-ibld.c: Regenerate.
	294
660e62b1 AM	295	2020-01-06 Alan Modra <amodra@gmail.com>
	296
	297	PR 25344
	298	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	299	Peek at next byte to prevent recursion on repeated prefix bytes.
	300	Ensure uninitialised "mybuf" is not accessed.
	301	(print_insn_z80): Don't zero n_fetch and n_used here,..
	302	(print_insn_z80_buf): ..do it here instead.
	303
c9ae58fe AM	304	2020-01-04 Alan Modra <amodra@gmail.com>
	305
	306	* m32r-ibld.c: Regenerate.
	307
5f57d4ec AM	308	2020-01-04 Alan Modra <amodra@gmail.com>
	309
	310	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
	311
2c5c1196 AM	312	2020-01-04 Alan Modra <amodra@gmail.com>
	313
	314	* crx-dis.c (match_opcode): Avoid shift left of signed value.
	315
2e98c6c5 AM	316	2020-01-04 Alan Modra <amodra@gmail.com>
	317
	318	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
	319
567dfba2 JB	320	2020-01-03 Jan Beulich <jbeulich@suse.com>
567dfba2 JB	321
5437a02a JB	322	* aarch64-tbl.h (aarch64_opcode_table): Use
	323	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
	324
	325	2020-01-03 Jan Beulich <jbeulich@suse.com>
	326
	327	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2 JB	328	forms of SUDOT and USDOT.
567dfba2 JB	329
8c45011a JB	330	2020-01-03 Jan Beulich <jbeulich@suse.com>
8c45011a JB	331
5437a02a	332	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a JB	333	uzip{1,2}.
	334	* opcodes/aarch64-dis-2.c: Re-generate.
	335
f4950f76 JB	336	2020-01-03 Jan Beulich <jbeulich@suse.com>
f4950f76 JB	337
5437a02a	338	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76 JB	339	FMMLA encoding.
	340	* opcodes/aarch64-dis-2.c: Re-generate.
	341
6655dba2 SB	342	2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
	343
	344	* z80-dis.c: Add support for eZ80 and Z80 instructions.
	345
b14ce8bf AM	346	2020-01-01 Alan Modra <amodra@gmail.com>
	347
	348	Update year range in copyright notice of all files.
	349
0b114740	350	For older changes see ChangeLog-2019
3499769a	351	\f
0b114740	352	Copyright (C) 2020 Free Software Foundation, Inc.
3499769a AM	353
	354	Copying and distribution of this file, with or without modification,
	355	are permitted in any medium without royalty provided the copyright
	356	notice and this notice are preserved.
	357
	358	Local Variables:
	359	mode: change-log
	360	left-margin: 8
	361	fill-column: 74
	362	version-control: never
	363	End: