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2002-02-27 Fred Fish <fnf@redhat.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
c5d00cc7
CD		 12002-02-18 Chris Demetriou <cgd@broadcom.com>
2
3 * mips.igen: For all functions and instructions, list model
4 names that support that instruction one per line.
5
074e9cb8
CD		 62002-02-11 Chris Demetriou <cgd@broadcom.com>
7
8 * mips.igen: Add some additional comments about supported
9 models, and about which instructions go where.
10 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
11 order as is used in the rest of the file.
12
9805e229
CD		 132002-02-11 Chris Demetriou <cgd@broadcom.com>
14
15 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
16 indicating that ALU32_END or ALU64_END are there to check
17 for overflow.
18 (DADD): Likewise, but also remove previous comment about
19 overflow checking.
20
f701dad2
CD		 212002-02-10 Chris Demetriou <cgd@broadcom.com>
22
23 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
24 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
25 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
26 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
27 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
28 fields (i.e., add and move commas) so that they more closely
29 match the MIPS ISA documentation opcode partitioning.
30
312002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 32
33 * mips.igen (ADDI): Print immediate value.
34 (BREAK): Print code.
35 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
36 (SLL): Print "nop" specially, and don't run the code
37 that does the shift for the "nop" case.
38
9e52972e
FF		 392001-11-17 Fred Fish <fnf@redhat.com>
40
41 * sim-main.h (float_operation): Move enum declaration outside
42 of _sim_cpu struct declaration.
43
c0efbca4
JB		 442001-04-12 Jim Blandy <jimb@redhat.com>
45
46 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
47 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
48 set of the FCSR.
49 * sim-main.h (COCIDX): Remove definition; this isn't supported by
50 PENDING_FILL, and you can get the intended effect gracefully by
51 calling PENDING_SCHED directly.
52
fb891446
BE		 532001-02-23 Ben Elliston <bje@redhat.com>
54
55 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
56 already defined elsewhere.
57
8030f857
BE		 582001-02-19 Ben Elliston <bje@redhat.com>
59
60 * sim-main.h (sim_monitor): Return an int.
61 * interp.c (sim_monitor): Add return values.
62 (signal_exception): Handle error conditions from sim_monitor.
63
56b48a7a
CD		 642001-02-08 Ben Elliston <bje@redhat.com>
65
66 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
67 (store_memory): Likewise, pass cia to sim_core_write*.
68
d3ee60d9
FCE		 692000-10-19 Frank Ch. Eigler <fche@redhat.com>
70
71 On advice from Chris G. Demetriou <cgd@sibyte.com>:
72 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
73
071da002
AC		 74Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
75
76 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
77 * Makefile.in: Don't delete *.igen when cleaning directory.
78
a28c02cd
AC		 79Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
80
81 * m16.igen (break): Call SignalException not sim_engine_halt.
82
80ee11fa
AC		 83Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
84
85 From Jason Eckhardt:
86 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
87
673388c0
AC		 88Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
89
90 * mips.igen (MxC1, DMxC1): Fix printf formatting.
91
4c0deff4
NC		 922000-05-24 Michael Hayes <mhayes@cygnus.com>
93
94 * mips.igen (do_dmultx): Fix typo.
95
eb2d80b4
AC		 96Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
97
98 * configure: Regenerated to track ../common/aclocal.m4 changes.
99
dd37a34b
AC		 100Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
101
102 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
103
4c0deff4
NC		 1042000-04-12 Frank Ch. Eigler <fche@redhat.com>
105
106 * sim-main.h (GPR_CLEAR): Define macro.
107
e30db738
AC		 108Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
109
110 * interp.c (decode_coproc): Output long using %lx and not %s.
111
cb7450ea
FCE		 1122000-03-21 Frank Ch. Eigler <fche@redhat.com>
113
114 * interp.c (sim_open): Sort & extend dummy memory regions for
115 --board=jmr3904 for eCos.
116
a3027dd7
FCE		 1172000-03-02 Frank Ch. Eigler <fche@redhat.com>
118
119 * configure: Regenerated.
120
121Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
122
123 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
124 calls, conditional on the simulator being in verbose mode.
125
dfcd3bfb
JM		 126Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
127
128 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
129 cache don't get ReservedInstruction traps.
130
c2d11a7d
JM		 1311999-11-29 Mark Salter <msalter@cygnus.com>
132
133 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
134 to clear status bits in sdisr register. This is how the hardware works.
135
136 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
137 being used by cygmon.
138
4ce44c66
JM		 1391999-11-11 Andrew Haley <aph@cygnus.com>
140
141 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
142 instructions.
143
cff3e48b
JM		 144Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
145
146 * mips.igen (MULT): Correct previous mis-applied patch.
147
d4f3574e
SS		 148Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
149
150 * mips.igen (delayslot32): Handle sequence like
151 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
152 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
153 (MULT): Actually pass the third register...
154
1551999-09-03 Mark Salter <msalter@cygnus.com>
156
157 * interp.c (sim_open): Added more memory aliases for additional
158 hardware being touched by cygmon on jmr3904 board.
159
160Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
161
162 * configure: Regenerated to track ../common/aclocal.m4 changes.
163
a0b3c4fd
JM		 164Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
165
166 * interp.c (sim_store_register): Handle case where client - GDB -
167 specifies that a 4 byte register is 8 bytes in size.
168 (sim_fetch_register): Ditto.
169
adf40b2e
JM		 1701999-07-14 Frank Ch. Eigler <fche@cygnus.com>
171
172 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
173 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
174 (idt_monitor_base): Base address for IDT monitor traps.
175 (pmon_monitor_base): Ditto for PMON.
176 (lsipmon_monitor_base): Ditto for LSI PMON.
177 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
178 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
179 (sim_firmware_command): New function.
180 (mips_option_handler): Call it for OPTION_FIRMWARE.
181 (sim_open): Allocate memory for idt_monitor region. If "--board"
182 option was given, add no monitor by default. Add BREAK hooks only if
183 monitors are also there.
184
43e526b9
JM		 185Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
186
187 * interp.c (sim_monitor): Flush output before reading input.
188
189Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
190
191 * tconfig.in (SIM_HANDLES_LMA): Always define.
192
193Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
194
195 From Mark Salter <msalter@cygnus.com>:
196 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
197 (sim_open): Add setup for BSP board.
198
9846de1b
JM		 199Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
200
201 * mips.igen (MULT, MULTU): Add syntax for two operand version.
202 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
203 them as unimplemented.
204
cd0fc7c3
SS		 2051999-05-08 Felix Lee <flee@cygnus.com>
206
207 * configure: Regenerated to track ../common/aclocal.m4 changes.
208
7a292a7a
SS		 2091999-04-21 Frank Ch. Eigler <fche@cygnus.com>
210
211 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
212
213Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
214
215 * configure.in: Any mips64vr5*-*-* target should have
216 -DTARGET_ENABLE_FR=1.
217 (default_endian): Any mips64vr*el-*-* target should default to
218 LITTLE_ENDIAN.
219 * configure: Re-generate.
220
2211999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
222
223 * mips.igen (ldl): Extend from _16_, not 32.
224
225Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
226
227 * interp.c (sim_store_register): Force registers written to by GDB
228 into an un-interpreted state.
229
c906108c
SS		 2301999-02-05 Frank Ch. Eigler <fche@cygnus.com>
231
232 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
233 CPU, start periodic background I/O polls.
234 (tx3904sio_poll): New function: periodic I/O poller.
235
2361998-12-30 Frank Ch. Eigler <fche@cygnus.com>
237
238 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
239
240Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
241
242 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
243 case statement.
244
2451998-12-29 Frank Ch. Eigler <fche@cygnus.com>
246
247 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
248 (load_word): Call SIM_CORE_SIGNAL hook on error.
249 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
250 starting. For exception dispatching, pass PC instead of NULL_CIA.
251 (decode_coproc): Use COP0_BADVADDR to store faulting address.
252 * sim-main.h (COP0_BADVADDR): Define.
253 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
254 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
255 (_sim_cpu): Add exc_* fields to store register value snapshots.
256 * mips.igen (*): Replace memory-related SignalException* calls
257 with references to SIM_CORE_SIGNAL hook.
258
259 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
260 fix.
261 * sim-main.c (*): Minor warning cleanups.
262
2631998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
264
265 * m16.igen (DADDIU5): Correct type-o.
266
267Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
268
269 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
270 variables.
271
272Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
273
274 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
275 to include path.
276 (interp.o): Add dependency on itable.h
277 (oengine.c, gencode): Delete remaining references.
278 (BUILT_SRC_FROM_GEN): Clean up.
279
2801998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
281
282 * vr4run.c: New.
283 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
284 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
285 tmp-run-hack) : New.
286 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
287 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
288 Drop the "64" qualifier to get the HACK generator working.
289 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
290 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
291 qualifier to get the hack generator working.
292 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
293 (DSLL): Use do_dsll.
294 (DSLLV): Use do_dsllv.
295 (DSRA): Use do_dsra.
296 (DSRL): Use do_dsrl.
297 (DSRLV): Use do_dsrlv.
298 (BC1): Move *vr4100 to get the HACK generator working.
299 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
300 get the HACK generator working.
301 (MACC) Rename to get the HACK generator working.
302 (DMACC,MACCS,DMACCS): Add the 64.
303
3041998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
305
306 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
307 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
308
3091998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
310
311 * mips/interp.c (DEBUG): Cleanups.
312
3131998-12-10 Frank Ch. Eigler <fche@cygnus.com>
314
315 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
316 (tx3904sio_tickle): fflush after a stdout character output.
317
3181998-12-03 Frank Ch. Eigler <fche@cygnus.com>
319
320 * interp.c (sim_close): Uninstall modules.
321
322Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
323
324 * sim-main.h, interp.c (sim_monitor): Change to global
325 function.
326
327Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
328
329 * configure.in (vr4100): Only include vr4100 instructions in
330 simulator.
331 * configure: Re-generate.
332 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
333
334Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
335
336 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
337 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
338 true alternative.
339
340 * configure.in (sim_default_gen, sim_use_gen): Replace with
341 sim_gen.
342 (--enable-sim-igen): Delete config option. Always using IGEN.
343 * configure: Re-generate.
344
345 * Makefile.in (gencode): Kill, kill, kill.
346 * gencode.c: Ditto.
347
348Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
349
350 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
351 bit mips16 igen simulator.
352 * configure: Re-generate.
353
354 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
355 as part of vr4100 ISA.
356 * vr.igen: Mark all instructions as 64 bit only.
357
358Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
359
360 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
361 Pacify GCC.
362
363Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
364
365 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
366 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
367 * configure: Re-generate.
368
369 * m16.igen (BREAK): Define breakpoint instruction.
370 (JALX32): Mark instruction as mips16 and not r3900.
371 * mips.igen (C.cond.fmt): Fix typo in instruction format.
372
373 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
374
375Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
376
377 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
378 insn as a debug breakpoint.
379
380 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
381 pending.slot_size.
382 (PENDING_SCHED): Clean up trace statement.
383 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
384 (PENDING_FILL): Delay write by only one cycle.
385 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
386
387 * sim-main.c (pending_tick): Clean up trace statements. Add trace
388 of pending writes.
389 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
390 32 & 64.
391 (pending_tick): Move incrementing of index to FOR statement.
392 (pending_tick): Only update PENDING_OUT after a write has occured.
393
394 * configure.in: Add explicit mips-lsi-* target. Use gencode to
395 build simulator.
396 * configure: Re-generate.
397
398 * interp.c (sim_engine_run OLD): Delete explicit call to
399 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
400
401Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
402
403 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
404 interrupt level number to match changed SignalExceptionInterrupt
405 macro.
406
407Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
408
409 * interp.c: #include "itable.h" if WITH_IGEN.
410 (get_insn_name): New function.
411 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
412 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
413
414Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
415
416 * configure: Rebuilt to inhale new common/aclocal.m4.
417
418Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
419
420 * dv-tx3904sio.c: Include sim-assert.h.
421
422Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
423
424 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
425 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
426 Reorganize target-specific sim-hardware checks.
427 * configure: rebuilt.
428 * interp.c (sim_open): For tx39 target boards, set
429 OPERATING_ENVIRONMENT, add tx3904sio devices.
430 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
431 ROM executables. Install dv-sockser into sim-modules list.
432
433 * dv-tx3904irc.c: Compiler warning clean-up.
434 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
435 frequent hw-trace messages.
436
437Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
438
439 * vr.igen (MulAcc): Identify as a vr4100 specific function.
440
441Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
442
443 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
444
445 * vr.igen: New file.
446 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
447 * mips.igen: Define vr4100 model. Include vr.igen.
448Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
449
450 * mips.igen (check_mf_hilo): Correct check.
451
452Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
453
454 * sim-main.h (interrupt_event): Add prototype.
455
456 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
457 register_ptr, register_value.
458 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
459
460 * sim-main.h (tracefh): Make extern.
461
462Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
463
464 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
465 Reduce unnecessarily high timer event frequency.
466 * dv-tx3904cpu.c: Ditto for interrupt event.
467
468Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
469
470 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
471 to allay warnings.
472 (interrupt_event): Made non-static.
473
474 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
475 interchange of configuration values for external vs. internal
476 clock dividers.
477
478Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
479
480 * mips.igen (BREAK): Moved code to here for
481 simulator-reserved break instructions.
482 * gencode.c (build_instruction): Ditto.
483 * interp.c (signal_exception): Code moved from here. Non-
484 reserved instructions now use exception vector, rather
485 than halting sim.
486 * sim-main.h: Moved magic constants to here.
487
488Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
489
490 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
491 register upon non-zero interrupt event level, clear upon zero
492 event value.
493 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
494 by passing zero event value.
495 (*_io_{read,write}_buffer): Endianness fixes.
496 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
497 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
498
499 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
500 serial I/O and timer module at base address 0xFFFF0000.
501
502Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
503
504 * mips.igen (SWC1) : Correct the handling of ReverseEndian
505 and BigEndianCPU.
506
507Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
508
509 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
510 parts.
511 * configure: Update.
512
513Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
514
515 * dv-tx3904tmr.c: New file - implements tx3904 timer.
516 * dv-tx3904{irc,cpu}.c: Mild reformatting.
517 * configure.in: Include tx3904tmr in hw_device list.
518 * configure: Rebuilt.
519 * interp.c (sim_open): Instantiate three timer instances.
520 Fix address typo of tx3904irc instance.
521
522Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
523
524 * interp.c (signal_exception): SystemCall exception now uses
525 the exception vector.
526
527Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
528
529 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
530 to allay warnings.
531
532Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
533
534 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
535
536Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
537
538 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
539
540 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
541 sim-main.h. Declare a struct hw_descriptor instead of struct
542 hw_device_descriptor.
543
544Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
545
546 * mips.igen (do_store_left, do_load_left): Compute nr of left and
547 right bits and then re-align left hand bytes to correct byte
548 lanes. Fix incorrect computation in do_store_left when loading
549 bytes from second word.
550
551Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
552
553 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
554 * interp.c (sim_open): Only create a device tree when HW is
555 enabled.
556
557 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
558 * interp.c (signal_exception): Ditto.
559
560Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
561
562 * gencode.c: Mark BEGEZALL as LIKELY.
563
564Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
565
566 * sim-main.h (ALU32_END): Sign extend 32 bit results.
567 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
568
569Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
570
571 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
572 modules. Recognize TX39 target with "mips*tx39" pattern.
573 * configure: Rebuilt.
574 * sim-main.h (*): Added many macros defining bits in
575 TX39 control registers.
576 (SignalInterrupt): Send actual PC instead of NULL.
577 (SignalNMIReset): New exception type.
578 * interp.c (board): New variable for future use to identify
579 a particular board being simulated.
580 (mips_option_handler,mips_options): Added "--board" option.
581 (interrupt_event): Send actual PC.
582 (sim_open): Make memory layout conditional on board setting.
583 (signal_exception): Initial implementation of hardware interrupt
584 handling. Accept another break instruction variant for simulator
585 exit.
586 (decode_coproc): Implement RFE instruction for TX39.
587 (mips.igen): Decode RFE instruction as such.
588 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
589 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
590 bbegin to implement memory map.
591 * dv-tx3904cpu.c: New file.
592 * dv-tx3904irc.c: New file.
593
594Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
595
596 * mips.igen (check_mt_hilo): Create a separate r3900 version.
597
598Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
599
600 * tx.igen (madd,maddu): Replace calls to check_op_hilo
601 with calls to check_div_hilo.
602
603Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
604
605 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
606 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
607 Add special r3900 version of do_mult_hilo.
608 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
609 with calls to check_mult_hilo.
610 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
611 with calls to check_div_hilo.
612
613Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
614
615 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
616 Document a replacement.
617
618Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
619
620 * interp.c (sim_monitor): Make mon_printf work.
621
622Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
623
624 * sim-main.h (INSN_NAME): New arg `cpu'.
625
626Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
627
628 * configure: Regenerated to track ../common/aclocal.m4 changes.
629
630Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
631
632 * configure: Regenerated to track ../common/aclocal.m4 changes.
633 * config.in: Ditto.
634
635Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
636
637 * acconfig.h: New file.
638 * configure.in: Reverted change of Apr 24; use sinclude again.
639
640Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
641
642 * configure: Regenerated to track ../common/aclocal.m4 changes.
643 * config.in: Ditto.
644
645Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
646
647 * configure.in: Don't call sinclude.
648
649Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
650
651 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
652
653Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
654
655 * mips.igen (ERET): Implement.
656
657 * interp.c (decode_coproc): Return sign-extended EPC.
658
659 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
660
661 * interp.c (signal_exception): Do not ignore Trap.
662 (signal_exception): On TRAP, restart at exception address.
663 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
664 (signal_exception): Update.
665 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
666 so that TRAP instructions are caught.
667
668Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
669
670 * sim-main.h (struct hilo_access, struct hilo_history): Define,
671 contains HI/LO access history.
672 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
673 (HIACCESS, LOACCESS): Delete, replace with
674 (HIHISTORY, LOHISTORY): New macros.
675 (CHECKHILO): Delete all, moved to mips.igen
676
677 * gencode.c (build_instruction): Do not generate checks for
678 correct HI/LO register usage.
679
680 * interp.c (old_engine_run): Delete checks for correct HI/LO
681 register usage.
682
683 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
684 check_mf_cycles): New functions.
685 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
686 do_divu, domultx, do_mult, do_multu): Use.
687
688 * tx.igen ("madd", "maddu"): Use.
689
690Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
691
692 * mips.igen (DSRAV): Use function do_dsrav.
693 (SRAV): Use new function do_srav.
694
695 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
696 (B): Sign extend 11 bit immediate.
697 (EXT-B*): Shift 16 bit immediate left by 1.
698 (ADDIU*): Don't sign extend immediate value.
699
700Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
701
702 * m16run.c (sim_engine_run): Restore CIA after handling an event.
703
704 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
705 functions.
706
707 * mips.igen (delayslot32, nullify_next_insn): New functions.
708 (m16.igen): Always include.
709 (do_*): Add more tracing.
710
711 * m16.igen (delayslot16): Add NIA argument, could be called by a
712 32 bit MIPS16 instruction.
713
714 * interp.c (ifetch16): Move function from here.
715 * sim-main.c (ifetch16): To here.
716
717 * sim-main.c (ifetch16, ifetch32): Update to match current
718 implementations of LH, LW.
719 (signal_exception): Don't print out incorrect hex value of illegal
720 instruction.
721
722Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
723
724 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
725 instruction.
726
727 * m16.igen: Implement MIPS16 instructions.
728
729 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
730 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
731 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
732 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
733 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
734 bodies of corresponding code from 32 bit insn to these. Also used
735 by MIPS16 versions of functions.
736
737 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
738 (IMEM16): Drop NR argument from macro.
739
740Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
741
742 * Makefile.in (SIM_OBJS): Add sim-main.o.
743
744 * sim-main.h (address_translation, load_memory, store_memory,
745 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
746 as INLINE_SIM_MAIN.
747 (pr_addr, pr_uword64): Declare.
748 (sim-main.c): Include when H_REVEALS_MODULE_P.
749
750 * interp.c (address_translation, load_memory, store_memory,
751 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
752 from here.
753 * sim-main.c: To here. Fix compilation problems.
754
755 * configure.in: Enable inlining.
756 * configure: Re-config.
757
758Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
759
760 * configure: Regenerated to track ../common/aclocal.m4 changes.
761
762Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
763
764 * mips.igen: Include tx.igen.
765 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
766 * tx.igen: New file, contains MADD and MADDU.
767
768 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
769 the hardwired constant `7'.
770 (store_memory): Ditto.
771 (LOADDRMASK): Move definition to sim-main.h.
772
773 mips.igen (MTC0): Enable for r3900.
774 (ADDU): Add trace.
775
776 mips.igen (do_load_byte): Delete.
777 (do_load, do_store, do_load_left, do_load_write, do_store_left,
778 do_store_right): New functions.
779 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
780
781 configure.in: Let the tx39 use igen again.
782 configure: Update.
783
784Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
785
786 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
787 not an address sized quantity. Return zero for cache sizes.
788
789Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
790
791 * mips.igen (r3900): r3900 does not support 64 bit integer
792 operations.
793
794Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
795
796 * configure.in (mipstx39*-*-*): Use gencode simulator rather
797 than igen one.
798 * configure : Rebuild.
799
800Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
801
802 * configure: Regenerated to track ../common/aclocal.m4 changes.
803
804Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
805
806 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
807
808Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
809
810 * configure: Regenerated to track ../common/aclocal.m4 changes.
811 * config.in: Regenerated to track ../common/aclocal.m4 changes.
812
813Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
814
815 * configure: Regenerated to track ../common/aclocal.m4 changes.
816
817Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
818
819 * interp.c (Max, Min): Comment out functions. Not yet used.
820
821Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
822
823 * configure: Regenerated to track ../common/aclocal.m4 changes.
824
825Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
826
827 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
828 configurable settings for stand-alone simulator.
829
830 * configure.in: Added X11 search, just in case.
831
832 * configure: Regenerated.
833
834Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
835
836 * interp.c (sim_write, sim_read, load_memory, store_memory):
837 Replace sim_core_*_map with read_map, write_map, exec_map resp.
838
839Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
840
841 * sim-main.h (GETFCC): Return an unsigned value.
842
843Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
844
845 * mips.igen (DIV): Fix check for -1 / MIN_INT.
846 (DADD): Result destination is RD not RT.
847
848Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
849
850 * sim-main.h (HIACCESS, LOACCESS): Always define.
851
852 * mdmx.igen (Maxi, Mini): Rename Max, Min.
853
854 * interp.c (sim_info): Delete.
855
856Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
857
858 * interp.c (DECLARE_OPTION_HANDLER): Use it.
859 (mips_option_handler): New argument `cpu'.
860 (sim_open): Update call to sim_add_option_table.
861
862Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
863
864 * mips.igen (CxC1): Add tracing.
865
866Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
867
868 * sim-main.h (Max, Min): Declare.
869
870 * interp.c (Max, Min): New functions.
871
872 * mips.igen (BC1): Add tracing.
873
874Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
875
876 * interp.c Added memory map for stack in vr4100
877
878Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
879
880 * interp.c (load_memory): Add missing "break"'s.
881
882Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
883
884 * interp.c (sim_store_register, sim_fetch_register): Pass in
885 length parameter. Return -1.
886
887Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
888
889 * interp.c: Added hardware init hook, fixed warnings.
890
891Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
892
893 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
894
895Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
896
897 * interp.c (ifetch16): New function.
898
899 * sim-main.h (IMEM32): Rename IMEM.
900 (IMEM16_IMMED): Define.
901 (IMEM16): Define.
902 (DELAY_SLOT): Update.
903
904 * m16run.c (sim_engine_run): New file.
905
906 * m16.igen: All instructions except LB.
907 (LB): Call do_load_byte.
908 * mips.igen (do_load_byte): New function.
909 (LB): Call do_load_byte.
910
911 * mips.igen: Move spec for insn bit size and high bit from here.
912 * Makefile.in (tmp-igen, tmp-m16): To here.
913
914 * m16.dc: New file, decode mips16 instructions.
915
916 * Makefile.in (SIM_NO_ALL): Define.
917 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
918
919Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
922 point unit to 32 bit registers.
923 * configure: Re-generate.
924
925Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
926
927 * configure.in (sim_use_gen): Make IGEN the default simulator
928 generator for generic 32 and 64 bit mips targets.
929 * configure: Re-generate.
930
931Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
932
933 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
934 bitsize.
935
936 * interp.c (sim_fetch_register, sim_store_register): Read/write
937 FGR from correct location.
938 (sim_open): Set size of FGR's according to
939 WITH_TARGET_FLOATING_POINT_BITSIZE.
940
941 * sim-main.h (FGR): Store floating point registers in a separate
942 array.
943
944Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
945
946 * configure: Regenerated to track ../common/aclocal.m4 changes.
947
948Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
949
950 * interp.c (ColdReset): Call PENDING_INVALIDATE.
951
952 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
953
954 * interp.c (pending_tick): New function. Deliver pending writes.
955
956 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
957 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
958 it can handle mixed sized quantites and single bits.
959
960Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
961
962 * interp.c (oengine.h): Do not include when building with IGEN.
963 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
964 (sim_info): Ditto for PROCESSOR_64BIT.
965 (sim_monitor): Replace ut_reg with unsigned_word.
966 (*): Ditto for t_reg.
967 (LOADDRMASK): Define.
968 (sim_open): Remove defunct check that host FP is IEEE compliant,
969 using software to emulate floating point.
970 (value_fpr, ...): Always compile, was conditional on HASFPU.
971
972Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
973
974 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
975 size.
976
977 * interp.c (SD, CPU): Define.
978 (mips_option_handler): Set flags in each CPU.
979 (interrupt_event): Assume CPU 0 is the one being iterrupted.
980 (sim_close): Do not clear STATE, deleted anyway.
981 (sim_write, sim_read): Assume CPU zero's vm should be used for
982 data transfers.
983 (sim_create_inferior): Set the PC for all processors.
984 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
985 argument.
986 (mips16_entry): Pass correct nr of args to store_word, load_word.
987 (ColdReset): Cold reset all cpu's.
988 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
989 (sim_monitor, load_memory, store_memory, signal_exception): Use
990 `CPU' instead of STATE_CPU.
991
992
993 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
994 SD or CPU_.
995
996 * sim-main.h (signal_exception): Add sim_cpu arg.
997 (SignalException*): Pass both SD and CPU to signal_exception.
998 * interp.c (signal_exception): Update.
999
1000 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1001 Ditto
1002 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1003 address_translation): Ditto
1004 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1005
1006Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1007
1008 * configure: Regenerated to track ../common/aclocal.m4 changes.
1009
1010Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1011
1012 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1013
1014 * mips.igen (model): Map processor names onto BFD name.
1015
1016 * sim-main.h (CPU_CIA): Delete.
1017 (SET_CIA, GET_CIA): Define
1018
1019Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1020
1021 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1022 regiser.
1023
1024 * configure.in (default_endian): Configure a big-endian simulator
1025 by default.
1026 * configure: Re-generate.
1027
1028Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1029
1030 * configure: Regenerated to track ../common/aclocal.m4 changes.
1031
1032Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1033
1034 * interp.c (sim_monitor): Handle Densan monitor outbyte
1035 and inbyte functions.
1036
10371997-12-29 Felix Lee <flee@cygnus.com>
1038
1039 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1040
1041Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1042
1043 * Makefile.in (tmp-igen): Arrange for $zero to always be
1044 reset to zero after every instruction.
1045
1046Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1047
1048 * configure: Regenerated to track ../common/aclocal.m4 changes.
1049 * config.in: Ditto.
1050
1051Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1052
1053 * mips.igen (MSUB): Fix to work like MADD.
1054 * gencode.c (MSUB): Similarly.
1055
1056Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1057
1058 * configure: Regenerated to track ../common/aclocal.m4 changes.
1059
1060Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1061
1062 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1063
1064Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1065
1066 * sim-main.h (sim-fpu.h): Include.
1067
1068 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1069 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1070 using host independant sim_fpu module.
1071
1072Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1073
1074 * interp.c (signal_exception): Report internal errors with SIGABRT
1075 not SIGQUIT.
1076
1077 * sim-main.h (C0_CONFIG): New register.
1078 (signal.h): No longer include.
1079
1080 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1081
1082Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1083
1084 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1085
1086Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 * mips.igen: Tag vr5000 instructions.
1089 (ANDI): Was missing mipsIV model, fix assembler syntax.
1090 (do_c_cond_fmt): New function.
1091 (C.cond.fmt): Handle mips I-III which do not support CC field
1092 separatly.
1093 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1094 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1095 in IV3.2 spec.
1096 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1097 vr5000 which saves LO in a GPR separatly.
1098
1099 * configure.in (enable-sim-igen): For vr5000, select vr5000
1100 specific instructions.
1101 * configure: Re-generate.
1102
1103Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1106
1107 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1108 fmt_uninterpreted_64 bit cases to switch. Convert to
1109 fmt_formatted,
1110
1111 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1112
1113 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1114 as specified in IV3.2 spec.
1115 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1116
1117Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1118
1119 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1120 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1121 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1122 PENDING_FILL versions of instructions. Simplify.
1123 (X): New function.
1124 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1125 instructions.
1126 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1127 a signed value.
1128 (MTHI, MFHI): Disable code checking HI-LO.
1129
1130 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1131 global.
1132 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1133
1134Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1135
1136 * gencode.c (build_mips16_operands): Replace IPC with cia.
1137
1138 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1139 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1140 IPC to `cia'.
1141 (UndefinedResult): Replace function with macro/function
1142 combination.
1143 (sim_engine_run): Don't save PC in IPC.
1144
1145 * sim-main.h (IPC): Delete.
1146
1147
1148 * interp.c (signal_exception, store_word, load_word,
1149 address_translation, load_memory, store_memory, cache_op,
1150 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1151 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1152 current instruction address - cia - argument.
1153 (sim_read, sim_write): Call address_translation directly.
1154 (sim_engine_run): Rename variable vaddr to cia.
1155 (signal_exception): Pass cia to sim_monitor
1156
1157 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1158 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1159 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1160
1161 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1162 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1163 SIM_ASSERT.
1164
1165 * interp.c (signal_exception): Pass restart address to
1166 sim_engine_restart.
1167
1168 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1169 idecode.o): Add dependency.
1170
1171 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1172 Delete definitions
1173 (DELAY_SLOT): Update NIA not PC with branch address.
1174 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1175
1176 * mips.igen: Use CIA not PC in branch calculations.
1177 (illegal): Call SignalException.
1178 (BEQ, ADDIU): Fix assembler.
1179
1180Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1181
1182 * m16.igen (JALX): Was missing.
1183
1184 * configure.in (enable-sim-igen): New configuration option.
1185 * configure: Re-generate.
1186
1187 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1188
1189 * interp.c (load_memory, store_memory): Delete parameter RAW.
1190 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1191 bypassing {load,store}_memory.
1192
1193 * sim-main.h (ByteSwapMem): Delete definition.
1194
1195 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1196
1197 * interp.c (sim_do_command, sim_commands): Delete mips specific
1198 commands. Handled by module sim-options.
1199
1200 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1201 (WITH_MODULO_MEMORY): Define.
1202
1203 * interp.c (sim_info): Delete code printing memory size.
1204
1205 * interp.c (mips_size): Nee sim_size, delete function.
1206 (power2): Delete.
1207 (monitor, monitor_base, monitor_size): Delete global variables.
1208 (sim_open, sim_close): Delete code creating monitor and other
1209 memory regions. Use sim-memopts module, via sim_do_commandf, to
1210 manage memory regions.
1211 (load_memory, store_memory): Use sim-core for memory model.
1212
1213 * interp.c (address_translation): Delete all memory map code
1214 except line forcing 32 bit addresses.
1215
1216Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1219 trace options.
1220
1221 * interp.c (logfh, logfile): Delete globals.
1222 (sim_open, sim_close): Delete code opening & closing log file.
1223 (mips_option_handler): Delete -l and -n options.
1224 (OPTION mips_options): Ditto.
1225
1226 * interp.c (OPTION mips_options): Rename option trace to dinero.
1227 (mips_option_handler): Update.
1228
1229Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1230
1231 * interp.c (fetch_str): New function.
1232 (sim_monitor): Rewrite using sim_read & sim_write.
1233 (sim_open): Check magic number.
1234 (sim_open): Write monitor vectors into memory using sim_write.
1235 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1236 (sim_read, sim_write): Simplify - transfer data one byte at a
1237 time.
1238 (load_memory, store_memory): Clarify meaning of parameter RAW.
1239
1240 * sim-main.h (isHOST): Defete definition.
1241 (isTARGET): Mark as depreciated.
1242 (address_translation): Delete parameter HOST.
1243
1244 * interp.c (address_translation): Delete parameter HOST.
1245
1246Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1247
1248 * mips.igen:
1249
1250 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1251 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1252
1253Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1254
1255 * mips.igen: Add model filter field to records.
1256
1257Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1260
1261 interp.c (sim_engine_run): Do not compile function sim_engine_run
1262 when WITH_IGEN == 1.
1263
1264 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1265 target architecture.
1266
1267 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1268 igen. Replace with configuration variables sim_igen_flags /
1269 sim_m16_flags.
1270
1271 * m16.igen: New file. Copy mips16 insns here.
1272 * mips.igen: From here.
1273
1274Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1275
1276 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1277 to top.
1278 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1279
1280Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1281
1282 * gencode.c (build_instruction): Follow sim_write's lead in using
1283 BigEndianMem instead of !ByteSwapMem.
1284
1285Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * configure.in (sim_gen): Dependent on target, select type of
1288 generator. Always select old style generator.
1289
1290 configure: Re-generate.
1291
1292 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1293 targets.
1294 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1295 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1296 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1297 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1298 SIM_@sim_gen@_*, set by autoconf.
1299
1300Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1301
1302 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1303
1304 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1305 CURRENT_FLOATING_POINT instead.
1306
1307 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1308 (address_translation): Raise exception InstructionFetch when
1309 translation fails and isINSTRUCTION.
1310
1311 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1312 sim_engine_run): Change type of of vaddr and paddr to
1313 address_word.
1314 (address_translation, prefetch, load_memory, store_memory,
1315 cache_op): Change type of vAddr and pAddr to address_word.
1316
1317 * gencode.c (build_instruction): Change type of vaddr and paddr to
1318 address_word.
1319
1320Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1321
1322 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1323 macro to obtain result of ALU op.
1324
1325Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1326
1327 * interp.c (sim_info): Call profile_print.
1328
1329Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1330
1331 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1332
1333 * sim-main.h (WITH_PROFILE): Do not define, defined in
1334 common/sim-config.h. Use sim-profile module.
1335 (simPROFILE): Delete defintion.
1336
1337 * interp.c (PROFILE): Delete definition.
1338 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1339 (sim_close): Delete code writing profile histogram.
1340 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1341 Delete.
1342 (sim_engine_run): Delete code profiling the PC.
1343
1344Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1345
1346 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1347
1348 * interp.c (sim_monitor): Make register pointers of type
1349 unsigned_word*.
1350
1351 * sim-main.h: Make registers of type unsigned_word not
1352 signed_word.
1353
1354Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1355
1356 * interp.c (sync_operation): Rename from SyncOperation, make
1357 global, add SD argument.
1358 (prefetch): Rename from Prefetch, make global, add SD argument.
1359 (decode_coproc): Make global.
1360
1361 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1362
1363 * gencode.c (build_instruction): Generate DecodeCoproc not
1364 decode_coproc calls.
1365
1366 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1367 (SizeFGR): Move to sim-main.h
1368 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1369 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1370 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1371 sim-main.h.
1372 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1373 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1374 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1375 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1376 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1377 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1378
1379 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1380 exception.
1381 (sim-alu.h): Include.
1382 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1383 (sim_cia): Typedef to instruction_address.
1384
1385Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1386
1387 * Makefile.in (interp.o): Rename generated file engine.c to
1388 oengine.c.
1389
1390 * interp.c: Update.
1391
1392Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1395
1396Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1397
1398 * gencode.c (build_instruction): For "FPSQRT", output correct
1399 number of arguments to Recip.
1400
1401Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * Makefile.in (interp.o): Depends on sim-main.h
1404
1405 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1406
1407 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1408 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1409 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1410 STATE, DSSTATE): Define
1411 (GPR, FGRIDX, ..): Define.
1412
1413 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1414 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1415 (GPR, FGRIDX, ...): Delete macros.
1416
1417 * interp.c: Update names to match defines from sim-main.h
1418
1419Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * interp.c (sim_monitor): Add SD argument.
1422 (sim_warning): Delete. Replace calls with calls to
1423 sim_io_eprintf.
1424 (sim_error): Delete. Replace calls with sim_io_error.
1425 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1426 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1427 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1428 argument.
1429 (mips_size): Rename from sim_size. Add SD argument.
1430
1431 * interp.c (simulator): Delete global variable.
1432 (callback): Delete global variable.
1433 (mips_option_handler, sim_open, sim_write, sim_read,
1434 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1435 sim_size,sim_monitor): Use sim_io_* not callback->*.
1436 (sim_open): ZALLOC simulator struct.
1437 (PROFILE): Do not define.
1438
1439Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1440
1441 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1442 support.h with corresponding code.
1443
1444 * sim-main.h (word64, uword64), support.h: Move definition to
1445 sim-main.h.
1446 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1447
1448 * support.h: Delete
1449 * Makefile.in: Update dependencies
1450 * interp.c: Do not include.
1451
1452Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1453
1454 * interp.c (address_translation, load_memory, store_memory,
1455 cache_op): Rename to from AddressTranslation et.al., make global,
1456 add SD argument
1457
1458 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1459 CacheOp): Define.
1460
1461 * interp.c (SignalException): Rename to signal_exception, make
1462 global.
1463
1464 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1465
1466 * sim-main.h (SignalException, SignalExceptionInterrupt,
1467 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1468 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1469 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1470 Define.
1471
1472 * interp.c, support.h: Use.
1473
1474Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1475
1476 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1477 to value_fpr / store_fpr. Add SD argument.
1478 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1479 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1480
1481 * sim-main.h (ValueFPR, StoreFPR): Define.
1482
1483Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1484
1485 * interp.c (sim_engine_run): Check consistency between configure
1486 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1487 and HASFPU.
1488
1489 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1490 (mips_fpu): Configure WITH_FLOATING_POINT.
1491 (mips_endian): Configure WITH_TARGET_ENDIAN.
1492 * configure: Update.
1493
1494Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * configure: Regenerated to track ../common/aclocal.m4 changes.
1497
1498Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1499
1500 * configure: Regenerated.
1501
1502Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1503
1504 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1505
1506Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * gencode.c (print_igen_insn_models): Assume certain architectures
1509 include all mips* instructions.
1510 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1511 instruction.
1512
1513 * Makefile.in (tmp.igen): Add target. Generate igen input from
1514 gencode file.
1515
1516 * gencode.c (FEATURE_IGEN): Define.
1517 (main): Add --igen option. Generate output in igen format.
1518 (process_instructions): Format output according to igen option.
1519 (print_igen_insn_format): New function.
1520 (print_igen_insn_models): New function.
1521 (process_instructions): Only issue warnings and ignore
1522 instructions when no FEATURE_IGEN.
1523
1524Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1527 MIPS targets.
1528
1529Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530
1531 * configure: Regenerated to track ../common/aclocal.m4 changes.
1532
1533Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1534
1535 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1536 SIM_RESERVED_BITS): Delete, moved to common.
1537 (SIM_EXTRA_CFLAGS): Update.
1538
1539Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * configure.in: Configure non-strict memory alignment.
1542 * configure: Regenerated to track ../common/aclocal.m4 changes.
1543
1544Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * configure: Regenerated to track ../common/aclocal.m4 changes.
1547
1548Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1549
1550 * gencode.c (SDBBP,DERET): Added (3900) insns.
1551 (RFE): Turn on for 3900.
1552 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1553 (dsstate): Made global.
1554 (SUBTARGET_R3900): Added.
1555 (CANCELDELAYSLOT): New.
1556 (SignalException): Ignore SystemCall rather than ignore and
1557 terminate. Add DebugBreakPoint handling.
1558 (decode_coproc): New insns RFE, DERET; and new registers Debug
1559 and DEPC protected by SUBTARGET_R3900.
1560 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1561 bits explicitly.
1562 * Makefile.in,configure.in: Add mips subtarget option.
1563 * configure: Update.
1564
1565Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1566
1567 * gencode.c: Add r3900 (tx39).
1568
1569
1570Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1571
1572 * gencode.c (build_instruction): Don't need to subtract 4 for
1573 JALR, just 2.
1574
1575Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1576
1577 * interp.c: Correct some HASFPU problems.
1578
1579Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1580
1581 * configure: Regenerated to track ../common/aclocal.m4 changes.
1582
1583Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1584
1585 * interp.c (mips_options): Fix samples option short form, should
1586 be `x'.
1587
1588Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1589
1590 * interp.c (sim_info): Enable info code. Was just returning.
1591
1592Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1593
1594 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1595 MFC0.
1596
1597Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1598
1599 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1600 constants.
1601 (build_instruction): Ditto for LL.
1602
1603Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1604
1605 * configure: Regenerated to track ../common/aclocal.m4 changes.
1606
1607Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608
1609 * configure: Regenerated to track ../common/aclocal.m4 changes.
1610 * config.in: Ditto.
1611
1612Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1613
1614 * interp.c (sim_open): Add call to sim_analyze_program, update
1615 call to sim_config.
1616
1617Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * interp.c (sim_kill): Delete.
1620 (sim_create_inferior): Add ABFD argument. Set PC from same.
1621 (sim_load): Move code initializing trap handlers from here.
1622 (sim_open): To here.
1623 (sim_load): Delete, use sim-hload.c.
1624
1625 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1626
1627Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628
1629 * configure: Regenerated to track ../common/aclocal.m4 changes.
1630 * config.in: Ditto.
1631
1632Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * interp.c (sim_open): Add ABFD argument.
1635 (sim_load): Move call to sim_config from here.
1636 (sim_open): To here. Check return status.
1637
1638Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1639
1640 * gencode.c (build_instruction): Two arg MADD should
1641 not assign result to $0.
1642
1643Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1644
1645 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1646 * sim/mips/configure.in: Regenerate.
1647
1648Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1649
1650 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1651 signed8, unsigned8 et.al. types.
1652
1653 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1654 hosts when selecting subreg.
1655
1656Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1657
1658 * interp.c (sim_engine_run): Reset the ZERO register to zero
1659 regardless of FEATURE_WARN_ZERO.
1660 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1661
1662Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663
1664 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1665 (SignalException): For BreakPoints ignore any mode bits and just
1666 save the PC.
1667 (SignalException): Always set the CAUSE register.
1668
1669Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670
1671 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1672 exception has been taken.
1673
1674 * interp.c: Implement the ERET and mt/f sr instructions.
1675
1676Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1677
1678 * interp.c (SignalException): Don't bother restarting an
1679 interrupt.
1680
1681Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1682
1683 * interp.c (SignalException): Really take an interrupt.
1684 (interrupt_event): Only deliver interrupts when enabled.
1685
1686Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1687
1688 * interp.c (sim_info): Only print info when verbose.
1689 (sim_info) Use sim_io_printf for output.
1690
1691Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1692
1693 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1694 mips architectures.
1695
1696Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1697
1698 * interp.c (sim_do_command): Check for common commands if a
1699 simulator specific command fails.
1700
1701Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1702
1703 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1704 and simBE when DEBUG is defined.
1705
1706Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1707
1708 * interp.c (interrupt_event): New function. Pass exception event
1709 onto exception handler.
1710
1711 * configure.in: Check for stdlib.h.
1712 * configure: Regenerate.
1713
1714 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1715 variable declaration.
1716 (build_instruction): Initialize memval1.
1717 (build_instruction): Add UNUSED attribute to byte, bigend,
1718 reverse.
1719 (build_operands): Ditto.
1720
1721 * interp.c: Fix GCC warnings.
1722 (sim_get_quit_code): Delete.
1723
1724 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1725 * Makefile.in: Ditto.
1726 * configure: Re-generate.
1727
1728 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1729
1730Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 * interp.c (mips_option_handler): New function parse argumes using
1733 sim-options.
1734 (myname): Replace with STATE_MY_NAME.
1735 (sim_open): Delete check for host endianness - performed by
1736 sim_config.
1737 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1738 (sim_open): Move much of the initialization from here.
1739 (sim_load): To here. After the image has been loaded and
1740 endianness set.
1741 (sim_open): Move ColdReset from here.
1742 (sim_create_inferior): To here.
1743 (sim_open): Make FP check less dependant on host endianness.
1744
1745 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1746 run.
1747 * interp.c (sim_set_callbacks): Delete.
1748
1749 * interp.c (membank, membank_base, membank_size): Replace with
1750 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1751 (sim_open): Remove call to callback->init. gdb/run do this.
1752
1753 * interp.c: Update
1754
1755 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1756
1757 * interp.c (big_endian_p): Delete, replaced by
1758 current_target_byte_order.
1759
1760Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * interp.c (host_read_long, host_read_word, host_swap_word,
1763 host_swap_long): Delete. Using common sim-endian.
1764 (sim_fetch_register, sim_store_register): Use H2T.
1765 (pipeline_ticks): Delete. Handled by sim-events.
1766 (sim_info): Update.
1767 (sim_engine_run): Update.
1768
1769Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1770
1771 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1772 reason from here.
1773 (SignalException): To here. Signal using sim_engine_halt.
1774 (sim_stop_reason): Delete, moved to common.
1775
1776Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1777
1778 * interp.c (sim_open): Add callback argument.
1779 (sim_set_callbacks): Delete SIM_DESC argument.
1780 (sim_size): Ditto.
1781
1782Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1783
1784 * Makefile.in (SIM_OBJS): Add common modules.
1785
1786 * interp.c (sim_set_callbacks): Also set SD callback.
1787 (set_endianness, xfer_*, swap_*): Delete.
1788 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1789 Change to functions using sim-endian macros.
1790 (control_c, sim_stop): Delete, use common version.
1791 (simulate): Convert into.
1792 (sim_engine_run): This function.
1793 (sim_resume): Delete.
1794
1795 * interp.c (simulation): New variable - the simulator object.
1796 (sim_kind): Delete global - merged into simulation.
1797 (sim_load): Cleanup. Move PC assignment from here.
1798 (sim_create_inferior): To here.
1799
1800 * sim-main.h: New file.
1801 * interp.c (sim-main.h): Include.
1802
1803Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1804
1805 * configure: Regenerated to track ../common/aclocal.m4 changes.
1806
1807Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1808
1809 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1810
1811Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1812
1813 * gencode.c (build_instruction): DIV instructions: check
1814 for division by zero and integer overflow before using
1815 host's division operation.
1816
1817Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1818
1819 * Makefile.in (SIM_OBJS): Add sim-load.o.
1820 * interp.c: #include bfd.h.
1821 (target_byte_order): Delete.
1822 (sim_kind, myname, big_endian_p): New static locals.
1823 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1824 after argument parsing. Recognize -E arg, set endianness accordingly.
1825 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1826 load file into simulator. Set PC from bfd.
1827 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1828 (set_endianness): Use big_endian_p instead of target_byte_order.
1829
1830Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1831
1832 * interp.c (sim_size): Delete prototype - conflicts with
1833 definition in remote-sim.h. Correct definition.
1834
1835Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1836
1837 * configure: Regenerated to track ../common/aclocal.m4 changes.
1838 * config.in: Ditto.
1839
1840Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1841
1842 * interp.c (sim_open): New arg `kind'.
1843
1844 * configure: Regenerated to track ../common/aclocal.m4 changes.
1845
1846Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1847
1848 * configure: Regenerated to track ../common/aclocal.m4 changes.
1849
1850Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1851
1852 * interp.c (sim_open): Set optind to 0 before calling getopt.
1853
1854Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1855
1856 * configure: Regenerated to track ../common/aclocal.m4 changes.
1857
1858Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1859
1860 * interp.c : Replace uses of pr_addr with pr_uword64
1861 where the bit length is always 64 independent of SIM_ADDR.
1862 (pr_uword64) : added.
1863
1864Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1865
1866 * configure: Re-generate.
1867
1868Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1869
1870 * configure: Regenerate to track ../common/aclocal.m4 changes.
1871
1872Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1873
1874 * interp.c (sim_open): New SIM_DESC result. Argument is now
1875 in argv form.
1876 (other sim_*): New SIM_DESC argument.
1877
1878Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1879
1880 * interp.c: Fix printing of addresses for non-64-bit targets.
1881 (pr_addr): Add function to print address based on size.
1882
1883Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1884
1885 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1886
1887Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1888
1889 * gencode.c (build_mips16_operands): Correct computation of base
1890 address for extended PC relative instruction.
1891
1892Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1893
1894 * interp.c (mips16_entry): Add support for floating point cases.
1895 (SignalException): Pass floating point cases to mips16_entry.
1896 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1897 registers.
1898 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1899 or fmt_word.
1900 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1901 and then set the state to fmt_uninterpreted.
1902 (COP_SW): Temporarily set the state to fmt_word while calling
1903 ValueFPR.
1904
1905Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1906
1907 * gencode.c (build_instruction): The high order may be set in the
1908 comparison flags at any ISA level, not just ISA 4.
1909
1910Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1911
1912 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1913 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1914 * configure.in: sinclude ../common/aclocal.m4.
1915 * configure: Regenerated.
1916
1917Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1918
1919 * configure: Rebuild after change to aclocal.m4.
1920
1921Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1922
1923 * configure configure.in Makefile.in: Update to new configure
1924 scheme which is more compatible with WinGDB builds.
1925 * configure.in: Improve comment on how to run autoconf.
1926 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1927 * Makefile.in: Use autoconf substitution to install common
1928 makefile fragment.
1929
1930Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1931
1932 * gencode.c (build_instruction): Use BigEndianCPU instead of
1933 ByteSwapMem.
1934
1935Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1936
1937 * interp.c (sim_monitor): Make output to stdout visible in
1938 wingdb's I/O log window.
1939
1940Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1941
1942 * support.h: Undo previous change to SIGTRAP
1943 and SIGQUIT values.
1944
1945Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1946
1947 * interp.c (store_word, load_word): New static functions.
1948 (mips16_entry): New static function.
1949 (SignalException): Look for mips16 entry and exit instructions.
1950 (simulate): Use the correct index when setting fpr_state after
1951 doing a pending move.
1952
1953Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1954
1955 * interp.c: Fix byte-swapping code throughout to work on
1956 both little- and big-endian hosts.
1957
1958Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1959
1960 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1961 with gdb/config/i386/xm-windows.h.
1962
1963Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1964
1965 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1966 that messes up arithmetic shifts.
1967
1968Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1969
1970 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1971 SIGTRAP and SIGQUIT for _WIN32.
1972
1973Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1974
1975 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1976 force a 64 bit multiplication.
1977 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1978 destination register is 0, since that is the default mips16 nop
1979 instruction.
1980
1981Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1982
1983 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1984 (build_endian_shift): Don't check proc64.
1985 (build_instruction): Always set memval to uword64. Cast op2 to
1986 uword64 when shifting it left in memory instructions. Always use
1987 the same code for stores--don't special case proc64.
1988
1989 * gencode.c (build_mips16_operands): Fix base PC value for PC
1990 relative operands.
1991 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1992 jal instruction.
1993 * interp.c (simJALDELAYSLOT): Define.
1994 (JALDELAYSLOT): Define.
1995 (INDELAYSLOT, INJALDELAYSLOT): Define.
1996 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1997
1998Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1999
2000 * interp.c (sim_open): add flush_cache as a PMON routine
2001 (sim_monitor): handle flush_cache by ignoring it
2002
2003Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2004
2005 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2006 BigEndianMem.
2007 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2008 (BigEndianMem): Rename to ByteSwapMem and change sense.
2009 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2010 BigEndianMem references to !ByteSwapMem.
2011 (set_endianness): New function, with prototype.
2012 (sim_open): Call set_endianness.
2013 (sim_info): Use simBE instead of BigEndianMem.
2014 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2015 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2016 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2017 ifdefs, keeping the prototype declaration.
2018 (swap_word): Rewrite correctly.
2019 (ColdReset): Delete references to CONFIG. Delete endianness related
2020 code; moved to set_endianness.
2021
2022Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2023
2024 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2025 * interp.c (CHECKHILO): Define away.
2026 (simSIGINT): New macro.
2027 (membank_size): Increase from 1MB to 2MB.
2028 (control_c): New function.
2029 (sim_resume): Rename parameter signal to signal_number. Add local
2030 variable prev. Call signal before and after simulate.
2031 (sim_stop_reason): Add simSIGINT support.
2032 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2033 functions always.
2034 (sim_warning): Delete call to SignalException. Do call printf_filtered
2035 if logfh is NULL.
2036 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2037 a call to sim_warning.
2038
2039Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2040
2041 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2042 16 bit instructions.
2043
2044Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2045
2046 Add support for mips16 (16 bit MIPS implementation):
2047 * gencode.c (inst_type): Add mips16 instruction encoding types.
2048 (GETDATASIZEINSN): Define.
2049 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2050 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2051 mtlo.
2052 (MIPS16_DECODE): New table, for mips16 instructions.
2053 (bitmap_val): New static function.
2054 (struct mips16_op): Define.
2055 (mips16_op_table): New table, for mips16 operands.
2056 (build_mips16_operands): New static function.
2057 (process_instructions): If PC is odd, decode a mips16
2058 instruction. Break out instruction handling into new
2059 build_instruction function.
2060 (build_instruction): New static function, broken out of
2061 process_instructions. Check modifiers rather than flags for SHIFT
2062 bit count and m[ft]{hi,lo} direction.
2063 (usage): Pass program name to fprintf.
2064 (main): Remove unused variable this_option_optind. Change
2065 ``*loptarg++'' to ``loptarg++''.
2066 (my_strtoul): Parenthesize && within ||.
2067 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2068 (simulate): If PC is odd, fetch a 16 bit instruction, and
2069 increment PC by 2 rather than 4.
2070 * configure.in: Add case for mips16*-*-*.
2071 * configure: Rebuild.
2072
2073Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2074
2075 * interp.c: Allow -t to enable tracing in standalone simulator.
2076 Fix garbage output in trace file and error messages.
2077
2078Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2079
2080 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2081 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2082 * configure.in: Simplify using macros in ../common/aclocal.m4.
2083 * configure: Regenerated.
2084 * tconfig.in: New file.
2085
2086Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2087
2088 * interp.c: Fix bugs in 64-bit port.
2089 Use ansi function declarations for msvc compiler.
2090 Initialize and test file pointer in trace code.
2091 Prevent duplicate definition of LAST_EMED_REGNUM.
2092
2093Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2094
2095 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2096
2097Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2098
2099 * interp.c (SignalException): Check for explicit terminating
2100 breakpoint value.
2101 * gencode.c: Pass instruction value through SignalException()
2102 calls for Trap, Breakpoint and Syscall.
2103
2104Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2105
2106 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2107 only used on those hosts that provide it.
2108 * configure.in: Add sqrt() to list of functions to be checked for.
2109 * config.in: Re-generated.
2110 * configure: Re-generated.
2111
2112Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2113
2114 * gencode.c (process_instructions): Call build_endian_shift when
2115 expanding STORE RIGHT, to fix swr.
2116 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2117 clear the high bits.
2118 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2119 Fix float to int conversions to produce signed values.
2120
2121Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2122
2123 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2124 (process_instructions): Correct handling of nor instruction.
2125 Correct shift count for 32 bit shift instructions. Correct sign
2126 extension for arithmetic shifts to not shift the number of bits in
2127 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2128 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2129 Fix madd.
2130 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2131 It's OK to have a mult follow a mult. What's not OK is to have a
2132 mult follow an mfhi.
2133 (Convert): Comment out incorrect rounding code.
2134
2135Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2136
2137 * interp.c (sim_monitor): Improved monitor printf
2138 simulation. Tidied up simulator warnings, and added "--log" option
2139 for directing warning message output.
2140 * gencode.c: Use sim_warning() rather than WARNING macro.
2141
2142Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2143
2144 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2145 getopt1.o, rather than on gencode.c. Link objects together.
2146 Don't link against -liberty.
2147 (gencode.o, getopt.o, getopt1.o): New targets.
2148 * gencode.c: Include <ctype.h> and "ansidecl.h".
2149 (AND): Undefine after including "ansidecl.h".
2150 (ULONG_MAX): Define if not defined.
2151 (OP_*): Don't define macros; now defined in opcode/mips.h.
2152 (main): Call my_strtoul rather than strtoul.
2153 (my_strtoul): New static function.
2154
2155Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2156
2157 * gencode.c (process_instructions): Generate word64 and uword64
2158 instead of `long long' and `unsigned long long' data types.
2159 * interp.c: #include sysdep.h to get signals, and define default
2160 for SIGBUS.
2161 * (Convert): Work around for Visual-C++ compiler bug with type
2162 conversion.
2163 * support.h: Make things compile under Visual-C++ by using
2164 __int64 instead of `long long'. Change many refs to long long
2165 into word64/uword64 typedefs.
2166
2167Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2168
2169 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2170 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2171 (docdir): Removed.
2172 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2173 (AC_PROG_INSTALL): Added.
2174 (AC_PROG_CC): Moved to before configure.host call.
2175 * configure: Rebuilt.
2176
2177Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2178
2179 * configure.in: Define @SIMCONF@ depending on mips target.
2180 * configure: Rebuild.
2181 * Makefile.in (run): Add @SIMCONF@ to control simulator
2182 construction.
2183 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2184 * interp.c: Remove some debugging, provide more detailed error
2185 messages, update memory accesses to use LOADDRMASK.
2186
2187Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2188
2189 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2190 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2191 stamp-h.
2192 * configure: Rebuild.
2193 * config.in: New file, generated by autoheader.
2194 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2195 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2196 HAVE_ANINT and HAVE_AINT, as appropriate.
2197 * Makefile.in (run): Use @LIBS@ rather than -lm.
2198 (interp.o): Depend upon config.h.
2199 (Makefile): Just rebuild Makefile.
2200 (clean): Remove stamp-h.
2201 (mostlyclean): Make the same as clean, not as distclean.
2202 (config.h, stamp-h): New targets.
2203
2204Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2205
2206 * interp.c (ColdReset): Fix boolean test. Make all simulator
2207 globals static.
2208
2209Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2210
2211 * interp.c (xfer_direct_word, xfer_direct_long,
2212 swap_direct_word, swap_direct_long, xfer_big_word,
2213 xfer_big_long, xfer_little_word, xfer_little_long,
2214 swap_word,swap_long): Added.
2215 * interp.c (ColdReset): Provide function indirection to
2216 host<->simulated_target transfer routines.
2217 * interp.c (sim_store_register, sim_fetch_register): Updated to
2218 make use of indirected transfer routines.
2219
2220Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2221
2222 * gencode.c (process_instructions): Ensure FP ABS instruction
2223 recognised.
2224 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2225 system call support.
2226
2227Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2228
2229 * interp.c (sim_do_command): Complain if callback structure not
2230 initialised.
2231
2232Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2233
2234 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2235 support for Sun hosts.
2236 * Makefile.in (gencode): Ensure the host compiler and libraries
2237 used for cross-hosted build.
2238
2239Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2240
2241 * interp.c, gencode.c: Some more (TODO) tidying.
2242
2243Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2244
2245 * gencode.c, interp.c: Replaced explicit long long references with
2246 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2247 * support.h (SET64LO, SET64HI): Macros added.
2248
2249Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2250
2251 * configure: Regenerate with autoconf 2.7.
2252
2253Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2254
2255 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2256 * support.h: Remove superfluous "1" from #if.
2257 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2258
2259Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2260
2261 * interp.c (StoreFPR): Control UndefinedResult() call on
2262 WARN_RESULT manifest.
2263
2264Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2265
2266 * gencode.c: Tidied instruction decoding, and added FP instruction
2267 support.
2268
2269 * interp.c: Added dineroIII, and BSD profiling support. Also
2270 run-time FP handling.
2271
2272Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2273
2274 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2275 gencode.c, interp.c, support.h: created.
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