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target/sparc: Split out ldst functions with asi pre-computed
[thirdparty/qemu.git] / target / sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
5650b549 10 version 2.1 of the License, or (at your option) any later version.
7a3f1944
FB		 11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
dcb32f1d 27#include "tcg/tcg-op.h"
7a3f1944 28
2ef6175a 29#include "exec/helper-gen.h"
a7812ae4 30
c5e6ccdf 31#include "exec/translator.h"
508127e2 32#include "exec/log.h"
0cc1f4bf 33#include "asi.h"
a7e30d84 34
d53106c9
RH		 35#define HELPER_H "helper.h"
36#include "exec/helper-info.c.inc"
37#undef HELPER_H
a7e30d84 38
668bb9b7
RH		 39#ifdef TARGET_SPARC64
40# define gen_helper_rdpsr(D, E) qemu_build_not_reached()
86b82fe0 41# define gen_helper_rett(E) qemu_build_not_reached()
0faef01b 42# define gen_helper_power_down(E) qemu_build_not_reached()
25524734 43# define gen_helper_wrpsr(E, S) qemu_build_not_reached()
668bb9b7 44#else
0faef01b 45# define gen_helper_clear_softint(E, S) qemu_build_not_reached()
8f75b8a4 46# define gen_helper_done(E) qemu_build_not_reached()
e8325dc0 47# define gen_helper_flushw(E) qemu_build_not_reached()
af25071c 48# define gen_helper_rdccr(D, E) qemu_build_not_reached()
5d617bfb 49# define gen_helper_rdcwp(D, E) qemu_build_not_reached()
25524734 50# define gen_helper_restored(E) qemu_build_not_reached()
8f75b8a4 51# define gen_helper_retry(E) qemu_build_not_reached()
25524734 52# define gen_helper_saved(E) qemu_build_not_reached()
4ee85ea9 53# define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached()
0faef01b 54# define gen_helper_set_softint(E, S) qemu_build_not_reached()
af25071c 55# define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached()
9422278e 56# define gen_helper_tick_set_count(P, S) qemu_build_not_reached()
bb97f2f5 57# define gen_helper_tick_set_limit(P, S) qemu_build_not_reached()
4ee85ea9 58# define gen_helper_udivx(D, E, A, B) qemu_build_not_reached()
0faef01b 59# define gen_helper_wrccr(E, S) qemu_build_not_reached()
9422278e
RH		 60# define gen_helper_wrcwp(E, S) qemu_build_not_reached()
61# define gen_helper_wrgl(E, S) qemu_build_not_reached()
0faef01b 62# define gen_helper_write_softint(E, S) qemu_build_not_reached()
9422278e
RH		 63# define gen_helper_wrpil(E, S) qemu_build_not_reached()
64# define gen_helper_wrpstate(E, S) qemu_build_not_reached()
668bb9b7 65# define MAXTL_MASK 0
af25071c
RH		 66#endif
67
633c4283
RH		 68/* Dynamic PC, must exit to main loop. */
69#define DYNAMIC_PC 1
70/* Dynamic PC, one of two values according to jump_pc[T2]. */
71#define JUMP_PC 2
72/* Dynamic PC, may lookup next TB. */
73#define DYNAMIC_PC_LOOKUP 3
72cbca10 74
46bb0137
MCA		 75#define DISAS_EXIT DISAS_TARGET_0
76
1a2fb1c0 77/* global register indexes */
1bcea73e 78static TCGv_ptr cpu_regwptr;
25517f99
PB		 79static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
80static TCGv_i32 cpu_cc_op;
a7812ae4 81static TCGv_i32 cpu_psr;
d2dc4069
RH		 82static TCGv cpu_fsr, cpu_pc, cpu_npc;
83static TCGv cpu_regs[32];
255e1fcb 84static TCGv cpu_y;
255e1fcb 85static TCGv cpu_tbr;
5793f2a4 86static TCGv cpu_cond;
dc99a3f2 87#ifdef TARGET_SPARC64
a6d567e5 88static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 89static TCGv cpu_gsr;
255e1fcb 90#else
af25071c
RH		 91# define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; })
92# define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; })
dc99a3f2 93#endif
714547bb 94/* Floating point registers */
30038fd8 95static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 96
af25071c
RH		 97#define env_field_offsetof(X) offsetof(CPUSPARCState, X)
98#ifdef TARGET_SPARC64
cd6269f7 99# define env32_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
af25071c
RH		 100# define env64_field_offsetof(X) env_field_offsetof(X)
101#else
cd6269f7 102# define env32_field_offsetof(X) env_field_offsetof(X)
af25071c
RH		 103# define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
104#endif
105
186e7890
RH		 106typedef struct DisasDelayException {
107 struct DisasDelayException *next;
108 TCGLabel *lab;
109 TCGv_i32 excp;
110 /* Saved state at parent insn. */
111 target_ulong pc;
112 target_ulong npc;
113} DisasDelayException;
114
7a3f1944 115typedef struct DisasContext {
af00be49 116 DisasContextBase base;
0f8a249a
BS		 117 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
118 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 119 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
e8af50a3 120 int mem_idx;
c9b459aa
AT		 121 bool fpu_enabled;
122 bool address_mask_32bit;
c9b459aa
AT		 123#ifndef CONFIG_USER_ONLY
124 bool supervisor;
125#ifdef TARGET_SPARC64
126 bool hypervisor;
127#endif
128#endif
129
8393617c 130 uint32_t cc_op; /* current CC operation */
5578ceab 131 sparc_def_t *def;
a6d567e5 132#ifdef TARGET_SPARC64
f9c816c0 133 int fprs_dirty;
a6d567e5
RH		 134 int asi;
135#endif
186e7890 136 DisasDelayException *delay_excp_list;
7a3f1944
FB		 137} DisasContext;
138
416fcaea
RH		 139typedef struct {
140 TCGCond cond;
141 bool is_bool;
416fcaea
RH		 142 TCGv c1, c2;
143} DisasCompare;
144
3475187d 145// This function uses non-native bit order
dc1a6971
BS		 146#define GET_FIELD(X, FROM, TO) \
147 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 148
3475187d 149// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 150#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 151 GET_FIELD(X, 31 - (TO), 31 - (FROM))
152
153#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 154#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 155
156#ifdef TARGET_SPARC64
0387d928 157#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 158#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 159#else
c185970a 160#define DFPREG(r) (r & 0x1e)
1f587329 161#define QFPREG(r) (r & 0x1c)
3475187d
FB		 162#endif
163
b158a785
BS		 164#define UA2005_HTRAP_MASK 0xff
165#define V8_TRAP_MASK 0x7f
166
3475187d
FB		 167static int sign_extend(int x, int len)
168{
169 len = 32 - len;
170 return (x << len) >> len;
171}
172
7a3f1944
FB		 173#define IS_IMM (insn & (1<<13))
174
0c2e96c1 175static void gen_update_fprs_dirty(DisasContext *dc, int rd)
141ae5c1
RH		 176{
177#if defined(TARGET_SPARC64)
f9c816c0
RH		 178 int bit = (rd < 32) ? 1 : 2;
179 /* If we know we've already set this bit within the TB,
180 we can avoid setting it again. */
181 if (!(dc->fprs_dirty & bit)) {
182 dc->fprs_dirty |= bit;
183 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
184 }
141ae5c1
RH		 185#endif
186}
187
ff07ec83 188/* floating point registers moves */
208ae657
RH		 189static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
190{
36ab4623 191 TCGv_i32 ret = tcg_temp_new_i32();
30038fd8 192 if (src & 1) {
dc41aa7d 193 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 194 } else {
dc41aa7d 195 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 196 }
dc41aa7d 197 return ret;
208ae657
RH		 198}
199
200static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
201{
8e7bbc75
RH		 202 TCGv_i64 t = tcg_temp_new_i64();
203
204 tcg_gen_extu_i32_i64(t, v);
30038fd8
RH		 205 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
206 (dst & 1 ? 0 : 32), 32);
f9c816c0 207 gen_update_fprs_dirty(dc, dst);
208ae657
RH		 208}
209
ba5f5179 210static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 211{
36ab4623 212 return tcg_temp_new_i32();
208ae657
RH		 213}
214
96eda024
RH		 215static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
216{
96eda024 217 src = DFPREG(src);
30038fd8 218 return cpu_fpr[src / 2];
96eda024
RH		 219}
220
221static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
222{
223 dst = DFPREG(dst);
30038fd8 224 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
f9c816c0 225 gen_update_fprs_dirty(dc, dst);
96eda024
RH		 226}
227
3886b8a3 228static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 229{
3886b8a3 230 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 231}
232
ff07ec83
BS		 233static void gen_op_load_fpr_QT0(unsigned int src)
234{
ad75a51e 235 tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 236 offsetof(CPU_QuadU, ll.upper));
ad75a51e 237 tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 238 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 239}
240
241static void gen_op_load_fpr_QT1(unsigned int src)
242{
ad75a51e 243 tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt1) +
30038fd8 244 offsetof(CPU_QuadU, ll.upper));
ad75a51e 245 tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt1) +
30038fd8 246 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 247}
248
249static void gen_op_store_QT0_fpr(unsigned int dst)
250{
ad75a51e 251 tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 252 offsetof(CPU_QuadU, ll.upper));
ad75a51e 253 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
30038fd8 254 offsetof(CPU_QuadU, ll.lower));
ff07ec83 255}
1f587329 256
f939ffe5
RH		 257static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
258 TCGv_i64 v1, TCGv_i64 v2)
259{
260 dst = QFPREG(dst);
261
262 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
263 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
264 gen_update_fprs_dirty(dc, dst);
265}
266
ac11f776 267#ifdef TARGET_SPARC64
f939ffe5
RH		 268static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
269{
270 src = QFPREG(src);
271 return cpu_fpr[src / 2];
272}
273
274static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
275{
276 src = QFPREG(src);
277 return cpu_fpr[src / 2 + 1];
278}
279
f9c816c0 280static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
ac11f776
RH		 281{
282 rd = QFPREG(rd);
283 rs = QFPREG(rs);
284
30038fd8
RH		 285 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
286 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
f9c816c0 287 gen_update_fprs_dirty(dc, rd);
ac11f776
RH		 288}
289#endif
290
81ad8ba2
BS		 291/* moves */
292#ifdef CONFIG_USER_ONLY
3475187d 293#define supervisor(dc) 0
e9ebed4d 294#define hypervisor(dc) 0
3475187d 295#else
81ad8ba2 296#ifdef TARGET_SPARC64
c9b459aa
AT		 297#define hypervisor(dc) (dc->hypervisor)
298#define supervisor(dc) (dc->supervisor | dc->hypervisor)
6f27aba6 299#else
c9b459aa 300#define supervisor(dc) (dc->supervisor)
668bb9b7 301#define hypervisor(dc) 0
3475187d 302#endif
81ad8ba2
BS		 303#endif
304
b1bc09ea
RH		 305#if !defined(TARGET_SPARC64)
306# define AM_CHECK(dc) false
307#elif defined(TARGET_ABI32)
308# define AM_CHECK(dc) true
309#elif defined(CONFIG_USER_ONLY)
310# define AM_CHECK(dc) false
1a2fb1c0 311#else
b1bc09ea 312# define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 313#endif
3391c818 314
0c2e96c1 315static void gen_address_mask(DisasContext *dc, TCGv addr)
2cade6a3 316{
b1bc09ea 317 if (AM_CHECK(dc)) {
2cade6a3 318 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
b1bc09ea 319 }
2cade6a3
BS		 320}
321
23ada1b1
RH		 322static target_ulong address_mask_i(DisasContext *dc, target_ulong addr)
323{
324 return AM_CHECK(dc) ? (uint32_t)addr : addr;
325}
326
0c2e96c1 327static TCGv gen_load_gpr(DisasContext *dc, int reg)
88023616 328{
d2dc4069
RH		 329 if (reg > 0) {
330 assert(reg < 32);
331 return cpu_regs[reg];
332 } else {
52123f14 333 TCGv t = tcg_temp_new();
d2dc4069 334 tcg_gen_movi_tl(t, 0);
88023616 335 return t;
88023616
RH		 336 }
337}
338
0c2e96c1 339static void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
88023616
RH		 340{
341 if (reg > 0) {
d2dc4069
RH		 342 assert(reg < 32);
343 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 344 }
345}
346
0c2e96c1 347static TCGv gen_dest_gpr(DisasContext *dc, int reg)
88023616 348{
d2dc4069
RH		 349 if (reg > 0) {
350 assert(reg < 32);
351 return cpu_regs[reg];
88023616 352 } else {
52123f14 353 return tcg_temp_new();
88023616
RH		 354 }
355}
356
5645aa2e 357static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc)
90aa39a1 358{
5645aa2e
RH		 359 return translator_use_goto_tb(&s->base, pc) &&
360 translator_use_goto_tb(&s->base, npc);
90aa39a1
SF		 361}
362
5645aa2e
RH		 363static void gen_goto_tb(DisasContext *s, int tb_num,
364 target_ulong pc, target_ulong npc)
6e256c93 365{
90aa39a1 366 if (use_goto_tb(s, pc, npc)) {
6e256c93 367 /* jump to same page: we can use a direct jump */
57fec1fe 368 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 369 tcg_gen_movi_tl(cpu_pc, pc);
370 tcg_gen_movi_tl(cpu_npc, npc);
07ea28b4 371 tcg_gen_exit_tb(s->base.tb, tb_num);
6e256c93 372 } else {
f67ccb2f 373 /* jump to another page: we can use an indirect jump */
2f5680ee
BS		 374 tcg_gen_movi_tl(cpu_pc, pc);
375 tcg_gen_movi_tl(cpu_npc, npc);
f67ccb2f 376 tcg_gen_lookup_and_goto_ptr();
6e256c93
FB		 377 }
378}
379
19f329ad 380// XXX suboptimal
0c2e96c1 381static void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 382{
8911f501 383 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 384 tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
19f329ad
BS		 385}
386
0c2e96c1 387static void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 388{
8911f501 389 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 390 tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
19f329ad
BS		 391}
392
0c2e96c1 393static void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 394{
8911f501 395 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 396 tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
19f329ad
BS		 397}
398
0c2e96c1 399static void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 400{
8911f501 401 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 402 tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
19f329ad
BS		 403}
404
0c2e96c1 405static void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 406{
4af984a7 407 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 408 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 409 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 410 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 411}
412
70c48285 413static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 414{
70c48285
RH		 415 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
416
417 /* Carry is computed from a previous add: (dst < src) */
418#if TARGET_LONG_BITS == 64
419 cc_src1_32 = tcg_temp_new_i32();
420 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 421 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
422 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 423#else
424 cc_src1_32 = cpu_cc_dst;
425 cc_src2_32 = cpu_cc_src;
426#endif
427
428 carry_32 = tcg_temp_new_i32();
429 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
430
70c48285 431 return carry_32;
41d72852
BS		 432}
433
70c48285 434static TCGv_i32 gen_sub32_carry32(void)
41d72852 435{
70c48285
RH		 436 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
437
438 /* Carry is computed from a previous borrow: (src1 < src2) */
439#if TARGET_LONG_BITS == 64
440 cc_src1_32 = tcg_temp_new_i32();
441 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 442 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
443 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 444#else
445 cc_src1_32 = cpu_cc_src;
446 cc_src2_32 = cpu_cc_src2;
447#endif
448
449 carry_32 = tcg_temp_new_i32();
450 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
451
70c48285
RH		 452 return carry_32;
453}
454
420a187d
RH		 455static void gen_op_addc_int(TCGv dst, TCGv src1, TCGv src2,
456 TCGv_i32 carry_32, bool update_cc)
70c48285 457{
420a187d 458 tcg_gen_add_tl(dst, src1, src2);
70c48285 459
420a187d
RH		 460#ifdef TARGET_SPARC64
461 TCGv carry = tcg_temp_new();
462 tcg_gen_extu_i32_tl(carry, carry_32);
463 tcg_gen_add_tl(dst, dst, carry);
464#else
465 tcg_gen_add_i32(dst, dst, carry_32);
466#endif
70c48285 467
420a187d
RH		 468 if (update_cc) {
469 tcg_debug_assert(dst == cpu_cc_dst);
470 tcg_gen_mov_tl(cpu_cc_src, src1);
471 tcg_gen_mov_tl(cpu_cc_src2, src2);
472 }
473}
70c48285 474
420a187d
RH		 475static void gen_op_addc_int_add(TCGv dst, TCGv src1, TCGv src2, bool update_cc)
476{
477 TCGv discard;
70c48285 478
420a187d
RH		 479 if (TARGET_LONG_BITS == 64) {
480 gen_op_addc_int(dst, src1, src2, gen_add32_carry32(), update_cc);
481 return;
70c48285
RH		 482 }
483
420a187d
RH		 484 /*
485 * We can re-use the host's hardware carry generation by using
486 * an ADD2 opcode. We discard the low part of the output.
487 * Ideally we'd combine this operation with the add that
488 * generated the carry in the first place.
489 */
490 discard = tcg_temp_new();
491 tcg_gen_add2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
70c48285 492
70c48285 493 if (update_cc) {
420a187d 494 tcg_debug_assert(dst == cpu_cc_dst);
70c48285
RH		 495 tcg_gen_mov_tl(cpu_cc_src, src1);
496 tcg_gen_mov_tl(cpu_cc_src2, src2);
70c48285 497 }
dc99a3f2
BS		 498}
499
420a187d
RH		 500static void gen_op_addc_add(TCGv dst, TCGv src1, TCGv src2)
501{
502 gen_op_addc_int_add(dst, src1, src2, false);
503}
504
505static void gen_op_addccc_add(TCGv dst, TCGv src1, TCGv src2)
506{
507 gen_op_addc_int_add(dst, src1, src2, true);
508}
509
510static void gen_op_addc_sub(TCGv dst, TCGv src1, TCGv src2)
511{
512 gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), false);
513}
514
515static void gen_op_addccc_sub(TCGv dst, TCGv src1, TCGv src2)
516{
517 gen_op_addc_int(dst, src1, src2, gen_sub32_carry32(), true);
518}
519
520static void gen_op_addc_int_generic(TCGv dst, TCGv src1, TCGv src2,
521 bool update_cc)
522{
523 TCGv_i32 carry_32 = tcg_temp_new_i32();
524 gen_helper_compute_C_icc(carry_32, tcg_env);
525 gen_op_addc_int(dst, src1, src2, carry_32, update_cc);
526}
527
528static void gen_op_addc_generic(TCGv dst, TCGv src1, TCGv src2)
529{
530 gen_op_addc_int_generic(dst, src1, src2, false);
531}
532
533static void gen_op_addccc_generic(TCGv dst, TCGv src1, TCGv src2)
534{
535 gen_op_addc_int_generic(dst, src1, src2, true);
536}
537
0c2e96c1 538static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 539{
4af984a7 540 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 541 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 542 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 543 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 544}
545
dfebb950
RH		 546static void gen_op_subc_int(TCGv dst, TCGv src1, TCGv src2,
547 TCGv_i32 carry_32, bool update_cc)
41d72852 548{
70c48285 549 TCGv carry;
41d72852 550
70c48285
RH		 551#if TARGET_LONG_BITS == 64
552 carry = tcg_temp_new();
553 tcg_gen_extu_i32_i64(carry, carry_32);
554#else
555 carry = carry_32;
556#endif
557
558 tcg_gen_sub_tl(dst, src1, src2);
559 tcg_gen_sub_tl(dst, dst, carry);
560
70c48285 561 if (update_cc) {
dfebb950 562 tcg_debug_assert(dst == cpu_cc_dst);
70c48285
RH		 563 tcg_gen_mov_tl(cpu_cc_src, src1);
564 tcg_gen_mov_tl(cpu_cc_src2, src2);
70c48285 565 }
dc99a3f2
BS		 566}
567
dfebb950
RH		 568static void gen_op_subc_add(TCGv dst, TCGv src1, TCGv src2)
569{
570 gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), false);
571}
572
573static void gen_op_subccc_add(TCGv dst, TCGv src1, TCGv src2)
574{
575 gen_op_subc_int(dst, src1, src2, gen_add32_carry32(), true);
576}
577
578static void gen_op_subc_int_sub(TCGv dst, TCGv src1, TCGv src2, bool update_cc)
579{
580 TCGv discard;
581
582 if (TARGET_LONG_BITS == 64) {
583 gen_op_subc_int(dst, src1, src2, gen_sub32_carry32(), update_cc);
584 return;
585 }
586
587 /*
588 * We can re-use the host's hardware carry generation by using
589 * a SUB2 opcode. We discard the low part of the output.
590 */
591 discard = tcg_temp_new();
592 tcg_gen_sub2_tl(discard, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
593
594 if (update_cc) {
595 tcg_debug_assert(dst == cpu_cc_dst);
596 tcg_gen_mov_tl(cpu_cc_src, src1);
597 tcg_gen_mov_tl(cpu_cc_src2, src2);
598 }
599}
600
601static void gen_op_subc_sub(TCGv dst, TCGv src1, TCGv src2)
602{
603 gen_op_subc_int_sub(dst, src1, src2, false);
604}
605
606static void gen_op_subccc_sub(TCGv dst, TCGv src1, TCGv src2)
607{
608 gen_op_subc_int_sub(dst, src1, src2, true);
609}
610
611static void gen_op_subc_int_generic(TCGv dst, TCGv src1, TCGv src2,
612 bool update_cc)
613{
614 TCGv_i32 carry_32 = tcg_temp_new_i32();
615
616 gen_helper_compute_C_icc(carry_32, tcg_env);
617 gen_op_subc_int(dst, src1, src2, carry_32, update_cc);
618}
619
620static void gen_op_subc_generic(TCGv dst, TCGv src1, TCGv src2)
621{
622 gen_op_subc_int_generic(dst, src1, src2, false);
623}
624
625static void gen_op_subccc_generic(TCGv dst, TCGv src1, TCGv src2)
626{
627 gen_op_subc_int_generic(dst, src1, src2, true);
628}
629
0c2e96c1 630static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 631{
de9e9d9f 632 TCGv r_temp, zero, t0;
d9bdab86 633
a7812ae4 634 r_temp = tcg_temp_new();
de9e9d9f 635 t0 = tcg_temp_new();
d9bdab86
BS		 636
637 /* old op:
638 if (!(env->y & 1))
639 T1 = 0;
640 */
00ab7e61 641 zero = tcg_constant_tl(0);
72ccba79 642 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 643 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 644 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 645 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
646 zero, cpu_cc_src2);
d9bdab86
BS		 647
648 // b2 = T0 & 1;
649 // env->y = (b2 << 31) | (env->y >> 1);
0b1183e3 650 tcg_gen_extract_tl(t0, cpu_y, 1, 31);
08d64e0d 651 tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
d9bdab86
BS		 652
653 // b1 = N ^ V;
de9e9d9f 654 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 655 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 656 tcg_gen_xor_tl(t0, t0, r_temp);
d9bdab86
BS		 657
658 // T0 = (b1 << 31) | (T0 >> 1);
659 // src1 = T0;
de9e9d9f 660 tcg_gen_shli_tl(t0, t0, 31);
6f551262 661 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f 662 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
d9bdab86 663
5c6a0628 664 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 665
5c6a0628 666 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 667}
668
0c2e96c1 669static void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 670{
528692a8 671#if TARGET_LONG_BITS == 32
fb170183 672 if (sign_ext) {
528692a8 673 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 674 } else {
528692a8 675 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 676 }
528692a8
RH		 677#else
678 TCGv t0 = tcg_temp_new_i64();
679 TCGv t1 = tcg_temp_new_i64();
fb170183 680
528692a8
RH		 681 if (sign_ext) {
682 tcg_gen_ext32s_i64(t0, src1);
683 tcg_gen_ext32s_i64(t1, src2);
684 } else {
685 tcg_gen_ext32u_i64(t0, src1);
686 tcg_gen_ext32u_i64(t1, src2);
687 }
fb170183 688
528692a8 689 tcg_gen_mul_i64(dst, t0, t1);
528692a8
RH		 690 tcg_gen_shri_i64(cpu_y, dst, 32);
691#endif
8879d139
BS		 692}
693
0c2e96c1 694static void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 695{
fb170183
IK		 696 /* zero-extend truncated operands before multiplication */
697 gen_op_multiply(dst, src1, src2, 0);
698}
8879d139 699
0c2e96c1 700static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
fb170183
IK		 701{
702 /* sign-extend truncated operands before multiplication */
703 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 704}
705
4ee85ea9
RH		 706static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2)
707{
708 gen_helper_udivx(dst, tcg_env, src1, src2);
709}
710
711static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
712{
713 gen_helper_sdivx(dst, tcg_env, src1, src2);
714}
715
c2636853
RH		 716static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
717{
718 gen_helper_udiv(dst, tcg_env, src1, src2);
719}
720
721static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
722{
723 gen_helper_sdiv(dst, tcg_env, src1, src2);
724}
725
726static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2)
727{
728 gen_helper_udiv_cc(dst, tcg_env, src1, src2);
729}
730
731static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
732{
733 gen_helper_sdiv_cc(dst, tcg_env, src1, src2);
734}
735
a9aba13d
RH		 736static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2)
737{
738 gen_helper_taddcctv(dst, tcg_env, src1, src2);
739}
740
741static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2)
742{
743 gen_helper_tsubcctv(dst, tcg_env, src1, src2);
744}
745
9c6ec5bc
RH		 746static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2)
747{
748 tcg_gen_ctpop_tl(dst, src2);
749}
750
19f329ad 751// 1
0c2e96c1 752static void gen_op_eval_ba(TCGv dst)
19f329ad
BS		 753{
754 tcg_gen_movi_tl(dst, 1);
755}
756
757// Z
0c2e96c1 758static void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 759{
760 gen_mov_reg_Z(dst, src);
761}
762
763// Z | (N ^ V)
0c2e96c1 764static void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 765{
de9e9d9f
RH		 766 TCGv t0 = tcg_temp_new();
767 gen_mov_reg_N(t0, src);
19f329ad 768 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 769 tcg_gen_xor_tl(dst, dst, t0);
770 gen_mov_reg_Z(t0, src);
771 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 772}
773
774// N ^ V
0c2e96c1 775static void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 776{
de9e9d9f
RH		 777 TCGv t0 = tcg_temp_new();
778 gen_mov_reg_V(t0, src);
19f329ad 779 gen_mov_reg_N(dst, src);
de9e9d9f 780 tcg_gen_xor_tl(dst, dst, t0);
19f329ad
BS		 781}
782
783// C | Z
0c2e96c1 784static void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 785{
de9e9d9f
RH		 786 TCGv t0 = tcg_temp_new();
787 gen_mov_reg_Z(t0, src);
19f329ad 788 gen_mov_reg_C(dst, src);
de9e9d9f 789 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 790}
791
792// C
0c2e96c1 793static void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 794{
795 gen_mov_reg_C(dst, src);
796}
797
798// V
0c2e96c1 799static void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 800{
801 gen_mov_reg_V(dst, src);
802}
803
804// 0
0c2e96c1 805static void gen_op_eval_bn(TCGv dst)
19f329ad
BS		 806{
807 tcg_gen_movi_tl(dst, 0);
808}
809
810// N
0c2e96c1 811static void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 812{
813 gen_mov_reg_N(dst, src);
814}
815
816// !Z
0c2e96c1 817static void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 818{
819 gen_mov_reg_Z(dst, src);
820 tcg_gen_xori_tl(dst, dst, 0x1);
821}
822
823// !(Z | (N ^ V))
0c2e96c1 824static void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 825{
de9e9d9f 826 gen_op_eval_ble(dst, src);
19f329ad
BS		 827 tcg_gen_xori_tl(dst, dst, 0x1);
828}
829
830// !(N ^ V)
0c2e96c1 831static void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 832{
de9e9d9f 833 gen_op_eval_bl(dst, src);
19f329ad
BS		 834 tcg_gen_xori_tl(dst, dst, 0x1);
835}
836
837// !(C | Z)
0c2e96c1 838static void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 839{
de9e9d9f 840 gen_op_eval_bleu(dst, src);
19f329ad
BS		 841 tcg_gen_xori_tl(dst, dst, 0x1);
842}
843
844// !C
0c2e96c1 845static void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 846{
847 gen_mov_reg_C(dst, src);
848 tcg_gen_xori_tl(dst, dst, 0x1);
849}
850
851// !N
0c2e96c1 852static void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 853{
854 gen_mov_reg_N(dst, src);
855 tcg_gen_xori_tl(dst, dst, 0x1);
856}
857
858// !V
0c2e96c1 859static void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 860{
861 gen_mov_reg_V(dst, src);
862 tcg_gen_xori_tl(dst, dst, 0x1);
863}
864
865/*
866 FPSR bit field FCC1 | FCC0:
867 0 =
868 1 <
869 2 >
870 3 unordered
871*/
0c2e96c1 872static void gen_mov_reg_FCC0(TCGv reg, TCGv src,
19f329ad
BS		 873 unsigned int fcc_offset)
874{
ba6a9d8c 875 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 876 tcg_gen_andi_tl(reg, reg, 0x1);
877}
878
0c2e96c1 879static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset)
19f329ad 880{
ba6a9d8c 881 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 882 tcg_gen_andi_tl(reg, reg, 0x1);
883}
884
885// !0: FCC0 | FCC1
0c2e96c1 886static void gen_op_eval_fbne(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 887{
de9e9d9f 888 TCGv t0 = tcg_temp_new();
19f329ad 889 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 890 gen_mov_reg_FCC1(t0, src, fcc_offset);
891 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 892}
893
894// 1 or 2: FCC0 ^ FCC1
0c2e96c1 895static void gen_op_eval_fblg(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 896{
de9e9d9f 897 TCGv t0 = tcg_temp_new();
19f329ad 898 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 899 gen_mov_reg_FCC1(t0, src, fcc_offset);
900 tcg_gen_xor_tl(dst, dst, t0);
19f329ad
BS		 901}
902
903// 1 or 3: FCC0
0c2e96c1 904static void gen_op_eval_fbul(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 905{
906 gen_mov_reg_FCC0(dst, src, fcc_offset);
907}
908
909// 1: FCC0 & !FCC1
0c2e96c1 910static void gen_op_eval_fbl(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 911{
de9e9d9f 912 TCGv t0 = tcg_temp_new();
19f329ad 913 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 914 gen_mov_reg_FCC1(t0, src, fcc_offset);
915 tcg_gen_andc_tl(dst, dst, t0);
19f329ad
BS		 916}
917
918// 2 or 3: FCC1
0c2e96c1 919static void gen_op_eval_fbug(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 920{
921 gen_mov_reg_FCC1(dst, src, fcc_offset);
922}
923
924// 2: !FCC0 & FCC1
0c2e96c1 925static void gen_op_eval_fbg(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 926{
de9e9d9f 927 TCGv t0 = tcg_temp_new();
19f329ad 928 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 929 gen_mov_reg_FCC1(t0, src, fcc_offset);
930 tcg_gen_andc_tl(dst, t0, dst);
19f329ad
BS		 931}
932
933// 3: FCC0 & FCC1
0c2e96c1 934static void gen_op_eval_fbu(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 935{
de9e9d9f 936 TCGv t0 = tcg_temp_new();
19f329ad 937 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 938 gen_mov_reg_FCC1(t0, src, fcc_offset);
939 tcg_gen_and_tl(dst, dst, t0);
19f329ad
BS		 940}
941
942// 0: !(FCC0 | FCC1)
0c2e96c1 943static void gen_op_eval_fbe(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 944{
de9e9d9f 945 TCGv t0 = tcg_temp_new();
19f329ad 946 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 947 gen_mov_reg_FCC1(t0, src, fcc_offset);
948 tcg_gen_or_tl(dst, dst, t0);
19f329ad
BS		 949 tcg_gen_xori_tl(dst, dst, 0x1);
950}
951
952// 0 or 3: !(FCC0 ^ FCC1)
0c2e96c1 953static void gen_op_eval_fbue(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 954{
de9e9d9f 955 TCGv t0 = tcg_temp_new();
19f329ad 956 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 957 gen_mov_reg_FCC1(t0, src, fcc_offset);
958 tcg_gen_xor_tl(dst, dst, t0);
19f329ad
BS		 959 tcg_gen_xori_tl(dst, dst, 0x1);
960}
961
962// 0 or 2: !FCC0
0c2e96c1 963static void gen_op_eval_fbge(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 964{
965 gen_mov_reg_FCC0(dst, src, fcc_offset);
966 tcg_gen_xori_tl(dst, dst, 0x1);
967}
968
969// !1: !(FCC0 & !FCC1)
0c2e96c1 970static void gen_op_eval_fbuge(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 971{
de9e9d9f 972 TCGv t0 = tcg_temp_new();
19f329ad 973 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 974 gen_mov_reg_FCC1(t0, src, fcc_offset);
975 tcg_gen_andc_tl(dst, dst, t0);
19f329ad
BS		 976 tcg_gen_xori_tl(dst, dst, 0x1);
977}
978
979// 0 or 1: !FCC1
0c2e96c1 980static void gen_op_eval_fble(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad
BS		 981{
982 gen_mov_reg_FCC1(dst, src, fcc_offset);
983 tcg_gen_xori_tl(dst, dst, 0x1);
984}
985
986// !2: !(!FCC0 & FCC1)
0c2e96c1 987static void gen_op_eval_fbule(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 988{
de9e9d9f 989 TCGv t0 = tcg_temp_new();
19f329ad 990 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 991 gen_mov_reg_FCC1(t0, src, fcc_offset);
992 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 993 tcg_gen_xori_tl(dst, dst, 0x1);
19f329ad
BS		 994}
995
996// !3: !(FCC0 & FCC1)
0c2e96c1 997static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned int fcc_offset)
19f329ad 998{
de9e9d9f 999 TCGv t0 = tcg_temp_new();
19f329ad 1000 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 1001 gen_mov_reg_FCC1(t0, src, fcc_offset);
1002 tcg_gen_and_tl(dst, dst, t0);
19f329ad
BS		 1003 tcg_gen_xori_tl(dst, dst, 0x1);
1004}
1005
0c2e96c1
RH		 1006static void gen_branch2(DisasContext *dc, target_ulong pc1,
1007 target_ulong pc2, TCGv r_cond)
83469015 1008{
42a268c2 1009 TCGLabel *l1 = gen_new_label();
83469015 1010
cb63669a 1011 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1012
6e256c93 1013 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1014
1015 gen_set_label(l1);
6e256c93 1016 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1017}
1018
0c2e96c1 1019static void gen_generic_branch(DisasContext *dc)
83469015 1020{
00ab7e61
RH		 1021 TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]);
1022 TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]);
1023 TCGv zero = tcg_constant_tl(0);
19f329ad 1024
61316742 1025 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015
FB		 1026}
1027
4af984a7
BS		 1028/* call this function before using the condition register as it may
1029 have been set for a jump */
0c2e96c1 1030static void flush_cond(DisasContext *dc)
83469015
FB		 1031{
1032 if (dc->npc == JUMP_PC) {
2e655fe7 1033 gen_generic_branch(dc);
99c82c47 1034 dc->npc = DYNAMIC_PC_LOOKUP;
83469015
FB		 1035 }
1036}
1037
0c2e96c1 1038static void save_npc(DisasContext *dc)
72cbca10 1039{
633c4283
RH		 1040 if (dc->npc & 3) {
1041 switch (dc->npc) {
1042 case JUMP_PC:
1043 gen_generic_branch(dc);
99c82c47 1044 dc->npc = DYNAMIC_PC_LOOKUP;
633c4283
RH		 1045 break;
1046 case DYNAMIC_PC:
1047 case DYNAMIC_PC_LOOKUP:
1048 break;
1049 default:
1050 g_assert_not_reached();
1051 }
1052 } else {
2f5680ee 1053 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1054 }
1055}
1056
0c2e96c1 1057static void update_psr(DisasContext *dc)
72cbca10 1058{
cfa90513
BS		 1059 if (dc->cc_op != CC_OP_FLAGS) {
1060 dc->cc_op = CC_OP_FLAGS;
ad75a51e 1061 gen_helper_compute_psr(tcg_env);
cfa90513 1062 }
20132b96
RH		 1063}
1064
0c2e96c1 1065static void save_state(DisasContext *dc)
20132b96
RH		 1066{
1067 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1068 save_npc(dc);
72cbca10
FB		 1069}
1070
4fbe0067
RH		 1071static void gen_exception(DisasContext *dc, int which)
1072{
4fbe0067 1073 save_state(dc);
ad75a51e 1074 gen_helper_raise_exception(tcg_env, tcg_constant_i32(which));
af00be49 1075 dc->base.is_jmp = DISAS_NORETURN;
4fbe0067
RH		 1076}
1077
186e7890 1078static TCGLabel *delay_exceptionv(DisasContext *dc, TCGv_i32 excp)
35e94905 1079{
186e7890
RH		 1080 DisasDelayException *e = g_new0(DisasDelayException, 1);
1081
1082 e->next = dc->delay_excp_list;
1083 dc->delay_excp_list = e;
1084
1085 e->lab = gen_new_label();
1086 e->excp = excp;
1087 e->pc = dc->pc;
1088 /* Caller must have used flush_cond before branch. */
1089 assert(e->npc != JUMP_PC);
1090 e->npc = dc->npc;
1091
1092 return e->lab;
1093}
1094
1095static TCGLabel *delay_exception(DisasContext *dc, int excp)
1096{
1097 return delay_exceptionv(dc, tcg_constant_i32(excp));
1098}
1099
1100static void gen_check_align(DisasContext *dc, TCGv addr, int mask)
1101{
1102 TCGv t = tcg_temp_new();
1103 TCGLabel *lab;
1104
1105 tcg_gen_andi_tl(t, addr, mask);
1106
1107 flush_cond(dc);
1108 lab = delay_exception(dc, TT_UNALIGNED);
1109 tcg_gen_brcondi_tl(TCG_COND_NE, t, 0, lab);
35e94905
RH		 1110}
1111
0c2e96c1 1112static void gen_mov_pc_npc(DisasContext *dc)
0bee699e 1113{
633c4283
RH		 1114 if (dc->npc & 3) {
1115 switch (dc->npc) {
1116 case JUMP_PC:
1117 gen_generic_branch(dc);
1118 tcg_gen_mov_tl(cpu_pc, cpu_npc);
99c82c47 1119 dc->pc = DYNAMIC_PC_LOOKUP;
633c4283
RH		 1120 break;
1121 case DYNAMIC_PC:
1122 case DYNAMIC_PC_LOOKUP:
1123 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1124 dc->pc = dc->npc;
1125 break;
1126 default:
1127 g_assert_not_reached();
1128 }
0bee699e
FB		 1129 } else {
1130 dc->pc = dc->npc;
1131 }
1132}
1133
0c2e96c1 1134static void gen_op_next_insn(void)
38bc628b 1135{
48d5c82b
BS		 1136 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1137 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1138}
1139
2a484ecf 1140static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1141 DisasContext *dc)
19f329ad 1142{
2a484ecf 1143 static int subcc_cond[16] = {
96b5a3d3 1144 TCG_COND_NEVER,
2a484ecf
RH		 1145 TCG_COND_EQ,
1146 TCG_COND_LE,
1147 TCG_COND_LT,
1148 TCG_COND_LEU,
1149 TCG_COND_LTU,
1150 -1, /* neg */
1151 -1, /* overflow */
96b5a3d3 1152 TCG_COND_ALWAYS,
2a484ecf
RH		 1153 TCG_COND_NE,
1154 TCG_COND_GT,
1155 TCG_COND_GE,
1156 TCG_COND_GTU,
1157 TCG_COND_GEU,
1158 -1, /* pos */
1159 -1, /* no overflow */
1160 };
1161
96b5a3d3
RH		 1162 static int logic_cond[16] = {
1163 TCG_COND_NEVER,
1164 TCG_COND_EQ, /* eq: Z */
1165 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1166 TCG_COND_LT, /* lt: N ^ V -> N */
1167 TCG_COND_EQ, /* leu: C | Z -> Z */
1168 TCG_COND_NEVER, /* ltu: C -> 0 */
1169 TCG_COND_LT, /* neg: N */
1170 TCG_COND_NEVER, /* vs: V -> 0 */
1171 TCG_COND_ALWAYS,
1172 TCG_COND_NE, /* ne: !Z */
1173 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1174 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1175 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1176 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1177 TCG_COND_GE, /* pos: !N */
1178 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1179 };
1180
a7812ae4 1181 TCGv_i32 r_src;
416fcaea
RH		 1182 TCGv r_dst;
1183
3475187d 1184#ifdef TARGET_SPARC64
2a484ecf 1185 if (xcc) {
dc99a3f2 1186 r_src = cpu_xcc;
2a484ecf 1187 } else {
dc99a3f2 1188 r_src = cpu_psr;
2a484ecf 1189 }
3475187d 1190#else
dc99a3f2 1191 r_src = cpu_psr;
3475187d 1192#endif
2a484ecf 1193
8393617c 1194 switch (dc->cc_op) {
96b5a3d3
RH		 1195 case CC_OP_LOGIC:
1196 cmp->cond = logic_cond[cond];
1197 do_compare_dst_0:
1198 cmp->is_bool = false;
00ab7e61 1199 cmp->c2 = tcg_constant_tl(0);
96b5a3d3
RH		 1200#ifdef TARGET_SPARC64
1201 if (!xcc) {
96b5a3d3
RH		 1202 cmp->c1 = tcg_temp_new();
1203 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1204 break;
1205 }
1206#endif
96b5a3d3
RH		 1207 cmp->c1 = cpu_cc_dst;
1208 break;
1209
2a484ecf
RH		 1210 case CC_OP_SUB:
1211 switch (cond) {
1212 case 6: /* neg */
1213 case 14: /* pos */
1214 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1215 goto do_compare_dst_0;
2a484ecf 1216
2a484ecf
RH		 1217 case 7: /* overflow */
1218 case 15: /* !overflow */
1219 goto do_dynamic;
1220
1221 default:
1222 cmp->cond = subcc_cond[cond];
1223 cmp->is_bool = false;
1224#ifdef TARGET_SPARC64
1225 if (!xcc) {
1226 /* Note that sign-extension works for unsigned compares as
1227 long as both operands are sign-extended. */
2a484ecf
RH		 1228 cmp->c1 = tcg_temp_new();
1229 cmp->c2 = tcg_temp_new();
1230 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1231 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1232 break;
2a484ecf
RH		 1233 }
1234#endif
2a484ecf
RH		 1235 cmp->c1 = cpu_cc_src;
1236 cmp->c2 = cpu_cc_src2;
1237 break;
1238 }
8393617c 1239 break;
2a484ecf 1240
8393617c 1241 default:
2a484ecf 1242 do_dynamic:
ad75a51e 1243 gen_helper_compute_psr(tcg_env);
8393617c 1244 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1245 /* FALLTHRU */
1246
1247 case CC_OP_FLAGS:
1248 /* We're going to generate a boolean result. */
1249 cmp->cond = TCG_COND_NE;
1250 cmp->is_bool = true;
2a484ecf 1251 cmp->c1 = r_dst = tcg_temp_new();
00ab7e61 1252 cmp->c2 = tcg_constant_tl(0);
2a484ecf
RH		 1253
1254 switch (cond) {
1255 case 0x0:
1256 gen_op_eval_bn(r_dst);
1257 break;
1258 case 0x1:
1259 gen_op_eval_be(r_dst, r_src);
1260 break;
1261 case 0x2:
1262 gen_op_eval_ble(r_dst, r_src);
1263 break;
1264 case 0x3:
1265 gen_op_eval_bl(r_dst, r_src);
1266 break;
1267 case 0x4:
1268 gen_op_eval_bleu(r_dst, r_src);
1269 break;
1270 case 0x5:
1271 gen_op_eval_bcs(r_dst, r_src);
1272 break;
1273 case 0x6:
1274 gen_op_eval_bneg(r_dst, r_src);
1275 break;
1276 case 0x7:
1277 gen_op_eval_bvs(r_dst, r_src);
1278 break;
1279 case 0x8:
1280 gen_op_eval_ba(r_dst);
1281 break;
1282 case 0x9:
1283 gen_op_eval_bne(r_dst, r_src);
1284 break;
1285 case 0xa:
1286 gen_op_eval_bg(r_dst, r_src);
1287 break;
1288 case 0xb:
1289 gen_op_eval_bge(r_dst, r_src);
1290 break;
1291 case 0xc:
1292 gen_op_eval_bgu(r_dst, r_src);
1293 break;
1294 case 0xd:
1295 gen_op_eval_bcc(r_dst, r_src);
1296 break;
1297 case 0xe:
1298 gen_op_eval_bpos(r_dst, r_src);
1299 break;
1300 case 0xf:
1301 gen_op_eval_bvc(r_dst, r_src);
1302 break;
1303 }
19f329ad
BS		 1304 break;
1305 }
1306}
7a3f1944 1307
416fcaea 1308static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1309{
19f329ad 1310 unsigned int offset;
416fcaea
RH		 1311 TCGv r_dst;
1312
1313 /* For now we still generate a straight boolean result. */
1314 cmp->cond = TCG_COND_NE;
1315 cmp->is_bool = true;
416fcaea 1316 cmp->c1 = r_dst = tcg_temp_new();
00ab7e61 1317 cmp->c2 = tcg_constant_tl(0);
19f329ad 1318
19f329ad
BS		 1319 switch (cc) {
1320 default:
1321 case 0x0:
1322 offset = 0;
1323 break;
1324 case 0x1:
1325 offset = 32 - 10;
1326 break;
1327 case 0x2:
1328 offset = 34 - 10;
1329 break;
1330 case 0x3:
1331 offset = 36 - 10;
1332 break;
1333 }
1334
1335 switch (cond) {
1336 case 0x0:
1337 gen_op_eval_bn(r_dst);
1338 break;
1339 case 0x1:
87e92502 1340 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1341 break;
1342 case 0x2:
87e92502 1343 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1344 break;
1345 case 0x3:
87e92502 1346 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1347 break;
1348 case 0x4:
87e92502 1349 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1350 break;
1351 case 0x5:
87e92502 1352 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1353 break;
1354 case 0x6:
87e92502 1355 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1356 break;
1357 case 0x7:
87e92502 1358 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1359 break;
1360 case 0x8:
1361 gen_op_eval_ba(r_dst);
1362 break;
1363 case 0x9:
87e92502 1364 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1365 break;
1366 case 0xa:
87e92502 1367 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1368 break;
1369 case 0xb:
87e92502 1370 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1371 break;
1372 case 0xc:
87e92502 1373 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1374 break;
1375 case 0xd:
87e92502 1376 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1377 break;
1378 case 0xe:
87e92502 1379 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1380 break;
1381 case 0xf:
87e92502 1382 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1383 break;
1384 }
e8af50a3 1385}
00f219bf
BS		 1386
1387// Inverted logic
ab9ffe98
RH		 1388static const TCGCond gen_tcg_cond_reg[8] = {
1389 TCG_COND_NEVER, /* reserved */
00f219bf
BS		 1390 TCG_COND_NE,
1391 TCG_COND_GT,
1392 TCG_COND_GE,
ab9ffe98 1393 TCG_COND_NEVER, /* reserved */
00f219bf
BS		 1394 TCG_COND_EQ,
1395 TCG_COND_LE,
1396 TCG_COND_LT,
1397};
19f329ad 1398
416fcaea
RH		 1399static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1400{
1401 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1402 cmp->is_bool = false;
416fcaea 1403 cmp->c1 = r_src;
00ab7e61 1404 cmp->c2 = tcg_constant_tl(0);
416fcaea
RH		 1405}
1406
3475187d 1407#ifdef TARGET_SPARC64
0c2e96c1 1408static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1409{
714547bb
BS		 1410 switch (fccno) {
1411 case 0:
ad75a51e 1412 gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1413 break;
1414 case 1:
ad75a51e 1415 gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1416 break;
1417 case 2:
ad75a51e 1418 gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1419 break;
1420 case 3:
ad75a51e 1421 gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1422 break;
1423 }
7e8c2b6c
BS		 1424}
1425
0c2e96c1 1426static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1427{
a7812ae4
PB		 1428 switch (fccno) {
1429 case 0:
ad75a51e 1430 gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1431 break;
1432 case 1:
ad75a51e 1433 gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1434 break;
1435 case 2:
ad75a51e 1436 gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1437 break;
1438 case 3:
ad75a51e 1439 gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1440 break;
1441 }
7e8c2b6c
BS		 1442}
1443
0c2e96c1 1444static void gen_op_fcmpq(int fccno)
7e8c2b6c 1445{
a7812ae4
PB		 1446 switch (fccno) {
1447 case 0:
ad75a51e 1448 gen_helper_fcmpq(cpu_fsr, tcg_env);
a7812ae4
PB		 1449 break;
1450 case 1:
ad75a51e 1451 gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env);
a7812ae4
PB		 1452 break;
1453 case 2:
ad75a51e 1454 gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env);
a7812ae4
PB		 1455 break;
1456 case 3:
ad75a51e 1457 gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env);
a7812ae4
PB		 1458 break;
1459 }
7e8c2b6c 1460}
7e8c2b6c 1461
0c2e96c1 1462static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1463{
714547bb
BS		 1464 switch (fccno) {
1465 case 0:
ad75a51e 1466 gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1467 break;
1468 case 1:
ad75a51e 1469 gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1470 break;
1471 case 2:
ad75a51e 1472 gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1473 break;
1474 case 3:
ad75a51e 1475 gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
714547bb
BS		 1476 break;
1477 }
7e8c2b6c
BS		 1478}
1479
0c2e96c1 1480static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1481{
a7812ae4
PB		 1482 switch (fccno) {
1483 case 0:
ad75a51e 1484 gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1485 break;
1486 case 1:
ad75a51e 1487 gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1488 break;
1489 case 2:
ad75a51e 1490 gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1491 break;
1492 case 3:
ad75a51e 1493 gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
a7812ae4
PB		 1494 break;
1495 }
7e8c2b6c
BS		 1496}
1497
0c2e96c1 1498static void gen_op_fcmpeq(int fccno)
7e8c2b6c 1499{
a7812ae4
PB		 1500 switch (fccno) {
1501 case 0:
ad75a51e 1502 gen_helper_fcmpeq(cpu_fsr, tcg_env);
a7812ae4
PB		 1503 break;
1504 case 1:
ad75a51e 1505 gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env);
a7812ae4
PB		 1506 break;
1507 case 2:
ad75a51e 1508 gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env);
a7812ae4
PB		 1509 break;
1510 case 3:
ad75a51e 1511 gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env);
a7812ae4
PB		 1512 break;
1513 }
7e8c2b6c 1514}
7e8c2b6c
BS		 1515
1516#else
1517
0c2e96c1 1518static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1519{
ad75a51e 1520 gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1521}
1522
0c2e96c1 1523static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1524{
ad75a51e 1525 gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1526}
1527
0c2e96c1 1528static void gen_op_fcmpq(int fccno)
7e8c2b6c 1529{
ad75a51e 1530 gen_helper_fcmpq(cpu_fsr, tcg_env);
7e8c2b6c 1531}
7e8c2b6c 1532
0c2e96c1 1533static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1534{
ad75a51e 1535 gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1536}
1537
0c2e96c1 1538static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1539{
ad75a51e 1540 gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1541}
1542
0c2e96c1 1543static void gen_op_fcmpeq(int fccno)
7e8c2b6c 1544{
ad75a51e 1545 gen_helper_fcmpeq(cpu_fsr, tcg_env);
7e8c2b6c
BS		 1546}
1547#endif
1548
4fbe0067 1549static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1550{
47ad35f1 1551 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1552 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1553 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1554}
1555
5b12f1e8 1556static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1557{
1558#if !defined(CONFIG_USER_ONLY)
1559 if (!dc->fpu_enabled) {
4fbe0067 1560 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1561 return 1;
1562 }
1563#endif
1564 return 0;
1565}
1566
0c2e96c1 1567static void gen_op_clear_ieee_excp_and_FTT(void)
7e8c2b6c 1568{
47ad35f1 1569 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1570}
1571
0c2e96c1 1572static void gen_fop_FF(DisasContext *dc, int rd, int rs,
61f17f6e
RH		 1573 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1574{
1575 TCGv_i32 dst, src;
1576
61f17f6e 1577 src = gen_load_fpr_F(dc, rs);
ba5f5179 1578 dst = gen_dest_fpr_F(dc);
61f17f6e 1579
ad75a51e
RH		 1580 gen(dst, tcg_env, src);
1581 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1582
61f17f6e
RH		 1583 gen_store_fpr_F(dc, rd, dst);
1584}
1585
0c2e96c1
RH		 1586static void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1587 void (*gen)(TCGv_i32, TCGv_i32))
61f17f6e
RH		 1588{
1589 TCGv_i32 dst, src;
1590
1591 src = gen_load_fpr_F(dc, rs);
ba5f5179 1592 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1593
1594 gen(dst, src);
1595
1596 gen_store_fpr_F(dc, rd, dst);
1597}
1598
0c2e96c1 1599static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
61f17f6e
RH		 1600 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1601{
1602 TCGv_i32 dst, src1, src2;
1603
61f17f6e
RH		 1604 src1 = gen_load_fpr_F(dc, rs1);
1605 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1606 dst = gen_dest_fpr_F(dc);
61f17f6e 1607
ad75a51e
RH		 1608 gen(dst, tcg_env, src1, src2);
1609 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1610
61f17f6e
RH		 1611 gen_store_fpr_F(dc, rd, dst);
1612}
1613
1614#ifdef TARGET_SPARC64
0c2e96c1
RH		 1615static void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1616 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
61f17f6e
RH		 1617{
1618 TCGv_i32 dst, src1, src2;
1619
1620 src1 = gen_load_fpr_F(dc, rs1);
1621 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1622 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1623
1624 gen(dst, src1, src2);
1625
1626 gen_store_fpr_F(dc, rd, dst);
1627}
1628#endif
1629
0c2e96c1
RH		 1630static void gen_fop_DD(DisasContext *dc, int rd, int rs,
1631 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
61f17f6e
RH		 1632{
1633 TCGv_i64 dst, src;
1634
61f17f6e 1635 src = gen_load_fpr_D(dc, rs);
3886b8a3 1636 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1637
ad75a51e
RH		 1638 gen(dst, tcg_env, src);
1639 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1640
61f17f6e
RH		 1641 gen_store_fpr_D(dc, rd, dst);
1642}
1643
1644#ifdef TARGET_SPARC64
0c2e96c1
RH		 1645static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1646 void (*gen)(TCGv_i64, TCGv_i64))
61f17f6e
RH		 1647{
1648 TCGv_i64 dst, src;
1649
1650 src = gen_load_fpr_D(dc, rs);
3886b8a3 1651 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1652
1653 gen(dst, src);
1654
1655 gen_store_fpr_D(dc, rd, dst);
1656}
1657#endif
1658
0c2e96c1 1659static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
61f17f6e
RH		 1660 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1661{
1662 TCGv_i64 dst, src1, src2;
1663
61f17f6e
RH		 1664 src1 = gen_load_fpr_D(dc, rs1);
1665 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1666 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1667
ad75a51e
RH		 1668 gen(dst, tcg_env, src1, src2);
1669 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1670
61f17f6e
RH		 1671 gen_store_fpr_D(dc, rd, dst);
1672}
1673
1674#ifdef TARGET_SPARC64
0c2e96c1
RH		 1675static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1676 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
61f17f6e
RH		 1677{
1678 TCGv_i64 dst, src1, src2;
1679
1680 src1 = gen_load_fpr_D(dc, rs1);
1681 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1682 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1683
1684 gen(dst, src1, src2);
1685
1686 gen_store_fpr_D(dc, rd, dst);
1687}
f888300b 1688
0c2e96c1
RH		 1689static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1690 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
2dedf314
RH		 1691{
1692 TCGv_i64 dst, src1, src2;
1693
1694 src1 = gen_load_fpr_D(dc, rs1);
1695 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1696 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1697
1698 gen(dst, cpu_gsr, src1, src2);
1699
1700 gen_store_fpr_D(dc, rd, dst);
1701}
1702
0c2e96c1
RH		 1703static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1704 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
f888300b
RH		 1705{
1706 TCGv_i64 dst, src0, src1, src2;
1707
1708 src1 = gen_load_fpr_D(dc, rs1);
1709 src2 = gen_load_fpr_D(dc, rs2);
1710 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1711 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1712
1713 gen(dst, src0, src1, src2);
1714
1715 gen_store_fpr_D(dc, rd, dst);
1716}
61f17f6e
RH		 1717#endif
1718
0c2e96c1
RH		 1719static void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1720 void (*gen)(TCGv_ptr))
61f17f6e 1721{
61f17f6e
RH		 1722 gen_op_load_fpr_QT1(QFPREG(rs));
1723
ad75a51e
RH		 1724 gen(tcg_env);
1725 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1726
61f17f6e 1727 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1728 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1729}
1730
1731#ifdef TARGET_SPARC64
0c2e96c1
RH		 1732static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1733 void (*gen)(TCGv_ptr))
61f17f6e
RH		 1734{
1735 gen_op_load_fpr_QT1(QFPREG(rs));
1736
ad75a51e 1737 gen(tcg_env);
61f17f6e
RH		 1738
1739 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1740 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1741}
1742#endif
1743
0c2e96c1
RH		 1744static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1745 void (*gen)(TCGv_ptr))
61f17f6e 1746{
61f17f6e
RH		 1747 gen_op_load_fpr_QT0(QFPREG(rs1));
1748 gen_op_load_fpr_QT1(QFPREG(rs2));
1749
ad75a51e
RH		 1750 gen(tcg_env);
1751 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1752
61f17f6e 1753 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1754 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1755}
1756
0c2e96c1 1757static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
61f17f6e
RH		 1758 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1759{
1760 TCGv_i64 dst;
1761 TCGv_i32 src1, src2;
1762
61f17f6e
RH		 1763 src1 = gen_load_fpr_F(dc, rs1);
1764 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1765 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1766
ad75a51e
RH		 1767 gen(dst, tcg_env, src1, src2);
1768 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1769
61f17f6e
RH		 1770 gen_store_fpr_D(dc, rd, dst);
1771}
1772
0c2e96c1
RH		 1773static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1774 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
61f17f6e
RH		 1775{
1776 TCGv_i64 src1, src2;
1777
61f17f6e
RH		 1778 src1 = gen_load_fpr_D(dc, rs1);
1779 src2 = gen_load_fpr_D(dc, rs2);
1780
ad75a51e
RH		 1781 gen(tcg_env, src1, src2);
1782 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1783
61f17f6e 1784 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1785 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1786}
1787
1788#ifdef TARGET_SPARC64
0c2e96c1
RH		 1789static void gen_fop_DF(DisasContext *dc, int rd, int rs,
1790 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
61f17f6e
RH		 1791{
1792 TCGv_i64 dst;
1793 TCGv_i32 src;
1794
61f17f6e 1795 src = gen_load_fpr_F(dc, rs);
3886b8a3 1796 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1797
ad75a51e
RH		 1798 gen(dst, tcg_env, src);
1799 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1800
61f17f6e
RH		 1801 gen_store_fpr_D(dc, rd, dst);
1802}
1803#endif
1804
0c2e96c1
RH		 1805static void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1806 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
61f17f6e
RH		 1807{
1808 TCGv_i64 dst;
1809 TCGv_i32 src;
1810
1811 src = gen_load_fpr_F(dc, rs);
3886b8a3 1812 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1813
ad75a51e 1814 gen(dst, tcg_env, src);
61f17f6e
RH		 1815
1816 gen_store_fpr_D(dc, rd, dst);
1817}
1818
0c2e96c1
RH		 1819static void gen_fop_FD(DisasContext *dc, int rd, int rs,
1820 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
61f17f6e
RH		 1821{
1822 TCGv_i32 dst;
1823 TCGv_i64 src;
1824
61f17f6e 1825 src = gen_load_fpr_D(dc, rs);
ba5f5179 1826 dst = gen_dest_fpr_F(dc);
61f17f6e 1827
ad75a51e
RH		 1828 gen(dst, tcg_env, src);
1829 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1830
61f17f6e
RH		 1831 gen_store_fpr_F(dc, rd, dst);
1832}
1833
0c2e96c1
RH		 1834static void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1835 void (*gen)(TCGv_i32, TCGv_ptr))
61f17f6e
RH		 1836{
1837 TCGv_i32 dst;
1838
61f17f6e 1839 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1840 dst = gen_dest_fpr_F(dc);
61f17f6e 1841
ad75a51e
RH		 1842 gen(dst, tcg_env);
1843 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1844
61f17f6e
RH		 1845 gen_store_fpr_F(dc, rd, dst);
1846}
1847
0c2e96c1
RH		 1848static void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1849 void (*gen)(TCGv_i64, TCGv_ptr))
61f17f6e
RH		 1850{
1851 TCGv_i64 dst;
1852
61f17f6e 1853 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1854 dst = gen_dest_fpr_D(dc, rd);
61f17f6e 1855
ad75a51e
RH		 1856 gen(dst, tcg_env);
1857 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
61f17f6e 1858
61f17f6e
RH		 1859 gen_store_fpr_D(dc, rd, dst);
1860}
1861
0c2e96c1
RH		 1862static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1863 void (*gen)(TCGv_ptr, TCGv_i32))
61f17f6e
RH		 1864{
1865 TCGv_i32 src;
1866
1867 src = gen_load_fpr_F(dc, rs);
1868
ad75a51e 1869 gen(tcg_env, src);
61f17f6e
RH		 1870
1871 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1872 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1873}
1874
0c2e96c1
RH		 1875static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1876 void (*gen)(TCGv_ptr, TCGv_i64))
61f17f6e
RH		 1877{
1878 TCGv_i64 src;
1879
1880 src = gen_load_fpr_D(dc, rs);
1881
ad75a51e 1882 gen(tcg_env, src);
61f17f6e
RH		 1883
1884 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1885 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1886}
1887
4fb554bc 1888static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
14776ab5 1889 TCGv addr, int mmu_idx, MemOp memop)
4fb554bc 1890{
4fb554bc 1891 gen_address_mask(dc, addr);
316b6783 1892 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN);
4fb554bc
RH		 1893}
1894
fbb4bbb6
RH		 1895static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
1896{
00ab7e61 1897 TCGv m1 = tcg_constant_tl(0xff);
fbb4bbb6 1898 gen_address_mask(dc, addr);
da1bcae6 1899 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
fbb4bbb6
RH		 1900}
1901
1a2fb1c0 1902/* asi moves */
7ec1e5ea
RH		 1903typedef enum {
1904 GET_ASI_HELPER,
1905 GET_ASI_EXCP,
f0913be0 1906 GET_ASI_DIRECT,
e4dc0052 1907 GET_ASI_DTWINX,
ca5ce572
RH		 1908 GET_ASI_BLOCK,
1909 GET_ASI_SHORT,
34810610
RH		 1910 GET_ASI_BCOPY,
1911 GET_ASI_BFILL,
7ec1e5ea
RH		 1912} ASIType;
1913
1914typedef struct {
1915 ASIType type;
a6d567e5 1916 int asi;
f0913be0 1917 int mem_idx;
14776ab5 1918 MemOp memop;
7ec1e5ea 1919} DisasASI;
1a2fb1c0 1920
811cc0b0
RH		 1921/*
1922 * Build DisasASI.
1923 * For asi == -1, treat as non-asi.
1924 * For ask == -2, treat as immediate offset (v8 error, v9 %asi).
1925 */
1926static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop)
7ec1e5ea 1927{
7ec1e5ea 1928 ASIType type = GET_ASI_HELPER;
f0913be0 1929 int mem_idx = dc->mem_idx;
7ec1e5ea 1930
811cc0b0
RH		 1931 if (asi == -1) {
1932 /* Artificial "non-asi" case. */
1933 type = GET_ASI_DIRECT;
1934 goto done;
1935 }
1936
7ec1e5ea
RH		 1937#ifndef TARGET_SPARC64
1938 /* Before v9, all asis are immediate and privileged. */
811cc0b0 1939 if (asi < 0) {
22e70060 1940 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 1941 type = GET_ASI_EXCP;
1942 } else if (supervisor(dc)
1943 /* Note that LEON accepts ASI_USERDATA in user mode, for
1944 use with CASA. Also note that previous versions of
0cc1f4bf
RH		 1945 QEMU allowed (and old versions of gcc emitted) ASI_P
1946 for LEON, which is incorrect. */
1947 || (asi == ASI_USERDATA
7ec1e5ea 1948 && (dc->def->features & CPU_FEATURE_CASA))) {
f0913be0
RH		 1949 switch (asi) {
1950 case ASI_USERDATA: /* User data access */
1951 mem_idx = MMU_USER_IDX;
1952 type = GET_ASI_DIRECT;
1953 break;
1954 case ASI_KERNELDATA: /* Supervisor data access */
1955 mem_idx = MMU_KERNEL_IDX;
1956 type = GET_ASI_DIRECT;
1957 break;
7f87c905
RH		 1958 case ASI_M_BYPASS: /* MMU passthrough */
1959 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1960 mem_idx = MMU_PHYS_IDX;
1961 type = GET_ASI_DIRECT;
1962 break;
34810610
RH		 1963 case ASI_M_BCOPY: /* Block copy, sta access */
1964 mem_idx = MMU_KERNEL_IDX;
1965 type = GET_ASI_BCOPY;
1966 break;
1967 case ASI_M_BFILL: /* Block fill, stda access */
1968 mem_idx = MMU_KERNEL_IDX;
1969 type = GET_ASI_BFILL;
1970 break;
f0913be0 1971 }
6e10f37c
KF		 1972
1973 /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the
1974 * permissions check in get_physical_address(..).
1975 */
1976 mem_idx = (dc->mem_idx == MMU_PHYS_IDX) ? MMU_PHYS_IDX : mem_idx;
1a2fb1c0 1977 } else {
7ec1e5ea
RH		 1978 gen_exception(dc, TT_PRIV_INSN);
1979 type = GET_ASI_EXCP;
1980 }
1981#else
811cc0b0 1982 if (asi < 0) {
7ec1e5ea 1983 asi = dc->asi;
1a2fb1c0 1984 }
f0913be0
RH		 1985 /* With v9, all asis below 0x80 are privileged. */
1986 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
1987 down that bit into DisasContext. For the moment that's ok,
1988 since the direct implementations below doesn't have any ASIs
1989 in the restricted [0x30, 0x7f] range, and the check will be
1990 done properly in the helper. */
1991 if (!supervisor(dc) && asi < 0x80) {
1992 gen_exception(dc, TT_PRIV_ACT);
1993 type = GET_ASI_EXCP;
1994 } else {
1995 switch (asi) {
7f87c905
RH		 1996 case ASI_REAL: /* Bypass */
1997 case ASI_REAL_IO: /* Bypass, non-cacheable */
1998 case ASI_REAL_L: /* Bypass LE */
1999 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2000 case ASI_TWINX_REAL: /* Real address, twinx */
2001 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
34a6e13d
RH		 2002 case ASI_QUAD_LDD_PHYS:
2003 case ASI_QUAD_LDD_PHYS_L:
7f87c905
RH		 2004 mem_idx = MMU_PHYS_IDX;
2005 break;
f0913be0
RH		 2006 case ASI_N: /* Nucleus */
2007 case ASI_NL: /* Nucleus LE */
e4dc0052
RH		 2008 case ASI_TWINX_N:
2009 case ASI_TWINX_NL:
34a6e13d
RH		 2010 case ASI_NUCLEUS_QUAD_LDD:
2011 case ASI_NUCLEUS_QUAD_LDD_L:
9a10756d 2012 if (hypervisor(dc)) {
84f8f587 2013 mem_idx = MMU_PHYS_IDX;
9a10756d
AT		 2014 } else {
2015 mem_idx = MMU_NUCLEUS_IDX;
2016 }
f0913be0
RH		 2017 break;
2018 case ASI_AIUP: /* As if user primary */
2019 case ASI_AIUPL: /* As if user primary LE */
e4dc0052
RH		 2020 case ASI_TWINX_AIUP:
2021 case ASI_TWINX_AIUP_L:
ca5ce572
RH		 2022 case ASI_BLK_AIUP_4V:
2023 case ASI_BLK_AIUP_L_4V:
2024 case ASI_BLK_AIUP:
2025 case ASI_BLK_AIUPL:
f0913be0
RH		 2026 mem_idx = MMU_USER_IDX;
2027 break;
2028 case ASI_AIUS: /* As if user secondary */
2029 case ASI_AIUSL: /* As if user secondary LE */
e4dc0052
RH		 2030 case ASI_TWINX_AIUS:
2031 case ASI_TWINX_AIUS_L:
ca5ce572
RH		 2032 case ASI_BLK_AIUS_4V:
2033 case ASI_BLK_AIUS_L_4V:
2034 case ASI_BLK_AIUS:
2035 case ASI_BLK_AIUSL:
f0913be0
RH		 2036 mem_idx = MMU_USER_SECONDARY_IDX;
2037 break;
2038 case ASI_S: /* Secondary */
2039 case ASI_SL: /* Secondary LE */
e4dc0052
RH		 2040 case ASI_TWINX_S:
2041 case ASI_TWINX_SL:
ca5ce572
RH		 2042 case ASI_BLK_COMMIT_S:
2043 case ASI_BLK_S:
2044 case ASI_BLK_SL:
2045 case ASI_FL8_S:
2046 case ASI_FL8_SL:
2047 case ASI_FL16_S:
2048 case ASI_FL16_SL:
f0913be0
RH		 2049 if (mem_idx == MMU_USER_IDX) {
2050 mem_idx = MMU_USER_SECONDARY_IDX;
2051 } else if (mem_idx == MMU_KERNEL_IDX) {
2052 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2053 }
2054 break;
2055 case ASI_P: /* Primary */
2056 case ASI_PL: /* Primary LE */
e4dc0052
RH		 2057 case ASI_TWINX_P:
2058 case ASI_TWINX_PL:
ca5ce572
RH		 2059 case ASI_BLK_COMMIT_P:
2060 case ASI_BLK_P:
2061 case ASI_BLK_PL:
2062 case ASI_FL8_P:
2063 case ASI_FL8_PL:
2064 case ASI_FL16_P:
2065 case ASI_FL16_PL:
f0913be0
RH		 2066 break;
2067 }
2068 switch (asi) {
7f87c905
RH		 2069 case ASI_REAL:
2070 case ASI_REAL_IO:
2071 case ASI_REAL_L:
2072 case ASI_REAL_IO_L:
f0913be0
RH		 2073 case ASI_N:
2074 case ASI_NL:
2075 case ASI_AIUP:
2076 case ASI_AIUPL:
2077 case ASI_AIUS:
2078 case ASI_AIUSL:
2079 case ASI_S:
2080 case ASI_SL:
2081 case ASI_P:
2082 case ASI_PL:
2083 type = GET_ASI_DIRECT;
2084 break;
7f87c905
RH		 2085 case ASI_TWINX_REAL:
2086 case ASI_TWINX_REAL_L:
e4dc0052
RH		 2087 case ASI_TWINX_N:
2088 case ASI_TWINX_NL:
2089 case ASI_TWINX_AIUP:
2090 case ASI_TWINX_AIUP_L:
2091 case ASI_TWINX_AIUS:
2092 case ASI_TWINX_AIUS_L:
2093 case ASI_TWINX_P:
2094 case ASI_TWINX_PL:
2095 case ASI_TWINX_S:
2096 case ASI_TWINX_SL:
34a6e13d
RH		 2097 case ASI_QUAD_LDD_PHYS:
2098 case ASI_QUAD_LDD_PHYS_L:
2099 case ASI_NUCLEUS_QUAD_LDD:
2100 case ASI_NUCLEUS_QUAD_LDD_L:
e4dc0052
RH		 2101 type = GET_ASI_DTWINX;
2102 break;
ca5ce572
RH		 2103 case ASI_BLK_COMMIT_P:
2104 case ASI_BLK_COMMIT_S:
2105 case ASI_BLK_AIUP_4V:
2106 case ASI_BLK_AIUP_L_4V:
2107 case ASI_BLK_AIUP:
2108 case ASI_BLK_AIUPL:
2109 case ASI_BLK_AIUS_4V:
2110 case ASI_BLK_AIUS_L_4V:
2111 case ASI_BLK_AIUS:
2112 case ASI_BLK_AIUSL:
2113 case ASI_BLK_S:
2114 case ASI_BLK_SL:
2115 case ASI_BLK_P:
2116 case ASI_BLK_PL:
2117 type = GET_ASI_BLOCK;
2118 break;
2119 case ASI_FL8_S:
2120 case ASI_FL8_SL:
2121 case ASI_FL8_P:
2122 case ASI_FL8_PL:
2123 memop = MO_UB;
2124 type = GET_ASI_SHORT;
2125 break;
2126 case ASI_FL16_S:
2127 case ASI_FL16_SL:
2128 case ASI_FL16_P:
2129 case ASI_FL16_PL:
2130 memop = MO_TEUW;
2131 type = GET_ASI_SHORT;
2132 break;
f0913be0
RH		 2133 }
2134 /* The little-endian asis all have bit 3 set. */
2135 if (asi & 8) {
2136 memop ^= MO_BSWAP;
2137 }
2138 }
7ec1e5ea
RH		 2139#endif
2140
811cc0b0 2141 done:
f0913be0 2142 return (DisasASI){ type, asi, mem_idx, memop };
0425bee5
BS		 2143}
2144
811cc0b0
RH		 2145static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
2146{
2147 int asi = IS_IMM ? -2 : GET_FIELD(insn, 19, 26);
2148 return resolve_asi(dc, asi, memop);
2149}
2150
a76779ee
RH		 2151#if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2152static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a,
2153 TCGv_i32 asi, TCGv_i32 mop)
2154{
2155 g_assert_not_reached();
2156}
2157
2158static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r,
2159 TCGv_i32 asi, TCGv_i32 mop)
2160{
2161 g_assert_not_reached();
2162}
2163#endif
2164
c03a0fd1 2165static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
0425bee5 2166{
c03a0fd1 2167 switch (da->type) {
7ec1e5ea
RH		 2168 case GET_ASI_EXCP:
2169 break;
e4dc0052
RH		 2170 case GET_ASI_DTWINX: /* Reserved for ldda. */
2171 gen_exception(dc, TT_ILL_INSN);
2172 break;
f0913be0 2173 case GET_ASI_DIRECT:
c03a0fd1 2174 tcg_gen_qemu_ld_tl(dst, addr, da->mem_idx, da->memop | MO_ALIGN);
f0913be0 2175 break;
7ec1e5ea
RH		 2176 default:
2177 {
c03a0fd1
RH		 2178 TCGv_i32 r_asi = tcg_constant_i32(da->asi);
2179 TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN);
7ec1e5ea
RH		 2180
2181 save_state(dc);
22e70060 2182#ifdef TARGET_SPARC64
ad75a51e 2183 gen_helper_ld_asi(dst, tcg_env, addr, r_asi, r_mop);
22e70060 2184#else
7ec1e5ea
RH		 2185 {
2186 TCGv_i64 t64 = tcg_temp_new_i64();
ad75a51e 2187 gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
7ec1e5ea 2188 tcg_gen_trunc_i64_tl(dst, t64);
7ec1e5ea 2189 }
22e70060 2190#endif
7ec1e5ea
RH		 2191 }
2192 break;
2193 }
1a2fb1c0
BS		 2194}
2195
a76779ee 2196static void __attribute__((unused))
c03a0fd1 2197gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop)
1a2fb1c0 2198{
f0913be0 2199 DisasASI da = get_asi(dc, insn, memop);
1a2fb1c0 2200
c03a0fd1
RH		 2201 gen_address_mask(dc, addr);
2202 gen_ld_asi0(dc, &da, dst, addr);
2203}
2204
2205static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr)
2206{
2207 switch (da->type) {
7ec1e5ea
RH		 2208 case GET_ASI_EXCP:
2209 break;
c03a0fd1 2210
e4dc0052 2211 case GET_ASI_DTWINX: /* Reserved for stda. */
c03a0fd1
RH		 2212 if (TARGET_LONG_BITS == 32) {
2213 gen_exception(dc, TT_ILL_INSN);
2214 break;
2215 } else if (!(dc->def->features & CPU_FEATURE_HYPV)) {
3390537b
AT		 2216 /* Pre OpenSPARC CPUs don't have these */
2217 gen_exception(dc, TT_ILL_INSN);
c03a0fd1 2218 break;
3390537b 2219 }
c03a0fd1 2220 /* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs */
fc0cd867 2221 /* fall through */
c03a0fd1 2222
f0913be0 2223 case GET_ASI_DIRECT:
c03a0fd1 2224 tcg_gen_qemu_st_tl(src, addr, da->mem_idx, da->memop | MO_ALIGN);
f0913be0 2225 break;
c03a0fd1 2226
34810610 2227 case GET_ASI_BCOPY:
c03a0fd1 2228 assert(TARGET_LONG_BITS == 32);
34810610
RH		 2229 /* Copy 32 bytes from the address in SRC to ADDR. */
2230 /* ??? The original qemu code suggests 4-byte alignment, dropping
2231 the low bits, but the only place I can see this used is in the
2232 Linux kernel with 32 byte alignment, which would make more sense
2233 as a cacheline-style operation. */
2234 {
2235 TCGv saddr = tcg_temp_new();
2236 TCGv daddr = tcg_temp_new();
00ab7e61 2237 TCGv four = tcg_constant_tl(4);
34810610
RH		 2238 TCGv_i32 tmp = tcg_temp_new_i32();
2239 int i;
2240
2241 tcg_gen_andi_tl(saddr, src, -4);
2242 tcg_gen_andi_tl(daddr, addr, -4);
2243 for (i = 0; i < 32; i += 4) {
2244 /* Since the loads and stores are paired, allow the
2245 copy to happen in the host endianness. */
c03a0fd1
RH		 2246 tcg_gen_qemu_ld_i32(tmp, saddr, da->mem_idx, MO_UL);
2247 tcg_gen_qemu_st_i32(tmp, daddr, da->mem_idx, MO_UL);
34810610
RH		 2248 tcg_gen_add_tl(saddr, saddr, four);
2249 tcg_gen_add_tl(daddr, daddr, four);
2250 }
34810610
RH		 2251 }
2252 break;
c03a0fd1 2253
7ec1e5ea
RH		 2254 default:
2255 {
c03a0fd1
RH		 2256 TCGv_i32 r_asi = tcg_constant_i32(da->asi);
2257 TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN);
7ec1e5ea
RH		 2258
2259 save_state(dc);
22e70060 2260#ifdef TARGET_SPARC64
ad75a51e 2261 gen_helper_st_asi(tcg_env, addr, src, r_asi, r_mop);
22e70060 2262#else
7ec1e5ea
RH		 2263 {
2264 TCGv_i64 t64 = tcg_temp_new_i64();
2265 tcg_gen_extu_tl_i64(t64, src);
ad75a51e 2266 gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
7ec1e5ea 2267 }
22e70060 2268#endif
7ec1e5ea
RH		 2269
2270 /* A write to a TLB register may alter page maps. End the TB. */
2271 dc->npc = DYNAMIC_PC;
2272 }
2273 break;
2274 }
1a2fb1c0
BS		 2275}
2276
a76779ee 2277static void __attribute__((unused))
c03a0fd1 2278gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
1a2fb1c0 2279{
c03a0fd1 2280 DisasASI da = get_asi(dc, insn, memop);
22e70060 2281
c03a0fd1
RH		 2282 gen_address_mask(dc, addr);
2283 gen_st_asi0(dc, &da, src, addr);
2284}
2285
2286static void gen_swap_asi0(DisasContext *dc, DisasASI *da,
2287 TCGv dst, TCGv src, TCGv addr)
2288{
2289 switch (da->type) {
7ec1e5ea
RH		 2290 case GET_ASI_EXCP:
2291 break;
4fb554bc 2292 case GET_ASI_DIRECT:
c03a0fd1 2293 gen_swap(dc, dst, src, addr, da->mem_idx, da->memop);
4fb554bc 2294 break;
7ec1e5ea 2295 default:
4fb554bc
RH		 2296 /* ??? Should be DAE_invalid_asi. */
2297 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2298 break;
2299 }
1a2fb1c0
BS		 2300}
2301
a76779ee 2302static void __attribute__((unused))
c03a0fd1 2303gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn)
22e70060 2304{
f0913be0 2305 DisasASI da = get_asi(dc, insn, MO_TEUL);
22e70060 2306
c03a0fd1
RH		 2307 gen_address_mask(dc, addr);
2308 gen_swap_asi0(dc, &da, dst, src, addr);
2309}
2310
2311static void gen_cas_asi0(DisasContext *dc, DisasASI *da,
2312 TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr)
2313{
2314 switch (da->type) {
7268adeb 2315 case GET_ASI_EXCP:
7ec1e5ea 2316 return;
7268adeb 2317 case GET_ASI_DIRECT:
c03a0fd1
RH		 2318 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, newv,
2319 da->mem_idx, da->memop | MO_ALIGN);
7268adeb
RH		 2320 break;
2321 default:
2322 /* ??? Should be DAE_invalid_asi. */
2323 gen_exception(dc, TT_DATA_ACCESS);
2324 break;
7ec1e5ea 2325 }
22e70060
RH		 2326}
2327
a76779ee 2328static void __attribute__((unused))
c03a0fd1 2329gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
22e70060 2330{
c03a0fd1
RH		 2331 DisasASI da = get_asi(dc, insn, MO_TEUL);
2332 TCGv oldv = gen_dest_gpr(dc, rd);
2333 TCGv newv = gen_load_gpr(dc, rd);
22e70060 2334
c03a0fd1
RH		 2335 gen_address_mask(dc, addr);
2336 gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr);
2337 gen_store_gpr(dc, rd, oldv);
2338}
2339
2340static void __attribute__((unused))
2341gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
2342{
2343 DisasASI da = get_asi(dc, insn, MO_TEUQ);
2344 TCGv oldv = gen_dest_gpr(dc, rd);
2345 TCGv newv = gen_load_gpr(dc, rd);
2346
2347 gen_address_mask(dc, addr);
2348 gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr);
2349 gen_store_gpr(dc, rd, oldv);
2350}
2351
2352static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
2353{
2354 switch (da->type) {
7ec1e5ea
RH		 2355 case GET_ASI_EXCP:
2356 break;
fbb4bbb6 2357 case GET_ASI_DIRECT:
c03a0fd1 2358 gen_ldstub(dc, dst, addr, da->mem_idx);
fbb4bbb6 2359 break;
7ec1e5ea 2360 default:
3db010c3
RH		 2361 /* ??? In theory, this should be raise DAE_invalid_asi.
2362 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
af00be49 2363 if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
ad75a51e 2364 gen_helper_exit_atomic(tcg_env);
3db010c3 2365 } else {
c03a0fd1 2366 TCGv_i32 r_asi = tcg_constant_i32(da->asi);
00ab7e61 2367 TCGv_i32 r_mop = tcg_constant_i32(MO_UB);
3db010c3
RH		 2368 TCGv_i64 s64, t64;
2369
2370 save_state(dc);
2371 t64 = tcg_temp_new_i64();
ad75a51e 2372 gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
3db010c3 2373
00ab7e61 2374 s64 = tcg_constant_i64(0xff);
ad75a51e 2375 gen_helper_st_asi(tcg_env, addr, s64, r_asi, r_mop);
3db010c3
RH		 2376
2377 tcg_gen_trunc_i64_tl(dst, t64);
3db010c3
RH		 2378
2379 /* End the TB. */
2380 dc->npc = DYNAMIC_PC;
2381 }
7ec1e5ea
RH		 2382 break;
2383 }
22e70060 2384}
22e70060 2385
c03a0fd1
RH		 2386static void __attribute__((unused))
2387gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2388{
2389 DisasASI da = get_asi(dc, insn, MO_UB);
2390
2391 gen_address_mask(dc, addr);
2392 gen_ldstub_asi0(dc, &da, dst, addr);
2393}
2394
a76779ee
RH		 2395static void __attribute__((unused))
2396gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
1a2fb1c0 2397{
fc313c64 2398 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
7705091c 2399 TCGv_i32 d32;
cb21b4da 2400 TCGv_i64 d64;
1a2fb1c0 2401
7ec1e5ea
RH		 2402 switch (da.type) {
2403 case GET_ASI_EXCP:
2404 break;
7705091c
RH		 2405
2406 case GET_ASI_DIRECT:
2407 gen_address_mask(dc, addr);
2408 switch (size) {
2409 case 4:
2410 d32 = gen_dest_fpr_F(dc);
316b6783 2411 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
7705091c
RH		 2412 gen_store_fpr_F(dc, rd, d32);
2413 break;
2414 case 8:
cb21b4da
RH		 2415 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2416 da.memop | MO_ALIGN_4);
7705091c
RH		 2417 break;
2418 case 16:
cb21b4da
RH		 2419 d64 = tcg_temp_new_i64();
2420 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
7705091c 2421 tcg_gen_addi_tl(addr, addr, 8);
cb21b4da
RH		 2422 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2423 da.memop | MO_ALIGN_4);
2424 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
7705091c
RH		 2425 break;
2426 default:
2427 g_assert_not_reached();
2428 }
2429 break;
2430
ca5ce572
RH		 2431 case GET_ASI_BLOCK:
2432 /* Valid for lddfa on aligned registers only. */
2433 if (size == 8 && (rd & 7) == 0) {
14776ab5 2434 MemOp memop;
ca5ce572
RH		 2435 TCGv eight;
2436 int i;
2437
ca5ce572
RH		 2438 gen_address_mask(dc, addr);
2439
80883227
RH		 2440 /* The first operation checks required alignment. */
2441 memop = da.memop | MO_ALIGN_64;
00ab7e61 2442 eight = tcg_constant_tl(8);
ca5ce572
RH		 2443 for (i = 0; ; ++i) {
2444 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2445 da.mem_idx, memop);
ca5ce572
RH		 2446 if (i == 7) {
2447 break;
2448 }
2449 tcg_gen_add_tl(addr, addr, eight);
80883227 2450 memop = da.memop;
ca5ce572 2451 }
ca5ce572
RH		 2452 } else {
2453 gen_exception(dc, TT_ILL_INSN);
2454 }
2455 break;
2456
2457 case GET_ASI_SHORT:
2458 /* Valid for lddfa only. */
2459 if (size == 8) {
2460 gen_address_mask(dc, addr);
316b6783
RH		 2461 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2462 da.memop | MO_ALIGN);
ca5ce572
RH		 2463 } else {
2464 gen_exception(dc, TT_ILL_INSN);
2465 }
2466 break;
2467
7ec1e5ea
RH		 2468 default:
2469 {
00ab7e61 2470 TCGv_i32 r_asi = tcg_constant_i32(da.asi);
316b6783 2471 TCGv_i32 r_mop = tcg_constant_i32(da.memop | MO_ALIGN);
7ec1e5ea
RH		 2472
2473 save_state(dc);
f2fe396f
RH		 2474 /* According to the table in the UA2011 manual, the only
2475 other asis that are valid for ldfa/lddfa/ldqfa are
2476 the NO_FAULT asis. We still need a helper for these,
2477 but we can just use the integer asi helper for them. */
2478 switch (size) {
2479 case 4:
cb21b4da 2480 d64 = tcg_temp_new_i64();
ad75a51e 2481 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
cb21b4da
RH		 2482 d32 = gen_dest_fpr_F(dc);
2483 tcg_gen_extrl_i64_i32(d32, d64);
cb21b4da 2484 gen_store_fpr_F(dc, rd, d32);
f2fe396f
RH		 2485 break;
2486 case 8:
ad75a51e 2487 gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r_mop);
f2fe396f
RH		 2488 break;
2489 case 16:
cb21b4da 2490 d64 = tcg_temp_new_i64();
ad75a51e 2491 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
f2fe396f 2492 tcg_gen_addi_tl(addr, addr, 8);
ad75a51e 2493 gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r_mop);
cb21b4da 2494 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
f2fe396f
RH		 2495 break;
2496 default:
2497 g_assert_not_reached();
2498 }
7ec1e5ea
RH		 2499 }
2500 break;
2501 }
1a2fb1c0
BS		 2502}
2503
a76779ee
RH		 2504static void __attribute__((unused))
2505gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
1a2fb1c0 2506{
fc313c64 2507 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
7705091c 2508 TCGv_i32 d32;
1a2fb1c0 2509
7ec1e5ea
RH		 2510 switch (da.type) {
2511 case GET_ASI_EXCP:
2512 break;
7705091c
RH		 2513
2514 case GET_ASI_DIRECT:
2515 gen_address_mask(dc, addr);
2516 switch (size) {
2517 case 4:
2518 d32 = gen_load_fpr_F(dc, rd);
316b6783 2519 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
7705091c
RH		 2520 break;
2521 case 8:
cb21b4da
RH		 2522 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2523 da.memop | MO_ALIGN_4);
7705091c
RH		 2524 break;
2525 case 16:
cb21b4da
RH		 2526 /* Only 4-byte alignment required. However, it is legal for the
2527 cpu to signal the alignment fault, and the OS trap handler is
2528 required to fix it up. Requiring 16-byte alignment here avoids
2529 having to probe the second page before performing the first
2530 write. */
f939ffe5
RH		 2531 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2532 da.memop | MO_ALIGN_16);
7705091c
RH		 2533 tcg_gen_addi_tl(addr, addr, 8);
2534 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2535 break;
2536 default:
2537 g_assert_not_reached();
2538 }
2539 break;
2540
ca5ce572
RH		 2541 case GET_ASI_BLOCK:
2542 /* Valid for stdfa on aligned registers only. */
2543 if (size == 8 && (rd & 7) == 0) {
14776ab5 2544 MemOp memop;
ca5ce572
RH		 2545 TCGv eight;
2546 int i;
2547
ca5ce572
RH		 2548 gen_address_mask(dc, addr);
2549
80883227
RH		 2550 /* The first operation checks required alignment. */
2551 memop = da.memop | MO_ALIGN_64;
00ab7e61 2552 eight = tcg_constant_tl(8);
ca5ce572
RH		 2553 for (i = 0; ; ++i) {
2554 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2555 da.mem_idx, memop);
ca5ce572
RH		 2556 if (i == 7) {
2557 break;
2558 }
2559 tcg_gen_add_tl(addr, addr, eight);
80883227 2560 memop = da.memop;
ca5ce572 2561 }
ca5ce572
RH		 2562 } else {
2563 gen_exception(dc, TT_ILL_INSN);
2564 }
2565 break;
2566
2567 case GET_ASI_SHORT:
2568 /* Valid for stdfa only. */
2569 if (size == 8) {
2570 gen_address_mask(dc, addr);
316b6783
RH		 2571 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2572 da.memop | MO_ALIGN);
ca5ce572
RH		 2573 } else {
2574 gen_exception(dc, TT_ILL_INSN);
2575 }
2576 break;
2577
7ec1e5ea 2578 default:
f2fe396f
RH		 2579 /* According to the table in the UA2011 manual, the only
2580 other asis that are valid for ldfa/lddfa/ldqfa are
2581 the PST* asis, which aren't currently handled. */
2582 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2583 break;
2584 }
1a2fb1c0
BS		 2585}
2586
c03a0fd1 2587static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
1a2fb1c0 2588{
a76779ee
RH		 2589 TCGv hi = gen_dest_gpr(dc, rd);
2590 TCGv lo = gen_dest_gpr(dc, rd + 1);
1a2fb1c0 2591
c03a0fd1 2592 switch (da->type) {
7ec1e5ea 2593 case GET_ASI_EXCP:
e4dc0052
RH		 2594 return;
2595
2596 case GET_ASI_DTWINX:
a76779ee 2597 assert(TARGET_LONG_BITS == 64);
c03a0fd1 2598 tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
e4dc0052 2599 tcg_gen_addi_tl(addr, addr, 8);
c03a0fd1 2600 tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop);
7ec1e5ea 2601 break;
e4dc0052
RH		 2602
2603 case GET_ASI_DIRECT:
2604 {
2605 TCGv_i64 tmp = tcg_temp_new_i64();
2606
c03a0fd1 2607 tcg_gen_qemu_ld_i64(tmp, addr, da->mem_idx, da->memop | MO_ALIGN);
e4dc0052
RH		 2608
2609 /* Note that LE ldda acts as if each 32-bit register
2610 result is byte swapped. Having just performed one
2611 64-bit bswap, we need now to swap the writebacks. */
c03a0fd1 2612 if ((da->memop & MO_BSWAP) == MO_TE) {
a76779ee 2613 tcg_gen_extr_i64_tl(lo, hi, tmp);
e4dc0052 2614 } else {
a76779ee 2615 tcg_gen_extr_i64_tl(hi, lo, tmp);
e4dc0052 2616 }
e4dc0052
RH		 2617 }
2618 break;
2619
7ec1e5ea 2620 default:
918d9a2c
RH		 2621 /* ??? In theory we've handled all of the ASIs that are valid
2622 for ldda, and this should raise DAE_invalid_asi. However,
2623 real hardware allows others. This can be seen with e.g.
2624 FreeBSD 10.3 wrt ASI_IC_TAG. */
7ec1e5ea 2625 {
c03a0fd1
RH		 2626 TCGv_i32 r_asi = tcg_constant_i32(da->asi);
2627 TCGv_i32 r_mop = tcg_constant_i32(da->memop);
918d9a2c 2628 TCGv_i64 tmp = tcg_temp_new_i64();
7ec1e5ea
RH		 2629
2630 save_state(dc);
ad75a51e 2631 gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop);
3f4288eb 2632
918d9a2c 2633 /* See above. */
c03a0fd1 2634 if ((da->memop & MO_BSWAP) == MO_TE) {
a76779ee 2635 tcg_gen_extr_i64_tl(lo, hi, tmp);
918d9a2c 2636 } else {
a76779ee 2637 tcg_gen_extr_i64_tl(hi, lo, tmp);
918d9a2c 2638 }
7ec1e5ea
RH		 2639 }
2640 break;
2641 }
e4dc0052
RH		 2642
2643 gen_store_gpr(dc, rd, hi);
2644 gen_store_gpr(dc, rd + 1, lo);
0425bee5
BS		 2645}
2646
a76779ee 2647static void __attribute__((unused))
c03a0fd1 2648gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
0425bee5 2649{
fc313c64 2650 DisasASI da = get_asi(dc, insn, MO_TEUQ);
c03a0fd1
RH		 2651
2652 gen_address_mask(dc, addr);
2653 gen_ldda_asi0(dc, &da, addr, rd);
2654}
2655
2656static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
2657{
2658 TCGv hi = gen_load_gpr(dc, rd);
c7785e16 2659 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2660
c03a0fd1 2661 switch (da->type) {
7ec1e5ea
RH		 2662 case GET_ASI_EXCP:
2663 break;
e4dc0052
RH		 2664
2665 case GET_ASI_DTWINX:
a76779ee 2666 assert(TARGET_LONG_BITS == 64);
c03a0fd1 2667 tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
e4dc0052 2668 tcg_gen_addi_tl(addr, addr, 8);
c03a0fd1 2669 tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop);
e4dc0052
RH		 2670 break;
2671
2672 case GET_ASI_DIRECT:
2673 {
2674 TCGv_i64 t64 = tcg_temp_new_i64();
2675
2676 /* Note that LE stda acts as if each 32-bit register result is
2677 byte swapped. We will perform one 64-bit LE store, so now
2678 we must swap the order of the construction. */
c03a0fd1 2679 if ((da->memop & MO_BSWAP) == MO_TE) {
a76779ee 2680 tcg_gen_concat_tl_i64(t64, lo, hi);
e4dc0052 2681 } else {
a76779ee 2682 tcg_gen_concat_tl_i64(t64, hi, lo);
e4dc0052 2683 }
c03a0fd1 2684 tcg_gen_qemu_st_i64(t64, addr, da->mem_idx, da->memop | MO_ALIGN);
e4dc0052
RH		 2685 }
2686 break;
2687
a76779ee
RH		 2688 case GET_ASI_BFILL:
2689 assert(TARGET_LONG_BITS == 32);
2690 /* Store 32 bytes of T64 to ADDR. */
2691 /* ??? The original qemu code suggests 8-byte alignment, dropping
2692 the low bits, but the only place I can see this used is in the
2693 Linux kernel with 32 byte alignment, which would make more sense
2694 as a cacheline-style operation. */
2695 {
2696 TCGv_i64 t64 = tcg_temp_new_i64();
2697 TCGv d_addr = tcg_temp_new();
2698 TCGv eight = tcg_constant_tl(8);
2699 int i;
2700
2701 tcg_gen_concat_tl_i64(t64, lo, hi);
2702 tcg_gen_andi_tl(d_addr, addr, -8);
2703 for (i = 0; i < 32; i += 8) {
c03a0fd1 2704 tcg_gen_qemu_st_i64(t64, d_addr, da->mem_idx, da->memop);
a76779ee
RH		 2705 tcg_gen_add_tl(d_addr, d_addr, eight);
2706 }
2707 }
2708 break;
2709
7ec1e5ea 2710 default:
918d9a2c
RH		 2711 /* ??? In theory we've handled all of the ASIs that are valid
2712 for stda, and this should raise DAE_invalid_asi. */
7ec1e5ea 2713 {
c03a0fd1
RH		 2714 TCGv_i32 r_asi = tcg_constant_i32(da->asi);
2715 TCGv_i32 r_mop = tcg_constant_i32(da->memop);
918d9a2c 2716 TCGv_i64 t64 = tcg_temp_new_i64();
7ec1e5ea 2717
918d9a2c 2718 /* See above. */
c03a0fd1 2719 if ((da->memop & MO_BSWAP) == MO_TE) {
a76779ee 2720 tcg_gen_concat_tl_i64(t64, lo, hi);
918d9a2c 2721 } else {
a76779ee 2722 tcg_gen_concat_tl_i64(t64, hi, lo);
918d9a2c 2723 }
7ec1e5ea 2724
918d9a2c 2725 save_state(dc);
ad75a51e 2726 gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
7ec1e5ea
RH		 2727 }
2728 break;
2729 }
1a2fb1c0
BS		 2730}
2731
a76779ee 2732static void __attribute__((unused))
c03a0fd1 2733gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
1a2fb1c0 2734{
fc313c64 2735 DisasASI da = get_asi(dc, insn, MO_TEUQ);
1a2fb1c0 2736
c03a0fd1
RH		 2737 gen_address_mask(dc, addr);
2738 gen_stda_asi0(dc, &da, addr, rd);
1a2fb1c0
BS		 2739}
2740
9d1d4e34 2741static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2742{
9d1d4e34
RH		 2743 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2744 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2745}
2746
8194f35a 2747#ifdef TARGET_SPARC64
7e480893
RH		 2748static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2749{
2750 TCGv_i32 c32, zero, dst, s1, s2;
2751
2752 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2753 or fold the comparison down to 32 bits and use movcond_i32. Choose
2754 the later. */
2755 c32 = tcg_temp_new_i32();
2756 if (cmp->is_bool) {
ecc7b3aa 2757 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2758 } else {
2759 TCGv_i64 c64 = tcg_temp_new_i64();
2760 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2761 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2762 }
2763
2764 s1 = gen_load_fpr_F(dc, rs);
2765 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2766 dst = gen_dest_fpr_F(dc);
00ab7e61 2767 zero = tcg_constant_i32(0);
7e480893
RH		 2768
2769 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2770
7e480893
RH		 2771 gen_store_fpr_F(dc, rd, dst);
2772}
2773
2774static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2775{
3886b8a3 2776 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2777 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2778 gen_load_fpr_D(dc, rs),
2779 gen_load_fpr_D(dc, rd));
2780 gen_store_fpr_D(dc, rd, dst);
2781}
2782
2783static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2784{
2785 int qd = QFPREG(rd);
2786 int qs = QFPREG(rs);
2787
2788 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2789 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2790 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2791 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2792
f9c816c0 2793 gen_update_fprs_dirty(dc, qd);
7e480893
RH		 2794}
2795
5d617bfb 2796static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
8194f35a 2797{
b551ec04 2798 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2799
2800 /* load env->tl into r_tl */
ad75a51e 2801 tcg_gen_ld_i32(r_tl, tcg_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2802
2803 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2804 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2805
2806 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2807 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
ad75a51e 2808 tcg_gen_addi_ptr(r_tsptr, tcg_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2809
2810 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2811 {
2812 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2813 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2814 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
b551ec04 2815 }
8194f35a 2816}
6c073553
RH		 2817
2818static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2819 int width, bool cc, bool left)
2820{
905a83de 2821 TCGv lo1, lo2;
6c073553
RH		 2822 uint64_t amask, tabl, tabr;
2823 int shift, imask, omask;
2824
2825 if (cc) {
2826 tcg_gen_mov_tl(cpu_cc_src, s1);
2827 tcg_gen_mov_tl(cpu_cc_src2, s2);
2828 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2829 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2830 dc->cc_op = CC_OP_SUB;
2831 }
2832
2833 /* Theory of operation: there are two tables, left and right (not to
2834 be confused with the left and right versions of the opcode). These
2835 are indexed by the low 3 bits of the inputs. To make things "easy",
2836 these tables are loaded into two constants, TABL and TABR below.
2837 The operation index = (input & imask) << shift calculates the index
2838 into the constant, while val = (table >> index) & omask calculates
2839 the value we're looking for. */
2840 switch (width) {
2841 case 8:
2842 imask = 0x7;
2843 shift = 3;
2844 omask = 0xff;
2845 if (left) {
2846 tabl = 0x80c0e0f0f8fcfeffULL;
2847 tabr = 0xff7f3f1f0f070301ULL;
2848 } else {
2849 tabl = 0x0103070f1f3f7fffULL;
2850 tabr = 0xfffefcf8f0e0c080ULL;
2851 }
2852 break;
2853 case 16:
2854 imask = 0x6;
2855 shift = 1;
2856 omask = 0xf;
2857 if (left) {
2858 tabl = 0x8cef;
2859 tabr = 0xf731;
2860 } else {
2861 tabl = 0x137f;
2862 tabr = 0xfec8;
2863 }
2864 break;
2865 case 32:
2866 imask = 0x4;
2867 shift = 0;
2868 omask = 0x3;
2869 if (left) {
2870 tabl = (2 << 2) | 3;
2871 tabr = (3 << 2) | 1;
2872 } else {
2873 tabl = (1 << 2) | 3;
2874 tabr = (3 << 2) | 2;
2875 }
2876 break;
2877 default:
2878 abort();
2879 }
2880
2881 lo1 = tcg_temp_new();
2882 lo2 = tcg_temp_new();
2883 tcg_gen_andi_tl(lo1, s1, imask);
2884 tcg_gen_andi_tl(lo2, s2, imask);
2885 tcg_gen_shli_tl(lo1, lo1, shift);
2886 tcg_gen_shli_tl(lo2, lo2, shift);
2887
905a83de
RH		 2888 tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
2889 tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
e3ebbade 2890 tcg_gen_andi_tl(lo1, lo1, omask);
6c073553
RH		 2891 tcg_gen_andi_tl(lo2, lo2, omask);
2892
2893 amask = -8;
2894 if (AM_CHECK(dc)) {
2895 amask &= 0xffffffffULL;
2896 }
2897 tcg_gen_andi_tl(s1, s1, amask);
2898 tcg_gen_andi_tl(s2, s2, amask);
2899
e3ebbade
RH		 2900 /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
2901 tcg_gen_and_tl(lo2, lo2, lo1);
2902 tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2);
6c073553 2903}
add545ab
RH		 2904
2905static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2906{
2907 TCGv tmp = tcg_temp_new();
2908
2909 tcg_gen_add_tl(tmp, s1, s2);
2910 tcg_gen_andi_tl(dst, tmp, -8);
2911 if (left) {
2912 tcg_gen_neg_tl(tmp, tmp);
2913 }
2914 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
add545ab 2915}
50c796f9
RH		 2916
2917static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2918{
2919 TCGv t1, t2, shift;
2920
2921 t1 = tcg_temp_new();
2922 t2 = tcg_temp_new();
2923 shift = tcg_temp_new();
2924
2925 tcg_gen_andi_tl(shift, gsr, 7);
2926 tcg_gen_shli_tl(shift, shift, 3);
2927 tcg_gen_shl_tl(t1, s1, shift);
2928
2929 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2930 shift of (up to 63) followed by a constant shift of 1. */
2931 tcg_gen_xori_tl(shift, shift, 63);
2932 tcg_gen_shr_tl(t2, s2, shift);
2933 tcg_gen_shri_tl(t2, t2, 1);
2934
2935 tcg_gen_or_tl(dst, t1, t2);
50c796f9 2936}
8194f35a
IK		 2937#endif
2938
878cc677
RH		 2939/* Include the auto-generated decoder. */
2940#include "decode-insns.c.inc"
2941
2942#define TRANS(NAME, AVAIL, FUNC, ...) \
2943 static bool trans_##NAME(DisasContext *dc, arg_##NAME *a) \
2944 { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); }
2945
2946#define avail_ALL(C) true
2947#ifdef TARGET_SPARC64
2948# define avail_32(C) false
af25071c 2949# define avail_ASR17(C) false
c2636853 2950# define avail_DIV(C) true
b5372650 2951# define avail_MUL(C) true
0faef01b 2952# define avail_POWERDOWN(C) false
878cc677 2953# define avail_64(C) true
5d617bfb 2954# define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
af25071c 2955# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
878cc677
RH		 2956#else
2957# define avail_32(C) true
af25071c 2958# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
c2636853 2959# define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV)
b5372650 2960# define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
0faef01b 2961# define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN)
878cc677 2962# define avail_64(C) false
5d617bfb 2963# define avail_GL(C) false
af25071c 2964# define avail_HYPV(C) false
878cc677
RH		 2965#endif
2966
2967/* Default case for non jump instructions. */
2968static bool advance_pc(DisasContext *dc)
2969{
2970 if (dc->npc & 3) {
2971 switch (dc->npc) {
2972 case DYNAMIC_PC:
2973 case DYNAMIC_PC_LOOKUP:
2974 dc->pc = dc->npc;
2975 gen_op_next_insn();
2976 break;
2977 case JUMP_PC:
2978 /* we can do a static jump */
2979 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
2980 dc->base.is_jmp = DISAS_NORETURN;
2981 break;
2982 default:
2983 g_assert_not_reached();
2984 }
2985 } else {
2986 dc->pc = dc->npc;
2987 dc->npc = dc->npc + 4;
2988 }
2989 return true;
2990}
2991
6d2a0768
RH		 2992/*
2993 * Major opcodes 00 and 01 -- branches, call, and sethi
2994 */
2995
276567aa
RH		 2996static bool advance_jump_uncond_never(DisasContext *dc, bool annul)
2997{
2998 if (annul) {
2999 dc->pc = dc->npc + 4;
3000 dc->npc = dc->pc + 4;
3001 } else {
3002 dc->pc = dc->npc;
3003 dc->npc = dc->pc + 4;
3004 }
3005 return true;
3006}
3007
3008static bool advance_jump_uncond_always(DisasContext *dc, bool annul,
3009 target_ulong dest)
3010{
3011 if (annul) {
3012 dc->pc = dest;
3013 dc->npc = dest + 4;
3014 } else {
3015 dc->pc = dc->npc;
3016 dc->npc = dest;
3017 tcg_gen_mov_tl(cpu_pc, cpu_npc);
3018 }
3019 return true;
3020}
3021
9d4e2bc7
RH		 3022static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp,
3023 bool annul, target_ulong dest)
276567aa 3024{
6b3e4cc6
RH		 3025 target_ulong npc = dc->npc;
3026
276567aa 3027 if (annul) {
6b3e4cc6
RH		 3028 TCGLabel *l1 = gen_new_label();
3029
9d4e2bc7 3030 tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1);
6b3e4cc6
RH		 3031 gen_goto_tb(dc, 0, npc, dest);
3032 gen_set_label(l1);
3033 gen_goto_tb(dc, 1, npc + 4, npc + 8);
3034
3035 dc->base.is_jmp = DISAS_NORETURN;
276567aa 3036 } else {
6b3e4cc6
RH		 3037 if (npc & 3) {
3038 switch (npc) {
3039 case DYNAMIC_PC:
3040 case DYNAMIC_PC_LOOKUP:
3041 tcg_gen_mov_tl(cpu_pc, cpu_npc);
3042 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
9d4e2bc7
RH		 3043 tcg_gen_movcond_tl(cmp->cond, cpu_npc,
3044 cmp->c1, cmp->c2,
6b3e4cc6
RH		 3045 tcg_constant_tl(dest), cpu_npc);
3046 dc->pc = npc;
3047 break;
3048 default:
3049 g_assert_not_reached();
3050 }
3051 } else {
3052 dc->pc = npc;
3053 dc->jump_pc[0] = dest;
3054 dc->jump_pc[1] = npc + 4;
3055 dc->npc = JUMP_PC;
9d4e2bc7
RH		 3056 if (cmp->is_bool) {
3057 tcg_gen_mov_tl(cpu_cond, cmp->c1);
3058 } else {
3059 tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
3060 }
6b3e4cc6 3061 }
276567aa
RH		 3062 }
3063 return true;
3064}
3065
af25071c
RH		 3066static bool raise_priv(DisasContext *dc)
3067{
3068 gen_exception(dc, TT_PRIV_INSN);
3069 return true;
3070}
3071
276567aa
RH		 3072static bool do_bpcc(DisasContext *dc, arg_bcc *a)
3073{
3074 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
1ea9c62a 3075 DisasCompare cmp;
276567aa
RH		 3076
3077 switch (a->cond) {
3078 case 0x0:
3079 return advance_jump_uncond_never(dc, a->a);
3080 case 0x8:
3081 return advance_jump_uncond_always(dc, a->a, target);
3082 default:
3083 flush_cond(dc);
1ea9c62a
RH		 3084
3085 gen_compare(&cmp, a->cc, a->cond, dc);
9d4e2bc7 3086 return advance_jump_cond(dc, &cmp, a->a, target);
276567aa
RH		 3087 }
3088}
3089
3090TRANS(Bicc, ALL, do_bpcc, a)
3091TRANS(BPcc, 64, do_bpcc, a)
3092
45196ea4
RH		 3093static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
3094{
3095 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
d5471936 3096 DisasCompare cmp;
45196ea4
RH		 3097
3098 if (gen_trap_ifnofpu(dc)) {
3099 return true;
3100 }
3101 switch (a->cond) {
3102 case 0x0:
3103 return advance_jump_uncond_never(dc, a->a);
3104 case 0x8:
3105 return advance_jump_uncond_always(dc, a->a, target);
3106 default:
3107 flush_cond(dc);
d5471936
RH		 3108
3109 gen_fcompare(&cmp, a->cc, a->cond);
9d4e2bc7 3110 return advance_jump_cond(dc, &cmp, a->a, target);
45196ea4
RH		 3111 }
3112}
3113
3114TRANS(FBPfcc, 64, do_fbpfcc, a)
3115TRANS(FBfcc, ALL, do_fbpfcc, a)
3116
ab9ffe98
RH		 3117static bool trans_BPr(DisasContext *dc, arg_BPr *a)
3118{
3119 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
3120 DisasCompare cmp;
3121
3122 if (!avail_64(dc)) {
3123 return false;
3124 }
3125 if (gen_tcg_cond_reg[a->cond] == TCG_COND_NEVER) {
3126 return false;
3127 }
3128
3129 flush_cond(dc);
3130 gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
9d4e2bc7 3131 return advance_jump_cond(dc, &cmp, a->a, target);
ab9ffe98
RH		 3132}
3133
23ada1b1
RH		 3134static bool trans_CALL(DisasContext *dc, arg_CALL *a)
3135{
3136 target_long target = address_mask_i(dc, dc->pc + a->i * 4);
3137
3138 gen_store_gpr(dc, 15, tcg_constant_tl(dc->pc));
3139 gen_mov_pc_npc(dc);
3140 dc->npc = target;
3141 return true;
3142}
3143
45196ea4
RH		 3144static bool trans_NCP(DisasContext *dc, arg_NCP *a)
3145{
3146 /*
3147 * For sparc32, always generate the no-coprocessor exception.
3148 * For sparc64, always generate illegal instruction.
3149 */
3150#ifdef TARGET_SPARC64
3151 return false;
3152#else
3153 gen_exception(dc, TT_NCP_INSN);
3154 return true;
3155#endif
3156}
3157
6d2a0768
RH		 3158static bool trans_SETHI(DisasContext *dc, arg_SETHI *a)
3159{
3160 /* Special-case %g0 because that's the canonical nop. */
3161 if (a->rd) {
3162 gen_store_gpr(dc, a->rd, tcg_constant_tl((uint32_t)a->i << 10));
3163 }
3164 return advance_pc(dc);
3165}
3166
0faef01b
RH		 3167/*
3168 * Major Opcode 10 -- integer, floating-point, vis, and system insns.
3169 */
3170
30376636
RH		 3171static bool do_tcc(DisasContext *dc, int cond, int cc,
3172 int rs1, bool imm, int rs2_or_imm)
3173{
3174 int mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3175 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3176 DisasCompare cmp;
3177 TCGLabel *lab;
3178 TCGv_i32 trap;
3179
3180 /* Trap never. */
3181 if (cond == 0) {
3182 return advance_pc(dc);
3183 }
3184
3185 /*
3186 * Immediate traps are the most common case. Since this value is
3187 * live across the branch, it really pays to evaluate the constant.
3188 */
3189 if (rs1 == 0 && (imm || rs2_or_imm == 0)) {
3190 trap = tcg_constant_i32((rs2_or_imm & mask) + TT_TRAP);
3191 } else {
3192 trap = tcg_temp_new_i32();
3193 tcg_gen_trunc_tl_i32(trap, gen_load_gpr(dc, rs1));
3194 if (imm) {
3195 tcg_gen_addi_i32(trap, trap, rs2_or_imm);
3196 } else {
3197 TCGv_i32 t2 = tcg_temp_new_i32();
3198 tcg_gen_trunc_tl_i32(t2, gen_load_gpr(dc, rs2_or_imm));
3199 tcg_gen_add_i32(trap, trap, t2);
3200 }
3201 tcg_gen_andi_i32(trap, trap, mask);
3202 tcg_gen_addi_i32(trap, trap, TT_TRAP);
3203 }
3204
3205 /* Trap always. */
3206 if (cond == 8) {
3207 save_state(dc);
3208 gen_helper_raise_exception(tcg_env, trap);
3209 dc->base.is_jmp = DISAS_NORETURN;
3210 return true;
3211 }
3212
3213 /* Conditional trap. */
3214 flush_cond(dc);
3215 lab = delay_exceptionv(dc, trap);
3216 gen_compare(&cmp, cc, cond, dc);
3217 tcg_gen_brcond_tl(cmp.cond, cmp.c1, cmp.c2, lab);
3218
3219 return advance_pc(dc);
3220}
3221
3222static bool trans_Tcc_r(DisasContext *dc, arg_Tcc_r *a)
3223{
3224 if (avail_32(dc) && a->cc) {
3225 return false;
3226 }
3227 return do_tcc(dc, a->cond, a->cc, a->rs1, false, a->rs2);
3228}
3229
3230static bool trans_Tcc_i_v7(DisasContext *dc, arg_Tcc_i_v7 *a)
3231{
3232 if (avail_64(dc)) {
3233 return false;
3234 }
3235 return do_tcc(dc, a->cond, 0, a->rs1, true, a->i);
3236}
3237
3238static bool trans_Tcc_i_v9(DisasContext *dc, arg_Tcc_i_v9 *a)
3239{
3240 if (avail_32(dc)) {
3241 return false;
3242 }
3243 return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i);
3244}
3245
af25071c
RH		 3246static bool trans_STBAR(DisasContext *dc, arg_STBAR *a)
3247{
3248 tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC);
3249 return advance_pc(dc);
3250}
3251
3252static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a)
3253{
3254 if (avail_32(dc)) {
3255 return false;
3256 }
3257 if (a->mmask) {
3258 /* Note TCG_MO_* was modeled on sparc64, so mmask matches. */
3259 tcg_gen_mb(a->mmask | TCG_BAR_SC);
3260 }
3261 if (a->cmask) {
3262 /* For #Sync, etc, end the TB to recognize interrupts. */
3263 dc->base.is_jmp = DISAS_EXIT;
3264 }
3265 return advance_pc(dc);
3266}
3267
3268static bool do_rd_special(DisasContext *dc, bool priv, int rd,
3269 TCGv (*func)(DisasContext *, TCGv))
3270{
3271 if (!priv) {
3272 return raise_priv(dc);
3273 }
3274 gen_store_gpr(dc, rd, func(dc, gen_dest_gpr(dc, rd)));
3275 return advance_pc(dc);
3276}
3277
3278static TCGv do_rdy(DisasContext *dc, TCGv dst)
3279{
3280 return cpu_y;
3281}
3282
3283static bool trans_RDY(DisasContext *dc, arg_RDY *a)
3284{
3285 /*
3286 * TODO: Need a feature bit for sparcv8. In the meantime, treat all
3287 * 32-bit cpus like sparcv7, which ignores the rs1 field.
3288 * This matches after all other ASR, so Leon3 Asr17 is handled first.
3289 */
3290 if (avail_64(dc) && a->rs1 != 0) {
3291 return false;
3292 }
3293 return do_rd_special(dc, true, a->rd, do_rdy);
3294}
3295
3296static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
3297{
3298 uint32_t val;
3299
3300 /*
3301 * TODO: There are many more fields to be filled,
3302 * some of which are writable.
3303 */
3304 val = dc->def->nwindows - 1; /* [4:0] NWIN */
3305 val |= 1 << 8; /* [8] V8 */
3306
3307 return tcg_constant_tl(val);
3308}
3309
3310TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
3311
3312static TCGv do_rdccr(DisasContext *dc, TCGv dst)
3313{
3314 update_psr(dc);
3315 gen_helper_rdccr(dst, tcg_env);
3316 return dst;
3317}
3318
3319TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr)
3320
3321static TCGv do_rdasi(DisasContext *dc, TCGv dst)
3322{
3323#ifdef TARGET_SPARC64
3324 return tcg_constant_tl(dc->asi);
3325#else
3326 qemu_build_not_reached();
3327#endif
3328}
3329
3330TRANS(RDASI, 64, do_rd_special, true, a->rd, do_rdasi)
3331
3332static TCGv do_rdtick(DisasContext *dc, TCGv dst)
3333{
3334 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3335
3336 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
3337 if (translator_io_start(&dc->base)) {
3338 dc->base.is_jmp = DISAS_EXIT;
3339 }
3340 gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
3341 tcg_constant_i32(dc->mem_idx));
3342 return dst;
3343}
3344
3345/* TODO: non-priv access only allowed when enabled. */
3346TRANS(RDTICK, 64, do_rd_special, true, a->rd, do_rdtick)
3347
3348static TCGv do_rdpc(DisasContext *dc, TCGv dst)
3349{
3350 return tcg_constant_tl(address_mask_i(dc, dc->pc));
3351}
3352
3353TRANS(RDPC, 64, do_rd_special, true, a->rd, do_rdpc)
3354
3355static TCGv do_rdfprs(DisasContext *dc, TCGv dst)
3356{
3357 tcg_gen_ext_i32_tl(dst, cpu_fprs);
3358 return dst;
3359}
3360
3361TRANS(RDFPRS, 64, do_rd_special, true, a->rd, do_rdfprs)
3362
3363static TCGv do_rdgsr(DisasContext *dc, TCGv dst)
3364{
3365 gen_trap_ifnofpu(dc);
3366 return cpu_gsr;
3367}
3368
3369TRANS(RDGSR, 64, do_rd_special, true, a->rd, do_rdgsr)
3370
3371static TCGv do_rdsoftint(DisasContext *dc, TCGv dst)
3372{
3373 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(softint));
3374 return dst;
3375}
3376
3377TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a->rd, do_rdsoftint)
3378
3379static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst)
3380{
577efa45
RH		 3381 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(tick_cmpr));
3382 return dst;
af25071c
RH		 3383}
3384
3385/* TODO: non-priv access only allowed when enabled. */
3386TRANS(RDTICK_CMPR, 64, do_rd_special, true, a->rd, do_rdtick_cmpr)
3387
3388static TCGv do_rdstick(DisasContext *dc, TCGv dst)
3389{
3390 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3391
3392 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick));
3393 if (translator_io_start(&dc->base)) {
3394 dc->base.is_jmp = DISAS_EXIT;
3395 }
3396 gen_helper_tick_get_count(dst, tcg_env, r_tickptr,
3397 tcg_constant_i32(dc->mem_idx));
3398 return dst;
3399}
3400
3401/* TODO: non-priv access only allowed when enabled. */
3402TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rdstick)
3403
3404static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst)
3405{
577efa45
RH		 3406 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(stick_cmpr));
3407 return dst;
af25071c
RH		 3408}
3409
3410/* TODO: supervisor access only allowed when enabled by hypervisor. */
3411TRANS(RDSTICK_CMPR, 64, do_rd_special, supervisor(dc), a->rd, do_rdstick_cmpr)
3412
3413/*
3414 * UltraSPARC-T1 Strand status.
3415 * HYPV check maybe not enough, UA2005 & UA2007 describe
3416 * this ASR as impl. dep
3417 */
3418static TCGv do_rdstrand_status(DisasContext *dc, TCGv dst)
3419{
3420 return tcg_constant_tl(1);
3421}
3422
3423TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status)
3424
668bb9b7
RH		 3425static TCGv do_rdpsr(DisasContext *dc, TCGv dst)
3426{
3427 update_psr(dc);
3428 gen_helper_rdpsr(dst, tcg_env);
3429 return dst;
3430}
3431
3432TRANS(RDPSR, 32, do_rd_special, supervisor(dc), a->rd, do_rdpsr)
3433
3434static TCGv do_rdhpstate(DisasContext *dc, TCGv dst)
3435{
3436 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hpstate));
3437 return dst;
3438}
3439
3440TRANS(RDHPR_hpstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhpstate)
3441
3442static TCGv do_rdhtstate(DisasContext *dc, TCGv dst)
3443{
3444 TCGv_i32 tl = tcg_temp_new_i32();
3445 TCGv_ptr tp = tcg_temp_new_ptr();
3446
3447 tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl));
3448 tcg_gen_andi_i32(tl, tl, MAXTL_MASK);
3449 tcg_gen_shli_i32(tl, tl, 3);
3450 tcg_gen_ext_i32_ptr(tp, tl);
3451 tcg_gen_add_ptr(tp, tp, tcg_env);
3452
3453 tcg_gen_ld_tl(dst, tp, env64_field_offsetof(htstate));
3454 return dst;
3455}
3456
3457TRANS(RDHPR_htstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtstate)
3458
3459static TCGv do_rdhintp(DisasContext *dc, TCGv dst)
3460{
2da789de
RH		 3461 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hintp));
3462 return dst;
668bb9b7
RH		 3463}
3464
3465TRANS(RDHPR_hintp, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhintp)
3466
3467static TCGv do_rdhtba(DisasContext *dc, TCGv dst)
3468{
2da789de
RH		 3469 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(htba));
3470 return dst;
668bb9b7
RH		 3471}
3472
3473TRANS(RDHPR_htba, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtba)
3474
3475static TCGv do_rdhver(DisasContext *dc, TCGv dst)
3476{
2da789de
RH		 3477 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hver));
3478 return dst;
668bb9b7
RH		 3479}
3480
3481TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhver)
3482
3483static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst)
3484{
577efa45
RH		 3485 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(hstick_cmpr));
3486 return dst;
668bb9b7
RH		 3487}
3488
3489TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd,
3490 do_rdhstick_cmpr)
3491
5d617bfb
RH		 3492static TCGv do_rdwim(DisasContext *dc, TCGv dst)
3493{
cd6269f7
RH		 3494 tcg_gen_ld_tl(dst, tcg_env, env32_field_offsetof(wim));
3495 return dst;
5d617bfb
RH		 3496}
3497
3498TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim)
3499
3500static TCGv do_rdtpc(DisasContext *dc, TCGv dst)
3501{
3502#ifdef TARGET_SPARC64
3503 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3504
3505 gen_load_trap_state_at_tl(r_tsptr);
3506 tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tpc));
3507 return dst;
3508#else
3509 qemu_build_not_reached();
3510#endif
3511}
3512
3513TRANS(RDPR_tpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtpc)
3514
3515static TCGv do_rdtnpc(DisasContext *dc, TCGv dst)
3516{
3517#ifdef TARGET_SPARC64
3518 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3519
3520 gen_load_trap_state_at_tl(r_tsptr);
3521 tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tnpc));
3522 return dst;
3523#else
3524 qemu_build_not_reached();
3525#endif
3526}
3527
3528TRANS(RDPR_tnpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtnpc)
3529
3530static TCGv do_rdtstate(DisasContext *dc, TCGv dst)
3531{
3532#ifdef TARGET_SPARC64
3533 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3534
3535 gen_load_trap_state_at_tl(r_tsptr);
3536 tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tstate));
3537 return dst;
3538#else
3539 qemu_build_not_reached();
3540#endif
3541}
3542
3543TRANS(RDPR_tstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdtstate)
3544
3545static TCGv do_rdtt(DisasContext *dc, TCGv dst)
3546{
3547#ifdef TARGET_SPARC64
3548 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3549
3550 gen_load_trap_state_at_tl(r_tsptr);
3551 tcg_gen_ld32s_tl(dst, r_tsptr, offsetof(trap_state, tt));
3552 return dst;
3553#else
3554 qemu_build_not_reached();
3555#endif
3556}
3557
3558TRANS(RDPR_tt, 64, do_rd_special, supervisor(dc), a->rd, do_rdtt)
3559TRANS(RDPR_tick, 64, do_rd_special, supervisor(dc), a->rd, do_rdtick)
3560
3561static TCGv do_rdtba(DisasContext *dc, TCGv dst)
3562{
3563 return cpu_tbr;
3564}
3565
e8325dc0 3566TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba)
5d617bfb
RH		 3567TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba)
3568
3569static TCGv do_rdpstate(DisasContext *dc, TCGv dst)
3570{
3571 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(pstate));
3572 return dst;
3573}
3574
3575TRANS(RDPR_pstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdpstate)
3576
3577static TCGv do_rdtl(DisasContext *dc, TCGv dst)
3578{
3579 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(tl));
3580 return dst;
3581}
3582
3583TRANS(RDPR_tl, 64, do_rd_special, supervisor(dc), a->rd, do_rdtl)
3584
3585static TCGv do_rdpil(DisasContext *dc, TCGv dst)
3586{
3587 tcg_gen_ld32s_tl(dst, tcg_env, env_field_offsetof(psrpil));
3588 return dst;
3589}
3590
3591TRANS(RDPR_pil, 64, do_rd_special, supervisor(dc), a->rd, do_rdpil)
3592
3593static TCGv do_rdcwp(DisasContext *dc, TCGv dst)
3594{
3595 gen_helper_rdcwp(dst, tcg_env);
3596 return dst;
3597}
3598
3599TRANS(RDPR_cwp, 64, do_rd_special, supervisor(dc), a->rd, do_rdcwp)
3600
3601static TCGv do_rdcansave(DisasContext *dc, TCGv dst)
3602{
3603 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cansave));
3604 return dst;
3605}
3606
3607TRANS(RDPR_cansave, 64, do_rd_special, supervisor(dc), a->rd, do_rdcansave)
3608
3609static TCGv do_rdcanrestore(DisasContext *dc, TCGv dst)
3610{
3611 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(canrestore));
3612 return dst;
3613}
3614
3615TRANS(RDPR_canrestore, 64, do_rd_special, supervisor(dc), a->rd,
3616 do_rdcanrestore)
3617
3618static TCGv do_rdcleanwin(DisasContext *dc, TCGv dst)
3619{
3620 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(cleanwin));
3621 return dst;
3622}
3623
3624TRANS(RDPR_cleanwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdcleanwin)
3625
3626static TCGv do_rdotherwin(DisasContext *dc, TCGv dst)
3627{
3628 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(otherwin));
3629 return dst;
3630}
3631
3632TRANS(RDPR_otherwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdotherwin)
3633
3634static TCGv do_rdwstate(DisasContext *dc, TCGv dst)
3635{
3636 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(wstate));
3637 return dst;
3638}
3639
3640TRANS(RDPR_wstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdwstate)
3641
3642static TCGv do_rdgl(DisasContext *dc, TCGv dst)
3643{
3644 tcg_gen_ld32s_tl(dst, tcg_env, env64_field_offsetof(gl));
3645 return dst;
3646}
3647
3648TRANS(RDPR_gl, GL, do_rd_special, supervisor(dc), a->rd, do_rdgl)
3649
3650/* UA2005 strand status */
3651static TCGv do_rdssr(DisasContext *dc, TCGv dst)
3652{
2da789de
RH		 3653 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(ssr));
3654 return dst;
5d617bfb
RH		 3655}
3656
3657TRANS(RDPR_strand_status, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdssr)
3658
3659static TCGv do_rdver(DisasContext *dc, TCGv dst)
3660{
2da789de
RH		 3661 tcg_gen_ld_tl(dst, tcg_env, env64_field_offsetof(version));
3662 return dst;
5d617bfb
RH		 3663}
3664
3665TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver)
3666
e8325dc0
RH		 3667static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a)
3668{
3669 if (avail_64(dc)) {
3670 gen_helper_flushw(tcg_env);
3671 return advance_pc(dc);
3672 }
3673 return false;
3674}
3675
0faef01b
RH		 3676static bool do_wr_special(DisasContext *dc, arg_r_r_ri *a, bool priv,
3677 void (*func)(DisasContext *, TCGv))
3678{
3679 TCGv src;
3680
3681 /* For simplicity, we under-decoded the rs2 form. */
3682 if (!a->imm && (a->rs2_or_imm & ~0x1f)) {
3683 return false;
3684 }
3685 if (!priv) {
3686 return raise_priv(dc);
3687 }
3688
3689 if (a->rs1 == 0 && (a->imm || a->rs2_or_imm == 0)) {
3690 src = tcg_constant_tl(a->rs2_or_imm);
3691 } else {
3692 TCGv src1 = gen_load_gpr(dc, a->rs1);
3693 if (a->rs2_or_imm == 0) {
3694 src = src1;
3695 } else {
3696 src = tcg_temp_new();
3697 if (a->imm) {
3698 tcg_gen_xori_tl(src, src1, a->rs2_or_imm);
3699 } else {
3700 tcg_gen_xor_tl(src, src1, gen_load_gpr(dc, a->rs2_or_imm));
3701 }
3702 }
3703 }
3704 func(dc, src);
3705 return advance_pc(dc);
3706}
3707
3708static void do_wry(DisasContext *dc, TCGv src)
3709{
3710 tcg_gen_ext32u_tl(cpu_y, src);
3711}
3712
3713TRANS(WRY, ALL, do_wr_special, a, true, do_wry)
3714
3715static void do_wrccr(DisasContext *dc, TCGv src)
3716{
3717 gen_helper_wrccr(tcg_env, src);
3718}
3719
3720TRANS(WRCCR, 64, do_wr_special, a, true, do_wrccr)
3721
3722static void do_wrasi(DisasContext *dc, TCGv src)
3723{
3724 TCGv tmp = tcg_temp_new();
3725
3726 tcg_gen_ext8u_tl(tmp, src);
3727 tcg_gen_st32_tl(tmp, tcg_env, env64_field_offsetof(asi));
3728 /* End TB to notice changed ASI. */
3729 dc->base.is_jmp = DISAS_EXIT;
3730}
3731
3732TRANS(WRASI, 64, do_wr_special, a, true, do_wrasi)
3733
3734static void do_wrfprs(DisasContext *dc, TCGv src)
3735{
3736#ifdef TARGET_SPARC64
3737 tcg_gen_trunc_tl_i32(cpu_fprs, src);
3738 dc->fprs_dirty = 0;
3739 dc->base.is_jmp = DISAS_EXIT;
3740#else
3741 qemu_build_not_reached();
3742#endif
3743}
3744
3745TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
3746
3747static void do_wrgsr(DisasContext *dc, TCGv src)
3748{
3749 gen_trap_ifnofpu(dc);
3750 tcg_gen_mov_tl(cpu_gsr, src);
3751}
3752
3753TRANS(WRGSR, 64, do_wr_special, a, true, do_wrgsr)
3754
3755static void do_wrsoftint_set(DisasContext *dc, TCGv src)
3756{
3757 gen_helper_set_softint(tcg_env, src);
3758}
3759
3760TRANS(WRSOFTINT_SET, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_set)
3761
3762static void do_wrsoftint_clr(DisasContext *dc, TCGv src)
3763{
3764 gen_helper_clear_softint(tcg_env, src);
3765}
3766
3767TRANS(WRSOFTINT_CLR, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_clr)
3768
3769static void do_wrsoftint(DisasContext *dc, TCGv src)
3770{
3771 gen_helper_write_softint(tcg_env, src);
3772}
3773
3774TRANS(WRSOFTINT, 64, do_wr_special, a, supervisor(dc), do_wrsoftint)
3775
3776static void do_wrtick_cmpr(DisasContext *dc, TCGv src)
3777{
0faef01b
RH		 3778 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3779
577efa45
RH		 3780 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(tick_cmpr));
3781 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
0faef01b 3782 translator_io_start(&dc->base);
577efa45 3783 gen_helper_tick_set_limit(r_tickptr, src);
0faef01b
RH		 3784 /* End TB to handle timer interrupt */
3785 dc->base.is_jmp = DISAS_EXIT;
0faef01b
RH		 3786}
3787
3788TRANS(WRTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrtick_cmpr)
3789
3790static void do_wrstick(DisasContext *dc, TCGv src)
3791{
3792#ifdef TARGET_SPARC64
3793 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3794
3795 tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick));
3796 translator_io_start(&dc->base);
3797 gen_helper_tick_set_count(r_tickptr, src);
3798 /* End TB to handle timer interrupt */
3799 dc->base.is_jmp = DISAS_EXIT;
3800#else
3801 qemu_build_not_reached();
3802#endif
3803}
3804
3805TRANS(WRSTICK, 64, do_wr_special, a, supervisor(dc), do_wrstick)
3806
3807static void do_wrstick_cmpr(DisasContext *dc, TCGv src)
3808{
0faef01b
RH		 3809 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3810
577efa45
RH		 3811 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(stick_cmpr));
3812 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(stick));
0faef01b 3813 translator_io_start(&dc->base);
577efa45 3814 gen_helper_tick_set_limit(r_tickptr, src);
0faef01b
RH		 3815 /* End TB to handle timer interrupt */
3816 dc->base.is_jmp = DISAS_EXIT;
0faef01b
RH		 3817}
3818
3819TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrstick_cmpr)
3820
3821static void do_wrpowerdown(DisasContext *dc, TCGv src)
3822{
3823 save_state(dc);
3824 gen_helper_power_down(tcg_env);
3825}
3826
3827TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown)
3828
25524734
RH		 3829static void do_wrpsr(DisasContext *dc, TCGv src)
3830{
3831 gen_helper_wrpsr(tcg_env, src);
3832 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3833 dc->cc_op = CC_OP_FLAGS;
3834 dc->base.is_jmp = DISAS_EXIT;
3835}
3836
3837TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
3838
9422278e
RH		 3839static void do_wrwim(DisasContext *dc, TCGv src)
3840{
3841 target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows);
cd6269f7
RH		 3842 TCGv tmp = tcg_temp_new();
3843
3844 tcg_gen_andi_tl(tmp, src, mask);
3845 tcg_gen_st_tl(tmp, tcg_env, env32_field_offsetof(wim));
9422278e
RH		 3846}
3847
3848TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim)
3849
3850static void do_wrtpc(DisasContext *dc, TCGv src)
3851{
3852#ifdef TARGET_SPARC64
3853 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3854
3855 gen_load_trap_state_at_tl(r_tsptr);
3856 tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tpc));
3857#else
3858 qemu_build_not_reached();
3859#endif
3860}
3861
3862TRANS(WRPR_tpc, 64, do_wr_special, a, supervisor(dc), do_wrtpc)
3863
3864static void do_wrtnpc(DisasContext *dc, TCGv src)
3865{
3866#ifdef TARGET_SPARC64
3867 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3868
3869 gen_load_trap_state_at_tl(r_tsptr);
3870 tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tnpc));
3871#else
3872 qemu_build_not_reached();
3873#endif
3874}
3875
3876TRANS(WRPR_tnpc, 64, do_wr_special, a, supervisor(dc), do_wrtnpc)
3877
3878static void do_wrtstate(DisasContext *dc, TCGv src)
3879{
3880#ifdef TARGET_SPARC64
3881 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3882
3883 gen_load_trap_state_at_tl(r_tsptr);
3884 tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tstate));
3885#else
3886 qemu_build_not_reached();
3887#endif
3888}
3889
3890TRANS(WRPR_tstate, 64, do_wr_special, a, supervisor(dc), do_wrtstate)
3891
3892static void do_wrtt(DisasContext *dc, TCGv src)
3893{
3894#ifdef TARGET_SPARC64
3895 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
3896
3897 gen_load_trap_state_at_tl(r_tsptr);
3898 tcg_gen_st32_tl(src, r_tsptr, offsetof(trap_state, tt));
3899#else
3900 qemu_build_not_reached();
3901#endif
3902}
3903
3904TRANS(WRPR_tt, 64, do_wr_special, a, supervisor(dc), do_wrtt)
3905
3906static void do_wrtick(DisasContext *dc, TCGv src)
3907{
3908 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
3909
3910 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(tick));
3911 translator_io_start(&dc->base);
3912 gen_helper_tick_set_count(r_tickptr, src);
3913 /* End TB to handle timer interrupt */
3914 dc->base.is_jmp = DISAS_EXIT;
3915}
3916
3917TRANS(WRPR_tick, 64, do_wr_special, a, supervisor(dc), do_wrtick)
3918
3919static void do_wrtba(DisasContext *dc, TCGv src)
3920{
3921 tcg_gen_mov_tl(cpu_tbr, src);
3922}
3923
3924TRANS(WRPR_tba, 64, do_wr_special, a, supervisor(dc), do_wrtba)
3925
3926static void do_wrpstate(DisasContext *dc, TCGv src)
3927{
3928 save_state(dc);
3929 if (translator_io_start(&dc->base)) {
3930 dc->base.is_jmp = DISAS_EXIT;
3931 }
3932 gen_helper_wrpstate(tcg_env, src);
3933 dc->npc = DYNAMIC_PC;
3934}
3935
3936TRANS(WRPR_pstate, 64, do_wr_special, a, supervisor(dc), do_wrpstate)
3937
3938static void do_wrtl(DisasContext *dc, TCGv src)
3939{
3940 save_state(dc);
3941 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(tl));
3942 dc->npc = DYNAMIC_PC;
3943}
3944
3945TRANS(WRPR_tl, 64, do_wr_special, a, supervisor(dc), do_wrtl)
3946
3947static void do_wrpil(DisasContext *dc, TCGv src)
3948{
3949 if (translator_io_start(&dc->base)) {
3950 dc->base.is_jmp = DISAS_EXIT;
3951 }
3952 gen_helper_wrpil(tcg_env, src);
3953}
3954
3955TRANS(WRPR_pil, 64, do_wr_special, a, supervisor(dc), do_wrpil)
3956
3957static void do_wrcwp(DisasContext *dc, TCGv src)
3958{
3959 gen_helper_wrcwp(tcg_env, src);
3960}
3961
3962TRANS(WRPR_cwp, 64, do_wr_special, a, supervisor(dc), do_wrcwp)
3963
3964static void do_wrcansave(DisasContext *dc, TCGv src)
3965{
3966 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cansave));
3967}
3968
3969TRANS(WRPR_cansave, 64, do_wr_special, a, supervisor(dc), do_wrcansave)
3970
3971static void do_wrcanrestore(DisasContext *dc, TCGv src)
3972{
3973 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(canrestore));
3974}
3975
3976TRANS(WRPR_canrestore, 64, do_wr_special, a, supervisor(dc), do_wrcanrestore)
3977
3978static void do_wrcleanwin(DisasContext *dc, TCGv src)
3979{
3980 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(cleanwin));
3981}
3982
3983TRANS(WRPR_cleanwin, 64, do_wr_special, a, supervisor(dc), do_wrcleanwin)
3984
3985static void do_wrotherwin(DisasContext *dc, TCGv src)
3986{
3987 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(otherwin));
3988}
3989
3990TRANS(WRPR_otherwin, 64, do_wr_special, a, supervisor(dc), do_wrotherwin)
3991
3992static void do_wrwstate(DisasContext *dc, TCGv src)
3993{
3994 tcg_gen_st32_tl(src, tcg_env, env64_field_offsetof(wstate));
3995}
3996
3997TRANS(WRPR_wstate, 64, do_wr_special, a, supervisor(dc), do_wrwstate)
3998
3999static void do_wrgl(DisasContext *dc, TCGv src)
4000{
4001 gen_helper_wrgl(tcg_env, src);
4002}
4003
4004TRANS(WRPR_gl, GL, do_wr_special, a, supervisor(dc), do_wrgl)
4005
4006/* UA2005 strand status */
4007static void do_wrssr(DisasContext *dc, TCGv src)
4008{
2da789de 4009 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(ssr));
9422278e
RH		 4010}
4011
4012TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr)
4013
bb97f2f5
RH		 4014TRANS(WRTBR, 32, do_wr_special, a, supervisor(dc), do_wrtba)
4015
4016static void do_wrhpstate(DisasContext *dc, TCGv src)
4017{
4018 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hpstate));
4019 dc->base.is_jmp = DISAS_EXIT;
4020}
4021
4022TRANS(WRHPR_hpstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhpstate)
4023
4024static void do_wrhtstate(DisasContext *dc, TCGv src)
4025{
4026 TCGv_i32 tl = tcg_temp_new_i32();
4027 TCGv_ptr tp = tcg_temp_new_ptr();
4028
4029 tcg_gen_ld_i32(tl, tcg_env, env64_field_offsetof(tl));
4030 tcg_gen_andi_i32(tl, tl, MAXTL_MASK);
4031 tcg_gen_shli_i32(tl, tl, 3);
4032 tcg_gen_ext_i32_ptr(tp, tl);
4033 tcg_gen_add_ptr(tp, tp, tcg_env);
4034
4035 tcg_gen_st_tl(src, tp, env64_field_offsetof(htstate));
4036}
4037
4038TRANS(WRHPR_htstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtstate)
4039
4040static void do_wrhintp(DisasContext *dc, TCGv src)
4041{
2da789de 4042 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hintp));
bb97f2f5
RH		 4043}
4044
4045TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp)
4046
4047static void do_wrhtba(DisasContext *dc, TCGv src)
4048{
2da789de 4049 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(htba));
bb97f2f5
RH		 4050}
4051
4052TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba)
4053
4054static void do_wrhstick_cmpr(DisasContext *dc, TCGv src)
4055{
4056 TCGv_ptr r_tickptr = tcg_temp_new_ptr();
4057
577efa45 4058 tcg_gen_st_tl(src, tcg_env, env64_field_offsetof(hstick_cmpr));
bb97f2f5
RH		 4059 tcg_gen_ld_ptr(r_tickptr, tcg_env, env64_field_offsetof(hstick));
4060 translator_io_start(&dc->base);
577efa45 4061 gen_helper_tick_set_limit(r_tickptr, src);
bb97f2f5
RH		 4062 /* End TB to handle timer interrupt */
4063 dc->base.is_jmp = DISAS_EXIT;
4064}
4065
4066TRANS(WRHPR_hstick_cmpr, HYPV, do_wr_special, a, hypervisor(dc),
4067 do_wrhstick_cmpr)
4068
25524734
RH		 4069static bool do_saved_restored(DisasContext *dc, bool saved)
4070{
4071 if (!supervisor(dc)) {
4072 return raise_priv(dc);
4073 }
4074 if (saved) {
4075 gen_helper_saved(tcg_env);
4076 } else {
4077 gen_helper_restored(tcg_env);
4078 }
4079 return advance_pc(dc);
4080}
4081
4082TRANS(SAVED, 64, do_saved_restored, true)
4083TRANS(RESTORED, 64, do_saved_restored, false)
4084
d3825800
RH		 4085static bool trans_NOP(DisasContext *dc, arg_NOP *a)
4086{
4087 return advance_pc(dc);
4088}
4089
0faef01b
RH		 4090static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
4091{
4092 /*
4093 * TODO: Need a feature bit for sparcv8.
4094 * In the meantime, treat all 32-bit cpus like sparcv7.
4095 */
4096 if (avail_32(dc)) {
4097 return advance_pc(dc);
4098 }
4099 return false;
4100}
4101
428881de
RH		 4102static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
4103 void (*func)(TCGv, TCGv, TCGv),
4104 void (*funci)(TCGv, TCGv, target_long))
4105{
4106 TCGv dst, src1;
4107
4108 /* For simplicity, we under-decoded the rs2 form. */
4109 if (!a->imm && a->rs2_or_imm & ~0x1f) {
4110 return false;
4111 }
4112
4113 if (a->cc) {
4114 dst = cpu_cc_dst;
4115 } else {
4116 dst = gen_dest_gpr(dc, a->rd);
4117 }
4118 src1 = gen_load_gpr(dc, a->rs1);
4119
4120 if (a->imm || a->rs2_or_imm == 0) {
4121 if (funci) {
4122 funci(dst, src1, a->rs2_or_imm);
4123 } else {
4124 func(dst, src1, tcg_constant_tl(a->rs2_or_imm));
4125 }
4126 } else {
4127 func(dst, src1, cpu_regs[a->rs2_or_imm]);
4128 }
4129 gen_store_gpr(dc, a->rd, dst);
4130
4131 if (a->cc) {
4132 tcg_gen_movi_i32(cpu_cc_op, cc_op);
4133 dc->cc_op = cc_op;
4134 }
4135 return advance_pc(dc);
4136}
4137
4138static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
4139 void (*func)(TCGv, TCGv, TCGv),
4140 void (*funci)(TCGv, TCGv, target_long),
4141 void (*func_cc)(TCGv, TCGv, TCGv))
4142{
4143 if (a->cc) {
22188d7d 4144 assert(cc_op >= 0);
428881de
RH		 4145 return do_arith_int(dc, a, cc_op, func_cc, NULL);
4146 }
4147 return do_arith_int(dc, a, cc_op, func, funci);
4148}
4149
4150static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a,
4151 void (*func)(TCGv, TCGv, TCGv),
4152 void (*funci)(TCGv, TCGv, target_long))
4153{
4154 return do_arith_int(dc, a, CC_OP_LOGIC, func, funci);
4155}
4156
4157TRANS(ADD, ALL, do_arith, a, CC_OP_ADD,
4158 tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc)
4159TRANS(SUB, ALL, do_arith, a, CC_OP_SUB,
4160 tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc)
4161
a9aba13d
RH		 4162TRANS(TADDcc, ALL, do_arith, a, CC_OP_TADD, NULL, NULL, gen_op_add_cc)
4163TRANS(TSUBcc, ALL, do_arith, a, CC_OP_TSUB, NULL, NULL, gen_op_sub_cc)
4164TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcctv)
4165TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcctv)
4166
428881de
RH		 4167TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
4168TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
4169TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
4170TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL)
4171TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL)
4172
22188d7d 4173TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL)
b5372650
RH		 4174TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL)
4175TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
22188d7d 4176
4ee85ea9
RH		 4177TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL)
4178TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL)
c2636853
RH		 4179TRANS(UDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_udiv, NULL, gen_op_udivcc)
4180TRANS(SDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_sdiv, NULL, gen_op_sdivcc)
4ee85ea9 4181
9c6ec5bc
RH		 4182/* TODO: Should have feature bit -- comes in with UltraSparc T2. */
4183TRANS(POPC, 64, do_arith, a, -1, gen_op_popc, NULL, NULL)
4184
428881de
RH		 4185static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
4186{
4187 /* OR with %g0 is the canonical alias for MOV. */
4188 if (!a->cc && a->rs1 == 0) {
4189 if (a->imm || a->rs2_or_imm == 0) {
4190 gen_store_gpr(dc, a->rd, tcg_constant_tl(a->rs2_or_imm));
4191 } else if (a->rs2_or_imm & ~0x1f) {
4192 /* For simplicity, we under-decoded the rs2 form. */
4193 return false;
4194 } else {
4195 gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]);
4196 }
4197 return advance_pc(dc);
4198 }
4199 return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
4200}
4201
420a187d
RH		 4202static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a)
4203{
4204 switch (dc->cc_op) {
4205 case CC_OP_DIV:
4206 case CC_OP_LOGIC:
4207 /* Carry is known to be zero. Fall back to plain ADD. */
4208 return do_arith(dc, a, CC_OP_ADD,
4209 tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_add_cc);
4210 case CC_OP_ADD:
4211 case CC_OP_TADD:
4212 case CC_OP_TADDTV:
4213 return do_arith(dc, a, CC_OP_ADDX,
4214 gen_op_addc_add, NULL, gen_op_addccc_add);
4215 case CC_OP_SUB:
4216 case CC_OP_TSUB:
4217 case CC_OP_TSUBTV:
4218 return do_arith(dc, a, CC_OP_ADDX,
4219 gen_op_addc_sub, NULL, gen_op_addccc_sub);
4220 default:
4221 return do_arith(dc, a, CC_OP_ADDX,
4222 gen_op_addc_generic, NULL, gen_op_addccc_generic);
4223 }
4224}
4225
dfebb950
RH		 4226static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a)
4227{
4228 switch (dc->cc_op) {
4229 case CC_OP_DIV:
4230 case CC_OP_LOGIC:
4231 /* Carry is known to be zero. Fall back to plain SUB. */
4232 return do_arith(dc, a, CC_OP_SUB,
4233 tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc);
4234 case CC_OP_ADD:
4235 case CC_OP_TADD:
4236 case CC_OP_TADDTV:
4237 return do_arith(dc, a, CC_OP_SUBX,
4238 gen_op_subc_add, NULL, gen_op_subccc_add);
4239 case CC_OP_SUB:
4240 case CC_OP_TSUB:
4241 case CC_OP_TSUBTV:
4242 return do_arith(dc, a, CC_OP_SUBX,
4243 gen_op_subc_sub, NULL, gen_op_subccc_sub);
4244 default:
4245 return do_arith(dc, a, CC_OP_SUBX,
4246 gen_op_subc_generic, NULL, gen_op_subccc_generic);
4247 }
4248}
4249
a9aba13d
RH		 4250static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a)
4251{
4252 update_psr(dc);
4253 return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc);
4254}
4255
5fc546ee
RH		 4256static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
4257{
4258 TCGv dst, src1, src2;
4259
4260 /* Reject 64-bit shifts for sparc32. */
4261 if (avail_32(dc) && a->x) {
4262 return false;
4263 }
4264
4265 src2 = tcg_temp_new();
4266 tcg_gen_andi_tl(src2, gen_load_gpr(dc, a->rs2), a->x ? 63 : 31);
4267 src1 = gen_load_gpr(dc, a->rs1);
4268 dst = gen_dest_gpr(dc, a->rd);
4269
4270 if (l) {
4271 tcg_gen_shl_tl(dst, src1, src2);
4272 if (!a->x) {
4273 tcg_gen_ext32u_tl(dst, dst);
4274 }
4275 } else if (u) {
4276 if (!a->x) {
4277 tcg_gen_ext32u_tl(dst, src1);
4278 src1 = dst;
4279 }
4280 tcg_gen_shr_tl(dst, src1, src2);
4281 } else {
4282 if (!a->x) {
4283 tcg_gen_ext32s_tl(dst, src1);
4284 src1 = dst;
4285 }
4286 tcg_gen_sar_tl(dst, src1, src2);
4287 }
4288 gen_store_gpr(dc, a->rd, dst);
4289 return advance_pc(dc);
4290}
4291
4292TRANS(SLL_r, ALL, do_shift_r, a, true, true)
4293TRANS(SRL_r, ALL, do_shift_r, a, false, true)
4294TRANS(SRA_r, ALL, do_shift_r, a, false, false)
4295
4296static bool do_shift_i(DisasContext *dc, arg_shifti *a, bool l, bool u)
4297{
4298 TCGv dst, src1;
4299
4300 /* Reject 64-bit shifts for sparc32. */
4301 if (avail_32(dc) && (a->x || a->i >= 32)) {
4302 return false;
4303 }
4304
4305 src1 = gen_load_gpr(dc, a->rs1);
4306 dst = gen_dest_gpr(dc, a->rd);
4307
4308 if (avail_32(dc) || a->x) {
4309 if (l) {
4310 tcg_gen_shli_tl(dst, src1, a->i);
4311 } else if (u) {
4312 tcg_gen_shri_tl(dst, src1, a->i);
4313 } else {
4314 tcg_gen_sari_tl(dst, src1, a->i);
4315 }
4316 } else {
4317 if (l) {
4318 tcg_gen_deposit_z_tl(dst, src1, a->i, 32 - a->i);
4319 } else if (u) {
4320 tcg_gen_extract_tl(dst, src1, a->i, 32 - a->i);
4321 } else {
4322 tcg_gen_sextract_tl(dst, src1, a->i, 32 - a->i);
4323 }
4324 }
4325 gen_store_gpr(dc, a->rd, dst);
4326 return advance_pc(dc);
4327}
4328
4329TRANS(SLL_i, ALL, do_shift_i, a, true, true)
4330TRANS(SRL_i, ALL, do_shift_i, a, false, true)
4331TRANS(SRA_i, ALL, do_shift_i, a, false, false)
4332
fb4ed7aa
RH		 4333static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm)
4334{
4335 /* For simplicity, we under-decoded the rs2 form. */
4336 if (!imm && rs2_or_imm & ~0x1f) {
4337 return NULL;
4338 }
4339 if (imm || rs2_or_imm == 0) {
4340 return tcg_constant_tl(rs2_or_imm);
4341 } else {
4342 return cpu_regs[rs2_or_imm];
4343 }
4344}
4345
4346static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv src2)
4347{
4348 TCGv dst = gen_load_gpr(dc, rd);
4349
4350 tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst);
4351 gen_store_gpr(dc, rd, dst);
4352 return advance_pc(dc);
4353}
4354
4355static bool trans_MOVcc(DisasContext *dc, arg_MOVcc *a)
4356{
4357 TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4358 DisasCompare cmp;
4359
4360 if (src2 == NULL) {
4361 return false;
4362 }
4363 gen_compare(&cmp, a->cc, a->cond, dc);
4364 return do_mov_cond(dc, &cmp, a->rd, src2);
4365}
4366
4367static bool trans_MOVfcc(DisasContext *dc, arg_MOVfcc *a)
4368{
4369 TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4370 DisasCompare cmp;
4371
4372 if (src2 == NULL) {
4373 return false;
4374 }
4375 gen_fcompare(&cmp, a->cc, a->cond);
4376 return do_mov_cond(dc, &cmp, a->rd, src2);
4377}
4378
4379static bool trans_MOVR(DisasContext *dc, arg_MOVR *a)
4380{
4381 TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
4382 DisasCompare cmp;
4383
4384 if (src2 == NULL) {
4385 return false;
4386 }
4387 gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
4388 return do_mov_cond(dc, &cmp, a->rd, src2);
4389}
4390
86b82fe0
RH		 4391static bool do_add_special(DisasContext *dc, arg_r_r_ri *a,
4392 bool (*func)(DisasContext *dc, int rd, TCGv src))
4393{
4394 TCGv src1, sum;
4395
4396 /* For simplicity, we under-decoded the rs2 form. */
4397 if (!a->imm && a->rs2_or_imm & ~0x1f) {
4398 return false;
4399 }
4400
4401 /*
4402 * Always load the sum into a new temporary.
4403 * This is required to capture the value across a window change,
4404 * e.g. SAVE and RESTORE, and may be optimized away otherwise.
4405 */
4406 sum = tcg_temp_new();
4407 src1 = gen_load_gpr(dc, a->rs1);
4408 if (a->imm || a->rs2_or_imm == 0) {
4409 tcg_gen_addi_tl(sum, src1, a->rs2_or_imm);
4410 } else {
4411 tcg_gen_add_tl(sum, src1, cpu_regs[a->rs2_or_imm]);
4412 }
4413 return func(dc, a->rd, sum);
4414}
4415
4416static bool do_jmpl(DisasContext *dc, int rd, TCGv src)
4417{
4418 /*
4419 * Preserve pc across advance, so that we can delay
4420 * the writeback to rd until after src is consumed.
4421 */
4422 target_ulong cur_pc = dc->pc;
4423
4424 gen_check_align(dc, src, 3);
4425
4426 gen_mov_pc_npc(dc);
4427 tcg_gen_mov_tl(cpu_npc, src);
4428 gen_address_mask(dc, cpu_npc);
4429 gen_store_gpr(dc, rd, tcg_constant_tl(cur_pc));
4430
4431 dc->npc = DYNAMIC_PC_LOOKUP;
4432 return true;
4433}
4434
4435TRANS(JMPL, ALL, do_add_special, a, do_jmpl)
4436
4437static bool do_rett(DisasContext *dc, int rd, TCGv src)
4438{
4439 if (!supervisor(dc)) {
4440 return raise_priv(dc);
4441 }
4442
4443 gen_check_align(dc, src, 3);
4444
4445 gen_mov_pc_npc(dc);
4446 tcg_gen_mov_tl(cpu_npc, src);
4447 gen_helper_rett(tcg_env);
4448
4449 dc->npc = DYNAMIC_PC;
4450 return true;
4451}
4452
4453TRANS(RETT, 32, do_add_special, a, do_rett)
4454
4455static bool do_return(DisasContext *dc, int rd, TCGv src)
4456{
4457 gen_check_align(dc, src, 3);
4458
4459 gen_mov_pc_npc(dc);
4460 tcg_gen_mov_tl(cpu_npc, src);
4461 gen_address_mask(dc, cpu_npc);
4462
4463 gen_helper_restore(tcg_env);
4464 dc->npc = DYNAMIC_PC_LOOKUP;
4465 return true;
4466}
4467
4468TRANS(RETURN, 64, do_add_special, a, do_return)
4469
d3825800
RH		 4470static bool do_save(DisasContext *dc, int rd, TCGv src)
4471{
4472 gen_helper_save(tcg_env);
4473 gen_store_gpr(dc, rd, src);
4474 return advance_pc(dc);
4475}
4476
4477TRANS(SAVE, ALL, do_add_special, a, do_save)
4478
4479static bool do_restore(DisasContext *dc, int rd, TCGv src)
4480{
4481 gen_helper_restore(tcg_env);
4482 gen_store_gpr(dc, rd, src);
4483 return advance_pc(dc);
4484}
4485
4486TRANS(RESTORE, ALL, do_add_special, a, do_restore)
4487
8f75b8a4
RH		 4488static bool do_done_retry(DisasContext *dc, bool done)
4489{
4490 if (!supervisor(dc)) {
4491 return raise_priv(dc);
4492 }
4493 dc->npc = DYNAMIC_PC;
4494 dc->pc = DYNAMIC_PC;
4495 translator_io_start(&dc->base);
4496 if (done) {
4497 gen_helper_done(tcg_env);
4498 } else {
4499 gen_helper_retry(tcg_env);
4500 }
4501 return true;
4502}
4503
4504TRANS(DONE, 64, do_done_retry, true)
4505TRANS(RETRY, 64, do_done_retry, false)
4506
64a88d5d 4507#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 4508 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 4509 goto illegal_insn;
4510#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 4511 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 4512 goto nfpu_insn;
4513
0bee699e 4514/* before an instruction, dc->pc must be static */
878cc677 4515static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cf495bcf 4516{
0184e266 4517 unsigned int opc, rs1, rs2, rd;
8f75b8a4
RH		 4518 TCGv cpu_src1;
4519 TCGv cpu_src2 __attribute__((unused));
208ae657 4520 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 4521 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 4522 target_long simm;
7a3f1944 4523
cf495bcf 4524 opc = GET_FIELD(insn, 0, 1);
cf495bcf 4525 rd = GET_FIELD(insn, 2, 6);
6ae20372 4526
cf495bcf 4527 switch (opc) {
6d2a0768
RH		 4528 case 0:
4529 goto illegal_insn; /* in decodetree */
23ada1b1
RH		 4530 case 1:
4531 g_assert_not_reached(); /* in decodetree */
0f8a249a
BS		 4532 case 2: /* FPU & Logical Operations */
4533 {
8f75b8a4 4534 unsigned int xop = GET_FIELD(insn, 7, 12);
af25071c 4535 TCGv cpu_dst __attribute__((unused)) = tcg_temp_new();
5793f2a4 4536
af25071c 4537 if (xop == 0x34) { /* FPU Operations */
5b12f1e8 4538 if (gen_trap_ifnofpu(dc)) {
a80dde08 4539 goto jmp_insn;
5b12f1e8 4540 }
0f8a249a 4541 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 4542 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 4543 rs2 = GET_FIELD(insn, 27, 31);
4544 xop = GET_FIELD(insn, 18, 26);
02c79d78 4545
0f8a249a 4546 switch (xop) {
dc1a6971 4547 case 0x1: /* fmovs */
208ae657
RH		 4548 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4549 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 4550 break;
4551 case 0x5: /* fnegs */
61f17f6e 4552 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 4553 break;
4554 case 0x9: /* fabss */
61f17f6e 4555 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 4556 break;
4557 case 0x29: /* fsqrts */
61f17f6e 4558 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 4559 break;
4560 case 0x2a: /* fsqrtd */
61f17f6e 4561 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 4562 break;
4563 case 0x2b: /* fsqrtq */
4564 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4565 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 4566 break;
4567 case 0x41: /* fadds */
61f17f6e 4568 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 4569 break;
4570 case 0x42: /* faddd */
61f17f6e 4571 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 4572 break;
4573 case 0x43: /* faddq */
4574 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4575 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 4576 break;
4577 case 0x45: /* fsubs */
61f17f6e 4578 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 4579 break;
4580 case 0x46: /* fsubd */
61f17f6e 4581 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 4582 break;
4583 case 0x47: /* fsubq */
4584 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4585 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 4586 break;
4587 case 0x49: /* fmuls */
61f17f6e 4588 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 4589 break;
4590 case 0x4a: /* fmuld */
61f17f6e 4591 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 4592 break;
4593 case 0x4b: /* fmulq */
4594 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4595 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 4596 break;
4597 case 0x4d: /* fdivs */
61f17f6e 4598 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 4599 break;
4600 case 0x4e: /* fdivd */
61f17f6e 4601 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 4602 break;
4603 case 0x4f: /* fdivq */
4604 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4605 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 4606 break;
4607 case 0x69: /* fsmuld */
4608 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 4609 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 4610 break;
4611 case 0x6e: /* fdmulq */
4612 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4613 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 4614 break;
4615 case 0xc4: /* fitos */
61f17f6e 4616 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 4617 break;
4618 case 0xc6: /* fdtos */
61f17f6e 4619 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 4620 break;
4621 case 0xc7: /* fqtos */
4622 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4623 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 4624 break;
4625 case 0xc8: /* fitod */
61f17f6e 4626 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 4627 break;
4628 case 0xc9: /* fstod */
61f17f6e 4629 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 4630 break;
4631 case 0xcb: /* fqtod */
4632 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4633 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 4634 break;
4635 case 0xcc: /* fitoq */
4636 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4637 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 4638 break;
4639 case 0xcd: /* fstoq */
4640 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4641 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 4642 break;
4643 case 0xce: /* fdtoq */
4644 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4645 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 4646 break;
4647 case 0xd1: /* fstoi */
61f17f6e 4648 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 4649 break;
4650 case 0xd2: /* fdtoi */
61f17f6e 4651 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 4652 break;
4653 case 0xd3: /* fqtoi */
4654 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4655 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 4656 break;
3475187d 4657#ifdef TARGET_SPARC64
dc1a6971 4658 case 0x2: /* V9 fmovd */
96eda024
RH		 4659 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4660 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 4661 break;
4662 case 0x3: /* V9 fmovq */
4663 CHECK_FPU_FEATURE(dc, FLOAT128);
f9c816c0 4664 gen_move_Q(dc, rd, rs2);
dc1a6971
BS		 4665 break;
4666 case 0x6: /* V9 fnegd */
61f17f6e 4667 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 4668 break;
4669 case 0x7: /* V9 fnegq */
4670 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4671 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 4672 break;
4673 case 0xa: /* V9 fabsd */
61f17f6e 4674 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 4675 break;
4676 case 0xb: /* V9 fabsq */
4677 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4678 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 4679 break;
4680 case 0x81: /* V9 fstox */
61f17f6e 4681 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 4682 break;
4683 case 0x82: /* V9 fdtox */
61f17f6e 4684 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 4685 break;
4686 case 0x83: /* V9 fqtox */
4687 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4688 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 4689 break;
4690 case 0x84: /* V9 fxtos */
61f17f6e 4691 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 4692 break;
4693 case 0x88: /* V9 fxtod */
61f17f6e 4694 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 4695 break;
4696 case 0x8c: /* V9 fxtoq */
4697 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 4698 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 4699 break;
0f8a249a 4700#endif
dc1a6971
BS		 4701 default:
4702 goto illegal_insn;
0f8a249a
BS		 4703 }
4704 } else if (xop == 0x35) { /* FPU Operations */
3475187d 4705#ifdef TARGET_SPARC64
0f8a249a 4706 int cond;
3475187d 4707#endif
5b12f1e8 4708 if (gen_trap_ifnofpu(dc)) {
a80dde08 4709 goto jmp_insn;
5b12f1e8 4710 }
0f8a249a 4711 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 4712 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 4713 rs2 = GET_FIELD(insn, 27, 31);
4714 xop = GET_FIELD(insn, 18, 26);
dcf24905 4715
690995a6
RH		 4716#ifdef TARGET_SPARC64
4717#define FMOVR(sz) \
4718 do { \
4719 DisasCompare cmp; \
e7c8afb9 4720 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 4721 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 4722 gen_compare_reg(&cmp, cond, cpu_src1); \
4723 gen_fmov##sz(dc, &cmp, rd, rs2); \
690995a6
RH		 4724 } while (0)
4725
4726 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
4727 FMOVR(s);
0f8a249a
BS		 4728 break;
4729 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 4730 FMOVR(d);
0f8a249a
BS		 4731 break;
4732 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 4733 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 4734 FMOVR(q);
1f587329 4735 break;
0f8a249a 4736 }
690995a6 4737#undef FMOVR
0f8a249a
BS		 4738#endif
4739 switch (xop) {
3475187d 4740#ifdef TARGET_SPARC64
7e480893
RH		 4741#define FMOVCC(fcc, sz) \
4742 do { \
4743 DisasCompare cmp; \
714547bb 4744 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 4745 gen_fcompare(&cmp, fcc, cond); \
4746 gen_fmov##sz(dc, &cmp, rd, rs2); \
7e480893
RH		 4747 } while (0)
4748
0f8a249a 4749 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 4750 FMOVCC(0, s);
0f8a249a
BS		 4751 break;
4752 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 4753 FMOVCC(0, d);
0f8a249a
BS		 4754 break;
4755 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 4756 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4757 FMOVCC(0, q);
1f587329 4758 break;
0f8a249a 4759 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 4760 FMOVCC(1, s);
0f8a249a
BS		 4761 break;
4762 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 4763 FMOVCC(1, d);
0f8a249a
BS		 4764 break;
4765 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 4766 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4767 FMOVCC(1, q);
1f587329 4768 break;
0f8a249a 4769 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 4770 FMOVCC(2, s);
0f8a249a
BS		 4771 break;
4772 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 4773 FMOVCC(2, d);
0f8a249a
BS		 4774 break;
4775 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 4776 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4777 FMOVCC(2, q);
1f587329 4778 break;
0f8a249a 4779 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 4780 FMOVCC(3, s);
0f8a249a
BS		 4781 break;
4782 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 4783 FMOVCC(3, d);
0f8a249a
BS		 4784 break;
4785 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 4786 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4787 FMOVCC(3, q);
1f587329 4788 break;
7e480893
RH		 4789#undef FMOVCC
4790#define FMOVCC(xcc, sz) \
4791 do { \
4792 DisasCompare cmp; \
714547bb 4793 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 4794 gen_compare(&cmp, xcc, cond, dc); \
4795 gen_fmov##sz(dc, &cmp, rd, rs2); \
7e480893 4796 } while (0)
19f329ad 4797
0f8a249a 4798 case 0x101: /* V9 fmovscc %icc */
7e480893 4799 FMOVCC(0, s);
0f8a249a
BS		 4800 break;
4801 case 0x102: /* V9 fmovdcc %icc */
7e480893 4802 FMOVCC(0, d);
b7d69dc2 4803 break;
0f8a249a 4804 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 4805 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4806 FMOVCC(0, q);
1f587329 4807 break;
0f8a249a 4808 case 0x181: /* V9 fmovscc %xcc */
7e480893 4809 FMOVCC(1, s);
0f8a249a
BS		 4810 break;
4811 case 0x182: /* V9 fmovdcc %xcc */
7e480893 4812 FMOVCC(1, d);
0f8a249a
BS		 4813 break;
4814 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 4815 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 4816 FMOVCC(1, q);
1f587329 4817 break;
7e480893 4818#undef FMOVCC
1f587329
BS		 4819#endif
4820 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 4821 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4822 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
4823 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 4824 break;
1f587329 4825 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 4826 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4827 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4828 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 4829 break;
1f587329 4830 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 4831 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 4832 gen_op_load_fpr_QT0(QFPREG(rs1));
4833 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 4834 gen_op_fcmpq(rd & 3);
1f587329 4835 break;
0f8a249a 4836 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 4837 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4838 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
4839 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 4840 break;
4841 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 4842 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4843 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4844 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 4845 break;
1f587329 4846 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 4847 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 4848 gen_op_load_fpr_QT0(QFPREG(rs1));
4849 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 4850 gen_op_fcmpeq(rd & 3);
1f587329 4851 break;
0f8a249a
BS		 4852 default:
4853 goto illegal_insn;
4854 }
d3c7e8ad 4855 } else if (xop == 0x36) {
3299908c 4856#ifdef TARGET_SPARC64
d3c7e8ad 4857 /* VIS */
3299908c
BS		 4858 int opf = GET_FIELD_SP(insn, 5, 13);
4859 rs1 = GET_FIELD(insn, 13, 17);
4860 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4861 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4862 goto jmp_insn;
5b12f1e8 4863 }
3299908c
BS		 4864
4865 switch (opf) {
e9ebed4d 4866 case 0x000: /* VIS I edge8cc */
6c073553 4867 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4868 cpu_src1 = gen_load_gpr(dc, rs1);
4869 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4870 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4871 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4872 break;
e9ebed4d 4873 case 0x001: /* VIS II edge8n */
6c073553 4874 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4875 cpu_src1 = gen_load_gpr(dc, rs1);
4876 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4877 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4878 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4879 break;
e9ebed4d 4880 case 0x002: /* VIS I edge8lcc */
6c073553 4881 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4882 cpu_src1 = gen_load_gpr(dc, rs1);
4883 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4884 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4885 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4886 break;
e9ebed4d 4887 case 0x003: /* VIS II edge8ln */
6c073553 4888 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4889 cpu_src1 = gen_load_gpr(dc, rs1);
4890 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4891 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4892 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4893 break;
e9ebed4d 4894 case 0x004: /* VIS I edge16cc */
6c073553 4895 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4896 cpu_src1 = gen_load_gpr(dc, rs1);
4897 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4898 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4899 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4900 break;
e9ebed4d 4901 case 0x005: /* VIS II edge16n */
6c073553 4902 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4903 cpu_src1 = gen_load_gpr(dc, rs1);
4904 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4905 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4906 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4907 break;
e9ebed4d 4908 case 0x006: /* VIS I edge16lcc */
6c073553 4909 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4910 cpu_src1 = gen_load_gpr(dc, rs1);
4911 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4912 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4913 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4914 break;
e9ebed4d 4915 case 0x007: /* VIS II edge16ln */
6c073553 4916 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4917 cpu_src1 = gen_load_gpr(dc, rs1);
4918 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4919 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4920 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4921 break;
e9ebed4d 4922 case 0x008: /* VIS I edge32cc */
6c073553 4923 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4924 cpu_src1 = gen_load_gpr(dc, rs1);
4925 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4926 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4927 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4928 break;
e9ebed4d 4929 case 0x009: /* VIS II edge32n */
6c073553 4930 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4931 cpu_src1 = gen_load_gpr(dc, rs1);
4932 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4933 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4934 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4935 break;
e9ebed4d 4936 case 0x00a: /* VIS I edge32lcc */
6c073553 4937 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4938 cpu_src1 = gen_load_gpr(dc, rs1);
4939 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4940 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4941 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4942 break;
e9ebed4d 4943 case 0x00b: /* VIS II edge32ln */
6c073553 4944 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4945 cpu_src1 = gen_load_gpr(dc, rs1);
4946 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4947 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4948 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4949 break;
e9ebed4d 4950 case 0x010: /* VIS I array8 */
64a88d5d 4951 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4952 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4953 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4954 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4955 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4956 break;
4957 case 0x012: /* VIS I array16 */
64a88d5d 4958 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4959 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4960 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4961 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4962 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4963 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4964 break;
4965 case 0x014: /* VIS I array32 */
64a88d5d 4966 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4967 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4968 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4969 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4970 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4971 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4972 break;
3299908c 4973 case 0x018: /* VIS I alignaddr */
64a88d5d 4974 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4975 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4976 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4977 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4978 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4979 break;
4980 case 0x01a: /* VIS I alignaddrl */
add545ab 4981 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4982 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4983 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4984 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4985 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4986 break;
4987 case 0x019: /* VIS II bmask */
793a137a 4988 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4989 cpu_src1 = gen_load_gpr(dc, rs1);
4990 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4991 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4992 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4993 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4994 break;
e9ebed4d 4995 case 0x020: /* VIS I fcmple16 */
64a88d5d 4996 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4997 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4998 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4999 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5000 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5001 break;
5002 case 0x022: /* VIS I fcmpne16 */
64a88d5d 5003 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5004 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5005 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5006 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5007 gen_store_gpr(dc, rd, cpu_dst);
3299908c 5008 break;
e9ebed4d 5009 case 0x024: /* VIS I fcmple32 */
64a88d5d 5010 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5011 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5012 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5013 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5014 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5015 break;
5016 case 0x026: /* VIS I fcmpne32 */
64a88d5d 5017 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5018 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5019 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5020 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5021 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5022 break;
5023 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 5024 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5025 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5026 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5027 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5028 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5029 break;
5030 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 5031 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5032 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5033 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5034 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5035 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5036 break;
5037 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 5038 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5039 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5040 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5041 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5042 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5043 break;
5044 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 5045 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 5046 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5047 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 5048 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 5049 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 5050 break;
5051 case 0x031: /* VIS I fmul8x16 */
64a88d5d 5052 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5053 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 5054 break;
5055 case 0x033: /* VIS I fmul8x16au */
64a88d5d 5056 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5057 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 5058 break;
5059 case 0x035: /* VIS I fmul8x16al */
64a88d5d 5060 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5061 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 5062 break;
5063 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 5064 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5065 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 5066 break;
5067 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 5068 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5069 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 5070 break;
5071 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 5072 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5073 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 5074 break;
5075 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 5076 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5077 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 5078 break;
5079 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 5080 CHECK_FPU_FEATURE(dc, VIS1);
5081 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
5082 break;
e9ebed4d 5083 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 5084 CHECK_FPU_FEATURE(dc, VIS1);
5085 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 5086 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 5087 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
5088 gen_store_fpr_F(dc, rd, cpu_dst_32);
5089 break;
e9ebed4d 5090 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 5091 CHECK_FPU_FEATURE(dc, VIS1);
5092 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 5093 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 5094 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
5095 gen_store_fpr_F(dc, rd, cpu_dst_32);
5096 break;
f888300b
RH		 5097 case 0x03e: /* VIS I pdist */
5098 CHECK_FPU_FEATURE(dc, VIS1);
5099 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
5100 break;
3299908c 5101 case 0x048: /* VIS I faligndata */
64a88d5d 5102 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 5103 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 5104 break;
e9ebed4d 5105 case 0x04b: /* VIS I fpmerge */
64a88d5d 5106 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5107 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 5108 break;
5109 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 5110 CHECK_FPU_FEATURE(dc, VIS2);
5111 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
5112 break;
e9ebed4d 5113 case 0x04d: /* VIS I fexpand */
64a88d5d 5114 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5115 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 5116 break;
5117 case 0x050: /* VIS I fpadd16 */
64a88d5d 5118 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5119 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 5120 break;
5121 case 0x051: /* VIS I fpadd16s */
64a88d5d 5122 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5123 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 5124 break;
5125 case 0x052: /* VIS I fpadd32 */
64a88d5d 5126 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5127 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 5128 break;
5129 case 0x053: /* VIS I fpadd32s */
64a88d5d 5130 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5131 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 5132 break;
5133 case 0x054: /* VIS I fpsub16 */
64a88d5d 5134 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5135 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 5136 break;
5137 case 0x055: /* VIS I fpsub16s */
64a88d5d 5138 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5139 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 5140 break;
5141 case 0x056: /* VIS I fpsub32 */
64a88d5d 5142 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5143 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 5144 break;
5145 case 0x057: /* VIS I fpsub32s */
64a88d5d 5146 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5147 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 5148 break;
3299908c 5149 case 0x060: /* VIS I fzero */
64a88d5d 5150 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5151 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5152 tcg_gen_movi_i64(cpu_dst_64, 0);
5153 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5154 break;
5155 case 0x061: /* VIS I fzeros */
64a88d5d 5156 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5157 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5158 tcg_gen_movi_i32(cpu_dst_32, 0);
5159 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5160 break;
e9ebed4d 5161 case 0x062: /* VIS I fnor */
64a88d5d 5162 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5163 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 5164 break;
5165 case 0x063: /* VIS I fnors */
64a88d5d 5166 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5167 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 5168 break;
5169 case 0x064: /* VIS I fandnot2 */
64a88d5d 5170 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5171 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 5172 break;
5173 case 0x065: /* VIS I fandnot2s */
64a88d5d 5174 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5175 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 5176 break;
5177 case 0x066: /* VIS I fnot2 */
64a88d5d 5178 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5179 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 5180 break;
5181 case 0x067: /* VIS I fnot2s */
64a88d5d 5182 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5183 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 5184 break;
5185 case 0x068: /* VIS I fandnot1 */
64a88d5d 5186 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5187 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 5188 break;
5189 case 0x069: /* VIS I fandnot1s */
64a88d5d 5190 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5191 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 5192 break;
5193 case 0x06a: /* VIS I fnot1 */
64a88d5d 5194 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5195 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 5196 break;
5197 case 0x06b: /* VIS I fnot1s */
64a88d5d 5198 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5199 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 5200 break;
5201 case 0x06c: /* VIS I fxor */
64a88d5d 5202 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5203 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 5204 break;
5205 case 0x06d: /* VIS I fxors */
64a88d5d 5206 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5207 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 5208 break;
5209 case 0x06e: /* VIS I fnand */
64a88d5d 5210 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5211 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 5212 break;
5213 case 0x06f: /* VIS I fnands */
64a88d5d 5214 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5215 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 5216 break;
5217 case 0x070: /* VIS I fand */
64a88d5d 5218 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5219 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 5220 break;
5221 case 0x071: /* VIS I fands */
64a88d5d 5222 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5223 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 5224 break;
5225 case 0x072: /* VIS I fxnor */
64a88d5d 5226 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5227 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 5228 break;
5229 case 0x073: /* VIS I fxnors */
64a88d5d 5230 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5231 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 5232 break;
3299908c 5233 case 0x074: /* VIS I fsrc1 */
64a88d5d 5234 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5235 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5236 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5237 break;
5238 case 0x075: /* VIS I fsrc1s */
64a88d5d 5239 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5240 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5241 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5242 break;
e9ebed4d 5243 case 0x076: /* VIS I fornot2 */
64a88d5d 5244 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5245 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 5246 break;
5247 case 0x077: /* VIS I fornot2s */
64a88d5d 5248 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5249 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 5250 break;
3299908c 5251 case 0x078: /* VIS I fsrc2 */
64a88d5d 5252 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5253 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5254 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5255 break;
5256 case 0x079: /* VIS I fsrc2s */
64a88d5d 5257 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5258 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5259 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5260 break;
e9ebed4d 5261 case 0x07a: /* VIS I fornot1 */
64a88d5d 5262 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5263 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 5264 break;
5265 case 0x07b: /* VIS I fornot1s */
64a88d5d 5266 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5267 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 5268 break;
5269 case 0x07c: /* VIS I for */
64a88d5d 5270 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5271 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 5272 break;
5273 case 0x07d: /* VIS I fors */
64a88d5d 5274 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5275 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 5276 break;
3299908c 5277 case 0x07e: /* VIS I fone */
64a88d5d 5278 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5279 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5280 tcg_gen_movi_i64(cpu_dst_64, -1);
5281 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5282 break;
5283 case 0x07f: /* VIS I fones */
64a88d5d 5284 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5285 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5286 tcg_gen_movi_i32(cpu_dst_32, -1);
5287 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5288 break;
e9ebed4d
BS		 5289 case 0x080: /* VIS I shutdown */
5290 case 0x081: /* VIS II siam */
5291 // XXX
5292 goto illegal_insn;
3299908c
BS		 5293 default:
5294 goto illegal_insn;
5295 }
fcc72045 5296#endif
0f8a249a 5297 } else {
8f75b8a4 5298 goto illegal_insn; /* in decodetree */
cf495bcf 5299 }
0f8a249a
BS		 5300 }
5301 break;
5302 case 3: /* load/store instructions */
5303 {
5304 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 5305 /* ??? gen_address_mask prevents us from using a source
5306 register directly. Always generate a temporary. */
52123f14 5307 TCGv cpu_addr = tcg_temp_new();
9322a4bf 5308
5e6ed439
RH		 5309 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5310 if (xop == 0x3c || xop == 0x3e) {
5311 /* V9 casa/casxa : no offset */
71817e48 5312 } else if (IS_IMM) { /* immediate */
67526b20 5313 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 5314 if (simm != 0) {
5315 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5316 }
0f8a249a
BS		 5317 } else { /* register */
5318 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5319 if (rs2 != 0) {
5e6ed439 5320 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 5321 }
0f8a249a 5322 }
2f2ecb83
BS		 5323 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5324 (xop > 0x17 && xop <= 0x1d ) ||
5325 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 5326 TCGv cpu_val = gen_dest_gpr(dc, rd);
5327
0f8a249a 5328 switch (xop) {
b89e94af 5329 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 5330 gen_address_mask(dc, cpu_addr);
08149118 5331 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5332 dc->mem_idx, MO_TEUL | MO_ALIGN);
0f8a249a 5333 break;
b89e94af 5334 case 0x1: /* ldub, load unsigned byte */
2cade6a3 5335 gen_address_mask(dc, cpu_addr);
08149118
RH		 5336 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
5337 dc->mem_idx, MO_UB);
0f8a249a 5338 break;
b89e94af 5339 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 5340 gen_address_mask(dc, cpu_addr);
08149118 5341 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5342 dc->mem_idx, MO_TEUW | MO_ALIGN);
0f8a249a 5343 break;
b89e94af 5344 case 0x3: /* ldd, load double word */
0f8a249a 5345 if (rd & 1)
d4218d99 5346 goto illegal_insn;
1a2fb1c0 5347 else {
abcc7191 5348 TCGv_i64 t64;
2ea815ca 5349
2cade6a3 5350 gen_address_mask(dc, cpu_addr);
abcc7191 5351 t64 = tcg_temp_new_i64();
08149118 5352 tcg_gen_qemu_ld_i64(t64, cpu_addr,
316b6783 5353 dc->mem_idx, MO_TEUQ | MO_ALIGN);
de9e9d9f
RH		 5354 tcg_gen_trunc_i64_tl(cpu_val, t64);
5355 tcg_gen_ext32u_tl(cpu_val, cpu_val);
5356 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 5357 tcg_gen_shri_i64(t64, t64, 32);
5358 tcg_gen_trunc_i64_tl(cpu_val, t64);
de9e9d9f 5359 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 5360 }
0f8a249a 5361 break;
b89e94af 5362 case 0x9: /* ldsb, load signed byte */
2cade6a3 5363 gen_address_mask(dc, cpu_addr);
08149118 5364 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB);
0f8a249a 5365 break;
b89e94af 5366 case 0xa: /* ldsh, load signed halfword */
2cade6a3 5367 gen_address_mask(dc, cpu_addr);
08149118 5368 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5369 dc->mem_idx, MO_TESW | MO_ALIGN);
0f8a249a 5370 break;
fbb4bbb6
RH		 5371 case 0xd: /* ldstub */
5372 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5373 break;
de9e9d9f
RH		 5374 case 0x0f:
5375 /* swap, swap register with memory. Also atomically */
4fb554bc
RH		 5376 cpu_src1 = gen_load_gpr(dc, rd);
5377 gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5378 dc->mem_idx, MO_TEUL);
0f8a249a 5379 break;
3475187d 5380#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5381 case 0x10: /* lda, V9 lduwa, load word alternate */
1d65b0f5 5382 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
0f8a249a 5383 break;
b89e94af 5384 case 0x11: /* lduba, load unsigned byte alternate */
1d65b0f5 5385 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
0f8a249a 5386 break;
b89e94af 5387 case 0x12: /* lduha, load unsigned halfword alternate */
1d65b0f5 5388 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
0f8a249a 5389 break;
b89e94af 5390 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 5391 if (rd & 1) {
d4218d99 5392 goto illegal_insn;
7ec1e5ea 5393 }
e4dc0052 5394 gen_ldda_asi(dc, cpu_addr, insn, rd);
db166940 5395 goto skip_move;
b89e94af 5396 case 0x19: /* ldsba, load signed byte alternate */
1d65b0f5 5397 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
0f8a249a 5398 break;
b89e94af 5399 case 0x1a: /* ldsha, load signed halfword alternate */
1d65b0f5 5400 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
0f8a249a
BS		 5401 break;
5402 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 5403 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 5404 break;
b89e94af 5405 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 5406 atomically */
06828032 5407 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 5408 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 5409 break;
3475187d
FB		 5410#endif
5411#ifdef TARGET_SPARC64
0f8a249a 5412 case 0x08: /* V9 ldsw */
2cade6a3 5413 gen_address_mask(dc, cpu_addr);
08149118 5414 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5415 dc->mem_idx, MO_TESL | MO_ALIGN);
0f8a249a
BS		 5416 break;
5417 case 0x0b: /* V9 ldx */
2cade6a3 5418 gen_address_mask(dc, cpu_addr);
08149118 5419 tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
316b6783 5420 dc->mem_idx, MO_TEUQ | MO_ALIGN);
0f8a249a
BS		 5421 break;
5422 case 0x18: /* V9 ldswa */
1d65b0f5 5423 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
0f8a249a
BS		 5424 break;
5425 case 0x1b: /* V9 ldxa */
fc313c64 5426 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
0f8a249a
BS		 5427 break;
5428 case 0x2d: /* V9 prefetch, no effect */
5429 goto skip_move;
5430 case 0x30: /* V9 ldfa */
5b12f1e8 5431 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5432 goto jmp_insn;
5433 }
22e70060 5434 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
f9c816c0 5435 gen_update_fprs_dirty(dc, rd);
81ad8ba2 5436 goto skip_move;
0f8a249a 5437 case 0x33: /* V9 lddfa */
5b12f1e8 5438 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5439 goto jmp_insn;
5440 }
22e70060 5441 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
f9c816c0 5442 gen_update_fprs_dirty(dc, DFPREG(rd));
81ad8ba2 5443 goto skip_move;
0f8a249a
BS		 5444 case 0x3d: /* V9 prefetcha, no effect */
5445 goto skip_move;
5446 case 0x32: /* V9 ldqfa */
64a88d5d 5447 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5448 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5449 goto jmp_insn;
5450 }
22e70060 5451 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
f9c816c0 5452 gen_update_fprs_dirty(dc, QFPREG(rd));
1f587329 5453 goto skip_move;
0f8a249a
BS		 5454#endif
5455 default:
5456 goto illegal_insn;
5457 }
97ea2859 5458 gen_store_gpr(dc, rd, cpu_val);
db166940 5459#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 5460 skip_move: ;
3475187d 5461#endif
0f8a249a 5462 } else if (xop >= 0x20 && xop < 0x24) {
5b12f1e8 5463 if (gen_trap_ifnofpu(dc)) {
a80dde08 5464 goto jmp_insn;
5b12f1e8 5465 }
0f8a249a 5466 switch (xop) {
b89e94af 5467 case 0x20: /* ldf, load fpreg */
2cade6a3 5468 gen_address_mask(dc, cpu_addr);
ba5f5179 5469 cpu_dst_32 = gen_dest_fpr_F(dc);
cb21b4da 5470 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
316b6783 5471 dc->mem_idx, MO_TEUL | MO_ALIGN);
208ae657 5472 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 5473 break;
3a3b925d
BS		 5474 case 0x21: /* ldfsr, V9 ldxfsr */
5475#ifdef TARGET_SPARC64
2cade6a3 5476 gen_address_mask(dc, cpu_addr);
3a3b925d 5477 if (rd == 1) {
abcc7191 5478 TCGv_i64 t64 = tcg_temp_new_i64();
cb21b4da 5479 tcg_gen_qemu_ld_i64(t64, cpu_addr,
316b6783 5480 dc->mem_idx, MO_TEUQ | MO_ALIGN);
ad75a51e 5481 gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, t64);
f8641947 5482 break;
fe987e23 5483 }
f8641947 5484#endif
36ab4623 5485 cpu_dst_32 = tcg_temp_new_i32();
cb21b4da 5486 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
316b6783 5487 dc->mem_idx, MO_TEUL | MO_ALIGN);
ad75a51e 5488 gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32);
0f8a249a 5489 break;
b89e94af 5490 case 0x22: /* ldqf, load quad fpreg */
f939ffe5
RH		 5491 CHECK_FPU_FEATURE(dc, FLOAT128);
5492 gen_address_mask(dc, cpu_addr);
5493 cpu_src1_64 = tcg_temp_new_i64();
cb21b4da 5494 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
fc313c64 5495 MO_TEUQ | MO_ALIGN_4);
f939ffe5
RH		 5496 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5497 cpu_src2_64 = tcg_temp_new_i64();
cb21b4da 5498 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
fc313c64 5499 MO_TEUQ | MO_ALIGN_4);
f939ffe5 5500 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
1f587329 5501 break;
b89e94af 5502 case 0x23: /* lddf, load double fpreg */
03fb8cfc 5503 gen_address_mask(dc, cpu_addr);
3886b8a3 5504 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
cb21b4da 5505 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
fc313c64 5506 MO_TEUQ | MO_ALIGN_4);
03fb8cfc 5507 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 5508 break;
5509 default:
5510 goto illegal_insn;
5511 }
dc1a6971 5512 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 5513 xop == 0xe || xop == 0x1e) {
81634eea
RH		 5514 TCGv cpu_val = gen_load_gpr(dc, rd);
5515
0f8a249a 5516 switch (xop) {
b89e94af 5517 case 0x4: /* st, store word */
2cade6a3 5518 gen_address_mask(dc, cpu_addr);
08149118 5519 tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
316b6783 5520 dc->mem_idx, MO_TEUL | MO_ALIGN);
0f8a249a 5521 break;
b89e94af 5522 case 0x5: /* stb, store byte */
2cade6a3 5523 gen_address_mask(dc, cpu_addr);
08149118 5524 tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB);
0f8a249a 5525 break;
b89e94af 5526 case 0x6: /* sth, store halfword */
2cade6a3 5527 gen_address_mask(dc, cpu_addr);
08149118 5528 tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
316b6783 5529 dc->mem_idx, MO_TEUW | MO_ALIGN);
0f8a249a 5530 break;
b89e94af 5531 case 0x7: /* std, store double word */
0f8a249a 5532 if (rd & 1)
d4218d99 5533 goto illegal_insn;
1a2fb1c0 5534 else {
abcc7191 5535 TCGv_i64 t64;
81634eea 5536 TCGv lo;
1a2fb1c0 5537
2cade6a3 5538 gen_address_mask(dc, cpu_addr);
81634eea 5539 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5540 t64 = tcg_temp_new_i64();
5541 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
08149118 5542 tcg_gen_qemu_st_i64(t64, cpu_addr,
316b6783 5543 dc->mem_idx, MO_TEUQ | MO_ALIGN);
7fa76c0b 5544 }
0f8a249a 5545 break;
3475187d 5546#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5547 case 0x14: /* sta, V9 stwa, store word alternate */
1d65b0f5 5548 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
d39c0b99 5549 break;
b89e94af 5550 case 0x15: /* stba, store byte alternate */
1d65b0f5 5551 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
d39c0b99 5552 break;
b89e94af 5553 case 0x16: /* stha, store halfword alternate */
1d65b0f5 5554 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
d39c0b99 5555 break;
b89e94af 5556 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5557 if (rd & 1) {
0f8a249a 5558 goto illegal_insn;
1a2fb1c0 5559 }
7ec1e5ea 5560 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5561 break;
e80cfcfc 5562#endif
3475187d 5563#ifdef TARGET_SPARC64
0f8a249a 5564 case 0x0e: /* V9 stx */
2cade6a3 5565 gen_address_mask(dc, cpu_addr);
08149118 5566 tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
316b6783 5567 dc->mem_idx, MO_TEUQ | MO_ALIGN);
0f8a249a
BS		 5568 break;
5569 case 0x1e: /* V9 stxa */
fc313c64 5570 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
0f8a249a 5571 break;
3475187d 5572#endif
0f8a249a
BS		 5573 default:
5574 goto illegal_insn;
5575 }
5576 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5577 if (gen_trap_ifnofpu(dc)) {
a80dde08 5578 goto jmp_insn;
5b12f1e8 5579 }
0f8a249a 5580 switch (xop) {
b89e94af 5581 case 0x24: /* stf, store fpreg */
cb21b4da
RH		 5582 gen_address_mask(dc, cpu_addr);
5583 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5584 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
316b6783 5585 dc->mem_idx, MO_TEUL | MO_ALIGN);
0f8a249a
BS		 5586 break;
5587 case 0x25: /* stfsr, V9 stxfsr */
f8641947 5588 {
3a3b925d 5589#ifdef TARGET_SPARC64
f8641947
RH		 5590 gen_address_mask(dc, cpu_addr);
5591 if (rd == 1) {
08149118 5592 tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
316b6783 5593 dc->mem_idx, MO_TEUQ | MO_ALIGN);
f8641947
RH		 5594 break;
5595 }
3a3b925d 5596#endif
08149118 5597 tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
316b6783 5598 dc->mem_idx, MO_TEUL | MO_ALIGN);
f8641947 5599 }
0f8a249a 5600 break;
1f587329
BS		 5601 case 0x26:
5602#ifdef TARGET_SPARC64
1f587329 5603 /* V9 stqf, store quad fpreg */
f939ffe5
RH		 5604 CHECK_FPU_FEATURE(dc, FLOAT128);
5605 gen_address_mask(dc, cpu_addr);
5606 /* ??? While stqf only requires 4-byte alignment, it is
5607 legal for the cpu to signal the unaligned exception.
5608 The OS trap handler is then required to fix it up.
5609 For qemu, this avoids having to probe the second page
5610 before performing the first write. */
5611 cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5612 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
fc313c64 5613 dc->mem_idx, MO_TEUQ | MO_ALIGN_16);
f939ffe5
RH		 5614 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5615 cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5616 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
fc313c64 5617 dc->mem_idx, MO_TEUQ);
1f587329 5618 break;
1f587329
BS		 5619#else /* !TARGET_SPARC64 */
5620 /* stdfq, store floating point queue */
5621#if defined(CONFIG_USER_ONLY)
5622 goto illegal_insn;
5623#else
0f8a249a
BS		 5624 if (!supervisor(dc))
5625 goto priv_insn;
5b12f1e8 5626 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5627 goto jmp_insn;
5b12f1e8 5628 }
0f8a249a 5629 goto nfq_insn;
1f587329 5630#endif
0f8a249a 5631#endif
b89e94af 5632 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5633 gen_address_mask(dc, cpu_addr);
5634 cpu_src1_64 = gen_load_fpr_D(dc, rd);
cb21b4da 5635 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
fc313c64 5636 MO_TEUQ | MO_ALIGN_4);
0f8a249a
BS		 5637 break;
5638 default:
5639 goto illegal_insn;
5640 }
5641 } else if (xop > 0x33 && xop < 0x3f) {
5642 switch (xop) {
a4d17f19 5643#ifdef TARGET_SPARC64
0f8a249a 5644 case 0x34: /* V9 stfa */
5b12f1e8 5645 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5646 goto jmp_insn;
5647 }
22e70060 5648 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5649 break;
1f587329 5650 case 0x36: /* V9 stqfa */
2ea815ca 5651 {
2ea815ca 5652 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5653 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5654 goto jmp_insn;
5655 }
22e70060 5656 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5657 }
1f587329 5658 break;
0f8a249a 5659 case 0x37: /* V9 stdfa */
5b12f1e8 5660 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5661 goto jmp_insn;
5662 }
22e70060 5663 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5664 break;
0f8a249a 5665 case 0x3e: /* V9 casxa */
a4273524
RH		 5666 rs2 = GET_FIELD(insn, 27, 31);
5667 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5668 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5669 break;
16c358e9
SH		 5670#endif
5671#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5672 case 0x3c: /* V9 or LEON3 casa */
5673#ifndef TARGET_SPARC64
5674 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5675#endif
5676 rs2 = GET_FIELD(insn, 27, 31);
5677 cpu_src2 = gen_load_gpr(dc, rs2);
5678 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5679 break;
0f8a249a
BS		 5680#endif
5681 default:
5682 goto illegal_insn;
5683 }
a4273524 5684 } else {
0f8a249a 5685 goto illegal_insn;
a4273524 5686 }
0f8a249a
BS		 5687 }
5688 break;
cf495bcf 5689 }
878cc677 5690 advance_pc(dc);
e80cfcfc 5691 jmp_insn:
a6ca81cb 5692 return;
cf495bcf 5693 illegal_insn:
4fbe0067 5694 gen_exception(dc, TT_ILL_INSN);
a6ca81cb 5695 return;
8f75b8a4 5696#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
e8af50a3 5697 priv_insn:
4fbe0067 5698 gen_exception(dc, TT_PRIV_INSN);
a6ca81cb 5699 return;
64a88d5d 5700#endif
e80cfcfc 5701 nfpu_insn:
4fbe0067 5702 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
a6ca81cb 5703 return;
64a88d5d 5704#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5705 nfq_insn:
4fbe0067 5706 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
a6ca81cb 5707 return;
9143e598 5708#endif
7a3f1944
FB		 5709}
5710
6e61bc94 5711static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7a3f1944 5712{
6e61bc94 5713 DisasContext *dc = container_of(dcbase, DisasContext, base);
b77af26e 5714 CPUSPARCState *env = cpu_env(cs);
6e61bc94 5715 int bound;
af00be49
EC		 5716
5717 dc->pc = dc->base.pc_first;
6e61bc94 5718 dc->npc = (target_ulong)dc->base.tb->cs_base;
8393617c 5719 dc->cc_op = CC_OP_DYNAMIC;
6e61bc94 5720 dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
576e1c4c 5721 dc->def = &env->def;
6e61bc94
EC		 5722 dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
5723 dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
c9b459aa 5724#ifndef CONFIG_USER_ONLY
6e61bc94 5725 dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
c9b459aa 5726#endif
a6d567e5 5727#ifdef TARGET_SPARC64
f9c816c0 5728 dc->fprs_dirty = 0;
6e61bc94 5729 dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
c9b459aa 5730#ifndef CONFIG_USER_ONLY
6e61bc94 5731 dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
c9b459aa 5732#endif
a6d567e5 5733#endif
6e61bc94
EC		 5734 /*
5735 * if we reach a page boundary, we stop generation so that the
5736 * PC of a TT_TFAULT exception is always in the right page
5737 */
5738 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
5739 dc->base.max_insns = MIN(dc->base.max_insns, bound);
5740}
cf495bcf 5741
6e61bc94
EC		 5742static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
5743{
5744}
190ce7fb 5745
6e61bc94
EC		 5746static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
5747{
5748 DisasContext *dc = container_of(dcbase, DisasContext, base);
633c4283 5749 target_ulong npc = dc->npc;
667b8e29 5750
633c4283
RH		 5751 if (npc & 3) {
5752 switch (npc) {
5753 case JUMP_PC:
5754 assert(dc->jump_pc[1] == dc->pc + 4);
5755 npc = dc->jump_pc[0] | JUMP_PC;
5756 break;
5757 case DYNAMIC_PC:
5758 case DYNAMIC_PC_LOOKUP:
5759 npc = DYNAMIC_PC;
5760 break;
5761 default:
5762 g_assert_not_reached();
5763 }
6e61bc94 5764 }
633c4283 5765 tcg_gen_insn_start(dc->pc, npc);
6e61bc94 5766}
b933066a 5767
6e61bc94
EC		 5768static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
5769{
5770 DisasContext *dc = container_of(dcbase, DisasContext, base);
b77af26e 5771 CPUSPARCState *env = cpu_env(cs);
6e61bc94 5772 unsigned int insn;
0f8a249a 5773
4e116893 5774 insn = translator_ldl(env, &dc->base, dc->pc);
6e61bc94 5775 dc->base.pc_next += 4;
878cc677
RH		 5776
5777 if (!decode(dc, insn)) {
5778 disas_sparc_legacy(dc, insn);
5779 }
e80cfcfc 5780
6e61bc94
EC		 5781 if (dc->base.is_jmp == DISAS_NORETURN) {
5782 return;
5783 }
5784 if (dc->pc != dc->base.pc_next) {
5785 dc->base.is_jmp = DISAS_TOO_MANY;
b09b2fd3 5786 }
6e61bc94
EC		 5787}
5788
5789static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
5790{
5791 DisasContext *dc = container_of(dcbase, DisasContext, base);
186e7890 5792 DisasDelayException *e, *e_next;
633c4283 5793 bool may_lookup;
6e61bc94 5794
46bb0137
MCA		 5795 switch (dc->base.is_jmp) {
5796 case DISAS_NEXT:
5797 case DISAS_TOO_MANY:
633c4283 5798 if (((dc->pc | dc->npc) & 3) == 0) {
72cbca10 5799 /* static PC and NPC: we can use direct chaining */
2f5680ee 5800 gen_goto_tb(dc, 0, dc->pc, dc->npc);
633c4283
RH		 5801 break;
5802 }
5803
930f1865 5804 may_lookup = true;
633c4283
RH		 5805 if (dc->pc & 3) {
5806 switch (dc->pc) {
5807 case DYNAMIC_PC_LOOKUP:
633c4283
RH		 5808 break;
5809 case DYNAMIC_PC:
5810 may_lookup = false;
5811 break;
5812 default:
5813 g_assert_not_reached();
b09b2fd3 5814 }
633c4283
RH		 5815 } else {
5816 tcg_gen_movi_tl(cpu_pc, dc->pc);
633c4283
RH		 5817 }
5818
930f1865
RH		 5819 if (dc->npc & 3) {
5820 switch (dc->npc) {
5821 case JUMP_PC:
5822 gen_generic_branch(dc);
5823 break;
5824 case DYNAMIC_PC:
5825 may_lookup = false;
5826 break;
5827 case DYNAMIC_PC_LOOKUP:
5828 break;
5829 default:
5830 g_assert_not_reached();
5831 }
5832 } else {
5833 tcg_gen_movi_tl(cpu_npc, dc->npc);
5834 }
633c4283
RH		 5835 if (may_lookup) {
5836 tcg_gen_lookup_and_goto_ptr();
5837 } else {
07ea28b4 5838 tcg_gen_exit_tb(NULL, 0);
72cbca10 5839 }
46bb0137
MCA		 5840 break;
5841
5842 case DISAS_NORETURN:
5843 break;
5844
5845 case DISAS_EXIT:
5846 /* Exit TB */
5847 save_state(dc);
5848 tcg_gen_exit_tb(NULL, 0);
5849 break;
5850
5851 default:
5852 g_assert_not_reached();
72cbca10 5853 }
186e7890
RH		 5854
5855 for (e = dc->delay_excp_list; e ; e = e_next) {
5856 gen_set_label(e->lab);
5857
5858 tcg_gen_movi_tl(cpu_pc, e->pc);
5859 if (e->npc % 4 == 0) {
5860 tcg_gen_movi_tl(cpu_npc, e->npc);
5861 }
5862 gen_helper_raise_exception(tcg_env, e->excp);
5863
5864 e_next = e->next;
5865 g_free(e);
5866 }
6e61bc94
EC		 5867}
5868
8eb806a7
RH		 5869static void sparc_tr_disas_log(const DisasContextBase *dcbase,
5870 CPUState *cpu, FILE *logfile)
6e61bc94 5871{
8eb806a7
RH		 5872 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
5873 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
6e61bc94
EC		 5874}
5875
5876static const TranslatorOps sparc_tr_ops = {
5877 .init_disas_context = sparc_tr_init_disas_context,
5878 .tb_start = sparc_tr_tb_start,
5879 .insn_start = sparc_tr_insn_start,
6e61bc94
EC		 5880 .translate_insn = sparc_tr_translate_insn,
5881 .tb_stop = sparc_tr_tb_stop,
5882 .disas_log = sparc_tr_disas_log,
5883};
5884
597f9b2d 5885void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
306c8721 5886 target_ulong pc, void *host_pc)
6e61bc94
EC		 5887{
5888 DisasContext dc = {};
5889
306c8721 5890 translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base);
7a3f1944
FB		 5891}
5892
55c3ceef 5893void sparc_tcg_init(void)
e80cfcfc 5894{
d2dc4069 5895 static const char gregnames[32][4] = {
0ea63844 5896 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5897 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5898 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5899 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5900 };
0ea63844 5901 static const char fregnames[32][4] = {
30038fd8
RH		 5902 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5903 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5904 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5905 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5906 };
aaed909a 5907
0ea63844 5908 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5909#ifdef TARGET_SPARC64
0ea63844 5910 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5911 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
0ea63844
RH		 5912#endif
5913 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5914 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5915 };
5916
5917 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5918#ifdef TARGET_SPARC64
5919 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
1a2fb1c0 5920#endif
0ea63844
RH		 5921 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5922 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5923 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5924 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5925 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5926 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5927 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5928 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
0ea63844 5929 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
0ea63844
RH		 5930 };
5931
5932 unsigned int i;
5933
ad75a51e 5934 cpu_regwptr = tcg_global_mem_new_ptr(tcg_env,
0ea63844
RH		 5935 offsetof(CPUSPARCState, regwptr),
5936 "regwptr");
5937
5938 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
ad75a51e 5939 *r32[i].ptr = tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i].name);
0ea63844
RH		 5940 }
5941
5942 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
ad75a51e 5943 *rtl[i].ptr = tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].name);
0ea63844
RH		 5944 }
5945
f764718d 5946 cpu_regs[0] = NULL;
0ea63844 5947 for (i = 1; i < 8; ++i) {
ad75a51e 5948 cpu_regs[i] = tcg_global_mem_new(tcg_env,
d2dc4069
RH		 5949 offsetof(CPUSPARCState, gregs[i]),
5950 gregnames[i]);
5951 }
5952
5953 for (i = 8; i < 32; ++i) {
5954 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5955 (i - 8) * sizeof(target_ulong),
5956 gregnames[i]);
0ea63844
RH		 5957 }
5958
5959 for (i = 0; i < TARGET_DPREGS; i++) {
ad75a51e 5960 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
0ea63844
RH		 5961 offsetof(CPUSPARCState, fpr[i]),
5962 fregnames[i]);
1a2fb1c0 5963 }
658138bc 5964}
d2856f1a 5965
f36aaa53
RH		 5966void sparc_restore_state_to_opc(CPUState *cs,
5967 const TranslationBlock *tb,
5968 const uint64_t *data)
d2856f1a 5969{
f36aaa53
RH		 5970 SPARCCPU *cpu = SPARC_CPU(cs);
5971 CPUSPARCState *env = &cpu->env;
bad729e2
RH		 5972 target_ulong pc = data[0];
5973 target_ulong npc = data[1];
5974
5975 env->pc = pc;
6c42444f 5976 if (npc == DYNAMIC_PC) {
d2856f1a 5977 /* dynamic NPC: already stored */
6c42444f 5978 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5979 /* jump PC: use 'cond' and the jump targets of the translation */
5980 if (env->cond) {
6c42444f 5981 env->npc = npc & ~3;
d7da2a10 5982 } else {
6c42444f 5983 env->npc = pc + 4;
d7da2a10 5984 }
d2856f1a
AJ		 5985 } else {
5986 env->npc = npc;
5987 }
5988}
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