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Merge tag 'kvm-arm-for-4.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git...
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
d91cab78 676 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 677 return 1;
d91cab78 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
d91cab78 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
d91cab78
DH		 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 692 return 1;
693
d91cab78
DH		 694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 696 return 1;
d91cab78 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 698 return 1;
699 }
42bdf991 700 kvm_put_guest_xcr0(vcpu);
2acf923e 701 vcpu->arch.xcr0 = xcr0;
56c103ec 702
d91cab78 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 704 kvm_update_cpuid(vcpu);
2acf923e
DC		 705 return 0;
706}
707
708int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709{
764bcbc5
Z		 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 712 kvm_inject_gp(vcpu, 0);
713 return 1;
714 }
715 return 0;
716}
717EXPORT_SYMBOL_GPL(kvm_set_xcr);
718
a83b29c6 719int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 720{
fc78f519 721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
724
0f12244f
GN		 725 if (cr4 & CR4_RESERVED_BITS)
726 return 1;
a03490ed 727
2acf923e
DC		 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 return 1;
730
c68b734f
YW		 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 return 1;
733
97ec8c06
FW		 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 return 1;
736
afcbf13f 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 738 return 1;
739
a03490ed 740 if (is_long_mode(vcpu)) {
0f12244f
GN		 741 if (!(cr4 & X86_CR4_PAE))
742 return 1;
a2edf57f
AK		 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 kvm_read_cr3(vcpu)))
0f12244f
GN		 747 return 1;
748
ad756a16
MJ		 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
751 return 1;
752
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 return 1;
756 }
757
5e1746d6 758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 759 return 1;
a03490ed 760
ad756a16
MJ		 761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 763 kvm_mmu_reset_context(vcpu);
0f12244f 764
2acf923e 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 766 kvm_update_cpuid(vcpu);
2acf923e 767
0f12244f
GN		 768 return 0;
769}
2d3ad1f4 770EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 771
2390218b 772int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 773{
ac146235 774#ifdef CONFIG_X86_64
9d88fca7 775 cr3 &= ~CR3_PCID_INVD;
ac146235 776#endif
9d88fca7 777
9f8fe504 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 779 kvm_mmu_sync_roots(vcpu);
77c3913b 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 781 return 0;
d835dfec
AK		 782 }
783
a03490ed 784 if (is_long_mode(vcpu)) {
d9f89b88
JK		 785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 return 1;
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 789 return 1;
a03490ed 790
0f12244f 791 vcpu->arch.cr3 = cr3;
aff48baa 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 793 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 797
eea1cff9 798int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 799{
0f12244f
GN		 800 if (cr8 & CR8_RESERVED_BITS)
801 return 1;
35754c98 802 if (lapic_in_kernel(vcpu))
a03490ed
CO		 803 kvm_lapic_set_tpr(vcpu, cr8);
804 else
ad312c7c 805 vcpu->arch.cr8 = cr8;
0f12244f
GN		 806 return 0;
807}
2d3ad1f4 808EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 809
2d3ad1f4 810unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 811{
35754c98 812 if (lapic_in_kernel(vcpu))
a03490ed
CO		 813 return kvm_lapic_get_cr8(vcpu);
814 else
ad312c7c 815 return vcpu->arch.cr8;
a03490ed 816}
2d3ad1f4 817EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 818
ae561ede
NA		 819static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820{
821 int i;
822
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 }
828}
829
73aaf249
JK		 830static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831{
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834}
835
c8639010
JK		 836static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837{
838 unsigned long dr7;
839
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
842 else
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 848}
849
6f43ed01
NA		 850static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851{
852 u64 fixed = DR6_FIXED_1;
853
854 if (!guest_cpuid_has_rtm(vcpu))
855 fixed |= DR6_RTM;
856 return fixed;
857}
858
338dbc97 859static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 860{
861 switch (dr) {
862 case 0 ... 3:
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
866 break;
867 case 4:
020df079
GN		 868 /* fall through */
869 case 6:
338dbc97
GN		 870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
6f43ed01 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 873 kvm_update_dr6(vcpu);
020df079
GN		 874 break;
875 case 5:
020df079
GN		 876 /* fall through */
877 default: /* 7 */
338dbc97
GN		 878 if (val & 0xffffffff00000000ULL)
879 return -1; /* #GP */
020df079 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 881 kvm_update_dr7(vcpu);
020df079
GN		 882 break;
883 }
884
885 return 0;
886}
338dbc97
GN		 887
888int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889{
16f8a6f9 890 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 891 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 892 return 1;
893 }
894 return 0;
338dbc97 895}
020df079
GN		 896EXPORT_SYMBOL_GPL(kvm_set_dr);
897
16f8a6f9 898int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 899{
900 switch (dr) {
901 case 0 ... 3:
902 *val = vcpu->arch.db[dr];
903 break;
904 case 4:
020df079
GN		 905 /* fall through */
906 case 6:
73aaf249
JK		 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
909 else
910 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 911 break;
912 case 5:
020df079
GN		 913 /* fall through */
914 default: /* 7 */
915 *val = vcpu->arch.dr7;
916 break;
917 }
338dbc97
GN		 918 return 0;
919}
020df079
GN		 920EXPORT_SYMBOL_GPL(kvm_get_dr);
921
022cd0e8
AK		 922bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923{
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 u64 data;
926 int err;
927
c6702c9d 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 929 if (err)
930 return err;
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 return err;
934}
935EXPORT_SYMBOL_GPL(kvm_rdpmc);
936
043405e1
CO		 937/*
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940 *
941 * This list is modified at module load time to reflect the
e3267cbb 942 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
043405e1 945 */
e3267cbb 946
043405e1
CO		 947static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 949 MSR_STAR,
043405e1
CO		 950#ifdef CONFIG_X86_64
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952#endif
b3897a49 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 955};
956
957static unsigned num_msrs_to_save;
958
62ef68bb
PB		 959static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 966 HV_X64_MSR_RESET,
11c4b1ca 967 HV_X64_MSR_VP_INDEX,
9eec50b8 968 HV_X64_MSR_VP_RUNTIME,
5c919412 969 HV_X64_MSR_SCONTROL,
1f4b34f8 970 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 971 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
972 MSR_KVM_PV_EOI_EN,
973
ba904635 974 MSR_IA32_TSC_ADJUST,
a3e06bbe 975 MSR_IA32_TSCDEADLINE,
043405e1 976 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 977 MSR_IA32_MCG_STATUS,
978 MSR_IA32_MCG_CTL,
64d60670 979 MSR_IA32_SMBASE,
043405e1
CO		 980};
981
62ef68bb
PB		 982static unsigned num_emulated_msrs;
983
384bb783 984bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 985{
b69e8cae 986 if (efer & efer_reserved_bits)
384bb783 987 return false;
15c4a640 988
1b2fd70c
AG		 989 if (efer & EFER_FFXSR) {
990 struct kvm_cpuid_entry2 *feat;
991
992 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 993 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 994 return false;
1b2fd70c
AG		 995 }
996
d8017474
AG		 997 if (efer & EFER_SVME) {
998 struct kvm_cpuid_entry2 *feat;
999
1000 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1001 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1002 return false;
d8017474
AG		 1003 }
1004
384bb783
JK		 1005 return true;
1006}
1007EXPORT_SYMBOL_GPL(kvm_valid_efer);
1008
1009static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1010{
1011 u64 old_efer = vcpu->arch.efer;
1012
1013 if (!kvm_valid_efer(vcpu, efer))
1014 return 1;
1015
1016 if (is_paging(vcpu)
1017 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1018 return 1;
1019
15c4a640 1020 efer &= ~EFER_LMA;
f6801dff 1021 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1022
a3d204e2
SY		 1023 kvm_x86_ops->set_efer(vcpu, efer);
1024
aad82703
SY		 1025 /* Update reserved bits */
1026 if ((efer ^ old_efer) & EFER_NX)
1027 kvm_mmu_reset_context(vcpu);
1028
b69e8cae 1029 return 0;
15c4a640
CO		 1030}
1031
f2b4b7dd
JR		 1032void kvm_enable_efer_bits(u64 mask)
1033{
1034 efer_reserved_bits &= ~mask;
1035}
1036EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1037
15c4a640
CO		 1038/*
1039 * Writes msr value into into the appropriate "register".
1040 * Returns 0 on success, non-0 otherwise.
1041 * Assumes vcpu_load() was already called.
1042 */
8fe8ab46 1043int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1044{
854e8bb1
NA		 1045 switch (msr->index) {
1046 case MSR_FS_BASE:
1047 case MSR_GS_BASE:
1048 case MSR_KERNEL_GS_BASE:
1049 case MSR_CSTAR:
1050 case MSR_LSTAR:
1051 if (is_noncanonical_address(msr->data))
1052 return 1;
1053 break;
1054 case MSR_IA32_SYSENTER_EIP:
1055 case MSR_IA32_SYSENTER_ESP:
1056 /*
1057 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1058 * non-canonical address is written on Intel but not on
1059 * AMD (which ignores the top 32-bits, because it does
1060 * not implement 64-bit SYSENTER).
1061 *
1062 * 64-bit code should hence be able to write a non-canonical
1063 * value on AMD. Making the address canonical ensures that
1064 * vmentry does not fail on Intel after writing a non-canonical
1065 * value, and that something deterministic happens if the guest
1066 * invokes 64-bit SYSENTER.
1067 */
1068 msr->data = get_canonical(msr->data);
1069 }
8fe8ab46 1070 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1071}
854e8bb1 1072EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1073
313a3dc7
CO		 1074/*
1075 * Adapt set_msr() to msr_io()'s calling convention
1076 */
609e36d3
PB		 1077static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1078{
1079 struct msr_data msr;
1080 int r;
1081
1082 msr.index = index;
1083 msr.host_initiated = true;
1084 r = kvm_get_msr(vcpu, &msr);
1085 if (r)
1086 return r;
1087
1088 *data = msr.data;
1089 return 0;
1090}
1091
313a3dc7
CO		 1092static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1093{
8fe8ab46
WA		 1094 struct msr_data msr;
1095
1096 msr.data = *data;
1097 msr.index = index;
1098 msr.host_initiated = true;
1099 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1100}
1101
16e8d74d
MT		 1102#ifdef CONFIG_X86_64
1103struct pvclock_gtod_data {
1104 seqcount_t seq;
1105
1106 struct { /* extract of a clocksource struct */
1107 int vclock_mode;
1108 cycle_t cycle_last;
1109 cycle_t mask;
1110 u32 mult;
1111 u32 shift;
1112 } clock;
1113
cbcf2dd3
TG		 1114 u64 boot_ns;
1115 u64 nsec_base;
16e8d74d
MT		 1116};
1117
1118static struct pvclock_gtod_data pvclock_gtod_data;
1119
1120static void update_pvclock_gtod(struct timekeeper *tk)
1121{
1122 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1123 u64 boot_ns;
1124
876e7881 1125 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1126
1127 write_seqcount_begin(&vdata->seq);
1128
1129 /* copy pvclock gtod data */
876e7881
PZ		 1130 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1131 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1132 vdata->clock.mask = tk->tkr_mono.mask;
1133 vdata->clock.mult = tk->tkr_mono.mult;
1134 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1135
cbcf2dd3 1136 vdata->boot_ns = boot_ns;
876e7881 1137 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1138
1139 write_seqcount_end(&vdata->seq);
1140}
1141#endif
1142
bab5bb39
NK		 1143void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1144{
1145 /*
1146 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1147 * vcpu_enter_guest. This function is only called from
1148 * the physical CPU that is running vcpu.
1149 */
1150 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1151}
16e8d74d 1152
18068523
GOC		 1153static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1154{
9ed3c444
AK		 1155 int version;
1156 int r;
50d0a0f9 1157 struct pvclock_wall_clock wc;
923de3cf 1158 struct timespec boot;
18068523
GOC		 1159
1160 if (!wall_clock)
1161 return;
1162
9ed3c444
AK		 1163 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1164 if (r)
1165 return;
1166
1167 if (version & 1)
1168 ++version; /* first time write, random junk */
1169
1170 ++version;
18068523 1171
1dab1345
NK		 1172 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1173 return;
18068523 1174
50d0a0f9
GH		 1175 /*
1176 * The guest calculates current wall clock time by adding
34c238a1 1177 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1178 * wall clock specified here. guest system time equals host
1179 * system time for us, thus we must fill in host boot time here.
1180 */
923de3cf 1181 getboottime(&boot);
50d0a0f9 1182
4b648665
BR		 1183 if (kvm->arch.kvmclock_offset) {
1184 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1185 boot = timespec_sub(boot, ts);
1186 }
50d0a0f9
GH		 1187 wc.sec = boot.tv_sec;
1188 wc.nsec = boot.tv_nsec;
1189 wc.version = version;
18068523
GOC		 1190
1191 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1192
1193 version++;
1194 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1195}
1196
50d0a0f9
GH		 1197static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1198{
1199 uint32_t quotient, remainder;
1200
1201 /* Don't try to replace with do_div(), this one calculates
1202 * "(dividend << 32) / divisor" */
1203 __asm__ ( "divl %4"
1204 : "=a" (quotient), "=d" (remainder)
1205 : "0" (0), "1" (dividend), "r" (divisor) );
1206 return quotient;
1207}
1208
5f4e3f88
ZA		 1209static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1210 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1211{
5f4e3f88 1212 uint64_t scaled64;
50d0a0f9
GH		 1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
5f4e3f88
ZA		 1217 tps64 = base_khz * 1000LL;
1218 scaled64 = scaled_khz * 1000LL;
50933623 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
50933623
JK		 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
50d0a0f9
GH		 1230 shift++;
1231 }
1232
5f4e3f88
ZA		 1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1235
5f4e3f88
ZA		 1236 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1237 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1238}
1239
d828199e 1240#ifdef CONFIG_X86_64
16e8d74d 1241static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1242#endif
16e8d74d 1243
c8076604 1244static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1245static unsigned long max_tsc_khz;
c8076604 1246
cc578287 1247static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1248{
cc578287
ZA		 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1251}
1252
cc578287 1253static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1254{
cc578287
ZA		 1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1e993611
JR		 1258}
1259
381d585c
HZ		 1260static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261{
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294}
1295
1296static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1297{
cc578287
ZA		 1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
217fc9cf 1300
03ba32ca 1301 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1302 if (this_tsc_khz == 0) {
1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1305 return -1;
ad721883 1306 }
03ba32ca 1307
c285545f
ZA		 1308 /* Compute a scale to convert nanoseconds in TSC cycles */
1309 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
1312 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1322 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1324 use_scaling = 1;
1325 }
381d585c 1326 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1327}
1328
1329static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330{
e26101b1 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
e26101b1 1334 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1335 return tsc;
1336}
1337
69b0049a 1338static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1339{
1340#ifdef CONFIG_X86_64
1341 bool vcpus_matched;
b48aa97e
MT		 1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
7f187922
MT		 1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363#endif
1364}
1365
ba904635
WA		 1366static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367{
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370}
1371
35181e86
HZ		 1372/*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383{
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385}
1386
1387u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388{
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396}
1397EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
07c1419a
HZ		 1399static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400{
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406}
1407
4ba76538
HZ		 1408u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409{
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411}
1412EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
8fe8ab46 1414void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1415{
1416 struct kvm *kvm = vcpu->kvm;
f38e098f 1417 u64 offset, ns, elapsed;
99e3e30a 1418 unsigned long flags;
02626b6a 1419 s64 usdiff;
b48aa97e 1420 bool matched;
0d3da0d2 1421 bool already_matched;
8fe8ab46 1422 u64 data = msr->data;
99e3e30a 1423
038f8c11 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1425 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1426 ns = get_kernel_ns();
f38e098f 1427 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1428
03ba32ca 1429 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1430 int faulted = 0;
1431
03ba32ca
MT		 1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1434#ifdef CONFIG_X86_64
03ba32ca 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1436#else
03ba32ca 1437 /* do_div() only does unsigned */
8915aa27
MT		 1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
5d3cb0f6 1452#endif
03ba32ca
MT		 1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
8915aa27
MT		 1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1463
1464 /*
5d3cb0f6
ZA		 1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
02626b6a 1474 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1476 if (!check_tsc_unstable()) {
e26101b1 1477 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
857e4099 1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1481 data += delta;
07c1419a 1482 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1484 }
b48aa97e 1485 matched = true;
0d3da0d2 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
4a969980 1493 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1501 matched = false;
0d3da0d2 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1503 kvm->arch.cur_tsc_generation, data);
f38e098f 1504 }
e26101b1
ZA		 1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
f38e098f
ZA		 1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
5d3cb0f6 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1513
b183aa58 1514 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
ba904635
WA		 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1527 if (!matched) {
b48aa97e 1528 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
b48aa97e
MT		 1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1535}
e26101b1 1536
99e3e30a
ZA		 1537EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
58ea6767
HZ		 1539static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541{
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543}
1544
1545static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546{
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
d828199e
MT		 1553#ifdef CONFIG_X86_64
1554
1555static cycle_t read_tsc(void)
1556{
03b9730b
AL		 1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a funciton of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573}
1574
1575static inline u64 vgettsc(cycle_t *cycle_now)
1576{
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584}
1585
cbcf2dd3 1586static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1587{
cbcf2dd3 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1589 unsigned long seq;
d828199e 1590 int mode;
cbcf2dd3 1591 u64 ns;
d828199e 1592
d828199e
MT		 1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
cbcf2dd3 1596 ns = gtod->nsec_base;
d828199e
MT		 1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
cbcf2dd3 1599 ns += gtod->boot_ns;
d828199e 1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1601 *t = ns;
d828199e
MT		 1602
1603 return mode;
1604}
1605
1606/* returns true if host is using tsc clocksource */
1607static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608{
d828199e
MT		 1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
cbcf2dd3 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1614}
1615#endif
1616
1617/*
1618 *
b48aa97e
MT		 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
d828199e
MT		 1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
b48aa97e 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1655 *
1656 */
1657
1658static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659{
1660#ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
b48aa97e
MT		 1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
b48aa97e 1672 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
16a96021 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1679
d828199e
MT		 1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
d828199e
MT		 1686#endif
1687}
1688
2860c4b1
PB		 1689void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690{
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692}
1693
2e762ff7
MT		 1694static void kvm_gen_update_masterclock(struct kvm *kvm)
1695{
1696#ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714#endif
1715}
1716
34c238a1 1717static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1718{
27cca94e 1719 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1720 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1721 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1722 s64 kernel_ns;
d828199e 1723 u64 tsc_timestamp, host_tsc;
0b79459b 1724 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1725 u8 pvclock_flags;
d828199e
MT		 1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
18068523 1730
d828199e
MT		 1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
89cbc767 1745 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1746 if (unlikely(this_tsc_khz == 0)) {
1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
d828199e 1751 if (!use_master_clock) {
4ea1636b 1752 host_tsc = rdtsc();
d828199e
MT		 1753 kernel_ns = get_kernel_ns();
1754 }
1755
4ba76538 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1757
c285545f
ZA		 1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
f1e2b260 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1772 tsc_timestamp = tsc;
1773 }
50d0a0f9
GH		 1774 }
1775
18068523
GOC		 1776 local_irq_restore(flags);
1777
0b79459b 1778 if (!vcpu->pv_time_enabled)
c285545f 1779 return 0;
18068523 1780
e48672fa 1781 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1782 tgt_tsc_khz = kvm_has_tsc_control ?
1783 vcpu->virtual_tsc_khz : this_tsc_khz;
1784 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1785 &vcpu->hv_clock.tsc_shift,
1786 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1787 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1788 }
1789
1790 /* With all the info we got, fill in the values */
1d5f066e 1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1793 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1794
09a0c3f1
OH		 1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1796 &guest_hv_clock, sizeof(guest_hv_clock))))
1797 return 0;
1798
5dca0d91
RK		 1799 /* This VCPU is paused, but it's legal for a guest to read another
1800 * VCPU's kvmclock, so we really have to follow the specification where
1801 * it says that version is odd if data is being modified, and even after
1802 * it is consistent.
1803 *
1804 * Version field updates must be kept separate. This is because
1805 * kvm_write_guest_cached might use a "rep movs" instruction, and
1806 * writes within a string instruction are weakly ordered. So there
1807 * are three writes overall.
1808 *
1809 * As a small optimization, only write the version field in the first
1810 * and third write. The vcpu->pv_time cache is still valid, because the
1811 * version field is the first in the struct.
18068523 1812 */
5dca0d91
RK		 1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1814
1815 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1817 &vcpu->hv_clock,
1818 sizeof(vcpu->hv_clock.version));
1819
1820 smp_wmb();
78c0337a
MT		 1821
1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1824
1825 if (vcpu->pvclock_set_guest_stopped_request) {
1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1827 vcpu->pvclock_set_guest_stopped_request = false;
1828 }
1829
d828199e
MT		 1830 /* If the host uses TSC clocksource, then it is stable */
1831 if (use_master_clock)
1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1833
78c0337a
MT		 1834 vcpu->hv_clock.flags = pvclock_flags;
1835
ce1a5e60
DM		 1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837
0b79459b
AH		 1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 &vcpu->hv_clock,
1840 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1841
1842 smp_wmb();
1843
1844 vcpu->hv_clock.version++;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock.version));
8cfdc000 1848 return 0;
c8076604
GH		 1849}
1850
0061d53d
MT		 1851/*
1852 * kvmclock updates which are isolated to a given vcpu, such as
1853 * vcpu->cpu migration, should not allow system_timestamp from
1854 * the rest of the vcpus to remain static. Otherwise ntp frequency
1855 * correction applies to one vcpu's system_timestamp but not
1856 * the others.
1857 *
1858 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1859 * We need to rate-limit these requests though, as they can
1860 * considerably slow guests that have a large number of vcpus.
1861 * The time for a remote vcpu to update its kvmclock is bound
1862 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1863 */
1864
7e44e449
AJ		 1865#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1866
1867static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1868{
1869 int i;
7e44e449
AJ		 1870 struct delayed_work *dwork = to_delayed_work(work);
1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1872 kvmclock_update_work);
1873 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1874 struct kvm_vcpu *vcpu;
1875
1876 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1878 kvm_vcpu_kick(vcpu);
1879 }
1880}
1881
7e44e449
AJ		 1882static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1883{
1884 struct kvm *kvm = v->kvm;
1885
105b21bb 1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1888 KVMCLOCK_UPDATE_DELAY);
1889}
1890
332967a3
AJ		 1891#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1892
1893static void kvmclock_sync_fn(struct work_struct *work)
1894{
1895 struct delayed_work *dwork = to_delayed_work(work);
1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1897 kvmclock_sync_work);
1898 struct kvm *kvm = container_of(ka, struct kvm, arch);
1899
630994b3
MT		 1900 if (!kvmclock_periodic_sync)
1901 return;
1902
332967a3
AJ		 1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1905 KVMCLOCK_SYNC_PERIOD);
1906}
1907
890ca9ae 1908static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1909{
890ca9ae
HY		 1910 u64 mcg_cap = vcpu->arch.mcg_cap;
1911 unsigned bank_num = mcg_cap & 0xff;
1912
15c4a640 1913 switch (msr) {
15c4a640 1914 case MSR_IA32_MCG_STATUS:
890ca9ae 1915 vcpu->arch.mcg_status = data;
15c4a640 1916 break;
c7ac679c 1917 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1918 if (!(mcg_cap & MCG_CTL_P))
1919 return 1;
1920 if (data != 0 && data != ~(u64)0)
1921 return -1;
1922 vcpu->arch.mcg_ctl = data;
1923 break;
1924 default:
1925 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1926 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1927 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1928 /* only 0 or all 1s can be written to IA32_MCi_CTL
1929 * some Linux kernels though clear bit 10 in bank 4 to
1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1931 * this to avoid an uncatched #GP in the guest
1932 */
890ca9ae 1933 if ((offset & 0x3) == 0 &&
114be429 1934 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1935 return -1;
1936 vcpu->arch.mce_banks[offset] = data;
1937 break;
1938 }
1939 return 1;
1940 }
1941 return 0;
1942}
1943
ffde22ac
ES		 1944static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1945{
1946 struct kvm *kvm = vcpu->kvm;
1947 int lm = is_long_mode(vcpu);
1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1951 : kvm->arch.xen_hvm_config.blob_size_32;
1952 u32 page_num = data & ~PAGE_MASK;
1953 u64 page_addr = data & PAGE_MASK;
1954 u8 *page;
1955 int r;
1956
1957 r = -E2BIG;
1958 if (page_num >= blob_size)
1959 goto out;
1960 r = -ENOMEM;
ff5c2c03
SL		 1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1962 if (IS_ERR(page)) {
1963 r = PTR_ERR(page);
ffde22ac 1964 goto out;
ff5c2c03 1965 }
54bf36aa 1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1967 goto out_free;
1968 r = 0;
1969out_free:
1970 kfree(page);
1971out:
1972 return r;
1973}
1974
344d9588
GN		 1975static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1976{
1977 gpa_t gpa = data & ~0x3f;
1978
4a969980 1979 /* Bits 2:5 are reserved, Should be zero */
6adba527 1980 if (data & 0x3c)
344d9588
GN		 1981 return 1;
1982
1983 vcpu->arch.apf.msr_val = data;
1984
1985 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1986 kvm_clear_async_pf_completion_queue(vcpu);
1987 kvm_async_pf_hash_reset(vcpu);
1988 return 0;
1989 }
1990
8f964525
AH		 1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1992 sizeof(u32)))
344d9588
GN		 1993 return 1;
1994
6adba527 1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1996 kvm_async_pf_wakeup_all(vcpu);
1997 return 0;
1998}
1999
12f9a48f
GC		 2000static void kvmclock_reset(struct kvm_vcpu *vcpu)
2001{
0b79459b 2002 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2003}
2004
c9aaa895
GC		 2005static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2006{
2007 u64 delta;
2008
2009 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2010 return;
2011
2012 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2013 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2014 vcpu->arch.st.accum_steal = delta;
2015}
2016
2017static void record_steal_time(struct kvm_vcpu *vcpu)
2018{
7cae2bed
MT		 2019 accumulate_steal_time(vcpu);
2020
c9aaa895
GC		 2021 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2022 return;
2023
2024 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2026 return;
2027
2028 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2029 vcpu->arch.st.steal.version += 2;
2030 vcpu->arch.st.accum_steal = 0;
2031
2032 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2033 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2034}
2035
8fe8ab46 2036int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2037{
5753785f 2038 bool pr = false;
8fe8ab46
WA		 2039 u32 msr = msr_info->index;
2040 u64 data = msr_info->data;
5753785f 2041
15c4a640 2042 switch (msr) {
2e32b719
BP		 2043 case MSR_AMD64_NB_CFG:
2044 case MSR_IA32_UCODE_REV:
2045 case MSR_IA32_UCODE_WRITE:
2046 case MSR_VM_HSAVE_PA:
2047 case MSR_AMD64_PATCH_LOADER:
2048 case MSR_AMD64_BU_CFG2:
2049 break;
2050
15c4a640 2051 case MSR_EFER:
b69e8cae 2052 return set_efer(vcpu, data);
8f1589d9
AP		 2053 case MSR_K7_HWCR:
2054 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2055 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2056 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2057 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2058 if (data != 0) {
a737f256
CD		 2059 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2060 data);
8f1589d9
AP		 2061 return 1;
2062 }
15c4a640 2063 break;
f7c6d140
AP		 2064 case MSR_FAM10H_MMIO_CONF_BASE:
2065 if (data != 0) {
a737f256
CD		 2066 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2067 "0x%llx\n", data);
f7c6d140
AP		 2068 return 1;
2069 }
15c4a640 2070 break;
b5e2fec0
AG		 2071 case MSR_IA32_DEBUGCTLMSR:
2072 if (!data) {
2073 /* We support the non-activated case already */
2074 break;
2075 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2076 /* Values other than LBR and BTF are vendor-specific,
2077 thus reserved and should throw a #GP */
2078 return 1;
2079 }
a737f256
CD		 2080 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2081 __func__, data);
b5e2fec0 2082 break;
9ba075a6 2083 case 0x200 ... 0x2ff:
ff53604b 2084 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2085 case MSR_IA32_APICBASE:
58cb628d 2086 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2087 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2088 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2089 case MSR_IA32_TSCDEADLINE:
2090 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2091 break;
ba904635
WA		 2092 case MSR_IA32_TSC_ADJUST:
2093 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2094 if (!msr_info->host_initiated) {
d913b904 2095 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2096 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2097 }
2098 vcpu->arch.ia32_tsc_adjust_msr = data;
2099 }
2100 break;
15c4a640 2101 case MSR_IA32_MISC_ENABLE:
ad312c7c 2102 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2103 break;
64d60670
PB		 2104 case MSR_IA32_SMBASE:
2105 if (!msr_info->host_initiated)
2106 return 1;
2107 vcpu->arch.smbase = data;
2108 break;
11c6bffa 2109 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2110 case MSR_KVM_WALL_CLOCK:
2111 vcpu->kvm->arch.wall_clock = data;
2112 kvm_write_wall_clock(vcpu->kvm, data);
2113 break;
11c6bffa 2114 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2115 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2116 u64 gpa_offset;
54750f2c
MT		 2117 struct kvm_arch *ka = &vcpu->kvm->arch;
2118
12f9a48f 2119 kvmclock_reset(vcpu);
18068523 2120
54750f2c
MT		 2121 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2122 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2123
2124 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2125 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2126 &vcpu->requests);
2127
2128 ka->boot_vcpu_runs_old_kvmclock = tmp;
2129 }
2130
18068523 2131 vcpu->arch.time = data;
0061d53d 2132 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2133
2134 /* we verify if the enable bit is set... */
2135 if (!(data & 1))
2136 break;
2137
0b79459b 2138 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2139
0b79459b 2140 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2141 &vcpu->arch.pv_time, data & ~1ULL,
2142 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2143 vcpu->arch.pv_time_enabled = false;
2144 else
2145 vcpu->arch.pv_time_enabled = true;
32cad84f 2146
18068523
GOC		 2147 break;
2148 }
344d9588
GN		 2149 case MSR_KVM_ASYNC_PF_EN:
2150 if (kvm_pv_enable_async_pf(vcpu, data))
2151 return 1;
2152 break;
c9aaa895
GC		 2153 case MSR_KVM_STEAL_TIME:
2154
2155 if (unlikely(!sched_info_on()))
2156 return 1;
2157
2158 if (data & KVM_STEAL_RESERVED_MASK)
2159 return 1;
2160
2161 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2162 data & KVM_STEAL_VALID_BITS,
2163 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2164 return 1;
2165
2166 vcpu->arch.st.msr_val = data;
2167
2168 if (!(data & KVM_MSR_ENABLED))
2169 break;
2170
c9aaa895
GC		 2171 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2172
2173 break;
ae7a2a3f
MT		 2174 case MSR_KVM_PV_EOI_EN:
2175 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2176 return 1;
2177 break;
c9aaa895 2178
890ca9ae
HY		 2179 case MSR_IA32_MCG_CTL:
2180 case MSR_IA32_MCG_STATUS:
81760dcc 2181 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2182 return set_msr_mce(vcpu, msr, data);
71db6023 2183
6912ac32
WH		 2184 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2185 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2186 pr = true; /* fall through */
2187 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2188 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2189 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2190 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2191
2192 if (pr || data != 0)
a737f256
CD		 2193 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2194 "0x%x data 0x%llx\n", msr, data);
5753785f 2195 break;
84e0cefa
JS		 2196 case MSR_K7_CLK_CTL:
2197 /*
2198 * Ignore all writes to this no longer documented MSR.
2199 * Writes are only relevant for old K7 processors,
2200 * all pre-dating SVM, but a recommended workaround from
4a969980 2201 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2202 * affected processor models on the command line, hence
2203 * the need to ignore the workaround.
2204 */
2205 break;
55cd8e5a 2206 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2207 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2208 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2209 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2210 return kvm_hv_set_msr_common(vcpu, msr, data,
2211 msr_info->host_initiated);
91c9c3ed 2212 case MSR_IA32_BBL_CR_CTL3:
2213 /* Drop writes to this legacy MSR -- see rdmsr
2214 * counterpart for further detail.
2215 */
a737f256 2216 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2217 break;
2b036c6b
BO		 2218 case MSR_AMD64_OSVW_ID_LENGTH:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.length = data;
2222 break;
2223 case MSR_AMD64_OSVW_STATUS:
2224 if (!guest_cpuid_has_osvw(vcpu))
2225 return 1;
2226 vcpu->arch.osvw.status = data;
2227 break;
15c4a640 2228 default:
ffde22ac
ES		 2229 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2230 return xen_hvm_config(vcpu, data);
c6702c9d 2231 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2232 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2233 if (!ignore_msrs) {
a737f256
CD		 2234 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2235 msr, data);
ed85c068
AP		 2236 return 1;
2237 } else {
a737f256
CD		 2238 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2239 msr, data);
ed85c068
AP		 2240 break;
2241 }
15c4a640
CO		 2242 }
2243 return 0;
2244}
2245EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2246
2247
2248/*
2249 * Reads an msr value (of 'msr_index') into 'pdata'.
2250 * Returns 0 on success, non-0 otherwise.
2251 * Assumes vcpu_load() was already called.
2252 */
609e36d3 2253int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2254{
609e36d3 2255 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2256}
ff651cb6 2257EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2258
890ca9ae 2259static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2260{
2261 u64 data;
890ca9ae
HY		 2262 u64 mcg_cap = vcpu->arch.mcg_cap;
2263 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2264
2265 switch (msr) {
15c4a640
CO		 2266 case MSR_IA32_P5_MC_ADDR:
2267 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2268 data = 0;
2269 break;
15c4a640 2270 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2271 data = vcpu->arch.mcg_cap;
2272 break;
c7ac679c 2273 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2274 if (!(mcg_cap & MCG_CTL_P))
2275 return 1;
2276 data = vcpu->arch.mcg_ctl;
2277 break;
2278 case MSR_IA32_MCG_STATUS:
2279 data = vcpu->arch.mcg_status;
2280 break;
2281 default:
2282 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2283 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2284 u32 offset = msr - MSR_IA32_MC0_CTL;
2285 data = vcpu->arch.mce_banks[offset];
2286 break;
2287 }
2288 return 1;
2289 }
2290 *pdata = data;
2291 return 0;
2292}
2293
609e36d3 2294int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2295{
609e36d3 2296 switch (msr_info->index) {
890ca9ae 2297 case MSR_IA32_PLATFORM_ID:
15c4a640 2298 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2299 case MSR_IA32_DEBUGCTLMSR:
2300 case MSR_IA32_LASTBRANCHFROMIP:
2301 case MSR_IA32_LASTBRANCHTOIP:
2302 case MSR_IA32_LASTINTFROMIP:
2303 case MSR_IA32_LASTINTTOIP:
60af2ecd 2304 case MSR_K8_SYSCFG:
3afb1121
PB		 2305 case MSR_K8_TSEG_ADDR:
2306 case MSR_K8_TSEG_MASK:
60af2ecd 2307 case MSR_K7_HWCR:
61a6bd67 2308 case MSR_VM_HSAVE_PA:
1fdbd48c 2309 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2310 case MSR_AMD64_NB_CFG:
f7c6d140 2311 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2312 case MSR_AMD64_BU_CFG2:
609e36d3 2313 msr_info->data = 0;
15c4a640 2314 break;
6912ac32
WH		 2315 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2316 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2317 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2318 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2319 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2320 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2321 msr_info->data = 0;
5753785f 2322 break;
742bc670 2323 case MSR_IA32_UCODE_REV:
609e36d3 2324 msr_info->data = 0x100000000ULL;
742bc670 2325 break;
9ba075a6 2326 case MSR_MTRRcap:
9ba075a6 2327 case 0x200 ... 0x2ff:
ff53604b 2328 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2329 case 0xcd: /* fsb frequency */
609e36d3 2330 msr_info->data = 3;
15c4a640 2331 break;
7b914098
JS		 2332 /*
2333 * MSR_EBC_FREQUENCY_ID
2334 * Conservative value valid for even the basic CPU models.
2335 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2336 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2337 * and 266MHz for model 3, or 4. Set Core Clock
2338 * Frequency to System Bus Frequency Ratio to 1 (bits
2339 * 31:24) even though these are only valid for CPU
2340 * models > 2, however guests may end up dividing or
2341 * multiplying by zero otherwise.
2342 */
2343 case MSR_EBC_FREQUENCY_ID:
609e36d3 2344 msr_info->data = 1 << 24;
7b914098 2345 break;
15c4a640 2346 case MSR_IA32_APICBASE:
609e36d3 2347 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2348 break;
0105d1a5 2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2350 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2351 break;
a3e06bbe 2352 case MSR_IA32_TSCDEADLINE:
609e36d3 2353 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2354 break;
ba904635 2355 case MSR_IA32_TSC_ADJUST:
609e36d3 2356 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2357 break;
15c4a640 2358 case MSR_IA32_MISC_ENABLE:
609e36d3 2359 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2360 break;
64d60670
PB		 2361 case MSR_IA32_SMBASE:
2362 if (!msr_info->host_initiated)
2363 return 1;
2364 msr_info->data = vcpu->arch.smbase;
15c4a640 2365 break;
847f0ad8
AG		 2366 case MSR_IA32_PERF_STATUS:
2367 /* TSC increment by tick */
609e36d3 2368 msr_info->data = 1000ULL;
847f0ad8 2369 /* CPU multiplier */
b0996ae4 2370 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2371 break;
15c4a640 2372 case MSR_EFER:
609e36d3 2373 msr_info->data = vcpu->arch.efer;
15c4a640 2374 break;
18068523 2375 case MSR_KVM_WALL_CLOCK:
11c6bffa 2376 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2377 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2378 break;
2379 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2380 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2381 msr_info->data = vcpu->arch.time;
18068523 2382 break;
344d9588 2383 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2384 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2385 break;
c9aaa895 2386 case MSR_KVM_STEAL_TIME:
609e36d3 2387 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2388 break;
1d92128f 2389 case MSR_KVM_PV_EOI_EN:
609e36d3 2390 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2391 break;
890ca9ae
HY		 2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
2394 case MSR_IA32_MCG_CAP:
2395 case MSR_IA32_MCG_CTL:
2396 case MSR_IA32_MCG_STATUS:
81760dcc 2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2398 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2399 case MSR_K7_CLK_CTL:
2400 /*
2401 * Provide expected ramp-up count for K7. All other
2402 * are set to zero, indicating minimum divisors for
2403 * every field.
2404 *
2405 * This prevents guest kernels on AMD host with CPU
2406 * type 6, model 8 and higher from exploding due to
2407 * the rdmsr failing.
2408 */
609e36d3 2409 msr_info->data = 0x20000000;
84e0cefa 2410 break;
55cd8e5a 2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2412 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2413 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2414 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2415 return kvm_hv_get_msr_common(vcpu,
2416 msr_info->index, &msr_info->data);
55cd8e5a 2417 break;
91c9c3ed 2418 case MSR_IA32_BBL_CR_CTL3:
2419 /* This legacy MSR exists but isn't fully documented in current
2420 * silicon. It is however accessed by winxp in very narrow
2421 * scenarios where it sets bit #19, itself documented as
2422 * a "reserved" bit. Best effort attempt to source coherent
2423 * read data here should the balance of the register be
2424 * interpreted by the guest:
2425 *
2426 * L2 cache control register 3: 64GB range, 256KB size,
2427 * enabled, latency 0x1, configured
2428 */
609e36d3 2429 msr_info->data = 0xbe702111;
91c9c3ed 2430 break;
2b036c6b
BO		 2431 case MSR_AMD64_OSVW_ID_LENGTH:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
609e36d3 2434 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2435 break;
2436 case MSR_AMD64_OSVW_STATUS:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
609e36d3 2439 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2440 break;
15c4a640 2441 default:
c6702c9d 2442 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2443 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2444 if (!ignore_msrs) {
609e36d3 2445 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2446 return 1;
2447 } else {
609e36d3
PB		 2448 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2449 msr_info->data = 0;
ed85c068
AP		 2450 }
2451 break;
15c4a640 2452 }
15c4a640
CO		 2453 return 0;
2454}
2455EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2456
313a3dc7
CO		 2457/*
2458 * Read or write a bunch of msrs. All parameters are kernel addresses.
2459 *
2460 * @return number of msrs set successfully.
2461 */
2462static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2463 struct kvm_msr_entry *entries,
2464 int (*do_msr)(struct kvm_vcpu *vcpu,
2465 unsigned index, u64 *data))
2466{
f656ce01 2467 int i, idx;
313a3dc7 2468
f656ce01 2469 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2470 for (i = 0; i < msrs->nmsrs; ++i)
2471 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2472 break;
f656ce01 2473 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2474
313a3dc7
CO		 2475 return i;
2476}
2477
2478/*
2479 * Read or write a bunch of msrs. Parameters are user addresses.
2480 *
2481 * @return number of msrs set successfully.
2482 */
2483static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2484 int (*do_msr)(struct kvm_vcpu *vcpu,
2485 unsigned index, u64 *data),
2486 int writeback)
2487{
2488 struct kvm_msrs msrs;
2489 struct kvm_msr_entry *entries;
2490 int r, n;
2491 unsigned size;
2492
2493 r = -EFAULT;
2494 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2495 goto out;
2496
2497 r = -E2BIG;
2498 if (msrs.nmsrs >= MAX_IO_MSRS)
2499 goto out;
2500
313a3dc7 2501 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2502 entries = memdup_user(user_msrs->entries, size);
2503 if (IS_ERR(entries)) {
2504 r = PTR_ERR(entries);
313a3dc7 2505 goto out;
ff5c2c03 2506 }
313a3dc7
CO		 2507
2508 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2509 if (r < 0)
2510 goto out_free;
2511
2512 r = -EFAULT;
2513 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2514 goto out_free;
2515
2516 r = n;
2517
2518out_free:
7a73c028 2519 kfree(entries);
313a3dc7
CO		 2520out:
2521 return r;
2522}
2523
784aa3d7 2524int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2525{
2526 int r;
2527
2528 switch (ext) {
2529 case KVM_CAP_IRQCHIP:
2530 case KVM_CAP_HLT:
2531 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2532 case KVM_CAP_SET_TSS_ADDR:
07716717 2533 case KVM_CAP_EXT_CPUID:
9c15bb1d 2534 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2535 case KVM_CAP_CLOCKSOURCE:
7837699f 2536 case KVM_CAP_PIT:
a28e4f5a 2537 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2538 case KVM_CAP_MP_STATE:
ed848624 2539 case KVM_CAP_SYNC_MMU:
a355c85c 2540 case KVM_CAP_USER_NMI:
52d939a0 2541 case KVM_CAP_REINJECT_CONTROL:
4925663a 2542 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2543 case KVM_CAP_IOEVENTFD:
f848a5a8 2544 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2545 case KVM_CAP_PIT2:
e9f42757 2546 case KVM_CAP_PIT_STATE2:
b927a3ce 2547 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2548 case KVM_CAP_XEN_HVM:
afbcf7ab 2549 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2550 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2551 case KVM_CAP_HYPERV:
10388a07 2552 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2553 case KVM_CAP_HYPERV_SPIN:
5c919412 2554 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2555 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2556 case KVM_CAP_DEBUGREGS:
d2be1651 2557 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2558 case KVM_CAP_XSAVE:
344d9588 2559 case KVM_CAP_ASYNC_PF:
92a1f12d 2560 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2561 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2562 case KVM_CAP_READONLY_MEM:
5f66b620 2563 case KVM_CAP_HYPERV_TIME:
100943c5 2564 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2565 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2566 case KVM_CAP_ENABLE_CAP_VM:
2567 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2568 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2569 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2570#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2571 case KVM_CAP_ASSIGN_DEV_IRQ:
2572 case KVM_CAP_PCI_2_3:
2573#endif
018d00d2
ZX		 2574 r = 1;
2575 break;
6d396b55
PB		 2576 case KVM_CAP_X86_SMM:
2577 /* SMBASE is usually relocated above 1M on modern chipsets,
2578 * and SMM handlers might indeed rely on 4G segment limits,
2579 * so do not report SMM to be available if real mode is
2580 * emulated via vm86 mode. Still, do not go to great lengths
2581 * to avoid userspace's usage of the feature, because it is a
2582 * fringe case that is not enabled except via specific settings
2583 * of the module parameters.
2584 */
2585 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2586 break;
542472b5
LV		 2587 case KVM_CAP_COALESCED_MMIO:
2588 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2589 break;
774ead3a
AK		 2590 case KVM_CAP_VAPIC:
2591 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2592 break;
f725230a 2593 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2594 r = KVM_SOFT_MAX_VCPUS;
2595 break;
2596 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2597 r = KVM_MAX_VCPUS;
2598 break;
a988b910 2599 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2600 r = KVM_USER_MEM_SLOTS;
a988b910 2601 break;
a68a6a72
MT		 2602 case KVM_CAP_PV_MMU: /* obsolete */
2603 r = 0;
2f333bcb 2604 break;
4cee4b72 2605#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2606 case KVM_CAP_IOMMU:
a1b60c1c 2607 r = iommu_present(&pci_bus_type);
62c476c7 2608 break;
4cee4b72 2609#endif
890ca9ae
HY		 2610 case KVM_CAP_MCE:
2611 r = KVM_MAX_MCE_BANKS;
2612 break;
2d5b5a66
SY		 2613 case KVM_CAP_XCRS:
2614 r = cpu_has_xsave;
2615 break;
92a1f12d
JR		 2616 case KVM_CAP_TSC_CONTROL:
2617 r = kvm_has_tsc_control;
2618 break;
018d00d2
ZX		 2619 default:
2620 r = 0;
2621 break;
2622 }
2623 return r;
2624
2625}
2626
043405e1
CO		 2627long kvm_arch_dev_ioctl(struct file *filp,
2628 unsigned int ioctl, unsigned long arg)
2629{
2630 void __user *argp = (void __user *)arg;
2631 long r;
2632
2633 switch (ioctl) {
2634 case KVM_GET_MSR_INDEX_LIST: {
2635 struct kvm_msr_list __user *user_msr_list = argp;
2636 struct kvm_msr_list msr_list;
2637 unsigned n;
2638
2639 r = -EFAULT;
2640 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2641 goto out;
2642 n = msr_list.nmsrs;
62ef68bb 2643 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2644 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2645 goto out;
2646 r = -E2BIG;
e125e7b6 2647 if (n < msr_list.nmsrs)
043405e1
CO		 2648 goto out;
2649 r = -EFAULT;
2650 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2651 num_msrs_to_save * sizeof(u32)))
2652 goto out;
e125e7b6 2653 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2654 &emulated_msrs,
62ef68bb 2655 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2656 goto out;
2657 r = 0;
2658 break;
2659 }
9c15bb1d
BP		 2660 case KVM_GET_SUPPORTED_CPUID:
2661 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2662 struct kvm_cpuid2 __user *cpuid_arg = argp;
2663 struct kvm_cpuid2 cpuid;
2664
2665 r = -EFAULT;
2666 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2667 goto out;
9c15bb1d
BP		 2668
2669 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2670 ioctl);
674eea0f
AK		 2671 if (r)
2672 goto out;
2673
2674 r = -EFAULT;
2675 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2676 goto out;
2677 r = 0;
2678 break;
2679 }
890ca9ae
HY		 2680 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2681 u64 mce_cap;
2682
2683 mce_cap = KVM_MCE_CAP_SUPPORTED;
2684 r = -EFAULT;
2685 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2686 goto out;
2687 r = 0;
2688 break;
2689 }
043405e1
CO		 2690 default:
2691 r = -EINVAL;
2692 }
2693out:
2694 return r;
2695}
2696
f5f48ee1
SY		 2697static void wbinvd_ipi(void *garbage)
2698{
2699 wbinvd();
2700}
2701
2702static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2703{
e0f0bbc5 2704 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2705}
2706
2860c4b1
PB		 2707static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2708{
2709 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2710}
2711
313a3dc7
CO		 2712void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2713{
f5f48ee1
SY		 2714 /* Address WBINVD may be executed by guest */
2715 if (need_emulate_wbinvd(vcpu)) {
2716 if (kvm_x86_ops->has_wbinvd_exit())
2717 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2718 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2719 smp_call_function_single(vcpu->cpu,
2720 wbinvd_ipi, NULL, 1);
2721 }
2722
313a3dc7 2723 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2724
0dd6a6ed
ZA		 2725 /* Apply any externally detected TSC adjustments (due to suspend) */
2726 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2727 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2728 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2730 }
8f6055cb 2731
48434c20 2732 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2733 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2734 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2735 if (tsc_delta < 0)
2736 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2737 if (check_tsc_unstable()) {
07c1419a 2738 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2739 vcpu->arch.last_guest_tsc);
2740 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2741 vcpu->arch.tsc_catchup = 1;
c285545f 2742 }
d98d07ca
MT		 2743 /*
2744 * On a host with synchronized TSC, there is no need to update
2745 * kvmclock on vcpu->cpu migration
2746 */
2747 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2748 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2749 if (vcpu->cpu != cpu)
2750 kvm_migrate_timers(vcpu);
e48672fa 2751 vcpu->cpu = cpu;
6b7d7e76 2752 }
c9aaa895 2753
c9aaa895 2754 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
172b2386 2755 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
313a3dc7
CO		 2756}
2757
2758void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2759{
02daab21 2760 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2761 kvm_put_guest_fpu(vcpu);
4ea1636b 2762 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2763}
2764
313a3dc7
CO		 2765static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2766 struct kvm_lapic_state *s)
2767{
d62caabb
AS		 2768 if (vcpu->arch.apicv_active)
2769 kvm_x86_ops->sync_pir_to_irr(vcpu);
2770
ad312c7c 2771 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2772
2773 return 0;
2774}
2775
2776static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2778{
64eb0620 2779 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2780 update_cr8_intercept(vcpu);
313a3dc7
CO		 2781
2782 return 0;
2783}
2784
127a457a
MG		 2785static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2786{
2787 return (!lapic_in_kernel(vcpu) ||
2788 kvm_apic_accept_pic_intr(vcpu));
2789}
2790
782d422b
MG		 2791/*
2792 * if userspace requested an interrupt window, check that the
2793 * interrupt window is open.
2794 *
2795 * No need to exit to userspace if we already have an interrupt queued.
2796 */
2797static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2798{
2799 return kvm_arch_interrupt_allowed(vcpu) &&
2800 !kvm_cpu_has_interrupt(vcpu) &&
2801 !kvm_event_needs_reinjection(vcpu) &&
2802 kvm_cpu_accept_dm_intr(vcpu);
2803}
2804
f77bc6a4
ZX		 2805static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2806 struct kvm_interrupt *irq)
2807{
02cdb50f 2808 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2809 return -EINVAL;
1c1a9ce9
SR		 2810
2811 if (!irqchip_in_kernel(vcpu->kvm)) {
2812 kvm_queue_interrupt(vcpu, irq->irq, false);
2813 kvm_make_request(KVM_REQ_EVENT, vcpu);
2814 return 0;
2815 }
2816
2817 /*
2818 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2819 * fail for in-kernel 8259.
2820 */
2821 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2822 return -ENXIO;
f77bc6a4 2823
1c1a9ce9
SR		 2824 if (vcpu->arch.pending_external_vector != -1)
2825 return -EEXIST;
f77bc6a4 2826
1c1a9ce9 2827 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2828 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2829 return 0;
2830}
2831
c4abb7c9
JK		 2832static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2833{
c4abb7c9 2834 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2835
2836 return 0;
2837}
2838
f077825a
PB		 2839static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2840{
64d60670
PB		 2841 kvm_make_request(KVM_REQ_SMI, vcpu);
2842
f077825a
PB		 2843 return 0;
2844}
2845
b209749f
AK		 2846static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2847 struct kvm_tpr_access_ctl *tac)
2848{
2849 if (tac->flags)
2850 return -EINVAL;
2851 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2852 return 0;
2853}
2854
890ca9ae
HY		 2855static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2856 u64 mcg_cap)
2857{
2858 int r;
2859 unsigned bank_num = mcg_cap & 0xff, bank;
2860
2861 r = -EINVAL;
a9e38c3e 2862 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2863 goto out;
2864 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2865 goto out;
2866 r = 0;
2867 vcpu->arch.mcg_cap = mcg_cap;
2868 /* Init IA32_MCG_CTL to all 1s */
2869 if (mcg_cap & MCG_CTL_P)
2870 vcpu->arch.mcg_ctl = ~(u64)0;
2871 /* Init IA32_MCi_CTL to all 1s */
2872 for (bank = 0; bank < bank_num; bank++)
2873 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2874out:
2875 return r;
2876}
2877
2878static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2879 struct kvm_x86_mce *mce)
2880{
2881 u64 mcg_cap = vcpu->arch.mcg_cap;
2882 unsigned bank_num = mcg_cap & 0xff;
2883 u64 *banks = vcpu->arch.mce_banks;
2884
2885 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2886 return -EINVAL;
2887 /*
2888 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2889 * reporting is disabled
2890 */
2891 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2892 vcpu->arch.mcg_ctl != ~(u64)0)
2893 return 0;
2894 banks += 4 * mce->bank;
2895 /*
2896 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2897 * reporting is disabled for the bank
2898 */
2899 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2900 return 0;
2901 if (mce->status & MCI_STATUS_UC) {
2902 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2903 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2904 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2905 return 0;
2906 }
2907 if (banks[1] & MCI_STATUS_VAL)
2908 mce->status |= MCI_STATUS_OVER;
2909 banks[2] = mce->addr;
2910 banks[3] = mce->misc;
2911 vcpu->arch.mcg_status = mce->mcg_status;
2912 banks[1] = mce->status;
2913 kvm_queue_exception(vcpu, MC_VECTOR);
2914 } else if (!(banks[1] & MCI_STATUS_VAL)
2915 || !(banks[1] & MCI_STATUS_UC)) {
2916 if (banks[1] & MCI_STATUS_VAL)
2917 mce->status |= MCI_STATUS_OVER;
2918 banks[2] = mce->addr;
2919 banks[3] = mce->misc;
2920 banks[1] = mce->status;
2921 } else
2922 banks[1] |= MCI_STATUS_OVER;
2923 return 0;
2924}
2925
3cfc3092
JK		 2926static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2927 struct kvm_vcpu_events *events)
2928{
7460fb4a 2929 process_nmi(vcpu);
03b82a30
JK		 2930 events->exception.injected =
2931 vcpu->arch.exception.pending &&
2932 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2933 events->exception.nr = vcpu->arch.exception.nr;
2934 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2935 events->exception.pad = 0;
3cfc3092
JK		 2936 events->exception.error_code = vcpu->arch.exception.error_code;
2937
03b82a30
JK		 2938 events->interrupt.injected =
2939 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2940 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2941 events->interrupt.soft = 0;
37ccdcbe 2942 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2943
2944 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2945 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2946 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2947 events->nmi.pad = 0;
3cfc3092 2948
66450a21 2949 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2950
f077825a
PB		 2951 events->smi.smm = is_smm(vcpu);
2952 events->smi.pending = vcpu->arch.smi_pending;
2953 events->smi.smm_inside_nmi =
2954 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2955 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2956
dab4b911 2957 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2958 | KVM_VCPUEVENT_VALID_SHADOW
2959 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2960 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2961}
2962
2963static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2964 struct kvm_vcpu_events *events)
2965{
dab4b911 2966 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2967 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2968 | KVM_VCPUEVENT_VALID_SHADOW
2969 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2970 return -EINVAL;
2971
7460fb4a 2972 process_nmi(vcpu);
3cfc3092
JK		 2973 vcpu->arch.exception.pending = events->exception.injected;
2974 vcpu->arch.exception.nr = events->exception.nr;
2975 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2976 vcpu->arch.exception.error_code = events->exception.error_code;
2977
2978 vcpu->arch.interrupt.pending = events->interrupt.injected;
2979 vcpu->arch.interrupt.nr = events->interrupt.nr;
2980 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2981 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2982 kvm_x86_ops->set_interrupt_shadow(vcpu,
2983 events->interrupt.shadow);
3cfc3092
JK		 2984
2985 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2986 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2987 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2988 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2989
66450a21
JK		 2990 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2991 kvm_vcpu_has_lapic(vcpu))
2992 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2993
f077825a
PB		 2994 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2995 if (events->smi.smm)
2996 vcpu->arch.hflags |= HF_SMM_MASK;
2997 else
2998 vcpu->arch.hflags &= ~HF_SMM_MASK;
2999 vcpu->arch.smi_pending = events->smi.pending;
3000 if (events->smi.smm_inside_nmi)
3001 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3002 else
3003 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3004 if (kvm_vcpu_has_lapic(vcpu)) {
3005 if (events->smi.latched_init)
3006 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3007 else
3008 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3009 }
3010 }
3011
3842d135
AK		 3012 kvm_make_request(KVM_REQ_EVENT, vcpu);
3013
3cfc3092
JK		 3014 return 0;
3015}
3016
a1efbe77
JK		 3017static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3018 struct kvm_debugregs *dbgregs)
3019{
73aaf249
JK		 3020 unsigned long val;
3021
a1efbe77 3022 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3023 kvm_get_dr(vcpu, 6, &val);
73aaf249 3024 dbgregs->dr6 = val;
a1efbe77
JK		 3025 dbgregs->dr7 = vcpu->arch.dr7;
3026 dbgregs->flags = 0;
97e69aa6 3027 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3028}
3029
3030static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3031 struct kvm_debugregs *dbgregs)
3032{
3033 if (dbgregs->flags)
3034 return -EINVAL;
3035
a1efbe77 3036 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3037 kvm_update_dr0123(vcpu);
a1efbe77 3038 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3039 kvm_update_dr6(vcpu);
a1efbe77 3040 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3041 kvm_update_dr7(vcpu);
a1efbe77 3042
a1efbe77
JK		 3043 return 0;
3044}
3045
df1daba7
PB		 3046#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3047
3048static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3049{
c47ada30 3050 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3051 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3052 u64 valid;
3053
3054 /*
3055 * Copy legacy XSAVE area, to avoid complications with CPUID
3056 * leaves 0 and 1 in the loop below.
3057 */
3058 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3059
3060 /* Set XSTATE_BV */
3061 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3062
3063 /*
3064 * Copy each region from the possibly compacted offset to the
3065 * non-compacted offset.
3066 */
d91cab78 3067 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3068 while (valid) {
3069 u64 feature = valid & -valid;
3070 int index = fls64(feature) - 1;
3071 void *src = get_xsave_addr(xsave, feature);
3072
3073 if (src) {
3074 u32 size, offset, ecx, edx;
3075 cpuid_count(XSTATE_CPUID, index,
3076 &size, &offset, &ecx, &edx);
3077 memcpy(dest + offset, src, size);
3078 }
3079
3080 valid -= feature;
3081 }
3082}
3083
3084static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3085{
c47ada30 3086 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3087 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3088 u64 valid;
3089
3090 /*
3091 * Copy legacy XSAVE area, to avoid complications with CPUID
3092 * leaves 0 and 1 in the loop below.
3093 */
3094 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3095
3096 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3097 xsave->header.xfeatures = xstate_bv;
df1daba7 3098 if (cpu_has_xsaves)
3a54450b 3099 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3100
3101 /*
3102 * Copy each region from the non-compacted offset to the
3103 * possibly compacted offset.
3104 */
d91cab78 3105 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3106 while (valid) {
3107 u64 feature = valid & -valid;
3108 int index = fls64(feature) - 1;
3109 void *dest = get_xsave_addr(xsave, feature);
3110
3111 if (dest) {
3112 u32 size, offset, ecx, edx;
3113 cpuid_count(XSTATE_CPUID, index,
3114 &size, &offset, &ecx, &edx);
3115 memcpy(dest, src + offset, size);
ee4100da 3116 }
df1daba7
PB		 3117
3118 valid -= feature;
3119 }
3120}
3121
2d5b5a66
SY		 3122static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3123 struct kvm_xsave *guest_xsave)
3124{
4344ee98 3125 if (cpu_has_xsave) {
df1daba7
PB		 3126 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3127 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3128 } else {
2d5b5a66 3129 memcpy(guest_xsave->region,
7366ed77 3130 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3131 sizeof(struct fxregs_state));
2d5b5a66 3132 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3133 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3134 }
3135}
3136
3137static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3138 struct kvm_xsave *guest_xsave)
3139{
3140 u64 xstate_bv =
3141 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3142
d7876f1b
PB		 3143 if (cpu_has_xsave) {
3144 /*
3145 * Here we allow setting states that are not present in
3146 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3147 * with old userspace.
3148 */
4ff41732 3149 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3150 return -EINVAL;
df1daba7 3151 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3152 } else {
d91cab78 3153 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3154 return -EINVAL;
7366ed77 3155 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3156 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3157 }
3158 return 0;
3159}
3160
3161static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3162 struct kvm_xcrs *guest_xcrs)
3163{
3164 if (!cpu_has_xsave) {
3165 guest_xcrs->nr_xcrs = 0;
3166 return;
3167 }
3168
3169 guest_xcrs->nr_xcrs = 1;
3170 guest_xcrs->flags = 0;
3171 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3172 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3173}
3174
3175static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3176 struct kvm_xcrs *guest_xcrs)
3177{
3178 int i, r = 0;
3179
3180 if (!cpu_has_xsave)
3181 return -EINVAL;
3182
3183 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3184 return -EINVAL;
3185
3186 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3187 /* Only support XCR0 currently */
c67a04cb 3188 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3189 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3190 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3191 break;
3192 }
3193 if (r)
3194 r = -EINVAL;
3195 return r;
3196}
3197
1c0b28c2
EM		 3198/*
3199 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3200 * stopped by the hypervisor. This function will be called from the host only.
3201 * EINVAL is returned when the host attempts to set the flag for a guest that
3202 * does not support pv clocks.
3203 */
3204static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3205{
0b79459b 3206 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3207 return -EINVAL;
51d59c6b 3208 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3209 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3210 return 0;
3211}
3212
5c919412
AS		 3213static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3214 struct kvm_enable_cap *cap)
3215{
3216 if (cap->flags)
3217 return -EINVAL;
3218
3219 switch (cap->cap) {
3220 case KVM_CAP_HYPERV_SYNIC:
3221 return kvm_hv_activate_synic(vcpu);
3222 default:
3223 return -EINVAL;
3224 }
3225}
3226
313a3dc7
CO		 3227long kvm_arch_vcpu_ioctl(struct file *filp,
3228 unsigned int ioctl, unsigned long arg)
3229{
3230 struct kvm_vcpu *vcpu = filp->private_data;
3231 void __user *argp = (void __user *)arg;
3232 int r;
d1ac91d8
AK		 3233 union {
3234 struct kvm_lapic_state *lapic;
3235 struct kvm_xsave *xsave;
3236 struct kvm_xcrs *xcrs;
3237 void *buffer;
3238 } u;
3239
3240 u.buffer = NULL;
313a3dc7
CO		 3241 switch (ioctl) {
3242 case KVM_GET_LAPIC: {
2204ae3c
MT		 3243 r = -EINVAL;
3244 if (!vcpu->arch.apic)
3245 goto out;
d1ac91d8 3246 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3247
b772ff36 3248 r = -ENOMEM;
d1ac91d8 3249 if (!u.lapic)
b772ff36 3250 goto out;
d1ac91d8 3251 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3252 if (r)
3253 goto out;
3254 r = -EFAULT;
d1ac91d8 3255 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3256 goto out;
3257 r = 0;
3258 break;
3259 }
3260 case KVM_SET_LAPIC: {
2204ae3c
MT		 3261 r = -EINVAL;
3262 if (!vcpu->arch.apic)
3263 goto out;
ff5c2c03 3264 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3265 if (IS_ERR(u.lapic))
3266 return PTR_ERR(u.lapic);
ff5c2c03 3267
d1ac91d8 3268 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3269 break;
3270 }
f77bc6a4
ZX		 3271 case KVM_INTERRUPT: {
3272 struct kvm_interrupt irq;
3273
3274 r = -EFAULT;
3275 if (copy_from_user(&irq, argp, sizeof irq))
3276 goto out;
3277 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3278 break;
3279 }
c4abb7c9
JK		 3280 case KVM_NMI: {
3281 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3282 break;
3283 }
f077825a
PB		 3284 case KVM_SMI: {
3285 r = kvm_vcpu_ioctl_smi(vcpu);
3286 break;
3287 }
313a3dc7
CO		 3288 case KVM_SET_CPUID: {
3289 struct kvm_cpuid __user *cpuid_arg = argp;
3290 struct kvm_cpuid cpuid;
3291
3292 r = -EFAULT;
3293 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3294 goto out;
3295 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3296 break;
3297 }
07716717
DK		 3298 case KVM_SET_CPUID2: {
3299 struct kvm_cpuid2 __user *cpuid_arg = argp;
3300 struct kvm_cpuid2 cpuid;
3301
3302 r = -EFAULT;
3303 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3304 goto out;
3305 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3306 cpuid_arg->entries);
07716717
DK		 3307 break;
3308 }
3309 case KVM_GET_CPUID2: {
3310 struct kvm_cpuid2 __user *cpuid_arg = argp;
3311 struct kvm_cpuid2 cpuid;
3312
3313 r = -EFAULT;
3314 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3315 goto out;
3316 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3317 cpuid_arg->entries);
07716717
DK		 3318 if (r)
3319 goto out;
3320 r = -EFAULT;
3321 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3322 goto out;
3323 r = 0;
3324 break;
3325 }
313a3dc7 3326 case KVM_GET_MSRS:
609e36d3 3327 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3328 break;
3329 case KVM_SET_MSRS:
3330 r = msr_io(vcpu, argp, do_set_msr, 0);
3331 break;
b209749f
AK		 3332 case KVM_TPR_ACCESS_REPORTING: {
3333 struct kvm_tpr_access_ctl tac;
3334
3335 r = -EFAULT;
3336 if (copy_from_user(&tac, argp, sizeof tac))
3337 goto out;
3338 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3339 if (r)
3340 goto out;
3341 r = -EFAULT;
3342 if (copy_to_user(argp, &tac, sizeof tac))
3343 goto out;
3344 r = 0;
3345 break;
3346 };
b93463aa
AK		 3347 case KVM_SET_VAPIC_ADDR: {
3348 struct kvm_vapic_addr va;
3349
3350 r = -EINVAL;
35754c98 3351 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3352 goto out;
3353 r = -EFAULT;
3354 if (copy_from_user(&va, argp, sizeof va))
3355 goto out;
fda4e2e8 3356 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3357 break;
3358 }
890ca9ae
HY		 3359 case KVM_X86_SETUP_MCE: {
3360 u64 mcg_cap;
3361
3362 r = -EFAULT;
3363 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3364 goto out;
3365 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3366 break;
3367 }
3368 case KVM_X86_SET_MCE: {
3369 struct kvm_x86_mce mce;
3370
3371 r = -EFAULT;
3372 if (copy_from_user(&mce, argp, sizeof mce))
3373 goto out;
3374 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3375 break;
3376 }
3cfc3092
JK		 3377 case KVM_GET_VCPU_EVENTS: {
3378 struct kvm_vcpu_events events;
3379
3380 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3381
3382 r = -EFAULT;
3383 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3384 break;
3385 r = 0;
3386 break;
3387 }
3388 case KVM_SET_VCPU_EVENTS: {
3389 struct kvm_vcpu_events events;
3390
3391 r = -EFAULT;
3392 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3393 break;
3394
3395 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3396 break;
3397 }
a1efbe77
JK		 3398 case KVM_GET_DEBUGREGS: {
3399 struct kvm_debugregs dbgregs;
3400
3401 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3402
3403 r = -EFAULT;
3404 if (copy_to_user(argp, &dbgregs,
3405 sizeof(struct kvm_debugregs)))
3406 break;
3407 r = 0;
3408 break;
3409 }
3410 case KVM_SET_DEBUGREGS: {
3411 struct kvm_debugregs dbgregs;
3412
3413 r = -EFAULT;
3414 if (copy_from_user(&dbgregs, argp,
3415 sizeof(struct kvm_debugregs)))
3416 break;
3417
3418 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3419 break;
3420 }
2d5b5a66 3421 case KVM_GET_XSAVE: {
d1ac91d8 3422 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3423 r = -ENOMEM;
d1ac91d8 3424 if (!u.xsave)
2d5b5a66
SY		 3425 break;
3426
d1ac91d8 3427 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3428
3429 r = -EFAULT;
d1ac91d8 3430 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3431 break;
3432 r = 0;
3433 break;
3434 }
3435 case KVM_SET_XSAVE: {
ff5c2c03 3436 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3437 if (IS_ERR(u.xsave))
3438 return PTR_ERR(u.xsave);
2d5b5a66 3439
d1ac91d8 3440 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3441 break;
3442 }
3443 case KVM_GET_XCRS: {
d1ac91d8 3444 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3445 r = -ENOMEM;
d1ac91d8 3446 if (!u.xcrs)
2d5b5a66
SY		 3447 break;
3448
d1ac91d8 3449 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3450
3451 r = -EFAULT;
d1ac91d8 3452 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3453 sizeof(struct kvm_xcrs)))
3454 break;
3455 r = 0;
3456 break;
3457 }
3458 case KVM_SET_XCRS: {
ff5c2c03 3459 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3460 if (IS_ERR(u.xcrs))
3461 return PTR_ERR(u.xcrs);
2d5b5a66 3462
d1ac91d8 3463 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3464 break;
3465 }
92a1f12d
JR		 3466 case KVM_SET_TSC_KHZ: {
3467 u32 user_tsc_khz;
3468
3469 r = -EINVAL;
92a1f12d
JR		 3470 user_tsc_khz = (u32)arg;
3471
3472 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3473 goto out;
3474
cc578287
ZA		 3475 if (user_tsc_khz == 0)
3476 user_tsc_khz = tsc_khz;
3477
381d585c
HZ		 3478 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3479 r = 0;
92a1f12d 3480
92a1f12d
JR		 3481 goto out;
3482 }
3483 case KVM_GET_TSC_KHZ: {
cc578287 3484 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3485 goto out;
3486 }
1c0b28c2
EM		 3487 case KVM_KVMCLOCK_CTRL: {
3488 r = kvm_set_guest_paused(vcpu);
3489 goto out;
3490 }
5c919412
AS		 3491 case KVM_ENABLE_CAP: {
3492 struct kvm_enable_cap cap;
3493
3494 r = -EFAULT;
3495 if (copy_from_user(&cap, argp, sizeof(cap)))
3496 goto out;
3497 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3498 break;
3499 }
313a3dc7
CO		 3500 default:
3501 r = -EINVAL;
3502 }
3503out:
d1ac91d8 3504 kfree(u.buffer);
313a3dc7
CO		 3505 return r;
3506}
3507
5b1c1493
CO		 3508int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3509{
3510 return VM_FAULT_SIGBUS;
3511}
3512
1fe779f8
CO		 3513static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3514{
3515 int ret;
3516
3517 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3518 return -EINVAL;
1fe779f8
CO		 3519 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3520 return ret;
3521}
3522
b927a3ce
SY		 3523static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3524 u64 ident_addr)
3525{
3526 kvm->arch.ept_identity_map_addr = ident_addr;
3527 return 0;
3528}
3529
1fe779f8
CO		 3530static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3531 u32 kvm_nr_mmu_pages)
3532{
3533 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3534 return -EINVAL;
3535
79fac95e 3536 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3537
3538 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3539 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3540
79fac95e 3541 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3542 return 0;
3543}
3544
3545static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3546{
39de71ec 3547 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3548}
3549
1fe779f8
CO		 3550static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3551{
3552 int r;
3553
3554 r = 0;
3555 switch (chip->chip_id) {
3556 case KVM_IRQCHIP_PIC_MASTER:
3557 memcpy(&chip->chip.pic,
3558 &pic_irqchip(kvm)->pics[0],
3559 sizeof(struct kvm_pic_state));
3560 break;
3561 case KVM_IRQCHIP_PIC_SLAVE:
3562 memcpy(&chip->chip.pic,
3563 &pic_irqchip(kvm)->pics[1],
3564 sizeof(struct kvm_pic_state));
3565 break;
3566 case KVM_IRQCHIP_IOAPIC:
eba0226b 3567 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3568 break;
3569 default:
3570 r = -EINVAL;
3571 break;
3572 }
3573 return r;
3574}
3575
3576static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3577{
3578 int r;
3579
3580 r = 0;
3581 switch (chip->chip_id) {
3582 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3583 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3584 memcpy(&pic_irqchip(kvm)->pics[0],
3585 &chip->chip.pic,
3586 sizeof(struct kvm_pic_state));
f4f51050 3587 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3588 break;
3589 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3590 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3591 memcpy(&pic_irqchip(kvm)->pics[1],
3592 &chip->chip.pic,
3593 sizeof(struct kvm_pic_state));
f4f51050 3594 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3595 break;
3596 case KVM_IRQCHIP_IOAPIC:
eba0226b 3597 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3598 break;
3599 default:
3600 r = -EINVAL;
3601 break;
3602 }
3603 kvm_pic_update_irq(pic_irqchip(kvm));
3604 return r;
3605}
3606
e0f63cb9
SY		 3607static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3608{
894a9c55 3609 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3610 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3611 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3612 return 0;
e0f63cb9
SY		 3613}
3614
3615static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3616{
0185604c 3617 int i;
894a9c55 3618 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3619 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
0185604c
AH		 3620 for (i = 0; i < 3; i++)
3621 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
e9f42757 3622 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3623 return 0;
e9f42757
BK		 3624}
3625
3626static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3627{
e9f42757
BK		 3628 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3629 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3630 sizeof(ps->channels));
3631 ps->flags = kvm->arch.vpit->pit_state.flags;
3632 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3633 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3634 return 0;
e9f42757
BK		 3635}
3636
3637static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3638{
2da29bcc 3639 int start = 0;
0185604c 3640 int i;
e9f42757
BK		 3641 u32 prev_legacy, cur_legacy;
3642 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3643 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3644 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3645 if (!prev_legacy && cur_legacy)
3646 start = 1;
3647 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3648 sizeof(kvm->arch.vpit->pit_state.channels));
3649 kvm->arch.vpit->pit_state.flags = ps->flags;
0185604c 3650 for (i = 0; i < 3; i++)
e5e57e7a
PB		 3651 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count,
3652 start && i == 0);
894a9c55 3653 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3654 return 0;
e0f63cb9
SY		 3655}
3656
52d939a0
MT		 3657static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3658 struct kvm_reinject_control *control)
3659{
3660 if (!kvm->arch.vpit)
3661 return -ENXIO;
894a9c55 3662 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3663 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3664 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3665 return 0;
3666}
3667
95d4c16c 3668/**
60c34612
TY		 3669 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3670 * @kvm: kvm instance
3671 * @log: slot id and address to which we copy the log
95d4c16c 3672 *
e108ff2f
PB		 3673 * Steps 1-4 below provide general overview of dirty page logging. See
3674 * kvm_get_dirty_log_protect() function description for additional details.
3675 *
3676 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3677 * always flush the TLB (step 4) even if previous step failed and the dirty
3678 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3679 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3680 * writes will be marked dirty for next log read.
95d4c16c 3681 *
60c34612
TY		 3682 * 1. Take a snapshot of the bit and clear it if needed.
3683 * 2. Write protect the corresponding page.
e108ff2f
PB		 3684 * 3. Copy the snapshot to the userspace.
3685 * 4. Flush TLB's if needed.
5bb064dc 3686 */
60c34612 3687int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3688{
60c34612 3689 bool is_dirty = false;
e108ff2f 3690 int r;
5bb064dc 3691
79fac95e 3692 mutex_lock(&kvm->slots_lock);
5bb064dc 3693
88178fd4
KH		 3694 /*
3695 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3696 */
3697 if (kvm_x86_ops->flush_log_dirty)
3698 kvm_x86_ops->flush_log_dirty(kvm);
3699
e108ff2f 3700 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3701
3702 /*
3703 * All the TLBs can be flushed out of mmu lock, see the comments in
3704 * kvm_mmu_slot_remove_write_access().
3705 */
e108ff2f 3706 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3707 if (is_dirty)
3708 kvm_flush_remote_tlbs(kvm);
3709
79fac95e 3710 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3711 return r;
3712}
3713
aa2fbe6d
YZ		 3714int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3715 bool line_status)
23d43cf9
CD		 3716{
3717 if (!irqchip_in_kernel(kvm))
3718 return -ENXIO;
3719
3720 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3721 irq_event->irq, irq_event->level,
3722 line_status);
23d43cf9
CD		 3723 return 0;
3724}
3725
90de4a18
NA		 3726static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3727 struct kvm_enable_cap *cap)
3728{
3729 int r;
3730
3731 if (cap->flags)
3732 return -EINVAL;
3733
3734 switch (cap->cap) {
3735 case KVM_CAP_DISABLE_QUIRKS:
3736 kvm->arch.disabled_quirks = cap->args[0];
3737 r = 0;
3738 break;
49df6397
SR		 3739 case KVM_CAP_SPLIT_IRQCHIP: {
3740 mutex_lock(&kvm->lock);
b053b2ae
SR		 3741 r = -EINVAL;
3742 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3743 goto split_irqchip_unlock;
49df6397
SR		 3744 r = -EEXIST;
3745 if (irqchip_in_kernel(kvm))
3746 goto split_irqchip_unlock;
3747 if (atomic_read(&kvm->online_vcpus))
3748 goto split_irqchip_unlock;
3749 r = kvm_setup_empty_irq_routing(kvm);
3750 if (r)
3751 goto split_irqchip_unlock;
3752 /* Pairs with irqchip_in_kernel. */
3753 smp_wmb();
3754 kvm->arch.irqchip_split = true;
b053b2ae 3755 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3756 r = 0;
3757split_irqchip_unlock:
3758 mutex_unlock(&kvm->lock);
3759 break;
3760 }
90de4a18
NA		 3761 default:
3762 r = -EINVAL;
3763 break;
3764 }
3765 return r;
3766}
3767
1fe779f8
CO		 3768long kvm_arch_vm_ioctl(struct file *filp,
3769 unsigned int ioctl, unsigned long arg)
3770{
3771 struct kvm *kvm = filp->private_data;
3772 void __user *argp = (void __user *)arg;
367e1319 3773 int r = -ENOTTY;
f0d66275
DH		 3774 /*
3775 * This union makes it completely explicit to gcc-3.x
3776 * that these two variables' stack usage should be
3777 * combined, not added together.
3778 */
3779 union {
3780 struct kvm_pit_state ps;
e9f42757 3781 struct kvm_pit_state2 ps2;
c5ff41ce 3782 struct kvm_pit_config pit_config;
f0d66275 3783 } u;
1fe779f8
CO		 3784
3785 switch (ioctl) {
3786 case KVM_SET_TSS_ADDR:
3787 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3788 break;
b927a3ce
SY		 3789 case KVM_SET_IDENTITY_MAP_ADDR: {
3790 u64 ident_addr;
3791
3792 r = -EFAULT;
3793 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3794 goto out;
3795 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3796 break;
3797 }
1fe779f8
CO		 3798 case KVM_SET_NR_MMU_PAGES:
3799 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3800 break;
3801 case KVM_GET_NR_MMU_PAGES:
3802 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3803 break;
3ddea128
MT		 3804 case KVM_CREATE_IRQCHIP: {
3805 struct kvm_pic *vpic;
3806
3807 mutex_lock(&kvm->lock);
3808 r = -EEXIST;
3809 if (kvm->arch.vpic)
3810 goto create_irqchip_unlock;
3e515705
AK		 3811 r = -EINVAL;
3812 if (atomic_read(&kvm->online_vcpus))
3813 goto create_irqchip_unlock;
1fe779f8 3814 r = -ENOMEM;
3ddea128
MT		 3815 vpic = kvm_create_pic(kvm);
3816 if (vpic) {
1fe779f8
CO		 3817 r = kvm_ioapic_init(kvm);
3818 if (r) {
175504cd 3819 mutex_lock(&kvm->slots_lock);
71ba994c 3820 kvm_destroy_pic(vpic);
175504cd 3821 mutex_unlock(&kvm->slots_lock);
3ddea128 3822 goto create_irqchip_unlock;
1fe779f8
CO		 3823 }
3824 } else
3ddea128 3825 goto create_irqchip_unlock;
399ec807
AK		 3826 r = kvm_setup_default_irq_routing(kvm);
3827 if (r) {
175504cd 3828 mutex_lock(&kvm->slots_lock);
3ddea128 3829 mutex_lock(&kvm->irq_lock);
72bb2fcd 3830 kvm_ioapic_destroy(kvm);
71ba994c 3831 kvm_destroy_pic(vpic);
3ddea128 3832 mutex_unlock(&kvm->irq_lock);
175504cd 3833 mutex_unlock(&kvm->slots_lock);
71ba994c 3834 goto create_irqchip_unlock;
399ec807 3835 }
71ba994c
PB		 3836 /* Write kvm->irq_routing before kvm->arch.vpic. */
3837 smp_wmb();
3838 kvm->arch.vpic = vpic;
3ddea128
MT		 3839 create_irqchip_unlock:
3840 mutex_unlock(&kvm->lock);
1fe779f8 3841 break;
3ddea128 3842 }
7837699f 3843 case KVM_CREATE_PIT:
c5ff41ce
JK		 3844 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3845 goto create_pit;
3846 case KVM_CREATE_PIT2:
3847 r = -EFAULT;
3848 if (copy_from_user(&u.pit_config, argp,
3849 sizeof(struct kvm_pit_config)))
3850 goto out;
3851 create_pit:
79fac95e 3852 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3853 r = -EEXIST;
3854 if (kvm->arch.vpit)
3855 goto create_pit_unlock;
7837699f 3856 r = -ENOMEM;
c5ff41ce 3857 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3858 if (kvm->arch.vpit)
3859 r = 0;
269e05e4 3860 create_pit_unlock:
79fac95e 3861 mutex_unlock(&kvm->slots_lock);
7837699f 3862 break;
1fe779f8
CO		 3863 case KVM_GET_IRQCHIP: {
3864 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3865 struct kvm_irqchip *chip;
1fe779f8 3866
ff5c2c03
SL		 3867 chip = memdup_user(argp, sizeof(*chip));
3868 if (IS_ERR(chip)) {
3869 r = PTR_ERR(chip);
1fe779f8 3870 goto out;
ff5c2c03
SL		 3871 }
3872
1fe779f8 3873 r = -ENXIO;
49df6397 3874 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3875 goto get_irqchip_out;
3876 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3877 if (r)
f0d66275 3878 goto get_irqchip_out;
1fe779f8 3879 r = -EFAULT;
f0d66275
DH		 3880 if (copy_to_user(argp, chip, sizeof *chip))
3881 goto get_irqchip_out;
1fe779f8 3882 r = 0;
f0d66275
DH		 3883 get_irqchip_out:
3884 kfree(chip);
1fe779f8
CO		 3885 break;
3886 }
3887 case KVM_SET_IRQCHIP: {
3888 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3889 struct kvm_irqchip *chip;
1fe779f8 3890
ff5c2c03
SL		 3891 chip = memdup_user(argp, sizeof(*chip));
3892 if (IS_ERR(chip)) {
3893 r = PTR_ERR(chip);
1fe779f8 3894 goto out;
ff5c2c03
SL		 3895 }
3896
1fe779f8 3897 r = -ENXIO;
49df6397 3898 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3899 goto set_irqchip_out;
3900 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3901 if (r)
f0d66275 3902 goto set_irqchip_out;
1fe779f8 3903 r = 0;
f0d66275
DH		 3904 set_irqchip_out:
3905 kfree(chip);
1fe779f8
CO		 3906 break;
3907 }
e0f63cb9 3908 case KVM_GET_PIT: {
e0f63cb9 3909 r = -EFAULT;
f0d66275 3910 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3911 goto out;
3912 r = -ENXIO;
3913 if (!kvm->arch.vpit)
3914 goto out;
f0d66275 3915 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3916 if (r)
3917 goto out;
3918 r = -EFAULT;
f0d66275 3919 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3920 goto out;
3921 r = 0;
3922 break;
3923 }
3924 case KVM_SET_PIT: {
e0f63cb9 3925 r = -EFAULT;
f0d66275 3926 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3927 goto out;
3928 r = -ENXIO;
3929 if (!kvm->arch.vpit)
3930 goto out;
f0d66275 3931 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3932 break;
3933 }
e9f42757
BK		 3934 case KVM_GET_PIT2: {
3935 r = -ENXIO;
3936 if (!kvm->arch.vpit)
3937 goto out;
3938 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3939 if (r)
3940 goto out;
3941 r = -EFAULT;
3942 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3943 goto out;
3944 r = 0;
3945 break;
3946 }
3947 case KVM_SET_PIT2: {
3948 r = -EFAULT;
3949 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3950 goto out;
3951 r = -ENXIO;
3952 if (!kvm->arch.vpit)
3953 goto out;
3954 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3955 break;
3956 }
52d939a0
MT		 3957 case KVM_REINJECT_CONTROL: {
3958 struct kvm_reinject_control control;
3959 r = -EFAULT;
3960 if (copy_from_user(&control, argp, sizeof(control)))
3961 goto out;
3962 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3963 break;
3964 }
d71ba788
PB		 3965 case KVM_SET_BOOT_CPU_ID:
3966 r = 0;
3967 mutex_lock(&kvm->lock);
3968 if (atomic_read(&kvm->online_vcpus) != 0)
3969 r = -EBUSY;
3970 else
3971 kvm->arch.bsp_vcpu_id = arg;
3972 mutex_unlock(&kvm->lock);
3973 break;
ffde22ac
ES		 3974 case KVM_XEN_HVM_CONFIG: {
3975 r = -EFAULT;
3976 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3977 sizeof(struct kvm_xen_hvm_config)))
3978 goto out;
3979 r = -EINVAL;
3980 if (kvm->arch.xen_hvm_config.flags)
3981 goto out;
3982 r = 0;
3983 break;
3984 }
afbcf7ab 3985 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3986 struct kvm_clock_data user_ns;
3987 u64 now_ns;
3988 s64 delta;
3989
3990 r = -EFAULT;
3991 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3992 goto out;
3993
3994 r = -EINVAL;
3995 if (user_ns.flags)
3996 goto out;
3997
3998 r = 0;
395c6b0a 3999 local_irq_disable();
759379dd 4000 now_ns = get_kernel_ns();
afbcf7ab 4001 delta = user_ns.clock - now_ns;
395c6b0a 4002 local_irq_enable();
afbcf7ab 4003 kvm->arch.kvmclock_offset = delta;
2e762ff7 4004 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4005 break;
4006 }
4007 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4008 struct kvm_clock_data user_ns;
4009 u64 now_ns;
4010
395c6b0a 4011 local_irq_disable();
759379dd 4012 now_ns = get_kernel_ns();
afbcf7ab 4013 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4014 local_irq_enable();
afbcf7ab 4015 user_ns.flags = 0;
97e69aa6 4016 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4017
4018 r = -EFAULT;
4019 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4020 goto out;
4021 r = 0;
4022 break;
4023 }
90de4a18
NA		 4024 case KVM_ENABLE_CAP: {
4025 struct kvm_enable_cap cap;
afbcf7ab 4026
90de4a18
NA		 4027 r = -EFAULT;
4028 if (copy_from_user(&cap, argp, sizeof(cap)))
4029 goto out;
4030 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4031 break;
4032 }
1fe779f8 4033 default:
c274e03a 4034 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4035 }
4036out:
4037 return r;
4038}
4039
a16b043c 4040static void kvm_init_msr_list(void)
043405e1
CO		 4041{
4042 u32 dummy[2];
4043 unsigned i, j;
4044
62ef68bb 4045 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4046 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4047 continue;
93c4adc7
PB		 4048
4049 /*
4050 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4051 * to the guests in some cases.
93c4adc7
PB		 4052 */
4053 switch (msrs_to_save[i]) {
4054 case MSR_IA32_BNDCFGS:
4055 if (!kvm_x86_ops->mpx_supported())
4056 continue;
4057 break;
9dbe6cf9
PB		 4058 case MSR_TSC_AUX:
4059 if (!kvm_x86_ops->rdtscp_supported())
4060 continue;
4061 break;
93c4adc7
PB		 4062 default:
4063 break;
4064 }
4065
043405e1
CO		 4066 if (j < i)
4067 msrs_to_save[j] = msrs_to_save[i];
4068 j++;
4069 }
4070 num_msrs_to_save = j;
62ef68bb
PB		 4071
4072 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4073 switch (emulated_msrs[i]) {
6d396b55
PB		 4074 case MSR_IA32_SMBASE:
4075 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4076 continue;
4077 break;
62ef68bb
PB		 4078 default:
4079 break;
4080 }
4081
4082 if (j < i)
4083 emulated_msrs[j] = emulated_msrs[i];
4084 j++;
4085 }
4086 num_emulated_msrs = j;
043405e1
CO		 4087}
4088
bda9020e
MT		 4089static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4090 const void *v)
bbd9b64e 4091{
70252a10
AK		 4092 int handled = 0;
4093 int n;
4094
4095 do {
4096 n = min(len, 8);
4097 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4098 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4099 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4100 break;
4101 handled += n;
4102 addr += n;
4103 len -= n;
4104 v += n;
4105 } while (len);
bbd9b64e 4106
70252a10 4107 return handled;
bbd9b64e
CO		 4108}
4109
bda9020e 4110static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4111{
70252a10
AK		 4112 int handled = 0;
4113 int n;
4114
4115 do {
4116 n = min(len, 8);
4117 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4118 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4119 addr, n, v))
4120 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4121 break;
4122 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4123 handled += n;
4124 addr += n;
4125 len -= n;
4126 v += n;
4127 } while (len);
bbd9b64e 4128
70252a10 4129 return handled;
bbd9b64e
CO		 4130}
4131
2dafc6c2
GN		 4132static void kvm_set_segment(struct kvm_vcpu *vcpu,
4133 struct kvm_segment *var, int seg)
4134{
4135 kvm_x86_ops->set_segment(vcpu, var, seg);
4136}
4137
4138void kvm_get_segment(struct kvm_vcpu *vcpu,
4139 struct kvm_segment *var, int seg)
4140{
4141 kvm_x86_ops->get_segment(vcpu, var, seg);
4142}
4143
54987b7a
PB		 4144gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4145 struct x86_exception *exception)
02f59dc9
JR		 4146{
4147 gpa_t t_gpa;
02f59dc9
JR		 4148
4149 BUG_ON(!mmu_is_nested(vcpu));
4150
4151 /* NPT walks are always user-walks */
4152 access |= PFERR_USER_MASK;
54987b7a 4153 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4154
4155 return t_gpa;
4156}
4157
ab9ae313
AK		 4158gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4159 struct x86_exception *exception)
1871c602
GN		 4160{
4161 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4162 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4163}
4164
ab9ae313
AK		 4165 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4166 struct x86_exception *exception)
1871c602
GN		 4167{
4168 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4169 access |= PFERR_FETCH_MASK;
ab9ae313 4170 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4171}
4172
ab9ae313
AK		 4173gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4174 struct x86_exception *exception)
1871c602
GN		 4175{
4176 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4177 access |= PFERR_WRITE_MASK;
ab9ae313 4178 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4179}
4180
4181/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4182gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4183 struct x86_exception *exception)
1871c602 4184{
ab9ae313 4185 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4186}
4187
4188static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4189 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4190 struct x86_exception *exception)
bbd9b64e
CO		 4191{
4192 void *data = val;
10589a46 4193 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4194
4195 while (bytes) {
14dfe855 4196 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4197 exception);
bbd9b64e 4198 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4199 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4200 int ret;
4201
bcc55cba 4202 if (gpa == UNMAPPED_GVA)
ab9ae313 4203 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4204 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4205 offset, toread);
10589a46 4206 if (ret < 0) {
c3cd7ffa 4207 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4208 goto out;
4209 }
bbd9b64e 4210
77c2002e
IE		 4211 bytes -= toread;
4212 data += toread;
4213 addr += toread;
bbd9b64e 4214 }
10589a46 4215out:
10589a46 4216 return r;
bbd9b64e 4217}
77c2002e 4218
1871c602 4219/* used for instruction fetching */
0f65dd70
AK		 4220static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4221 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4222 struct x86_exception *exception)
1871c602 4223{
0f65dd70 4224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4225 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4226 unsigned offset;
4227 int ret;
0f65dd70 4228
44583cba
PB		 4229 /* Inline kvm_read_guest_virt_helper for speed. */
4230 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4231 exception);
4232 if (unlikely(gpa == UNMAPPED_GVA))
4233 return X86EMUL_PROPAGATE_FAULT;
4234
4235 offset = addr & (PAGE_SIZE-1);
4236 if (WARN_ON(offset + bytes > PAGE_SIZE))
4237 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4238 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4239 offset, bytes);
44583cba
PB		 4240 if (unlikely(ret < 0))
4241 return X86EMUL_IO_NEEDED;
4242
4243 return X86EMUL_CONTINUE;
1871c602
GN		 4244}
4245
064aea77 4246int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4247 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4248 struct x86_exception *exception)
1871c602 4249{
0f65dd70 4250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4251 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4252
1871c602 4253 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4254 exception);
1871c602 4255}
064aea77 4256EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4257
0f65dd70
AK		 4258static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4259 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4260 struct x86_exception *exception)
1871c602 4261{
0f65dd70 4262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4263 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4264}
4265
7a036a6f
RK		 4266static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4267 unsigned long addr, void *val, unsigned int bytes)
4268{
4269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4270 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4271
4272 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4273}
4274
6a4d7550 4275int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4276 gva_t addr, void *val,
2dafc6c2 4277 unsigned int bytes,
bcc55cba 4278 struct x86_exception *exception)
77c2002e 4279{
0f65dd70 4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4281 void *data = val;
4282 int r = X86EMUL_CONTINUE;
4283
4284 while (bytes) {
14dfe855
JR		 4285 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4286 PFERR_WRITE_MASK,
ab9ae313 4287 exception);
77c2002e
IE		 4288 unsigned offset = addr & (PAGE_SIZE-1);
4289 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4290 int ret;
4291
bcc55cba 4292 if (gpa == UNMAPPED_GVA)
ab9ae313 4293 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4294 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4295 if (ret < 0) {
c3cd7ffa 4296 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4297 goto out;
4298 }
4299
4300 bytes -= towrite;
4301 data += towrite;
4302 addr += towrite;
4303 }
4304out:
4305 return r;
4306}
6a4d7550 4307EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4308
af7cc7d1
XG		 4309static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4310 gpa_t *gpa, struct x86_exception *exception,
4311 bool write)
4312{
97d64b78
AK		 4313 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4314 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4315
97d64b78 4316 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4317 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4318 vcpu->arch.access, access)) {
bebb106a
XG		 4319 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4320 (gva & (PAGE_SIZE - 1));
4f022648 4321 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4322 return 1;
4323 }
4324
af7cc7d1
XG		 4325 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4326
4327 if (*gpa == UNMAPPED_GVA)
4328 return -1;
4329
4330 /* For APIC access vmexit */
4331 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4332 return 1;
4333
4f022648
XG		 4334 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4335 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4336 return 1;
4f022648 4337 }
bebb106a 4338
af7cc7d1
XG		 4339 return 0;
4340}
4341
3200f405 4342int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4343 const void *val, int bytes)
bbd9b64e
CO		 4344{
4345 int ret;
4346
54bf36aa 4347 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4348 if (ret < 0)
bbd9b64e 4349 return 0;
f57f2ef5 4350 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4351 return 1;
4352}
4353
77d197b2
XG		 4354struct read_write_emulator_ops {
4355 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4356 int bytes);
4357 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4358 void *val, int bytes);
4359 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4360 int bytes, void *val);
4361 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4362 void *val, int bytes);
4363 bool write;
4364};
4365
4366static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4367{
4368 if (vcpu->mmio_read_completed) {
77d197b2 4369 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4370 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4371 vcpu->mmio_read_completed = 0;
4372 return 1;
4373 }
4374
4375 return 0;
4376}
4377
4378static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4379 void *val, int bytes)
4380{
54bf36aa 4381 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4382}
4383
4384static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4385 void *val, int bytes)
4386{
4387 return emulator_write_phys(vcpu, gpa, val, bytes);
4388}
4389
4390static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4391{
4392 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4393 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4394}
4395
4396static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4397 void *val, int bytes)
4398{
4399 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4400 return X86EMUL_IO_NEEDED;
4401}
4402
4403static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 void *val, int bytes)
4405{
f78146b0
AK		 4406 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4407
87da7e66 4408 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4409 return X86EMUL_CONTINUE;
4410}
4411
0fbe9b0b 4412static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4413 .read_write_prepare = read_prepare,
4414 .read_write_emulate = read_emulate,
4415 .read_write_mmio = vcpu_mmio_read,
4416 .read_write_exit_mmio = read_exit_mmio,
4417};
4418
0fbe9b0b 4419static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4420 .read_write_emulate = write_emulate,
4421 .read_write_mmio = write_mmio,
4422 .read_write_exit_mmio = write_exit_mmio,
4423 .write = true,
4424};
4425
22388a3c
XG		 4426static int emulator_read_write_onepage(unsigned long addr, void *val,
4427 unsigned int bytes,
4428 struct x86_exception *exception,
4429 struct kvm_vcpu *vcpu,
0fbe9b0b 4430 const struct read_write_emulator_ops *ops)
bbd9b64e 4431{
af7cc7d1
XG		 4432 gpa_t gpa;
4433 int handled, ret;
22388a3c 4434 bool write = ops->write;
f78146b0 4435 struct kvm_mmio_fragment *frag;
10589a46 4436
22388a3c 4437 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4438
af7cc7d1 4439 if (ret < 0)
bbd9b64e 4440 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4441
4442 /* For APIC access vmexit */
af7cc7d1 4443 if (ret)
bbd9b64e
CO		 4444 goto mmio;
4445
22388a3c 4446 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4447 return X86EMUL_CONTINUE;
4448
4449mmio:
4450 /*
4451 * Is this MMIO handled locally?
4452 */
22388a3c 4453 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4454 if (handled == bytes)
bbd9b64e 4455 return X86EMUL_CONTINUE;
bbd9b64e 4456
70252a10
AK		 4457 gpa += handled;
4458 bytes -= handled;
4459 val += handled;
4460
87da7e66
XG		 4461 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4462 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4463 frag->gpa = gpa;
4464 frag->data = val;
4465 frag->len = bytes;
f78146b0 4466 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4467}
4468
52eb5a6d
XL		 4469static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4470 unsigned long addr,
22388a3c
XG		 4471 void *val, unsigned int bytes,
4472 struct x86_exception *exception,
0fbe9b0b 4473 const struct read_write_emulator_ops *ops)
bbd9b64e 4474{
0f65dd70 4475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4476 gpa_t gpa;
4477 int rc;
4478
4479 if (ops->read_write_prepare &&
4480 ops->read_write_prepare(vcpu, val, bytes))
4481 return X86EMUL_CONTINUE;
4482
4483 vcpu->mmio_nr_fragments = 0;
0f65dd70 4484
bbd9b64e
CO		 4485 /* Crossing a page boundary? */
4486 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4487 int now;
bbd9b64e
CO		 4488
4489 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4490 rc = emulator_read_write_onepage(addr, val, now, exception,
4491 vcpu, ops);
4492
bbd9b64e
CO		 4493 if (rc != X86EMUL_CONTINUE)
4494 return rc;
4495 addr += now;
bac15531
NA		 4496 if (ctxt->mode != X86EMUL_MODE_PROT64)
4497 addr = (u32)addr;
bbd9b64e
CO		 4498 val += now;
4499 bytes -= now;
4500 }
22388a3c 4501
f78146b0
AK		 4502 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4503 vcpu, ops);
4504 if (rc != X86EMUL_CONTINUE)
4505 return rc;
4506
4507 if (!vcpu->mmio_nr_fragments)
4508 return rc;
4509
4510 gpa = vcpu->mmio_fragments[0].gpa;
4511
4512 vcpu->mmio_needed = 1;
4513 vcpu->mmio_cur_fragment = 0;
4514
87da7e66 4515 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4516 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4517 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4518 vcpu->run->mmio.phys_addr = gpa;
4519
4520 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4521}
4522
4523static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4524 unsigned long addr,
4525 void *val,
4526 unsigned int bytes,
4527 struct x86_exception *exception)
4528{
4529 return emulator_read_write(ctxt, addr, val, bytes,
4530 exception, &read_emultor);
4531}
4532
52eb5a6d 4533static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4534 unsigned long addr,
4535 const void *val,
4536 unsigned int bytes,
4537 struct x86_exception *exception)
4538{
4539 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4540 exception, &write_emultor);
bbd9b64e 4541}
bbd9b64e 4542
daea3e73
AK		 4543#define CMPXCHG_TYPE(t, ptr, old, new) \
4544 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4545
4546#ifdef CONFIG_X86_64
4547# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4548#else
4549# define CMPXCHG64(ptr, old, new) \
9749a6c0 4550 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4551#endif
4552
0f65dd70
AK		 4553static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4554 unsigned long addr,
bbd9b64e
CO		 4555 const void *old,
4556 const void *new,
4557 unsigned int bytes,
0f65dd70 4558 struct x86_exception *exception)
bbd9b64e 4559{
0f65dd70 4560 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4561 gpa_t gpa;
4562 struct page *page;
4563 char *kaddr;
4564 bool exchanged;
2bacc55c 4565
daea3e73
AK		 4566 /* guests cmpxchg8b have to be emulated atomically */
4567 if (bytes > 8 || (bytes & (bytes - 1)))
4568 goto emul_write;
10589a46 4569
daea3e73 4570 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4571
daea3e73
AK		 4572 if (gpa == UNMAPPED_GVA ||
4573 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4574 goto emul_write;
2bacc55c 4575
daea3e73
AK		 4576 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4577 goto emul_write;
72dc67a6 4578
54bf36aa 4579 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4580 if (is_error_page(page))
c19b8bd6 4581 goto emul_write;
72dc67a6 4582
8fd75e12 4583 kaddr = kmap_atomic(page);
daea3e73
AK		 4584 kaddr += offset_in_page(gpa);
4585 switch (bytes) {
4586 case 1:
4587 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4588 break;
4589 case 2:
4590 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4591 break;
4592 case 4:
4593 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4594 break;
4595 case 8:
4596 exchanged = CMPXCHG64(kaddr, old, new);
4597 break;
4598 default:
4599 BUG();
2bacc55c 4600 }
8fd75e12 4601 kunmap_atomic(kaddr);
daea3e73
AK		 4602 kvm_release_page_dirty(page);
4603
4604 if (!exchanged)
4605 return X86EMUL_CMPXCHG_FAILED;
4606
54bf36aa 4607 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4608 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4609
4610 return X86EMUL_CONTINUE;
4a5f48f6 4611
3200f405 4612emul_write:
daea3e73 4613 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4614
0f65dd70 4615 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4616}
4617
cf8f70bf
GN		 4618static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4619{
4620 /* TODO: String I/O for in kernel device */
4621 int r;
4622
4623 if (vcpu->arch.pio.in)
e32edf4f 4624 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4625 vcpu->arch.pio.size, pd);
4626 else
e32edf4f 4627 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4628 vcpu->arch.pio.port, vcpu->arch.pio.size,
4629 pd);
4630 return r;
4631}
4632
6f6fbe98
XG		 4633static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4634 unsigned short port, void *val,
4635 unsigned int count, bool in)
cf8f70bf 4636{
cf8f70bf 4637 vcpu->arch.pio.port = port;
6f6fbe98 4638 vcpu->arch.pio.in = in;
7972995b 4639 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4640 vcpu->arch.pio.size = size;
4641
4642 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4643 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4644 return 1;
4645 }
4646
4647 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4648 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4649 vcpu->run->io.size = size;
4650 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4651 vcpu->run->io.count = count;
4652 vcpu->run->io.port = port;
4653
4654 return 0;
4655}
4656
6f6fbe98
XG		 4657static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4658 int size, unsigned short port, void *val,
4659 unsigned int count)
cf8f70bf 4660{
ca1d4a9e 4661 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4662 int ret;
ca1d4a9e 4663
6f6fbe98
XG		 4664 if (vcpu->arch.pio.count)
4665 goto data_avail;
cf8f70bf 4666
6f6fbe98
XG		 4667 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4668 if (ret) {
4669data_avail:
4670 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4671 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4672 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4673 return 1;
4674 }
4675
cf8f70bf
GN		 4676 return 0;
4677}
4678
6f6fbe98
XG		 4679static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4680 int size, unsigned short port,
4681 const void *val, unsigned int count)
4682{
4683 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4684
4685 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4686 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4687 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4688}
4689
bbd9b64e
CO		 4690static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4691{
4692 return kvm_x86_ops->get_segment_base(vcpu, seg);
4693}
4694
3cb16fe7 4695static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4696{
3cb16fe7 4697 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4698}
4699
5cb56059 4700int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4701{
4702 if (!need_emulate_wbinvd(vcpu))
4703 return X86EMUL_CONTINUE;
4704
4705 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4706 int cpu = get_cpu();
4707
4708 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4709 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4710 wbinvd_ipi, NULL, 1);
2eec7343 4711 put_cpu();
f5f48ee1 4712 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4713 } else
4714 wbinvd();
f5f48ee1
SY		 4715 return X86EMUL_CONTINUE;
4716}
5cb56059
JS		 4717
4718int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4719{
4720 kvm_x86_ops->skip_emulated_instruction(vcpu);
4721 return kvm_emulate_wbinvd_noskip(vcpu);
4722}
f5f48ee1
SY		 4723EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4724
5cb56059
JS		 4725
4726
bcaf5cc5
AK		 4727static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4728{
5cb56059 4729 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4730}
4731
52eb5a6d
XL		 4732static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4733 unsigned long *dest)
bbd9b64e 4734{
16f8a6f9 4735 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4736}
4737
52eb5a6d
XL		 4738static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4739 unsigned long value)
bbd9b64e 4740{
338dbc97 4741
717746e3 4742 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4743}
4744
52a46617 4745static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4746{
52a46617 4747 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4748}
4749
717746e3 4750static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4751{
717746e3 4752 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4753 unsigned long value;
4754
4755 switch (cr) {
4756 case 0:
4757 value = kvm_read_cr0(vcpu);
4758 break;
4759 case 2:
4760 value = vcpu->arch.cr2;
4761 break;
4762 case 3:
9f8fe504 4763 value = kvm_read_cr3(vcpu);
52a46617
GN		 4764 break;
4765 case 4:
4766 value = kvm_read_cr4(vcpu);
4767 break;
4768 case 8:
4769 value = kvm_get_cr8(vcpu);
4770 break;
4771 default:
a737f256 4772 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4773 return 0;
4774 }
4775
4776 return value;
4777}
4778
717746e3 4779static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4780{
717746e3 4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4782 int res = 0;
4783
52a46617
GN		 4784 switch (cr) {
4785 case 0:
49a9b07e 4786 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4787 break;
4788 case 2:
4789 vcpu->arch.cr2 = val;
4790 break;
4791 case 3:
2390218b 4792 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4793 break;
4794 case 4:
a83b29c6 4795 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4796 break;
4797 case 8:
eea1cff9 4798 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4799 break;
4800 default:
a737f256 4801 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4802 res = -1;
52a46617 4803 }
0f12244f
GN		 4804
4805 return res;
52a46617
GN		 4806}
4807
717746e3 4808static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4809{
717746e3 4810 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4811}
4812
4bff1e86 4813static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4814{
4bff1e86 4815 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4816}
4817
4bff1e86 4818static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4819{
4bff1e86 4820 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4821}
4822
1ac9d0cf
AK		 4823static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4824{
4825 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4826}
4827
4828static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4829{
4830 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4831}
4832
4bff1e86
AK		 4833static unsigned long emulator_get_cached_segment_base(
4834 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4835{
4bff1e86 4836 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4837}
4838
1aa36616
AK		 4839static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4840 struct desc_struct *desc, u32 *base3,
4841 int seg)
2dafc6c2
GN		 4842{
4843 struct kvm_segment var;
4844
4bff1e86 4845 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4846 *selector = var.selector;
2dafc6c2 4847
378a8b09
GN		 4848 if (var.unusable) {
4849 memset(desc, 0, sizeof(*desc));
2dafc6c2 4850 return false;
378a8b09 4851 }
2dafc6c2
GN		 4852
4853 if (var.g)
4854 var.limit >>= 12;
4855 set_desc_limit(desc, var.limit);
4856 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4857#ifdef CONFIG_X86_64
4858 if (base3)
4859 *base3 = var.base >> 32;
4860#endif
2dafc6c2
GN		 4861 desc->type = var.type;
4862 desc->s = var.s;
4863 desc->dpl = var.dpl;
4864 desc->p = var.present;
4865 desc->avl = var.avl;
4866 desc->l = var.l;
4867 desc->d = var.db;
4868 desc->g = var.g;
4869
4870 return true;
4871}
4872
1aa36616
AK		 4873static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4874 struct desc_struct *desc, u32 base3,
4875 int seg)
2dafc6c2 4876{
4bff1e86 4877 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4878 struct kvm_segment var;
4879
1aa36616 4880 var.selector = selector;
2dafc6c2 4881 var.base = get_desc_base(desc);
5601d05b
GN		 4882#ifdef CONFIG_X86_64
4883 var.base |= ((u64)base3) << 32;
4884#endif
2dafc6c2
GN		 4885 var.limit = get_desc_limit(desc);
4886 if (desc->g)
4887 var.limit = (var.limit << 12) | 0xfff;
4888 var.type = desc->type;
2dafc6c2
GN		 4889 var.dpl = desc->dpl;
4890 var.db = desc->d;
4891 var.s = desc->s;
4892 var.l = desc->l;
4893 var.g = desc->g;
4894 var.avl = desc->avl;
4895 var.present = desc->p;
4896 var.unusable = !var.present;
4897 var.padding = 0;
4898
4899 kvm_set_segment(vcpu, &var, seg);
4900 return;
4901}
4902
717746e3
AK		 4903static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4904 u32 msr_index, u64 *pdata)
4905{
609e36d3
PB		 4906 struct msr_data msr;
4907 int r;
4908
4909 msr.index = msr_index;
4910 msr.host_initiated = false;
4911 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4912 if (r)
4913 return r;
4914
4915 *pdata = msr.data;
4916 return 0;
717746e3
AK		 4917}
4918
4919static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4920 u32 msr_index, u64 data)
4921{
8fe8ab46
WA		 4922 struct msr_data msr;
4923
4924 msr.data = data;
4925 msr.index = msr_index;
4926 msr.host_initiated = false;
4927 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4928}
4929
64d60670
PB		 4930static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4931{
4932 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4933
4934 return vcpu->arch.smbase;
4935}
4936
4937static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4938{
4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4940
4941 vcpu->arch.smbase = smbase;
4942}
4943
67f4d428
NA		 4944static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4945 u32 pmc)
4946{
c6702c9d 4947 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4948}
4949
222d21aa
AK		 4950static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4951 u32 pmc, u64 *pdata)
4952{
c6702c9d 4953 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4954}
4955
6c3287f7
AK		 4956static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4957{
4958 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4959}
4960
5037f6f3
AK		 4961static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4962{
4963 preempt_disable();
5197b808 4964 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4965 /*
4966 * CR0.TS may reference the host fpu state, not the guest fpu state,
4967 * so it may be clear at this point.
4968 */
4969 clts();
4970}
4971
4972static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4973{
4974 preempt_enable();
4975}
4976
2953538e 4977static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4978 struct x86_instruction_info *info,
c4f035c6
AK		 4979 enum x86_intercept_stage stage)
4980{
2953538e 4981 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4982}
4983
0017f93a 4984static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4985 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4986{
0017f93a 4987 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4988}
4989
dd856efa
AK		 4990static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4991{
4992 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4993}
4994
4995static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4996{
4997 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4998}
4999
801806d9
NA		 5000static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5001{
5002 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5003}
5004
0225fb50 5005static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5006 .read_gpr = emulator_read_gpr,
5007 .write_gpr = emulator_write_gpr,
1871c602 5008 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5009 .write_std = kvm_write_guest_virt_system,
7a036a6f 5010 .read_phys = kvm_read_guest_phys_system,
1871c602 5011 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5012 .read_emulated = emulator_read_emulated,
5013 .write_emulated = emulator_write_emulated,
5014 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5015 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5016 .pio_in_emulated = emulator_pio_in_emulated,
5017 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5018 .get_segment = emulator_get_segment,
5019 .set_segment = emulator_set_segment,
5951c442 5020 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5021 .get_gdt = emulator_get_gdt,
160ce1f1 5022 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5023 .set_gdt = emulator_set_gdt,
5024 .set_idt = emulator_set_idt,
52a46617
GN		 5025 .get_cr = emulator_get_cr,
5026 .set_cr = emulator_set_cr,
9c537244 5027 .cpl = emulator_get_cpl,
35aa5375
GN		 5028 .get_dr = emulator_get_dr,
5029 .set_dr = emulator_set_dr,
64d60670
PB		 5030 .get_smbase = emulator_get_smbase,
5031 .set_smbase = emulator_set_smbase,
717746e3
AK		 5032 .set_msr = emulator_set_msr,
5033 .get_msr = emulator_get_msr,
67f4d428 5034 .check_pmc = emulator_check_pmc,
222d21aa 5035 .read_pmc = emulator_read_pmc,
6c3287f7 5036 .halt = emulator_halt,
bcaf5cc5 5037 .wbinvd = emulator_wbinvd,
d6aa1000 5038 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5039 .get_fpu = emulator_get_fpu,
5040 .put_fpu = emulator_put_fpu,
c4f035c6 5041 .intercept = emulator_intercept,
bdb42f5a 5042 .get_cpuid = emulator_get_cpuid,
801806d9 5043 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5044};
5045
95cb2295
GN		 5046static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5047{
37ccdcbe 5048 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5049 /*
5050 * an sti; sti; sequence only disable interrupts for the first
5051 * instruction. So, if the last instruction, be it emulated or
5052 * not, left the system with the INT_STI flag enabled, it
5053 * means that the last instruction is an sti. We should not
5054 * leave the flag on in this case. The same goes for mov ss
5055 */
37ccdcbe
PB		 5056 if (int_shadow & mask)
5057 mask = 0;
6addfc42 5058 if (unlikely(int_shadow || mask)) {
95cb2295 5059 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5060 if (!mask)
5061 kvm_make_request(KVM_REQ_EVENT, vcpu);
5062 }
95cb2295
GN		 5063}
5064
ef54bcfe 5065static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5066{
5067 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5068 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5069 return kvm_propagate_fault(vcpu, &ctxt->exception);
5070
5071 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5072 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5073 ctxt->exception.error_code);
54b8486f 5074 else
da9cb575 5075 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5076 return false;
54b8486f
GN		 5077}
5078
8ec4722d
MG		 5079static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5080{
adf52235 5081 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5082 int cs_db, cs_l;
5083
8ec4722d
MG		 5084 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5085
adf52235
TY		 5086 ctxt->eflags = kvm_get_rflags(vcpu);
5087 ctxt->eip = kvm_rip_read(vcpu);
5088 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5089 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5090 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5091 cs_db ? X86EMUL_MODE_PROT32 :
5092 X86EMUL_MODE_PROT16;
a584539b 5093 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5094 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5095 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5096 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5097
dd856efa 5098 init_decode_cache(ctxt);
7ae441ea 5099 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5100}
5101
71f9833b 5102int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5103{
9d74191a 5104 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5105 int ret;
5106
5107 init_emulate_ctxt(vcpu);
5108
9dac77fa
AK		 5109 ctxt->op_bytes = 2;
5110 ctxt->ad_bytes = 2;
5111 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5112 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5113
5114 if (ret != X86EMUL_CONTINUE)
5115 return EMULATE_FAIL;
5116
9dac77fa 5117 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5118 kvm_rip_write(vcpu, ctxt->eip);
5119 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5120
5121 if (irq == NMI_VECTOR)
7460fb4a 5122 vcpu->arch.nmi_pending = 0;
63995653
MG		 5123 else
5124 vcpu->arch.interrupt.pending = false;
5125
5126 return EMULATE_DONE;
5127}
5128EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5129
6d77dbfc
GN		 5130static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5131{
fc3a9157
JR		 5132 int r = EMULATE_DONE;
5133
6d77dbfc
GN		 5134 ++vcpu->stat.insn_emulation_fail;
5135 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5136 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5137 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5138 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5139 vcpu->run->internal.ndata = 0;
5140 r = EMULATE_FAIL;
5141 }
6d77dbfc 5142 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5143
5144 return r;
6d77dbfc
GN		 5145}
5146
93c05d3e 5147static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5148 bool write_fault_to_shadow_pgtable,
5149 int emulation_type)
a6f177ef 5150{
95b3cf69 5151 gpa_t gpa = cr2;
ba049e93 5152 kvm_pfn_t pfn;
a6f177ef 5153
991eebf9
GN		 5154 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5155 return false;
5156
95b3cf69
XG		 5157 if (!vcpu->arch.mmu.direct_map) {
5158 /*
5159 * Write permission should be allowed since only
5160 * write access need to be emulated.
5161 */
5162 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5163
95b3cf69
XG		 5164 /*
5165 * If the mapping is invalid in guest, let cpu retry
5166 * it to generate fault.
5167 */
5168 if (gpa == UNMAPPED_GVA)
5169 return true;
5170 }
a6f177ef 5171
8e3d9d06
XG		 5172 /*
5173 * Do not retry the unhandleable instruction if it faults on the
5174 * readonly host memory, otherwise it will goto a infinite loop:
5175 * retry instruction -> write #PF -> emulation fail -> retry
5176 * instruction -> ...
5177 */
5178 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5179
5180 /*
5181 * If the instruction failed on the error pfn, it can not be fixed,
5182 * report the error to userspace.
5183 */
5184 if (is_error_noslot_pfn(pfn))
5185 return false;
5186
5187 kvm_release_pfn_clean(pfn);
5188
5189 /* The instructions are well-emulated on direct mmu. */
5190 if (vcpu->arch.mmu.direct_map) {
5191 unsigned int indirect_shadow_pages;
5192
5193 spin_lock(&vcpu->kvm->mmu_lock);
5194 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5195 spin_unlock(&vcpu->kvm->mmu_lock);
5196
5197 if (indirect_shadow_pages)
5198 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5199
a6f177ef 5200 return true;
8e3d9d06 5201 }
a6f177ef 5202
95b3cf69
XG		 5203 /*
5204 * if emulation was due to access to shadowed page table
5205 * and it failed try to unshadow page and re-enter the
5206 * guest to let CPU execute the instruction.
5207 */
5208 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5209
5210 /*
5211 * If the access faults on its page table, it can not
5212 * be fixed by unprotecting shadow page and it should
5213 * be reported to userspace.
5214 */
5215 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5216}
5217
1cb3f3ae
XG		 5218static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5219 unsigned long cr2, int emulation_type)
5220{
5221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5222 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5223
5224 last_retry_eip = vcpu->arch.last_retry_eip;
5225 last_retry_addr = vcpu->arch.last_retry_addr;
5226
5227 /*
5228 * If the emulation is caused by #PF and it is non-page_table
5229 * writing instruction, it means the VM-EXIT is caused by shadow
5230 * page protected, we can zap the shadow page and retry this
5231 * instruction directly.
5232 *
5233 * Note: if the guest uses a non-page-table modifying instruction
5234 * on the PDE that points to the instruction, then we will unmap
5235 * the instruction and go to an infinite loop. So, we cache the
5236 * last retried eip and the last fault address, if we meet the eip
5237 * and the address again, we can break out of the potential infinite
5238 * loop.
5239 */
5240 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5241
5242 if (!(emulation_type & EMULTYPE_RETRY))
5243 return false;
5244
5245 if (x86_page_table_writing_insn(ctxt))
5246 return false;
5247
5248 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5249 return false;
5250
5251 vcpu->arch.last_retry_eip = ctxt->eip;
5252 vcpu->arch.last_retry_addr = cr2;
5253
5254 if (!vcpu->arch.mmu.direct_map)
5255 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5256
22368028 5257 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5258
5259 return true;
5260}
5261
716d51ab
GN		 5262static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5263static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5264
64d60670 5265static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5266{
64d60670 5267 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5268 /* This is a good place to trace that we are exiting SMM. */
5269 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5270
64d60670
PB		 5271 if (unlikely(vcpu->arch.smi_pending)) {
5272 kvm_make_request(KVM_REQ_SMI, vcpu);
5273 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5274 } else {
5275 /* Process a latched INIT, if any. */
5276 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5277 }
5278 }
699023e2
PB		 5279
5280 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5281}
5282
5283static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5284{
5285 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5286
a584539b 5287 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5288
5289 if (changed & HF_SMM_MASK)
5290 kvm_smm_changed(vcpu);
a584539b
PB		 5291}
5292
4a1e10d5
PB		 5293static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5294 unsigned long *db)
5295{
5296 u32 dr6 = 0;
5297 int i;
5298 u32 enable, rwlen;
5299
5300 enable = dr7;
5301 rwlen = dr7 >> 16;
5302 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5303 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5304 dr6 |= (1 << i);
5305 return dr6;
5306}
5307
6addfc42 5308static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5309{
5310 struct kvm_run *kvm_run = vcpu->run;
5311
5312 /*
6addfc42
PB		 5313 * rflags is the old, "raw" value of the flags. The new value has
5314 * not been saved yet.
663f4c61
PB		 5315 *
5316 * This is correct even for TF set by the guest, because "the
5317 * processor will not generate this exception after the instruction
5318 * that sets the TF flag".
5319 */
663f4c61
PB		 5320 if (unlikely(rflags & X86_EFLAGS_TF)) {
5321 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5322 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5323 DR6_RTM;
663f4c61
PB		 5324 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5325 kvm_run->debug.arch.exception = DB_VECTOR;
5326 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5327 *r = EMULATE_USER_EXIT;
5328 } else {
5329 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5330 /*
5331 * "Certain debug exceptions may clear bit 0-3. The
5332 * remaining contents of the DR6 register are never
5333 * cleared by the processor".
5334 */
5335 vcpu->arch.dr6 &= ~15;
6f43ed01 5336 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5337 kvm_queue_exception(vcpu, DB_VECTOR);
5338 }
5339 }
5340}
5341
4a1e10d5
PB		 5342static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5343{
4a1e10d5
PB		 5344 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5345 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5346 struct kvm_run *kvm_run = vcpu->run;
5347 unsigned long eip = kvm_get_linear_rip(vcpu);
5348 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5349 vcpu->arch.guest_debug_dr7,
5350 vcpu->arch.eff_db);
5351
5352 if (dr6 != 0) {
6f43ed01 5353 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5354 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5355 kvm_run->debug.arch.exception = DB_VECTOR;
5356 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5357 *r = EMULATE_USER_EXIT;
5358 return true;
5359 }
5360 }
5361
4161a569
NA		 5362 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5363 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5364 unsigned long eip = kvm_get_linear_rip(vcpu);
5365 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5366 vcpu->arch.dr7,
5367 vcpu->arch.db);
5368
5369 if (dr6 != 0) {
5370 vcpu->arch.dr6 &= ~15;
6f43ed01 5371 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5372 kvm_queue_exception(vcpu, DB_VECTOR);
5373 *r = EMULATE_DONE;
5374 return true;
5375 }
5376 }
5377
5378 return false;
5379}
5380
51d8b661
AP		 5381int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5382 unsigned long cr2,
dc25e89e
AP		 5383 int emulation_type,
5384 void *insn,
5385 int insn_len)
bbd9b64e 5386{
95cb2295 5387 int r;
9d74191a 5388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5389 bool writeback = true;
93c05d3e 5390 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5391
93c05d3e
XG		 5392 /*
5393 * Clear write_fault_to_shadow_pgtable here to ensure it is
5394 * never reused.
5395 */
5396 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5397 kvm_clear_exception_queue(vcpu);
8d7d8102 5398
571008da 5399 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5400 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5401
5402 /*
5403 * We will reenter on the same instruction since
5404 * we do not set complete_userspace_io. This does not
5405 * handle watchpoints yet, those would be handled in
5406 * the emulate_ops.
5407 */
5408 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5409 return r;
5410
9d74191a
TY		 5411 ctxt->interruptibility = 0;
5412 ctxt->have_exception = false;
e0ad0b47 5413 ctxt->exception.vector = -1;
9d74191a 5414 ctxt->perm_ok = false;
bbd9b64e 5415
b51e974f 5416 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5417
9d74191a 5418 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5419
e46479f8 5420 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5421 ++vcpu->stat.insn_emulation;
1d2887e2 5422 if (r != EMULATION_OK) {
4005996e
AK		 5423 if (emulation_type & EMULTYPE_TRAP_UD)
5424 return EMULATE_FAIL;
991eebf9
GN		 5425 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5426 emulation_type))
bbd9b64e 5427 return EMULATE_DONE;
6d77dbfc
GN		 5428 if (emulation_type & EMULTYPE_SKIP)
5429 return EMULATE_FAIL;
5430 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5431 }
5432 }
5433
ba8afb6b 5434 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5435 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5436 if (ctxt->eflags & X86_EFLAGS_RF)
5437 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5438 return EMULATE_DONE;
5439 }
5440
1cb3f3ae
XG		 5441 if (retry_instruction(ctxt, cr2, emulation_type))
5442 return EMULATE_DONE;
5443
7ae441ea 5444 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5445 changes registers values during IO operation */
7ae441ea
GN		 5446 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5447 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5448 emulator_invalidate_register_cache(ctxt);
7ae441ea 5449 }
4d2179e1 5450
5cd21917 5451restart:
9d74191a 5452 r = x86_emulate_insn(ctxt);
bbd9b64e 5453
775fde86
JR		 5454 if (r == EMULATION_INTERCEPTED)
5455 return EMULATE_DONE;
5456
d2ddd1c4 5457 if (r == EMULATION_FAILED) {
991eebf9
GN		 5458 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5459 emulation_type))
c3cd7ffa
GN		 5460 return EMULATE_DONE;
5461
6d77dbfc 5462 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5463 }
5464
9d74191a 5465 if (ctxt->have_exception) {
d2ddd1c4 5466 r = EMULATE_DONE;
ef54bcfe
PB		 5467 if (inject_emulated_exception(vcpu))
5468 return r;
d2ddd1c4 5469 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5470 if (!vcpu->arch.pio.in) {
5471 /* FIXME: return into emulator if single-stepping. */
3457e419 5472 vcpu->arch.pio.count = 0;
0912c977 5473 } else {
7ae441ea 5474 writeback = false;
716d51ab
GN		 5475 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5476 }
ac0a48c3 5477 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5478 } else if (vcpu->mmio_needed) {
5479 if (!vcpu->mmio_is_write)
5480 writeback = false;
ac0a48c3 5481 r = EMULATE_USER_EXIT;
716d51ab 5482 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5483 } else if (r == EMULATION_RESTART)
5cd21917 5484 goto restart;
d2ddd1c4
GN		 5485 else
5486 r = EMULATE_DONE;
f850e2e6 5487
7ae441ea 5488 if (writeback) {
6addfc42 5489 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5490 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5491 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5492 if (vcpu->arch.hflags != ctxt->emul_flags)
5493 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5494 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5495 if (r == EMULATE_DONE)
6addfc42 5496 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5497 if (!ctxt->have_exception ||
5498 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5499 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5500
5501 /*
5502 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5503 * do nothing, and it will be requested again as soon as
5504 * the shadow expires. But we still need to check here,
5505 * because POPF has no interrupt shadow.
5506 */
5507 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5508 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5509 } else
5510 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5511
5512 return r;
de7d789a 5513}
51d8b661 5514EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5515
cf8f70bf 5516int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5517{
cf8f70bf 5518 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5519 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5520 size, port, &val, 1);
cf8f70bf 5521 /* do not return to emulator after return from userspace */
7972995b 5522 vcpu->arch.pio.count = 0;
de7d789a
CO		 5523 return ret;
5524}
cf8f70bf 5525EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5526
8cfdc000
ZA		 5527static void tsc_bad(void *info)
5528{
0a3aee0d 5529 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5530}
5531
5532static void tsc_khz_changed(void *data)
c8076604 5533{
8cfdc000
ZA		 5534 struct cpufreq_freqs *freq = data;
5535 unsigned long khz = 0;
5536
5537 if (data)
5538 khz = freq->new;
5539 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5540 khz = cpufreq_quick_get(raw_smp_processor_id());
5541 if (!khz)
5542 khz = tsc_khz;
0a3aee0d 5543 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5544}
5545
c8076604
GH		 5546static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5547 void *data)
5548{
5549 struct cpufreq_freqs *freq = data;
5550 struct kvm *kvm;
5551 struct kvm_vcpu *vcpu;
5552 int i, send_ipi = 0;
5553
8cfdc000
ZA		 5554 /*
5555 * We allow guests to temporarily run on slowing clocks,
5556 * provided we notify them after, or to run on accelerating
5557 * clocks, provided we notify them before. Thus time never
5558 * goes backwards.
5559 *
5560 * However, we have a problem. We can't atomically update
5561 * the frequency of a given CPU from this function; it is
5562 * merely a notifier, which can be called from any CPU.
5563 * Changing the TSC frequency at arbitrary points in time
5564 * requires a recomputation of local variables related to
5565 * the TSC for each VCPU. We must flag these local variables
5566 * to be updated and be sure the update takes place with the
5567 * new frequency before any guests proceed.
5568 *
5569 * Unfortunately, the combination of hotplug CPU and frequency
5570 * change creates an intractable locking scenario; the order
5571 * of when these callouts happen is undefined with respect to
5572 * CPU hotplug, and they can race with each other. As such,
5573 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5574 * undefined; you can actually have a CPU frequency change take
5575 * place in between the computation of X and the setting of the
5576 * variable. To protect against this problem, all updates of
5577 * the per_cpu tsc_khz variable are done in an interrupt
5578 * protected IPI, and all callers wishing to update the value
5579 * must wait for a synchronous IPI to complete (which is trivial
5580 * if the caller is on the CPU already). This establishes the
5581 * necessary total order on variable updates.
5582 *
5583 * Note that because a guest time update may take place
5584 * anytime after the setting of the VCPU's request bit, the
5585 * correct TSC value must be set before the request. However,
5586 * to ensure the update actually makes it to any guest which
5587 * starts running in hardware virtualization between the set
5588 * and the acquisition of the spinlock, we must also ping the
5589 * CPU after setting the request bit.
5590 *
5591 */
5592
c8076604
GH		 5593 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5594 return 0;
5595 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5596 return 0;
8cfdc000
ZA		 5597
5598 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5599
2f303b74 5600 spin_lock(&kvm_lock);
c8076604 5601 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5602 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5603 if (vcpu->cpu != freq->cpu)
5604 continue;
c285545f 5605 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5606 if (vcpu->cpu != smp_processor_id())
8cfdc000 5607 send_ipi = 1;
c8076604
GH		 5608 }
5609 }
2f303b74 5610 spin_unlock(&kvm_lock);
c8076604
GH		 5611
5612 if (freq->old < freq->new && send_ipi) {
5613 /*
5614 * We upscale the frequency. Must make the guest
5615 * doesn't see old kvmclock values while running with
5616 * the new frequency, otherwise we risk the guest sees
5617 * time go backwards.
5618 *
5619 * In case we update the frequency for another cpu
5620 * (which might be in guest context) send an interrupt
5621 * to kick the cpu out of guest context. Next time
5622 * guest context is entered kvmclock will be updated,
5623 * so the guest will not see stale values.
5624 */
8cfdc000 5625 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5626 }
5627 return 0;
5628}
5629
5630static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5631 .notifier_call = kvmclock_cpufreq_notifier
5632};
5633
5634static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5635 unsigned long action, void *hcpu)
5636{
5637 unsigned int cpu = (unsigned long)hcpu;
5638
5639 switch (action) {
5640 case CPU_ONLINE:
5641 case CPU_DOWN_FAILED:
5642 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5643 break;
5644 case CPU_DOWN_PREPARE:
5645 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5646 break;
5647 }
5648 return NOTIFY_OK;
5649}
5650
5651static struct notifier_block kvmclock_cpu_notifier_block = {
5652 .notifier_call = kvmclock_cpu_notifier,
5653 .priority = -INT_MAX
c8076604
GH		 5654};
5655
b820cc0c
ZA		 5656static void kvm_timer_init(void)
5657{
5658 int cpu;
5659
c285545f 5660 max_tsc_khz = tsc_khz;
460dd42e
SB		 5661
5662 cpu_notifier_register_begin();
b820cc0c 5663 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5664#ifdef CONFIG_CPU_FREQ
5665 struct cpufreq_policy policy;
5666 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5667 cpu = get_cpu();
5668 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5669 if (policy.cpuinfo.max_freq)
5670 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5671 put_cpu();
c285545f 5672#endif
b820cc0c
ZA		 5673 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5674 CPUFREQ_TRANSITION_NOTIFIER);
5675 }
c285545f 5676 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5677 for_each_online_cpu(cpu)
5678 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5679
5680 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5681 cpu_notifier_register_done();
5682
b820cc0c
ZA		 5683}
5684
ff9d07a0
ZY		 5685static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5686
f5132b01 5687int kvm_is_in_guest(void)
ff9d07a0 5688{
086c9855 5689 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5690}
5691
5692static int kvm_is_user_mode(void)
5693{
5694 int user_mode = 3;
dcf46b94 5695
086c9855
AS		 5696 if (__this_cpu_read(current_vcpu))
5697 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5698
ff9d07a0
ZY		 5699 return user_mode != 0;
5700}
5701
5702static unsigned long kvm_get_guest_ip(void)
5703{
5704 unsigned long ip = 0;
dcf46b94 5705
086c9855
AS		 5706 if (__this_cpu_read(current_vcpu))
5707 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5708
ff9d07a0
ZY		 5709 return ip;
5710}
5711
5712static struct perf_guest_info_callbacks kvm_guest_cbs = {
5713 .is_in_guest = kvm_is_in_guest,
5714 .is_user_mode = kvm_is_user_mode,
5715 .get_guest_ip = kvm_get_guest_ip,
5716};
5717
5718void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5719{
086c9855 5720 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5721}
5722EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5723
5724void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5725{
086c9855 5726 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5727}
5728EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5729
ce88decf
XG		 5730static void kvm_set_mmio_spte_mask(void)
5731{
5732 u64 mask;
5733 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5734
5735 /*
5736 * Set the reserved bits and the present bit of an paging-structure
5737 * entry to generate page fault with PFER.RSV = 1.
5738 */
885032b9 5739 /* Mask the reserved physical address bits. */
d1431483 5740 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5741
5742 /* Bit 62 is always reserved for 32bit host. */
5743 mask |= 0x3ull << 62;
5744
5745 /* Set the present bit. */
ce88decf
XG		 5746 mask |= 1ull;
5747
5748#ifdef CONFIG_X86_64
5749 /*
5750 * If reserved bit is not supported, clear the present bit to disable
5751 * mmio page fault.
5752 */
5753 if (maxphyaddr == 52)
5754 mask &= ~1ull;
5755#endif
5756
5757 kvm_mmu_set_mmio_spte_mask(mask);
5758}
5759
16e8d74d
MT		 5760#ifdef CONFIG_X86_64
5761static void pvclock_gtod_update_fn(struct work_struct *work)
5762{
d828199e
MT		 5763 struct kvm *kvm;
5764
5765 struct kvm_vcpu *vcpu;
5766 int i;
5767
2f303b74 5768 spin_lock(&kvm_lock);
d828199e
MT		 5769 list_for_each_entry(kvm, &vm_list, vm_list)
5770 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5771 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5772 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5773 spin_unlock(&kvm_lock);
16e8d74d
MT		 5774}
5775
5776static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5777
5778/*
5779 * Notification about pvclock gtod data update.
5780 */
5781static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5782 void *priv)
5783{
5784 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5785 struct timekeeper *tk = priv;
5786
5787 update_pvclock_gtod(tk);
5788
5789 /* disable master clock if host does not trust, or does not
5790 * use, TSC clocksource
5791 */
5792 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5793 atomic_read(&kvm_guest_has_master_clock) != 0)
5794 queue_work(system_long_wq, &pvclock_gtod_work);
5795
5796 return 0;
5797}
5798
5799static struct notifier_block pvclock_gtod_notifier = {
5800 .notifier_call = pvclock_gtod_notify,
5801};
5802#endif
5803
f8c16bba 5804int kvm_arch_init(void *opaque)
043405e1 5805{
b820cc0c 5806 int r;
6b61edf7 5807 struct kvm_x86_ops *ops = opaque;
f8c16bba 5808
f8c16bba
ZX		 5809 if (kvm_x86_ops) {
5810 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5811 r = -EEXIST;
5812 goto out;
f8c16bba
ZX		 5813 }
5814
5815 if (!ops->cpu_has_kvm_support()) {
5816 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5817 r = -EOPNOTSUPP;
5818 goto out;
f8c16bba
ZX		 5819 }
5820 if (ops->disabled_by_bios()) {
5821 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5822 r = -EOPNOTSUPP;
5823 goto out;
f8c16bba
ZX		 5824 }
5825
013f6a5d
MT		 5826 r = -ENOMEM;
5827 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5828 if (!shared_msrs) {
5829 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5830 goto out;
5831 }
5832
97db56ce
AK		 5833 r = kvm_mmu_module_init();
5834 if (r)
013f6a5d 5835 goto out_free_percpu;
97db56ce 5836
ce88decf 5837 kvm_set_mmio_spte_mask();
97db56ce 5838
f8c16bba 5839 kvm_x86_ops = ops;
920c8377 5840
7b52345e 5841 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5842 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5843
b820cc0c 5844 kvm_timer_init();
c8076604 5845
ff9d07a0
ZY		 5846 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5847
2acf923e
DC		 5848 if (cpu_has_xsave)
5849 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5850
c5cc421b 5851 kvm_lapic_init();
16e8d74d
MT		 5852#ifdef CONFIG_X86_64
5853 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5854#endif
5855
f8c16bba 5856 return 0;
56c6d28a 5857
013f6a5d
MT		 5858out_free_percpu:
5859 free_percpu(shared_msrs);
56c6d28a 5860out:
56c6d28a 5861 return r;
043405e1 5862}
8776e519 5863
f8c16bba
ZX		 5864void kvm_arch_exit(void)
5865{
ff9d07a0
ZY		 5866 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5867
888d256e
JK		 5868 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5869 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5870 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5871 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5872#ifdef CONFIG_X86_64
5873 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5874#endif
f8c16bba 5875 kvm_x86_ops = NULL;
56c6d28a 5876 kvm_mmu_module_exit();
013f6a5d 5877 free_percpu(shared_msrs);
56c6d28a 5878}
f8c16bba 5879
5cb56059 5880int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5881{
5882 ++vcpu->stat.halt_exits;
35754c98 5883 if (lapic_in_kernel(vcpu)) {
a4535290 5884 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5885 return 1;
5886 } else {
5887 vcpu->run->exit_reason = KVM_EXIT_HLT;
5888 return 0;
5889 }
5890}
5cb56059
JS		 5891EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5892
5893int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5894{
5895 kvm_x86_ops->skip_emulated_instruction(vcpu);
5896 return kvm_vcpu_halt(vcpu);
5897}
8776e519
HB		 5898EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5899
6aef266c
SV		 5900/*
5901 * kvm_pv_kick_cpu_op: Kick a vcpu.
5902 *
5903 * @apicid - apicid of vcpu to be kicked.
5904 */
5905static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5906{
24d2166b 5907 struct kvm_lapic_irq lapic_irq;
6aef266c 5908
24d2166b
R		 5909 lapic_irq.shorthand = 0;
5910 lapic_irq.dest_mode = 0;
5911 lapic_irq.dest_id = apicid;
93bbf0b8 5912 lapic_irq.msi_redir_hint = false;
6aef266c 5913
24d2166b 5914 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5915 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5916}
5917
d62caabb
AS		 5918void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5919{
5920 vcpu->arch.apicv_active = false;
5921 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5922}
5923
8776e519
HB		 5924int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5925{
5926 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5927 int op_64_bit, r = 1;
8776e519 5928
5cb56059
JS		 5929 kvm_x86_ops->skip_emulated_instruction(vcpu);
5930
55cd8e5a
GN		 5931 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5932 return kvm_hv_hypercall(vcpu);
5933
5fdbf976
MT		 5934 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5935 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5936 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5937 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5938 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5939
229456fc 5940 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5941
a449c7aa
NA		 5942 op_64_bit = is_64_bit_mode(vcpu);
5943 if (!op_64_bit) {
8776e519
HB		 5944 nr &= 0xFFFFFFFF;
5945 a0 &= 0xFFFFFFFF;
5946 a1 &= 0xFFFFFFFF;
5947 a2 &= 0xFFFFFFFF;
5948 a3 &= 0xFFFFFFFF;
5949 }
5950
07708c4a
JK		 5951 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5952 ret = -KVM_EPERM;
5953 goto out;
5954 }
5955
8776e519 5956 switch (nr) {
b93463aa
AK		 5957 case KVM_HC_VAPIC_POLL_IRQ:
5958 ret = 0;
5959 break;
6aef266c
SV		 5960 case KVM_HC_KICK_CPU:
5961 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5962 ret = 0;
5963 break;
8776e519
HB		 5964 default:
5965 ret = -KVM_ENOSYS;
5966 break;
5967 }
07708c4a 5968out:
a449c7aa
NA		 5969 if (!op_64_bit)
5970 ret = (u32)ret;
5fdbf976 5971 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5972 ++vcpu->stat.hypercalls;
2f333bcb 5973 return r;
8776e519
HB		 5974}
5975EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5976
b6785def 5977static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5978{
d6aa1000 5979 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5980 char instruction[3];
5fdbf976 5981 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5982
8776e519 5983 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5984
9d74191a 5985 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5986}
5987
851ba692 5988static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5989{
782d422b
MG		 5990 return vcpu->run->request_interrupt_window &&
5991 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 5992}
5993
851ba692 5994static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5995{
851ba692
AK		 5996 struct kvm_run *kvm_run = vcpu->run;
5997
91586a3b 5998 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5999 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6000 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6001 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6002 kvm_run->ready_for_interrupt_injection =
6003 pic_in_kernel(vcpu->kvm) ||
782d422b 6004 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6005}
6006
95ba8273
GN		 6007static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6008{
6009 int max_irr, tpr;
6010
6011 if (!kvm_x86_ops->update_cr8_intercept)
6012 return;
6013
88c808fd
AK		 6014 if (!vcpu->arch.apic)
6015 return;
6016
d62caabb
AS		 6017 if (vcpu->arch.apicv_active)
6018 return;
6019
8db3baa2
GN		 6020 if (!vcpu->arch.apic->vapic_addr)
6021 max_irr = kvm_lapic_find_highest_irr(vcpu);
6022 else
6023 max_irr = -1;
95ba8273
GN		 6024
6025 if (max_irr != -1)
6026 max_irr >>= 4;
6027
6028 tpr = kvm_lapic_get_cr8(vcpu);
6029
6030 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6031}
6032
b6b8a145 6033static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6034{
b6b8a145
JK		 6035 int r;
6036
95ba8273 6037 /* try to reinject previous events if any */
b59bb7bd 6038 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6039 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6040 vcpu->arch.exception.has_error_code,
6041 vcpu->arch.exception.error_code);
d6e8c854
NA		 6042
6043 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6044 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6045 X86_EFLAGS_RF);
6046
6bdf0662
NA		 6047 if (vcpu->arch.exception.nr == DB_VECTOR &&
6048 (vcpu->arch.dr7 & DR7_GD)) {
6049 vcpu->arch.dr7 &= ~DR7_GD;
6050 kvm_update_dr7(vcpu);
6051 }
6052
b59bb7bd
GN		 6053 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6054 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6055 vcpu->arch.exception.error_code,
6056 vcpu->arch.exception.reinject);
b6b8a145 6057 return 0;
b59bb7bd
GN		 6058 }
6059
95ba8273
GN		 6060 if (vcpu->arch.nmi_injected) {
6061 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6062 return 0;
95ba8273
GN		 6063 }
6064
6065 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6066 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6067 return 0;
6068 }
6069
6070 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6071 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6072 if (r != 0)
6073 return r;
95ba8273
GN		 6074 }
6075
6076 /* try to inject new event if pending */
6077 if (vcpu->arch.nmi_pending) {
6078 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6079 --vcpu->arch.nmi_pending;
95ba8273
GN		 6080 vcpu->arch.nmi_injected = true;
6081 kvm_x86_ops->set_nmi(vcpu);
6082 }
c7c9c56c 6083 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6084 /*
6085 * Because interrupts can be injected asynchronously, we are
6086 * calling check_nested_events again here to avoid a race condition.
6087 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6088 * proposal and current concerns. Perhaps we should be setting
6089 * KVM_REQ_EVENT only on certain events and not unconditionally?
6090 */
6091 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6092 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6093 if (r != 0)
6094 return r;
6095 }
95ba8273 6096 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6097 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6098 false);
6099 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6100 }
6101 }
b6b8a145 6102 return 0;
95ba8273
GN		 6103}
6104
7460fb4a
AK		 6105static void process_nmi(struct kvm_vcpu *vcpu)
6106{
6107 unsigned limit = 2;
6108
6109 /*
6110 * x86 is limited to one NMI running, and one NMI pending after it.
6111 * If an NMI is already in progress, limit further NMIs to just one.
6112 * Otherwise, allow two (and we'll inject the first one immediately).
6113 */
6114 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6115 limit = 1;
6116
6117 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6118 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6119 kvm_make_request(KVM_REQ_EVENT, vcpu);
6120}
6121
660a5d51
PB		 6122#define put_smstate(type, buf, offset, val) \
6123 *(type *)((buf) + (offset) - 0x7e00) = val
6124
6125static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6126{
6127 u32 flags = 0;
6128 flags |= seg->g << 23;
6129 flags |= seg->db << 22;
6130 flags |= seg->l << 21;
6131 flags |= seg->avl << 20;
6132 flags |= seg->present << 15;
6133 flags |= seg->dpl << 13;
6134 flags |= seg->s << 12;
6135 flags |= seg->type << 8;
6136 return flags;
6137}
6138
6139static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6140{
6141 struct kvm_segment seg;
6142 int offset;
6143
6144 kvm_get_segment(vcpu, &seg, n);
6145 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6146
6147 if (n < 3)
6148 offset = 0x7f84 + n * 12;
6149 else
6150 offset = 0x7f2c + (n - 3) * 12;
6151
6152 put_smstate(u32, buf, offset + 8, seg.base);
6153 put_smstate(u32, buf, offset + 4, seg.limit);
6154 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6155}
6156
efbb288a 6157#ifdef CONFIG_X86_64
660a5d51
PB		 6158static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6159{
6160 struct kvm_segment seg;
6161 int offset;
6162 u16 flags;
6163
6164 kvm_get_segment(vcpu, &seg, n);
6165 offset = 0x7e00 + n * 16;
6166
6167 flags = process_smi_get_segment_flags(&seg) >> 8;
6168 put_smstate(u16, buf, offset, seg.selector);
6169 put_smstate(u16, buf, offset + 2, flags);
6170 put_smstate(u32, buf, offset + 4, seg.limit);
6171 put_smstate(u64, buf, offset + 8, seg.base);
6172}
efbb288a 6173#endif
660a5d51
PB		 6174
6175static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6176{
6177 struct desc_ptr dt;
6178 struct kvm_segment seg;
6179 unsigned long val;
6180 int i;
6181
6182 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6183 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6184 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6185 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6186
6187 for (i = 0; i < 8; i++)
6188 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6189
6190 kvm_get_dr(vcpu, 6, &val);
6191 put_smstate(u32, buf, 0x7fcc, (u32)val);
6192 kvm_get_dr(vcpu, 7, &val);
6193 put_smstate(u32, buf, 0x7fc8, (u32)val);
6194
6195 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6196 put_smstate(u32, buf, 0x7fc4, seg.selector);
6197 put_smstate(u32, buf, 0x7f64, seg.base);
6198 put_smstate(u32, buf, 0x7f60, seg.limit);
6199 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6200
6201 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6202 put_smstate(u32, buf, 0x7fc0, seg.selector);
6203 put_smstate(u32, buf, 0x7f80, seg.base);
6204 put_smstate(u32, buf, 0x7f7c, seg.limit);
6205 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6206
6207 kvm_x86_ops->get_gdt(vcpu, &dt);
6208 put_smstate(u32, buf, 0x7f74, dt.address);
6209 put_smstate(u32, buf, 0x7f70, dt.size);
6210
6211 kvm_x86_ops->get_idt(vcpu, &dt);
6212 put_smstate(u32, buf, 0x7f58, dt.address);
6213 put_smstate(u32, buf, 0x7f54, dt.size);
6214
6215 for (i = 0; i < 6; i++)
6216 process_smi_save_seg_32(vcpu, buf, i);
6217
6218 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6219
6220 /* revision id */
6221 put_smstate(u32, buf, 0x7efc, 0x00020000);
6222 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6223}
6224
6225static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6226{
6227#ifdef CONFIG_X86_64
6228 struct desc_ptr dt;
6229 struct kvm_segment seg;
6230 unsigned long val;
6231 int i;
6232
6233 for (i = 0; i < 16; i++)
6234 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6235
6236 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6237 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6238
6239 kvm_get_dr(vcpu, 6, &val);
6240 put_smstate(u64, buf, 0x7f68, val);
6241 kvm_get_dr(vcpu, 7, &val);
6242 put_smstate(u64, buf, 0x7f60, val);
6243
6244 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6245 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6246 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6247
6248 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6249
6250 /* revision id */
6251 put_smstate(u32, buf, 0x7efc, 0x00020064);
6252
6253 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6254
6255 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6256 put_smstate(u16, buf, 0x7e90, seg.selector);
6257 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6258 put_smstate(u32, buf, 0x7e94, seg.limit);
6259 put_smstate(u64, buf, 0x7e98, seg.base);
6260
6261 kvm_x86_ops->get_idt(vcpu, &dt);
6262 put_smstate(u32, buf, 0x7e84, dt.size);
6263 put_smstate(u64, buf, 0x7e88, dt.address);
6264
6265 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6266 put_smstate(u16, buf, 0x7e70, seg.selector);
6267 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6268 put_smstate(u32, buf, 0x7e74, seg.limit);
6269 put_smstate(u64, buf, 0x7e78, seg.base);
6270
6271 kvm_x86_ops->get_gdt(vcpu, &dt);
6272 put_smstate(u32, buf, 0x7e64, dt.size);
6273 put_smstate(u64, buf, 0x7e68, dt.address);
6274
6275 for (i = 0; i < 6; i++)
6276 process_smi_save_seg_64(vcpu, buf, i);
6277#else
6278 WARN_ON_ONCE(1);
6279#endif
6280}
6281
64d60670
PB		 6282static void process_smi(struct kvm_vcpu *vcpu)
6283{
660a5d51 6284 struct kvm_segment cs, ds;
18c3626e 6285 struct desc_ptr dt;
660a5d51
PB		 6286 char buf[512];
6287 u32 cr0;
6288
64d60670
PB		 6289 if (is_smm(vcpu)) {
6290 vcpu->arch.smi_pending = true;
6291 return;
6292 }
6293
660a5d51
PB		 6294 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6295 vcpu->arch.hflags |= HF_SMM_MASK;
6296 memset(buf, 0, 512);
6297 if (guest_cpuid_has_longmode(vcpu))
6298 process_smi_save_state_64(vcpu, buf);
6299 else
6300 process_smi_save_state_32(vcpu, buf);
6301
54bf36aa 6302 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6303
6304 if (kvm_x86_ops->get_nmi_mask(vcpu))
6305 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6306 else
6307 kvm_x86_ops->set_nmi_mask(vcpu, true);
6308
6309 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6310 kvm_rip_write(vcpu, 0x8000);
6311
6312 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6313 kvm_x86_ops->set_cr0(vcpu, cr0);
6314 vcpu->arch.cr0 = cr0;
6315
6316 kvm_x86_ops->set_cr4(vcpu, 0);
6317
18c3626e
PB		 6318 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6319 dt.address = dt.size = 0;
6320 kvm_x86_ops->set_idt(vcpu, &dt);
6321
660a5d51
PB		 6322 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6323
6324 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6325 cs.base = vcpu->arch.smbase;
6326
6327 ds.selector = 0;
6328 ds.base = 0;
6329
6330 cs.limit = ds.limit = 0xffffffff;
6331 cs.type = ds.type = 0x3;
6332 cs.dpl = ds.dpl = 0;
6333 cs.db = ds.db = 0;
6334 cs.s = ds.s = 1;
6335 cs.l = ds.l = 0;
6336 cs.g = ds.g = 1;
6337 cs.avl = ds.avl = 0;
6338 cs.present = ds.present = 1;
6339 cs.unusable = ds.unusable = 0;
6340 cs.padding = ds.padding = 0;
6341
6342 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6343 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6344 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6345 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6346 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6347 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6348
6349 if (guest_cpuid_has_longmode(vcpu))
6350 kvm_x86_ops->set_efer(vcpu, 0);
6351
6352 kvm_update_cpuid(vcpu);
6353 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6354}
6355
2860c4b1
PB		 6356void kvm_make_scan_ioapic_request(struct kvm *kvm)
6357{
6358 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6359}
6360
3d81bc7e 6361static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6362{
5c919412
AS		 6363 u64 eoi_exit_bitmap[4];
6364
3d81bc7e
YZ		 6365 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6366 return;
c7c9c56c 6367
6308630b 6368 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6369
b053b2ae 6370 if (irqchip_split(vcpu->kvm))
6308630b 6371 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6372 else {
d62caabb
AS		 6373 if (vcpu->arch.apicv_active)
6374 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6375 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6376 }
5c919412
AS		 6377 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6378 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6379 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6380}
6381
a70656b6
RK		 6382static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6383{
6384 ++vcpu->stat.tlb_flush;
6385 kvm_x86_ops->tlb_flush(vcpu);
6386}
6387
4256f43f
TC		 6388void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6389{
c24ae0dc
TC		 6390 struct page *page = NULL;
6391
35754c98 6392 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6393 return;
6394
4256f43f
TC		 6395 if (!kvm_x86_ops->set_apic_access_page_addr)
6396 return;
6397
c24ae0dc 6398 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6399 if (is_error_page(page))
6400 return;
c24ae0dc
TC		 6401 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6402
6403 /*
6404 * Do not pin apic access page in memory, the MMU notifier
6405 * will call us again if it is migrated or swapped out.
6406 */
6407 put_page(page);
4256f43f
TC		 6408}
6409EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6410
fe71557a
TC		 6411void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6412 unsigned long address)
6413{
c24ae0dc
TC		 6414 /*
6415 * The physical address of apic access page is stored in the VMCS.
6416 * Update it when it becomes invalid.
6417 */
6418 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6419 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6420}
6421
9357d939 6422/*
362c698f 6423 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6424 * exiting to the userspace. Otherwise, the value will be returned to the
6425 * userspace.
6426 */
851ba692 6427static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6428{
6429 int r;
62a193ed
MG		 6430 bool req_int_win =
6431 dm_request_for_irq_injection(vcpu) &&
6432 kvm_cpu_accept_dm_intr(vcpu);
6433
730dca42 6434 bool req_immediate_exit = false;
b6c7a5dc 6435
3e007509 6436 if (vcpu->requests) {
a8eeb04a 6437 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6438 kvm_mmu_unload(vcpu);
a8eeb04a 6439 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6440 __kvm_migrate_timers(vcpu);
d828199e
MT		 6441 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6442 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6443 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6444 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6445 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6446 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6447 if (unlikely(r))
6448 goto out;
6449 }
a8eeb04a 6450 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6451 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6452 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6453 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6454 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6455 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6456 r = 0;
6457 goto out;
6458 }
a8eeb04a 6459 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6460 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6461 r = 0;
6462 goto out;
6463 }
a8eeb04a 6464 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6465 vcpu->fpu_active = 0;
6466 kvm_x86_ops->fpu_deactivate(vcpu);
6467 }
af585b92
GN		 6468 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6469 /* Page is swapped out. Do synthetic halt */
6470 vcpu->arch.apf.halted = true;
6471 r = 1;
6472 goto out;
6473 }
c9aaa895
GC		 6474 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6475 record_steal_time(vcpu);
64d60670
PB		 6476 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6477 process_smi(vcpu);
7460fb4a
AK		 6478 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6479 process_nmi(vcpu);
f5132b01 6480 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6481 kvm_pmu_handle_event(vcpu);
f5132b01 6482 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6483 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6484 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6485 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6486 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6487 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6488 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6489 vcpu->run->eoi.vector =
6490 vcpu->arch.pending_ioapic_eoi;
6491 r = 0;
6492 goto out;
6493 }
6494 }
3d81bc7e
YZ		 6495 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6496 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6497 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6498 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6499 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6500 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6501 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6502 r = 0;
6503 goto out;
6504 }
e516cebb
AS		 6505 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6506 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6507 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6508 r = 0;
6509 goto out;
6510 }
db397571
AS		 6511 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6512 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6513 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6514 r = 0;
6515 goto out;
6516 }
f3b138c5
AS		 6517
6518 /*
6519 * KVM_REQ_HV_STIMER has to be processed after
6520 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6521 * depend on the guest clock being up-to-date
6522 */
1f4b34f8
AS		 6523 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6524 kvm_hv_process_stimers(vcpu);
2f52d58c 6525 }
b93463aa 6526
bf9f6ac8
FW		 6527 /*
6528 * KVM_REQ_EVENT is not set when posted interrupts are set by
6529 * VT-d hardware, so we have to update RVI unconditionally.
6530 */
6531 if (kvm_lapic_enabled(vcpu)) {
6532 /*
6533 * Update architecture specific hints for APIC
6534 * virtual interrupt delivery.
6535 */
d62caabb 6536 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6537 kvm_x86_ops->hwapic_irr_update(vcpu,
6538 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6539 }
b93463aa 6540
b463a6f7 6541 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6542 kvm_apic_accept_events(vcpu);
6543 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6544 r = 1;
6545 goto out;
6546 }
6547
b6b8a145
JK		 6548 if (inject_pending_event(vcpu, req_int_win) != 0)
6549 req_immediate_exit = true;
b463a6f7 6550 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6551 else if (vcpu->arch.nmi_pending)
c9a7953f 6552 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6553 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6554 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6555
6556 if (kvm_lapic_enabled(vcpu)) {
6557 update_cr8_intercept(vcpu);
6558 kvm_lapic_sync_to_vapic(vcpu);
6559 }
6560 }
6561
d8368af8
AK		 6562 r = kvm_mmu_reload(vcpu);
6563 if (unlikely(r)) {
d905c069 6564 goto cancel_injection;
d8368af8
AK		 6565 }
6566
b6c7a5dc
HB		 6567 preempt_disable();
6568
6569 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6570 if (vcpu->fpu_active)
6571 kvm_load_guest_fpu(vcpu);
2acf923e 6572 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6573
6b7e2d09
XG		 6574 vcpu->mode = IN_GUEST_MODE;
6575
01b71917
MT		 6576 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6577
6b7e2d09
XG		 6578 /* We should set ->mode before check ->requests,
6579 * see the comment in make_all_cpus_request.
6580 */
01b71917 6581 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6582
d94e1dc9 6583 local_irq_disable();
32f88400 6584
6b7e2d09 6585 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6586 || need_resched() || signal_pending(current)) {
6b7e2d09 6587 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6588 smp_wmb();
6c142801
AK		 6589 local_irq_enable();
6590 preempt_enable();
01b71917 6591 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6592 r = 1;
d905c069 6593 goto cancel_injection;
6c142801
AK		 6594 }
6595
d6185f20
NHE		 6596 if (req_immediate_exit)
6597 smp_send_reschedule(vcpu->cpu);
6598
8b89fe1f
PB		 6599 trace_kvm_entry(vcpu->vcpu_id);
6600 wait_lapic_expire(vcpu);
ccf73aaf 6601 __kvm_guest_enter();
b6c7a5dc 6602
42dbaa5a 6603 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6604 set_debugreg(0, 7);
6605 set_debugreg(vcpu->arch.eff_db[0], 0);
6606 set_debugreg(vcpu->arch.eff_db[1], 1);
6607 set_debugreg(vcpu->arch.eff_db[2], 2);
6608 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6609 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6610 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6611 }
b6c7a5dc 6612
851ba692 6613 kvm_x86_ops->run(vcpu);
b6c7a5dc 6614
c77fb5fe
PB		 6615 /*
6616 * Do this here before restoring debug registers on the host. And
6617 * since we do this before handling the vmexit, a DR access vmexit
6618 * can (a) read the correct value of the debug registers, (b) set
6619 * KVM_DEBUGREG_WONT_EXIT again.
6620 */
6621 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6622 int i;
6623
6624 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6625 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6626 for (i = 0; i < KVM_NR_DB_REGS; i++)
6627 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6628 }
6629
24f1e32c
FW		 6630 /*
6631 * If the guest has used debug registers, at least dr7
6632 * will be disabled while returning to the host.
6633 * If we don't have active breakpoints in the host, we don't
6634 * care about the messed up debug address registers. But if
6635 * we have some of them active, restore the old state.
6636 */
59d8eb53 6637 if (hw_breakpoint_active())
24f1e32c 6638 hw_breakpoint_restore();
42dbaa5a 6639
4ba76538 6640 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6641
6b7e2d09 6642 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6643 smp_wmb();
a547c6db
YZ		 6644
6645 /* Interrupt is enabled by handle_external_intr() */
6646 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6647
6648 ++vcpu->stat.exits;
6649
6650 /*
6651 * We must have an instruction between local_irq_enable() and
6652 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6653 * the interrupt shadow. The stat.exits increment will do nicely.
6654 * But we need to prevent reordering, hence this barrier():
6655 */
6656 barrier();
6657
6658 kvm_guest_exit();
6659
6660 preempt_enable();
6661
f656ce01 6662 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6663
b6c7a5dc
HB		 6664 /*
6665 * Profile KVM exit RIPs:
6666 */
6667 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6668 unsigned long rip = kvm_rip_read(vcpu);
6669 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6670 }
6671
cc578287
ZA		 6672 if (unlikely(vcpu->arch.tsc_always_catchup))
6673 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6674
5cfb1d5a
MT		 6675 if (vcpu->arch.apic_attention)
6676 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6677
851ba692 6678 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6679 return r;
6680
6681cancel_injection:
6682 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6683 if (unlikely(vcpu->arch.apic_attention))
6684 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6685out:
6686 return r;
6687}
b6c7a5dc 6688
362c698f
PB		 6689static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6690{
bf9f6ac8
FW		 6691 if (!kvm_arch_vcpu_runnable(vcpu) &&
6692 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6693 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6694 kvm_vcpu_block(vcpu);
6695 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6696
6697 if (kvm_x86_ops->post_block)
6698 kvm_x86_ops->post_block(vcpu);
6699
9c8fd1ba
PB		 6700 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6701 return 1;
6702 }
362c698f
PB		 6703
6704 kvm_apic_accept_events(vcpu);
6705 switch(vcpu->arch.mp_state) {
6706 case KVM_MP_STATE_HALTED:
6707 vcpu->arch.pv.pv_unhalted = false;
6708 vcpu->arch.mp_state =
6709 KVM_MP_STATE_RUNNABLE;
6710 case KVM_MP_STATE_RUNNABLE:
6711 vcpu->arch.apf.halted = false;
6712 break;
6713 case KVM_MP_STATE_INIT_RECEIVED:
6714 break;
6715 default:
6716 return -EINTR;
6717 break;
6718 }
6719 return 1;
6720}
09cec754 6721
5d9bc648
PB		 6722static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6723{
6724 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6725 !vcpu->arch.apf.halted);
6726}
6727
362c698f 6728static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6729{
6730 int r;
f656ce01 6731 struct kvm *kvm = vcpu->kvm;
d7690175 6732
f656ce01 6733 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6734
362c698f 6735 for (;;) {
58f800d5 6736 if (kvm_vcpu_running(vcpu)) {
851ba692 6737 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6738 } else {
362c698f 6739 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6740 }
6741
09cec754
GN		 6742 if (r <= 0)
6743 break;
6744
6745 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6746 if (kvm_cpu_has_pending_timer(vcpu))
6747 kvm_inject_pending_timer_irqs(vcpu);
6748
782d422b
MG		 6749 if (dm_request_for_irq_injection(vcpu) &&
6750 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6751 r = 0;
6752 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6753 ++vcpu->stat.request_irq_exits;
362c698f 6754 break;
09cec754 6755 }
af585b92
GN		 6756
6757 kvm_check_async_pf_completion(vcpu);
6758
09cec754
GN		 6759 if (signal_pending(current)) {
6760 r = -EINTR;
851ba692 6761 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6762 ++vcpu->stat.signal_exits;
362c698f 6763 break;
09cec754
GN		 6764 }
6765 if (need_resched()) {
f656ce01 6766 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6767 cond_resched();
f656ce01 6768 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6769 }
b6c7a5dc
HB		 6770 }
6771
f656ce01 6772 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6773
6774 return r;
6775}
6776
716d51ab
GN		 6777static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6778{
6779 int r;
6780 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6781 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6782 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6783 if (r != EMULATE_DONE)
6784 return 0;
6785 return 1;
6786}
6787
6788static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6789{
6790 BUG_ON(!vcpu->arch.pio.count);
6791
6792 return complete_emulated_io(vcpu);
6793}
6794
f78146b0
AK		 6795/*
6796 * Implements the following, as a state machine:
6797 *
6798 * read:
6799 * for each fragment
87da7e66
XG		 6800 * for each mmio piece in the fragment
6801 * write gpa, len
6802 * exit
6803 * copy data
f78146b0
AK		 6804 * execute insn
6805 *
6806 * write:
6807 * for each fragment
87da7e66
XG		 6808 * for each mmio piece in the fragment
6809 * write gpa, len
6810 * copy data
6811 * exit
f78146b0 6812 */
716d51ab 6813static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6814{
6815 struct kvm_run *run = vcpu->run;
f78146b0 6816 struct kvm_mmio_fragment *frag;
87da7e66 6817 unsigned len;
5287f194 6818
716d51ab 6819 BUG_ON(!vcpu->mmio_needed);
5287f194 6820
716d51ab 6821 /* Complete previous fragment */
87da7e66
XG		 6822 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6823 len = min(8u, frag->len);
716d51ab 6824 if (!vcpu->mmio_is_write)
87da7e66
XG		 6825 memcpy(frag->data, run->mmio.data, len);
6826
6827 if (frag->len <= 8) {
6828 /* Switch to the next fragment. */
6829 frag++;
6830 vcpu->mmio_cur_fragment++;
6831 } else {
6832 /* Go forward to the next mmio piece. */
6833 frag->data += len;
6834 frag->gpa += len;
6835 frag->len -= len;
6836 }
6837
a08d3b3b 6838 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6839 vcpu->mmio_needed = 0;
0912c977
PB		 6840
6841 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6842 if (vcpu->mmio_is_write)
716d51ab
GN		 6843 return 1;
6844 vcpu->mmio_read_completed = 1;
6845 return complete_emulated_io(vcpu);
6846 }
87da7e66 6847
716d51ab
GN		 6848 run->exit_reason = KVM_EXIT_MMIO;
6849 run->mmio.phys_addr = frag->gpa;
6850 if (vcpu->mmio_is_write)
87da7e66
XG		 6851 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6852 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6853 run->mmio.is_write = vcpu->mmio_is_write;
6854 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6855 return 0;
5287f194
AK		 6856}
6857
716d51ab 6858
b6c7a5dc
HB		 6859int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6860{
c5bedc68 6861 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6862 int r;
6863 sigset_t sigsaved;
6864
c4d72e2d 6865 fpu__activate_curr(fpu);
e5c30142 6866
ac9f6dc0
AK		 6867 if (vcpu->sigset_active)
6868 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6869
a4535290 6870 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6871 kvm_vcpu_block(vcpu);
66450a21 6872 kvm_apic_accept_events(vcpu);
d7690175 6873 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6874 r = -EAGAIN;
6875 goto out;
b6c7a5dc
HB		 6876 }
6877
b6c7a5dc 6878 /* re-sync apic's tpr */
35754c98 6879 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6880 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6881 r = -EINVAL;
6882 goto out;
6883 }
6884 }
b6c7a5dc 6885
716d51ab
GN		 6886 if (unlikely(vcpu->arch.complete_userspace_io)) {
6887 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6888 vcpu->arch.complete_userspace_io = NULL;
6889 r = cui(vcpu);
6890 if (r <= 0)
6891 goto out;
6892 } else
6893 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6894
362c698f 6895 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6896
6897out:
f1d86e46 6898 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6899 if (vcpu->sigset_active)
6900 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6901
b6c7a5dc
HB		 6902 return r;
6903}
6904
6905int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6906{
7ae441ea
GN		 6907 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6908 /*
6909 * We are here if userspace calls get_regs() in the middle of
6910 * instruction emulation. Registers state needs to be copied
4a969980 6911 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6912 * that usually, but some bad designed PV devices (vmware
6913 * backdoor interface) need this to work
6914 */
dd856efa 6915 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6916 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6917 }
5fdbf976
MT		 6918 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6919 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6920 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6921 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6922 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6923 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6924 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6925 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6926#ifdef CONFIG_X86_64
5fdbf976
MT		 6927 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6928 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6929 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6930 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6931 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6932 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6933 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6934 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6935#endif
6936
5fdbf976 6937 regs->rip = kvm_rip_read(vcpu);
91586a3b 6938 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6939
b6c7a5dc
HB		 6940 return 0;
6941}
6942
6943int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6944{
7ae441ea
GN		 6945 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6946 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6947
5fdbf976
MT		 6948 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6949 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6950 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6951 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6952 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6953 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6954 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6955 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6956#ifdef CONFIG_X86_64
5fdbf976
MT		 6957 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6958 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6959 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6960 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6961 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6962 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6963 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6964 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6965#endif
6966
5fdbf976 6967 kvm_rip_write(vcpu, regs->rip);
91586a3b 6968 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6969
b4f14abd
JK		 6970 vcpu->arch.exception.pending = false;
6971
3842d135
AK		 6972 kvm_make_request(KVM_REQ_EVENT, vcpu);
6973
b6c7a5dc
HB		 6974 return 0;
6975}
6976
b6c7a5dc
HB		 6977void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6978{
6979 struct kvm_segment cs;
6980
3e6e0aab 6981 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6982 *db = cs.db;
6983 *l = cs.l;
6984}
6985EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6986
6987int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6988 struct kvm_sregs *sregs)
6989{
89a27f4d 6990 struct desc_ptr dt;
b6c7a5dc 6991
3e6e0aab
GT		 6992 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6993 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6994 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6995 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6996 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6997 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6998
3e6e0aab
GT		 6999 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7000 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7001
7002 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7003 sregs->idt.limit = dt.size;
7004 sregs->idt.base = dt.address;
b6c7a5dc 7005 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7006 sregs->gdt.limit = dt.size;
7007 sregs->gdt.base = dt.address;
b6c7a5dc 7008
4d4ec087 7009 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7010 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7011 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7012 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7013 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7014 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7015 sregs->apic_base = kvm_get_apic_base(vcpu);
7016
923c61bb 7017 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7018
36752c9b 7019 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7020 set_bit(vcpu->arch.interrupt.nr,
7021 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7022
b6c7a5dc
HB		 7023 return 0;
7024}
7025
62d9f0db
MT		 7026int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7027 struct kvm_mp_state *mp_state)
7028{
66450a21 7029 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7030 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7031 vcpu->arch.pv.pv_unhalted)
7032 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7033 else
7034 mp_state->mp_state = vcpu->arch.mp_state;
7035
62d9f0db
MT		 7036 return 0;
7037}
7038
7039int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7040 struct kvm_mp_state *mp_state)
7041{
66450a21
JK		 7042 if (!kvm_vcpu_has_lapic(vcpu) &&
7043 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7044 return -EINVAL;
7045
7046 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7047 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7048 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7049 } else
7050 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7051 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7052 return 0;
7053}
7054
7f3d35fd
KW		 7055int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7056 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7057{
9d74191a 7058 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7059 int ret;
e01c2426 7060
8ec4722d 7061 init_emulate_ctxt(vcpu);
c697518a 7062
7f3d35fd 7063 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7064 has_error_code, error_code);
c697518a 7065
c697518a 7066 if (ret)
19d04437 7067 return EMULATE_FAIL;
37817f29 7068
9d74191a
TY		 7069 kvm_rip_write(vcpu, ctxt->eip);
7070 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7071 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7072 return EMULATE_DONE;
37817f29
IE		 7073}
7074EXPORT_SYMBOL_GPL(kvm_task_switch);
7075
b6c7a5dc
HB		 7076int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7077 struct kvm_sregs *sregs)
7078{
58cb628d 7079 struct msr_data apic_base_msr;
b6c7a5dc 7080 int mmu_reset_needed = 0;
63f42e02 7081 int pending_vec, max_bits, idx;
89a27f4d 7082 struct desc_ptr dt;
b6c7a5dc 7083
6d1068b3
PM		 7084 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7085 return -EINVAL;
7086
89a27f4d
GN		 7087 dt.size = sregs->idt.limit;
7088 dt.address = sregs->idt.base;
b6c7a5dc 7089 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7090 dt.size = sregs->gdt.limit;
7091 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7092 kvm_x86_ops->set_gdt(vcpu, &dt);
7093
ad312c7c 7094 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7095 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7096 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7097 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7098
2d3ad1f4 7099 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7100
f6801dff 7101 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7102 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7103 apic_base_msr.data = sregs->apic_base;
7104 apic_base_msr.host_initiated = true;
7105 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7106
4d4ec087 7107 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7108 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7109 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7110
fc78f519 7111 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7112 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7113 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7114 kvm_update_cpuid(vcpu);
63f42e02
XG		 7115
7116 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7117 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7118 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7119 mmu_reset_needed = 1;
7120 }
63f42e02 7121 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7122
7123 if (mmu_reset_needed)
7124 kvm_mmu_reset_context(vcpu);
7125
a50abc3b 7126 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7127 pending_vec = find_first_bit(
7128 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7129 if (pending_vec < max_bits) {
66fd3f7f 7130 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7131 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7132 }
7133
3e6e0aab
GT		 7134 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7135 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7136 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7137 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7138 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7139 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7140
3e6e0aab
GT		 7141 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7142 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7143
5f0269f5
ME		 7144 update_cr8_intercept(vcpu);
7145
9c3e4aab 7146 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7147 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7148 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7149 !is_protmode(vcpu))
9c3e4aab
MT		 7150 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7151
3842d135
AK		 7152 kvm_make_request(KVM_REQ_EVENT, vcpu);
7153
b6c7a5dc
HB		 7154 return 0;
7155}
7156
d0bfb940
JK		 7157int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7158 struct kvm_guest_debug *dbg)
b6c7a5dc 7159{
355be0b9 7160 unsigned long rflags;
ae675ef0 7161 int i, r;
b6c7a5dc 7162
4f926bf2
JK		 7163 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7164 r = -EBUSY;
7165 if (vcpu->arch.exception.pending)
2122ff5e 7166 goto out;
4f926bf2
JK		 7167 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7168 kvm_queue_exception(vcpu, DB_VECTOR);
7169 else
7170 kvm_queue_exception(vcpu, BP_VECTOR);
7171 }
7172
91586a3b
JK		 7173 /*
7174 * Read rflags as long as potentially injected trace flags are still
7175 * filtered out.
7176 */
7177 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7178
7179 vcpu->guest_debug = dbg->control;
7180 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7181 vcpu->guest_debug = 0;
7182
7183 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7184 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7185 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7186 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7187 } else {
7188 for (i = 0; i < KVM_NR_DB_REGS; i++)
7189 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7190 }
c8639010 7191 kvm_update_dr7(vcpu);
ae675ef0 7192
f92653ee
JK		 7193 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7194 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7195 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7196
91586a3b
JK		 7197 /*
7198 * Trigger an rflags update that will inject or remove the trace
7199 * flags.
7200 */
7201 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7202
a96036b8 7203 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7204
4f926bf2 7205 r = 0;
d0bfb940 7206
2122ff5e 7207out:
b6c7a5dc
HB		 7208
7209 return r;
7210}
7211
8b006791
ZX		 7212/*
7213 * Translate a guest virtual address to a guest physical address.
7214 */
7215int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7216 struct kvm_translation *tr)
7217{
7218 unsigned long vaddr = tr->linear_address;
7219 gpa_t gpa;
f656ce01 7220 int idx;
8b006791 7221
f656ce01 7222 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7223 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7224 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7225 tr->physical_address = gpa;
7226 tr->valid = gpa != UNMAPPED_GVA;
7227 tr->writeable = 1;
7228 tr->usermode = 0;
8b006791
ZX		 7229
7230 return 0;
7231}
7232
d0752060
HB		 7233int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7234{
c47ada30 7235 struct fxregs_state *fxsave =
7366ed77 7236 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7237
d0752060
HB		 7238 memcpy(fpu->fpr, fxsave->st_space, 128);
7239 fpu->fcw = fxsave->cwd;
7240 fpu->fsw = fxsave->swd;
7241 fpu->ftwx = fxsave->twd;
7242 fpu->last_opcode = fxsave->fop;
7243 fpu->last_ip = fxsave->rip;
7244 fpu->last_dp = fxsave->rdp;
7245 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7246
d0752060
HB		 7247 return 0;
7248}
7249
7250int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7251{
c47ada30 7252 struct fxregs_state *fxsave =
7366ed77 7253 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7254
d0752060
HB		 7255 memcpy(fxsave->st_space, fpu->fpr, 128);
7256 fxsave->cwd = fpu->fcw;
7257 fxsave->swd = fpu->fsw;
7258 fxsave->twd = fpu->ftwx;
7259 fxsave->fop = fpu->last_opcode;
7260 fxsave->rip = fpu->last_ip;
7261 fxsave->rdp = fpu->last_dp;
7262 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7263
d0752060
HB		 7264 return 0;
7265}
7266
0ee6a517 7267static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7268{
bf935b0b 7269 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7270 if (cpu_has_xsaves)
7366ed77 7271 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7272 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7273
2acf923e
DC		 7274 /*
7275 * Ensure guest xcr0 is valid for loading
7276 */
d91cab78 7277 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7278
ad312c7c 7279 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7280}
d0752060
HB		 7281
7282void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7283{
2608d7a1 7284 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7285 return;
7286
2acf923e
DC		 7287 /*
7288 * Restore all possible states in the guest,
7289 * and assume host would use all available bits.
7290 * Guest xcr0 would be loaded later.
7291 */
7292 kvm_put_guest_xcr0(vcpu);
d0752060 7293 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7294 __kernel_fpu_begin();
003e2e8b 7295 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7296 trace_kvm_fpu(1);
d0752060 7297}
d0752060
HB		 7298
7299void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7300{
2acf923e
DC		 7301 kvm_put_guest_xcr0(vcpu);
7302
653f52c3
RR		 7303 if (!vcpu->guest_fpu_loaded) {
7304 vcpu->fpu_counter = 0;
d0752060 7305 return;
653f52c3 7306 }
d0752060
HB		 7307
7308 vcpu->guest_fpu_loaded = 0;
4f836347 7309 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7310 __kernel_fpu_end();
f096ed85 7311 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7312 /*
7313 * If using eager FPU mode, or if the guest is a frequent user
7314 * of the FPU, just leave the FPU active for next time.
7315 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7316 * the FPU in bursts will revert to loading it on demand.
7317 */
a9b4fb7e 7318 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7319 if (++vcpu->fpu_counter < 5)
7320 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7321 }
0c04851c 7322 trace_kvm_fpu(0);
d0752060 7323}
e9b11c17
ZX		 7324
7325void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7326{
12f9a48f 7327 kvmclock_reset(vcpu);
7f1ea208 7328
f5f48ee1 7329 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7330 kvm_x86_ops->vcpu_free(vcpu);
7331}
7332
7333struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7334 unsigned int id)
7335{
c447e76b
LL		 7336 struct kvm_vcpu *vcpu;
7337
6755bae8
ZA		 7338 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7339 printk_once(KERN_WARNING
7340 "kvm: SMP vm created on host with unstable TSC; "
7341 "guest TSC will not be reliable\n");
c447e76b
LL		 7342
7343 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7344
c447e76b 7345 return vcpu;
26e5215f 7346}
e9b11c17 7347
26e5215f
AK		 7348int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7349{
7350 int r;
e9b11c17 7351
19efffa2 7352 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7353 r = vcpu_load(vcpu);
7354 if (r)
7355 return r;
d28bc9dd 7356 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7357 kvm_mmu_setup(vcpu);
e9b11c17 7358 vcpu_put(vcpu);
26e5215f 7359 return r;
e9b11c17
ZX		 7360}
7361
31928aa5 7362void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7363{
8fe8ab46 7364 struct msr_data msr;
332967a3 7365 struct kvm *kvm = vcpu->kvm;
42897d86 7366
31928aa5
DD		 7367 if (vcpu_load(vcpu))
7368 return;
8fe8ab46
WA		 7369 msr.data = 0x0;
7370 msr.index = MSR_IA32_TSC;
7371 msr.host_initiated = true;
7372 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7373 vcpu_put(vcpu);
7374
630994b3
MT		 7375 if (!kvmclock_periodic_sync)
7376 return;
7377
332967a3
AJ		 7378 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7379 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7380}
7381
d40ccc62 7382void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7383{
9fc77441 7384 int r;
344d9588
GN		 7385 vcpu->arch.apf.msr_val = 0;
7386
9fc77441
MT		 7387 r = vcpu_load(vcpu);
7388 BUG_ON(r);
e9b11c17
ZX		 7389 kvm_mmu_unload(vcpu);
7390 vcpu_put(vcpu);
7391
7392 kvm_x86_ops->vcpu_free(vcpu);
7393}
7394
d28bc9dd 7395void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7396{
e69fab5d
PB		 7397 vcpu->arch.hflags = 0;
7398
7460fb4a
AK		 7399 atomic_set(&vcpu->arch.nmi_queued, 0);
7400 vcpu->arch.nmi_pending = 0;
448fa4a9 7401 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7402 kvm_clear_interrupt_queue(vcpu);
7403 kvm_clear_exception_queue(vcpu);
448fa4a9 7404
42dbaa5a 7405 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7406 kvm_update_dr0123(vcpu);
6f43ed01 7407 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7408 kvm_update_dr6(vcpu);
42dbaa5a 7409 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7410 kvm_update_dr7(vcpu);
42dbaa5a 7411
1119022c
NA		 7412 vcpu->arch.cr2 = 0;
7413
3842d135 7414 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7415 vcpu->arch.apf.msr_val = 0;
c9aaa895 7416 vcpu->arch.st.msr_val = 0;
3842d135 7417
12f9a48f
GC		 7418 kvmclock_reset(vcpu);
7419
af585b92
GN		 7420 kvm_clear_async_pf_completion_queue(vcpu);
7421 kvm_async_pf_hash_reset(vcpu);
7422 vcpu->arch.apf.halted = false;
3842d135 7423
64d60670 7424 if (!init_event) {
d28bc9dd 7425 kvm_pmu_reset(vcpu);
64d60670
PB		 7426 vcpu->arch.smbase = 0x30000;
7427 }
f5132b01 7428
66f7b72e
JS		 7429 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7430 vcpu->arch.regs_avail = ~0;
7431 vcpu->arch.regs_dirty = ~0;
7432
d28bc9dd 7433 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7434}
7435
2b4a273b 7436void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7437{
7438 struct kvm_segment cs;
7439
7440 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7441 cs.selector = vector << 8;
7442 cs.base = vector << 12;
7443 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7444 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7445}
7446
13a34e06 7447int kvm_arch_hardware_enable(void)
e9b11c17 7448{
ca84d1a2
ZA		 7449 struct kvm *kvm;
7450 struct kvm_vcpu *vcpu;
7451 int i;
0dd6a6ed
ZA		 7452 int ret;
7453 u64 local_tsc;
7454 u64 max_tsc = 0;
7455 bool stable, backwards_tsc = false;
18863bdd
AK		 7456
7457 kvm_shared_msr_cpu_online();
13a34e06 7458 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7459 if (ret != 0)
7460 return ret;
7461
4ea1636b 7462 local_tsc = rdtsc();
0dd6a6ed
ZA		 7463 stable = !check_tsc_unstable();
7464 list_for_each_entry(kvm, &vm_list, vm_list) {
7465 kvm_for_each_vcpu(i, vcpu, kvm) {
7466 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7467 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7468 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7469 backwards_tsc = true;
7470 if (vcpu->arch.last_host_tsc > max_tsc)
7471 max_tsc = vcpu->arch.last_host_tsc;
7472 }
7473 }
7474 }
7475
7476 /*
7477 * Sometimes, even reliable TSCs go backwards. This happens on
7478 * platforms that reset TSC during suspend or hibernate actions, but
7479 * maintain synchronization. We must compensate. Fortunately, we can
7480 * detect that condition here, which happens early in CPU bringup,
7481 * before any KVM threads can be running. Unfortunately, we can't
7482 * bring the TSCs fully up to date with real time, as we aren't yet far
7483 * enough into CPU bringup that we know how much real time has actually
7484 * elapsed; our helper function, get_kernel_ns() will be using boot
7485 * variables that haven't been updated yet.
7486 *
7487 * So we simply find the maximum observed TSC above, then record the
7488 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7489 * the adjustment will be applied. Note that we accumulate
7490 * adjustments, in case multiple suspend cycles happen before some VCPU
7491 * gets a chance to run again. In the event that no KVM threads get a
7492 * chance to run, we will miss the entire elapsed period, as we'll have
7493 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7494 * loose cycle time. This isn't too big a deal, since the loss will be
7495 * uniform across all VCPUs (not to mention the scenario is extremely
7496 * unlikely). It is possible that a second hibernate recovery happens
7497 * much faster than a first, causing the observed TSC here to be
7498 * smaller; this would require additional padding adjustment, which is
7499 * why we set last_host_tsc to the local tsc observed here.
7500 *
7501 * N.B. - this code below runs only on platforms with reliable TSC,
7502 * as that is the only way backwards_tsc is set above. Also note
7503 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7504 * have the same delta_cyc adjustment applied if backwards_tsc
7505 * is detected. Note further, this adjustment is only done once,
7506 * as we reset last_host_tsc on all VCPUs to stop this from being
7507 * called multiple times (one for each physical CPU bringup).
7508 *
4a969980 7509 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7510 * will be compensated by the logic in vcpu_load, which sets the TSC to
7511 * catchup mode. This will catchup all VCPUs to real time, but cannot
7512 * guarantee that they stay in perfect synchronization.
7513 */
7514 if (backwards_tsc) {
7515 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7516 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7517 list_for_each_entry(kvm, &vm_list, vm_list) {
7518 kvm_for_each_vcpu(i, vcpu, kvm) {
7519 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7520 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7521 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7522 }
7523
7524 /*
7525 * We have to disable TSC offset matching.. if you were
7526 * booting a VM while issuing an S4 host suspend....
7527 * you may have some problem. Solving this issue is
7528 * left as an exercise to the reader.
7529 */
7530 kvm->arch.last_tsc_nsec = 0;
7531 kvm->arch.last_tsc_write = 0;
7532 }
7533
7534 }
7535 return 0;
e9b11c17
ZX		 7536}
7537
13a34e06 7538void kvm_arch_hardware_disable(void)
e9b11c17 7539{
13a34e06
RK		 7540 kvm_x86_ops->hardware_disable();
7541 drop_user_return_notifiers();
e9b11c17
ZX		 7542}
7543
7544int kvm_arch_hardware_setup(void)
7545{
9e9c3fe4
NA		 7546 int r;
7547
7548 r = kvm_x86_ops->hardware_setup();
7549 if (r != 0)
7550 return r;
7551
35181e86
HZ		 7552 if (kvm_has_tsc_control) {
7553 /*
7554 * Make sure the user can only configure tsc_khz values that
7555 * fit into a signed integer.
7556 * A min value is not calculated needed because it will always
7557 * be 1 on all machines.
7558 */
7559 u64 max = min(0x7fffffffULL,
7560 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7561 kvm_max_guest_tsc_khz = max;
7562
ad721883 7563 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7564 }
ad721883 7565
9e9c3fe4
NA		 7566 kvm_init_msr_list();
7567 return 0;
e9b11c17
ZX		 7568}
7569
7570void kvm_arch_hardware_unsetup(void)
7571{
7572 kvm_x86_ops->hardware_unsetup();
7573}
7574
7575void kvm_arch_check_processor_compat(void *rtn)
7576{
7577 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7578}
7579
7580bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7581{
7582 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7583}
7584EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7585
7586bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7587{
7588 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7589}
7590
3e515705
AK		 7591bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7592{
35754c98 7593 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7594}
7595
54e9818f
GN		 7596struct static_key kvm_no_apic_vcpu __read_mostly;
7597
e9b11c17
ZX		 7598int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7599{
7600 struct page *page;
7601 struct kvm *kvm;
7602 int r;
7603
7604 BUG_ON(vcpu->kvm == NULL);
7605 kvm = vcpu->kvm;
7606
d62caabb 7607 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7608 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7609 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7610 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7611 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7612 else
a4535290 7613 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7614
7615 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7616 if (!page) {
7617 r = -ENOMEM;
7618 goto fail;
7619 }
ad312c7c 7620 vcpu->arch.pio_data = page_address(page);
e9b11c17 7621
cc578287 7622 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7623
e9b11c17
ZX		 7624 r = kvm_mmu_create(vcpu);
7625 if (r < 0)
7626 goto fail_free_pio_data;
7627
7628 if (irqchip_in_kernel(kvm)) {
7629 r = kvm_create_lapic(vcpu);
7630 if (r < 0)
7631 goto fail_mmu_destroy;
54e9818f
GN		 7632 } else
7633 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7634
890ca9ae
HY		 7635 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7636 GFP_KERNEL);
7637 if (!vcpu->arch.mce_banks) {
7638 r = -ENOMEM;
443c39bc 7639 goto fail_free_lapic;
890ca9ae
HY		 7640 }
7641 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7642
f1797359
WY		 7643 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7644 r = -ENOMEM;
f5f48ee1 7645 goto fail_free_mce_banks;
f1797359 7646 }
f5f48ee1 7647
0ee6a517 7648 fx_init(vcpu);
66f7b72e 7649
ba904635 7650 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7651 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7652
7653 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7654 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7655
5a4f55cd
EK		 7656 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7657
74545705
RK		 7658 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7659
af585b92 7660 kvm_async_pf_hash_reset(vcpu);
f5132b01 7661 kvm_pmu_init(vcpu);
af585b92 7662
1c1a9ce9
SR		 7663 vcpu->arch.pending_external_vector = -1;
7664
5c919412
AS		 7665 kvm_hv_vcpu_init(vcpu);
7666
e9b11c17 7667 return 0;
0ee6a517 7668
f5f48ee1
SY		 7669fail_free_mce_banks:
7670 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7671fail_free_lapic:
7672 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7673fail_mmu_destroy:
7674 kvm_mmu_destroy(vcpu);
7675fail_free_pio_data:
ad312c7c 7676 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7677fail:
7678 return r;
7679}
7680
7681void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7682{
f656ce01
MT		 7683 int idx;
7684
1f4b34f8 7685 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7686 kvm_pmu_destroy(vcpu);
36cb93fd 7687 kfree(vcpu->arch.mce_banks);
e9b11c17 7688 kvm_free_lapic(vcpu);
f656ce01 7689 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7690 kvm_mmu_destroy(vcpu);
f656ce01 7691 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7692 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7693 if (!lapic_in_kernel(vcpu))
54e9818f 7694 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7695}
d19a9cd2 7696
e790d9ef
RK		 7697void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7698{
ae97a3b8 7699 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7700}
7701
e08b9637 7702int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7703{
e08b9637
CO		 7704 if (type)
7705 return -EINVAL;
7706
6ef768fa 7707 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7708 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7709 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7710 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7711 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7712
5550af4d
SY		 7713 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7714 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7715 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7716 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7717 &kvm->arch.irq_sources_bitmap);
5550af4d 7718
038f8c11 7719 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7720 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7721 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7722
7723 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7724
7e44e449 7725 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7726 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7727
d89f5eff 7728 return 0;
d19a9cd2
ZX		 7729}
7730
7731static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7732{
9fc77441
MT		 7733 int r;
7734 r = vcpu_load(vcpu);
7735 BUG_ON(r);
d19a9cd2
ZX		 7736 kvm_mmu_unload(vcpu);
7737 vcpu_put(vcpu);
7738}
7739
7740static void kvm_free_vcpus(struct kvm *kvm)
7741{
7742 unsigned int i;
988a2cae 7743 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7744
7745 /*
7746 * Unpin any mmu pages first.
7747 */
af585b92
GN		 7748 kvm_for_each_vcpu(i, vcpu, kvm) {
7749 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7750 kvm_unload_vcpu_mmu(vcpu);
af585b92 7751 }
988a2cae
GN		 7752 kvm_for_each_vcpu(i, vcpu, kvm)
7753 kvm_arch_vcpu_free(vcpu);
7754
7755 mutex_lock(&kvm->lock);
7756 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7757 kvm->vcpus[i] = NULL;
d19a9cd2 7758
988a2cae
GN		 7759 atomic_set(&kvm->online_vcpus, 0);
7760 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7761}
7762
ad8ba2cd
SY		 7763void kvm_arch_sync_events(struct kvm *kvm)
7764{
332967a3 7765 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7766 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7767 kvm_free_all_assigned_devices(kvm);
aea924f6 7768 kvm_free_pit(kvm);
ad8ba2cd
SY		 7769}
7770
1d8007bd 7771int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7772{
7773 int i, r;
25188b99 7774 unsigned long hva;
f0d648bd
PB		 7775 struct kvm_memslots *slots = kvm_memslots(kvm);
7776 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7777
7778 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7779 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7780 return -EINVAL;
9da0e4d5 7781
f0d648bd
PB		 7782 slot = id_to_memslot(slots, id);
7783 if (size) {
7784 if (WARN_ON(slot->npages))
7785 return -EEXIST;
7786
7787 /*
7788 * MAP_SHARED to prevent internal slot pages from being moved
7789 * by fork()/COW.
7790 */
7791 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7792 MAP_SHARED | MAP_ANONYMOUS, 0);
7793 if (IS_ERR((void *)hva))
7794 return PTR_ERR((void *)hva);
7795 } else {
7796 if (!slot->npages)
7797 return 0;
7798
7799 hva = 0;
7800 }
7801
7802 old = *slot;
9da0e4d5 7803 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7804 struct kvm_userspace_memory_region m;
9da0e4d5 7805
1d8007bd
PB		 7806 m.slot = id | (i << 16);
7807 m.flags = 0;
7808 m.guest_phys_addr = gpa;
f0d648bd 7809 m.userspace_addr = hva;
1d8007bd 7810 m.memory_size = size;
9da0e4d5
PB		 7811 r = __kvm_set_memory_region(kvm, &m);
7812 if (r < 0)
7813 return r;
7814 }
7815
f0d648bd
PB		 7816 if (!size) {
7817 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7818 WARN_ON(r < 0);
7819 }
7820
9da0e4d5
PB		 7821 return 0;
7822}
7823EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7824
1d8007bd 7825int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7826{
7827 int r;
7828
7829 mutex_lock(&kvm->slots_lock);
1d8007bd 7830 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7831 mutex_unlock(&kvm->slots_lock);
7832
7833 return r;
7834}
7835EXPORT_SYMBOL_GPL(x86_set_memory_region);
7836
d19a9cd2
ZX		 7837void kvm_arch_destroy_vm(struct kvm *kvm)
7838{
27469d29
AH		 7839 if (current->mm == kvm->mm) {
7840 /*
7841 * Free memory regions allocated on behalf of userspace,
7842 * unless the the memory map has changed due to process exit
7843 * or fd copying.
7844 */
1d8007bd
PB		 7845 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7846 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7847 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7848 }
6eb55818 7849 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7850 kfree(kvm->arch.vpic);
7851 kfree(kvm->arch.vioapic);
d19a9cd2 7852 kvm_free_vcpus(kvm);
1e08ec4a 7853 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7854}
0de10343 7855
5587027c 7856void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7857 struct kvm_memory_slot *dont)
7858{
7859 int i;
7860
d89cc617
TY		 7861 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7862 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7863 kvfree(free->arch.rmap[i]);
d89cc617 7864 free->arch.rmap[i] = NULL;
77d11309 7865 }
d89cc617
TY		 7866 if (i == 0)
7867 continue;
7868
7869 if (!dont || free->arch.lpage_info[i - 1] !=
7870 dont->arch.lpage_info[i - 1]) {
548ef284 7871 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7872 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7873 }
7874 }
7875}
7876
5587027c
AK		 7877int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7878 unsigned long npages)
db3fe4eb
TY		 7879{
7880 int i;
7881
d89cc617 7882 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7883 unsigned long ugfn;
7884 int lpages;
d89cc617 7885 int level = i + 1;
db3fe4eb
TY		 7886
7887 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7888 slot->base_gfn, level) + 1;
7889
d89cc617
TY		 7890 slot->arch.rmap[i] =
7891 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7892 if (!slot->arch.rmap[i])
77d11309 7893 goto out_free;
d89cc617
TY		 7894 if (i == 0)
7895 continue;
77d11309 7896
d89cc617
TY		 7897 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7898 sizeof(*slot->arch.lpage_info[i - 1]));
7899 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7900 goto out_free;
7901
7902 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7903 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7904 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7905 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7906 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7907 /*
7908 * If the gfn and userspace address are not aligned wrt each
7909 * other, or if explicitly asked to, disable large page
7910 * support for this slot
7911 */
7912 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7913 !kvm_largepages_enabled()) {
7914 unsigned long j;
7915
7916 for (j = 0; j < lpages; ++j)
d89cc617 7917 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7918 }
7919 }
7920
7921 return 0;
7922
7923out_free:
d89cc617 7924 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7925 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7926 slot->arch.rmap[i] = NULL;
7927 if (i == 0)
7928 continue;
7929
548ef284 7930 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7931 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7932 }
7933 return -ENOMEM;
7934}
7935
15f46015 7936void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7937{
e6dff7d1
TY		 7938 /*
7939 * memslots->generation has been incremented.
7940 * mmio generation may have reached its maximum value.
7941 */
54bf36aa 7942 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7943}
7944
f7784b8e
MT		 7945int kvm_arch_prepare_memory_region(struct kvm *kvm,
7946 struct kvm_memory_slot *memslot,
09170a49 7947 const struct kvm_userspace_memory_region *mem,
7b6195a9 7948 enum kvm_mr_change change)
0de10343 7949{
f7784b8e
MT		 7950 return 0;
7951}
7952
88178fd4
KH		 7953static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7954 struct kvm_memory_slot *new)
7955{
7956 /* Still write protect RO slot */
7957 if (new->flags & KVM_MEM_READONLY) {
7958 kvm_mmu_slot_remove_write_access(kvm, new);
7959 return;
7960 }
7961
7962 /*
7963 * Call kvm_x86_ops dirty logging hooks when they are valid.
7964 *
7965 * kvm_x86_ops->slot_disable_log_dirty is called when:
7966 *
7967 * - KVM_MR_CREATE with dirty logging is disabled
7968 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7969 *
7970 * The reason is, in case of PML, we need to set D-bit for any slots
7971 * with dirty logging disabled in order to eliminate unnecessary GPA
7972 * logging in PML buffer (and potential PML buffer full VMEXT). This
7973 * guarantees leaving PML enabled during guest's lifetime won't have
7974 * any additonal overhead from PML when guest is running with dirty
7975 * logging disabled for memory slots.
7976 *
7977 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7978 * to dirty logging mode.
7979 *
7980 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7981 *
7982 * In case of write protect:
7983 *
7984 * Write protect all pages for dirty logging.
7985 *
7986 * All the sptes including the large sptes which point to this
7987 * slot are set to readonly. We can not create any new large
7988 * spte on this slot until the end of the logging.
7989 *
7990 * See the comments in fast_page_fault().
7991 */
7992 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7993 if (kvm_x86_ops->slot_enable_log_dirty)
7994 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7995 else
7996 kvm_mmu_slot_remove_write_access(kvm, new);
7997 } else {
7998 if (kvm_x86_ops->slot_disable_log_dirty)
7999 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8000 }
8001}
8002
f7784b8e 8003void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8004 const struct kvm_userspace_memory_region *mem,
8482644a 8005 const struct kvm_memory_slot *old,
f36f3f28 8006 const struct kvm_memory_slot *new,
8482644a 8007 enum kvm_mr_change change)
f7784b8e 8008{
8482644a 8009 int nr_mmu_pages = 0;
f7784b8e 8010
48c0e4e9
XG		 8011 if (!kvm->arch.n_requested_mmu_pages)
8012 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8013
48c0e4e9 8014 if (nr_mmu_pages)
0de10343 8015 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8016
3ea3b7fa
WL		 8017 /*
8018 * Dirty logging tracks sptes in 4k granularity, meaning that large
8019 * sptes have to be split. If live migration is successful, the guest
8020 * in the source machine will be destroyed and large sptes will be
8021 * created in the destination. However, if the guest continues to run
8022 * in the source machine (for example if live migration fails), small
8023 * sptes will remain around and cause bad performance.
8024 *
8025 * Scan sptes if dirty logging has been stopped, dropping those
8026 * which can be collapsed into a single large-page spte. Later
8027 * page faults will create the large-page sptes.
8028 */
8029 if ((change != KVM_MR_DELETE) &&
8030 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8031 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8032 kvm_mmu_zap_collapsible_sptes(kvm, new);
8033
c972f3b1 8034 /*
88178fd4 8035 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8036 *
88178fd4
KH		 8037 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8038 * been zapped so no dirty logging staff is needed for old slot. For
8039 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8040 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8041 *
8042 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8043 */
88178fd4 8044 if (change != KVM_MR_DELETE)
f36f3f28 8045 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8046}
1d737c8a 8047
2df72e9b 8048void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8049{
6ca18b69 8050 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8051}
8052
2df72e9b
MT		 8053void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8054 struct kvm_memory_slot *slot)
8055{
6ca18b69 8056 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8057}
8058
5d9bc648
PB		 8059static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8060{
8061 if (!list_empty_careful(&vcpu->async_pf.done))
8062 return true;
8063
8064 if (kvm_apic_has_events(vcpu))
8065 return true;
8066
8067 if (vcpu->arch.pv.pv_unhalted)
8068 return true;
8069
8070 if (atomic_read(&vcpu->arch.nmi_queued))
8071 return true;
8072
73917739
PB		 8073 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8074 return true;
8075
5d9bc648
PB		 8076 if (kvm_arch_interrupt_allowed(vcpu) &&
8077 kvm_cpu_has_interrupt(vcpu))
8078 return true;
8079
1f4b34f8
AS		 8080 if (kvm_hv_has_stimer_pending(vcpu))
8081 return true;
8082
5d9bc648
PB		 8083 return false;
8084}
8085
1d737c8a
ZX		 8086int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8087{
b6b8a145
JK		 8088 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8089 kvm_x86_ops->check_nested_events(vcpu, false);
8090
5d9bc648 8091 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8092}
5736199a 8093
b6d33834 8094int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8095{
b6d33834 8096 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8097}
78646121
GN		 8098
8099int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8100{
8101 return kvm_x86_ops->interrupt_allowed(vcpu);
8102}
229456fc 8103
82b32774 8104unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8105{
82b32774
NA		 8106 if (is_64_bit_mode(vcpu))
8107 return kvm_rip_read(vcpu);
8108 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8109 kvm_rip_read(vcpu));
8110}
8111EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8112
82b32774
NA		 8113bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8114{
8115 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8116}
8117EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8118
94fe45da
JK		 8119unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8120{
8121 unsigned long rflags;
8122
8123 rflags = kvm_x86_ops->get_rflags(vcpu);
8124 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8125 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8126 return rflags;
8127}
8128EXPORT_SYMBOL_GPL(kvm_get_rflags);
8129
6addfc42 8130static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8131{
8132 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8133 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8134 rflags |= X86_EFLAGS_TF;
94fe45da 8135 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8136}
8137
8138void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8139{
8140 __kvm_set_rflags(vcpu, rflags);
3842d135 8141 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8142}
8143EXPORT_SYMBOL_GPL(kvm_set_rflags);
8144
56028d08
GN		 8145void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8146{
8147 int r;
8148
fb67e14f 8149 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8150 work->wakeup_all)
56028d08
GN		 8151 return;
8152
8153 r = kvm_mmu_reload(vcpu);
8154 if (unlikely(r))
8155 return;
8156
fb67e14f
XG		 8157 if (!vcpu->arch.mmu.direct_map &&
8158 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8159 return;
8160
56028d08
GN		 8161 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8162}
8163
af585b92
GN		 8164static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8165{
8166 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8167}
8168
8169static inline u32 kvm_async_pf_next_probe(u32 key)
8170{
8171 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8172}
8173
8174static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8175{
8176 u32 key = kvm_async_pf_hash_fn(gfn);
8177
8178 while (vcpu->arch.apf.gfns[key] != ~0)
8179 key = kvm_async_pf_next_probe(key);
8180
8181 vcpu->arch.apf.gfns[key] = gfn;
8182}
8183
8184static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8185{
8186 int i;
8187 u32 key = kvm_async_pf_hash_fn(gfn);
8188
8189 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8190 (vcpu->arch.apf.gfns[key] != gfn &&
8191 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8192 key = kvm_async_pf_next_probe(key);
8193
8194 return key;
8195}
8196
8197bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8198{
8199 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8200}
8201
8202static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8203{
8204 u32 i, j, k;
8205
8206 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8207 while (true) {
8208 vcpu->arch.apf.gfns[i] = ~0;
8209 do {
8210 j = kvm_async_pf_next_probe(j);
8211 if (vcpu->arch.apf.gfns[j] == ~0)
8212 return;
8213 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8214 /*
8215 * k lies cyclically in ]i,j]
8216 * | i.k.j |
8217 * |....j i.k.| or |.k..j i...|
8218 */
8219 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8220 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8221 i = j;
8222 }
8223}
8224
7c90705b
GN		 8225static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8226{
8227
8228 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8229 sizeof(val));
8230}
8231
af585b92
GN		 8232void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8233 struct kvm_async_pf *work)
8234{
6389ee94
AK		 8235 struct x86_exception fault;
8236
7c90705b 8237 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8238 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8239
8240 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8241 (vcpu->arch.apf.send_user_only &&
8242 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8243 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8244 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8245 fault.vector = PF_VECTOR;
8246 fault.error_code_valid = true;
8247 fault.error_code = 0;
8248 fault.nested_page_fault = false;
8249 fault.address = work->arch.token;
8250 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8251 }
af585b92
GN		 8252}
8253
8254void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8255 struct kvm_async_pf *work)
8256{
6389ee94
AK		 8257 struct x86_exception fault;
8258
7c90705b 8259 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8260 if (work->wakeup_all)
7c90705b
GN		 8261 work->arch.token = ~0; /* broadcast wakeup */
8262 else
8263 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8264
8265 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8266 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8267 fault.vector = PF_VECTOR;
8268 fault.error_code_valid = true;
8269 fault.error_code = 0;
8270 fault.nested_page_fault = false;
8271 fault.address = work->arch.token;
8272 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8273 }
e6d53e3b 8274 vcpu->arch.apf.halted = false;
a4fa1635 8275 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8276}
8277
8278bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8279{
8280 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8281 return true;
8282 else
8283 return !kvm_event_needs_reinjection(vcpu) &&
8284 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8285}
8286
5544eb9b
PB		 8287void kvm_arch_start_assignment(struct kvm *kvm)
8288{
8289 atomic_inc(&kvm->arch.assigned_device_count);
8290}
8291EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8292
8293void kvm_arch_end_assignment(struct kvm *kvm)
8294{
8295 atomic_dec(&kvm->arch.assigned_device_count);
8296}
8297EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8298
8299bool kvm_arch_has_assigned_device(struct kvm *kvm)
8300{
8301 return atomic_read(&kvm->arch.assigned_device_count);
8302}
8303EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8304
e0f0bbc5
AW		 8305void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8306{
8307 atomic_inc(&kvm->arch.noncoherent_dma_count);
8308}
8309EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8310
8311void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8312{
8313 atomic_dec(&kvm->arch.noncoherent_dma_count);
8314}
8315EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8316
8317bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8318{
8319 return atomic_read(&kvm->arch.noncoherent_dma_count);
8320}
8321EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8322
87276880
FW		 8323int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8324 struct irq_bypass_producer *prod)
8325{
8326 struct kvm_kernel_irqfd *irqfd =
8327 container_of(cons, struct kvm_kernel_irqfd, consumer);
8328
8329 if (kvm_x86_ops->update_pi_irte) {
8330 irqfd->producer = prod;
8331 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8332 prod->irq, irqfd->gsi, 1);
8333 }
8334
8335 return -EINVAL;
8336}
8337
8338void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8339 struct irq_bypass_producer *prod)
8340{
8341 int ret;
8342 struct kvm_kernel_irqfd *irqfd =
8343 container_of(cons, struct kvm_kernel_irqfd, consumer);
8344
8345 if (!kvm_x86_ops->update_pi_irte) {
8346 WARN_ON(irqfd->producer != NULL);
8347 return;
8348 }
8349
8350 WARN_ON(irqfd->producer != prod);
8351 irqfd->producer = NULL;
8352
8353 /*
8354 * When producer of consumer is unregistered, we change back to
8355 * remapped mode, so we can re-use the current implementation
8356 * when the irq is masked/disabed or the consumer side (KVM
8357 * int this case doesn't want to receive the interrupts.
8358 */
8359 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8360 if (ret)
8361 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8362 " fails: %d\n", irqfd->consumer.token, ret);
8363}
8364
8365int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8366 uint32_t guest_irq, bool set)
8367{
8368 if (!kvm_x86_ops->update_pi_irte)
8369 return -EINVAL;
8370
8371 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8372}
8373
229456fc 8374EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8375EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8376EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8377EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8378EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8379EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8380EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8381EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8382EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8383EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8384EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8385EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8386EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8387EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8388EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8389EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8390EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git