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[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
aec51dc4 54#include <trace/events/kvm.h>
2ed152af 55
229456fc
MT		 56#define CREATE_TRACE_POINTS
57#include "trace.h"
043405e1 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 153 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 154 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 155 { "request_irq", VCPU_STAT(request_irq_exits) },
156 { "irq_exits", VCPU_STAT(irq_exits) },
157 { "host_state_reload", VCPU_STAT(host_state_reload) },
158 { "efer_reload", VCPU_STAT(efer_reload) },
159 { "fpu_reload", VCPU_STAT(fpu_reload) },
160 { "insn_emulation", VCPU_STAT(insn_emulation) },
161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 162 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 163 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
165 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
168 { "mmu_flooded", VM_STAT(mmu_flooded) },
169 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 171 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 173 { "largepages", VM_STAT(lpages) },
417bc304
HB		 174 { NULL }
175};
176
2acf923e
DC		 177u64 __read_mostly host_xcr0;
178
b6785def 179static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 180
af585b92
GN		 181static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
182{
183 int i;
184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
185 vcpu->arch.apf.gfns[i] = ~0;
186}
187
18863bdd
AK		 188static void kvm_on_user_return(struct user_return_notifier *urn)
189{
190 unsigned slot;
18863bdd
AK		 191 struct kvm_shared_msrs *locals
192 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 193 struct kvm_shared_msr_values *values;
18863bdd
AK		 194
195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 196 values = &locals->values[slot];
197 if (values->host != values->curr) {
198 wrmsrl(shared_msrs_global.msrs[slot], values->host);
199 values->curr = values->host;
18863bdd
AK		 200 }
201 }
202 locals->registered = false;
203 user_return_notifier_unregister(urn);
204}
205
2bf78fa7 206static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 207{
18863bdd 208 u64 value;
013f6a5d
MT		 209 unsigned int cpu = smp_processor_id();
210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 211
2bf78fa7
SY		 212 /* only read, and nobody should modify it at this time,
213 * so don't need lock */
214 if (slot >= shared_msrs_global.nr) {
215 printk(KERN_ERR "kvm: invalid MSR slot!");
216 return;
217 }
218 rdmsrl_safe(msr, &value);
219 smsr->values[slot].host = value;
220 smsr->values[slot].curr = value;
221}
222
223void kvm_define_shared_msr(unsigned slot, u32 msr)
224{
0123be42 225 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 226 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 227 if (slot >= shared_msrs_global.nr)
228 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 229}
230EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232static void kvm_shared_msr_cpu_online(void)
233{
234 unsigned i;
18863bdd
AK		 235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 237 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 238}
239
8b3c3104 240int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 241{
013f6a5d
MT		 242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 244 int err;
18863bdd 245
2bf78fa7 246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 247 return 0;
2bf78fa7 248 smsr->values[slot].curr = value;
8b3c3104
AH		 249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
18863bdd
AK		 253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
8b3c3104 258 return 0;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
13a34e06 262static void drop_user_return_notifiers(void)
3548bab5 263{
013f6a5d
MT		 264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269}
270
6866b83e
CO		 271u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272{
8a5a87d9 273 return vcpu->arch.apic_base;
6866b83e
CO		 274}
275EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
58cb628d
JK		 277int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278{
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
6866b83e
CO		 297}
298EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
2605fc21 300asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 301{
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304}
305EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
3fd28fce
ED		 307#define EXCPT_BENIGN 0
308#define EXCPT_CONTRIBUTORY 1
309#define EXCPT_PF 2
310
311static int exception_class(int vector)
312{
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326}
327
d6e8c854
NA		 328#define EXCPT_FAULT 0
329#define EXCPT_TRAP 1
330#define EXCPT_ABORT 2
331#define EXCPT_INTERRUPT 3
332
333static int exception_type(int vector)
334{
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351}
352
3fd28fce 353static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
3fd28fce
ED		 356{
357 u32 prev_nr;
358 int class1, class2;
359
3842d135
AK		 360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
3fd28fce
ED		 362 if (!vcpu->arch.exception.pending) {
363 queue:
3ffb2468
NA		 364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
3fd28fce
ED		 366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
3f0fd292 370 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
a8eeb04a 378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395}
396
298101da
AK		 397void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
ce7ddec4
JR		 403void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404{
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
db8fcefa 409void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 410{
db8fcefa
AP		 411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415}
416EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 417
6389ee94 418void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 419{
420 ++vcpu->stat.pf_guest;
6389ee94
AK		 421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 423}
27d6c865 424EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 425
ef54bcfe 426static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 427{
6389ee94
AK		 428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 430 else
6389ee94 431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 432
433 return fault->nested_page_fault;
d4f8cf66
JR		 434}
435
3419ffc8
SY		 436void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437{
7460fb4a
AK		 438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 440}
441EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
298101da
AK		 443void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444{
ce7ddec4 445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 446}
447EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
ce7ddec4
JR		 449void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450{
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452}
453EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
0a79b009
AK		 455/*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 460{
0a79b009
AK		 461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
298101da 465}
0a79b009 466EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 467
16f8a6f9
NA		 468bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469{
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475}
476EXPORT_SYMBOL_GPL(kvm_require_dr);
477
ec92fe44
JR		 478/*
479 * This function will be used to read from the physical memory of the currently
54bf36aa 480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 481 * can read from guest physical or from the guest's guest physical memory.
482 */
483int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486{
54987b7a 487 struct x86_exception exception;
ec92fe44
JR		 488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
54987b7a 492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
54bf36aa 498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 499}
500EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
69b0049a 502static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 503 void *data, int offset, int len, u32 access)
504{
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507}
508
a03490ed
CO		 509/*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
ff03a073 512int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 513{
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
ff03a073 518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 519
ff03a073
JR		 520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 528 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 529 (pdpte[i] &
530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 624
625 if ((cr0 ^ old_cr0) & X86_CR0_CD)
626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
627
0f12244f
GN		 628 return 0;
629}
2d3ad1f4 630EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 631
2d3ad1f4 632void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 633{
49a9b07e 634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 637
42bdf991
MT		 638static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
639{
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
641 !vcpu->guest_xcr0_loaded) {
642 /* kvm_set_xcr() also depends on this */
643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
644 vcpu->guest_xcr0_loaded = 1;
645 }
646}
647
648static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (vcpu->guest_xcr0_loaded) {
651 if (vcpu->arch.xcr0 != host_xcr0)
652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
653 vcpu->guest_xcr0_loaded = 0;
654 }
655}
656
69b0049a 657static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 658{
56c103ec
LJ		 659 u64 xcr0 = xcr;
660 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 661 u64 valid_bits;
2acf923e
DC		 662
663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
664 if (index != XCR_XFEATURE_ENABLED_MASK)
665 return 1;
2acf923e
DC		 666 if (!(xcr0 & XSTATE_FP))
667 return 1;
668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
669 return 1;
46c34cb0
PB		 670
671 /*
672 * Do not allow the guest to set bits that we do not support
673 * saving. However, xcr0 bit 0 is always set, even if the
674 * emulated CPU does not support XSAVE (see fx_init).
675 */
676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
677 if (xcr0 & ~valid_bits)
2acf923e 678 return 1;
46c34cb0 679
390bd528
LJ		 680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
681 return 1;
682
612263b3
CP		 683 if (xcr0 & XSTATE_AVX512) {
684 if (!(xcr0 & XSTATE_YMM))
685 return 1;
686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
687 return 1;
688 }
42bdf991 689 kvm_put_guest_xcr0(vcpu);
2acf923e 690 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 691
692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
693 kvm_update_cpuid(vcpu);
2acf923e
DC		 694 return 0;
695}
696
697int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
698{
764bcbc5
Z		 699 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
700 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 701 kvm_inject_gp(vcpu, 0);
702 return 1;
703 }
704 return 0;
705}
706EXPORT_SYMBOL_GPL(kvm_set_xcr);
707
a83b29c6 708int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 709{
fc78f519 710 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
712 X86_CR4_SMEP | X86_CR4_SMAP;
713
0f12244f
GN		 714 if (cr4 & CR4_RESERVED_BITS)
715 return 1;
a03490ed 716
2acf923e
DC		 717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
718 return 1;
719
c68b734f
YW		 720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
721 return 1;
722
97ec8c06
FW		 723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
724 return 1;
725
afcbf13f 726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 727 return 1;
728
a03490ed 729 if (is_long_mode(vcpu)) {
0f12244f
GN		 730 if (!(cr4 & X86_CR4_PAE))
731 return 1;
a2edf57f
AK		 732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
733 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
735 kvm_read_cr3(vcpu)))
0f12244f
GN		 736 return 1;
737
ad756a16
MJ		 738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
739 if (!guest_cpuid_has_pcid(vcpu))
740 return 1;
741
742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
744 return 1;
745 }
746
5e1746d6 747 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 748 return 1;
a03490ed 749
ad756a16
MJ		 750 if (((cr4 ^ old_cr4) & pdptr_bits) ||
751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 752 kvm_mmu_reset_context(vcpu);
0f12244f 753
2acf923e 754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 755 kvm_update_cpuid(vcpu);
2acf923e 756
0f12244f
GN		 757 return 0;
758}
2d3ad1f4 759EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 760
2390218b 761int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 762{
ac146235 763#ifdef CONFIG_X86_64
9d88fca7 764 cr3 &= ~CR3_PCID_INVD;
ac146235 765#endif
9d88fca7 766
9f8fe504 767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 768 kvm_mmu_sync_roots(vcpu);
77c3913b 769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 770 return 0;
d835dfec
AK		 771 }
772
a03490ed 773 if (is_long_mode(vcpu)) {
d9f89b88
JK		 774 if (cr3 & CR3_L_MODE_RESERVED_BITS)
775 return 1;
776 } else if (is_pae(vcpu) && is_paging(vcpu) &&
777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 778 return 1;
a03490ed 779
0f12244f 780 vcpu->arch.cr3 = cr3;
aff48baa 781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 782 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 783 return 0;
784}
2d3ad1f4 785EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 786
eea1cff9 787int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 788{
0f12244f
GN		 789 if (cr8 & CR8_RESERVED_BITS)
790 return 1;
35754c98 791 if (lapic_in_kernel(vcpu))
a03490ed
CO		 792 kvm_lapic_set_tpr(vcpu, cr8);
793 else
ad312c7c 794 vcpu->arch.cr8 = cr8;
0f12244f
GN		 795 return 0;
796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 798
2d3ad1f4 799unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 800{
35754c98 801 if (lapic_in_kernel(vcpu))
a03490ed
CO		 802 return kvm_lapic_get_cr8(vcpu);
803 else
ad312c7c 804 return vcpu->arch.cr8;
a03490ed 805}
2d3ad1f4 806EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 807
ae561ede
NA		 808static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
809{
810 int i;
811
812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
813 for (i = 0; i < KVM_NR_DB_REGS; i++)
814 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
816 }
817}
818
73aaf249
JK		 819static void kvm_update_dr6(struct kvm_vcpu *vcpu)
820{
821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
823}
824
c8639010
JK		 825static void kvm_update_dr7(struct kvm_vcpu *vcpu)
826{
827 unsigned long dr7;
828
829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 dr7 = vcpu->arch.guest_debug_dr7;
831 else
832 dr7 = vcpu->arch.dr7;
833 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
835 if (dr7 & DR7_BP_EN_MASK)
836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 837}
838
6f43ed01
NA		 839static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
840{
841 u64 fixed = DR6_FIXED_1;
842
843 if (!guest_cpuid_has_rtm(vcpu))
844 fixed |= DR6_RTM;
845 return fixed;
846}
847
338dbc97 848static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 849{
850 switch (dr) {
851 case 0 ... 3:
852 vcpu->arch.db[dr] = val;
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
854 vcpu->arch.eff_db[dr] = val;
855 break;
856 case 4:
020df079
GN		 857 /* fall through */
858 case 6:
338dbc97
GN		 859 if (val & 0xffffffff00000000ULL)
860 return -1; /* #GP */
6f43ed01 861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 862 kvm_update_dr6(vcpu);
020df079
GN		 863 break;
864 case 5:
020df079
GN		 865 /* fall through */
866 default: /* 7 */
338dbc97
GN		 867 if (val & 0xffffffff00000000ULL)
868 return -1; /* #GP */
020df079 869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 870 kvm_update_dr7(vcpu);
020df079
GN		 871 break;
872 }
873
874 return 0;
875}
338dbc97
GN		 876
877int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
878{
16f8a6f9 879 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 880 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 881 return 1;
882 }
883 return 0;
338dbc97 884}
020df079
GN		 885EXPORT_SYMBOL_GPL(kvm_set_dr);
886
16f8a6f9 887int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 888{
889 switch (dr) {
890 case 0 ... 3:
891 *val = vcpu->arch.db[dr];
892 break;
893 case 4:
020df079
GN		 894 /* fall through */
895 case 6:
73aaf249
JK		 896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
897 *val = vcpu->arch.dr6;
898 else
899 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 900 break;
901 case 5:
020df079
GN		 902 /* fall through */
903 default: /* 7 */
904 *val = vcpu->arch.dr7;
905 break;
906 }
338dbc97
GN		 907 return 0;
908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_get_dr);
910
022cd0e8
AK		 911bool kvm_rdpmc(struct kvm_vcpu *vcpu)
912{
913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
914 u64 data;
915 int err;
916
c6702c9d 917 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 918 if (err)
919 return err;
920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
922 return err;
923}
924EXPORT_SYMBOL_GPL(kvm_rdpmc);
925
043405e1
CO		 926/*
927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
929 *
930 * This list is modified at module load time to reflect the
e3267cbb 931 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
933 * may depend on host virtualization features rather than host cpu features.
043405e1 934 */
e3267cbb 935
043405e1
CO		 936static u32 msrs_to_save[] = {
937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 938 MSR_STAR,
043405e1
CO		 939#ifdef CONFIG_X86_64
940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941#endif
b3897a49 942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 944};
945
946static unsigned num_msrs_to_save;
947
62ef68bb
PB		 948static u32 emulated_msrs[] = {
949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 955 HV_X64_MSR_RESET,
11c4b1ca 956 HV_X64_MSR_VP_INDEX,
9eec50b8 957 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 958 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
959 MSR_KVM_PV_EOI_EN,
960
ba904635 961 MSR_IA32_TSC_ADJUST,
a3e06bbe 962 MSR_IA32_TSCDEADLINE,
043405e1 963 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 964 MSR_IA32_MCG_STATUS,
965 MSR_IA32_MCG_CTL,
64d60670 966 MSR_IA32_SMBASE,
043405e1
CO		 967};
968
62ef68bb
PB		 969static unsigned num_emulated_msrs;
970
384bb783 971bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 972{
b69e8cae 973 if (efer & efer_reserved_bits)
384bb783 974 return false;
15c4a640 975
1b2fd70c
AG		 976 if (efer & EFER_FFXSR) {
977 struct kvm_cpuid_entry2 *feat;
978
979 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 980 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 981 return false;
1b2fd70c
AG		 982 }
983
d8017474
AG		 984 if (efer & EFER_SVME) {
985 struct kvm_cpuid_entry2 *feat;
986
987 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 988 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 989 return false;
d8017474
AG		 990 }
991
384bb783
JK		 992 return true;
993}
994EXPORT_SYMBOL_GPL(kvm_valid_efer);
995
996static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
997{
998 u64 old_efer = vcpu->arch.efer;
999
1000 if (!kvm_valid_efer(vcpu, efer))
1001 return 1;
1002
1003 if (is_paging(vcpu)
1004 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1005 return 1;
1006
15c4a640 1007 efer &= ~EFER_LMA;
f6801dff 1008 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1009
a3d204e2
SY		 1010 kvm_x86_ops->set_efer(vcpu, efer);
1011
aad82703
SY		 1012 /* Update reserved bits */
1013 if ((efer ^ old_efer) & EFER_NX)
1014 kvm_mmu_reset_context(vcpu);
1015
b69e8cae 1016 return 0;
15c4a640
CO		 1017}
1018
f2b4b7dd
JR		 1019void kvm_enable_efer_bits(u64 mask)
1020{
1021 efer_reserved_bits &= ~mask;
1022}
1023EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1024
15c4a640
CO		 1025/*
1026 * Writes msr value into into the appropriate "register".
1027 * Returns 0 on success, non-0 otherwise.
1028 * Assumes vcpu_load() was already called.
1029 */
8fe8ab46 1030int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1031{
854e8bb1
NA		 1032 switch (msr->index) {
1033 case MSR_FS_BASE:
1034 case MSR_GS_BASE:
1035 case MSR_KERNEL_GS_BASE:
1036 case MSR_CSTAR:
1037 case MSR_LSTAR:
1038 if (is_noncanonical_address(msr->data))
1039 return 1;
1040 break;
1041 case MSR_IA32_SYSENTER_EIP:
1042 case MSR_IA32_SYSENTER_ESP:
1043 /*
1044 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1045 * non-canonical address is written on Intel but not on
1046 * AMD (which ignores the top 32-bits, because it does
1047 * not implement 64-bit SYSENTER).
1048 *
1049 * 64-bit code should hence be able to write a non-canonical
1050 * value on AMD. Making the address canonical ensures that
1051 * vmentry does not fail on Intel after writing a non-canonical
1052 * value, and that something deterministic happens if the guest
1053 * invokes 64-bit SYSENTER.
1054 */
1055 msr->data = get_canonical(msr->data);
1056 }
8fe8ab46 1057 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1058}
854e8bb1 1059EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1060
313a3dc7
CO		 1061/*
1062 * Adapt set_msr() to msr_io()'s calling convention
1063 */
609e36d3
PB		 1064static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1065{
1066 struct msr_data msr;
1067 int r;
1068
1069 msr.index = index;
1070 msr.host_initiated = true;
1071 r = kvm_get_msr(vcpu, &msr);
1072 if (r)
1073 return r;
1074
1075 *data = msr.data;
1076 return 0;
1077}
1078
313a3dc7
CO		 1079static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1080{
8fe8ab46
WA		 1081 struct msr_data msr;
1082
1083 msr.data = *data;
1084 msr.index = index;
1085 msr.host_initiated = true;
1086 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1087}
1088
16e8d74d
MT		 1089#ifdef CONFIG_X86_64
1090struct pvclock_gtod_data {
1091 seqcount_t seq;
1092
1093 struct { /* extract of a clocksource struct */
1094 int vclock_mode;
1095 cycle_t cycle_last;
1096 cycle_t mask;
1097 u32 mult;
1098 u32 shift;
1099 } clock;
1100
cbcf2dd3
TG		 1101 u64 boot_ns;
1102 u64 nsec_base;
16e8d74d
MT		 1103};
1104
1105static struct pvclock_gtod_data pvclock_gtod_data;
1106
1107static void update_pvclock_gtod(struct timekeeper *tk)
1108{
1109 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1110 u64 boot_ns;
1111
876e7881 1112 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1113
1114 write_seqcount_begin(&vdata->seq);
1115
1116 /* copy pvclock gtod data */
876e7881
PZ		 1117 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1118 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1119 vdata->clock.mask = tk->tkr_mono.mask;
1120 vdata->clock.mult = tk->tkr_mono.mult;
1121 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1122
cbcf2dd3 1123 vdata->boot_ns = boot_ns;
876e7881 1124 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1125
1126 write_seqcount_end(&vdata->seq);
1127}
1128#endif
1129
bab5bb39
NK		 1130void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1131{
1132 /*
1133 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1134 * vcpu_enter_guest. This function is only called from
1135 * the physical CPU that is running vcpu.
1136 */
1137 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1138}
16e8d74d 1139
18068523
GOC		 1140static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1141{
9ed3c444
AK		 1142 int version;
1143 int r;
50d0a0f9 1144 struct pvclock_wall_clock wc;
923de3cf 1145 struct timespec boot;
18068523
GOC		 1146
1147 if (!wall_clock)
1148 return;
1149
9ed3c444
AK		 1150 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1151 if (r)
1152 return;
1153
1154 if (version & 1)
1155 ++version; /* first time write, random junk */
1156
1157 ++version;
18068523 1158
18068523
GOC		 1159 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1160
50d0a0f9
GH		 1161 /*
1162 * The guest calculates current wall clock time by adding
34c238a1 1163 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1164 * wall clock specified here. guest system time equals host
1165 * system time for us, thus we must fill in host boot time here.
1166 */
923de3cf 1167 getboottime(&boot);
50d0a0f9 1168
4b648665
BR		 1169 if (kvm->arch.kvmclock_offset) {
1170 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1171 boot = timespec_sub(boot, ts);
1172 }
50d0a0f9
GH		 1173 wc.sec = boot.tv_sec;
1174 wc.nsec = boot.tv_nsec;
1175 wc.version = version;
18068523
GOC		 1176
1177 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1178
1179 version++;
1180 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1181}
1182
50d0a0f9
GH		 1183static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1184{
1185 uint32_t quotient, remainder;
1186
1187 /* Don't try to replace with do_div(), this one calculates
1188 * "(dividend << 32) / divisor" */
1189 __asm__ ( "divl %4"
1190 : "=a" (quotient), "=d" (remainder)
1191 : "0" (0), "1" (dividend), "r" (divisor) );
1192 return quotient;
1193}
1194
5f4e3f88
ZA		 1195static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1196 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1197{
5f4e3f88 1198 uint64_t scaled64;
50d0a0f9
GH		 1199 int32_t shift = 0;
1200 uint64_t tps64;
1201 uint32_t tps32;
1202
5f4e3f88
ZA		 1203 tps64 = base_khz * 1000LL;
1204 scaled64 = scaled_khz * 1000LL;
50933623 1205 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1206 tps64 >>= 1;
1207 shift--;
1208 }
1209
1210 tps32 = (uint32_t)tps64;
50933623
JK		 1211 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1212 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1213 scaled64 >>= 1;
1214 else
1215 tps32 <<= 1;
50d0a0f9
GH		 1216 shift++;
1217 }
1218
5f4e3f88
ZA		 1219 *pshift = shift;
1220 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1221
5f4e3f88
ZA		 1222 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1223 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1224}
1225
d828199e 1226#ifdef CONFIG_X86_64
16e8d74d 1227static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1228#endif
16e8d74d 1229
c8076604 1230static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1231static unsigned long max_tsc_khz;
c8076604 1232
cc578287 1233static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1234{
cc578287
ZA		 1235 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1236 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1237}
1238
cc578287 1239static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1240{
cc578287
ZA		 1241 u64 v = (u64)khz * (1000000 + ppm);
1242 do_div(v, 1000000);
1243 return v;
1e993611
JR		 1244}
1245
cc578287 1246static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1247{
cc578287
ZA		 1248 u32 thresh_lo, thresh_hi;
1249 int use_scaling = 0;
217fc9cf 1250
03ba32ca
MT		 1251 /* tsc_khz can be zero if TSC calibration fails */
1252 if (this_tsc_khz == 0)
1253 return;
1254
c285545f
ZA		 1255 /* Compute a scale to convert nanoseconds in TSC cycles */
1256 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1257 &vcpu->arch.virtual_tsc_shift,
1258 &vcpu->arch.virtual_tsc_mult);
1259 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1260
1261 /*
1262 * Compute the variation in TSC rate which is acceptable
1263 * within the range of tolerance and decide if the
1264 * rate being applied is within that bounds of the hardware
1265 * rate. If so, no scaling or compensation need be done.
1266 */
1267 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1268 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1269 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1270 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1271 use_scaling = 1;
1272 }
1273 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1274}
1275
1276static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1277{
e26101b1 1278 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1279 vcpu->arch.virtual_tsc_mult,
1280 vcpu->arch.virtual_tsc_shift);
e26101b1 1281 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1282 return tsc;
1283}
1284
69b0049a 1285static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1286{
1287#ifdef CONFIG_X86_64
1288 bool vcpus_matched;
b48aa97e
MT		 1289 struct kvm_arch *ka = &vcpu->kvm->arch;
1290 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1291
1292 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1293 atomic_read(&vcpu->kvm->online_vcpus));
1294
7f187922
MT		 1295 /*
1296 * Once the masterclock is enabled, always perform request in
1297 * order to update it.
1298 *
1299 * In order to enable masterclock, the host clocksource must be TSC
1300 * and the vcpus need to have matched TSCs. When that happens,
1301 * perform request to enable masterclock.
1302 */
1303 if (ka->use_master_clock ||
1304 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1305 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1306
1307 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1308 atomic_read(&vcpu->kvm->online_vcpus),
1309 ka->use_master_clock, gtod->clock.vclock_mode);
1310#endif
1311}
1312
ba904635
WA		 1313static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1314{
1315 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1316 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1317}
1318
8fe8ab46 1319void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1320{
1321 struct kvm *kvm = vcpu->kvm;
f38e098f 1322 u64 offset, ns, elapsed;
99e3e30a 1323 unsigned long flags;
02626b6a 1324 s64 usdiff;
b48aa97e 1325 bool matched;
0d3da0d2 1326 bool already_matched;
8fe8ab46 1327 u64 data = msr->data;
99e3e30a 1328
038f8c11 1329 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1330 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1331 ns = get_kernel_ns();
f38e098f 1332 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1333
03ba32ca 1334 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1335 int faulted = 0;
1336
03ba32ca
MT		 1337 /* n.b - signed multiplication and division required */
1338 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1339#ifdef CONFIG_X86_64
03ba32ca 1340 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1341#else
03ba32ca 1342 /* do_div() only does unsigned */
8915aa27
MT		 1343 asm("1: idivl %[divisor]\n"
1344 "2: xor %%edx, %%edx\n"
1345 " movl $0, %[faulted]\n"
1346 "3:\n"
1347 ".section .fixup,\"ax\"\n"
1348 "4: movl $1, %[faulted]\n"
1349 " jmp 3b\n"
1350 ".previous\n"
1351
1352 _ASM_EXTABLE(1b, 4b)
1353
1354 : "=A"(usdiff), [faulted] "=r" (faulted)
1355 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1356
5d3cb0f6 1357#endif
03ba32ca
MT		 1358 do_div(elapsed, 1000);
1359 usdiff -= elapsed;
1360 if (usdiff < 0)
1361 usdiff = -usdiff;
8915aa27
MT		 1362
1363 /* idivl overflow => difference is larger than USEC_PER_SEC */
1364 if (faulted)
1365 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1366 } else
1367 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1368
1369 /*
5d3cb0f6
ZA		 1370 * Special case: TSC write with a small delta (1 second) of virtual
1371 * cycle time against real time is interpreted as an attempt to
1372 * synchronize the CPU.
1373 *
1374 * For a reliable TSC, we can match TSC offsets, and for an unstable
1375 * TSC, we add elapsed time in this computation. We could let the
1376 * compensation code attempt to catch up if we fall behind, but
1377 * it's better to try to match offsets from the beginning.
1378 */
02626b6a 1379 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1380 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1381 if (!check_tsc_unstable()) {
e26101b1 1382 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1383 pr_debug("kvm: matched tsc offset for %llu\n", data);
1384 } else {
857e4099 1385 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1386 data += delta;
1387 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1388 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1389 }
b48aa97e 1390 matched = true;
0d3da0d2 1391 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1392 } else {
1393 /*
1394 * We split periods of matched TSC writes into generations.
1395 * For each generation, we track the original measured
1396 * nanosecond time, offset, and write, so if TSCs are in
1397 * sync, we can match exact offset, and if not, we can match
4a969980 1398 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1399 *
1400 * These values are tracked in kvm->arch.cur_xxx variables.
1401 */
1402 kvm->arch.cur_tsc_generation++;
1403 kvm->arch.cur_tsc_nsec = ns;
1404 kvm->arch.cur_tsc_write = data;
1405 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1406 matched = false;
0d3da0d2 1407 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1408 kvm->arch.cur_tsc_generation, data);
f38e098f 1409 }
e26101b1
ZA		 1410
1411 /*
1412 * We also track th most recent recorded KHZ, write and time to
1413 * allow the matching interval to be extended at each write.
1414 */
f38e098f
ZA		 1415 kvm->arch.last_tsc_nsec = ns;
1416 kvm->arch.last_tsc_write = data;
5d3cb0f6 1417 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1418
b183aa58 1419 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1420
1421 /* Keep track of which generation this VCPU has synchronized to */
1422 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1423 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1424 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1425
ba904635
WA		 1426 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1427 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1428 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1429 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1430
1431 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1432 if (!matched) {
b48aa97e 1433 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1434 } else if (!already_matched) {
1435 kvm->arch.nr_vcpus_matched_tsc++;
1436 }
b48aa97e
MT		 1437
1438 kvm_track_tsc_matching(vcpu);
1439 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1440}
e26101b1 1441
99e3e30a
ZA		 1442EXPORT_SYMBOL_GPL(kvm_write_tsc);
1443
d828199e
MT		 1444#ifdef CONFIG_X86_64
1445
1446static cycle_t read_tsc(void)
1447{
03b9730b
AL		 1448 cycle_t ret = (cycle_t)rdtsc_ordered();
1449 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1450
1451 if (likely(ret >= last))
1452 return ret;
1453
1454 /*
1455 * GCC likes to generate cmov here, but this branch is extremely
1456 * predictable (it's just a funciton of time and the likely is
1457 * very likely) and there's a data dependence, so force GCC
1458 * to generate a branch instead. I don't barrier() because
1459 * we don't actually need a barrier, and if this function
1460 * ever gets inlined it will generate worse code.
1461 */
1462 asm volatile ("");
1463 return last;
1464}
1465
1466static inline u64 vgettsc(cycle_t *cycle_now)
1467{
1468 long v;
1469 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1470
1471 *cycle_now = read_tsc();
1472
1473 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1474 return v * gtod->clock.mult;
1475}
1476
cbcf2dd3 1477static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1478{
cbcf2dd3 1479 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1480 unsigned long seq;
d828199e 1481 int mode;
cbcf2dd3 1482 u64 ns;
d828199e 1483
d828199e
MT		 1484 do {
1485 seq = read_seqcount_begin(&gtod->seq);
1486 mode = gtod->clock.vclock_mode;
cbcf2dd3 1487 ns = gtod->nsec_base;
d828199e
MT		 1488 ns += vgettsc(cycle_now);
1489 ns >>= gtod->clock.shift;
cbcf2dd3 1490 ns += gtod->boot_ns;
d828199e 1491 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1492 *t = ns;
d828199e
MT		 1493
1494 return mode;
1495}
1496
1497/* returns true if host is using tsc clocksource */
1498static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1499{
d828199e
MT		 1500 /* checked again under seqlock below */
1501 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1502 return false;
1503
cbcf2dd3 1504 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1505}
1506#endif
1507
1508/*
1509 *
b48aa97e
MT		 1510 * Assuming a stable TSC across physical CPUS, and a stable TSC
1511 * across virtual CPUs, the following condition is possible.
1512 * Each numbered line represents an event visible to both
d828199e
MT		 1513 * CPUs at the next numbered event.
1514 *
1515 * "timespecX" represents host monotonic time. "tscX" represents
1516 * RDTSC value.
1517 *
1518 * VCPU0 on CPU0 | VCPU1 on CPU1
1519 *
1520 * 1. read timespec0,tsc0
1521 * 2. | timespec1 = timespec0 + N
1522 * | tsc1 = tsc0 + M
1523 * 3. transition to guest | transition to guest
1524 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1525 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1526 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1527 *
1528 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1529 *
1530 * - ret0 < ret1
1531 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1532 * ...
1533 * - 0 < N - M => M < N
1534 *
1535 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1536 * always the case (the difference between two distinct xtime instances
1537 * might be smaller then the difference between corresponding TSC reads,
1538 * when updating guest vcpus pvclock areas).
1539 *
1540 * To avoid that problem, do not allow visibility of distinct
1541 * system_timestamp/tsc_timestamp values simultaneously: use a master
1542 * copy of host monotonic time values. Update that master copy
1543 * in lockstep.
1544 *
b48aa97e 1545 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1546 *
1547 */
1548
1549static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1550{
1551#ifdef CONFIG_X86_64
1552 struct kvm_arch *ka = &kvm->arch;
1553 int vclock_mode;
b48aa97e
MT		 1554 bool host_tsc_clocksource, vcpus_matched;
1555
1556 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1557 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1558
1559 /*
1560 * If the host uses TSC clock, then passthrough TSC as stable
1561 * to the guest.
1562 */
b48aa97e 1563 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1564 &ka->master_kernel_ns,
1565 &ka->master_cycle_now);
1566
16a96021 1567 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1568 && !backwards_tsc_observed
1569 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1570
d828199e
MT		 1571 if (ka->use_master_clock)
1572 atomic_set(&kvm_guest_has_master_clock, 1);
1573
1574 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1575 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1576 vcpus_matched);
d828199e
MT		 1577#endif
1578}
1579
2e762ff7
MT		 1580static void kvm_gen_update_masterclock(struct kvm *kvm)
1581{
1582#ifdef CONFIG_X86_64
1583 int i;
1584 struct kvm_vcpu *vcpu;
1585 struct kvm_arch *ka = &kvm->arch;
1586
1587 spin_lock(&ka->pvclock_gtod_sync_lock);
1588 kvm_make_mclock_inprogress_request(kvm);
1589 /* no guest entries from this point */
1590 pvclock_update_vm_gtod_copy(kvm);
1591
1592 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1593 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1594
1595 /* guest entries allowed */
1596 kvm_for_each_vcpu(i, vcpu, kvm)
1597 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1598
1599 spin_unlock(&ka->pvclock_gtod_sync_lock);
1600#endif
1601}
1602
34c238a1 1603static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1604{
d828199e 1605 unsigned long flags, this_tsc_khz;
18068523 1606 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1607 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1608 s64 kernel_ns;
d828199e 1609 u64 tsc_timestamp, host_tsc;
0b79459b 1610 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1611 u8 pvclock_flags;
d828199e
MT		 1612 bool use_master_clock;
1613
1614 kernel_ns = 0;
1615 host_tsc = 0;
18068523 1616
d828199e
MT		 1617 /*
1618 * If the host uses TSC clock, then passthrough TSC as stable
1619 * to the guest.
1620 */
1621 spin_lock(&ka->pvclock_gtod_sync_lock);
1622 use_master_clock = ka->use_master_clock;
1623 if (use_master_clock) {
1624 host_tsc = ka->master_cycle_now;
1625 kernel_ns = ka->master_kernel_ns;
1626 }
1627 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1628
1629 /* Keep irq disabled to prevent changes to the clock */
1630 local_irq_save(flags);
89cbc767 1631 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1632 if (unlikely(this_tsc_khz == 0)) {
1633 local_irq_restore(flags);
1634 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1635 return 1;
1636 }
d828199e 1637 if (!use_master_clock) {
4ea1636b 1638 host_tsc = rdtsc();
d828199e
MT		 1639 kernel_ns = get_kernel_ns();
1640 }
1641
1642 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1643
c285545f
ZA		 1644 /*
1645 * We may have to catch up the TSC to match elapsed wall clock
1646 * time for two reasons, even if kvmclock is used.
1647 * 1) CPU could have been running below the maximum TSC rate
1648 * 2) Broken TSC compensation resets the base at each VCPU
1649 * entry to avoid unknown leaps of TSC even when running
1650 * again on the same CPU. This may cause apparent elapsed
1651 * time to disappear, and the guest to stand still or run
1652 * very slowly.
1653 */
1654 if (vcpu->tsc_catchup) {
1655 u64 tsc = compute_guest_tsc(v, kernel_ns);
1656 if (tsc > tsc_timestamp) {
f1e2b260 1657 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1658 tsc_timestamp = tsc;
1659 }
50d0a0f9
GH		 1660 }
1661
18068523
GOC		 1662 local_irq_restore(flags);
1663
0b79459b 1664 if (!vcpu->pv_time_enabled)
c285545f 1665 return 0;
18068523 1666
e48672fa 1667 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1668 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1669 &vcpu->hv_clock.tsc_shift,
1670 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1671 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1672 }
1673
1674 /* With all the info we got, fill in the values */
1d5f066e 1675 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1676 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1677 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1678
09a0c3f1
OH		 1679 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1680 &guest_hv_clock, sizeof(guest_hv_clock))))
1681 return 0;
1682
5dca0d91
RK		 1683 /* This VCPU is paused, but it's legal for a guest to read another
1684 * VCPU's kvmclock, so we really have to follow the specification where
1685 * it says that version is odd if data is being modified, and even after
1686 * it is consistent.
1687 *
1688 * Version field updates must be kept separate. This is because
1689 * kvm_write_guest_cached might use a "rep movs" instruction, and
1690 * writes within a string instruction are weakly ordered. So there
1691 * are three writes overall.
1692 *
1693 * As a small optimization, only write the version field in the first
1694 * and third write. The vcpu->pv_time cache is still valid, because the
1695 * version field is the first in the struct.
18068523 1696 */
5dca0d91
RK		 1697 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1698
1699 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1700 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1701 &vcpu->hv_clock,
1702 sizeof(vcpu->hv_clock.version));
1703
1704 smp_wmb();
78c0337a
MT		 1705
1706 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1707 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1708
1709 if (vcpu->pvclock_set_guest_stopped_request) {
1710 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1711 vcpu->pvclock_set_guest_stopped_request = false;
1712 }
1713
d828199e
MT		 1714 /* If the host uses TSC clocksource, then it is stable */
1715 if (use_master_clock)
1716 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1717
78c0337a
MT		 1718 vcpu->hv_clock.flags = pvclock_flags;
1719
ce1a5e60
DM		 1720 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1721
0b79459b
AH		 1722 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1723 &vcpu->hv_clock,
1724 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1725
1726 smp_wmb();
1727
1728 vcpu->hv_clock.version++;
1729 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1730 &vcpu->hv_clock,
1731 sizeof(vcpu->hv_clock.version));
8cfdc000 1732 return 0;
c8076604
GH		 1733}
1734
0061d53d
MT		 1735/*
1736 * kvmclock updates which are isolated to a given vcpu, such as
1737 * vcpu->cpu migration, should not allow system_timestamp from
1738 * the rest of the vcpus to remain static. Otherwise ntp frequency
1739 * correction applies to one vcpu's system_timestamp but not
1740 * the others.
1741 *
1742 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1743 * We need to rate-limit these requests though, as they can
1744 * considerably slow guests that have a large number of vcpus.
1745 * The time for a remote vcpu to update its kvmclock is bound
1746 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1747 */
1748
7e44e449
AJ		 1749#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1750
1751static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1752{
1753 int i;
7e44e449
AJ		 1754 struct delayed_work *dwork = to_delayed_work(work);
1755 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1756 kvmclock_update_work);
1757 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1758 struct kvm_vcpu *vcpu;
1759
1760 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1761 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1762 kvm_vcpu_kick(vcpu);
1763 }
1764}
1765
7e44e449
AJ		 1766static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1767{
1768 struct kvm *kvm = v->kvm;
1769
105b21bb 1770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1771 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1772 KVMCLOCK_UPDATE_DELAY);
1773}
1774
332967a3
AJ		 1775#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1776
1777static void kvmclock_sync_fn(struct work_struct *work)
1778{
1779 struct delayed_work *dwork = to_delayed_work(work);
1780 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1781 kvmclock_sync_work);
1782 struct kvm *kvm = container_of(ka, struct kvm, arch);
1783
630994b3
MT		 1784 if (!kvmclock_periodic_sync)
1785 return;
1786
332967a3
AJ		 1787 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1788 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1789 KVMCLOCK_SYNC_PERIOD);
1790}
1791
890ca9ae 1792static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1793{
890ca9ae
HY		 1794 u64 mcg_cap = vcpu->arch.mcg_cap;
1795 unsigned bank_num = mcg_cap & 0xff;
1796
15c4a640 1797 switch (msr) {
15c4a640 1798 case MSR_IA32_MCG_STATUS:
890ca9ae 1799 vcpu->arch.mcg_status = data;
15c4a640 1800 break;
c7ac679c 1801 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1802 if (!(mcg_cap & MCG_CTL_P))
1803 return 1;
1804 if (data != 0 && data != ~(u64)0)
1805 return -1;
1806 vcpu->arch.mcg_ctl = data;
1807 break;
1808 default:
1809 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1810 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1811 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1812 /* only 0 or all 1s can be written to IA32_MCi_CTL
1813 * some Linux kernels though clear bit 10 in bank 4 to
1814 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1815 * this to avoid an uncatched #GP in the guest
1816 */
890ca9ae 1817 if ((offset & 0x3) == 0 &&
114be429 1818 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1819 return -1;
1820 vcpu->arch.mce_banks[offset] = data;
1821 break;
1822 }
1823 return 1;
1824 }
1825 return 0;
1826}
1827
ffde22ac
ES		 1828static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1829{
1830 struct kvm *kvm = vcpu->kvm;
1831 int lm = is_long_mode(vcpu);
1832 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1833 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1834 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1835 : kvm->arch.xen_hvm_config.blob_size_32;
1836 u32 page_num = data & ~PAGE_MASK;
1837 u64 page_addr = data & PAGE_MASK;
1838 u8 *page;
1839 int r;
1840
1841 r = -E2BIG;
1842 if (page_num >= blob_size)
1843 goto out;
1844 r = -ENOMEM;
ff5c2c03
SL		 1845 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1846 if (IS_ERR(page)) {
1847 r = PTR_ERR(page);
ffde22ac 1848 goto out;
ff5c2c03 1849 }
54bf36aa 1850 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1851 goto out_free;
1852 r = 0;
1853out_free:
1854 kfree(page);
1855out:
1856 return r;
1857}
1858
344d9588
GN		 1859static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1860{
1861 gpa_t gpa = data & ~0x3f;
1862
4a969980 1863 /* Bits 2:5 are reserved, Should be zero */
6adba527 1864 if (data & 0x3c)
344d9588
GN		 1865 return 1;
1866
1867 vcpu->arch.apf.msr_val = data;
1868
1869 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1870 kvm_clear_async_pf_completion_queue(vcpu);
1871 kvm_async_pf_hash_reset(vcpu);
1872 return 0;
1873 }
1874
8f964525
AH		 1875 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1876 sizeof(u32)))
344d9588
GN		 1877 return 1;
1878
6adba527 1879 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1880 kvm_async_pf_wakeup_all(vcpu);
1881 return 0;
1882}
1883
12f9a48f
GC		 1884static void kvmclock_reset(struct kvm_vcpu *vcpu)
1885{
0b79459b 1886 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1887}
1888
c9aaa895
GC		 1889static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1890{
1891 u64 delta;
1892
1893 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1894 return;
1895
1896 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1897 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1898 vcpu->arch.st.accum_steal = delta;
1899}
1900
1901static void record_steal_time(struct kvm_vcpu *vcpu)
1902{
1903 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1904 return;
1905
1906 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1907 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1908 return;
1909
1910 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1911 vcpu->arch.st.steal.version += 2;
1912 vcpu->arch.st.accum_steal = 0;
1913
1914 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1915 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1916}
1917
8fe8ab46 1918int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1919{
5753785f 1920 bool pr = false;
8fe8ab46
WA		 1921 u32 msr = msr_info->index;
1922 u64 data = msr_info->data;
5753785f 1923
15c4a640 1924 switch (msr) {
2e32b719
BP		 1925 case MSR_AMD64_NB_CFG:
1926 case MSR_IA32_UCODE_REV:
1927 case MSR_IA32_UCODE_WRITE:
1928 case MSR_VM_HSAVE_PA:
1929 case MSR_AMD64_PATCH_LOADER:
1930 case MSR_AMD64_BU_CFG2:
1931 break;
1932
15c4a640 1933 case MSR_EFER:
b69e8cae 1934 return set_efer(vcpu, data);
8f1589d9
AP		 1935 case MSR_K7_HWCR:
1936 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1937 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1938 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1939 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1940 if (data != 0) {
a737f256
CD		 1941 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1942 data);
8f1589d9
AP		 1943 return 1;
1944 }
15c4a640 1945 break;
f7c6d140
AP		 1946 case MSR_FAM10H_MMIO_CONF_BASE:
1947 if (data != 0) {
a737f256
CD		 1948 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1949 "0x%llx\n", data);
f7c6d140
AP		 1950 return 1;
1951 }
15c4a640 1952 break;
b5e2fec0
AG		 1953 case MSR_IA32_DEBUGCTLMSR:
1954 if (!data) {
1955 /* We support the non-activated case already */
1956 break;
1957 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1958 /* Values other than LBR and BTF are vendor-specific,
1959 thus reserved and should throw a #GP */
1960 return 1;
1961 }
a737f256
CD		 1962 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1963 __func__, data);
b5e2fec0 1964 break;
9ba075a6 1965 case 0x200 ... 0x2ff:
ff53604b 1966 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1967 case MSR_IA32_APICBASE:
58cb628d 1968 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1969 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1970 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1971 case MSR_IA32_TSCDEADLINE:
1972 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1973 break;
ba904635
WA		 1974 case MSR_IA32_TSC_ADJUST:
1975 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1976 if (!msr_info->host_initiated) {
d913b904 1977 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 1978 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 1979 }
1980 vcpu->arch.ia32_tsc_adjust_msr = data;
1981 }
1982 break;
15c4a640 1983 case MSR_IA32_MISC_ENABLE:
ad312c7c 1984 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1985 break;
64d60670
PB		 1986 case MSR_IA32_SMBASE:
1987 if (!msr_info->host_initiated)
1988 return 1;
1989 vcpu->arch.smbase = data;
1990 break;
11c6bffa 1991 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1992 case MSR_KVM_WALL_CLOCK:
1993 vcpu->kvm->arch.wall_clock = data;
1994 kvm_write_wall_clock(vcpu->kvm, data);
1995 break;
11c6bffa 1996 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1997 case MSR_KVM_SYSTEM_TIME: {
0b79459b 1998 u64 gpa_offset;
54750f2c
MT		 1999 struct kvm_arch *ka = &vcpu->kvm->arch;
2000
12f9a48f 2001 kvmclock_reset(vcpu);
18068523 2002
54750f2c
MT		 2003 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2004 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2005
2006 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2007 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2008 &vcpu->requests);
2009
2010 ka->boot_vcpu_runs_old_kvmclock = tmp;
2011 }
2012
18068523 2013 vcpu->arch.time = data;
0061d53d 2014 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2015
2016 /* we verify if the enable bit is set... */
2017 if (!(data & 1))
2018 break;
2019
0b79459b 2020 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2021
0b79459b 2022 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2023 &vcpu->arch.pv_time, data & ~1ULL,
2024 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2025 vcpu->arch.pv_time_enabled = false;
2026 else
2027 vcpu->arch.pv_time_enabled = true;
32cad84f 2028
18068523
GOC		 2029 break;
2030 }
344d9588
GN		 2031 case MSR_KVM_ASYNC_PF_EN:
2032 if (kvm_pv_enable_async_pf(vcpu, data))
2033 return 1;
2034 break;
c9aaa895
GC		 2035 case MSR_KVM_STEAL_TIME:
2036
2037 if (unlikely(!sched_info_on()))
2038 return 1;
2039
2040 if (data & KVM_STEAL_RESERVED_MASK)
2041 return 1;
2042
2043 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2044 data & KVM_STEAL_VALID_BITS,
2045 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2046 return 1;
2047
2048 vcpu->arch.st.msr_val = data;
2049
2050 if (!(data & KVM_MSR_ENABLED))
2051 break;
2052
2053 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2054
2055 preempt_disable();
2056 accumulate_steal_time(vcpu);
2057 preempt_enable();
2058
2059 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2060
2061 break;
ae7a2a3f
MT		 2062 case MSR_KVM_PV_EOI_EN:
2063 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2064 return 1;
2065 break;
c9aaa895 2066
890ca9ae
HY		 2067 case MSR_IA32_MCG_CTL:
2068 case MSR_IA32_MCG_STATUS:
81760dcc 2069 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2070 return set_msr_mce(vcpu, msr, data);
71db6023 2071
6912ac32
WH		 2072 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2073 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2074 pr = true; /* fall through */
2075 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2076 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2077 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2078 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2079
2080 if (pr || data != 0)
a737f256
CD		 2081 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2082 "0x%x data 0x%llx\n", msr, data);
5753785f 2083 break;
84e0cefa
JS		 2084 case MSR_K7_CLK_CTL:
2085 /*
2086 * Ignore all writes to this no longer documented MSR.
2087 * Writes are only relevant for old K7 processors,
2088 * all pre-dating SVM, but a recommended workaround from
4a969980 2089 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2090 * affected processor models on the command line, hence
2091 * the need to ignore the workaround.
2092 */
2093 break;
55cd8e5a 2094 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2095 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2096 case HV_X64_MSR_CRASH_CTL:
2097 return kvm_hv_set_msr_common(vcpu, msr, data,
2098 msr_info->host_initiated);
91c9c3ed 2099 case MSR_IA32_BBL_CR_CTL3:
2100 /* Drop writes to this legacy MSR -- see rdmsr
2101 * counterpart for further detail.
2102 */
a737f256 2103 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2104 break;
2b036c6b
BO		 2105 case MSR_AMD64_OSVW_ID_LENGTH:
2106 if (!guest_cpuid_has_osvw(vcpu))
2107 return 1;
2108 vcpu->arch.osvw.length = data;
2109 break;
2110 case MSR_AMD64_OSVW_STATUS:
2111 if (!guest_cpuid_has_osvw(vcpu))
2112 return 1;
2113 vcpu->arch.osvw.status = data;
2114 break;
15c4a640 2115 default:
ffde22ac
ES		 2116 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2117 return xen_hvm_config(vcpu, data);
c6702c9d 2118 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2119 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2120 if (!ignore_msrs) {
a737f256
CD		 2121 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2122 msr, data);
ed85c068
AP		 2123 return 1;
2124 } else {
a737f256
CD		 2125 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2126 msr, data);
ed85c068
AP		 2127 break;
2128 }
15c4a640
CO		 2129 }
2130 return 0;
2131}
2132EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2133
2134
2135/*
2136 * Reads an msr value (of 'msr_index') into 'pdata'.
2137 * Returns 0 on success, non-0 otherwise.
2138 * Assumes vcpu_load() was already called.
2139 */
609e36d3 2140int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2141{
609e36d3 2142 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2143}
ff651cb6 2144EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2145
890ca9ae 2146static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2147{
2148 u64 data;
890ca9ae
HY		 2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2151
2152 switch (msr) {
15c4a640
CO		 2153 case MSR_IA32_P5_MC_ADDR:
2154 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2155 data = 0;
2156 break;
15c4a640 2157 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2158 data = vcpu->arch.mcg_cap;
2159 break;
c7ac679c 2160 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2161 if (!(mcg_cap & MCG_CTL_P))
2162 return 1;
2163 data = vcpu->arch.mcg_ctl;
2164 break;
2165 case MSR_IA32_MCG_STATUS:
2166 data = vcpu->arch.mcg_status;
2167 break;
2168 default:
2169 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2170 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2171 u32 offset = msr - MSR_IA32_MC0_CTL;
2172 data = vcpu->arch.mce_banks[offset];
2173 break;
2174 }
2175 return 1;
2176 }
2177 *pdata = data;
2178 return 0;
2179}
2180
609e36d3 2181int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2182{
609e36d3 2183 switch (msr_info->index) {
890ca9ae 2184 case MSR_IA32_PLATFORM_ID:
15c4a640 2185 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2186 case MSR_IA32_DEBUGCTLMSR:
2187 case MSR_IA32_LASTBRANCHFROMIP:
2188 case MSR_IA32_LASTBRANCHTOIP:
2189 case MSR_IA32_LASTINTFROMIP:
2190 case MSR_IA32_LASTINTTOIP:
60af2ecd 2191 case MSR_K8_SYSCFG:
3afb1121
PB		 2192 case MSR_K8_TSEG_ADDR:
2193 case MSR_K8_TSEG_MASK:
60af2ecd 2194 case MSR_K7_HWCR:
61a6bd67 2195 case MSR_VM_HSAVE_PA:
1fdbd48c 2196 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2197 case MSR_AMD64_NB_CFG:
f7c6d140 2198 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2199 case MSR_AMD64_BU_CFG2:
609e36d3 2200 msr_info->data = 0;
15c4a640 2201 break;
6912ac32
WH		 2202 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2203 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2204 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2205 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2206 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2207 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2208 msr_info->data = 0;
5753785f 2209 break;
742bc670 2210 case MSR_IA32_UCODE_REV:
609e36d3 2211 msr_info->data = 0x100000000ULL;
742bc670 2212 break;
9ba075a6 2213 case MSR_MTRRcap:
9ba075a6 2214 case 0x200 ... 0x2ff:
ff53604b 2215 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2216 case 0xcd: /* fsb frequency */
609e36d3 2217 msr_info->data = 3;
15c4a640 2218 break;
7b914098
JS		 2219 /*
2220 * MSR_EBC_FREQUENCY_ID
2221 * Conservative value valid for even the basic CPU models.
2222 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2223 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2224 * and 266MHz for model 3, or 4. Set Core Clock
2225 * Frequency to System Bus Frequency Ratio to 1 (bits
2226 * 31:24) even though these are only valid for CPU
2227 * models > 2, however guests may end up dividing or
2228 * multiplying by zero otherwise.
2229 */
2230 case MSR_EBC_FREQUENCY_ID:
609e36d3 2231 msr_info->data = 1 << 24;
7b914098 2232 break;
15c4a640 2233 case MSR_IA32_APICBASE:
609e36d3 2234 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2235 break;
0105d1a5 2236 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2237 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2238 break;
a3e06bbe 2239 case MSR_IA32_TSCDEADLINE:
609e36d3 2240 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2241 break;
ba904635 2242 case MSR_IA32_TSC_ADJUST:
609e36d3 2243 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2244 break;
15c4a640 2245 case MSR_IA32_MISC_ENABLE:
609e36d3 2246 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2247 break;
64d60670
PB		 2248 case MSR_IA32_SMBASE:
2249 if (!msr_info->host_initiated)
2250 return 1;
2251 msr_info->data = vcpu->arch.smbase;
15c4a640 2252 break;
847f0ad8
AG		 2253 case MSR_IA32_PERF_STATUS:
2254 /* TSC increment by tick */
609e36d3 2255 msr_info->data = 1000ULL;
847f0ad8 2256 /* CPU multiplier */
b0996ae4 2257 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2258 break;
15c4a640 2259 case MSR_EFER:
609e36d3 2260 msr_info->data = vcpu->arch.efer;
15c4a640 2261 break;
18068523 2262 case MSR_KVM_WALL_CLOCK:
11c6bffa 2263 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2264 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2265 break;
2266 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2267 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2268 msr_info->data = vcpu->arch.time;
18068523 2269 break;
344d9588 2270 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2271 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2272 break;
c9aaa895 2273 case MSR_KVM_STEAL_TIME:
609e36d3 2274 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2275 break;
1d92128f 2276 case MSR_KVM_PV_EOI_EN:
609e36d3 2277 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2278 break;
890ca9ae
HY		 2279 case MSR_IA32_P5_MC_ADDR:
2280 case MSR_IA32_P5_MC_TYPE:
2281 case MSR_IA32_MCG_CAP:
2282 case MSR_IA32_MCG_CTL:
2283 case MSR_IA32_MCG_STATUS:
81760dcc 2284 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2285 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2286 case MSR_K7_CLK_CTL:
2287 /*
2288 * Provide expected ramp-up count for K7. All other
2289 * are set to zero, indicating minimum divisors for
2290 * every field.
2291 *
2292 * This prevents guest kernels on AMD host with CPU
2293 * type 6, model 8 and higher from exploding due to
2294 * the rdmsr failing.
2295 */
609e36d3 2296 msr_info->data = 0x20000000;
84e0cefa 2297 break;
55cd8e5a 2298 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2299 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2300 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2301 return kvm_hv_get_msr_common(vcpu,
2302 msr_info->index, &msr_info->data);
55cd8e5a 2303 break;
91c9c3ed 2304 case MSR_IA32_BBL_CR_CTL3:
2305 /* This legacy MSR exists but isn't fully documented in current
2306 * silicon. It is however accessed by winxp in very narrow
2307 * scenarios where it sets bit #19, itself documented as
2308 * a "reserved" bit. Best effort attempt to source coherent
2309 * read data here should the balance of the register be
2310 * interpreted by the guest:
2311 *
2312 * L2 cache control register 3: 64GB range, 256KB size,
2313 * enabled, latency 0x1, configured
2314 */
609e36d3 2315 msr_info->data = 0xbe702111;
91c9c3ed 2316 break;
2b036c6b
BO		 2317 case MSR_AMD64_OSVW_ID_LENGTH:
2318 if (!guest_cpuid_has_osvw(vcpu))
2319 return 1;
609e36d3 2320 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2321 break;
2322 case MSR_AMD64_OSVW_STATUS:
2323 if (!guest_cpuid_has_osvw(vcpu))
2324 return 1;
609e36d3 2325 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2326 break;
15c4a640 2327 default:
c6702c9d 2328 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2329 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2330 if (!ignore_msrs) {
609e36d3 2331 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2332 return 1;
2333 } else {
609e36d3
PB		 2334 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2335 msr_info->data = 0;
ed85c068
AP		 2336 }
2337 break;
15c4a640 2338 }
15c4a640
CO		 2339 return 0;
2340}
2341EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2342
313a3dc7
CO		 2343/*
2344 * Read or write a bunch of msrs. All parameters are kernel addresses.
2345 *
2346 * @return number of msrs set successfully.
2347 */
2348static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2349 struct kvm_msr_entry *entries,
2350 int (*do_msr)(struct kvm_vcpu *vcpu,
2351 unsigned index, u64 *data))
2352{
f656ce01 2353 int i, idx;
313a3dc7 2354
f656ce01 2355 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2356 for (i = 0; i < msrs->nmsrs; ++i)
2357 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2358 break;
f656ce01 2359 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2360
313a3dc7
CO		 2361 return i;
2362}
2363
2364/*
2365 * Read or write a bunch of msrs. Parameters are user addresses.
2366 *
2367 * @return number of msrs set successfully.
2368 */
2369static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2370 int (*do_msr)(struct kvm_vcpu *vcpu,
2371 unsigned index, u64 *data),
2372 int writeback)
2373{
2374 struct kvm_msrs msrs;
2375 struct kvm_msr_entry *entries;
2376 int r, n;
2377 unsigned size;
2378
2379 r = -EFAULT;
2380 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2381 goto out;
2382
2383 r = -E2BIG;
2384 if (msrs.nmsrs >= MAX_IO_MSRS)
2385 goto out;
2386
313a3dc7 2387 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2388 entries = memdup_user(user_msrs->entries, size);
2389 if (IS_ERR(entries)) {
2390 r = PTR_ERR(entries);
313a3dc7 2391 goto out;
ff5c2c03 2392 }
313a3dc7
CO		 2393
2394 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2395 if (r < 0)
2396 goto out_free;
2397
2398 r = -EFAULT;
2399 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2400 goto out_free;
2401
2402 r = n;
2403
2404out_free:
7a73c028 2405 kfree(entries);
313a3dc7
CO		 2406out:
2407 return r;
2408}
2409
784aa3d7 2410int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2411{
2412 int r;
2413
2414 switch (ext) {
2415 case KVM_CAP_IRQCHIP:
2416 case KVM_CAP_HLT:
2417 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2418 case KVM_CAP_SET_TSS_ADDR:
07716717 2419 case KVM_CAP_EXT_CPUID:
9c15bb1d 2420 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2421 case KVM_CAP_CLOCKSOURCE:
7837699f 2422 case KVM_CAP_PIT:
a28e4f5a 2423 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2424 case KVM_CAP_MP_STATE:
ed848624 2425 case KVM_CAP_SYNC_MMU:
a355c85c 2426 case KVM_CAP_USER_NMI:
52d939a0 2427 case KVM_CAP_REINJECT_CONTROL:
4925663a 2428 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2429 case KVM_CAP_IOEVENTFD:
f848a5a8 2430 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2431 case KVM_CAP_PIT2:
e9f42757 2432 case KVM_CAP_PIT_STATE2:
b927a3ce 2433 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2434 case KVM_CAP_XEN_HVM:
afbcf7ab 2435 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2436 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2437 case KVM_CAP_HYPERV:
10388a07 2438 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2439 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2440 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2441 case KVM_CAP_DEBUGREGS:
d2be1651 2442 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2443 case KVM_CAP_XSAVE:
344d9588 2444 case KVM_CAP_ASYNC_PF:
92a1f12d 2445 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2446 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2447 case KVM_CAP_READONLY_MEM:
5f66b620 2448 case KVM_CAP_HYPERV_TIME:
100943c5 2449 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2450 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2451 case KVM_CAP_ENABLE_CAP_VM:
2452 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2453 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2454 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2455#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2456 case KVM_CAP_ASSIGN_DEV_IRQ:
2457 case KVM_CAP_PCI_2_3:
2458#endif
018d00d2
ZX		 2459 r = 1;
2460 break;
6d396b55
PB		 2461 case KVM_CAP_X86_SMM:
2462 /* SMBASE is usually relocated above 1M on modern chipsets,
2463 * and SMM handlers might indeed rely on 4G segment limits,
2464 * so do not report SMM to be available if real mode is
2465 * emulated via vm86 mode. Still, do not go to great lengths
2466 * to avoid userspace's usage of the feature, because it is a
2467 * fringe case that is not enabled except via specific settings
2468 * of the module parameters.
2469 */
2470 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2471 break;
542472b5
LV		 2472 case KVM_CAP_COALESCED_MMIO:
2473 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2474 break;
774ead3a
AK		 2475 case KVM_CAP_VAPIC:
2476 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2477 break;
f725230a 2478 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2479 r = KVM_SOFT_MAX_VCPUS;
2480 break;
2481 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2482 r = KVM_MAX_VCPUS;
2483 break;
a988b910 2484 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2485 r = KVM_USER_MEM_SLOTS;
a988b910 2486 break;
a68a6a72
MT		 2487 case KVM_CAP_PV_MMU: /* obsolete */
2488 r = 0;
2f333bcb 2489 break;
4cee4b72 2490#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2491 case KVM_CAP_IOMMU:
a1b60c1c 2492 r = iommu_present(&pci_bus_type);
62c476c7 2493 break;
4cee4b72 2494#endif
890ca9ae
HY		 2495 case KVM_CAP_MCE:
2496 r = KVM_MAX_MCE_BANKS;
2497 break;
2d5b5a66
SY		 2498 case KVM_CAP_XCRS:
2499 r = cpu_has_xsave;
2500 break;
92a1f12d
JR		 2501 case KVM_CAP_TSC_CONTROL:
2502 r = kvm_has_tsc_control;
2503 break;
018d00d2
ZX		 2504 default:
2505 r = 0;
2506 break;
2507 }
2508 return r;
2509
2510}
2511
043405e1
CO		 2512long kvm_arch_dev_ioctl(struct file *filp,
2513 unsigned int ioctl, unsigned long arg)
2514{
2515 void __user *argp = (void __user *)arg;
2516 long r;
2517
2518 switch (ioctl) {
2519 case KVM_GET_MSR_INDEX_LIST: {
2520 struct kvm_msr_list __user *user_msr_list = argp;
2521 struct kvm_msr_list msr_list;
2522 unsigned n;
2523
2524 r = -EFAULT;
2525 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2526 goto out;
2527 n = msr_list.nmsrs;
62ef68bb 2528 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2529 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2530 goto out;
2531 r = -E2BIG;
e125e7b6 2532 if (n < msr_list.nmsrs)
043405e1
CO		 2533 goto out;
2534 r = -EFAULT;
2535 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2536 num_msrs_to_save * sizeof(u32)))
2537 goto out;
e125e7b6 2538 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2539 &emulated_msrs,
62ef68bb 2540 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2541 goto out;
2542 r = 0;
2543 break;
2544 }
9c15bb1d
BP		 2545 case KVM_GET_SUPPORTED_CPUID:
2546 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2547 struct kvm_cpuid2 __user *cpuid_arg = argp;
2548 struct kvm_cpuid2 cpuid;
2549
2550 r = -EFAULT;
2551 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2552 goto out;
9c15bb1d
BP		 2553
2554 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2555 ioctl);
674eea0f
AK		 2556 if (r)
2557 goto out;
2558
2559 r = -EFAULT;
2560 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2561 goto out;
2562 r = 0;
2563 break;
2564 }
890ca9ae
HY		 2565 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2566 u64 mce_cap;
2567
2568 mce_cap = KVM_MCE_CAP_SUPPORTED;
2569 r = -EFAULT;
2570 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2571 goto out;
2572 r = 0;
2573 break;
2574 }
043405e1
CO		 2575 default:
2576 r = -EINVAL;
2577 }
2578out:
2579 return r;
2580}
2581
f5f48ee1
SY		 2582static void wbinvd_ipi(void *garbage)
2583{
2584 wbinvd();
2585}
2586
2587static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2588{
e0f0bbc5 2589 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2590}
2591
313a3dc7
CO		 2592void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2593{
f5f48ee1
SY		 2594 /* Address WBINVD may be executed by guest */
2595 if (need_emulate_wbinvd(vcpu)) {
2596 if (kvm_x86_ops->has_wbinvd_exit())
2597 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2598 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2599 smp_call_function_single(vcpu->cpu,
2600 wbinvd_ipi, NULL, 1);
2601 }
2602
313a3dc7 2603 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2604
0dd6a6ed
ZA		 2605 /* Apply any externally detected TSC adjustments (due to suspend) */
2606 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2607 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2608 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2609 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2610 }
8f6055cb 2611
48434c20 2612 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2613 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2614 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2615 if (tsc_delta < 0)
2616 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2617 if (check_tsc_unstable()) {
b183aa58
ZA		 2618 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2619 vcpu->arch.last_guest_tsc);
2620 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2621 vcpu->arch.tsc_catchup = 1;
c285545f 2622 }
d98d07ca
MT		 2623 /*
2624 * On a host with synchronized TSC, there is no need to update
2625 * kvmclock on vcpu->cpu migration
2626 */
2627 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2628 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2629 if (vcpu->cpu != cpu)
2630 kvm_migrate_timers(vcpu);
e48672fa 2631 vcpu->cpu = cpu;
6b7d7e76 2632 }
c9aaa895
GC		 2633
2634 accumulate_steal_time(vcpu);
2635 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2636}
2637
2638void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2639{
02daab21 2640 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2641 kvm_put_guest_fpu(vcpu);
4ea1636b 2642 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2643}
2644
313a3dc7
CO		 2645static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2646 struct kvm_lapic_state *s)
2647{
5a71785d 2648 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2649 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2650
2651 return 0;
2652}
2653
2654static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2655 struct kvm_lapic_state *s)
2656{
64eb0620 2657 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2658 update_cr8_intercept(vcpu);
313a3dc7
CO		 2659
2660 return 0;
2661}
2662
f77bc6a4
ZX		 2663static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2664 struct kvm_interrupt *irq)
2665{
02cdb50f 2666 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2667 return -EINVAL;
1c1a9ce9
SR		 2668
2669 if (!irqchip_in_kernel(vcpu->kvm)) {
2670 kvm_queue_interrupt(vcpu, irq->irq, false);
2671 kvm_make_request(KVM_REQ_EVENT, vcpu);
2672 return 0;
2673 }
2674
2675 /*
2676 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2677 * fail for in-kernel 8259.
2678 */
2679 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2680 return -ENXIO;
f77bc6a4 2681
1c1a9ce9
SR		 2682 if (vcpu->arch.pending_external_vector != -1)
2683 return -EEXIST;
f77bc6a4 2684
1c1a9ce9 2685 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2686 return 0;
2687}
2688
c4abb7c9
JK		 2689static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2690{
c4abb7c9 2691 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2692
2693 return 0;
2694}
2695
f077825a
PB		 2696static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2697{
64d60670
PB		 2698 kvm_make_request(KVM_REQ_SMI, vcpu);
2699
f077825a
PB		 2700 return 0;
2701}
2702
b209749f
AK		 2703static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2704 struct kvm_tpr_access_ctl *tac)
2705{
2706 if (tac->flags)
2707 return -EINVAL;
2708 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2709 return 0;
2710}
2711
890ca9ae
HY		 2712static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2713 u64 mcg_cap)
2714{
2715 int r;
2716 unsigned bank_num = mcg_cap & 0xff, bank;
2717
2718 r = -EINVAL;
a9e38c3e 2719 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2720 goto out;
2721 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2722 goto out;
2723 r = 0;
2724 vcpu->arch.mcg_cap = mcg_cap;
2725 /* Init IA32_MCG_CTL to all 1s */
2726 if (mcg_cap & MCG_CTL_P)
2727 vcpu->arch.mcg_ctl = ~(u64)0;
2728 /* Init IA32_MCi_CTL to all 1s */
2729 for (bank = 0; bank < bank_num; bank++)
2730 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2731out:
2732 return r;
2733}
2734
2735static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2736 struct kvm_x86_mce *mce)
2737{
2738 u64 mcg_cap = vcpu->arch.mcg_cap;
2739 unsigned bank_num = mcg_cap & 0xff;
2740 u64 *banks = vcpu->arch.mce_banks;
2741
2742 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2743 return -EINVAL;
2744 /*
2745 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2746 * reporting is disabled
2747 */
2748 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2749 vcpu->arch.mcg_ctl != ~(u64)0)
2750 return 0;
2751 banks += 4 * mce->bank;
2752 /*
2753 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2754 * reporting is disabled for the bank
2755 */
2756 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2757 return 0;
2758 if (mce->status & MCI_STATUS_UC) {
2759 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2760 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2761 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2762 return 0;
2763 }
2764 if (banks[1] & MCI_STATUS_VAL)
2765 mce->status |= MCI_STATUS_OVER;
2766 banks[2] = mce->addr;
2767 banks[3] = mce->misc;
2768 vcpu->arch.mcg_status = mce->mcg_status;
2769 banks[1] = mce->status;
2770 kvm_queue_exception(vcpu, MC_VECTOR);
2771 } else if (!(banks[1] & MCI_STATUS_VAL)
2772 || !(banks[1] & MCI_STATUS_UC)) {
2773 if (banks[1] & MCI_STATUS_VAL)
2774 mce->status |= MCI_STATUS_OVER;
2775 banks[2] = mce->addr;
2776 banks[3] = mce->misc;
2777 banks[1] = mce->status;
2778 } else
2779 banks[1] |= MCI_STATUS_OVER;
2780 return 0;
2781}
2782
3cfc3092
JK		 2783static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2784 struct kvm_vcpu_events *events)
2785{
7460fb4a 2786 process_nmi(vcpu);
03b82a30
JK		 2787 events->exception.injected =
2788 vcpu->arch.exception.pending &&
2789 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2790 events->exception.nr = vcpu->arch.exception.nr;
2791 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2792 events->exception.pad = 0;
3cfc3092
JK		 2793 events->exception.error_code = vcpu->arch.exception.error_code;
2794
03b82a30
JK		 2795 events->interrupt.injected =
2796 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2797 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2798 events->interrupt.soft = 0;
37ccdcbe 2799 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2800
2801 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2802 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2803 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2804 events->nmi.pad = 0;
3cfc3092 2805
66450a21 2806 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2807
f077825a
PB		 2808 events->smi.smm = is_smm(vcpu);
2809 events->smi.pending = vcpu->arch.smi_pending;
2810 events->smi.smm_inside_nmi =
2811 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2812 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2813
dab4b911 2814 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2815 | KVM_VCPUEVENT_VALID_SHADOW
2816 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2817 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2818}
2819
2820static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2821 struct kvm_vcpu_events *events)
2822{
dab4b911 2823 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2824 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2825 | KVM_VCPUEVENT_VALID_SHADOW
2826 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2827 return -EINVAL;
2828
7460fb4a 2829 process_nmi(vcpu);
3cfc3092
JK		 2830 vcpu->arch.exception.pending = events->exception.injected;
2831 vcpu->arch.exception.nr = events->exception.nr;
2832 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2833 vcpu->arch.exception.error_code = events->exception.error_code;
2834
2835 vcpu->arch.interrupt.pending = events->interrupt.injected;
2836 vcpu->arch.interrupt.nr = events->interrupt.nr;
2837 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2838 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2839 kvm_x86_ops->set_interrupt_shadow(vcpu,
2840 events->interrupt.shadow);
3cfc3092
JK		 2841
2842 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2843 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2844 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2845 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2846
66450a21
JK		 2847 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2848 kvm_vcpu_has_lapic(vcpu))
2849 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2850
f077825a
PB		 2851 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2852 if (events->smi.smm)
2853 vcpu->arch.hflags |= HF_SMM_MASK;
2854 else
2855 vcpu->arch.hflags &= ~HF_SMM_MASK;
2856 vcpu->arch.smi_pending = events->smi.pending;
2857 if (events->smi.smm_inside_nmi)
2858 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2859 else
2860 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2861 if (kvm_vcpu_has_lapic(vcpu)) {
2862 if (events->smi.latched_init)
2863 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2864 else
2865 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2866 }
2867 }
2868
3842d135
AK		 2869 kvm_make_request(KVM_REQ_EVENT, vcpu);
2870
3cfc3092
JK		 2871 return 0;
2872}
2873
a1efbe77
JK		 2874static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2875 struct kvm_debugregs *dbgregs)
2876{
73aaf249
JK		 2877 unsigned long val;
2878
a1efbe77 2879 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2880 kvm_get_dr(vcpu, 6, &val);
73aaf249 2881 dbgregs->dr6 = val;
a1efbe77
JK		 2882 dbgregs->dr7 = vcpu->arch.dr7;
2883 dbgregs->flags = 0;
97e69aa6 2884 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2885}
2886
2887static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2888 struct kvm_debugregs *dbgregs)
2889{
2890 if (dbgregs->flags)
2891 return -EINVAL;
2892
a1efbe77 2893 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2894 kvm_update_dr0123(vcpu);
a1efbe77 2895 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2896 kvm_update_dr6(vcpu);
a1efbe77 2897 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2898 kvm_update_dr7(vcpu);
a1efbe77 2899
a1efbe77
JK		 2900 return 0;
2901}
2902
df1daba7
PB		 2903#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2904
2905static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2906{
c47ada30 2907 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2908 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2909 u64 valid;
2910
2911 /*
2912 * Copy legacy XSAVE area, to avoid complications with CPUID
2913 * leaves 0 and 1 in the loop below.
2914 */
2915 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2916
2917 /* Set XSTATE_BV */
2918 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2919
2920 /*
2921 * Copy each region from the possibly compacted offset to the
2922 * non-compacted offset.
2923 */
2924 valid = xstate_bv & ~XSTATE_FPSSE;
2925 while (valid) {
2926 u64 feature = valid & -valid;
2927 int index = fls64(feature) - 1;
2928 void *src = get_xsave_addr(xsave, feature);
2929
2930 if (src) {
2931 u32 size, offset, ecx, edx;
2932 cpuid_count(XSTATE_CPUID, index,
2933 &size, &offset, &ecx, &edx);
2934 memcpy(dest + offset, src, size);
2935 }
2936
2937 valid -= feature;
2938 }
2939}
2940
2941static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2942{
c47ada30 2943 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2944 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2945 u64 valid;
2946
2947 /*
2948 * Copy legacy XSAVE area, to avoid complications with CPUID
2949 * leaves 0 and 1 in the loop below.
2950 */
2951 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2952
2953 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2954 xsave->header.xfeatures = xstate_bv;
df1daba7 2955 if (cpu_has_xsaves)
3a54450b 2956 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2957
2958 /*
2959 * Copy each region from the non-compacted offset to the
2960 * possibly compacted offset.
2961 */
2962 valid = xstate_bv & ~XSTATE_FPSSE;
2963 while (valid) {
2964 u64 feature = valid & -valid;
2965 int index = fls64(feature) - 1;
2966 void *dest = get_xsave_addr(xsave, feature);
2967
2968 if (dest) {
2969 u32 size, offset, ecx, edx;
2970 cpuid_count(XSTATE_CPUID, index,
2971 &size, &offset, &ecx, &edx);
2972 memcpy(dest, src + offset, size);
ee4100da 2973 }
df1daba7
PB		 2974
2975 valid -= feature;
2976 }
2977}
2978
2d5b5a66
SY		 2979static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2980 struct kvm_xsave *guest_xsave)
2981{
4344ee98 2982 if (cpu_has_xsave) {
df1daba7
PB		 2983 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2984 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2985 } else {
2d5b5a66 2986 memcpy(guest_xsave->region,
7366ed77 2987 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2988 sizeof(struct fxregs_state));
2d5b5a66
SY		 2989 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2990 XSTATE_FPSSE;
2991 }
2992}
2993
2994static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2995 struct kvm_xsave *guest_xsave)
2996{
2997 u64 xstate_bv =
2998 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2999
d7876f1b
PB		 3000 if (cpu_has_xsave) {
3001 /*
3002 * Here we allow setting states that are not present in
3003 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3004 * with old userspace.
3005 */
4ff41732 3006 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3007 return -EINVAL;
df1daba7 3008 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3009 } else {
2d5b5a66
SY		 3010 if (xstate_bv & ~XSTATE_FPSSE)
3011 return -EINVAL;
7366ed77 3012 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3013 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3014 }
3015 return 0;
3016}
3017
3018static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3019 struct kvm_xcrs *guest_xcrs)
3020{
3021 if (!cpu_has_xsave) {
3022 guest_xcrs->nr_xcrs = 0;
3023 return;
3024 }
3025
3026 guest_xcrs->nr_xcrs = 1;
3027 guest_xcrs->flags = 0;
3028 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3029 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3030}
3031
3032static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3033 struct kvm_xcrs *guest_xcrs)
3034{
3035 int i, r = 0;
3036
3037 if (!cpu_has_xsave)
3038 return -EINVAL;
3039
3040 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3041 return -EINVAL;
3042
3043 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3044 /* Only support XCR0 currently */
c67a04cb 3045 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3046 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3047 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3048 break;
3049 }
3050 if (r)
3051 r = -EINVAL;
3052 return r;
3053}
3054
1c0b28c2
EM		 3055/*
3056 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3057 * stopped by the hypervisor. This function will be called from the host only.
3058 * EINVAL is returned when the host attempts to set the flag for a guest that
3059 * does not support pv clocks.
3060 */
3061static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3062{
0b79459b 3063 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3064 return -EINVAL;
51d59c6b 3065 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3067 return 0;
3068}
3069
313a3dc7
CO		 3070long kvm_arch_vcpu_ioctl(struct file *filp,
3071 unsigned int ioctl, unsigned long arg)
3072{
3073 struct kvm_vcpu *vcpu = filp->private_data;
3074 void __user *argp = (void __user *)arg;
3075 int r;
d1ac91d8
AK		 3076 union {
3077 struct kvm_lapic_state *lapic;
3078 struct kvm_xsave *xsave;
3079 struct kvm_xcrs *xcrs;
3080 void *buffer;
3081 } u;
3082
3083 u.buffer = NULL;
313a3dc7
CO		 3084 switch (ioctl) {
3085 case KVM_GET_LAPIC: {
2204ae3c
MT		 3086 r = -EINVAL;
3087 if (!vcpu->arch.apic)
3088 goto out;
d1ac91d8 3089 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3090
b772ff36 3091 r = -ENOMEM;
d1ac91d8 3092 if (!u.lapic)
b772ff36 3093 goto out;
d1ac91d8 3094 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3095 if (r)
3096 goto out;
3097 r = -EFAULT;
d1ac91d8 3098 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3099 goto out;
3100 r = 0;
3101 break;
3102 }
3103 case KVM_SET_LAPIC: {
2204ae3c
MT		 3104 r = -EINVAL;
3105 if (!vcpu->arch.apic)
3106 goto out;
ff5c2c03 3107 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3108 if (IS_ERR(u.lapic))
3109 return PTR_ERR(u.lapic);
ff5c2c03 3110
d1ac91d8 3111 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3112 break;
3113 }
f77bc6a4
ZX		 3114 case KVM_INTERRUPT: {
3115 struct kvm_interrupt irq;
3116
3117 r = -EFAULT;
3118 if (copy_from_user(&irq, argp, sizeof irq))
3119 goto out;
3120 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3121 break;
3122 }
c4abb7c9
JK		 3123 case KVM_NMI: {
3124 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3125 break;
3126 }
f077825a
PB		 3127 case KVM_SMI: {
3128 r = kvm_vcpu_ioctl_smi(vcpu);
3129 break;
3130 }
313a3dc7
CO		 3131 case KVM_SET_CPUID: {
3132 struct kvm_cpuid __user *cpuid_arg = argp;
3133 struct kvm_cpuid cpuid;
3134
3135 r = -EFAULT;
3136 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3137 goto out;
3138 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3139 break;
3140 }
07716717
DK		 3141 case KVM_SET_CPUID2: {
3142 struct kvm_cpuid2 __user *cpuid_arg = argp;
3143 struct kvm_cpuid2 cpuid;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3147 goto out;
3148 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3149 cpuid_arg->entries);
07716717
DK		 3150 break;
3151 }
3152 case KVM_GET_CPUID2: {
3153 struct kvm_cpuid2 __user *cpuid_arg = argp;
3154 struct kvm_cpuid2 cpuid;
3155
3156 r = -EFAULT;
3157 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3158 goto out;
3159 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3160 cpuid_arg->entries);
07716717
DK		 3161 if (r)
3162 goto out;
3163 r = -EFAULT;
3164 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3165 goto out;
3166 r = 0;
3167 break;
3168 }
313a3dc7 3169 case KVM_GET_MSRS:
609e36d3 3170 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3171 break;
3172 case KVM_SET_MSRS:
3173 r = msr_io(vcpu, argp, do_set_msr, 0);
3174 break;
b209749f
AK		 3175 case KVM_TPR_ACCESS_REPORTING: {
3176 struct kvm_tpr_access_ctl tac;
3177
3178 r = -EFAULT;
3179 if (copy_from_user(&tac, argp, sizeof tac))
3180 goto out;
3181 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3182 if (r)
3183 goto out;
3184 r = -EFAULT;
3185 if (copy_to_user(argp, &tac, sizeof tac))
3186 goto out;
3187 r = 0;
3188 break;
3189 };
b93463aa
AK		 3190 case KVM_SET_VAPIC_ADDR: {
3191 struct kvm_vapic_addr va;
3192
3193 r = -EINVAL;
35754c98 3194 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3195 goto out;
3196 r = -EFAULT;
3197 if (copy_from_user(&va, argp, sizeof va))
3198 goto out;
fda4e2e8 3199 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3200 break;
3201 }
890ca9ae
HY		 3202 case KVM_X86_SETUP_MCE: {
3203 u64 mcg_cap;
3204
3205 r = -EFAULT;
3206 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3207 goto out;
3208 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3209 break;
3210 }
3211 case KVM_X86_SET_MCE: {
3212 struct kvm_x86_mce mce;
3213
3214 r = -EFAULT;
3215 if (copy_from_user(&mce, argp, sizeof mce))
3216 goto out;
3217 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3218 break;
3219 }
3cfc3092
JK		 3220 case KVM_GET_VCPU_EVENTS: {
3221 struct kvm_vcpu_events events;
3222
3223 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3224
3225 r = -EFAULT;
3226 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3227 break;
3228 r = 0;
3229 break;
3230 }
3231 case KVM_SET_VCPU_EVENTS: {
3232 struct kvm_vcpu_events events;
3233
3234 r = -EFAULT;
3235 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3236 break;
3237
3238 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3239 break;
3240 }
a1efbe77
JK		 3241 case KVM_GET_DEBUGREGS: {
3242 struct kvm_debugregs dbgregs;
3243
3244 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3245
3246 r = -EFAULT;
3247 if (copy_to_user(argp, &dbgregs,
3248 sizeof(struct kvm_debugregs)))
3249 break;
3250 r = 0;
3251 break;
3252 }
3253 case KVM_SET_DEBUGREGS: {
3254 struct kvm_debugregs dbgregs;
3255
3256 r = -EFAULT;
3257 if (copy_from_user(&dbgregs, argp,
3258 sizeof(struct kvm_debugregs)))
3259 break;
3260
3261 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3262 break;
3263 }
2d5b5a66 3264 case KVM_GET_XSAVE: {
d1ac91d8 3265 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3266 r = -ENOMEM;
d1ac91d8 3267 if (!u.xsave)
2d5b5a66
SY		 3268 break;
3269
d1ac91d8 3270 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3271
3272 r = -EFAULT;
d1ac91d8 3273 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3274 break;
3275 r = 0;
3276 break;
3277 }
3278 case KVM_SET_XSAVE: {
ff5c2c03 3279 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3280 if (IS_ERR(u.xsave))
3281 return PTR_ERR(u.xsave);
2d5b5a66 3282
d1ac91d8 3283 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3284 break;
3285 }
3286 case KVM_GET_XCRS: {
d1ac91d8 3287 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3288 r = -ENOMEM;
d1ac91d8 3289 if (!u.xcrs)
2d5b5a66
SY		 3290 break;
3291
d1ac91d8 3292 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3293
3294 r = -EFAULT;
d1ac91d8 3295 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3296 sizeof(struct kvm_xcrs)))
3297 break;
3298 r = 0;
3299 break;
3300 }
3301 case KVM_SET_XCRS: {
ff5c2c03 3302 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3303 if (IS_ERR(u.xcrs))
3304 return PTR_ERR(u.xcrs);
2d5b5a66 3305
d1ac91d8 3306 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3307 break;
3308 }
92a1f12d
JR		 3309 case KVM_SET_TSC_KHZ: {
3310 u32 user_tsc_khz;
3311
3312 r = -EINVAL;
92a1f12d
JR		 3313 user_tsc_khz = (u32)arg;
3314
3315 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3316 goto out;
3317
cc578287
ZA		 3318 if (user_tsc_khz == 0)
3319 user_tsc_khz = tsc_khz;
3320
3321 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3322
3323 r = 0;
3324 goto out;
3325 }
3326 case KVM_GET_TSC_KHZ: {
cc578287 3327 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3328 goto out;
3329 }
1c0b28c2
EM		 3330 case KVM_KVMCLOCK_CTRL: {
3331 r = kvm_set_guest_paused(vcpu);
3332 goto out;
3333 }
313a3dc7
CO		 3334 default:
3335 r = -EINVAL;
3336 }
3337out:
d1ac91d8 3338 kfree(u.buffer);
313a3dc7
CO		 3339 return r;
3340}
3341
5b1c1493
CO		 3342int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3343{
3344 return VM_FAULT_SIGBUS;
3345}
3346
1fe779f8
CO		 3347static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3348{
3349 int ret;
3350
3351 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3352 return -EINVAL;
1fe779f8
CO		 3353 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3354 return ret;
3355}
3356
b927a3ce
SY		 3357static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3358 u64 ident_addr)
3359{
3360 kvm->arch.ept_identity_map_addr = ident_addr;
3361 return 0;
3362}
3363
1fe779f8
CO		 3364static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3365 u32 kvm_nr_mmu_pages)
3366{
3367 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3368 return -EINVAL;
3369
79fac95e 3370 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3371
3372 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3373 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3374
79fac95e 3375 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3376 return 0;
3377}
3378
3379static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3380{
39de71ec 3381 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3382}
3383
1fe779f8
CO		 3384static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3385{
3386 int r;
3387
3388 r = 0;
3389 switch (chip->chip_id) {
3390 case KVM_IRQCHIP_PIC_MASTER:
3391 memcpy(&chip->chip.pic,
3392 &pic_irqchip(kvm)->pics[0],
3393 sizeof(struct kvm_pic_state));
3394 break;
3395 case KVM_IRQCHIP_PIC_SLAVE:
3396 memcpy(&chip->chip.pic,
3397 &pic_irqchip(kvm)->pics[1],
3398 sizeof(struct kvm_pic_state));
3399 break;
3400 case KVM_IRQCHIP_IOAPIC:
eba0226b 3401 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3402 break;
3403 default:
3404 r = -EINVAL;
3405 break;
3406 }
3407 return r;
3408}
3409
3410static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3411{
3412 int r;
3413
3414 r = 0;
3415 switch (chip->chip_id) {
3416 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3417 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3418 memcpy(&pic_irqchip(kvm)->pics[0],
3419 &chip->chip.pic,
3420 sizeof(struct kvm_pic_state));
f4f51050 3421 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3422 break;
3423 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3424 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3425 memcpy(&pic_irqchip(kvm)->pics[1],
3426 &chip->chip.pic,
3427 sizeof(struct kvm_pic_state));
f4f51050 3428 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3429 break;
3430 case KVM_IRQCHIP_IOAPIC:
eba0226b 3431 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3432 break;
3433 default:
3434 r = -EINVAL;
3435 break;
3436 }
3437 kvm_pic_update_irq(pic_irqchip(kvm));
3438 return r;
3439}
3440
e0f63cb9
SY		 3441static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3442{
3443 int r = 0;
3444
894a9c55 3445 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3446 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3447 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3448 return r;
3449}
3450
3451static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3452{
3453 int r = 0;
3454
894a9c55 3455 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3456 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3457 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3458 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3459 return r;
3460}
3461
3462static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3463{
3464 int r = 0;
3465
3466 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3467 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3468 sizeof(ps->channels));
3469 ps->flags = kvm->arch.vpit->pit_state.flags;
3470 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3471 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3472 return r;
3473}
3474
3475static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3476{
3477 int r = 0, start = 0;
3478 u32 prev_legacy, cur_legacy;
3479 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3480 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3481 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3482 if (!prev_legacy && cur_legacy)
3483 start = 1;
3484 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3485 sizeof(kvm->arch.vpit->pit_state.channels));
3486 kvm->arch.vpit->pit_state.flags = ps->flags;
3487 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3488 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3489 return r;
3490}
3491
52d939a0
MT		 3492static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3493 struct kvm_reinject_control *control)
3494{
3495 if (!kvm->arch.vpit)
3496 return -ENXIO;
894a9c55 3497 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3498 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3499 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3500 return 0;
3501}
3502
95d4c16c 3503/**
60c34612
TY		 3504 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3505 * @kvm: kvm instance
3506 * @log: slot id and address to which we copy the log
95d4c16c 3507 *
e108ff2f
PB		 3508 * Steps 1-4 below provide general overview of dirty page logging. See
3509 * kvm_get_dirty_log_protect() function description for additional details.
3510 *
3511 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3512 * always flush the TLB (step 4) even if previous step failed and the dirty
3513 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3514 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3515 * writes will be marked dirty for next log read.
95d4c16c 3516 *
60c34612
TY		 3517 * 1. Take a snapshot of the bit and clear it if needed.
3518 * 2. Write protect the corresponding page.
e108ff2f
PB		 3519 * 3. Copy the snapshot to the userspace.
3520 * 4. Flush TLB's if needed.
5bb064dc 3521 */
60c34612 3522int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3523{
60c34612 3524 bool is_dirty = false;
e108ff2f 3525 int r;
5bb064dc 3526
79fac95e 3527 mutex_lock(&kvm->slots_lock);
5bb064dc 3528
88178fd4
KH		 3529 /*
3530 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3531 */
3532 if (kvm_x86_ops->flush_log_dirty)
3533 kvm_x86_ops->flush_log_dirty(kvm);
3534
e108ff2f 3535 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3536
3537 /*
3538 * All the TLBs can be flushed out of mmu lock, see the comments in
3539 * kvm_mmu_slot_remove_write_access().
3540 */
e108ff2f 3541 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3542 if (is_dirty)
3543 kvm_flush_remote_tlbs(kvm);
3544
79fac95e 3545 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3546 return r;
3547}
3548
aa2fbe6d
YZ		 3549int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3550 bool line_status)
23d43cf9
CD		 3551{
3552 if (!irqchip_in_kernel(kvm))
3553 return -ENXIO;
3554
3555 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3556 irq_event->irq, irq_event->level,
3557 line_status);
23d43cf9
CD		 3558 return 0;
3559}
3560
90de4a18
NA		 3561static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3562 struct kvm_enable_cap *cap)
3563{
3564 int r;
3565
3566 if (cap->flags)
3567 return -EINVAL;
3568
3569 switch (cap->cap) {
3570 case KVM_CAP_DISABLE_QUIRKS:
3571 kvm->arch.disabled_quirks = cap->args[0];
3572 r = 0;
3573 break;
49df6397
SR		 3574 case KVM_CAP_SPLIT_IRQCHIP: {
3575 mutex_lock(&kvm->lock);
b053b2ae
SR		 3576 r = -EINVAL;
3577 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3578 goto split_irqchip_unlock;
49df6397
SR		 3579 r = -EEXIST;
3580 if (irqchip_in_kernel(kvm))
3581 goto split_irqchip_unlock;
3582 if (atomic_read(&kvm->online_vcpus))
3583 goto split_irqchip_unlock;
3584 r = kvm_setup_empty_irq_routing(kvm);
3585 if (r)
3586 goto split_irqchip_unlock;
3587 /* Pairs with irqchip_in_kernel. */
3588 smp_wmb();
3589 kvm->arch.irqchip_split = true;
b053b2ae 3590 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3591 r = 0;
3592split_irqchip_unlock:
3593 mutex_unlock(&kvm->lock);
3594 break;
3595 }
90de4a18
NA		 3596 default:
3597 r = -EINVAL;
3598 break;
3599 }
3600 return r;
3601}
3602
1fe779f8
CO		 3603long kvm_arch_vm_ioctl(struct file *filp,
3604 unsigned int ioctl, unsigned long arg)
3605{
3606 struct kvm *kvm = filp->private_data;
3607 void __user *argp = (void __user *)arg;
367e1319 3608 int r = -ENOTTY;
f0d66275
DH		 3609 /*
3610 * This union makes it completely explicit to gcc-3.x
3611 * that these two variables' stack usage should be
3612 * combined, not added together.
3613 */
3614 union {
3615 struct kvm_pit_state ps;
e9f42757 3616 struct kvm_pit_state2 ps2;
c5ff41ce 3617 struct kvm_pit_config pit_config;
f0d66275 3618 } u;
1fe779f8
CO		 3619
3620 switch (ioctl) {
3621 case KVM_SET_TSS_ADDR:
3622 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3623 break;
b927a3ce
SY		 3624 case KVM_SET_IDENTITY_MAP_ADDR: {
3625 u64 ident_addr;
3626
3627 r = -EFAULT;
3628 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3629 goto out;
3630 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3631 break;
3632 }
1fe779f8
CO		 3633 case KVM_SET_NR_MMU_PAGES:
3634 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3635 break;
3636 case KVM_GET_NR_MMU_PAGES:
3637 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3638 break;
3ddea128
MT		 3639 case KVM_CREATE_IRQCHIP: {
3640 struct kvm_pic *vpic;
3641
3642 mutex_lock(&kvm->lock);
3643 r = -EEXIST;
3644 if (kvm->arch.vpic)
3645 goto create_irqchip_unlock;
3e515705
AK		 3646 r = -EINVAL;
3647 if (atomic_read(&kvm->online_vcpus))
3648 goto create_irqchip_unlock;
1fe779f8 3649 r = -ENOMEM;
3ddea128
MT		 3650 vpic = kvm_create_pic(kvm);
3651 if (vpic) {
1fe779f8
CO		 3652 r = kvm_ioapic_init(kvm);
3653 if (r) {
175504cd 3654 mutex_lock(&kvm->slots_lock);
71ba994c 3655 kvm_destroy_pic(vpic);
175504cd 3656 mutex_unlock(&kvm->slots_lock);
3ddea128 3657 goto create_irqchip_unlock;
1fe779f8
CO		 3658 }
3659 } else
3ddea128 3660 goto create_irqchip_unlock;
399ec807
AK		 3661 r = kvm_setup_default_irq_routing(kvm);
3662 if (r) {
175504cd 3663 mutex_lock(&kvm->slots_lock);
3ddea128 3664 mutex_lock(&kvm->irq_lock);
72bb2fcd 3665 kvm_ioapic_destroy(kvm);
71ba994c 3666 kvm_destroy_pic(vpic);
3ddea128 3667 mutex_unlock(&kvm->irq_lock);
175504cd 3668 mutex_unlock(&kvm->slots_lock);
71ba994c 3669 goto create_irqchip_unlock;
399ec807 3670 }
71ba994c
PB		 3671 /* Write kvm->irq_routing before kvm->arch.vpic. */
3672 smp_wmb();
3673 kvm->arch.vpic = vpic;
3ddea128
MT		 3674 create_irqchip_unlock:
3675 mutex_unlock(&kvm->lock);
1fe779f8 3676 break;
3ddea128 3677 }
7837699f 3678 case KVM_CREATE_PIT:
c5ff41ce
JK		 3679 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3680 goto create_pit;
3681 case KVM_CREATE_PIT2:
3682 r = -EFAULT;
3683 if (copy_from_user(&u.pit_config, argp,
3684 sizeof(struct kvm_pit_config)))
3685 goto out;
3686 create_pit:
79fac95e 3687 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3688 r = -EEXIST;
3689 if (kvm->arch.vpit)
3690 goto create_pit_unlock;
7837699f 3691 r = -ENOMEM;
c5ff41ce 3692 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3693 if (kvm->arch.vpit)
3694 r = 0;
269e05e4 3695 create_pit_unlock:
79fac95e 3696 mutex_unlock(&kvm->slots_lock);
7837699f 3697 break;
1fe779f8
CO		 3698 case KVM_GET_IRQCHIP: {
3699 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3700 struct kvm_irqchip *chip;
1fe779f8 3701
ff5c2c03
SL		 3702 chip = memdup_user(argp, sizeof(*chip));
3703 if (IS_ERR(chip)) {
3704 r = PTR_ERR(chip);
1fe779f8 3705 goto out;
ff5c2c03
SL		 3706 }
3707
1fe779f8 3708 r = -ENXIO;
49df6397 3709 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3710 goto get_irqchip_out;
3711 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3712 if (r)
f0d66275 3713 goto get_irqchip_out;
1fe779f8 3714 r = -EFAULT;
f0d66275
DH		 3715 if (copy_to_user(argp, chip, sizeof *chip))
3716 goto get_irqchip_out;
1fe779f8 3717 r = 0;
f0d66275
DH		 3718 get_irqchip_out:
3719 kfree(chip);
1fe779f8
CO		 3720 break;
3721 }
3722 case KVM_SET_IRQCHIP: {
3723 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3724 struct kvm_irqchip *chip;
1fe779f8 3725
ff5c2c03
SL		 3726 chip = memdup_user(argp, sizeof(*chip));
3727 if (IS_ERR(chip)) {
3728 r = PTR_ERR(chip);
1fe779f8 3729 goto out;
ff5c2c03
SL		 3730 }
3731
1fe779f8 3732 r = -ENXIO;
49df6397 3733 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3734 goto set_irqchip_out;
3735 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3736 if (r)
f0d66275 3737 goto set_irqchip_out;
1fe779f8 3738 r = 0;
f0d66275
DH		 3739 set_irqchip_out:
3740 kfree(chip);
1fe779f8
CO		 3741 break;
3742 }
e0f63cb9 3743 case KVM_GET_PIT: {
e0f63cb9 3744 r = -EFAULT;
f0d66275 3745 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3746 goto out;
3747 r = -ENXIO;
3748 if (!kvm->arch.vpit)
3749 goto out;
f0d66275 3750 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3751 if (r)
3752 goto out;
3753 r = -EFAULT;
f0d66275 3754 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3755 goto out;
3756 r = 0;
3757 break;
3758 }
3759 case KVM_SET_PIT: {
e0f63cb9 3760 r = -EFAULT;
f0d66275 3761 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3762 goto out;
3763 r = -ENXIO;
3764 if (!kvm->arch.vpit)
3765 goto out;
f0d66275 3766 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3767 break;
3768 }
e9f42757
BK		 3769 case KVM_GET_PIT2: {
3770 r = -ENXIO;
3771 if (!kvm->arch.vpit)
3772 goto out;
3773 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3774 if (r)
3775 goto out;
3776 r = -EFAULT;
3777 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3778 goto out;
3779 r = 0;
3780 break;
3781 }
3782 case KVM_SET_PIT2: {
3783 r = -EFAULT;
3784 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3785 goto out;
3786 r = -ENXIO;
3787 if (!kvm->arch.vpit)
3788 goto out;
3789 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3790 break;
3791 }
52d939a0
MT		 3792 case KVM_REINJECT_CONTROL: {
3793 struct kvm_reinject_control control;
3794 r = -EFAULT;
3795 if (copy_from_user(&control, argp, sizeof(control)))
3796 goto out;
3797 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3798 break;
3799 }
d71ba788
PB		 3800 case KVM_SET_BOOT_CPU_ID:
3801 r = 0;
3802 mutex_lock(&kvm->lock);
3803 if (atomic_read(&kvm->online_vcpus) != 0)
3804 r = -EBUSY;
3805 else
3806 kvm->arch.bsp_vcpu_id = arg;
3807 mutex_unlock(&kvm->lock);
3808 break;
ffde22ac
ES		 3809 case KVM_XEN_HVM_CONFIG: {
3810 r = -EFAULT;
3811 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3812 sizeof(struct kvm_xen_hvm_config)))
3813 goto out;
3814 r = -EINVAL;
3815 if (kvm->arch.xen_hvm_config.flags)
3816 goto out;
3817 r = 0;
3818 break;
3819 }
afbcf7ab 3820 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3821 struct kvm_clock_data user_ns;
3822 u64 now_ns;
3823 s64 delta;
3824
3825 r = -EFAULT;
3826 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3827 goto out;
3828
3829 r = -EINVAL;
3830 if (user_ns.flags)
3831 goto out;
3832
3833 r = 0;
395c6b0a 3834 local_irq_disable();
759379dd 3835 now_ns = get_kernel_ns();
afbcf7ab 3836 delta = user_ns.clock - now_ns;
395c6b0a 3837 local_irq_enable();
afbcf7ab 3838 kvm->arch.kvmclock_offset = delta;
2e762ff7 3839 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3840 break;
3841 }
3842 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3843 struct kvm_clock_data user_ns;
3844 u64 now_ns;
3845
395c6b0a 3846 local_irq_disable();
759379dd 3847 now_ns = get_kernel_ns();
afbcf7ab 3848 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3849 local_irq_enable();
afbcf7ab 3850 user_ns.flags = 0;
97e69aa6 3851 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3852
3853 r = -EFAULT;
3854 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3855 goto out;
3856 r = 0;
3857 break;
3858 }
90de4a18
NA		 3859 case KVM_ENABLE_CAP: {
3860 struct kvm_enable_cap cap;
afbcf7ab 3861
90de4a18
NA		 3862 r = -EFAULT;
3863 if (copy_from_user(&cap, argp, sizeof(cap)))
3864 goto out;
3865 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3866 break;
3867 }
1fe779f8 3868 default:
c274e03a 3869 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3870 }
3871out:
3872 return r;
3873}
3874
a16b043c 3875static void kvm_init_msr_list(void)
043405e1
CO		 3876{
3877 u32 dummy[2];
3878 unsigned i, j;
3879
62ef68bb 3880 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3881 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3882 continue;
93c4adc7
PB		 3883
3884 /*
3885 * Even MSRs that are valid in the host may not be exposed
3886 * to the guests in some cases. We could work around this
3887 * in VMX with the generic MSR save/load machinery, but it
3888 * is not really worthwhile since it will really only
3889 * happen with nested virtualization.
3890 */
3891 switch (msrs_to_save[i]) {
3892 case MSR_IA32_BNDCFGS:
3893 if (!kvm_x86_ops->mpx_supported())
3894 continue;
3895 break;
3896 default:
3897 break;
3898 }
3899
043405e1
CO		 3900 if (j < i)
3901 msrs_to_save[j] = msrs_to_save[i];
3902 j++;
3903 }
3904 num_msrs_to_save = j;
62ef68bb
PB		 3905
3906 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3907 switch (emulated_msrs[i]) {
6d396b55
PB		 3908 case MSR_IA32_SMBASE:
3909 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3910 continue;
3911 break;
62ef68bb
PB		 3912 default:
3913 break;
3914 }
3915
3916 if (j < i)
3917 emulated_msrs[j] = emulated_msrs[i];
3918 j++;
3919 }
3920 num_emulated_msrs = j;
043405e1
CO		 3921}
3922
bda9020e
MT		 3923static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3924 const void *v)
bbd9b64e 3925{
70252a10
AK		 3926 int handled = 0;
3927 int n;
3928
3929 do {
3930 n = min(len, 8);
3931 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3932 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3933 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3934 break;
3935 handled += n;
3936 addr += n;
3937 len -= n;
3938 v += n;
3939 } while (len);
bbd9b64e 3940
70252a10 3941 return handled;
bbd9b64e
CO		 3942}
3943
bda9020e 3944static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3945{
70252a10
AK		 3946 int handled = 0;
3947 int n;
3948
3949 do {
3950 n = min(len, 8);
3951 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3952 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3953 addr, n, v))
3954 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3955 break;
3956 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3957 handled += n;
3958 addr += n;
3959 len -= n;
3960 v += n;
3961 } while (len);
bbd9b64e 3962
70252a10 3963 return handled;
bbd9b64e
CO		 3964}
3965
2dafc6c2
GN		 3966static void kvm_set_segment(struct kvm_vcpu *vcpu,
3967 struct kvm_segment *var, int seg)
3968{
3969 kvm_x86_ops->set_segment(vcpu, var, seg);
3970}
3971
3972void kvm_get_segment(struct kvm_vcpu *vcpu,
3973 struct kvm_segment *var, int seg)
3974{
3975 kvm_x86_ops->get_segment(vcpu, var, seg);
3976}
3977
54987b7a
PB		 3978gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3979 struct x86_exception *exception)
02f59dc9
JR		 3980{
3981 gpa_t t_gpa;
02f59dc9
JR		 3982
3983 BUG_ON(!mmu_is_nested(vcpu));
3984
3985 /* NPT walks are always user-walks */
3986 access |= PFERR_USER_MASK;
54987b7a 3987 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3988
3989 return t_gpa;
3990}
3991
ab9ae313
AK		 3992gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3993 struct x86_exception *exception)
1871c602
GN		 3994{
3995 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3996 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3997}
3998
ab9ae313
AK		 3999 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4000 struct x86_exception *exception)
1871c602
GN		 4001{
4002 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4003 access |= PFERR_FETCH_MASK;
ab9ae313 4004 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4005}
4006
ab9ae313
AK		 4007gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4008 struct x86_exception *exception)
1871c602
GN		 4009{
4010 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4011 access |= PFERR_WRITE_MASK;
ab9ae313 4012 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4013}
4014
4015/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4016gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4017 struct x86_exception *exception)
1871c602 4018{
ab9ae313 4019 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4020}
4021
4022static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4023 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4024 struct x86_exception *exception)
bbd9b64e
CO		 4025{
4026 void *data = val;
10589a46 4027 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4028
4029 while (bytes) {
14dfe855 4030 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4031 exception);
bbd9b64e 4032 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4033 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4034 int ret;
4035
bcc55cba 4036 if (gpa == UNMAPPED_GVA)
ab9ae313 4037 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4038 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4039 offset, toread);
10589a46 4040 if (ret < 0) {
c3cd7ffa 4041 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4042 goto out;
4043 }
bbd9b64e 4044
77c2002e
IE		 4045 bytes -= toread;
4046 data += toread;
4047 addr += toread;
bbd9b64e 4048 }
10589a46 4049out:
10589a46 4050 return r;
bbd9b64e 4051}
77c2002e 4052
1871c602 4053/* used for instruction fetching */
0f65dd70
AK		 4054static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4055 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4056 struct x86_exception *exception)
1871c602 4057{
0f65dd70 4058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4059 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4060 unsigned offset;
4061 int ret;
0f65dd70 4062
44583cba
PB		 4063 /* Inline kvm_read_guest_virt_helper for speed. */
4064 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4065 exception);
4066 if (unlikely(gpa == UNMAPPED_GVA))
4067 return X86EMUL_PROPAGATE_FAULT;
4068
4069 offset = addr & (PAGE_SIZE-1);
4070 if (WARN_ON(offset + bytes > PAGE_SIZE))
4071 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4072 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4073 offset, bytes);
44583cba
PB		 4074 if (unlikely(ret < 0))
4075 return X86EMUL_IO_NEEDED;
4076
4077 return X86EMUL_CONTINUE;
1871c602
GN		 4078}
4079
064aea77 4080int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4081 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4082 struct x86_exception *exception)
1871c602 4083{
0f65dd70 4084 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4085 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4086
1871c602 4087 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4088 exception);
1871c602 4089}
064aea77 4090EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4091
0f65dd70
AK		 4092static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4093 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4094 struct x86_exception *exception)
1871c602 4095{
0f65dd70 4096 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4097 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4098}
4099
6a4d7550 4100int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4101 gva_t addr, void *val,
2dafc6c2 4102 unsigned int bytes,
bcc55cba 4103 struct x86_exception *exception)
77c2002e 4104{
0f65dd70 4105 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4106 void *data = val;
4107 int r = X86EMUL_CONTINUE;
4108
4109 while (bytes) {
14dfe855
JR		 4110 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4111 PFERR_WRITE_MASK,
ab9ae313 4112 exception);
77c2002e
IE		 4113 unsigned offset = addr & (PAGE_SIZE-1);
4114 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4115 int ret;
4116
bcc55cba 4117 if (gpa == UNMAPPED_GVA)
ab9ae313 4118 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4119 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4120 if (ret < 0) {
c3cd7ffa 4121 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4122 goto out;
4123 }
4124
4125 bytes -= towrite;
4126 data += towrite;
4127 addr += towrite;
4128 }
4129out:
4130 return r;
4131}
6a4d7550 4132EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4133
af7cc7d1
XG		 4134static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4135 gpa_t *gpa, struct x86_exception *exception,
4136 bool write)
4137{
97d64b78
AK		 4138 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4139 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4140
97d64b78 4141 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4142 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4143 vcpu->arch.access, access)) {
bebb106a
XG		 4144 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4145 (gva & (PAGE_SIZE - 1));
4f022648 4146 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4147 return 1;
4148 }
4149
af7cc7d1
XG		 4150 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4151
4152 if (*gpa == UNMAPPED_GVA)
4153 return -1;
4154
4155 /* For APIC access vmexit */
4156 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4157 return 1;
4158
4f022648
XG		 4159 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4160 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4161 return 1;
4f022648 4162 }
bebb106a 4163
af7cc7d1
XG		 4164 return 0;
4165}
4166
3200f405 4167int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4168 const void *val, int bytes)
bbd9b64e
CO		 4169{
4170 int ret;
4171
54bf36aa 4172 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4173 if (ret < 0)
bbd9b64e 4174 return 0;
f57f2ef5 4175 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4176 return 1;
4177}
4178
77d197b2
XG		 4179struct read_write_emulator_ops {
4180 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4181 int bytes);
4182 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4183 void *val, int bytes);
4184 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4185 int bytes, void *val);
4186 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4187 void *val, int bytes);
4188 bool write;
4189};
4190
4191static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4192{
4193 if (vcpu->mmio_read_completed) {
77d197b2 4194 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4195 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4196 vcpu->mmio_read_completed = 0;
4197 return 1;
4198 }
4199
4200 return 0;
4201}
4202
4203static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4204 void *val, int bytes)
4205{
54bf36aa 4206 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4207}
4208
4209static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4210 void *val, int bytes)
4211{
4212 return emulator_write_phys(vcpu, gpa, val, bytes);
4213}
4214
4215static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4216{
4217 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4218 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4219}
4220
4221static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4222 void *val, int bytes)
4223{
4224 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4225 return X86EMUL_IO_NEEDED;
4226}
4227
4228static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4229 void *val, int bytes)
4230{
f78146b0
AK		 4231 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4232
87da7e66 4233 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4234 return X86EMUL_CONTINUE;
4235}
4236
0fbe9b0b 4237static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4238 .read_write_prepare = read_prepare,
4239 .read_write_emulate = read_emulate,
4240 .read_write_mmio = vcpu_mmio_read,
4241 .read_write_exit_mmio = read_exit_mmio,
4242};
4243
0fbe9b0b 4244static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4245 .read_write_emulate = write_emulate,
4246 .read_write_mmio = write_mmio,
4247 .read_write_exit_mmio = write_exit_mmio,
4248 .write = true,
4249};
4250
22388a3c
XG		 4251static int emulator_read_write_onepage(unsigned long addr, void *val,
4252 unsigned int bytes,
4253 struct x86_exception *exception,
4254 struct kvm_vcpu *vcpu,
0fbe9b0b 4255 const struct read_write_emulator_ops *ops)
bbd9b64e 4256{
af7cc7d1
XG		 4257 gpa_t gpa;
4258 int handled, ret;
22388a3c 4259 bool write = ops->write;
f78146b0 4260 struct kvm_mmio_fragment *frag;
10589a46 4261
22388a3c 4262 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4263
af7cc7d1 4264 if (ret < 0)
bbd9b64e 4265 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4266
4267 /* For APIC access vmexit */
af7cc7d1 4268 if (ret)
bbd9b64e
CO		 4269 goto mmio;
4270
22388a3c 4271 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4272 return X86EMUL_CONTINUE;
4273
4274mmio:
4275 /*
4276 * Is this MMIO handled locally?
4277 */
22388a3c 4278 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4279 if (handled == bytes)
bbd9b64e 4280 return X86EMUL_CONTINUE;
bbd9b64e 4281
70252a10
AK		 4282 gpa += handled;
4283 bytes -= handled;
4284 val += handled;
4285
87da7e66
XG		 4286 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4287 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4288 frag->gpa = gpa;
4289 frag->data = val;
4290 frag->len = bytes;
f78146b0 4291 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4292}
4293
52eb5a6d
XL		 4294static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4295 unsigned long addr,
22388a3c
XG		 4296 void *val, unsigned int bytes,
4297 struct x86_exception *exception,
0fbe9b0b 4298 const struct read_write_emulator_ops *ops)
bbd9b64e 4299{
0f65dd70 4300 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4301 gpa_t gpa;
4302 int rc;
4303
4304 if (ops->read_write_prepare &&
4305 ops->read_write_prepare(vcpu, val, bytes))
4306 return X86EMUL_CONTINUE;
4307
4308 vcpu->mmio_nr_fragments = 0;
0f65dd70 4309
bbd9b64e
CO		 4310 /* Crossing a page boundary? */
4311 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4312 int now;
bbd9b64e
CO		 4313
4314 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4315 rc = emulator_read_write_onepage(addr, val, now, exception,
4316 vcpu, ops);
4317
bbd9b64e
CO		 4318 if (rc != X86EMUL_CONTINUE)
4319 return rc;
4320 addr += now;
bac15531
NA		 4321 if (ctxt->mode != X86EMUL_MODE_PROT64)
4322 addr = (u32)addr;
bbd9b64e
CO		 4323 val += now;
4324 bytes -= now;
4325 }
22388a3c 4326
f78146b0
AK		 4327 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4328 vcpu, ops);
4329 if (rc != X86EMUL_CONTINUE)
4330 return rc;
4331
4332 if (!vcpu->mmio_nr_fragments)
4333 return rc;
4334
4335 gpa = vcpu->mmio_fragments[0].gpa;
4336
4337 vcpu->mmio_needed = 1;
4338 vcpu->mmio_cur_fragment = 0;
4339
87da7e66 4340 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4341 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4342 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4343 vcpu->run->mmio.phys_addr = gpa;
4344
4345 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4346}
4347
4348static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4349 unsigned long addr,
4350 void *val,
4351 unsigned int bytes,
4352 struct x86_exception *exception)
4353{
4354 return emulator_read_write(ctxt, addr, val, bytes,
4355 exception, &read_emultor);
4356}
4357
52eb5a6d 4358static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4359 unsigned long addr,
4360 const void *val,
4361 unsigned int bytes,
4362 struct x86_exception *exception)
4363{
4364 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4365 exception, &write_emultor);
bbd9b64e 4366}
bbd9b64e 4367
daea3e73
AK		 4368#define CMPXCHG_TYPE(t, ptr, old, new) \
4369 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4370
4371#ifdef CONFIG_X86_64
4372# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4373#else
4374# define CMPXCHG64(ptr, old, new) \
9749a6c0 4375 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4376#endif
4377
0f65dd70
AK		 4378static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4379 unsigned long addr,
bbd9b64e
CO		 4380 const void *old,
4381 const void *new,
4382 unsigned int bytes,
0f65dd70 4383 struct x86_exception *exception)
bbd9b64e 4384{
0f65dd70 4385 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4386 gpa_t gpa;
4387 struct page *page;
4388 char *kaddr;
4389 bool exchanged;
2bacc55c 4390
daea3e73
AK		 4391 /* guests cmpxchg8b have to be emulated atomically */
4392 if (bytes > 8 || (bytes & (bytes - 1)))
4393 goto emul_write;
10589a46 4394
daea3e73 4395 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4396
daea3e73
AK		 4397 if (gpa == UNMAPPED_GVA ||
4398 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4399 goto emul_write;
2bacc55c 4400
daea3e73
AK		 4401 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4402 goto emul_write;
72dc67a6 4403
54bf36aa 4404 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4405 if (is_error_page(page))
c19b8bd6 4406 goto emul_write;
72dc67a6 4407
8fd75e12 4408 kaddr = kmap_atomic(page);
daea3e73
AK		 4409 kaddr += offset_in_page(gpa);
4410 switch (bytes) {
4411 case 1:
4412 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4413 break;
4414 case 2:
4415 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4416 break;
4417 case 4:
4418 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4419 break;
4420 case 8:
4421 exchanged = CMPXCHG64(kaddr, old, new);
4422 break;
4423 default:
4424 BUG();
2bacc55c 4425 }
8fd75e12 4426 kunmap_atomic(kaddr);
daea3e73
AK		 4427 kvm_release_page_dirty(page);
4428
4429 if (!exchanged)
4430 return X86EMUL_CMPXCHG_FAILED;
4431
54bf36aa 4432 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4433 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4434
4435 return X86EMUL_CONTINUE;
4a5f48f6 4436
3200f405 4437emul_write:
daea3e73 4438 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4439
0f65dd70 4440 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4441}
4442
cf8f70bf
GN		 4443static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4444{
4445 /* TODO: String I/O for in kernel device */
4446 int r;
4447
4448 if (vcpu->arch.pio.in)
e32edf4f 4449 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4450 vcpu->arch.pio.size, pd);
4451 else
e32edf4f 4452 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4453 vcpu->arch.pio.port, vcpu->arch.pio.size,
4454 pd);
4455 return r;
4456}
4457
6f6fbe98
XG		 4458static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4459 unsigned short port, void *val,
4460 unsigned int count, bool in)
cf8f70bf 4461{
cf8f70bf 4462 vcpu->arch.pio.port = port;
6f6fbe98 4463 vcpu->arch.pio.in = in;
7972995b 4464 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4465 vcpu->arch.pio.size = size;
4466
4467 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4468 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4469 return 1;
4470 }
4471
4472 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4473 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4474 vcpu->run->io.size = size;
4475 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4476 vcpu->run->io.count = count;
4477 vcpu->run->io.port = port;
4478
4479 return 0;
4480}
4481
6f6fbe98
XG		 4482static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4483 int size, unsigned short port, void *val,
4484 unsigned int count)
cf8f70bf 4485{
ca1d4a9e 4486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4487 int ret;
ca1d4a9e 4488
6f6fbe98
XG		 4489 if (vcpu->arch.pio.count)
4490 goto data_avail;
cf8f70bf 4491
6f6fbe98
XG		 4492 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4493 if (ret) {
4494data_avail:
4495 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4496 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4497 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4498 return 1;
4499 }
4500
cf8f70bf
GN		 4501 return 0;
4502}
4503
6f6fbe98
XG		 4504static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4505 int size, unsigned short port,
4506 const void *val, unsigned int count)
4507{
4508 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4509
4510 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4511 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4512 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4513}
4514
bbd9b64e
CO		 4515static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4516{
4517 return kvm_x86_ops->get_segment_base(vcpu, seg);
4518}
4519
3cb16fe7 4520static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4521{
3cb16fe7 4522 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4523}
4524
5cb56059 4525int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4526{
4527 if (!need_emulate_wbinvd(vcpu))
4528 return X86EMUL_CONTINUE;
4529
4530 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4531 int cpu = get_cpu();
4532
4533 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4534 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4535 wbinvd_ipi, NULL, 1);
2eec7343 4536 put_cpu();
f5f48ee1 4537 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4538 } else
4539 wbinvd();
f5f48ee1
SY		 4540 return X86EMUL_CONTINUE;
4541}
5cb56059
JS		 4542
4543int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4544{
4545 kvm_x86_ops->skip_emulated_instruction(vcpu);
4546 return kvm_emulate_wbinvd_noskip(vcpu);
4547}
f5f48ee1
SY		 4548EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4549
5cb56059
JS		 4550
4551
bcaf5cc5
AK		 4552static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4553{
5cb56059 4554 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4555}
4556
52eb5a6d
XL		 4557static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4558 unsigned long *dest)
bbd9b64e 4559{
16f8a6f9 4560 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4561}
4562
52eb5a6d
XL		 4563static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4564 unsigned long value)
bbd9b64e 4565{
338dbc97 4566
717746e3 4567 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4568}
4569
52a46617 4570static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4571{
52a46617 4572 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4573}
4574
717746e3 4575static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4576{
717746e3 4577 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4578 unsigned long value;
4579
4580 switch (cr) {
4581 case 0:
4582 value = kvm_read_cr0(vcpu);
4583 break;
4584 case 2:
4585 value = vcpu->arch.cr2;
4586 break;
4587 case 3:
9f8fe504 4588 value = kvm_read_cr3(vcpu);
52a46617
GN		 4589 break;
4590 case 4:
4591 value = kvm_read_cr4(vcpu);
4592 break;
4593 case 8:
4594 value = kvm_get_cr8(vcpu);
4595 break;
4596 default:
a737f256 4597 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4598 return 0;
4599 }
4600
4601 return value;
4602}
4603
717746e3 4604static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4605{
717746e3 4606 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4607 int res = 0;
4608
52a46617
GN		 4609 switch (cr) {
4610 case 0:
49a9b07e 4611 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4612 break;
4613 case 2:
4614 vcpu->arch.cr2 = val;
4615 break;
4616 case 3:
2390218b 4617 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4618 break;
4619 case 4:
a83b29c6 4620 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4621 break;
4622 case 8:
eea1cff9 4623 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4624 break;
4625 default:
a737f256 4626 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4627 res = -1;
52a46617 4628 }
0f12244f
GN		 4629
4630 return res;
52a46617
GN		 4631}
4632
717746e3 4633static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4634{
717746e3 4635 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4636}
4637
4bff1e86 4638static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4639{
4bff1e86 4640 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4641}
4642
4bff1e86 4643static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4644{
4bff1e86 4645 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4646}
4647
1ac9d0cf
AK		 4648static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4649{
4650 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4651}
4652
4653static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4654{
4655 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4656}
4657
4bff1e86
AK		 4658static unsigned long emulator_get_cached_segment_base(
4659 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4660{
4bff1e86 4661 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4662}
4663
1aa36616
AK		 4664static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4665 struct desc_struct *desc, u32 *base3,
4666 int seg)
2dafc6c2
GN		 4667{
4668 struct kvm_segment var;
4669
4bff1e86 4670 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4671 *selector = var.selector;
2dafc6c2 4672
378a8b09
GN		 4673 if (var.unusable) {
4674 memset(desc, 0, sizeof(*desc));
2dafc6c2 4675 return false;
378a8b09 4676 }
2dafc6c2
GN		 4677
4678 if (var.g)
4679 var.limit >>= 12;
4680 set_desc_limit(desc, var.limit);
4681 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4682#ifdef CONFIG_X86_64
4683 if (base3)
4684 *base3 = var.base >> 32;
4685#endif
2dafc6c2
GN		 4686 desc->type = var.type;
4687 desc->s = var.s;
4688 desc->dpl = var.dpl;
4689 desc->p = var.present;
4690 desc->avl = var.avl;
4691 desc->l = var.l;
4692 desc->d = var.db;
4693 desc->g = var.g;
4694
4695 return true;
4696}
4697
1aa36616
AK		 4698static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4699 struct desc_struct *desc, u32 base3,
4700 int seg)
2dafc6c2 4701{
4bff1e86 4702 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4703 struct kvm_segment var;
4704
1aa36616 4705 var.selector = selector;
2dafc6c2 4706 var.base = get_desc_base(desc);
5601d05b
GN		 4707#ifdef CONFIG_X86_64
4708 var.base |= ((u64)base3) << 32;
4709#endif
2dafc6c2
GN		 4710 var.limit = get_desc_limit(desc);
4711 if (desc->g)
4712 var.limit = (var.limit << 12) | 0xfff;
4713 var.type = desc->type;
2dafc6c2
GN		 4714 var.dpl = desc->dpl;
4715 var.db = desc->d;
4716 var.s = desc->s;
4717 var.l = desc->l;
4718 var.g = desc->g;
4719 var.avl = desc->avl;
4720 var.present = desc->p;
4721 var.unusable = !var.present;
4722 var.padding = 0;
4723
4724 kvm_set_segment(vcpu, &var, seg);
4725 return;
4726}
4727
717746e3
AK		 4728static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4729 u32 msr_index, u64 *pdata)
4730{
609e36d3
PB		 4731 struct msr_data msr;
4732 int r;
4733
4734 msr.index = msr_index;
4735 msr.host_initiated = false;
4736 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4737 if (r)
4738 return r;
4739
4740 *pdata = msr.data;
4741 return 0;
717746e3
AK		 4742}
4743
4744static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4745 u32 msr_index, u64 data)
4746{
8fe8ab46
WA		 4747 struct msr_data msr;
4748
4749 msr.data = data;
4750 msr.index = msr_index;
4751 msr.host_initiated = false;
4752 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4753}
4754
64d60670
PB		 4755static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4756{
4757 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4758
4759 return vcpu->arch.smbase;
4760}
4761
4762static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4763{
4764 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4765
4766 vcpu->arch.smbase = smbase;
4767}
4768
67f4d428
NA		 4769static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4770 u32 pmc)
4771{
c6702c9d 4772 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4773}
4774
222d21aa
AK		 4775static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4776 u32 pmc, u64 *pdata)
4777{
c6702c9d 4778 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4779}
4780
6c3287f7
AK		 4781static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4782{
4783 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4784}
4785
5037f6f3
AK		 4786static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4787{
4788 preempt_disable();
5197b808 4789 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4790 /*
4791 * CR0.TS may reference the host fpu state, not the guest fpu state,
4792 * so it may be clear at this point.
4793 */
4794 clts();
4795}
4796
4797static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4798{
4799 preempt_enable();
4800}
4801
2953538e 4802static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4803 struct x86_instruction_info *info,
c4f035c6
AK		 4804 enum x86_intercept_stage stage)
4805{
2953538e 4806 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4807}
4808
0017f93a 4809static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4810 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4811{
0017f93a 4812 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4813}
4814
dd856efa
AK		 4815static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4816{
4817 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4818}
4819
4820static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4821{
4822 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4823}
4824
801806d9
NA		 4825static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4826{
4827 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4828}
4829
0225fb50 4830static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4831 .read_gpr = emulator_read_gpr,
4832 .write_gpr = emulator_write_gpr,
1871c602 4833 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4834 .write_std = kvm_write_guest_virt_system,
1871c602 4835 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4836 .read_emulated = emulator_read_emulated,
4837 .write_emulated = emulator_write_emulated,
4838 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4839 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4840 .pio_in_emulated = emulator_pio_in_emulated,
4841 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4842 .get_segment = emulator_get_segment,
4843 .set_segment = emulator_set_segment,
5951c442 4844 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4845 .get_gdt = emulator_get_gdt,
160ce1f1 4846 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4847 .set_gdt = emulator_set_gdt,
4848 .set_idt = emulator_set_idt,
52a46617
GN		 4849 .get_cr = emulator_get_cr,
4850 .set_cr = emulator_set_cr,
9c537244 4851 .cpl = emulator_get_cpl,
35aa5375
GN		 4852 .get_dr = emulator_get_dr,
4853 .set_dr = emulator_set_dr,
64d60670
PB		 4854 .get_smbase = emulator_get_smbase,
4855 .set_smbase = emulator_set_smbase,
717746e3
AK		 4856 .set_msr = emulator_set_msr,
4857 .get_msr = emulator_get_msr,
67f4d428 4858 .check_pmc = emulator_check_pmc,
222d21aa 4859 .read_pmc = emulator_read_pmc,
6c3287f7 4860 .halt = emulator_halt,
bcaf5cc5 4861 .wbinvd = emulator_wbinvd,
d6aa1000 4862 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4863 .get_fpu = emulator_get_fpu,
4864 .put_fpu = emulator_put_fpu,
c4f035c6 4865 .intercept = emulator_intercept,
bdb42f5a 4866 .get_cpuid = emulator_get_cpuid,
801806d9 4867 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4868};
4869
95cb2295
GN		 4870static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4871{
37ccdcbe 4872 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4873 /*
4874 * an sti; sti; sequence only disable interrupts for the first
4875 * instruction. So, if the last instruction, be it emulated or
4876 * not, left the system with the INT_STI flag enabled, it
4877 * means that the last instruction is an sti. We should not
4878 * leave the flag on in this case. The same goes for mov ss
4879 */
37ccdcbe
PB		 4880 if (int_shadow & mask)
4881 mask = 0;
6addfc42 4882 if (unlikely(int_shadow || mask)) {
95cb2295 4883 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4884 if (!mask)
4885 kvm_make_request(KVM_REQ_EVENT, vcpu);
4886 }
95cb2295
GN		 4887}
4888
ef54bcfe 4889static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4890{
4891 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4892 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4893 return kvm_propagate_fault(vcpu, &ctxt->exception);
4894
4895 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4896 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4897 ctxt->exception.error_code);
54b8486f 4898 else
da9cb575 4899 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4900 return false;
54b8486f
GN		 4901}
4902
8ec4722d
MG		 4903static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4904{
adf52235 4905 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4906 int cs_db, cs_l;
4907
8ec4722d
MG		 4908 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4909
adf52235
TY		 4910 ctxt->eflags = kvm_get_rflags(vcpu);
4911 ctxt->eip = kvm_rip_read(vcpu);
4912 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4913 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4914 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4915 cs_db ? X86EMUL_MODE_PROT32 :
4916 X86EMUL_MODE_PROT16;
a584539b 4917 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4918 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4919 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4920 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4921
dd856efa 4922 init_decode_cache(ctxt);
7ae441ea 4923 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4924}
4925
71f9833b 4926int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4927{
9d74191a 4928 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4929 int ret;
4930
4931 init_emulate_ctxt(vcpu);
4932
9dac77fa
AK		 4933 ctxt->op_bytes = 2;
4934 ctxt->ad_bytes = 2;
4935 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4936 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4937
4938 if (ret != X86EMUL_CONTINUE)
4939 return EMULATE_FAIL;
4940
9dac77fa 4941 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4942 kvm_rip_write(vcpu, ctxt->eip);
4943 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4944
4945 if (irq == NMI_VECTOR)
7460fb4a 4946 vcpu->arch.nmi_pending = 0;
63995653
MG		 4947 else
4948 vcpu->arch.interrupt.pending = false;
4949
4950 return EMULATE_DONE;
4951}
4952EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4953
6d77dbfc
GN		 4954static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4955{
fc3a9157
JR		 4956 int r = EMULATE_DONE;
4957
6d77dbfc
GN		 4958 ++vcpu->stat.insn_emulation_fail;
4959 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4960 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4961 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4962 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4963 vcpu->run->internal.ndata = 0;
4964 r = EMULATE_FAIL;
4965 }
6d77dbfc 4966 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4967
4968 return r;
6d77dbfc
GN		 4969}
4970
93c05d3e 4971static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4972 bool write_fault_to_shadow_pgtable,
4973 int emulation_type)
a6f177ef 4974{
95b3cf69 4975 gpa_t gpa = cr2;
8e3d9d06 4976 pfn_t pfn;
a6f177ef 4977
991eebf9
GN		 4978 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4979 return false;
4980
95b3cf69
XG		 4981 if (!vcpu->arch.mmu.direct_map) {
4982 /*
4983 * Write permission should be allowed since only
4984 * write access need to be emulated.
4985 */
4986 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4987
95b3cf69
XG		 4988 /*
4989 * If the mapping is invalid in guest, let cpu retry
4990 * it to generate fault.
4991 */
4992 if (gpa == UNMAPPED_GVA)
4993 return true;
4994 }
a6f177ef 4995
8e3d9d06
XG		 4996 /*
4997 * Do not retry the unhandleable instruction if it faults on the
4998 * readonly host memory, otherwise it will goto a infinite loop:
4999 * retry instruction -> write #PF -> emulation fail -> retry
5000 * instruction -> ...
5001 */
5002 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5003
5004 /*
5005 * If the instruction failed on the error pfn, it can not be fixed,
5006 * report the error to userspace.
5007 */
5008 if (is_error_noslot_pfn(pfn))
5009 return false;
5010
5011 kvm_release_pfn_clean(pfn);
5012
5013 /* The instructions are well-emulated on direct mmu. */
5014 if (vcpu->arch.mmu.direct_map) {
5015 unsigned int indirect_shadow_pages;
5016
5017 spin_lock(&vcpu->kvm->mmu_lock);
5018 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5019 spin_unlock(&vcpu->kvm->mmu_lock);
5020
5021 if (indirect_shadow_pages)
5022 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5023
a6f177ef 5024 return true;
8e3d9d06 5025 }
a6f177ef 5026
95b3cf69
XG		 5027 /*
5028 * if emulation was due to access to shadowed page table
5029 * and it failed try to unshadow page and re-enter the
5030 * guest to let CPU execute the instruction.
5031 */
5032 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5033
5034 /*
5035 * If the access faults on its page table, it can not
5036 * be fixed by unprotecting shadow page and it should
5037 * be reported to userspace.
5038 */
5039 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5040}
5041
1cb3f3ae
XG		 5042static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5043 unsigned long cr2, int emulation_type)
5044{
5045 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5046 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5047
5048 last_retry_eip = vcpu->arch.last_retry_eip;
5049 last_retry_addr = vcpu->arch.last_retry_addr;
5050
5051 /*
5052 * If the emulation is caused by #PF and it is non-page_table
5053 * writing instruction, it means the VM-EXIT is caused by shadow
5054 * page protected, we can zap the shadow page and retry this
5055 * instruction directly.
5056 *
5057 * Note: if the guest uses a non-page-table modifying instruction
5058 * on the PDE that points to the instruction, then we will unmap
5059 * the instruction and go to an infinite loop. So, we cache the
5060 * last retried eip and the last fault address, if we meet the eip
5061 * and the address again, we can break out of the potential infinite
5062 * loop.
5063 */
5064 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5065
5066 if (!(emulation_type & EMULTYPE_RETRY))
5067 return false;
5068
5069 if (x86_page_table_writing_insn(ctxt))
5070 return false;
5071
5072 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5073 return false;
5074
5075 vcpu->arch.last_retry_eip = ctxt->eip;
5076 vcpu->arch.last_retry_addr = cr2;
5077
5078 if (!vcpu->arch.mmu.direct_map)
5079 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5080
22368028 5081 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5082
5083 return true;
5084}
5085
716d51ab
GN		 5086static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5087static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5088
64d60670 5089static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5090{
64d60670 5091 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5092 /* This is a good place to trace that we are exiting SMM. */
5093 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5094
64d60670
PB		 5095 if (unlikely(vcpu->arch.smi_pending)) {
5096 kvm_make_request(KVM_REQ_SMI, vcpu);
5097 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5098 } else {
5099 /* Process a latched INIT, if any. */
5100 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5101 }
5102 }
699023e2
PB		 5103
5104 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5105}
5106
5107static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5108{
5109 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5110
a584539b 5111 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5112
5113 if (changed & HF_SMM_MASK)
5114 kvm_smm_changed(vcpu);
a584539b
PB		 5115}
5116
4a1e10d5
PB		 5117static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5118 unsigned long *db)
5119{
5120 u32 dr6 = 0;
5121 int i;
5122 u32 enable, rwlen;
5123
5124 enable = dr7;
5125 rwlen = dr7 >> 16;
5126 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5127 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5128 dr6 |= (1 << i);
5129 return dr6;
5130}
5131
6addfc42 5132static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5133{
5134 struct kvm_run *kvm_run = vcpu->run;
5135
5136 /*
6addfc42
PB		 5137 * rflags is the old, "raw" value of the flags. The new value has
5138 * not been saved yet.
663f4c61
PB		 5139 *
5140 * This is correct even for TF set by the guest, because "the
5141 * processor will not generate this exception after the instruction
5142 * that sets the TF flag".
5143 */
663f4c61
PB		 5144 if (unlikely(rflags & X86_EFLAGS_TF)) {
5145 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5146 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5147 DR6_RTM;
663f4c61
PB		 5148 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5149 kvm_run->debug.arch.exception = DB_VECTOR;
5150 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5151 *r = EMULATE_USER_EXIT;
5152 } else {
5153 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5154 /*
5155 * "Certain debug exceptions may clear bit 0-3. The
5156 * remaining contents of the DR6 register are never
5157 * cleared by the processor".
5158 */
5159 vcpu->arch.dr6 &= ~15;
6f43ed01 5160 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5161 kvm_queue_exception(vcpu, DB_VECTOR);
5162 }
5163 }
5164}
5165
4a1e10d5
PB		 5166static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5167{
4a1e10d5
PB		 5168 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5169 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5170 struct kvm_run *kvm_run = vcpu->run;
5171 unsigned long eip = kvm_get_linear_rip(vcpu);
5172 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5173 vcpu->arch.guest_debug_dr7,
5174 vcpu->arch.eff_db);
5175
5176 if (dr6 != 0) {
6f43ed01 5177 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5178 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5179 kvm_run->debug.arch.exception = DB_VECTOR;
5180 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5181 *r = EMULATE_USER_EXIT;
5182 return true;
5183 }
5184 }
5185
4161a569
NA		 5186 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5187 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5188 unsigned long eip = kvm_get_linear_rip(vcpu);
5189 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5190 vcpu->arch.dr7,
5191 vcpu->arch.db);
5192
5193 if (dr6 != 0) {
5194 vcpu->arch.dr6 &= ~15;
6f43ed01 5195 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5196 kvm_queue_exception(vcpu, DB_VECTOR);
5197 *r = EMULATE_DONE;
5198 return true;
5199 }
5200 }
5201
5202 return false;
5203}
5204
51d8b661
AP		 5205int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5206 unsigned long cr2,
dc25e89e
AP		 5207 int emulation_type,
5208 void *insn,
5209 int insn_len)
bbd9b64e 5210{
95cb2295 5211 int r;
9d74191a 5212 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5213 bool writeback = true;
93c05d3e 5214 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5215
93c05d3e
XG		 5216 /*
5217 * Clear write_fault_to_shadow_pgtable here to ensure it is
5218 * never reused.
5219 */
5220 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5221 kvm_clear_exception_queue(vcpu);
8d7d8102 5222
571008da 5223 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5224 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5225
5226 /*
5227 * We will reenter on the same instruction since
5228 * we do not set complete_userspace_io. This does not
5229 * handle watchpoints yet, those would be handled in
5230 * the emulate_ops.
5231 */
5232 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5233 return r;
5234
9d74191a
TY		 5235 ctxt->interruptibility = 0;
5236 ctxt->have_exception = false;
e0ad0b47 5237 ctxt->exception.vector = -1;
9d74191a 5238 ctxt->perm_ok = false;
bbd9b64e 5239
b51e974f 5240 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5241
9d74191a 5242 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5243
e46479f8 5244 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5245 ++vcpu->stat.insn_emulation;
1d2887e2 5246 if (r != EMULATION_OK) {
4005996e
AK		 5247 if (emulation_type & EMULTYPE_TRAP_UD)
5248 return EMULATE_FAIL;
991eebf9
GN		 5249 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5250 emulation_type))
bbd9b64e 5251 return EMULATE_DONE;
6d77dbfc
GN		 5252 if (emulation_type & EMULTYPE_SKIP)
5253 return EMULATE_FAIL;
5254 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5255 }
5256 }
5257
ba8afb6b 5258 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5259 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5260 if (ctxt->eflags & X86_EFLAGS_RF)
5261 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5262 return EMULATE_DONE;
5263 }
5264
1cb3f3ae
XG		 5265 if (retry_instruction(ctxt, cr2, emulation_type))
5266 return EMULATE_DONE;
5267
7ae441ea 5268 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5269 changes registers values during IO operation */
7ae441ea
GN		 5270 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5271 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5272 emulator_invalidate_register_cache(ctxt);
7ae441ea 5273 }
4d2179e1 5274
5cd21917 5275restart:
9d74191a 5276 r = x86_emulate_insn(ctxt);
bbd9b64e 5277
775fde86
JR		 5278 if (r == EMULATION_INTERCEPTED)
5279 return EMULATE_DONE;
5280
d2ddd1c4 5281 if (r == EMULATION_FAILED) {
991eebf9
GN		 5282 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5283 emulation_type))
c3cd7ffa
GN		 5284 return EMULATE_DONE;
5285
6d77dbfc 5286 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5287 }
5288
9d74191a 5289 if (ctxt->have_exception) {
d2ddd1c4 5290 r = EMULATE_DONE;
ef54bcfe
PB		 5291 if (inject_emulated_exception(vcpu))
5292 return r;
d2ddd1c4 5293 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5294 if (!vcpu->arch.pio.in) {
5295 /* FIXME: return into emulator if single-stepping. */
3457e419 5296 vcpu->arch.pio.count = 0;
0912c977 5297 } else {
7ae441ea 5298 writeback = false;
716d51ab
GN		 5299 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5300 }
ac0a48c3 5301 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5302 } else if (vcpu->mmio_needed) {
5303 if (!vcpu->mmio_is_write)
5304 writeback = false;
ac0a48c3 5305 r = EMULATE_USER_EXIT;
716d51ab 5306 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5307 } else if (r == EMULATION_RESTART)
5cd21917 5308 goto restart;
d2ddd1c4
GN		 5309 else
5310 r = EMULATE_DONE;
f850e2e6 5311
7ae441ea 5312 if (writeback) {
6addfc42 5313 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5314 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5315 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5316 if (vcpu->arch.hflags != ctxt->emul_flags)
5317 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5318 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5319 if (r == EMULATE_DONE)
6addfc42 5320 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5321 if (!ctxt->have_exception ||
5322 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5323 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5324
5325 /*
5326 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5327 * do nothing, and it will be requested again as soon as
5328 * the shadow expires. But we still need to check here,
5329 * because POPF has no interrupt shadow.
5330 */
5331 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5332 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5333 } else
5334 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5335
5336 return r;
de7d789a 5337}
51d8b661 5338EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5339
cf8f70bf 5340int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5341{
cf8f70bf 5342 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5343 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5344 size, port, &val, 1);
cf8f70bf 5345 /* do not return to emulator after return from userspace */
7972995b 5346 vcpu->arch.pio.count = 0;
de7d789a
CO		 5347 return ret;
5348}
cf8f70bf 5349EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5350
8cfdc000
ZA		 5351static void tsc_bad(void *info)
5352{
0a3aee0d 5353 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5354}
5355
5356static void tsc_khz_changed(void *data)
c8076604 5357{
8cfdc000
ZA		 5358 struct cpufreq_freqs *freq = data;
5359 unsigned long khz = 0;
5360
5361 if (data)
5362 khz = freq->new;
5363 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5364 khz = cpufreq_quick_get(raw_smp_processor_id());
5365 if (!khz)
5366 khz = tsc_khz;
0a3aee0d 5367 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5368}
5369
c8076604
GH		 5370static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5371 void *data)
5372{
5373 struct cpufreq_freqs *freq = data;
5374 struct kvm *kvm;
5375 struct kvm_vcpu *vcpu;
5376 int i, send_ipi = 0;
5377
8cfdc000
ZA		 5378 /*
5379 * We allow guests to temporarily run on slowing clocks,
5380 * provided we notify them after, or to run on accelerating
5381 * clocks, provided we notify them before. Thus time never
5382 * goes backwards.
5383 *
5384 * However, we have a problem. We can't atomically update
5385 * the frequency of a given CPU from this function; it is
5386 * merely a notifier, which can be called from any CPU.
5387 * Changing the TSC frequency at arbitrary points in time
5388 * requires a recomputation of local variables related to
5389 * the TSC for each VCPU. We must flag these local variables
5390 * to be updated and be sure the update takes place with the
5391 * new frequency before any guests proceed.
5392 *
5393 * Unfortunately, the combination of hotplug CPU and frequency
5394 * change creates an intractable locking scenario; the order
5395 * of when these callouts happen is undefined with respect to
5396 * CPU hotplug, and they can race with each other. As such,
5397 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5398 * undefined; you can actually have a CPU frequency change take
5399 * place in between the computation of X and the setting of the
5400 * variable. To protect against this problem, all updates of
5401 * the per_cpu tsc_khz variable are done in an interrupt
5402 * protected IPI, and all callers wishing to update the value
5403 * must wait for a synchronous IPI to complete (which is trivial
5404 * if the caller is on the CPU already). This establishes the
5405 * necessary total order on variable updates.
5406 *
5407 * Note that because a guest time update may take place
5408 * anytime after the setting of the VCPU's request bit, the
5409 * correct TSC value must be set before the request. However,
5410 * to ensure the update actually makes it to any guest which
5411 * starts running in hardware virtualization between the set
5412 * and the acquisition of the spinlock, we must also ping the
5413 * CPU after setting the request bit.
5414 *
5415 */
5416
c8076604
GH		 5417 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5418 return 0;
5419 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5420 return 0;
8cfdc000
ZA		 5421
5422 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5423
2f303b74 5424 spin_lock(&kvm_lock);
c8076604 5425 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5426 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5427 if (vcpu->cpu != freq->cpu)
5428 continue;
c285545f 5429 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5430 if (vcpu->cpu != smp_processor_id())
8cfdc000 5431 send_ipi = 1;
c8076604
GH		 5432 }
5433 }
2f303b74 5434 spin_unlock(&kvm_lock);
c8076604
GH		 5435
5436 if (freq->old < freq->new && send_ipi) {
5437 /*
5438 * We upscale the frequency. Must make the guest
5439 * doesn't see old kvmclock values while running with
5440 * the new frequency, otherwise we risk the guest sees
5441 * time go backwards.
5442 *
5443 * In case we update the frequency for another cpu
5444 * (which might be in guest context) send an interrupt
5445 * to kick the cpu out of guest context. Next time
5446 * guest context is entered kvmclock will be updated,
5447 * so the guest will not see stale values.
5448 */
8cfdc000 5449 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5450 }
5451 return 0;
5452}
5453
5454static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5455 .notifier_call = kvmclock_cpufreq_notifier
5456};
5457
5458static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5459 unsigned long action, void *hcpu)
5460{
5461 unsigned int cpu = (unsigned long)hcpu;
5462
5463 switch (action) {
5464 case CPU_ONLINE:
5465 case CPU_DOWN_FAILED:
5466 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5467 break;
5468 case CPU_DOWN_PREPARE:
5469 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5470 break;
5471 }
5472 return NOTIFY_OK;
5473}
5474
5475static struct notifier_block kvmclock_cpu_notifier_block = {
5476 .notifier_call = kvmclock_cpu_notifier,
5477 .priority = -INT_MAX
c8076604
GH		 5478};
5479
b820cc0c
ZA		 5480static void kvm_timer_init(void)
5481{
5482 int cpu;
5483
c285545f 5484 max_tsc_khz = tsc_khz;
460dd42e
SB		 5485
5486 cpu_notifier_register_begin();
b820cc0c 5487 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5488#ifdef CONFIG_CPU_FREQ
5489 struct cpufreq_policy policy;
5490 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5491 cpu = get_cpu();
5492 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5493 if (policy.cpuinfo.max_freq)
5494 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5495 put_cpu();
c285545f 5496#endif
b820cc0c
ZA		 5497 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5498 CPUFREQ_TRANSITION_NOTIFIER);
5499 }
c285545f 5500 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5501 for_each_online_cpu(cpu)
5502 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5503
5504 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5505 cpu_notifier_register_done();
5506
b820cc0c
ZA		 5507}
5508
ff9d07a0
ZY		 5509static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5510
f5132b01 5511int kvm_is_in_guest(void)
ff9d07a0 5512{
086c9855 5513 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5514}
5515
5516static int kvm_is_user_mode(void)
5517{
5518 int user_mode = 3;
dcf46b94 5519
086c9855
AS		 5520 if (__this_cpu_read(current_vcpu))
5521 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5522
ff9d07a0
ZY		 5523 return user_mode != 0;
5524}
5525
5526static unsigned long kvm_get_guest_ip(void)
5527{
5528 unsigned long ip = 0;
dcf46b94 5529
086c9855
AS		 5530 if (__this_cpu_read(current_vcpu))
5531 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5532
ff9d07a0
ZY		 5533 return ip;
5534}
5535
5536static struct perf_guest_info_callbacks kvm_guest_cbs = {
5537 .is_in_guest = kvm_is_in_guest,
5538 .is_user_mode = kvm_is_user_mode,
5539 .get_guest_ip = kvm_get_guest_ip,
5540};
5541
5542void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5543{
086c9855 5544 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5545}
5546EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5547
5548void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5549{
086c9855 5550 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5551}
5552EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5553
ce88decf
XG		 5554static void kvm_set_mmio_spte_mask(void)
5555{
5556 u64 mask;
5557 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5558
5559 /*
5560 * Set the reserved bits and the present bit of an paging-structure
5561 * entry to generate page fault with PFER.RSV = 1.
5562 */
885032b9 5563 /* Mask the reserved physical address bits. */
d1431483 5564 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5565
5566 /* Bit 62 is always reserved for 32bit host. */
5567 mask |= 0x3ull << 62;
5568
5569 /* Set the present bit. */
ce88decf
XG		 5570 mask |= 1ull;
5571
5572#ifdef CONFIG_X86_64
5573 /*
5574 * If reserved bit is not supported, clear the present bit to disable
5575 * mmio page fault.
5576 */
5577 if (maxphyaddr == 52)
5578 mask &= ~1ull;
5579#endif
5580
5581 kvm_mmu_set_mmio_spte_mask(mask);
5582}
5583
16e8d74d
MT		 5584#ifdef CONFIG_X86_64
5585static void pvclock_gtod_update_fn(struct work_struct *work)
5586{
d828199e
MT		 5587 struct kvm *kvm;
5588
5589 struct kvm_vcpu *vcpu;
5590 int i;
5591
2f303b74 5592 spin_lock(&kvm_lock);
d828199e
MT		 5593 list_for_each_entry(kvm, &vm_list, vm_list)
5594 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5595 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5596 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5597 spin_unlock(&kvm_lock);
16e8d74d
MT		 5598}
5599
5600static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5601
5602/*
5603 * Notification about pvclock gtod data update.
5604 */
5605static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5606 void *priv)
5607{
5608 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5609 struct timekeeper *tk = priv;
5610
5611 update_pvclock_gtod(tk);
5612
5613 /* disable master clock if host does not trust, or does not
5614 * use, TSC clocksource
5615 */
5616 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5617 atomic_read(&kvm_guest_has_master_clock) != 0)
5618 queue_work(system_long_wq, &pvclock_gtod_work);
5619
5620 return 0;
5621}
5622
5623static struct notifier_block pvclock_gtod_notifier = {
5624 .notifier_call = pvclock_gtod_notify,
5625};
5626#endif
5627
f8c16bba 5628int kvm_arch_init(void *opaque)
043405e1 5629{
b820cc0c 5630 int r;
6b61edf7 5631 struct kvm_x86_ops *ops = opaque;
f8c16bba 5632
f8c16bba
ZX		 5633 if (kvm_x86_ops) {
5634 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5635 r = -EEXIST;
5636 goto out;
f8c16bba
ZX		 5637 }
5638
5639 if (!ops->cpu_has_kvm_support()) {
5640 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5641 r = -EOPNOTSUPP;
5642 goto out;
f8c16bba
ZX		 5643 }
5644 if (ops->disabled_by_bios()) {
5645 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5646 r = -EOPNOTSUPP;
5647 goto out;
f8c16bba
ZX		 5648 }
5649
013f6a5d
MT		 5650 r = -ENOMEM;
5651 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5652 if (!shared_msrs) {
5653 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5654 goto out;
5655 }
5656
97db56ce
AK		 5657 r = kvm_mmu_module_init();
5658 if (r)
013f6a5d 5659 goto out_free_percpu;
97db56ce 5660
ce88decf 5661 kvm_set_mmio_spte_mask();
97db56ce 5662
f8c16bba 5663 kvm_x86_ops = ops;
920c8377 5664
7b52345e 5665 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5666 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5667
b820cc0c 5668 kvm_timer_init();
c8076604 5669
ff9d07a0
ZY		 5670 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5671
2acf923e
DC		 5672 if (cpu_has_xsave)
5673 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5674
c5cc421b 5675 kvm_lapic_init();
16e8d74d
MT		 5676#ifdef CONFIG_X86_64
5677 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5678#endif
5679
f8c16bba 5680 return 0;
56c6d28a 5681
013f6a5d
MT		 5682out_free_percpu:
5683 free_percpu(shared_msrs);
56c6d28a 5684out:
56c6d28a 5685 return r;
043405e1 5686}
8776e519 5687
f8c16bba
ZX		 5688void kvm_arch_exit(void)
5689{
ff9d07a0
ZY		 5690 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5691
888d256e
JK		 5692 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5693 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5694 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5695 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5696#ifdef CONFIG_X86_64
5697 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5698#endif
f8c16bba 5699 kvm_x86_ops = NULL;
56c6d28a 5700 kvm_mmu_module_exit();
013f6a5d 5701 free_percpu(shared_msrs);
56c6d28a 5702}
f8c16bba 5703
5cb56059 5704int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5705{
5706 ++vcpu->stat.halt_exits;
35754c98 5707 if (lapic_in_kernel(vcpu)) {
a4535290 5708 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5709 return 1;
5710 } else {
5711 vcpu->run->exit_reason = KVM_EXIT_HLT;
5712 return 0;
5713 }
5714}
5cb56059
JS		 5715EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5716
5717int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5718{
5719 kvm_x86_ops->skip_emulated_instruction(vcpu);
5720 return kvm_vcpu_halt(vcpu);
5721}
8776e519
HB		 5722EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5723
6aef266c
SV		 5724/*
5725 * kvm_pv_kick_cpu_op: Kick a vcpu.
5726 *
5727 * @apicid - apicid of vcpu to be kicked.
5728 */
5729static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5730{
24d2166b 5731 struct kvm_lapic_irq lapic_irq;
6aef266c 5732
24d2166b
R		 5733 lapic_irq.shorthand = 0;
5734 lapic_irq.dest_mode = 0;
5735 lapic_irq.dest_id = apicid;
93bbf0b8 5736 lapic_irq.msi_redir_hint = false;
6aef266c 5737
24d2166b 5738 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5739 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5740}
5741
8776e519
HB		 5742int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5743{
5744 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5745 int op_64_bit, r = 1;
8776e519 5746
5cb56059
JS		 5747 kvm_x86_ops->skip_emulated_instruction(vcpu);
5748
55cd8e5a
GN		 5749 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5750 return kvm_hv_hypercall(vcpu);
5751
5fdbf976
MT		 5752 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5753 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5754 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5755 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5756 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5757
229456fc 5758 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5759
a449c7aa
NA		 5760 op_64_bit = is_64_bit_mode(vcpu);
5761 if (!op_64_bit) {
8776e519
HB		 5762 nr &= 0xFFFFFFFF;
5763 a0 &= 0xFFFFFFFF;
5764 a1 &= 0xFFFFFFFF;
5765 a2 &= 0xFFFFFFFF;
5766 a3 &= 0xFFFFFFFF;
5767 }
5768
07708c4a
JK		 5769 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5770 ret = -KVM_EPERM;
5771 goto out;
5772 }
5773
8776e519 5774 switch (nr) {
b93463aa
AK		 5775 case KVM_HC_VAPIC_POLL_IRQ:
5776 ret = 0;
5777 break;
6aef266c
SV		 5778 case KVM_HC_KICK_CPU:
5779 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5780 ret = 0;
5781 break;
8776e519
HB		 5782 default:
5783 ret = -KVM_ENOSYS;
5784 break;
5785 }
07708c4a 5786out:
a449c7aa
NA		 5787 if (!op_64_bit)
5788 ret = (u32)ret;
5fdbf976 5789 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5790 ++vcpu->stat.hypercalls;
2f333bcb 5791 return r;
8776e519
HB		 5792}
5793EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5794
b6785def 5795static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5796{
d6aa1000 5797 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5798 char instruction[3];
5fdbf976 5799 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5800
8776e519 5801 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5802
9d74191a 5803 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5804}
5805
b6c7a5dc
HB		 5806/*
5807 * Check if userspace requested an interrupt window, and that the
5808 * interrupt window is open.
5809 *
5810 * No need to exit to userspace if we already have an interrupt queued.
5811 */
851ba692 5812static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5813{
1c1a9ce9
SR		 5814 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5815 return false;
5816
5817 if (kvm_cpu_has_interrupt(vcpu))
5818 return false;
5819
5820 return (irqchip_split(vcpu->kvm)
5821 ? kvm_apic_accept_pic_intr(vcpu)
5822 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5823}
5824
851ba692 5825static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5826{
851ba692
AK		 5827 struct kvm_run *kvm_run = vcpu->run;
5828
91586a3b 5829 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5830 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5831 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5832 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5833 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5834 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5835 kvm_arch_interrupt_allowed(vcpu) &&
5836 !kvm_cpu_has_interrupt(vcpu) &&
5837 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5838 else if (!pic_in_kernel(vcpu->kvm))
5839 kvm_run->ready_for_interrupt_injection =
5840 kvm_apic_accept_pic_intr(vcpu) &&
5841 !kvm_cpu_has_interrupt(vcpu);
5842 else
5843 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5844}
5845
95ba8273
GN		 5846static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5847{
5848 int max_irr, tpr;
5849
5850 if (!kvm_x86_ops->update_cr8_intercept)
5851 return;
5852
88c808fd
AK		 5853 if (!vcpu->arch.apic)
5854 return;
5855
8db3baa2
GN		 5856 if (!vcpu->arch.apic->vapic_addr)
5857 max_irr = kvm_lapic_find_highest_irr(vcpu);
5858 else
5859 max_irr = -1;
95ba8273
GN		 5860
5861 if (max_irr != -1)
5862 max_irr >>= 4;
5863
5864 tpr = kvm_lapic_get_cr8(vcpu);
5865
5866 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5867}
5868
b6b8a145 5869static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5870{
b6b8a145
JK		 5871 int r;
5872
95ba8273 5873 /* try to reinject previous events if any */
b59bb7bd 5874 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5875 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5876 vcpu->arch.exception.has_error_code,
5877 vcpu->arch.exception.error_code);
d6e8c854
NA		 5878
5879 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5880 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5881 X86_EFLAGS_RF);
5882
6bdf0662
NA		 5883 if (vcpu->arch.exception.nr == DB_VECTOR &&
5884 (vcpu->arch.dr7 & DR7_GD)) {
5885 vcpu->arch.dr7 &= ~DR7_GD;
5886 kvm_update_dr7(vcpu);
5887 }
5888
b59bb7bd
GN		 5889 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5890 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5891 vcpu->arch.exception.error_code,
5892 vcpu->arch.exception.reinject);
b6b8a145 5893 return 0;
b59bb7bd
GN		 5894 }
5895
95ba8273
GN		 5896 if (vcpu->arch.nmi_injected) {
5897 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5898 return 0;
95ba8273
GN		 5899 }
5900
5901 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5902 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5903 return 0;
5904 }
5905
5906 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5907 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5908 if (r != 0)
5909 return r;
95ba8273
GN		 5910 }
5911
5912 /* try to inject new event if pending */
5913 if (vcpu->arch.nmi_pending) {
5914 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5915 --vcpu->arch.nmi_pending;
95ba8273
GN		 5916 vcpu->arch.nmi_injected = true;
5917 kvm_x86_ops->set_nmi(vcpu);
5918 }
c7c9c56c 5919 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5920 /*
5921 * Because interrupts can be injected asynchronously, we are
5922 * calling check_nested_events again here to avoid a race condition.
5923 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5924 * proposal and current concerns. Perhaps we should be setting
5925 * KVM_REQ_EVENT only on certain events and not unconditionally?
5926 */
5927 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5928 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5929 if (r != 0)
5930 return r;
5931 }
95ba8273 5932 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5933 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5934 false);
5935 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5936 }
5937 }
b6b8a145 5938 return 0;
95ba8273
GN		 5939}
5940
7460fb4a
AK		 5941static void process_nmi(struct kvm_vcpu *vcpu)
5942{
5943 unsigned limit = 2;
5944
5945 /*
5946 * x86 is limited to one NMI running, and one NMI pending after it.
5947 * If an NMI is already in progress, limit further NMIs to just one.
5948 * Otherwise, allow two (and we'll inject the first one immediately).
5949 */
5950 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5951 limit = 1;
5952
5953 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5954 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5955 kvm_make_request(KVM_REQ_EVENT, vcpu);
5956}
5957
660a5d51
PB		 5958#define put_smstate(type, buf, offset, val) \
5959 *(type *)((buf) + (offset) - 0x7e00) = val
5960
5961static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5962{
5963 u32 flags = 0;
5964 flags |= seg->g << 23;
5965 flags |= seg->db << 22;
5966 flags |= seg->l << 21;
5967 flags |= seg->avl << 20;
5968 flags |= seg->present << 15;
5969 flags |= seg->dpl << 13;
5970 flags |= seg->s << 12;
5971 flags |= seg->type << 8;
5972 return flags;
5973}
5974
5975static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5976{
5977 struct kvm_segment seg;
5978 int offset;
5979
5980 kvm_get_segment(vcpu, &seg, n);
5981 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5982
5983 if (n < 3)
5984 offset = 0x7f84 + n * 12;
5985 else
5986 offset = 0x7f2c + (n - 3) * 12;
5987
5988 put_smstate(u32, buf, offset + 8, seg.base);
5989 put_smstate(u32, buf, offset + 4, seg.limit);
5990 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5991}
5992
efbb288a 5993#ifdef CONFIG_X86_64
660a5d51
PB		 5994static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5995{
5996 struct kvm_segment seg;
5997 int offset;
5998 u16 flags;
5999
6000 kvm_get_segment(vcpu, &seg, n);
6001 offset = 0x7e00 + n * 16;
6002
6003 flags = process_smi_get_segment_flags(&seg) >> 8;
6004 put_smstate(u16, buf, offset, seg.selector);
6005 put_smstate(u16, buf, offset + 2, flags);
6006 put_smstate(u32, buf, offset + 4, seg.limit);
6007 put_smstate(u64, buf, offset + 8, seg.base);
6008}
efbb288a 6009#endif
660a5d51
PB		 6010
6011static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6012{
6013 struct desc_ptr dt;
6014 struct kvm_segment seg;
6015 unsigned long val;
6016 int i;
6017
6018 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6019 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6020 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6021 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6022
6023 for (i = 0; i < 8; i++)
6024 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6025
6026 kvm_get_dr(vcpu, 6, &val);
6027 put_smstate(u32, buf, 0x7fcc, (u32)val);
6028 kvm_get_dr(vcpu, 7, &val);
6029 put_smstate(u32, buf, 0x7fc8, (u32)val);
6030
6031 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6032 put_smstate(u32, buf, 0x7fc4, seg.selector);
6033 put_smstate(u32, buf, 0x7f64, seg.base);
6034 put_smstate(u32, buf, 0x7f60, seg.limit);
6035 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6036
6037 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6038 put_smstate(u32, buf, 0x7fc0, seg.selector);
6039 put_smstate(u32, buf, 0x7f80, seg.base);
6040 put_smstate(u32, buf, 0x7f7c, seg.limit);
6041 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6042
6043 kvm_x86_ops->get_gdt(vcpu, &dt);
6044 put_smstate(u32, buf, 0x7f74, dt.address);
6045 put_smstate(u32, buf, 0x7f70, dt.size);
6046
6047 kvm_x86_ops->get_idt(vcpu, &dt);
6048 put_smstate(u32, buf, 0x7f58, dt.address);
6049 put_smstate(u32, buf, 0x7f54, dt.size);
6050
6051 for (i = 0; i < 6; i++)
6052 process_smi_save_seg_32(vcpu, buf, i);
6053
6054 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6055
6056 /* revision id */
6057 put_smstate(u32, buf, 0x7efc, 0x00020000);
6058 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6059}
6060
6061static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6062{
6063#ifdef CONFIG_X86_64
6064 struct desc_ptr dt;
6065 struct kvm_segment seg;
6066 unsigned long val;
6067 int i;
6068
6069 for (i = 0; i < 16; i++)
6070 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6071
6072 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6073 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6074
6075 kvm_get_dr(vcpu, 6, &val);
6076 put_smstate(u64, buf, 0x7f68, val);
6077 kvm_get_dr(vcpu, 7, &val);
6078 put_smstate(u64, buf, 0x7f60, val);
6079
6080 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6081 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6082 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6083
6084 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6085
6086 /* revision id */
6087 put_smstate(u32, buf, 0x7efc, 0x00020064);
6088
6089 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6090
6091 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6092 put_smstate(u16, buf, 0x7e90, seg.selector);
6093 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6094 put_smstate(u32, buf, 0x7e94, seg.limit);
6095 put_smstate(u64, buf, 0x7e98, seg.base);
6096
6097 kvm_x86_ops->get_idt(vcpu, &dt);
6098 put_smstate(u32, buf, 0x7e84, dt.size);
6099 put_smstate(u64, buf, 0x7e88, dt.address);
6100
6101 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6102 put_smstate(u16, buf, 0x7e70, seg.selector);
6103 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6104 put_smstate(u32, buf, 0x7e74, seg.limit);
6105 put_smstate(u64, buf, 0x7e78, seg.base);
6106
6107 kvm_x86_ops->get_gdt(vcpu, &dt);
6108 put_smstate(u32, buf, 0x7e64, dt.size);
6109 put_smstate(u64, buf, 0x7e68, dt.address);
6110
6111 for (i = 0; i < 6; i++)
6112 process_smi_save_seg_64(vcpu, buf, i);
6113#else
6114 WARN_ON_ONCE(1);
6115#endif
6116}
6117
64d60670
PB		 6118static void process_smi(struct kvm_vcpu *vcpu)
6119{
660a5d51 6120 struct kvm_segment cs, ds;
18c3626e 6121 struct desc_ptr dt;
660a5d51
PB		 6122 char buf[512];
6123 u32 cr0;
6124
64d60670
PB		 6125 if (is_smm(vcpu)) {
6126 vcpu->arch.smi_pending = true;
6127 return;
6128 }
6129
660a5d51
PB		 6130 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6131 vcpu->arch.hflags |= HF_SMM_MASK;
6132 memset(buf, 0, 512);
6133 if (guest_cpuid_has_longmode(vcpu))
6134 process_smi_save_state_64(vcpu, buf);
6135 else
6136 process_smi_save_state_32(vcpu, buf);
6137
54bf36aa 6138 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6139
6140 if (kvm_x86_ops->get_nmi_mask(vcpu))
6141 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6142 else
6143 kvm_x86_ops->set_nmi_mask(vcpu, true);
6144
6145 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6146 kvm_rip_write(vcpu, 0x8000);
6147
6148 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6149 kvm_x86_ops->set_cr0(vcpu, cr0);
6150 vcpu->arch.cr0 = cr0;
6151
6152 kvm_x86_ops->set_cr4(vcpu, 0);
6153
18c3626e
PB		 6154 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6155 dt.address = dt.size = 0;
6156 kvm_x86_ops->set_idt(vcpu, &dt);
6157
660a5d51
PB		 6158 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6159
6160 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6161 cs.base = vcpu->arch.smbase;
6162
6163 ds.selector = 0;
6164 ds.base = 0;
6165
6166 cs.limit = ds.limit = 0xffffffff;
6167 cs.type = ds.type = 0x3;
6168 cs.dpl = ds.dpl = 0;
6169 cs.db = ds.db = 0;
6170 cs.s = ds.s = 1;
6171 cs.l = ds.l = 0;
6172 cs.g = ds.g = 1;
6173 cs.avl = ds.avl = 0;
6174 cs.present = ds.present = 1;
6175 cs.unusable = ds.unusable = 0;
6176 cs.padding = ds.padding = 0;
6177
6178 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6179 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6180 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6181 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6182 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6183 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6184
6185 if (guest_cpuid_has_longmode(vcpu))
6186 kvm_x86_ops->set_efer(vcpu, 0);
6187
6188 kvm_update_cpuid(vcpu);
6189 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6190}
6191
3d81bc7e 6192static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6193{
3d81bc7e
YZ		 6194 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6195 return;
c7c9c56c 6196
3bb345f3 6197 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6198
b053b2ae
SR		 6199 if (irqchip_split(vcpu->kvm))
6200 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6201 else
6202 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
3bb345f3 6203 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6204}
6205
a70656b6
RK		 6206static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6207{
6208 ++vcpu->stat.tlb_flush;
6209 kvm_x86_ops->tlb_flush(vcpu);
6210}
6211
4256f43f
TC		 6212void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6213{
c24ae0dc
TC		 6214 struct page *page = NULL;
6215
35754c98 6216 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6217 return;
6218
4256f43f
TC		 6219 if (!kvm_x86_ops->set_apic_access_page_addr)
6220 return;
6221
c24ae0dc 6222 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6223 if (is_error_page(page))
6224 return;
c24ae0dc
TC		 6225 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6226
6227 /*
6228 * Do not pin apic access page in memory, the MMU notifier
6229 * will call us again if it is migrated or swapped out.
6230 */
6231 put_page(page);
4256f43f
TC		 6232}
6233EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6234
fe71557a
TC		 6235void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6236 unsigned long address)
6237{
c24ae0dc
TC		 6238 /*
6239 * The physical address of apic access page is stored in the VMCS.
6240 * Update it when it becomes invalid.
6241 */
6242 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6243 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6244}
6245
9357d939 6246/*
362c698f 6247 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6248 * exiting to the userspace. Otherwise, the value will be returned to the
6249 * userspace.
6250 */
851ba692 6251static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6252{
6253 int r;
35754c98 6254 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6255 vcpu->run->request_interrupt_window;
730dca42 6256 bool req_immediate_exit = false;
b6c7a5dc 6257
3e007509 6258 if (vcpu->requests) {
a8eeb04a 6259 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6260 kvm_mmu_unload(vcpu);
a8eeb04a 6261 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6262 __kvm_migrate_timers(vcpu);
d828199e
MT		 6263 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6264 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6265 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6266 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6267 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6268 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6269 if (unlikely(r))
6270 goto out;
6271 }
a8eeb04a 6272 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6273 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6274 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6275 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6276 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6277 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6278 r = 0;
6279 goto out;
6280 }
a8eeb04a 6281 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6282 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6283 r = 0;
6284 goto out;
6285 }
a8eeb04a 6286 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6287 vcpu->fpu_active = 0;
6288 kvm_x86_ops->fpu_deactivate(vcpu);
6289 }
af585b92
GN		 6290 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6291 /* Page is swapped out. Do synthetic halt */
6292 vcpu->arch.apf.halted = true;
6293 r = 1;
6294 goto out;
6295 }
c9aaa895
GC		 6296 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6297 record_steal_time(vcpu);
64d60670
PB		 6298 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6299 process_smi(vcpu);
7460fb4a
AK		 6300 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6301 process_nmi(vcpu);
f5132b01 6302 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6303 kvm_pmu_handle_event(vcpu);
f5132b01 6304 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6305 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6306 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6307 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6308 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6309 (void *) vcpu->arch.eoi_exit_bitmap)) {
6310 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6311 vcpu->run->eoi.vector =
6312 vcpu->arch.pending_ioapic_eoi;
6313 r = 0;
6314 goto out;
6315 }
6316 }
3d81bc7e
YZ		 6317 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6318 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6319 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6320 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6321 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6322 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6323 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6324 r = 0;
6325 goto out;
6326 }
e516cebb
AS		 6327 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6328 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6329 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6330 r = 0;
6331 goto out;
6332 }
2f52d58c 6333 }
b93463aa 6334
b463a6f7 6335 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6336 kvm_apic_accept_events(vcpu);
6337 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6338 r = 1;
6339 goto out;
6340 }
6341
b6b8a145
JK		 6342 if (inject_pending_event(vcpu, req_int_win) != 0)
6343 req_immediate_exit = true;
b463a6f7 6344 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6345 else if (vcpu->arch.nmi_pending)
c9a7953f 6346 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6347 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6348 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6349
6350 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6351 /*
6352 * Update architecture specific hints for APIC
6353 * virtual interrupt delivery.
6354 */
6355 if (kvm_x86_ops->hwapic_irr_update)
6356 kvm_x86_ops->hwapic_irr_update(vcpu,
6357 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6358 update_cr8_intercept(vcpu);
6359 kvm_lapic_sync_to_vapic(vcpu);
6360 }
6361 }
6362
d8368af8
AK		 6363 r = kvm_mmu_reload(vcpu);
6364 if (unlikely(r)) {
d905c069 6365 goto cancel_injection;
d8368af8
AK		 6366 }
6367
b6c7a5dc
HB		 6368 preempt_disable();
6369
6370 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6371 if (vcpu->fpu_active)
6372 kvm_load_guest_fpu(vcpu);
2acf923e 6373 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6374
6b7e2d09
XG		 6375 vcpu->mode = IN_GUEST_MODE;
6376
01b71917
MT		 6377 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6378
6b7e2d09
XG		 6379 /* We should set ->mode before check ->requests,
6380 * see the comment in make_all_cpus_request.
6381 */
01b71917 6382 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6383
d94e1dc9 6384 local_irq_disable();
32f88400 6385
6b7e2d09 6386 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6387 || need_resched() || signal_pending(current)) {
6b7e2d09 6388 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6389 smp_wmb();
6c142801
AK		 6390 local_irq_enable();
6391 preempt_enable();
01b71917 6392 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6393 r = 1;
d905c069 6394 goto cancel_injection;
6c142801
AK		 6395 }
6396
d6185f20
NHE		 6397 if (req_immediate_exit)
6398 smp_send_reschedule(vcpu->cpu);
6399
ccf73aaf 6400 __kvm_guest_enter();
b6c7a5dc 6401
42dbaa5a 6402 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6403 set_debugreg(0, 7);
6404 set_debugreg(vcpu->arch.eff_db[0], 0);
6405 set_debugreg(vcpu->arch.eff_db[1], 1);
6406 set_debugreg(vcpu->arch.eff_db[2], 2);
6407 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6408 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6409 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6410 }
b6c7a5dc 6411
229456fc 6412 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6413 wait_lapic_expire(vcpu);
851ba692 6414 kvm_x86_ops->run(vcpu);
b6c7a5dc 6415
c77fb5fe
PB		 6416 /*
6417 * Do this here before restoring debug registers on the host. And
6418 * since we do this before handling the vmexit, a DR access vmexit
6419 * can (a) read the correct value of the debug registers, (b) set
6420 * KVM_DEBUGREG_WONT_EXIT again.
6421 */
6422 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6423 int i;
6424
6425 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6426 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6427 for (i = 0; i < KVM_NR_DB_REGS; i++)
6428 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6429 }
6430
24f1e32c
FW		 6431 /*
6432 * If the guest has used debug registers, at least dr7
6433 * will be disabled while returning to the host.
6434 * If we don't have active breakpoints in the host, we don't
6435 * care about the messed up debug address registers. But if
6436 * we have some of them active, restore the old state.
6437 */
59d8eb53 6438 if (hw_breakpoint_active())
24f1e32c 6439 hw_breakpoint_restore();
42dbaa5a 6440
886b470c 6441 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
4ea1636b 6442 rdtsc());
1d5f066e 6443
6b7e2d09 6444 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6445 smp_wmb();
a547c6db
YZ		 6446
6447 /* Interrupt is enabled by handle_external_intr() */
6448 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6449
6450 ++vcpu->stat.exits;
6451
6452 /*
6453 * We must have an instruction between local_irq_enable() and
6454 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6455 * the interrupt shadow. The stat.exits increment will do nicely.
6456 * But we need to prevent reordering, hence this barrier():
6457 */
6458 barrier();
6459
6460 kvm_guest_exit();
6461
6462 preempt_enable();
6463
f656ce01 6464 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6465
b6c7a5dc
HB		 6466 /*
6467 * Profile KVM exit RIPs:
6468 */
6469 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6470 unsigned long rip = kvm_rip_read(vcpu);
6471 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6472 }
6473
cc578287
ZA		 6474 if (unlikely(vcpu->arch.tsc_always_catchup))
6475 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6476
5cfb1d5a
MT		 6477 if (vcpu->arch.apic_attention)
6478 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6479
851ba692 6480 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6481 return r;
6482
6483cancel_injection:
6484 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6485 if (unlikely(vcpu->arch.apic_attention))
6486 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6487out:
6488 return r;
6489}
b6c7a5dc 6490
362c698f
PB		 6491static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6492{
9c8fd1ba
PB		 6493 if (!kvm_arch_vcpu_runnable(vcpu)) {
6494 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6495 kvm_vcpu_block(vcpu);
6496 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6497 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6498 return 1;
6499 }
362c698f
PB		 6500
6501 kvm_apic_accept_events(vcpu);
6502 switch(vcpu->arch.mp_state) {
6503 case KVM_MP_STATE_HALTED:
6504 vcpu->arch.pv.pv_unhalted = false;
6505 vcpu->arch.mp_state =
6506 KVM_MP_STATE_RUNNABLE;
6507 case KVM_MP_STATE_RUNNABLE:
6508 vcpu->arch.apf.halted = false;
6509 break;
6510 case KVM_MP_STATE_INIT_RECEIVED:
6511 break;
6512 default:
6513 return -EINTR;
6514 break;
6515 }
6516 return 1;
6517}
09cec754 6518
362c698f 6519static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6520{
6521 int r;
f656ce01 6522 struct kvm *kvm = vcpu->kvm;
d7690175 6523
f656ce01 6524 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6525
362c698f 6526 for (;;) {
af585b92
GN		 6527 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6528 !vcpu->arch.apf.halted)
851ba692 6529 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6530 else
6531 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6532 if (r <= 0)
6533 break;
6534
6535 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6536 if (kvm_cpu_has_pending_timer(vcpu))
6537 kvm_inject_pending_timer_irqs(vcpu);
6538
851ba692 6539 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6540 r = 0;
6541 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6542 ++vcpu->stat.request_irq_exits;
362c698f 6543 break;
09cec754 6544 }
af585b92
GN		 6545
6546 kvm_check_async_pf_completion(vcpu);
6547
09cec754
GN		 6548 if (signal_pending(current)) {
6549 r = -EINTR;
851ba692 6550 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6551 ++vcpu->stat.signal_exits;
362c698f 6552 break;
09cec754
GN		 6553 }
6554 if (need_resched()) {
f656ce01 6555 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6556 cond_resched();
f656ce01 6557 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6558 }
b6c7a5dc
HB		 6559 }
6560
f656ce01 6561 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6562
6563 return r;
6564}
6565
716d51ab
GN		 6566static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6567{
6568 int r;
6569 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6570 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6571 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6572 if (r != EMULATE_DONE)
6573 return 0;
6574 return 1;
6575}
6576
6577static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6578{
6579 BUG_ON(!vcpu->arch.pio.count);
6580
6581 return complete_emulated_io(vcpu);
6582}
6583
f78146b0
AK		 6584/*
6585 * Implements the following, as a state machine:
6586 *
6587 * read:
6588 * for each fragment
87da7e66
XG		 6589 * for each mmio piece in the fragment
6590 * write gpa, len
6591 * exit
6592 * copy data
f78146b0
AK		 6593 * execute insn
6594 *
6595 * write:
6596 * for each fragment
87da7e66
XG		 6597 * for each mmio piece in the fragment
6598 * write gpa, len
6599 * copy data
6600 * exit
f78146b0 6601 */
716d51ab 6602static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6603{
6604 struct kvm_run *run = vcpu->run;
f78146b0 6605 struct kvm_mmio_fragment *frag;
87da7e66 6606 unsigned len;
5287f194 6607
716d51ab 6608 BUG_ON(!vcpu->mmio_needed);
5287f194 6609
716d51ab 6610 /* Complete previous fragment */
87da7e66
XG		 6611 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6612 len = min(8u, frag->len);
716d51ab 6613 if (!vcpu->mmio_is_write)
87da7e66
XG		 6614 memcpy(frag->data, run->mmio.data, len);
6615
6616 if (frag->len <= 8) {
6617 /* Switch to the next fragment. */
6618 frag++;
6619 vcpu->mmio_cur_fragment++;
6620 } else {
6621 /* Go forward to the next mmio piece. */
6622 frag->data += len;
6623 frag->gpa += len;
6624 frag->len -= len;
6625 }
6626
a08d3b3b 6627 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6628 vcpu->mmio_needed = 0;
0912c977
PB		 6629
6630 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6631 if (vcpu->mmio_is_write)
716d51ab
GN		 6632 return 1;
6633 vcpu->mmio_read_completed = 1;
6634 return complete_emulated_io(vcpu);
6635 }
87da7e66 6636
716d51ab
GN		 6637 run->exit_reason = KVM_EXIT_MMIO;
6638 run->mmio.phys_addr = frag->gpa;
6639 if (vcpu->mmio_is_write)
87da7e66
XG		 6640 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6641 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6642 run->mmio.is_write = vcpu->mmio_is_write;
6643 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6644 return 0;
5287f194
AK		 6645}
6646
716d51ab 6647
b6c7a5dc
HB		 6648int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6649{
c5bedc68 6650 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6651 int r;
6652 sigset_t sigsaved;
6653
c4d72e2d 6654 fpu__activate_curr(fpu);
e5c30142 6655
ac9f6dc0
AK		 6656 if (vcpu->sigset_active)
6657 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6658
a4535290 6659 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6660 kvm_vcpu_block(vcpu);
66450a21 6661 kvm_apic_accept_events(vcpu);
d7690175 6662 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6663 r = -EAGAIN;
6664 goto out;
b6c7a5dc
HB		 6665 }
6666
b6c7a5dc 6667 /* re-sync apic's tpr */
35754c98 6668 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6669 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6670 r = -EINVAL;
6671 goto out;
6672 }
6673 }
b6c7a5dc 6674
716d51ab
GN		 6675 if (unlikely(vcpu->arch.complete_userspace_io)) {
6676 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6677 vcpu->arch.complete_userspace_io = NULL;
6678 r = cui(vcpu);
6679 if (r <= 0)
6680 goto out;
6681 } else
6682 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6683
362c698f 6684 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6685
6686out:
f1d86e46 6687 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6688 if (vcpu->sigset_active)
6689 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6690
b6c7a5dc
HB		 6691 return r;
6692}
6693
6694int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6695{
7ae441ea
GN		 6696 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6697 /*
6698 * We are here if userspace calls get_regs() in the middle of
6699 * instruction emulation. Registers state needs to be copied
4a969980 6700 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6701 * that usually, but some bad designed PV devices (vmware
6702 * backdoor interface) need this to work
6703 */
dd856efa 6704 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6705 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6706 }
5fdbf976
MT		 6707 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6708 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6709 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6710 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6711 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6712 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6713 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6714 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6715#ifdef CONFIG_X86_64
5fdbf976
MT		 6716 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6717 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6718 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6719 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6720 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6721 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6722 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6723 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6724#endif
6725
5fdbf976 6726 regs->rip = kvm_rip_read(vcpu);
91586a3b 6727 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6728
b6c7a5dc
HB		 6729 return 0;
6730}
6731
6732int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6733{
7ae441ea
GN		 6734 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6735 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6736
5fdbf976
MT		 6737 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6738 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6739 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6740 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6741 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6742 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6743 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6744 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6745#ifdef CONFIG_X86_64
5fdbf976
MT		 6746 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6747 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6748 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6749 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6750 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6751 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6752 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6753 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6754#endif
6755
5fdbf976 6756 kvm_rip_write(vcpu, regs->rip);
91586a3b 6757 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6758
b4f14abd
JK		 6759 vcpu->arch.exception.pending = false;
6760
3842d135
AK		 6761 kvm_make_request(KVM_REQ_EVENT, vcpu);
6762
b6c7a5dc
HB		 6763 return 0;
6764}
6765
b6c7a5dc
HB		 6766void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6767{
6768 struct kvm_segment cs;
6769
3e6e0aab 6770 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6771 *db = cs.db;
6772 *l = cs.l;
6773}
6774EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6775
6776int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6777 struct kvm_sregs *sregs)
6778{
89a27f4d 6779 struct desc_ptr dt;
b6c7a5dc 6780
3e6e0aab
GT		 6781 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6782 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6783 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6784 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6785 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6786 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6787
3e6e0aab
GT		 6788 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6789 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6790
6791 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6792 sregs->idt.limit = dt.size;
6793 sregs->idt.base = dt.address;
b6c7a5dc 6794 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6795 sregs->gdt.limit = dt.size;
6796 sregs->gdt.base = dt.address;
b6c7a5dc 6797
4d4ec087 6798 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6799 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6800 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6801 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6802 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6803 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6804 sregs->apic_base = kvm_get_apic_base(vcpu);
6805
923c61bb 6806 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6807
36752c9b 6808 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6809 set_bit(vcpu->arch.interrupt.nr,
6810 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6811
b6c7a5dc
HB		 6812 return 0;
6813}
6814
62d9f0db
MT		 6815int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6816 struct kvm_mp_state *mp_state)
6817{
66450a21 6818 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6819 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6820 vcpu->arch.pv.pv_unhalted)
6821 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6822 else
6823 mp_state->mp_state = vcpu->arch.mp_state;
6824
62d9f0db
MT		 6825 return 0;
6826}
6827
6828int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6829 struct kvm_mp_state *mp_state)
6830{
66450a21
JK		 6831 if (!kvm_vcpu_has_lapic(vcpu) &&
6832 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6833 return -EINVAL;
6834
6835 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6836 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6837 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6838 } else
6839 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6840 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6841 return 0;
6842}
6843
7f3d35fd
KW		 6844int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6845 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6846{
9d74191a 6847 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6848 int ret;
e01c2426 6849
8ec4722d 6850 init_emulate_ctxt(vcpu);
c697518a 6851
7f3d35fd 6852 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6853 has_error_code, error_code);
c697518a 6854
c697518a 6855 if (ret)
19d04437 6856 return EMULATE_FAIL;
37817f29 6857
9d74191a
TY		 6858 kvm_rip_write(vcpu, ctxt->eip);
6859 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6860 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6861 return EMULATE_DONE;
37817f29
IE		 6862}
6863EXPORT_SYMBOL_GPL(kvm_task_switch);
6864
b6c7a5dc
HB		 6865int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6866 struct kvm_sregs *sregs)
6867{
58cb628d 6868 struct msr_data apic_base_msr;
b6c7a5dc 6869 int mmu_reset_needed = 0;
63f42e02 6870 int pending_vec, max_bits, idx;
89a27f4d 6871 struct desc_ptr dt;
b6c7a5dc 6872
6d1068b3
PM		 6873 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6874 return -EINVAL;
6875
89a27f4d
GN		 6876 dt.size = sregs->idt.limit;
6877 dt.address = sregs->idt.base;
b6c7a5dc 6878 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6879 dt.size = sregs->gdt.limit;
6880 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6881 kvm_x86_ops->set_gdt(vcpu, &dt);
6882
ad312c7c 6883 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6884 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6885 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6886 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6887
2d3ad1f4 6888 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6889
f6801dff 6890 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6891 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6892 apic_base_msr.data = sregs->apic_base;
6893 apic_base_msr.host_initiated = true;
6894 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6895
4d4ec087 6896 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6897 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6898 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6899
fc78f519 6900 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6901 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6902 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6903 kvm_update_cpuid(vcpu);
63f42e02
XG		 6904
6905 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6906 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6907 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6908 mmu_reset_needed = 1;
6909 }
63f42e02 6910 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6911
6912 if (mmu_reset_needed)
6913 kvm_mmu_reset_context(vcpu);
6914
a50abc3b 6915 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6916 pending_vec = find_first_bit(
6917 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6918 if (pending_vec < max_bits) {
66fd3f7f 6919 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6920 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6921 }
6922
3e6e0aab
GT		 6923 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6924 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6925 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6926 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6927 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6928 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6929
3e6e0aab
GT		 6930 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6931 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6932
5f0269f5
ME		 6933 update_cr8_intercept(vcpu);
6934
9c3e4aab 6935 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6936 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6937 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6938 !is_protmode(vcpu))
9c3e4aab
MT		 6939 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6940
3842d135
AK		 6941 kvm_make_request(KVM_REQ_EVENT, vcpu);
6942
b6c7a5dc
HB		 6943 return 0;
6944}
6945
d0bfb940
JK		 6946int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6947 struct kvm_guest_debug *dbg)
b6c7a5dc 6948{
355be0b9 6949 unsigned long rflags;
ae675ef0 6950 int i, r;
b6c7a5dc 6951
4f926bf2
JK		 6952 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6953 r = -EBUSY;
6954 if (vcpu->arch.exception.pending)
2122ff5e 6955 goto out;
4f926bf2
JK		 6956 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6957 kvm_queue_exception(vcpu, DB_VECTOR);
6958 else
6959 kvm_queue_exception(vcpu, BP_VECTOR);
6960 }
6961
91586a3b
JK		 6962 /*
6963 * Read rflags as long as potentially injected trace flags are still
6964 * filtered out.
6965 */
6966 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6967
6968 vcpu->guest_debug = dbg->control;
6969 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6970 vcpu->guest_debug = 0;
6971
6972 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6973 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6974 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6975 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6976 } else {
6977 for (i = 0; i < KVM_NR_DB_REGS; i++)
6978 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6979 }
c8639010 6980 kvm_update_dr7(vcpu);
ae675ef0 6981
f92653ee
JK		 6982 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6983 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6984 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6985
91586a3b
JK		 6986 /*
6987 * Trigger an rflags update that will inject or remove the trace
6988 * flags.
6989 */
6990 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6991
c8639010 6992 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6993
4f926bf2 6994 r = 0;
d0bfb940 6995
2122ff5e 6996out:
b6c7a5dc
HB		 6997
6998 return r;
6999}
7000
8b006791
ZX		 7001/*
7002 * Translate a guest virtual address to a guest physical address.
7003 */
7004int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7005 struct kvm_translation *tr)
7006{
7007 unsigned long vaddr = tr->linear_address;
7008 gpa_t gpa;
f656ce01 7009 int idx;
8b006791 7010
f656ce01 7011 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7012 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7013 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7014 tr->physical_address = gpa;
7015 tr->valid = gpa != UNMAPPED_GVA;
7016 tr->writeable = 1;
7017 tr->usermode = 0;
8b006791
ZX		 7018
7019 return 0;
7020}
7021
d0752060
HB		 7022int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7023{
c47ada30 7024 struct fxregs_state *fxsave =
7366ed77 7025 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7026
d0752060
HB		 7027 memcpy(fpu->fpr, fxsave->st_space, 128);
7028 fpu->fcw = fxsave->cwd;
7029 fpu->fsw = fxsave->swd;
7030 fpu->ftwx = fxsave->twd;
7031 fpu->last_opcode = fxsave->fop;
7032 fpu->last_ip = fxsave->rip;
7033 fpu->last_dp = fxsave->rdp;
7034 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7035
d0752060
HB		 7036 return 0;
7037}
7038
7039int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7040{
c47ada30 7041 struct fxregs_state *fxsave =
7366ed77 7042 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7043
d0752060
HB		 7044 memcpy(fxsave->st_space, fpu->fpr, 128);
7045 fxsave->cwd = fpu->fcw;
7046 fxsave->swd = fpu->fsw;
7047 fxsave->twd = fpu->ftwx;
7048 fxsave->fop = fpu->last_opcode;
7049 fxsave->rip = fpu->last_ip;
7050 fxsave->rdp = fpu->last_dp;
7051 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7052
d0752060
HB		 7053 return 0;
7054}
7055
0ee6a517 7056static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7057{
bf935b0b 7058 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7059 if (cpu_has_xsaves)
7366ed77 7060 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7061 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7062
2acf923e
DC		 7063 /*
7064 * Ensure guest xcr0 is valid for loading
7065 */
7066 vcpu->arch.xcr0 = XSTATE_FP;
7067
ad312c7c 7068 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7069}
d0752060
HB		 7070
7071void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7072{
2608d7a1 7073 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7074 return;
7075
2acf923e
DC		 7076 /*
7077 * Restore all possible states in the guest,
7078 * and assume host would use all available bits.
7079 * Guest xcr0 would be loaded later.
7080 */
7081 kvm_put_guest_xcr0(vcpu);
d0752060 7082 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7083 __kernel_fpu_begin();
003e2e8b 7084 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7085 trace_kvm_fpu(1);
d0752060 7086}
d0752060
HB		 7087
7088void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7089{
2acf923e
DC		 7090 kvm_put_guest_xcr0(vcpu);
7091
653f52c3
RR		 7092 if (!vcpu->guest_fpu_loaded) {
7093 vcpu->fpu_counter = 0;
d0752060 7094 return;
653f52c3 7095 }
d0752060
HB		 7096
7097 vcpu->guest_fpu_loaded = 0;
4f836347 7098 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7099 __kernel_fpu_end();
f096ed85 7100 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7101 /*
7102 * If using eager FPU mode, or if the guest is a frequent user
7103 * of the FPU, just leave the FPU active for next time.
7104 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7105 * the FPU in bursts will revert to loading it on demand.
7106 */
a9b4fb7e 7107 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7108 if (++vcpu->fpu_counter < 5)
7109 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7110 }
0c04851c 7111 trace_kvm_fpu(0);
d0752060 7112}
e9b11c17
ZX		 7113
7114void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7115{
12f9a48f 7116 kvmclock_reset(vcpu);
7f1ea208 7117
f5f48ee1 7118 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7119 kvm_x86_ops->vcpu_free(vcpu);
7120}
7121
7122struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7123 unsigned int id)
7124{
c447e76b
LL		 7125 struct kvm_vcpu *vcpu;
7126
6755bae8
ZA		 7127 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7128 printk_once(KERN_WARNING
7129 "kvm: SMP vm created on host with unstable TSC; "
7130 "guest TSC will not be reliable\n");
c447e76b
LL		 7131
7132 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7133
c447e76b 7134 return vcpu;
26e5215f 7135}
e9b11c17 7136
26e5215f
AK		 7137int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7138{
7139 int r;
e9b11c17 7140
19efffa2 7141 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7142 r = vcpu_load(vcpu);
7143 if (r)
7144 return r;
d28bc9dd 7145 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7146 kvm_mmu_setup(vcpu);
e9b11c17 7147 vcpu_put(vcpu);
26e5215f 7148 return r;
e9b11c17
ZX		 7149}
7150
31928aa5 7151void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7152{
8fe8ab46 7153 struct msr_data msr;
332967a3 7154 struct kvm *kvm = vcpu->kvm;
42897d86 7155
31928aa5
DD		 7156 if (vcpu_load(vcpu))
7157 return;
8fe8ab46
WA		 7158 msr.data = 0x0;
7159 msr.index = MSR_IA32_TSC;
7160 msr.host_initiated = true;
7161 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7162 vcpu_put(vcpu);
7163
630994b3
MT		 7164 if (!kvmclock_periodic_sync)
7165 return;
7166
332967a3
AJ		 7167 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7168 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7169}
7170
d40ccc62 7171void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7172{
9fc77441 7173 int r;
344d9588
GN		 7174 vcpu->arch.apf.msr_val = 0;
7175
9fc77441
MT		 7176 r = vcpu_load(vcpu);
7177 BUG_ON(r);
e9b11c17
ZX		 7178 kvm_mmu_unload(vcpu);
7179 vcpu_put(vcpu);
7180
7181 kvm_x86_ops->vcpu_free(vcpu);
7182}
7183
d28bc9dd 7184void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7185{
e69fab5d
PB		 7186 vcpu->arch.hflags = 0;
7187
7460fb4a
AK		 7188 atomic_set(&vcpu->arch.nmi_queued, 0);
7189 vcpu->arch.nmi_pending = 0;
448fa4a9 7190 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7191 kvm_clear_interrupt_queue(vcpu);
7192 kvm_clear_exception_queue(vcpu);
448fa4a9 7193
42dbaa5a 7194 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7195 kvm_update_dr0123(vcpu);
6f43ed01 7196 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7197 kvm_update_dr6(vcpu);
42dbaa5a 7198 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7199 kvm_update_dr7(vcpu);
42dbaa5a 7200
1119022c
NA		 7201 vcpu->arch.cr2 = 0;
7202
3842d135 7203 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7204 vcpu->arch.apf.msr_val = 0;
c9aaa895 7205 vcpu->arch.st.msr_val = 0;
3842d135 7206
12f9a48f
GC		 7207 kvmclock_reset(vcpu);
7208
af585b92
GN		 7209 kvm_clear_async_pf_completion_queue(vcpu);
7210 kvm_async_pf_hash_reset(vcpu);
7211 vcpu->arch.apf.halted = false;
3842d135 7212
64d60670 7213 if (!init_event) {
d28bc9dd 7214 kvm_pmu_reset(vcpu);
64d60670
PB		 7215 vcpu->arch.smbase = 0x30000;
7216 }
f5132b01 7217
66f7b72e
JS		 7218 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7219 vcpu->arch.regs_avail = ~0;
7220 vcpu->arch.regs_dirty = ~0;
7221
d28bc9dd 7222 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7223}
7224
2b4a273b 7225void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7226{
7227 struct kvm_segment cs;
7228
7229 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7230 cs.selector = vector << 8;
7231 cs.base = vector << 12;
7232 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7233 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7234}
7235
13a34e06 7236int kvm_arch_hardware_enable(void)
e9b11c17 7237{
ca84d1a2
ZA		 7238 struct kvm *kvm;
7239 struct kvm_vcpu *vcpu;
7240 int i;
0dd6a6ed
ZA		 7241 int ret;
7242 u64 local_tsc;
7243 u64 max_tsc = 0;
7244 bool stable, backwards_tsc = false;
18863bdd
AK		 7245
7246 kvm_shared_msr_cpu_online();
13a34e06 7247 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7248 if (ret != 0)
7249 return ret;
7250
4ea1636b 7251 local_tsc = rdtsc();
0dd6a6ed
ZA		 7252 stable = !check_tsc_unstable();
7253 list_for_each_entry(kvm, &vm_list, vm_list) {
7254 kvm_for_each_vcpu(i, vcpu, kvm) {
7255 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7256 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7257 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7258 backwards_tsc = true;
7259 if (vcpu->arch.last_host_tsc > max_tsc)
7260 max_tsc = vcpu->arch.last_host_tsc;
7261 }
7262 }
7263 }
7264
7265 /*
7266 * Sometimes, even reliable TSCs go backwards. This happens on
7267 * platforms that reset TSC during suspend or hibernate actions, but
7268 * maintain synchronization. We must compensate. Fortunately, we can
7269 * detect that condition here, which happens early in CPU bringup,
7270 * before any KVM threads can be running. Unfortunately, we can't
7271 * bring the TSCs fully up to date with real time, as we aren't yet far
7272 * enough into CPU bringup that we know how much real time has actually
7273 * elapsed; our helper function, get_kernel_ns() will be using boot
7274 * variables that haven't been updated yet.
7275 *
7276 * So we simply find the maximum observed TSC above, then record the
7277 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7278 * the adjustment will be applied. Note that we accumulate
7279 * adjustments, in case multiple suspend cycles happen before some VCPU
7280 * gets a chance to run again. In the event that no KVM threads get a
7281 * chance to run, we will miss the entire elapsed period, as we'll have
7282 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7283 * loose cycle time. This isn't too big a deal, since the loss will be
7284 * uniform across all VCPUs (not to mention the scenario is extremely
7285 * unlikely). It is possible that a second hibernate recovery happens
7286 * much faster than a first, causing the observed TSC here to be
7287 * smaller; this would require additional padding adjustment, which is
7288 * why we set last_host_tsc to the local tsc observed here.
7289 *
7290 * N.B. - this code below runs only on platforms with reliable TSC,
7291 * as that is the only way backwards_tsc is set above. Also note
7292 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7293 * have the same delta_cyc adjustment applied if backwards_tsc
7294 * is detected. Note further, this adjustment is only done once,
7295 * as we reset last_host_tsc on all VCPUs to stop this from being
7296 * called multiple times (one for each physical CPU bringup).
7297 *
4a969980 7298 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7299 * will be compensated by the logic in vcpu_load, which sets the TSC to
7300 * catchup mode. This will catchup all VCPUs to real time, but cannot
7301 * guarantee that they stay in perfect synchronization.
7302 */
7303 if (backwards_tsc) {
7304 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7305 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7306 list_for_each_entry(kvm, &vm_list, vm_list) {
7307 kvm_for_each_vcpu(i, vcpu, kvm) {
7308 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7309 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7310 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7311 }
7312
7313 /*
7314 * We have to disable TSC offset matching.. if you were
7315 * booting a VM while issuing an S4 host suspend....
7316 * you may have some problem. Solving this issue is
7317 * left as an exercise to the reader.
7318 */
7319 kvm->arch.last_tsc_nsec = 0;
7320 kvm->arch.last_tsc_write = 0;
7321 }
7322
7323 }
7324 return 0;
e9b11c17
ZX		 7325}
7326
13a34e06 7327void kvm_arch_hardware_disable(void)
e9b11c17 7328{
13a34e06
RK		 7329 kvm_x86_ops->hardware_disable();
7330 drop_user_return_notifiers();
e9b11c17
ZX		 7331}
7332
7333int kvm_arch_hardware_setup(void)
7334{
9e9c3fe4
NA		 7335 int r;
7336
7337 r = kvm_x86_ops->hardware_setup();
7338 if (r != 0)
7339 return r;
7340
7341 kvm_init_msr_list();
7342 return 0;
e9b11c17
ZX		 7343}
7344
7345void kvm_arch_hardware_unsetup(void)
7346{
7347 kvm_x86_ops->hardware_unsetup();
7348}
7349
7350void kvm_arch_check_processor_compat(void *rtn)
7351{
7352 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7353}
7354
7355bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7356{
7357 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7358}
7359EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7360
7361bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7362{
7363 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7364}
7365
3e515705
AK		 7366bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7367{
35754c98 7368 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7369}
7370
54e9818f
GN		 7371struct static_key kvm_no_apic_vcpu __read_mostly;
7372
e9b11c17
ZX		 7373int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7374{
7375 struct page *page;
7376 struct kvm *kvm;
7377 int r;
7378
7379 BUG_ON(vcpu->kvm == NULL);
7380 kvm = vcpu->kvm;
7381
6aef266c 7382 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7383 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7384 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7385 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7386 else
a4535290 7387 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7388
7389 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7390 if (!page) {
7391 r = -ENOMEM;
7392 goto fail;
7393 }
ad312c7c 7394 vcpu->arch.pio_data = page_address(page);
e9b11c17 7395
cc578287 7396 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7397
e9b11c17
ZX		 7398 r = kvm_mmu_create(vcpu);
7399 if (r < 0)
7400 goto fail_free_pio_data;
7401
7402 if (irqchip_in_kernel(kvm)) {
7403 r = kvm_create_lapic(vcpu);
7404 if (r < 0)
7405 goto fail_mmu_destroy;
54e9818f
GN		 7406 } else
7407 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7408
890ca9ae
HY		 7409 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7410 GFP_KERNEL);
7411 if (!vcpu->arch.mce_banks) {
7412 r = -ENOMEM;
443c39bc 7413 goto fail_free_lapic;
890ca9ae
HY		 7414 }
7415 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7416
f1797359
WY		 7417 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7418 r = -ENOMEM;
f5f48ee1 7419 goto fail_free_mce_banks;
f1797359 7420 }
f5f48ee1 7421
0ee6a517 7422 fx_init(vcpu);
66f7b72e 7423
ba904635 7424 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7425 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7426
7427 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7428 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7429
5a4f55cd
EK		 7430 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7431
74545705
RK		 7432 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7433
af585b92 7434 kvm_async_pf_hash_reset(vcpu);
f5132b01 7435 kvm_pmu_init(vcpu);
af585b92 7436
1c1a9ce9
SR		 7437 vcpu->arch.pending_external_vector = -1;
7438
e9b11c17 7439 return 0;
0ee6a517 7440
f5f48ee1
SY		 7441fail_free_mce_banks:
7442 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7443fail_free_lapic:
7444 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7445fail_mmu_destroy:
7446 kvm_mmu_destroy(vcpu);
7447fail_free_pio_data:
ad312c7c 7448 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7449fail:
7450 return r;
7451}
7452
7453void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7454{
f656ce01
MT		 7455 int idx;
7456
f5132b01 7457 kvm_pmu_destroy(vcpu);
36cb93fd 7458 kfree(vcpu->arch.mce_banks);
e9b11c17 7459 kvm_free_lapic(vcpu);
f656ce01 7460 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7461 kvm_mmu_destroy(vcpu);
f656ce01 7462 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7463 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7464 if (!lapic_in_kernel(vcpu))
54e9818f 7465 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7466}
d19a9cd2 7467
e790d9ef
RK		 7468void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7469{
ae97a3b8 7470 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7471}
7472
e08b9637 7473int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7474{
e08b9637
CO		 7475 if (type)
7476 return -EINVAL;
7477
6ef768fa 7478 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7479 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7480 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7481 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7482 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7483
5550af4d
SY		 7484 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7485 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7486 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7487 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7488 &kvm->arch.irq_sources_bitmap);
5550af4d 7489
038f8c11 7490 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7491 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7492 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7493
7494 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7495
7e44e449 7496 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7497 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7498
d89f5eff 7499 return 0;
d19a9cd2
ZX		 7500}
7501
7502static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7503{
9fc77441
MT		 7504 int r;
7505 r = vcpu_load(vcpu);
7506 BUG_ON(r);
d19a9cd2
ZX		 7507 kvm_mmu_unload(vcpu);
7508 vcpu_put(vcpu);
7509}
7510
7511static void kvm_free_vcpus(struct kvm *kvm)
7512{
7513 unsigned int i;
988a2cae 7514 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7515
7516 /*
7517 * Unpin any mmu pages first.
7518 */
af585b92
GN		 7519 kvm_for_each_vcpu(i, vcpu, kvm) {
7520 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7521 kvm_unload_vcpu_mmu(vcpu);
af585b92 7522 }
988a2cae
GN		 7523 kvm_for_each_vcpu(i, vcpu, kvm)
7524 kvm_arch_vcpu_free(vcpu);
7525
7526 mutex_lock(&kvm->lock);
7527 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7528 kvm->vcpus[i] = NULL;
d19a9cd2 7529
988a2cae
GN		 7530 atomic_set(&kvm->online_vcpus, 0);
7531 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7532}
7533
ad8ba2cd
SY		 7534void kvm_arch_sync_events(struct kvm *kvm)
7535{
332967a3 7536 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7537 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7538 kvm_free_all_assigned_devices(kvm);
aea924f6 7539 kvm_free_pit(kvm);
ad8ba2cd
SY		 7540}
7541
9da0e4d5
PB		 7542int __x86_set_memory_region(struct kvm *kvm,
7543 const struct kvm_userspace_memory_region *mem)
7544{
7545 int i, r;
7546
7547 /* Called with kvm->slots_lock held. */
7548 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7549
7550 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7551 struct kvm_userspace_memory_region m = *mem;
7552
7553 m.slot |= i << 16;
7554 r = __kvm_set_memory_region(kvm, &m);
7555 if (r < 0)
7556 return r;
7557 }
7558
7559 return 0;
7560}
7561EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7562
7563int x86_set_memory_region(struct kvm *kvm,
7564 const struct kvm_userspace_memory_region *mem)
7565{
7566 int r;
7567
7568 mutex_lock(&kvm->slots_lock);
7569 r = __x86_set_memory_region(kvm, mem);
7570 mutex_unlock(&kvm->slots_lock);
7571
7572 return r;
7573}
7574EXPORT_SYMBOL_GPL(x86_set_memory_region);
7575
d19a9cd2
ZX		 7576void kvm_arch_destroy_vm(struct kvm *kvm)
7577{
27469d29
AH		 7578 if (current->mm == kvm->mm) {
7579 /*
7580 * Free memory regions allocated on behalf of userspace,
7581 * unless the the memory map has changed due to process exit
7582 * or fd copying.
7583 */
7584 struct kvm_userspace_memory_region mem;
7585 memset(&mem, 0, sizeof(mem));
7586 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7587 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7588
7589 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7590 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7591
7592 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7593 x86_set_memory_region(kvm, &mem);
27469d29 7594 }
6eb55818 7595 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7596 kfree(kvm->arch.vpic);
7597 kfree(kvm->arch.vioapic);
d19a9cd2 7598 kvm_free_vcpus(kvm);
1e08ec4a 7599 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7600}
0de10343 7601
5587027c 7602void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7603 struct kvm_memory_slot *dont)
7604{
7605 int i;
7606
d89cc617
TY		 7607 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7608 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7609 kvfree(free->arch.rmap[i]);
d89cc617 7610 free->arch.rmap[i] = NULL;
77d11309 7611 }
d89cc617
TY		 7612 if (i == 0)
7613 continue;
7614
7615 if (!dont || free->arch.lpage_info[i - 1] !=
7616 dont->arch.lpage_info[i - 1]) {
548ef284 7617 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7618 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7619 }
7620 }
7621}
7622
5587027c
AK		 7623int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7624 unsigned long npages)
db3fe4eb
TY		 7625{
7626 int i;
7627
d89cc617 7628 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7629 unsigned long ugfn;
7630 int lpages;
d89cc617 7631 int level = i + 1;
db3fe4eb
TY		 7632
7633 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7634 slot->base_gfn, level) + 1;
7635
d89cc617
TY		 7636 slot->arch.rmap[i] =
7637 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7638 if (!slot->arch.rmap[i])
77d11309 7639 goto out_free;
d89cc617
TY		 7640 if (i == 0)
7641 continue;
77d11309 7642
d89cc617
TY		 7643 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7644 sizeof(*slot->arch.lpage_info[i - 1]));
7645 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7646 goto out_free;
7647
7648 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7649 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7650 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7651 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7652 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7653 /*
7654 * If the gfn and userspace address are not aligned wrt each
7655 * other, or if explicitly asked to, disable large page
7656 * support for this slot
7657 */
7658 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7659 !kvm_largepages_enabled()) {
7660 unsigned long j;
7661
7662 for (j = 0; j < lpages; ++j)
d89cc617 7663 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7664 }
7665 }
7666
7667 return 0;
7668
7669out_free:
d89cc617 7670 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7671 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7672 slot->arch.rmap[i] = NULL;
7673 if (i == 0)
7674 continue;
7675
548ef284 7676 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7677 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7678 }
7679 return -ENOMEM;
7680}
7681
15f46015 7682void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7683{
e6dff7d1
TY		 7684 /*
7685 * memslots->generation has been incremented.
7686 * mmio generation may have reached its maximum value.
7687 */
54bf36aa 7688 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7689}
7690
f7784b8e
MT		 7691int kvm_arch_prepare_memory_region(struct kvm *kvm,
7692 struct kvm_memory_slot *memslot,
09170a49 7693 const struct kvm_userspace_memory_region *mem,
7b6195a9 7694 enum kvm_mr_change change)
0de10343 7695{
7a905b14
TY		 7696 /*
7697 * Only private memory slots need to be mapped here since
7698 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7699 */
7b6195a9 7700 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7701 unsigned long userspace_addr;
604b38ac 7702
7a905b14
TY		 7703 /*
7704 * MAP_SHARED to prevent internal slot pages from being moved
7705 * by fork()/COW.
7706 */
7b6195a9 7707 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7708 PROT_READ | PROT_WRITE,
7709 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7710
7a905b14
TY		 7711 if (IS_ERR((void *)userspace_addr))
7712 return PTR_ERR((void *)userspace_addr);
604b38ac 7713
7a905b14 7714 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7715 }
7716
f7784b8e
MT		 7717 return 0;
7718}
7719
88178fd4
KH		 7720static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7721 struct kvm_memory_slot *new)
7722{
7723 /* Still write protect RO slot */
7724 if (new->flags & KVM_MEM_READONLY) {
7725 kvm_mmu_slot_remove_write_access(kvm, new);
7726 return;
7727 }
7728
7729 /*
7730 * Call kvm_x86_ops dirty logging hooks when they are valid.
7731 *
7732 * kvm_x86_ops->slot_disable_log_dirty is called when:
7733 *
7734 * - KVM_MR_CREATE with dirty logging is disabled
7735 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7736 *
7737 * The reason is, in case of PML, we need to set D-bit for any slots
7738 * with dirty logging disabled in order to eliminate unnecessary GPA
7739 * logging in PML buffer (and potential PML buffer full VMEXT). This
7740 * guarantees leaving PML enabled during guest's lifetime won't have
7741 * any additonal overhead from PML when guest is running with dirty
7742 * logging disabled for memory slots.
7743 *
7744 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7745 * to dirty logging mode.
7746 *
7747 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7748 *
7749 * In case of write protect:
7750 *
7751 * Write protect all pages for dirty logging.
7752 *
7753 * All the sptes including the large sptes which point to this
7754 * slot are set to readonly. We can not create any new large
7755 * spte on this slot until the end of the logging.
7756 *
7757 * See the comments in fast_page_fault().
7758 */
7759 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7760 if (kvm_x86_ops->slot_enable_log_dirty)
7761 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7762 else
7763 kvm_mmu_slot_remove_write_access(kvm, new);
7764 } else {
7765 if (kvm_x86_ops->slot_disable_log_dirty)
7766 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7767 }
7768}
7769
f7784b8e 7770void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7771 const struct kvm_userspace_memory_region *mem,
8482644a 7772 const struct kvm_memory_slot *old,
f36f3f28 7773 const struct kvm_memory_slot *new,
8482644a 7774 enum kvm_mr_change change)
f7784b8e 7775{
8482644a 7776 int nr_mmu_pages = 0;
f7784b8e 7777
f36f3f28 7778 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7779 int ret;
7780
8482644a
TY		 7781 ret = vm_munmap(old->userspace_addr,
7782 old->npages * PAGE_SIZE);
f7784b8e
MT		 7783 if (ret < 0)
7784 printk(KERN_WARNING
7785 "kvm_vm_ioctl_set_memory_region: "
7786 "failed to munmap memory\n");
7787 }
7788
48c0e4e9
XG		 7789 if (!kvm->arch.n_requested_mmu_pages)
7790 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7791
48c0e4e9 7792 if (nr_mmu_pages)
0de10343 7793 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7794
3ea3b7fa
WL		 7795 /*
7796 * Dirty logging tracks sptes in 4k granularity, meaning that large
7797 * sptes have to be split. If live migration is successful, the guest
7798 * in the source machine will be destroyed and large sptes will be
7799 * created in the destination. However, if the guest continues to run
7800 * in the source machine (for example if live migration fails), small
7801 * sptes will remain around and cause bad performance.
7802 *
7803 * Scan sptes if dirty logging has been stopped, dropping those
7804 * which can be collapsed into a single large-page spte. Later
7805 * page faults will create the large-page sptes.
7806 */
7807 if ((change != KVM_MR_DELETE) &&
7808 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7809 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7810 kvm_mmu_zap_collapsible_sptes(kvm, new);
7811
c972f3b1 7812 /*
88178fd4 7813 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7814 *
88178fd4
KH		 7815 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7816 * been zapped so no dirty logging staff is needed for old slot. For
7817 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7818 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7819 *
7820 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7821 */
88178fd4 7822 if (change != KVM_MR_DELETE)
f36f3f28 7823 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7824}
1d737c8a 7825
2df72e9b 7826void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7827{
6ca18b69 7828 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7829}
7830
2df72e9b
MT		 7831void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7832 struct kvm_memory_slot *slot)
7833{
6ca18b69 7834 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7835}
7836
1d737c8a
ZX		 7837int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7838{
b6b8a145
JK		 7839 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7840 kvm_x86_ops->check_nested_events(vcpu, false);
7841
af585b92
GN		 7842 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7843 !vcpu->arch.apf.halted)
7844 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7845 || kvm_apic_has_events(vcpu)
6aef266c 7846 || vcpu->arch.pv.pv_unhalted
7460fb4a 7847 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7848 (kvm_arch_interrupt_allowed(vcpu) &&
7849 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7850}
5736199a 7851
b6d33834 7852int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7853{
b6d33834 7854 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7855}
78646121
GN		 7856
7857int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7858{
7859 return kvm_x86_ops->interrupt_allowed(vcpu);
7860}
229456fc 7861
82b32774 7862unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7863{
82b32774
NA		 7864 if (is_64_bit_mode(vcpu))
7865 return kvm_rip_read(vcpu);
7866 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7867 kvm_rip_read(vcpu));
7868}
7869EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7870
82b32774
NA		 7871bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7872{
7873 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7874}
7875EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7876
94fe45da
JK		 7877unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7878{
7879 unsigned long rflags;
7880
7881 rflags = kvm_x86_ops->get_rflags(vcpu);
7882 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7883 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7884 return rflags;
7885}
7886EXPORT_SYMBOL_GPL(kvm_get_rflags);
7887
6addfc42 7888static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7889{
7890 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7891 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7892 rflags |= X86_EFLAGS_TF;
94fe45da 7893 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7894}
7895
7896void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7897{
7898 __kvm_set_rflags(vcpu, rflags);
3842d135 7899 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7900}
7901EXPORT_SYMBOL_GPL(kvm_set_rflags);
7902
56028d08
GN		 7903void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7904{
7905 int r;
7906
fb67e14f 7907 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7908 work->wakeup_all)
56028d08
GN		 7909 return;
7910
7911 r = kvm_mmu_reload(vcpu);
7912 if (unlikely(r))
7913 return;
7914
fb67e14f
XG		 7915 if (!vcpu->arch.mmu.direct_map &&
7916 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7917 return;
7918
56028d08
GN		 7919 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7920}
7921
af585b92
GN		 7922static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7923{
7924 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7925}
7926
7927static inline u32 kvm_async_pf_next_probe(u32 key)
7928{
7929 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7930}
7931
7932static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7933{
7934 u32 key = kvm_async_pf_hash_fn(gfn);
7935
7936 while (vcpu->arch.apf.gfns[key] != ~0)
7937 key = kvm_async_pf_next_probe(key);
7938
7939 vcpu->arch.apf.gfns[key] = gfn;
7940}
7941
7942static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7943{
7944 int i;
7945 u32 key = kvm_async_pf_hash_fn(gfn);
7946
7947 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7948 (vcpu->arch.apf.gfns[key] != gfn &&
7949 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7950 key = kvm_async_pf_next_probe(key);
7951
7952 return key;
7953}
7954
7955bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7956{
7957 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7958}
7959
7960static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7961{
7962 u32 i, j, k;
7963
7964 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7965 while (true) {
7966 vcpu->arch.apf.gfns[i] = ~0;
7967 do {
7968 j = kvm_async_pf_next_probe(j);
7969 if (vcpu->arch.apf.gfns[j] == ~0)
7970 return;
7971 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7972 /*
7973 * k lies cyclically in ]i,j]
7974 * | i.k.j |
7975 * |....j i.k.| or |.k..j i...|
7976 */
7977 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7978 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7979 i = j;
7980 }
7981}
7982
7c90705b
GN		 7983static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7984{
7985
7986 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7987 sizeof(val));
7988}
7989
af585b92
GN		 7990void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7991 struct kvm_async_pf *work)
7992{
6389ee94
AK		 7993 struct x86_exception fault;
7994
7c90705b 7995 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7996 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7997
7998 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7999 (vcpu->arch.apf.send_user_only &&
8000 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8001 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8002 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8003 fault.vector = PF_VECTOR;
8004 fault.error_code_valid = true;
8005 fault.error_code = 0;
8006 fault.nested_page_fault = false;
8007 fault.address = work->arch.token;
8008 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8009 }
af585b92
GN		 8010}
8011
8012void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8013 struct kvm_async_pf *work)
8014{
6389ee94
AK		 8015 struct x86_exception fault;
8016
7c90705b 8017 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8018 if (work->wakeup_all)
7c90705b
GN		 8019 work->arch.token = ~0; /* broadcast wakeup */
8020 else
8021 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8022
8023 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8024 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8025 fault.vector = PF_VECTOR;
8026 fault.error_code_valid = true;
8027 fault.error_code = 0;
8028 fault.nested_page_fault = false;
8029 fault.address = work->arch.token;
8030 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8031 }
e6d53e3b 8032 vcpu->arch.apf.halted = false;
a4fa1635 8033 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8034}
8035
8036bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8037{
8038 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8039 return true;
8040 else
8041 return !kvm_event_needs_reinjection(vcpu) &&
8042 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8043}
8044
5544eb9b
PB		 8045void kvm_arch_start_assignment(struct kvm *kvm)
8046{
8047 atomic_inc(&kvm->arch.assigned_device_count);
8048}
8049EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8050
8051void kvm_arch_end_assignment(struct kvm *kvm)
8052{
8053 atomic_dec(&kvm->arch.assigned_device_count);
8054}
8055EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8056
8057bool kvm_arch_has_assigned_device(struct kvm *kvm)
8058{
8059 return atomic_read(&kvm->arch.assigned_device_count);
8060}
8061EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8062
e0f0bbc5
AW		 8063void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8064{
8065 atomic_inc(&kvm->arch.noncoherent_dma_count);
8066}
8067EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8068
8069void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8070{
8071 atomic_dec(&kvm->arch.noncoherent_dma_count);
8072}
8073EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8074
8075bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8076{
8077 return atomic_read(&kvm->arch.noncoherent_dma_count);
8078}
8079EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8080
229456fc 8081EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8082EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8083EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8084EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8085EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8086EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8087EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8088EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8089EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8090EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8091EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8092EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8093EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8094EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8095EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8096EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git