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Commit | Line | Data |
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dc7c9a1a WD |
1 | /* |
2 | * Driver for NAND support, Rick Bronson | |
3 | * borrowed heavily from: | |
4 | * (c) 1999 Machine Vision Holdings, Inc. | |
5 | * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org> | |
384cc687 WD |
6 | * |
7 | * Added 16-bit nand support | |
8 | * (C) 2004 Texas Instruments | |
dc7c9a1a WD |
9 | */ |
10 | ||
11 | #include <common.h> | |
dc7c9a1a WD |
12 | #include <command.h> |
13 | #include <malloc.h> | |
14 | #include <asm/io.h> | |
a3d991bd | 15 | #include <watchdog.h> |
dc7c9a1a WD |
16 | |
17 | #ifdef CONFIG_SHOW_BOOT_PROGRESS | |
18 | # include <status_led.h> | |
19 | # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) | |
20 | #else | |
21 | # define SHOW_BOOT_PROGRESS(arg) | |
22 | #endif | |
23 | ||
24 | #if (CONFIG_COMMANDS & CFG_CMD_NAND) | |
25 | ||
dc7c9a1a WD |
26 | #include <linux/mtd/nand.h> |
27 | #include <linux/mtd/nand_ids.h> | |
7a8e9bed | 28 | #include <jffs2/jffs2.h> |
dc7c9a1a | 29 | |
1f4bb37d WD |
30 | #ifdef CONFIG_OMAP1510 |
31 | void archflashwp(void *archdata, int wp); | |
32 | #endif | |
33 | ||
34 | #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) | |
35 | ||
dc7c9a1a WD |
36 | /* |
37 | * Definition of the out of band configuration structure | |
38 | */ | |
39 | struct nand_oob_config { | |
40 | int ecc_pos[6]; /* position of ECC bytes inside oob */ | |
41 | int badblock_pos; /* position of bad block flag inside oob -1 = inactive */ | |
42 | int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */ | |
43 | } oob_config = { {0}, 0, 0}; | |
44 | ||
a43278a4 | 45 | #undef NAND_DEBUG |
dc7c9a1a | 46 | #undef PSYCHO_DEBUG |
7a8e9bed WD |
47 | |
48 | /* ****************** WARNING ********************* | |
49 | * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will | |
50 | * erase (or at least attempt to erase) blocks that are marked | |
51 | * bad. This can be very handy if you are _sure_ that the block | |
52 | * is OK, say because you marked a good block bad to test bad | |
53 | * block handling and you are done testing, or if you have | |
54 | * accidentally marked blocks bad. | |
55 | * | |
56 | * Erasing factory marked bad blocks is a _bad_ idea. If the | |
57 | * erase succeeds there is no reliable way to find them again, | |
58 | * and attempting to program or erase bad blocks can affect | |
59 | * the data in _other_ (good) blocks. | |
60 | */ | |
61 | #define ALLOW_ERASE_BAD_DEBUG 0 | |
dc7c9a1a WD |
62 | |
63 | #define CONFIG_MTD_NAND_ECC /* enable ECC */ | |
1f4bb37d | 64 | #define CONFIG_MTD_NAND_ECC_JFFS2 |
dc7c9a1a | 65 | |
7a8e9bed WD |
66 | /* bits for nand_rw() `cmd'; or together as needed */ |
67 | #define NANDRW_READ 0x01 | |
68 | #define NANDRW_WRITE 0x00 | |
69 | #define NANDRW_JFFS2 0x02 | |
a3d991bd | 70 | #define NANDRW_JFFS2_SKIP 0x04 |
7a8e9bed | 71 | |
dc7c9a1a WD |
72 | /* |
73 | * Function Prototypes | |
74 | */ | |
75 | static void nand_print(struct nand_chip *nand); | |
13a5695b | 76 | int nand_rw (struct nand_chip* nand, int cmd, |
dc7c9a1a WD |
77 | size_t start, size_t len, |
78 | size_t * retlen, u_char * buf); | |
13a5695b | 79 | int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); |
dc7c9a1a WD |
80 | static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, |
81 | size_t * retlen, u_char *buf, u_char *ecc_code); | |
82 | static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, | |
83 | size_t * retlen, const u_char * buf, u_char * ecc_code); | |
7a8e9bed WD |
84 | static void nand_print_bad(struct nand_chip *nand); |
85 | static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, | |
86 | size_t * retlen, u_char * buf); | |
87 | static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, | |
88 | size_t * retlen, const u_char * buf); | |
1f4bb37d | 89 | static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); |
dc7c9a1a WD |
90 | #ifdef CONFIG_MTD_NAND_ECC |
91 | static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); | |
92 | static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); | |
93 | #endif | |
94 | ||
7a8e9bed | 95 | struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; |
dc7c9a1a WD |
96 | |
97 | /* Current NAND Device */ | |
98 | static int curr_device = -1; | |
99 | ||
100 | /* ------------------------------------------------------------------------- */ | |
101 | ||
102 | int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
103 | { | |
104 | int rcode = 0; | |
105 | ||
106 | switch (argc) { | |
107 | case 0: | |
108 | case 1: | |
109 | printf ("Usage:\n%s\n", cmdtp->usage); | |
110 | return 1; | |
111 | case 2: | |
8bde7f77 | 112 | if (strcmp(argv[1],"info") == 0) { |
dc7c9a1a WD |
113 | int i; |
114 | ||
115 | putc ('\n'); | |
116 | ||
117 | for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) { | |
118 | if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) | |
119 | continue; /* list only known devices */ | |
120 | printf ("Device %d: ", i); | |
121 | nand_print(&nand_dev_desc[i]); | |
122 | } | |
123 | return 0; | |
124 | ||
125 | } else if (strcmp(argv[1],"device") == 0) { | |
126 | if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { | |
127 | puts ("\nno devices available\n"); | |
128 | return 1; | |
129 | } | |
130 | printf ("\nDevice %d: ", curr_device); | |
131 | nand_print(&nand_dev_desc[curr_device]); | |
132 | return 0; | |
7a8e9bed WD |
133 | |
134 | } else if (strcmp(argv[1],"bad") == 0) { | |
135 | if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { | |
136 | puts ("\nno devices available\n"); | |
137 | return 1; | |
138 | } | |
139 | printf ("\nDevice %d bad blocks:\n", curr_device); | |
140 | nand_print_bad(&nand_dev_desc[curr_device]); | |
141 | return 0; | |
142 | ||
dc7c9a1a WD |
143 | } |
144 | printf ("Usage:\n%s\n", cmdtp->usage); | |
145 | return 1; | |
146 | case 3: | |
147 | if (strcmp(argv[1],"device") == 0) { | |
148 | int dev = (int)simple_strtoul(argv[2], NULL, 10); | |
149 | ||
150 | printf ("\nDevice %d: ", dev); | |
151 | if (dev >= CFG_MAX_NAND_DEVICE) { | |
152 | puts ("unknown device\n"); | |
153 | return 1; | |
154 | } | |
155 | nand_print(&nand_dev_desc[dev]); | |
156 | /*nand_print (dev);*/ | |
157 | ||
158 | if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { | |
159 | return 1; | |
160 | } | |
161 | ||
162 | curr_device = dev; | |
163 | ||
164 | puts ("... is now current device\n"); | |
165 | ||
166 | return 0; | |
167 | } | |
7a8e9bed WD |
168 | else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) { |
169 | struct nand_chip* nand = &nand_dev_desc[curr_device]; | |
170 | ulong off = 0; | |
171 | ulong size = nand->totlen; | |
172 | int ret; | |
173 | ||
174 | printf ("\nNAND erase: device %d offset %ld, size %ld ... ", | |
175 | curr_device, off, size); | |
176 | ||
177 | ret = nand_erase (nand, off, size, 1); | |
178 | ||
179 | printf("%s\n", ret ? "ERROR" : "OK"); | |
180 | ||
181 | return ret; | |
182 | } | |
dc7c9a1a WD |
183 | |
184 | printf ("Usage:\n%s\n", cmdtp->usage); | |
185 | return 1; | |
186 | default: | |
187 | /* at least 4 args */ | |
188 | ||
7a8e9bed WD |
189 | if (strncmp(argv[1], "read", 4) == 0 || |
190 | strncmp(argv[1], "write", 5) == 0) { | |
dc7c9a1a WD |
191 | ulong addr = simple_strtoul(argv[2], NULL, 16); |
192 | ulong off = simple_strtoul(argv[3], NULL, 16); | |
193 | ulong size = simple_strtoul(argv[4], NULL, 16); | |
7a8e9bed WD |
194 | int cmd = (strncmp(argv[1], "read", 4) == 0) ? |
195 | NANDRW_READ : NANDRW_WRITE; | |
dc7c9a1a | 196 | int ret, total; |
7a8e9bed WD |
197 | char* cmdtail = strchr(argv[1], '.'); |
198 | ||
199 | if (cmdtail && !strncmp(cmdtail, ".oob", 2)) { | |
200 | /* read out-of-band data */ | |
201 | if (cmd & NANDRW_READ) { | |
202 | ret = nand_read_oob(nand_dev_desc + curr_device, | |
77ddac94 | 203 | off, size, (size_t *)&total, |
7a8e9bed WD |
204 | (u_char*)addr); |
205 | } | |
206 | else { | |
207 | ret = nand_write_oob(nand_dev_desc + curr_device, | |
77ddac94 | 208 | off, size, (size_t *)&total, |
7a8e9bed WD |
209 | (u_char*)addr); |
210 | } | |
211 | return ret; | |
212 | } | |
213 | else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) | |
214 | cmd |= NANDRW_JFFS2; /* skip bad blocks */ | |
a3d991bd WD |
215 | else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { |
216 | cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ | |
217 | if (cmd & NANDRW_READ) | |
218 | cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ | |
219 | } | |
7a8e9bed WD |
220 | #ifdef SXNI855T |
221 | /* need ".e" same as ".j" for compatibility with older units */ | |
222 | else if (cmdtail && !strcmp(cmdtail, ".e")) | |
223 | cmd |= NANDRW_JFFS2; /* skip bad blocks */ | |
224 | #endif | |
a842a6d2 SR |
225 | #ifdef CFG_NAND_SKIP_BAD_DOT_I |
226 | /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ | |
227 | /* ".i" for image -> read skips bad block (no 0xff) */ | |
9bcf2ab4 | 228 | else if (cmdtail && !strcmp(cmdtail, ".i")) { |
a842a6d2 SR |
229 | cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ |
230 | if (cmd & NANDRW_READ) | |
231 | cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ | |
9bcf2ab4 | 232 | } |
a842a6d2 | 233 | #endif /* CFG_NAND_SKIP_BAD_DOT_I */ |
7a8e9bed WD |
234 | else if (cmdtail) { |
235 | printf ("Usage:\n%s\n", cmdtp->usage); | |
236 | return 1; | |
237 | } | |
dc7c9a1a WD |
238 | |
239 | printf ("\nNAND %s: device %d offset %ld, size %ld ... ", | |
7a8e9bed WD |
240 | (cmd & NANDRW_READ) ? "read" : "write", |
241 | curr_device, off, size); | |
dc7c9a1a WD |
242 | |
243 | ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size, | |
77ddac94 | 244 | (size_t *)&total, (u_char*)addr); |
dc7c9a1a | 245 | |
1f4bb37d | 246 | printf (" %d bytes %s: %s\n", total, |
998eaaec | 247 | (cmd & NANDRW_READ) ? "read" : "written", |
dc7c9a1a WD |
248 | ret ? "ERROR" : "OK"); |
249 | ||
250 | return ret; | |
7a8e9bed WD |
251 | } else if (strcmp(argv[1],"erase") == 0 && |
252 | (argc == 4 || strcmp("clean", argv[2]) == 0)) { | |
253 | int clean = argc == 5; | |
254 | ulong off = simple_strtoul(argv[2 + clean], NULL, 16); | |
255 | ulong size = simple_strtoul(argv[3 + clean], NULL, 16); | |
dc7c9a1a WD |
256 | int ret; |
257 | ||
258 | printf ("\nNAND erase: device %d offset %ld, size %ld ... ", | |
259 | curr_device, off, size); | |
260 | ||
7a8e9bed | 261 | ret = nand_erase (nand_dev_desc + curr_device, off, size, clean); |
dc7c9a1a WD |
262 | |
263 | printf("%s\n", ret ? "ERROR" : "OK"); | |
264 | ||
265 | return ret; | |
266 | } else { | |
267 | printf ("Usage:\n%s\n", cmdtp->usage); | |
268 | rcode = 1; | |
269 | } | |
270 | ||
271 | return rcode; | |
272 | } | |
273 | } | |
274 | ||
0d498393 WD |
275 | U_BOOT_CMD( |
276 | nand, 5, 1, do_nand, | |
b0fce99b WD |
277 | "nand - NAND sub-system\n", |
278 | "info - show available NAND devices\n" | |
279 | "nand device [dev] - show or set current device\n" | |
a3d991bd | 280 | "nand read[.jffs2[s]] addr off size\n" |
b0fce99b WD |
281 | "nand write[.jffs2] addr off size - read/write `size' bytes starting\n" |
282 | " at offset `off' to/from memory address `addr'\n" | |
283 | "nand erase [clean] [off size] - erase `size' bytes from\n" | |
284 | " offset `off' (entire device if not specified)\n" | |
285 | "nand bad - show bad blocks\n" | |
286 | "nand read.oob addr off size - read out-of-band data\n" | |
287 | "nand write.oob addr off size - read out-of-band data\n" | |
288 | ); | |
289 | ||
dc7c9a1a WD |
290 | int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
291 | { | |
292 | char *boot_device = NULL; | |
293 | char *ep; | |
294 | int dev; | |
295 | ulong cnt; | |
296 | ulong addr; | |
297 | ulong offset = 0; | |
298 | image_header_t *hdr; | |
299 | int rcode = 0; | |
300 | switch (argc) { | |
301 | case 1: | |
302 | addr = CFG_LOAD_ADDR; | |
303 | boot_device = getenv ("bootdevice"); | |
304 | break; | |
305 | case 2: | |
306 | addr = simple_strtoul(argv[1], NULL, 16); | |
307 | boot_device = getenv ("bootdevice"); | |
308 | break; | |
309 | case 3: | |
310 | addr = simple_strtoul(argv[1], NULL, 16); | |
311 | boot_device = argv[2]; | |
312 | break; | |
313 | case 4: | |
314 | addr = simple_strtoul(argv[1], NULL, 16); | |
315 | boot_device = argv[2]; | |
316 | offset = simple_strtoul(argv[3], NULL, 16); | |
317 | break; | |
318 | default: | |
319 | printf ("Usage:\n%s\n", cmdtp->usage); | |
320 | SHOW_BOOT_PROGRESS (-1); | |
321 | return 1; | |
322 | } | |
323 | ||
324 | if (!boot_device) { | |
325 | puts ("\n** No boot device **\n"); | |
326 | SHOW_BOOT_PROGRESS (-1); | |
327 | return 1; | |
328 | } | |
329 | ||
330 | dev = simple_strtoul(boot_device, &ep, 16); | |
331 | ||
332 | if ((dev >= CFG_MAX_NAND_DEVICE) || | |
333 | (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) { | |
334 | printf ("\n** Device %d not available\n", dev); | |
335 | SHOW_BOOT_PROGRESS (-1); | |
336 | return 1; | |
337 | } | |
338 | ||
7a8e9bed | 339 | printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n", |
dc7c9a1a WD |
340 | dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, |
341 | offset); | |
342 | ||
7a8e9bed | 343 | if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset, |
dc7c9a1a WD |
344 | SECTORSIZE, NULL, (u_char *)addr)) { |
345 | printf ("** Read error on %d\n", dev); | |
346 | SHOW_BOOT_PROGRESS (-1); | |
347 | return 1; | |
348 | } | |
349 | ||
350 | hdr = (image_header_t *)addr; | |
351 | ||
352 | if (ntohl(hdr->ih_magic) == IH_MAGIC) { | |
353 | ||
354 | print_image_hdr (hdr); | |
355 | ||
356 | cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); | |
357 | cnt -= SECTORSIZE; | |
358 | } else { | |
359 | printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); | |
360 | SHOW_BOOT_PROGRESS (-1); | |
361 | return 1; | |
362 | } | |
363 | ||
7a8e9bed | 364 | if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, |
dc7c9a1a WD |
365 | NULL, (u_char *)(addr+SECTORSIZE))) { |
366 | printf ("** Read error on %d\n", dev); | |
367 | SHOW_BOOT_PROGRESS (-1); | |
368 | return 1; | |
369 | } | |
370 | ||
371 | /* Loading ok, update default load address */ | |
372 | ||
373 | load_addr = addr; | |
374 | ||
375 | /* Check if we should attempt an auto-start */ | |
376 | if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { | |
377 | char *local_args[2]; | |
378 | extern int do_bootm (cmd_tbl_t *, int, int, char *[]); | |
379 | ||
380 | local_args[0] = argv[0]; | |
381 | local_args[1] = NULL; | |
382 | ||
7a8e9bed | 383 | printf ("Automatic boot of image at addr 0x%08lx ...\n", addr); |
dc7c9a1a WD |
384 | |
385 | do_bootm (cmdtp, 0, 1, local_args); | |
386 | rcode = 1; | |
387 | } | |
388 | return rcode; | |
389 | } | |
390 | ||
0d498393 WD |
391 | U_BOOT_CMD( |
392 | nboot, 4, 1, do_nandboot, | |
b0fce99b WD |
393 | "nboot - boot from NAND device\n", |
394 | "loadAddr dev\n" | |
395 | ); | |
396 | ||
7a8e9bed WD |
397 | /* returns 0 if block containing pos is OK: |
398 | * valid erase block and | |
399 | * not marked bad, or no bad mark position is specified | |
400 | * returns 1 if marked bad or otherwise invalid | |
401 | */ | |
384cc687 | 402 | int check_block (struct nand_chip *nand, unsigned long pos) |
7a8e9bed | 403 | { |
77ddac94 | 404 | size_t retlen; |
7a8e9bed | 405 | uint8_t oob_data; |
384cc687 | 406 | uint16_t oob_data16[6]; |
7a8e9bed WD |
407 | int page0 = pos & (-nand->erasesize); |
408 | int page1 = page0 + nand->oobblock; | |
409 | int badpos = oob_config.badblock_pos; | |
410 | ||
411 | if (pos >= nand->totlen) | |
412 | return 1; | |
413 | ||
414 | if (badpos < 0) | |
415 | return 0; /* no way to check, assume OK */ | |
416 | ||
384cc687 WD |
417 | if (nand->bus16) { |
418 | if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16) | |
419 | || (oob_data16[2] & 0xff00) != 0xff00) | |
420 | return 1; | |
421 | if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16) | |
422 | || (oob_data16[2] & 0xff00) != 0xff00) | |
423 | return 1; | |
424 | } else { | |
425 | /* Note - bad block marker can be on first or second page */ | |
77ddac94 | 426 | if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data) |
384cc687 | 427 | || oob_data != 0xff |
77ddac94 | 428 | || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data) |
384cc687 WD |
429 | || oob_data != 0xff) |
430 | return 1; | |
431 | } | |
7a8e9bed WD |
432 | |
433 | return 0; | |
434 | } | |
8bde7f77 | 435 | |
7a8e9bed WD |
436 | /* print bad blocks in NAND flash */ |
437 | static void nand_print_bad(struct nand_chip* nand) | |
438 | { | |
439 | unsigned long pos; | |
440 | ||
441 | for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { | |
442 | if (check_block(nand, pos)) | |
443 | printf(" 0x%8.8lx\n", pos); | |
444 | } | |
445 | puts("\n"); | |
446 | } | |
447 | ||
448 | /* cmd: 0: NANDRW_WRITE write, fail on bad block | |
449 | * 1: NANDRW_READ read, fail on bad block | |
450 | * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks | |
451 | * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks | |
a3d991bd | 452 | * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks |
7a8e9bed | 453 | */ |
13a5695b | 454 | int nand_rw (struct nand_chip* nand, int cmd, |
dc7c9a1a WD |
455 | size_t start, size_t len, |
456 | size_t * retlen, u_char * buf) | |
457 | { | |
1f4bb37d | 458 | int ret = 0, n, total = 0; |
dc7c9a1a | 459 | char eccbuf[6]; |
7a8e9bed WD |
460 | /* eblk (once set) is the start of the erase block containing the |
461 | * data being processed. | |
462 | */ | |
463 | unsigned long eblk = ~0; /* force mismatch on first pass */ | |
464 | unsigned long erasesize = nand->erasesize; | |
465 | ||
466 | while (len) { | |
467 | if ((start & (-erasesize)) != eblk) { | |
468 | /* have crossed into new erase block, deal with | |
469 | * it if it is sure marked bad. | |
470 | */ | |
471 | eblk = start & (-erasesize); /* start of block */ | |
472 | if (check_block(nand, eblk)) { | |
473 | if (cmd == (NANDRW_READ | NANDRW_JFFS2)) { | |
474 | while (len > 0 && | |
475 | start - eblk < erasesize) { | |
476 | *(buf++) = 0xff; | |
477 | ++start; | |
478 | ++total; | |
479 | --len; | |
480 | } | |
481 | continue; | |
384cc687 | 482 | } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { |
a3d991bd WD |
483 | start += erasesize; |
484 | continue; | |
384cc687 | 485 | } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { |
7a8e9bed WD |
486 | /* skip bad block */ |
487 | start += erasesize; | |
488 | continue; | |
384cc687 | 489 | } else { |
7a8e9bed WD |
490 | ret = 1; |
491 | break; | |
492 | } | |
493 | } | |
494 | } | |
dc7c9a1a WD |
495 | /* The ECC will not be calculated correctly if |
496 | less than 512 is written or read */ | |
1f4bb37d WD |
497 | /* Is request at least 512 bytes AND it starts on a proper boundry */ |
498 | if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200)) | |
499 | printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n"); | |
500 | ||
384cc687 | 501 | if (cmd & NANDRW_READ) { |
7a8e9bed WD |
502 | ret = nand_read_ecc(nand, start, |
503 | min(len, eblk + erasesize - start), | |
77ddac94 | 504 | (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); |
384cc687 | 505 | } else { |
7a8e9bed WD |
506 | ret = nand_write_ecc(nand, start, |
507 | min(len, eblk + erasesize - start), | |
77ddac94 | 508 | (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); |
384cc687 | 509 | } |
dc7c9a1a WD |
510 | |
511 | if (ret) | |
512 | break; | |
513 | ||
514 | start += n; | |
515 | buf += n; | |
516 | total += n; | |
517 | len -= n; | |
518 | } | |
519 | if (retlen) | |
520 | *retlen = total; | |
521 | ||
522 | return ret; | |
523 | } | |
524 | ||
525 | static void nand_print(struct nand_chip *nand) | |
0db5bca8 | 526 | { |
7a8e9bed WD |
527 | if (nand->numchips > 1) { |
528 | printf("%s at 0x%lx,\n" | |
529 | "\t %d chips %s, size %d MB, \n" | |
530 | "\t total size %ld MB, sector size %ld kB\n", | |
531 | nand->name, nand->IO_ADDR, nand->numchips, | |
532 | nand->chips_name, 1 << (nand->chipshift - 20), | |
533 | nand->totlen >> 20, nand->erasesize >> 10); | |
534 | } | |
535 | else { | |
8bde7f77 | 536 | printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR); |
7a8e9bed WD |
537 | print_size(nand->totlen, ", "); |
538 | print_size(nand->erasesize, " sector)\n"); | |
dc7c9a1a WD |
539 | } |
540 | } | |
541 | ||
542 | /* ------------------------------------------------------------------------- */ | |
543 | ||
1f4bb37d | 544 | static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) |
dc7c9a1a WD |
545 | { |
546 | /* This is inline, to optimise the common case, where it's ready instantly */ | |
547 | int ret = 0; | |
dc7c9a1a | 548 | |
1f4bb37d WD |
549 | #ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ |
550 | if(ale_wait) | |
551 | NAND_WAIT_READY(nand); /* do the worst case 25us wait */ | |
552 | else | |
553 | udelay(10); | |
554 | #else /* has functional r/b signal */ | |
12f34241 | 555 | NAND_WAIT_READY(nand); |
1f4bb37d | 556 | #endif |
dc7c9a1a WD |
557 | return ret; |
558 | } | |
559 | ||
560 | /* NanD_Command: Send a flash command to the flash chip */ | |
561 | ||
562 | static inline int NanD_Command(struct nand_chip *nand, unsigned char command) | |
563 | { | |
564 | unsigned long nandptr = nand->IO_ADDR; | |
565 | ||
566 | /* Assert the CLE (Command Latch Enable) line to the flash chip */ | |
567 | NAND_CTL_SETCLE(nandptr); | |
568 | ||
569 | /* Send the command */ | |
570 | WRITE_NAND_COMMAND(command, nandptr); | |
571 | ||
572 | /* Lower the CLE line */ | |
573 | NAND_CTL_CLRCLE(nandptr); | |
574 | ||
1f4bb37d WD |
575 | #ifdef NAND_NO_RB |
576 | if(command == NAND_CMD_RESET){ | |
577 | u_char ret_val; | |
578 | NanD_Command(nand, NAND_CMD_STATUS); | |
384cc687 | 579 | do { |
1f4bb37d WD |
580 | ret_val = READ_NAND(nandptr);/* wait till ready */ |
581 | } while((ret_val & 0x40) != 0x40); | |
582 | } | |
583 | #endif | |
584 | return NanD_WaitReady(nand, 0); | |
dc7c9a1a WD |
585 | } |
586 | ||
587 | /* NanD_Address: Set the current address for the flash chip */ | |
588 | ||
589 | static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) | |
0db5bca8 WD |
590 | { |
591 | unsigned long nandptr; | |
592 | int i; | |
dc7c9a1a | 593 | |
0db5bca8 | 594 | nandptr = nand->IO_ADDR; |
dc7c9a1a WD |
595 | |
596 | /* Assert the ALE (Address Latch Enable) line to the flash chip */ | |
0db5bca8 WD |
597 | NAND_CTL_SETALE(nandptr); |
598 | ||
599 | /* Send the address */ | |
600 | /* Devices with 256-byte page are addressed as: | |
601 | * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) | |
602 | * there is no device on the market with page256 | |
603 | * and more than 24 bits. | |
604 | * Devices with 512-byte page are addressed as: | |
605 | * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) | |
606 | * 25-31 is sent only if the chip support it. | |
607 | * bit 8 changes the read command to be sent | |
608 | * (NAND_CMD_READ0 or NAND_CMD_READ1). | |
dc7c9a1a WD |
609 | */ |
610 | ||
0db5bca8 WD |
611 | if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) |
612 | WRITE_NAND_ADDRESS(ofs, nandptr); | |
dc7c9a1a | 613 | |
0db5bca8 | 614 | ofs = ofs >> nand->page_shift; |
dc7c9a1a | 615 | |
384cc687 WD |
616 | if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) { |
617 | for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) { | |
0db5bca8 | 618 | WRITE_NAND_ADDRESS(ofs, nandptr); |
384cc687 WD |
619 | } |
620 | } | |
dc7c9a1a | 621 | |
0db5bca8 WD |
622 | /* Lower the ALE line */ |
623 | NAND_CTL_CLRALE(nandptr); | |
dc7c9a1a | 624 | |
0db5bca8 | 625 | /* Wait for the chip to respond */ |
1f4bb37d | 626 | return NanD_WaitReady(nand, 1); |
0db5bca8 | 627 | } |
dc7c9a1a WD |
628 | |
629 | /* NanD_SelectChip: Select a given flash chip within the current floor */ | |
630 | ||
631 | static inline int NanD_SelectChip(struct nand_chip *nand, int chip) | |
632 | { | |
633 | /* Wait for it to be ready */ | |
1f4bb37d | 634 | return NanD_WaitReady(nand, 0); |
dc7c9a1a WD |
635 | } |
636 | ||
637 | /* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */ | |
638 | ||
639 | static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip) | |
640 | { | |
641 | int mfr, id, i; | |
642 | ||
0db5bca8 | 643 | NAND_ENABLE_CE(nand); /* set pin low */ |
dc7c9a1a WD |
644 | /* Reset the chip */ |
645 | if (NanD_Command(nand, NAND_CMD_RESET)) { | |
646 | #ifdef NAND_DEBUG | |
647 | printf("NanD_Command (reset) for %d,%d returned true\n", | |
648 | floor, chip); | |
649 | #endif | |
0db5bca8 | 650 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
651 | return 0; |
652 | } | |
653 | ||
654 | /* Read the NAND chip ID: 1. Send ReadID command */ | |
655 | if (NanD_Command(nand, NAND_CMD_READID)) { | |
656 | #ifdef NAND_DEBUG | |
657 | printf("NanD_Command (ReadID) for %d,%d returned true\n", | |
658 | floor, chip); | |
659 | #endif | |
0db5bca8 | 660 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
661 | return 0; |
662 | } | |
663 | ||
664 | /* Read the NAND chip ID: 2. Send address byte zero */ | |
665 | NanD_Address(nand, ADDR_COLUMN, 0); | |
666 | ||
667 | /* Read the manufacturer and device id codes from the device */ | |
668 | ||
669 | mfr = READ_NAND(nand->IO_ADDR); | |
670 | ||
671 | id = READ_NAND(nand->IO_ADDR); | |
672 | ||
8bde7f77 | 673 | NAND_DISABLE_CE(nand); /* set pin high */ |
9dd41a7b | 674 | |
4d816774 | 675 | #ifdef NAND_DEBUG |
9dd41a7b | 676 | printf("NanD_Command (ReadID) got %x %x\n", mfr, id); |
4d816774 | 677 | #endif |
9dd41a7b WD |
678 | if (mfr == 0xff || mfr == 0) { |
679 | /* No response - return failure */ | |
0db5bca8 WD |
680 | return 0; |
681 | } | |
dc7c9a1a WD |
682 | |
683 | /* Check it's the same as the first chip we identified. | |
684 | * M-Systems say that any given nand_chip device should only | |
685 | * contain _one_ type of flash part, although that's not a | |
686 | * hardware restriction. */ | |
687 | if (nand->mfr) { | |
384cc687 | 688 | if (nand->mfr == mfr && nand->id == id) { |
dc7c9a1a | 689 | return 1; /* This is another the same the first */ |
384cc687 | 690 | } else { |
dc7c9a1a WD |
691 | printf("Flash chip at floor %d, chip %d is different:\n", |
692 | floor, chip); | |
384cc687 | 693 | } |
dc7c9a1a WD |
694 | } |
695 | ||
696 | /* Print and store the manufacturer and ID codes. */ | |
697 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { | |
698 | if (mfr == nand_flash_ids[i].manufacture_id && | |
699 | id == nand_flash_ids[i].model_id) { | |
700 | #ifdef NAND_DEBUG | |
701 | printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, " | |
702 | "Chip ID: 0x%2.2X (%s)\n", mfr, id, | |
703 | nand_flash_ids[i].name); | |
704 | #endif | |
705 | if (!nand->mfr) { | |
706 | nand->mfr = mfr; | |
707 | nand->id = id; | |
708 | nand->chipshift = | |
709 | nand_flash_ids[i].chipshift; | |
710 | nand->page256 = nand_flash_ids[i].page256; | |
7a8e9bed | 711 | nand->eccsize = 256; |
dc7c9a1a WD |
712 | if (nand->page256) { |
713 | nand->oobblock = 256; | |
714 | nand->oobsize = 8; | |
715 | nand->page_shift = 8; | |
716 | } else { | |
717 | nand->oobblock = 512; | |
718 | nand->oobsize = 16; | |
719 | nand->page_shift = 9; | |
720 | } | |
384cc687 WD |
721 | nand->pageadrlen = nand_flash_ids[i].pageadrlen; |
722 | nand->erasesize = nand_flash_ids[i].erasesize; | |
723 | nand->chips_name = nand_flash_ids[i].name; | |
724 | nand->bus16 = nand_flash_ids[i].bus16; | |
725 | return 1; | |
dc7c9a1a WD |
726 | } |
727 | return 0; | |
728 | } | |
729 | } | |
730 | ||
731 | ||
732 | #ifdef NAND_DEBUG | |
733 | /* We haven't fully identified the chip. Print as much as we know. */ | |
734 | printf("Unknown flash chip found: %2.2X %2.2X\n", | |
735 | id, mfr); | |
736 | #endif | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
741 | /* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */ | |
742 | ||
743 | static void NanD_ScanChips(struct nand_chip *nand) | |
744 | { | |
745 | int floor, chip; | |
746 | int numchips[NAND_MAX_FLOORS]; | |
747 | int maxchips = NAND_MAX_CHIPS; | |
748 | int ret = 1; | |
749 | ||
750 | nand->numchips = 0; | |
751 | nand->mfr = 0; | |
752 | nand->id = 0; | |
753 | ||
754 | ||
755 | /* For each floor, find the number of valid chips it contains */ | |
756 | for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { | |
757 | ret = 1; | |
758 | numchips[floor] = 0; | |
759 | for (chip = 0; chip < maxchips && ret != 0; chip++) { | |
760 | ||
761 | ret = NanD_IdentChip(nand, floor, chip); | |
762 | if (ret) { | |
763 | numchips[floor]++; | |
764 | nand->numchips++; | |
765 | } | |
766 | } | |
767 | } | |
768 | ||
769 | /* If there are none at all that we recognise, bail */ | |
770 | if (!nand->numchips) { | |
a43278a4 | 771 | #ifdef NAND_DEBUG |
4d816774 | 772 | puts ("No NAND flash chips recognised.\n"); |
a43278a4 | 773 | #endif |
dc7c9a1a WD |
774 | return; |
775 | } | |
776 | ||
777 | /* Allocate an array to hold the information for each chip */ | |
778 | nand->chips = malloc(sizeof(struct Nand) * nand->numchips); | |
779 | if (!nand->chips) { | |
780 | puts ("No memory for allocating chip info structures\n"); | |
781 | return; | |
782 | } | |
783 | ||
784 | ret = 0; | |
785 | ||
786 | /* Fill out the chip array with {floor, chipno} for each | |
787 | * detected chip in the device. */ | |
788 | for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { | |
789 | for (chip = 0; chip < numchips[floor]; chip++) { | |
790 | nand->chips[ret].floor = floor; | |
791 | nand->chips[ret].chip = chip; | |
792 | nand->chips[ret].curadr = 0; | |
793 | nand->chips[ret].curmode = 0x50; | |
794 | ret++; | |
795 | } | |
796 | } | |
797 | ||
798 | /* Calculate and print the total size of the device */ | |
799 | nand->totlen = nand->numchips * (1 << nand->chipshift); | |
800 | ||
801 | #ifdef NAND_DEBUG | |
802 | printf("%d flash chips found. Total nand_chip size: %ld MB\n", | |
803 | nand->numchips, nand->totlen >> 20); | |
804 | #endif | |
805 | } | |
0db5bca8 | 806 | |
dc7c9a1a | 807 | /* we need to be fast here, 1 us per read translates to 1 second per meg */ |
384cc687 | 808 | static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr) |
0db5bca8 | 809 | { |
7a8e9bed | 810 | unsigned long nandptr = nand->IO_ADDR; |
0db5bca8 | 811 | |
384cc687 WD |
812 | NanD_Command (nand, NAND_CMD_READ0); |
813 | ||
814 | if (nand->bus16) { | |
815 | u16 val; | |
816 | ||
817 | while (cntr >= 16) { | |
818 | val = READ_NAND (nandptr); | |
819 | *data_buf++ = val & 0xff; | |
820 | *data_buf++ = val >> 8; | |
821 | val = READ_NAND (nandptr); | |
822 | *data_buf++ = val & 0xff; | |
823 | *data_buf++ = val >> 8; | |
824 | val = READ_NAND (nandptr); | |
825 | *data_buf++ = val & 0xff; | |
826 | *data_buf++ = val >> 8; | |
827 | val = READ_NAND (nandptr); | |
828 | *data_buf++ = val & 0xff; | |
829 | *data_buf++ = val >> 8; | |
830 | val = READ_NAND (nandptr); | |
831 | *data_buf++ = val & 0xff; | |
832 | *data_buf++ = val >> 8; | |
833 | val = READ_NAND (nandptr); | |
834 | *data_buf++ = val & 0xff; | |
835 | *data_buf++ = val >> 8; | |
836 | val = READ_NAND (nandptr); | |
837 | *data_buf++ = val & 0xff; | |
838 | *data_buf++ = val >> 8; | |
839 | val = READ_NAND (nandptr); | |
840 | *data_buf++ = val & 0xff; | |
841 | *data_buf++ = val >> 8; | |
842 | cntr -= 16; | |
843 | } | |
844 | ||
845 | while (cntr > 0) { | |
846 | val = READ_NAND (nandptr); | |
847 | *data_buf++ = val & 0xff; | |
848 | *data_buf++ = val >> 8; | |
849 | cntr -= 2; | |
850 | } | |
851 | } else { | |
852 | while (cntr >= 16) { | |
853 | *data_buf++ = READ_NAND (nandptr); | |
854 | *data_buf++ = READ_NAND (nandptr); | |
855 | *data_buf++ = READ_NAND (nandptr); | |
856 | *data_buf++ = READ_NAND (nandptr); | |
857 | *data_buf++ = READ_NAND (nandptr); | |
858 | *data_buf++ = READ_NAND (nandptr); | |
859 | *data_buf++ = READ_NAND (nandptr); | |
860 | *data_buf++ = READ_NAND (nandptr); | |
861 | *data_buf++ = READ_NAND (nandptr); | |
862 | *data_buf++ = READ_NAND (nandptr); | |
863 | *data_buf++ = READ_NAND (nandptr); | |
864 | *data_buf++ = READ_NAND (nandptr); | |
865 | *data_buf++ = READ_NAND (nandptr); | |
866 | *data_buf++ = READ_NAND (nandptr); | |
867 | *data_buf++ = READ_NAND (nandptr); | |
868 | *data_buf++ = READ_NAND (nandptr); | |
869 | cntr -= 16; | |
870 | } | |
871 | ||
872 | while (cntr > 0) { | |
873 | *data_buf++ = READ_NAND (nandptr); | |
874 | cntr--; | |
875 | } | |
0db5bca8 WD |
876 | } |
877 | } | |
dc7c9a1a | 878 | |
dc7c9a1a WD |
879 | /* |
880 | * NAND read with ECC | |
881 | */ | |
882 | static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, | |
883 | size_t * retlen, u_char *buf, u_char *ecc_code) | |
884 | { | |
885 | int col, page; | |
886 | int ecc_status = 0; | |
887 | #ifdef CONFIG_MTD_NAND_ECC | |
888 | int j; | |
889 | int ecc_failed = 0; | |
890 | u_char *data_poi; | |
891 | u_char ecc_calc[6]; | |
892 | #endif | |
dc7c9a1a WD |
893 | |
894 | /* Do not allow reads past end of device */ | |
895 | if ((start + len) > nand->totlen) { | |
384cc687 WD |
896 | printf ("%s: Attempt read beyond end of device %x %x %x\n", |
897 | __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen); | |
dc7c9a1a WD |
898 | *retlen = 0; |
899 | return -1; | |
900 | } | |
901 | ||
902 | /* First we calculate the starting page */ | |
0db5bca8 WD |
903 | /*page = shr(start, nand->page_shift);*/ |
904 | page = start >> nand->page_shift; | |
dc7c9a1a WD |
905 | |
906 | /* Get raw starting column */ | |
907 | col = start & (nand->oobblock - 1); | |
908 | ||
909 | /* Initialize return value */ | |
910 | *retlen = 0; | |
911 | ||
912 | /* Select the NAND device */ | |
913 | NAND_ENABLE_CE(nand); /* set pin low */ | |
914 | ||
915 | /* Loop until all data read */ | |
916 | while (*retlen < len) { | |
917 | ||
dc7c9a1a | 918 | #ifdef CONFIG_MTD_NAND_ECC |
dc7c9a1a WD |
919 | /* Do we have this page in cache ? */ |
920 | if (nand->cache_page == page) | |
921 | goto readdata; | |
922 | /* Send the read command */ | |
923 | NanD_Command(nand, NAND_CMD_READ0); | |
384cc687 WD |
924 | if (nand->bus16) { |
925 | NanD_Address(nand, ADDR_COLUMN_PAGE, | |
926 | (page << nand->page_shift) + (col >> 1)); | |
927 | } else { | |
928 | NanD_Address(nand, ADDR_COLUMN_PAGE, | |
929 | (page << nand->page_shift) + col); | |
930 | } | |
931 | ||
dc7c9a1a | 932 | /* Read in a page + oob data */ |
7a8e9bed | 933 | NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize); |
dc7c9a1a WD |
934 | |
935 | /* copy data into cache, for read out of cache and if ecc fails */ | |
384cc687 WD |
936 | if (nand->data_cache) { |
937 | memcpy (nand->data_cache, nand->data_buf, | |
938 | nand->oobblock + nand->oobsize); | |
939 | } | |
dc7c9a1a WD |
940 | |
941 | /* Pick the ECC bytes out of the oob data */ | |
384cc687 | 942 | for (j = 0; j < 6; j++) { |
dc7c9a1a | 943 | ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])]; |
384cc687 | 944 | } |
dc7c9a1a WD |
945 | |
946 | /* Calculate the ECC and verify it */ | |
947 | /* If block was not written with ECC, skip ECC */ | |
948 | if (oob_config.eccvalid_pos != -1 && | |
949 | (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) { | |
950 | ||
951 | nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]); | |
952 | switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) { | |
953 | case -1: | |
0db5bca8 | 954 | printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); |
dc7c9a1a WD |
955 | ecc_failed++; |
956 | break; | |
957 | case 1: | |
958 | case 2: /* transfer ECC corrected data to cache */ | |
7a8e9bed WD |
959 | if (nand->data_cache) |
960 | memcpy (nand->data_cache, nand->data_buf, 256); | |
dc7c9a1a WD |
961 | break; |
962 | } | |
963 | } | |
964 | ||
965 | if (oob_config.eccvalid_pos != -1 && | |
966 | nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) { | |
967 | ||
968 | nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]); | |
969 | switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) { | |
970 | case -1: | |
0db5bca8 | 971 | printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); |
dc7c9a1a WD |
972 | ecc_failed++; |
973 | break; | |
974 | case 1: | |
975 | case 2: /* transfer ECC corrected data to cache */ | |
976 | if (nand->data_cache) | |
977 | memcpy (&nand->data_cache[256], &nand->data_buf[256], 256); | |
978 | break; | |
979 | } | |
980 | } | |
981 | readdata: | |
982 | /* Read the data from ECC data buffer into return buffer */ | |
983 | data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf; | |
984 | data_poi += col; | |
985 | if ((*retlen + (nand->oobblock - col)) >= len) { | |
7a8e9bed | 986 | memcpy (buf + *retlen, data_poi, len - *retlen); |
dc7c9a1a WD |
987 | *retlen = len; |
988 | } else { | |
7a8e9bed | 989 | memcpy (buf + *retlen, data_poi, nand->oobblock - col); |
dc7c9a1a WD |
990 | *retlen += nand->oobblock - col; |
991 | } | |
992 | /* Set cache page address, invalidate, if ecc_failed */ | |
993 | nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1; | |
994 | ||
995 | ecc_status += ecc_failed; | |
996 | ecc_failed = 0; | |
997 | ||
998 | #else | |
999 | /* Send the read command */ | |
1000 | NanD_Command(nand, NAND_CMD_READ0); | |
384cc687 WD |
1001 | if (nand->bus16) { |
1002 | NanD_Address(nand, ADDR_COLUMN_PAGE, | |
1003 | (page << nand->page_shift) + (col >> 1)); | |
1004 | } else { | |
1005 | NanD_Address(nand, ADDR_COLUMN_PAGE, | |
1006 | (page << nand->page_shift) + col); | |
1007 | } | |
1008 | ||
dc7c9a1a WD |
1009 | /* Read the data directly into the return buffer */ |
1010 | if ((*retlen + (nand->oobblock - col)) >= len) { | |
7a8e9bed | 1011 | NanD_ReadBuf(nand, buf + *retlen, len - *retlen); |
dc7c9a1a WD |
1012 | *retlen = len; |
1013 | /* We're done */ | |
1014 | continue; | |
1015 | } else { | |
7a8e9bed | 1016 | NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col); |
dc7c9a1a WD |
1017 | *retlen += nand->oobblock - col; |
1018 | } | |
1019 | #endif | |
1020 | /* For subsequent reads align to page boundary. */ | |
1021 | col = 0; | |
1022 | /* Increment page address */ | |
1023 | page++; | |
1024 | } | |
1025 | ||
1026 | /* De-select the NAND device */ | |
0db5bca8 | 1027 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1028 | |
1029 | /* | |
1030 | * Return success, if no ECC failures, else -EIO | |
1031 | * fs driver will take care of that, because | |
1032 | * retlen == desired len and result == -EIO | |
1033 | */ | |
1034 | return ecc_status ? -1 : 0; | |
1035 | } | |
1036 | ||
dc7c9a1a WD |
1037 | /* |
1038 | * Nand_page_program function is used for write and writev ! | |
1039 | */ | |
1040 | static int nand_write_page (struct nand_chip *nand, | |
1041 | int page, int col, int last, u_char * ecc_code) | |
1042 | { | |
1043 | ||
1044 | int i; | |
dc7c9a1a | 1045 | unsigned long nandptr = nand->IO_ADDR; |
384cc687 | 1046 | |
1f4bb37d | 1047 | #ifdef CONFIG_MTD_NAND_ECC |
dc7c9a1a WD |
1048 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE |
1049 | int ecc_bytes = (nand->oobblock == 512) ? 6 : 3; | |
1050 | #endif | |
1051 | #endif | |
1052 | /* pad oob area */ | |
1053 | for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++) | |
1054 | nand->data_buf[i] = 0xff; | |
1055 | ||
1056 | #ifdef CONFIG_MTD_NAND_ECC | |
1057 | /* Zero out the ECC array */ | |
1058 | for (i = 0; i < 6; i++) | |
1059 | ecc_code[i] = 0x00; | |
1060 | ||
1061 | /* Read back previous written data, if col > 0 */ | |
1062 | if (col) { | |
384cc687 WD |
1063 | NanD_Command (nand, NAND_CMD_READ0); |
1064 | if (nand->bus16) { | |
1065 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1066 | (page << nand->page_shift) + (col >> 1)); | |
1067 | } else { | |
1068 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1069 | (page << nand->page_shift) + col); | |
1070 | } | |
1071 | ||
1072 | if (nand->bus16) { | |
1073 | u16 val; | |
1074 | ||
1075 | for (i = 0; i < col; i += 2) { | |
1076 | val = READ_NAND (nandptr); | |
1077 | nand->data_buf[i] = val & 0xff; | |
1078 | nand->data_buf[i + 1] = val >> 8; | |
1079 | } | |
1080 | } else { | |
1081 | for (i = 0; i < col; i++) | |
1082 | nand->data_buf[i] = READ_NAND (nandptr); | |
1083 | } | |
dc7c9a1a WD |
1084 | } |
1085 | ||
1086 | /* Calculate and write the ECC if we have enough data */ | |
1087 | if ((col < nand->eccsize) && (last >= nand->eccsize)) { | |
1088 | nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0])); | |
384cc687 WD |
1089 | for (i = 0; i < 3; i++) { |
1090 | nand->data_buf[(nand->oobblock + | |
1091 | oob_config.ecc_pos[i])] = ecc_code[i]; | |
1092 | } | |
1093 | if (oob_config.eccvalid_pos != -1) { | |
1094 | nand->data_buf[nand->oobblock + | |
1095 | oob_config.eccvalid_pos] = 0xf0; | |
1096 | } | |
dc7c9a1a WD |
1097 | } |
1098 | ||
1099 | /* Calculate and write the second ECC if we have enough data */ | |
1100 | if ((nand->oobblock == 512) && (last == nand->oobblock)) { | |
1101 | nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3])); | |
384cc687 WD |
1102 | for (i = 3; i < 6; i++) { |
1103 | nand->data_buf[(nand->oobblock + | |
1104 | oob_config.ecc_pos[i])] = ecc_code[i]; | |
1105 | } | |
1106 | if (oob_config.eccvalid_pos != -1) { | |
1107 | nand->data_buf[nand->oobblock + | |
1108 | oob_config.eccvalid_pos] &= 0x0f; | |
1109 | } | |
dc7c9a1a WD |
1110 | } |
1111 | #endif | |
1112 | /* Prepad for partial page programming !!! */ | |
1113 | for (i = 0; i < col; i++) | |
1114 | nand->data_buf[i] = 0xff; | |
1115 | ||
1116 | /* Postpad for partial page programming !!! oob is already padded */ | |
1117 | for (i = last; i < nand->oobblock; i++) | |
1118 | nand->data_buf[i] = 0xff; | |
1119 | ||
1120 | /* Send command to begin auto page programming */ | |
384cc687 WD |
1121 | NanD_Command (nand, NAND_CMD_READ0); |
1122 | NanD_Command (nand, NAND_CMD_SEQIN); | |
1123 | if (nand->bus16) { | |
1124 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1125 | (page << nand->page_shift) + (col >> 1)); | |
1126 | } else { | |
1127 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1128 | (page << nand->page_shift) + col); | |
1129 | } | |
dc7c9a1a WD |
1130 | |
1131 | /* Write out complete page of data */ | |
384cc687 WD |
1132 | if (nand->bus16) { |
1133 | for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) { | |
1134 | WRITE_NAND (nand->data_buf[i] + | |
1135 | (nand->data_buf[i + 1] << 8), | |
1136 | nand->IO_ADDR); | |
1137 | } | |
1138 | } else { | |
1139 | for (i = 0; i < (nand->oobblock + nand->oobsize); i++) | |
1140 | WRITE_NAND (nand->data_buf[i], nand->IO_ADDR); | |
1141 | } | |
dc7c9a1a WD |
1142 | |
1143 | /* Send command to actually program the data */ | |
384cc687 WD |
1144 | NanD_Command (nand, NAND_CMD_PAGEPROG); |
1145 | NanD_Command (nand, NAND_CMD_STATUS); | |
1f4bb37d | 1146 | #ifdef NAND_NO_RB |
384cc687 WD |
1147 | { |
1148 | u_char ret_val; | |
dc7c9a1a | 1149 | |
384cc687 WD |
1150 | do { |
1151 | ret_val = READ_NAND (nandptr); /* wait till ready */ | |
1152 | } while ((ret_val & 0x40) != 0x40); | |
1f4bb37d WD |
1153 | } |
1154 | #endif | |
dc7c9a1a | 1155 | /* See if device thinks it succeeded */ |
384cc687 WD |
1156 | if (READ_NAND (nand->IO_ADDR) & 0x01) { |
1157 | printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, | |
1158 | page); | |
dc7c9a1a WD |
1159 | return -1; |
1160 | } | |
1161 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
1162 | /* | |
1163 | * The NAND device assumes that it is always writing to | |
1164 | * a cleanly erased page. Hence, it performs its internal | |
1165 | * write verification only on bits that transitioned from | |
1166 | * 1 to 0. The device does NOT verify the whole page on a | |
1167 | * byte by byte basis. It is possible that the page was | |
1168 | * not completely erased or the page is becoming unusable | |
1169 | * due to wear. The read with ECC would catch the error | |
1170 | * later when the ECC page check fails, but we would rather | |
1171 | * catch it early in the page write stage. Better to write | |
1172 | * no data than invalid data. | |
1173 | */ | |
1174 | ||
1175 | /* Send command to read back the page */ | |
1176 | if (col < nand->eccsize) | |
384cc687 | 1177 | NanD_Command (nand, NAND_CMD_READ0); |
dc7c9a1a | 1178 | else |
384cc687 WD |
1179 | NanD_Command (nand, NAND_CMD_READ1); |
1180 | if (nand->bus16) { | |
1181 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1182 | (page << nand->page_shift) + (col >> 1)); | |
1183 | } else { | |
1184 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1185 | (page << nand->page_shift) + col); | |
1186 | } | |
dc7c9a1a WD |
1187 | |
1188 | /* Loop through and verify the data */ | |
384cc687 WD |
1189 | if (nand->bus16) { |
1190 | for (i = col; i < last; i = +2) { | |
1191 | if ((nand->data_buf[i] + | |
1192 | (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) { | |
1193 | printf ("%s: Failed write verify, page 0x%08x ", | |
1194 | __FUNCTION__, page); | |
1195 | return -1; | |
1196 | } | |
1197 | } | |
1198 | } else { | |
1199 | for (i = col; i < last; i++) { | |
1200 | if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) { | |
1201 | printf ("%s: Failed write verify, page 0x%08x ", | |
1202 | __FUNCTION__, page); | |
1203 | return -1; | |
1204 | } | |
dc7c9a1a WD |
1205 | } |
1206 | } | |
1207 | ||
1208 | #ifdef CONFIG_MTD_NAND_ECC | |
1209 | /* | |
1210 | * We also want to check that the ECC bytes wrote | |
1211 | * correctly for the same reasons stated above. | |
1212 | */ | |
384cc687 WD |
1213 | NanD_Command (nand, NAND_CMD_READOOB); |
1214 | if (nand->bus16) { | |
1215 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1216 | (page << nand->page_shift) + (col >> 1)); | |
1217 | } else { | |
1218 | NanD_Address (nand, ADDR_COLUMN_PAGE, | |
1219 | (page << nand->page_shift) + col); | |
1220 | } | |
1221 | if (nand->bus16) { | |
1222 | for (i = 0; i < nand->oobsize; i += 2) { | |
81b83c9e SR |
1223 | u16 val; |
1224 | ||
384cc687 WD |
1225 | val = READ_NAND (nand->IO_ADDR); |
1226 | nand->data_buf[i] = val & 0xff; | |
1227 | nand->data_buf[i + 1] = val >> 8; | |
1228 | } | |
1229 | } else { | |
1230 | for (i = 0; i < nand->oobsize; i++) { | |
1231 | nand->data_buf[i] = READ_NAND (nand->IO_ADDR); | |
1232 | } | |
1233 | } | |
dc7c9a1a WD |
1234 | for (i = 0; i < ecc_bytes; i++) { |
1235 | if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { | |
0db5bca8 | 1236 | printf ("%s: Failed ECC write " |
384cc687 WD |
1237 | "verify, page 0x%08x, " |
1238 | "%6i bytes were succesful\n", | |
1239 | __FUNCTION__, page, i); | |
dc7c9a1a WD |
1240 | return -1; |
1241 | } | |
1242 | } | |
384cc687 WD |
1243 | #endif /* CONFIG_MTD_NAND_ECC */ |
1244 | #endif /* CONFIG_MTD_NAND_VERIFY_WRITE */ | |
dc7c9a1a WD |
1245 | return 0; |
1246 | } | |
0db5bca8 | 1247 | |
dc7c9a1a WD |
1248 | static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, |
1249 | size_t * retlen, const u_char * buf, u_char * ecc_code) | |
1250 | { | |
1251 | int i, page, col, cnt, ret = 0; | |
1252 | ||
1253 | /* Do not allow write past end of device */ | |
1254 | if ((to + len) > nand->totlen) { | |
0db5bca8 | 1255 | printf ("%s: Attempt to write past end of page\n", __FUNCTION__); |
dc7c9a1a WD |
1256 | return -1; |
1257 | } | |
1258 | ||
1259 | /* Shift to get page */ | |
1260 | page = ((int) to) >> nand->page_shift; | |
1261 | ||
1262 | /* Get the starting column */ | |
1263 | col = to & (nand->oobblock - 1); | |
1264 | ||
1265 | /* Initialize return length value */ | |
1266 | *retlen = 0; | |
1267 | ||
1268 | /* Select the NAND device */ | |
1f4bb37d WD |
1269 | #ifdef CONFIG_OMAP1510 |
1270 | archflashwp(0,0); | |
1271 | #endif | |
384cc687 WD |
1272 | #ifdef CFG_NAND_WP |
1273 | NAND_WP_OFF(); | |
1274 | #endif | |
1275 | ||
1f4bb37d | 1276 | NAND_ENABLE_CE(nand); /* set pin low */ |
dc7c9a1a WD |
1277 | |
1278 | /* Check the WP bit */ | |
0db5bca8 | 1279 | NanD_Command(nand, NAND_CMD_STATUS); |
dc7c9a1a | 1280 | if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { |
0db5bca8 | 1281 | printf ("%s: Device is write protected!!!\n", __FUNCTION__); |
dc7c9a1a WD |
1282 | ret = -1; |
1283 | goto out; | |
1284 | } | |
1285 | ||
1286 | /* Loop until all data is written */ | |
1287 | while (*retlen < len) { | |
1288 | /* Invalidate cache, if we write to this page */ | |
1289 | if (nand->cache_page == page) | |
1290 | nand->cache_page = -1; | |
1291 | ||
1292 | /* Write data into buffer */ | |
384cc687 WD |
1293 | if ((col + len) >= nand->oobblock) { |
1294 | for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) { | |
dc7c9a1a | 1295 | nand->data_buf[i] = buf[(*retlen + cnt)]; |
384cc687 WD |
1296 | } |
1297 | } else { | |
1298 | for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) { | |
dc7c9a1a | 1299 | nand->data_buf[i] = buf[(*retlen + cnt)]; |
384cc687 WD |
1300 | } |
1301 | } | |
dc7c9a1a WD |
1302 | /* We use the same function for write and writev !) */ |
1303 | ret = nand_write_page (nand, page, col, i, ecc_code); | |
1304 | if (ret) | |
1305 | goto out; | |
1306 | ||
1307 | /* Next data start at page boundary */ | |
1308 | col = 0; | |
1309 | ||
1310 | /* Update written bytes count */ | |
1311 | *retlen += cnt; | |
1312 | ||
1313 | /* Increment page address */ | |
1314 | page++; | |
1315 | } | |
1316 | ||
1317 | /* Return happy */ | |
1318 | *retlen = len; | |
1319 | ||
1320 | out: | |
1321 | /* De-select the NAND device */ | |
0db5bca8 | 1322 | NAND_DISABLE_CE(nand); /* set pin high */ |
1f4bb37d WD |
1323 | #ifdef CONFIG_OMAP1510 |
1324 | archflashwp(0,1); | |
1325 | #endif | |
384cc687 WD |
1326 | #ifdef CFG_NAND_WP |
1327 | NAND_WP_ON(); | |
1328 | #endif | |
1329 | ||
dc7c9a1a WD |
1330 | return ret; |
1331 | } | |
1332 | ||
7a8e9bed WD |
1333 | /* read from the 16 bytes of oob data that correspond to a 512 byte |
1334 | * page or 2 256-byte pages. | |
dc7c9a1a | 1335 | */ |
dc7c9a1a | 1336 | static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, |
7a8e9bed | 1337 | size_t * retlen, u_char * buf) |
dc7c9a1a | 1338 | { |
7a8e9bed | 1339 | int len256 = 0; |
dc7c9a1a | 1340 | struct Nand *mychip; |
0db5bca8 | 1341 | int ret = 0; |
dc7c9a1a | 1342 | |
7a8e9bed | 1343 | mychip = &nand->chips[ofs >> nand->chipshift]; |
dc7c9a1a WD |
1344 | |
1345 | /* update address for 2M x 8bit devices. OOB starts on the second */ | |
1346 | /* page to maintain compatibility with nand_read_ecc. */ | |
1347 | if (nand->page256) { | |
1348 | if (!(ofs & 0x8)) | |
1349 | ofs += 0x100; | |
1350 | else | |
1351 | ofs -= 0x8; | |
1352 | } | |
1353 | ||
7a8e9bed | 1354 | NAND_ENABLE_CE(nand); /* set pin low */ |
dc7c9a1a | 1355 | NanD_Command(nand, NAND_CMD_READOOB); |
384cc687 WD |
1356 | if (nand->bus16) { |
1357 | NanD_Address(nand, ADDR_COLUMN_PAGE, | |
1358 | ((ofs >> nand->page_shift) << nand->page_shift) + | |
1359 | ((ofs & (nand->oobblock - 1)) >> 1)); | |
1360 | } else { | |
1361 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); | |
1362 | } | |
dc7c9a1a WD |
1363 | |
1364 | /* treat crossing 8-byte OOB data for 2M x 8bit devices */ | |
1365 | /* Note: datasheet says it should automaticaly wrap to the */ | |
1366 | /* next OOB block, but it didn't work here. mf. */ | |
1367 | if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { | |
1368 | len256 = (ofs | 0x7) + 1 - ofs; | |
1369 | NanD_ReadBuf(nand, buf, len256); | |
1370 | ||
1371 | NanD_Command(nand, NAND_CMD_READOOB); | |
1372 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); | |
1373 | } | |
1374 | ||
1375 | NanD_ReadBuf(nand, &buf[len256], len - len256); | |
1376 | ||
1377 | *retlen = len; | |
1378 | /* Reading the full OOB data drops us off of the end of the page, | |
8bde7f77 WD |
1379 | * causing the flash device to go into busy mode, so we need |
1380 | * to wait until ready 11.4.1 and Toshiba TC58256FT nands */ | |
dc7c9a1a | 1381 | |
1f4bb37d | 1382 | ret = NanD_WaitReady(nand, 1); |
8bde7f77 | 1383 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1384 | |
1385 | return ret; | |
1386 | ||
1387 | } | |
7a8e9bed WD |
1388 | |
1389 | /* write to the 16 bytes of oob data that correspond to a 512 byte | |
1390 | * page or 2 256-byte pages. | |
1391 | */ | |
dc7c9a1a WD |
1392 | static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, |
1393 | size_t * retlen, const u_char * buf) | |
1394 | { | |
1395 | int len256 = 0; | |
7a8e9bed | 1396 | int i; |
dc7c9a1a WD |
1397 | unsigned long nandptr = nand->IO_ADDR; |
1398 | ||
1399 | #ifdef PSYCHO_DEBUG | |
1400 | printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", | |
1401 | (long)ofs, len, buf[0], buf[1], buf[2], buf[3], | |
1402 | buf[8], buf[9], buf[14],buf[15]); | |
1403 | #endif | |
1404 | ||
7a8e9bed WD |
1405 | NAND_ENABLE_CE(nand); /* set pin low to enable chip */ |
1406 | ||
dc7c9a1a WD |
1407 | /* Reset the chip */ |
1408 | NanD_Command(nand, NAND_CMD_RESET); | |
1409 | ||
1410 | /* issue the Read2 command to set the pointer to the Spare Data Area. */ | |
1411 | NanD_Command(nand, NAND_CMD_READOOB); | |
384cc687 WD |
1412 | if (nand->bus16) { |
1413 | NanD_Address(nand, ADDR_COLUMN_PAGE, | |
1414 | ((ofs >> nand->page_shift) << nand->page_shift) + | |
1415 | ((ofs & (nand->oobblock - 1)) >> 1)); | |
1416 | } else { | |
1417 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); | |
1418 | } | |
dc7c9a1a WD |
1419 | |
1420 | /* update address for 2M x 8bit devices. OOB starts on the second */ | |
1421 | /* page to maintain compatibility with nand_read_ecc. */ | |
1422 | if (nand->page256) { | |
1423 | if (!(ofs & 0x8)) | |
1424 | ofs += 0x100; | |
1425 | else | |
1426 | ofs -= 0x8; | |
1427 | } | |
1428 | ||
1429 | /* issue the Serial Data In command to initial the Page Program process */ | |
1430 | NanD_Command(nand, NAND_CMD_SEQIN); | |
384cc687 WD |
1431 | if (nand->bus16) { |
1432 | NanD_Address(nand, ADDR_COLUMN_PAGE, | |
1433 | ((ofs >> nand->page_shift) << nand->page_shift) + | |
1434 | ((ofs & (nand->oobblock - 1)) >> 1)); | |
1435 | } else { | |
1436 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); | |
1437 | } | |
dc7c9a1a WD |
1438 | |
1439 | /* treat crossing 8-byte OOB data for 2M x 8bit devices */ | |
1440 | /* Note: datasheet says it should automaticaly wrap to the */ | |
1441 | /* next OOB block, but it didn't work here. mf. */ | |
1442 | if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { | |
1443 | len256 = (ofs | 0x7) + 1 - ofs; | |
7a8e9bed WD |
1444 | for (i = 0; i < len256; i++) |
1445 | WRITE_NAND(buf[i], nandptr); | |
dc7c9a1a WD |
1446 | |
1447 | NanD_Command(nand, NAND_CMD_PAGEPROG); | |
1448 | NanD_Command(nand, NAND_CMD_STATUS); | |
1f4bb37d WD |
1449 | #ifdef NAND_NO_RB |
1450 | { u_char ret_val; | |
384cc687 WD |
1451 | do { |
1452 | ret_val = READ_NAND(nandptr); /* wait till ready */ | |
1453 | } while ((ret_val & 0x40) != 0x40); | |
1f4bb37d WD |
1454 | } |
1455 | #endif | |
dc7c9a1a WD |
1456 | if (READ_NAND(nandptr) & 1) { |
1457 | puts ("Error programming oob data\n"); | |
1458 | /* There was an error */ | |
7a8e9bed | 1459 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1460 | *retlen = 0; |
1461 | return -1; | |
1462 | } | |
1463 | NanD_Command(nand, NAND_CMD_SEQIN); | |
1464 | NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); | |
1465 | } | |
1466 | ||
384cc687 WD |
1467 | if (nand->bus16) { |
1468 | for (i = len256; i < len; i += 2) { | |
1469 | WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr); | |
1470 | } | |
1471 | } else { | |
1472 | for (i = len256; i < len; i++) | |
1473 | WRITE_NAND(buf[i], nandptr); | |
1474 | } | |
dc7c9a1a WD |
1475 | |
1476 | NanD_Command(nand, NAND_CMD_PAGEPROG); | |
1477 | NanD_Command(nand, NAND_CMD_STATUS); | |
1f4bb37d | 1478 | #ifdef NAND_NO_RB |
384cc687 WD |
1479 | { u_char ret_val; |
1480 | do { | |
1481 | ret_val = READ_NAND(nandptr); /* wait till ready */ | |
1482 | } while ((ret_val & 0x40) != 0x40); | |
1f4bb37d WD |
1483 | } |
1484 | #endif | |
dc7c9a1a WD |
1485 | if (READ_NAND(nandptr) & 1) { |
1486 | puts ("Error programming oob data\n"); | |
1487 | /* There was an error */ | |
7a8e9bed | 1488 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1489 | *retlen = 0; |
1490 | return -1; | |
1491 | } | |
1492 | ||
7a8e9bed | 1493 | NAND_DISABLE_CE(nand); /* set pin high */ |
dc7c9a1a WD |
1494 | *retlen = len; |
1495 | return 0; | |
1496 | ||
1497 | } | |
dc7c9a1a | 1498 | |
13a5695b | 1499 | int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) |
dc7c9a1a | 1500 | { |
7a8e9bed WD |
1501 | /* This is defined as a structure so it will work on any system |
1502 | * using native endian jffs2 (the default). | |
1503 | */ | |
1504 | static struct jffs2_unknown_node clean_marker = { | |
1505 | JFFS2_MAGIC_BITMASK, | |
1506 | JFFS2_NODETYPE_CLEANMARKER, | |
1507 | 8 /* 8 bytes in this node */ | |
1508 | }; | |
dc7c9a1a WD |
1509 | unsigned long nandptr; |
1510 | struct Nand *mychip; | |
85ec0bcc | 1511 | int ret = 0; |
dc7c9a1a WD |
1512 | |
1513 | if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) { | |
1514 | printf ("Offset and size must be sector aligned, erasesize = %d\n", | |
8bde7f77 | 1515 | (int) nand->erasesize); |
dc7c9a1a WD |
1516 | return -1; |
1517 | } | |
1518 | ||
1519 | nandptr = nand->IO_ADDR; | |
1520 | ||
85ec0bcc | 1521 | /* Select the NAND device */ |
1f4bb37d WD |
1522 | #ifdef CONFIG_OMAP1510 |
1523 | archflashwp(0,0); | |
384cc687 WD |
1524 | #endif |
1525 | #ifdef CFG_NAND_WP | |
1526 | NAND_WP_OFF(); | |
1f4bb37d WD |
1527 | #endif |
1528 | NAND_ENABLE_CE(nand); /* set pin low */ | |
85ec0bcc WD |
1529 | |
1530 | /* Check the WP bit */ | |
1531 | NanD_Command(nand, NAND_CMD_STATUS); | |
1532 | if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { | |
1533 | printf ("nand_write_ecc: Device is write protected!!!\n"); | |
1534 | ret = -1; | |
1535 | goto out; | |
1536 | } | |
1537 | ||
0db5bca8 WD |
1538 | /* Check the WP bit */ |
1539 | NanD_Command(nand, NAND_CMD_STATUS); | |
1540 | if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { | |
1541 | printf ("%s: Device is write protected!!!\n", __FUNCTION__); | |
1542 | ret = -1; | |
1543 | goto out; | |
1544 | } | |
1545 | ||
dc7c9a1a WD |
1546 | /* FIXME: Do nand in the background. Use timers or schedule_task() */ |
1547 | while(len) { | |
0db5bca8 WD |
1548 | /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/ |
1549 | mychip = &nand->chips[ofs >> nand->chipshift]; | |
dc7c9a1a | 1550 | |
7a8e9bed WD |
1551 | /* always check for bad block first, genuine bad blocks |
1552 | * should _never_ be erased. | |
1553 | */ | |
1554 | if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) { | |
1555 | /* Select the NAND device */ | |
1556 | NAND_ENABLE_CE(nand); /* set pin low */ | |
1557 | ||
1558 | NanD_Command(nand, NAND_CMD_ERASE1); | |
1559 | NanD_Address(nand, ADDR_PAGE, ofs); | |
1560 | NanD_Command(nand, NAND_CMD_ERASE2); | |
1561 | ||
1562 | NanD_Command(nand, NAND_CMD_STATUS); | |
1563 | ||
1f4bb37d | 1564 | #ifdef NAND_NO_RB |
384cc687 WD |
1565 | { u_char ret_val; |
1566 | do { | |
1567 | ret_val = READ_NAND(nandptr); /* wait till ready */ | |
1568 | } while ((ret_val & 0x40) != 0x40); | |
1f4bb37d WD |
1569 | } |
1570 | #endif | |
7a8e9bed WD |
1571 | if (READ_NAND(nandptr) & 1) { |
1572 | printf ("%s: Error erasing at 0x%lx\n", | |
1573 | __FUNCTION__, (long)ofs); | |
1574 | /* There was an error */ | |
1575 | ret = -1; | |
1576 | goto out; | |
1577 | } | |
1578 | if (clean) { | |
1579 | int n; /* return value not used */ | |
1580 | int p, l; | |
1581 | ||
1582 | /* clean marker position and size depend | |
1583 | * on the page size, since 256 byte pages | |
1584 | * only have 8 bytes of oob data | |
1585 | */ | |
1586 | if (nand->page256) { | |
1587 | p = NAND_JFFS2_OOB8_FSDAPOS; | |
1588 | l = NAND_JFFS2_OOB8_FSDALEN; | |
384cc687 | 1589 | } else { |
7a8e9bed WD |
1590 | p = NAND_JFFS2_OOB16_FSDAPOS; |
1591 | l = NAND_JFFS2_OOB16_FSDALEN; | |
1592 | } | |
dc7c9a1a | 1593 | |
77ddac94 | 1594 | ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n, |
7a8e9bed WD |
1595 | (u_char *)&clean_marker); |
1596 | /* quit here if write failed */ | |
1597 | if (ret) | |
1598 | goto out; | |
1599 | } | |
dc7c9a1a WD |
1600 | } |
1601 | ofs += nand->erasesize; | |
1602 | len -= nand->erasesize; | |
1603 | } | |
1604 | ||
85ec0bcc WD |
1605 | out: |
1606 | /* De-select the NAND device */ | |
1607 | NAND_DISABLE_CE(nand); /* set pin high */ | |
1f4bb37d WD |
1608 | #ifdef CONFIG_OMAP1510 |
1609 | archflashwp(0,1); | |
1610 | #endif | |
384cc687 WD |
1611 | #ifdef CFG_NAND_WP |
1612 | NAND_WP_ON(); | |
1613 | #endif | |
1614 | ||
85ec0bcc | 1615 | return ret; |
dc7c9a1a WD |
1616 | } |
1617 | ||
1618 | static inline int nandcheck(unsigned long potential, unsigned long physadr) | |
1619 | { | |
dc7c9a1a WD |
1620 | return 0; |
1621 | } | |
1622 | ||
a43278a4 | 1623 | unsigned long nand_probe(unsigned long physadr) |
dc7c9a1a WD |
1624 | { |
1625 | struct nand_chip *nand = NULL; | |
1626 | int i = 0, ChipID = 1; | |
1627 | ||
1628 | #ifdef CONFIG_MTD_NAND_ECC_JFFS2 | |
1629 | oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0; | |
1630 | oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1; | |
1631 | oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2; | |
1632 | oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3; | |
1633 | oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4; | |
1634 | oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5; | |
dc7c9a1a WD |
1635 | oob_config.eccvalid_pos = 4; |
1636 | #else | |
1637 | oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0; | |
1638 | oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1; | |
1639 | oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2; | |
1640 | oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3; | |
1641 | oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4; | |
1642 | oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5; | |
dc7c9a1a WD |
1643 | oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS; |
1644 | #endif | |
7a8e9bed | 1645 | oob_config.badblock_pos = 5; |
dc7c9a1a WD |
1646 | |
1647 | for (i=0; i<CFG_MAX_NAND_DEVICE; i++) { | |
1648 | if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) { | |
a43278a4 | 1649 | nand = &nand_dev_desc[i]; |
dc7c9a1a WD |
1650 | break; |
1651 | } | |
1652 | } | |
a43278a4 WD |
1653 | if (!nand) |
1654 | return (0); | |
dc7c9a1a | 1655 | |
0db5bca8 | 1656 | memset((char *)nand, 0, sizeof(struct nand_chip)); |
dc7c9a1a | 1657 | |
0db5bca8 | 1658 | nand->IO_ADDR = physadr; |
7a8e9bed | 1659 | nand->cache_page = -1; /* init the cache page */ |
0db5bca8 | 1660 | NanD_ScanChips(nand); |
7a8e9bed WD |
1661 | |
1662 | if (nand->totlen == 0) { | |
1663 | /* no chips found, clean up and quit */ | |
1664 | memset((char *)nand, 0, sizeof(struct nand_chip)); | |
1665 | nand->ChipID = NAND_ChipID_UNKNOWN; | |
a43278a4 | 1666 | return (0); |
7a8e9bed WD |
1667 | } |
1668 | ||
1669 | nand->ChipID = ChipID; | |
1670 | if (curr_device == -1) | |
1671 | curr_device = i; | |
1672 | ||
0db5bca8 WD |
1673 | nand->data_buf = malloc (nand->oobblock + nand->oobsize); |
1674 | if (!nand->data_buf) { | |
1675 | puts ("Cannot allocate memory for data structures.\n"); | |
a43278a4 | 1676 | return (0); |
0db5bca8 | 1677 | } |
a43278a4 WD |
1678 | |
1679 | return (nand->totlen); | |
dc7c9a1a WD |
1680 | } |
1681 | ||
1682 | #ifdef CONFIG_MTD_NAND_ECC | |
1683 | /* | |
1684 | * Pre-calculated 256-way 1 byte column parity | |
1685 | */ | |
1686 | static const u_char nand_ecc_precalc_table[] = { | |
384cc687 WD |
1687 | 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, |
1688 | 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, | |
1689 | 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, | |
1690 | 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, | |
1691 | 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, | |
1692 | 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, | |
1693 | 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, | |
1694 | 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, | |
1695 | 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, | |
1696 | 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, | |
1697 | 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, | |
1698 | 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, | |
1699 | 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, | |
1700 | 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, | |
1701 | 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, | |
1702 | 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, | |
1703 | 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, | |
1704 | 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, | |
1705 | 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, | |
1706 | 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, | |
1707 | 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, | |
1708 | 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, | |
1709 | 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, | |
1710 | 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, | |
1711 | 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, | |
1712 | 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, | |
1713 | 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, | |
1714 | 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, | |
1715 | 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, | |
1716 | 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, | |
1717 | 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, | |
1718 | 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 | |
dc7c9a1a WD |
1719 | }; |
1720 | ||
1721 | ||
1722 | /* | |
1723 | * Creates non-inverted ECC code from line parity | |
1724 | */ | |
1725 | static void nand_trans_result(u_char reg2, u_char reg3, | |
1726 | u_char *ecc_code) | |
1727 | { | |
1728 | u_char a, b, i, tmp1, tmp2; | |
1729 | ||
1730 | /* Initialize variables */ | |
1731 | a = b = 0x80; | |
1732 | tmp1 = tmp2 = 0; | |
1733 | ||
1734 | /* Calculate first ECC byte */ | |
1735 | for (i = 0; i < 4; i++) { | |
1736 | if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ | |
1737 | tmp1 |= b; | |
1738 | b >>= 1; | |
1739 | if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ | |
1740 | tmp1 |= b; | |
1741 | b >>= 1; | |
1742 | a >>= 1; | |
1743 | } | |
1744 | ||
1745 | /* Calculate second ECC byte */ | |
1746 | b = 0x80; | |
1747 | for (i = 0; i < 4; i++) { | |
1748 | if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ | |
1749 | tmp2 |= b; | |
1750 | b >>= 1; | |
1751 | if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ | |
1752 | tmp2 |= b; | |
1753 | b >>= 1; | |
1754 | a >>= 1; | |
1755 | } | |
1756 | ||
1757 | /* Store two of the ECC bytes */ | |
1758 | ecc_code[0] = tmp1; | |
1759 | ecc_code[1] = tmp2; | |
1760 | } | |
1761 | ||
1762 | /* | |
1763 | * Calculate 3 byte ECC code for 256 byte block | |
1764 | */ | |
1765 | static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) | |
1766 | { | |
7a8e9bed | 1767 | u_char idx, reg1, reg3; |
dc7c9a1a WD |
1768 | int j; |
1769 | ||
1770 | /* Initialize variables */ | |
7a8e9bed | 1771 | reg1 = reg3 = 0; |
dc7c9a1a WD |
1772 | ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; |
1773 | ||
1774 | /* Build up column parity */ | |
1775 | for(j = 0; j < 256; j++) { | |
1776 | ||
1777 | /* Get CP0 - CP5 from table */ | |
1778 | idx = nand_ecc_precalc_table[dat[j]]; | |
7a8e9bed | 1779 | reg1 ^= idx; |
dc7c9a1a WD |
1780 | |
1781 | /* All bit XOR = 1 ? */ | |
1782 | if (idx & 0x40) { | |
1783 | reg3 ^= (u_char) j; | |
dc7c9a1a WD |
1784 | } |
1785 | } | |
1786 | ||
1787 | /* Create non-inverted ECC code from line parity */ | |
7a8e9bed | 1788 | nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); |
dc7c9a1a WD |
1789 | |
1790 | /* Calculate final ECC code */ | |
1791 | ecc_code[0] = ~ecc_code[0]; | |
1792 | ecc_code[1] = ~ecc_code[1]; | |
1793 | ecc_code[2] = ((~reg1) << 2) | 0x03; | |
1794 | } | |
1795 | ||
1796 | /* | |
1797 | * Detect and correct a 1 bit error for 256 byte block | |
1798 | */ | |
1799 | static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) | |
1800 | { | |
1801 | u_char a, b, c, d1, d2, d3, add, bit, i; | |
1802 | ||
1803 | /* Do error detection */ | |
1804 | d1 = calc_ecc[0] ^ read_ecc[0]; | |
1805 | d2 = calc_ecc[1] ^ read_ecc[1]; | |
1806 | d3 = calc_ecc[2] ^ read_ecc[2]; | |
1807 | ||
1808 | if ((d1 | d2 | d3) == 0) { | |
1809 | /* No errors */ | |
1810 | return 0; | |
384cc687 | 1811 | } else { |
dc7c9a1a WD |
1812 | a = (d1 ^ (d1 >> 1)) & 0x55; |
1813 | b = (d2 ^ (d2 >> 1)) & 0x55; | |
1814 | c = (d3 ^ (d3 >> 1)) & 0x54; | |
1815 | ||
1816 | /* Found and will correct single bit error in the data */ | |
1817 | if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { | |
1818 | c = 0x80; | |
1819 | add = 0; | |
1820 | a = 0x80; | |
1821 | for (i=0; i<4; i++) { | |
1822 | if (d1 & c) | |
1823 | add |= a; | |
1824 | c >>= 2; | |
1825 | a >>= 1; | |
1826 | } | |
1827 | c = 0x80; | |
1828 | for (i=0; i<4; i++) { | |
1829 | if (d2 & c) | |
1830 | add |= a; | |
1831 | c >>= 2; | |
1832 | a >>= 1; | |
1833 | } | |
1834 | bit = 0; | |
1835 | b = 0x04; | |
1836 | c = 0x80; | |
1837 | for (i=0; i<3; i++) { | |
1838 | if (d3 & c) | |
1839 | bit |= b; | |
1840 | c >>= 2; | |
1841 | b >>= 1; | |
1842 | } | |
1843 | b = 0x01; | |
1844 | a = dat[add]; | |
1845 | a ^= (b << bit); | |
1846 | dat[add] = a; | |
1847 | return 1; | |
1848 | } | |
1849 | else { | |
1850 | i = 0; | |
1851 | while (d1) { | |
1852 | if (d1 & 0x01) | |
1853 | ++i; | |
1854 | d1 >>= 1; | |
1855 | } | |
1856 | while (d2) { | |
1857 | if (d2 & 0x01) | |
1858 | ++i; | |
1859 | d2 >>= 1; | |
1860 | } | |
1861 | while (d3) { | |
1862 | if (d3 & 0x01) | |
1863 | ++i; | |
1864 | d3 >>= 1; | |
1865 | } | |
1866 | if (i == 1) { | |
1867 | /* ECC Code Error Correction */ | |
1868 | read_ecc[0] = calc_ecc[0]; | |
1869 | read_ecc[1] = calc_ecc[1]; | |
1870 | read_ecc[2] = calc_ecc[2]; | |
1871 | return 2; | |
1872 | } | |
1873 | else { | |
1874 | /* Uncorrectable Error */ | |
1875 | return -1; | |
1876 | } | |
1877 | } | |
1878 | } | |
1879 | ||
1880 | /* Should never happen */ | |
1881 | return -1; | |
1882 | } | |
1f4bb37d | 1883 | |
dc7c9a1a | 1884 | #endif |
998eaaec WD |
1885 | |
1886 | #ifdef CONFIG_JFFS2_NAND | |
1887 | ||
1888 | int read_jffs2_nand(size_t start, size_t len, | |
1889 | size_t * retlen, u_char * buf, int nanddev) | |
1890 | { | |
1891 | return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2, | |
1892 | start, len, retlen, buf); | |
1893 | } | |
1894 | ||
1895 | #endif /* CONFIG_JFFS2_NAND */ | |
1896 | ||
1897 | ||
dc7c9a1a | 1898 | #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ |