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c906108c | 1 | /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger. |
0fd88904 | 2 | |
213516ef | 3 | Copyright (C) 1993-2023 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
d55e5aa6 | 21 | #include "frame.h" |
4de283e4 TT |
22 | #include "frame-unwind.h" |
23 | #include "frame-base.h" | |
82ca8957 | 24 | #include "dwarf2/frame.h" |
4de283e4 TT |
25 | #include "inferior.h" |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
c906108c SS |
28 | #include "gdbcmd.h" |
29 | #include "gdbcore.h" | |
4de283e4 TT |
30 | #include "dis-asm.h" |
31 | #include "symfile.h" | |
d55e5aa6 | 32 | #include "objfiles.h" |
4de283e4 | 33 | #include "linespec.h" |
4e052eda | 34 | #include "regcache.h" |
615967cb | 35 | #include "reggroups.h" |
4de283e4 TT |
36 | #include "arch-utils.h" |
37 | #include "osabi.h" | |
4de283e4 | 38 | #include "infcall.h" |
07ea644b | 39 | #include "trad-frame.h" |
4de283e4 TT |
40 | |
41 | #include "elf-bfd.h" | |
42 | ||
43 | #include "alpha-tdep.h" | |
44 | #include <algorithm> | |
dc129d82 | 45 | |
3a48e6ff JG |
46 | /* Instruction decoding. The notations for registers, immediates and |
47 | opcodes are the same as the one used in Compaq's Alpha architecture | |
48 | handbook. */ | |
49 | ||
50 | #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26) | |
51 | ||
52 | /* Memory instruction format */ | |
53 | #define MEM_RA(insn) ((insn & 0x03e00000) >> 21) | |
54 | #define MEM_RB(insn) ((insn & 0x001f0000) >> 16) | |
55 | #define MEM_DISP(insn) \ | |
56 | (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff)) | |
57 | ||
58 | static const int lda_opcode = 0x08; | |
59 | static const int stq_opcode = 0x2d; | |
60 | ||
61 | /* Branch instruction format */ | |
62 | #define BR_RA(insn) MEM_RA(insn) | |
63 | ||
46ad3598 | 64 | static const int br_opcode = 0x30; |
3a48e6ff JG |
65 | static const int bne_opcode = 0x3d; |
66 | ||
67 | /* Operate instruction format */ | |
68 | #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5) | |
69 | #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000) | |
70 | #define OPR_RA(insn) MEM_RA(insn) | |
71 | #define OPR_RC(insn) ((insn & 0x1f)) | |
72 | #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13) | |
73 | ||
74 | static const int subq_opcode = 0x10; | |
75 | static const int subq_function = 0x29; | |
76 | ||
c906108c | 77 | \f |
515921d7 JB |
78 | /* Return the name of the REGNO register. |
79 | ||
80 | An empty name corresponds to a register number that used to | |
0963b4bd | 81 | be used for a virtual register. That virtual register has |
515921d7 JB |
82 | been removed, but the index is still reserved to maintain |
83 | compatibility with existing remote alpha targets. */ | |
84 | ||
fa88f677 | 85 | static const char * |
d93859e2 | 86 | alpha_register_name (struct gdbarch *gdbarch, int regno) |
636a6dfc | 87 | { |
5ab84872 | 88 | static const char * const register_names[] = |
636a6dfc JT |
89 | { |
90 | "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", | |
91 | "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", | |
92 | "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", | |
93 | "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", | |
94 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
95 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
96 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
97 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr", | |
44d88583 | 98 | "pc", "", "unique" |
636a6dfc JT |
99 | }; |
100 | ||
9b9e61c7 | 101 | gdb_static_assert (ALPHA_NUM_REGS == ARRAY_SIZE (register_names)); |
5ab84872 | 102 | return register_names[regno]; |
636a6dfc | 103 | } |
d734c450 | 104 | |
dc129d82 | 105 | static int |
64a3914f | 106 | alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
d734c450 | 107 | { |
4a1be8d2 | 108 | return (strlen (alpha_register_name (gdbarch, regno)) == 0); |
d734c450 JT |
109 | } |
110 | ||
dc129d82 | 111 | static int |
64a3914f | 112 | alpha_cannot_store_register (struct gdbarch *gdbarch, int regno) |
d734c450 | 113 | { |
515921d7 | 114 | return (regno == ALPHA_ZERO_REGNUM |
dda83cd7 | 115 | || strlen (alpha_register_name (gdbarch, regno)) == 0); |
d734c450 JT |
116 | } |
117 | ||
dc129d82 | 118 | static struct type * |
c483c494 | 119 | alpha_register_type (struct gdbarch *gdbarch, int regno) |
0d056799 | 120 | { |
72667056 | 121 | if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM) |
0dfff4cb | 122 | return builtin_type (gdbarch)->builtin_data_ptr; |
72667056 | 123 | if (regno == ALPHA_PC_REGNUM) |
0dfff4cb | 124 | return builtin_type (gdbarch)->builtin_func_ptr; |
72667056 RH |
125 | |
126 | /* Don't need to worry about little vs big endian until | |
127 | some jerk tries to port to alpha-unicosmk. */ | |
b38b6be2 | 128 | if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31) |
27067745 | 129 | return builtin_type (gdbarch)->builtin_double; |
72667056 | 130 | |
df4df182 | 131 | return builtin_type (gdbarch)->builtin_int64; |
0d056799 | 132 | } |
f8453e34 | 133 | |
615967cb RH |
134 | /* Is REGNUM a member of REGGROUP? */ |
135 | ||
136 | static int | |
137 | alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 138 | const struct reggroup *group) |
615967cb RH |
139 | { |
140 | /* Filter out any registers eliminated, but whose regnum is | |
141 | reserved for backward compatibility, e.g. the vfp. */ | |
637b2f86 | 142 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
615967cb RH |
143 | return 0; |
144 | ||
df4a182b RH |
145 | if (group == all_reggroup) |
146 | return 1; | |
147 | ||
148 | /* Zero should not be saved or restored. Technically it is a general | |
149 | register (just as $f31 would be a float if we represented it), but | |
150 | there's no point displaying it during "info regs", so leave it out | |
151 | of all groups except for "all". */ | |
152 | if (regnum == ALPHA_ZERO_REGNUM) | |
153 | return 0; | |
154 | ||
155 | /* All other registers are saved and restored. */ | |
156 | if (group == save_reggroup || group == restore_reggroup) | |
615967cb RH |
157 | return 1; |
158 | ||
159 | /* All other groups are non-overlapping. */ | |
160 | ||
161 | /* Since this is really a PALcode memory slot... */ | |
162 | if (regnum == ALPHA_UNIQUE_REGNUM) | |
163 | return group == system_reggroup; | |
164 | ||
165 | /* Force the FPCR to be considered part of the floating point state. */ | |
166 | if (regnum == ALPHA_FPCR_REGNUM) | |
167 | return group == float_reggroup; | |
168 | ||
169 | if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31) | |
170 | return group == float_reggroup; | |
171 | else | |
172 | return group == general_reggroup; | |
173 | } | |
174 | ||
c483c494 RH |
175 | /* The following represents exactly the conversion performed by |
176 | the LDS instruction. This applies to both single-precision | |
177 | floating point and 32-bit integers. */ | |
178 | ||
179 | static void | |
e17a4113 | 180 | alpha_lds (struct gdbarch *gdbarch, void *out, const void *in) |
c483c494 | 181 | { |
e17a4113 | 182 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9a3c8263 SM |
183 | ULONGEST mem |
184 | = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order); | |
c483c494 RH |
185 | ULONGEST frac = (mem >> 0) & 0x7fffff; |
186 | ULONGEST sign = (mem >> 31) & 1; | |
187 | ULONGEST exp_msb = (mem >> 30) & 1; | |
188 | ULONGEST exp_low = (mem >> 23) & 0x7f; | |
189 | ULONGEST exp, reg; | |
190 | ||
191 | exp = (exp_msb << 10) | exp_low; | |
192 | if (exp_msb) | |
193 | { | |
194 | if (exp_low == 0x7f) | |
195 | exp = 0x7ff; | |
196 | } | |
197 | else | |
198 | { | |
199 | if (exp_low != 0x00) | |
200 | exp |= 0x380; | |
201 | } | |
202 | ||
203 | reg = (sign << 63) | (exp << 52) | (frac << 29); | |
9a3c8263 | 204 | store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg); |
c483c494 RH |
205 | } |
206 | ||
207 | /* Similarly, this represents exactly the conversion performed by | |
208 | the STS instruction. */ | |
209 | ||
39efb398 | 210 | static void |
e17a4113 | 211 | alpha_sts (struct gdbarch *gdbarch, void *out, const void *in) |
c483c494 | 212 | { |
e17a4113 | 213 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c483c494 RH |
214 | ULONGEST reg, mem; |
215 | ||
9a3c8263 | 216 | reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order); |
c483c494 | 217 | mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff); |
9a3c8263 | 218 | store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem); |
c483c494 RH |
219 | } |
220 | ||
d2427a71 RH |
221 | /* The alpha needs a conversion between register and memory format if the |
222 | register is a floating point register and memory format is float, as the | |
223 | register format must be double or memory format is an integer with 4 | |
68fce50f | 224 | bytes, as the representation of integers in floating point |
0963b4bd | 225 | registers is different. */ |
d2427a71 | 226 | |
c483c494 | 227 | static int |
0963b4bd MS |
228 | alpha_convert_register_p (struct gdbarch *gdbarch, int regno, |
229 | struct type *type) | |
14696584 | 230 | { |
83acabca | 231 | return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31 |
df86565b | 232 | && type->length () == 4); |
14696584 RH |
233 | } |
234 | ||
8dccd430 | 235 | static int |
bd2b40ac | 236 | alpha_register_to_value (frame_info_ptr frame, int regnum, |
8dccd430 PA |
237 | struct type *valtype, gdb_byte *out, |
238 | int *optimizedp, int *unavailablep) | |
5868c862 | 239 | { |
8dccd430 | 240 | struct gdbarch *gdbarch = get_frame_arch (frame); |
fbe654c8 | 241 | struct value *value = get_frame_register_value (frame, regnum); |
2a1ce6ec | 242 | |
fbe654c8 | 243 | gdb_assert (value != NULL); |
d00664db TT |
244 | *optimizedp = value->optimized_out (); |
245 | *unavailablep = !value->entirely_available (); | |
fbe654c8 AH |
246 | |
247 | if (*optimizedp || *unavailablep) | |
248 | { | |
249 | release_value (value); | |
fbe654c8 AH |
250 | return 0; |
251 | } | |
252 | ||
253 | /* Convert to VALTYPE. */ | |
8dccd430 | 254 | |
df86565b | 255 | gdb_assert (valtype->length () == 4); |
efaf1ae0 | 256 | alpha_sts (gdbarch, out, value->contents_all ().data ()); |
fbe654c8 AH |
257 | |
258 | release_value (value); | |
68fce50f | 259 | return 1; |
d2427a71 | 260 | } |
5868c862 | 261 | |
d2427a71 | 262 | static void |
bd2b40ac | 263 | alpha_value_to_register (frame_info_ptr frame, int regnum, |
5b819568 | 264 | struct type *valtype, const gdb_byte *in) |
d2427a71 | 265 | { |
fbe654c8 | 266 | gdb_byte out[ALPHA_REGISTER_SIZE]; |
2a1ce6ec | 267 | |
df86565b | 268 | gdb_assert (valtype->length () == 4); |
fbe654c8 AH |
269 | gdb_assert (register_size (get_frame_arch (frame), regnum) |
270 | <= ALPHA_REGISTER_SIZE); | |
68fce50f YQ |
271 | alpha_lds (get_frame_arch (frame), out, in); |
272 | ||
ff2e87ac | 273 | put_frame_register (frame, regnum, out); |
5868c862 JT |
274 | } |
275 | ||
d2427a71 RH |
276 | \f |
277 | /* The alpha passes the first six arguments in the registers, the rest on | |
c88e30c0 RH |
278 | the stack. The register arguments are stored in ARG_REG_BUFFER, and |
279 | then moved into the register file; this simplifies the passing of a | |
280 | large struct which extends from the registers to the stack, plus avoids | |
281 | three ptrace invocations per word. | |
282 | ||
283 | We don't bother tracking which register values should go in integer | |
284 | regs or fp regs; we load the same values into both. | |
285 | ||
d2427a71 RH |
286 | If the called function is returning a structure, the address of the |
287 | structure to be returned is passed as a hidden first argument. */ | |
c906108c | 288 | |
d2427a71 | 289 | static CORE_ADDR |
7d9b040b | 290 | alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
c88e30c0 RH |
291 | struct regcache *regcache, CORE_ADDR bp_addr, |
292 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
293 | function_call_return_method return_method, |
294 | CORE_ADDR struct_addr) | |
c906108c | 295 | { |
e17a4113 | 296 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d2427a71 | 297 | int i; |
cf84fa6b | 298 | int accumulate_size = (return_method == return_method_struct) ? 8 : 0; |
d2427a71 | 299 | struct alpha_arg |
c906108c | 300 | { |
f42a0a33 | 301 | const gdb_byte *contents; |
d2427a71 RH |
302 | int len; |
303 | int offset; | |
304 | }; | |
8d749320 | 305 | struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs); |
52f0bd74 | 306 | struct alpha_arg *m_arg; |
2a1ce6ec | 307 | gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS]; |
d2427a71 | 308 | int required_arg_regs; |
7d9b040b | 309 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 310 | |
c88e30c0 RH |
311 | /* The ABI places the address of the called function in T12. */ |
312 | regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr); | |
313 | ||
314 | /* Set the return address register to point to the entry point | |
315 | of the program, where a breakpoint lies in wait. */ | |
316 | regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr); | |
317 | ||
318 | /* Lay out the arguments in memory. */ | |
d2427a71 RH |
319 | for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++) |
320 | { | |
321 | struct value *arg = args[i]; | |
d0c97917 | 322 | struct type *arg_type = check_typedef (arg->type ()); |
c88e30c0 | 323 | |
d2427a71 | 324 | /* Cast argument to long if necessary as the compiler does it too. */ |
78134374 | 325 | switch (arg_type->code ()) |
c906108c | 326 | { |
d2427a71 RH |
327 | case TYPE_CODE_INT: |
328 | case TYPE_CODE_BOOL: | |
329 | case TYPE_CODE_CHAR: | |
330 | case TYPE_CODE_RANGE: | |
331 | case TYPE_CODE_ENUM: | |
df86565b | 332 | if (arg_type->length () == 4) |
d2427a71 | 333 | { |
0ede8eca RH |
334 | /* 32-bit values must be sign-extended to 64 bits |
335 | even if the base data type is unsigned. */ | |
df4df182 | 336 | arg_type = builtin_type (gdbarch)->builtin_int32; |
0ede8eca RH |
337 | arg = value_cast (arg_type, arg); |
338 | } | |
df86565b | 339 | if (arg_type->length () < ALPHA_REGISTER_SIZE) |
0ede8eca | 340 | { |
df4df182 | 341 | arg_type = builtin_type (gdbarch)->builtin_int64; |
d2427a71 RH |
342 | arg = value_cast (arg_type, arg); |
343 | } | |
344 | break; | |
7b5e1cb3 | 345 | |
c88e30c0 RH |
346 | case TYPE_CODE_FLT: |
347 | /* "float" arguments loaded in registers must be passed in | |
348 | register format, aka "double". */ | |
349 | if (accumulate_size < sizeof (arg_reg_buffer) | |
df86565b | 350 | && arg_type->length () == 4) |
c88e30c0 | 351 | { |
27067745 | 352 | arg_type = builtin_type (gdbarch)->builtin_double; |
c88e30c0 RH |
353 | arg = value_cast (arg_type, arg); |
354 | } | |
355 | /* Tru64 5.1 has a 128-bit long double, and passes this by | |
356 | invisible reference. No one else uses this data type. */ | |
df86565b | 357 | else if (arg_type->length () == 16) |
c88e30c0 RH |
358 | { |
359 | /* Allocate aligned storage. */ | |
360 | sp = (sp & -16) - 16; | |
361 | ||
362 | /* Write the real data into the stack. */ | |
efaf1ae0 | 363 | write_memory (sp, arg->contents ().data (), 16); |
c88e30c0 RH |
364 | |
365 | /* Construct the indirection. */ | |
366 | arg_type = lookup_pointer_type (arg_type); | |
367 | arg = value_from_pointer (arg_type, sp); | |
368 | } | |
369 | break; | |
7b5e1cb3 RH |
370 | |
371 | case TYPE_CODE_COMPLEX: | |
372 | /* ??? The ABI says that complex values are passed as two | |
373 | separate scalar values. This distinction only matters | |
374 | for complex float. However, GCC does not implement this. */ | |
375 | ||
376 | /* Tru64 5.1 has a 128-bit long double, and passes this by | |
377 | invisible reference. */ | |
df86565b | 378 | if (arg_type->length () == 32) |
7b5e1cb3 RH |
379 | { |
380 | /* Allocate aligned storage. */ | |
381 | sp = (sp & -16) - 16; | |
382 | ||
383 | /* Write the real data into the stack. */ | |
efaf1ae0 | 384 | write_memory (sp, arg->contents ().data (), 32); |
7b5e1cb3 RH |
385 | |
386 | /* Construct the indirection. */ | |
387 | arg_type = lookup_pointer_type (arg_type); | |
388 | arg = value_from_pointer (arg_type, sp); | |
389 | } | |
390 | break; | |
391 | ||
d2427a71 RH |
392 | default: |
393 | break; | |
c906108c | 394 | } |
df86565b | 395 | m_arg->len = arg_type->length (); |
d2427a71 RH |
396 | m_arg->offset = accumulate_size; |
397 | accumulate_size = (accumulate_size + m_arg->len + 7) & ~7; | |
efaf1ae0 | 398 | m_arg->contents = arg->contents ().data (); |
c906108c SS |
399 | } |
400 | ||
d2427a71 RH |
401 | /* Determine required argument register loads, loading an argument register |
402 | is expensive as it uses three ptrace calls. */ | |
403 | required_arg_regs = accumulate_size / 8; | |
404 | if (required_arg_regs > ALPHA_NUM_ARG_REGS) | |
405 | required_arg_regs = ALPHA_NUM_ARG_REGS; | |
c906108c | 406 | |
d2427a71 | 407 | /* Make room for the arguments on the stack. */ |
c88e30c0 RH |
408 | if (accumulate_size < sizeof(arg_reg_buffer)) |
409 | accumulate_size = 0; | |
410 | else | |
411 | accumulate_size -= sizeof(arg_reg_buffer); | |
d2427a71 | 412 | sp -= accumulate_size; |
c906108c | 413 | |
c88e30c0 | 414 | /* Keep sp aligned to a multiple of 16 as the ABI requires. */ |
d2427a71 | 415 | sp &= ~15; |
c906108c | 416 | |
d2427a71 RH |
417 | /* `Push' arguments on the stack. */ |
418 | for (i = nargs; m_arg--, --i >= 0;) | |
c906108c | 419 | { |
f42a0a33 | 420 | const gdb_byte *contents = m_arg->contents; |
c88e30c0 RH |
421 | int offset = m_arg->offset; |
422 | int len = m_arg->len; | |
423 | ||
424 | /* Copy the bytes destined for registers into arg_reg_buffer. */ | |
425 | if (offset < sizeof(arg_reg_buffer)) | |
426 | { | |
427 | if (offset + len <= sizeof(arg_reg_buffer)) | |
428 | { | |
429 | memcpy (arg_reg_buffer + offset, contents, len); | |
430 | continue; | |
431 | } | |
432 | else | |
433 | { | |
434 | int tlen = sizeof(arg_reg_buffer) - offset; | |
435 | memcpy (arg_reg_buffer + offset, contents, tlen); | |
436 | offset += tlen; | |
437 | contents += tlen; | |
438 | len -= tlen; | |
439 | } | |
440 | } | |
441 | ||
442 | /* Everything else goes to the stack. */ | |
443 | write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len); | |
c906108c | 444 | } |
cf84fa6b | 445 | if (return_method == return_method_struct) |
e17a4113 UW |
446 | store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE, |
447 | byte_order, struct_addr); | |
c906108c | 448 | |
d2427a71 RH |
449 | /* Load the argument registers. */ |
450 | for (i = 0; i < required_arg_regs; i++) | |
451 | { | |
b66f5587 SM |
452 | regcache->cooked_write (ALPHA_A0_REGNUM + i, |
453 | arg_reg_buffer + i * ALPHA_REGISTER_SIZE); | |
454 | regcache->cooked_write (ALPHA_FPA0_REGNUM + i, | |
455 | arg_reg_buffer + i * ALPHA_REGISTER_SIZE); | |
d2427a71 | 456 | } |
c906108c | 457 | |
09cc52fd RH |
458 | /* Finally, update the stack pointer. */ |
459 | regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp); | |
460 | ||
c88e30c0 | 461 | return sp; |
c906108c SS |
462 | } |
463 | ||
5ec2bb99 RH |
464 | /* Extract from REGCACHE the value about to be returned from a function |
465 | and copy it into VALBUF. */ | |
d2427a71 | 466 | |
dc129d82 | 467 | static void |
5ec2bb99 | 468 | alpha_extract_return_value (struct type *valtype, struct regcache *regcache, |
5b819568 | 469 | gdb_byte *valbuf) |
140f9984 | 470 | { |
ac7936df | 471 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 472 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2a1ce6ec | 473 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
5ec2bb99 RH |
474 | ULONGEST l; |
475 | ||
78134374 | 476 | switch (valtype->code ()) |
5ec2bb99 RH |
477 | { |
478 | case TYPE_CODE_FLT: | |
df86565b | 479 | switch (valtype->length ()) |
5ec2bb99 RH |
480 | { |
481 | case 4: | |
dca08e1f | 482 | regcache->cooked_read (ALPHA_FP0_REGNUM, raw_buffer); |
e17a4113 | 483 | alpha_sts (gdbarch, valbuf, raw_buffer); |
5ec2bb99 RH |
484 | break; |
485 | ||
486 | case 8: | |
dca08e1f | 487 | regcache->cooked_read (ALPHA_FP0_REGNUM, valbuf); |
5ec2bb99 RH |
488 | break; |
489 | ||
24064b5c RH |
490 | case 16: |
491 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); | |
492 | read_memory (l, valbuf, 16); | |
493 | break; | |
494 | ||
5ec2bb99 | 495 | default: |
f34652de | 496 | internal_error (_("unknown floating point width")); |
5ec2bb99 RH |
497 | } |
498 | break; | |
499 | ||
7b5e1cb3 | 500 | case TYPE_CODE_COMPLEX: |
df86565b | 501 | switch (valtype->length ()) |
7b5e1cb3 RH |
502 | { |
503 | case 8: | |
504 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ | |
dca08e1f | 505 | regcache->cooked_read (ALPHA_FP0_REGNUM, valbuf); |
7b5e1cb3 RH |
506 | break; |
507 | ||
508 | case 16: | |
dca08e1f SM |
509 | regcache->cooked_read (ALPHA_FP0_REGNUM, valbuf); |
510 | regcache->cooked_read (ALPHA_FP0_REGNUM + 1, valbuf + 8); | |
7b5e1cb3 RH |
511 | break; |
512 | ||
513 | case 32: | |
a9933661 | 514 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); |
7b5e1cb3 RH |
515 | read_memory (l, valbuf, 32); |
516 | break; | |
517 | ||
518 | default: | |
f34652de | 519 | internal_error (_("unknown floating point width")); |
7b5e1cb3 RH |
520 | } |
521 | break; | |
522 | ||
5ec2bb99 RH |
523 | default: |
524 | /* Assume everything else degenerates to an integer. */ | |
525 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); | |
df86565b | 526 | store_unsigned_integer (valbuf, valtype->length (), byte_order, l); |
5ec2bb99 RH |
527 | break; |
528 | } | |
140f9984 JT |
529 | } |
530 | ||
5ec2bb99 RH |
531 | /* Insert the given value into REGCACHE as if it was being |
532 | returned by a function. */ | |
0d056799 | 533 | |
d2427a71 | 534 | static void |
5ec2bb99 | 535 | alpha_store_return_value (struct type *valtype, struct regcache *regcache, |
5b819568 | 536 | const gdb_byte *valbuf) |
c906108c | 537 | { |
ac7936df | 538 | struct gdbarch *gdbarch = regcache->arch (); |
2a1ce6ec | 539 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
5ec2bb99 | 540 | ULONGEST l; |
d2427a71 | 541 | |
78134374 | 542 | switch (valtype->code ()) |
c906108c | 543 | { |
5ec2bb99 | 544 | case TYPE_CODE_FLT: |
df86565b | 545 | switch (valtype->length ()) |
5ec2bb99 RH |
546 | { |
547 | case 4: | |
e17a4113 | 548 | alpha_lds (gdbarch, raw_buffer, valbuf); |
b66f5587 | 549 | regcache->cooked_write (ALPHA_FP0_REGNUM, raw_buffer); |
f75d70cc | 550 | break; |
5ec2bb99 RH |
551 | |
552 | case 8: | |
b66f5587 | 553 | regcache->cooked_write (ALPHA_FP0_REGNUM, valbuf); |
5ec2bb99 RH |
554 | break; |
555 | ||
24064b5c RH |
556 | case 16: |
557 | /* FIXME: 128-bit long doubles are returned like structures: | |
558 | by writing into indirect storage provided by the caller | |
559 | as the first argument. */ | |
323e0a4a | 560 | error (_("Cannot set a 128-bit long double return value.")); |
24064b5c | 561 | |
5ec2bb99 | 562 | default: |
f34652de | 563 | internal_error (_("unknown floating point width")); |
5ec2bb99 RH |
564 | } |
565 | break; | |
d2427a71 | 566 | |
7b5e1cb3 | 567 | case TYPE_CODE_COMPLEX: |
df86565b | 568 | switch (valtype->length ()) |
7b5e1cb3 RH |
569 | { |
570 | case 8: | |
571 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ | |
b66f5587 | 572 | regcache->cooked_write (ALPHA_FP0_REGNUM, valbuf); |
7b5e1cb3 RH |
573 | break; |
574 | ||
575 | case 16: | |
b66f5587 SM |
576 | regcache->cooked_write (ALPHA_FP0_REGNUM, valbuf); |
577 | regcache->cooked_write (ALPHA_FP0_REGNUM + 1, valbuf + 8); | |
7b5e1cb3 RH |
578 | break; |
579 | ||
580 | case 32: | |
581 | /* FIXME: 128-bit long doubles are returned like structures: | |
582 | by writing into indirect storage provided by the caller | |
583 | as the first argument. */ | |
323e0a4a | 584 | error (_("Cannot set a 128-bit long double return value.")); |
7b5e1cb3 RH |
585 | |
586 | default: | |
f34652de | 587 | internal_error (_("unknown floating point width")); |
7b5e1cb3 RH |
588 | } |
589 | break; | |
590 | ||
5ec2bb99 RH |
591 | default: |
592 | /* Assume everything else degenerates to an integer. */ | |
0ede8eca RH |
593 | /* 32-bit values must be sign-extended to 64 bits |
594 | even if the base data type is unsigned. */ | |
df86565b | 595 | if (valtype->length () == 4) |
df4df182 | 596 | valtype = builtin_type (gdbarch)->builtin_int32; |
5ec2bb99 RH |
597 | l = unpack_long (valtype, valbuf); |
598 | regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l); | |
599 | break; | |
600 | } | |
c906108c SS |
601 | } |
602 | ||
9823e921 | 603 | static enum return_value_convention |
6a3a010b | 604 | alpha_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
605 | struct type *type, struct regcache *regcache, |
606 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
9823e921 | 607 | { |
78134374 | 608 | enum type_code code = type->code (); |
08106042 | 609 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); |
9823e921 RH |
610 | |
611 | if ((code == TYPE_CODE_STRUCT | |
612 | || code == TYPE_CODE_UNION | |
613 | || code == TYPE_CODE_ARRAY) | |
345bd07c | 614 | && tdep->return_in_memory (type)) |
9823e921 RH |
615 | { |
616 | if (readbuf) | |
617 | { | |
618 | ULONGEST addr; | |
619 | regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr); | |
df86565b | 620 | read_memory (addr, readbuf, type->length ()); |
9823e921 RH |
621 | } |
622 | ||
623 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
624 | } | |
625 | ||
626 | if (readbuf) | |
627 | alpha_extract_return_value (type, regcache, readbuf); | |
628 | if (writebuf) | |
629 | alpha_store_return_value (type, regcache, writebuf); | |
630 | ||
631 | return RETURN_VALUE_REGISTER_CONVENTION; | |
632 | } | |
633 | ||
634 | static int | |
635 | alpha_return_in_memory_always (struct type *type) | |
636 | { | |
637 | return 1; | |
638 | } | |
d2427a71 | 639 | \f |
c906108c | 640 | |
04180708 | 641 | constexpr gdb_byte alpha_break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */ |
598cc9dc | 642 | |
04180708 | 643 | typedef BP_MANIPULATION (alpha_break_insn) alpha_breakpoint; |
c906108c | 644 | |
d2427a71 RH |
645 | \f |
646 | /* This returns the PC of the first insn after the prologue. | |
647 | If we can't find the prologue, then return 0. */ | |
c906108c | 648 | |
d2427a71 RH |
649 | CORE_ADDR |
650 | alpha_after_prologue (CORE_ADDR pc) | |
c906108c | 651 | { |
d2427a71 RH |
652 | struct symtab_and_line sal; |
653 | CORE_ADDR func_addr, func_end; | |
c906108c | 654 | |
d2427a71 | 655 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
c5aa993b | 656 | return 0; |
c906108c | 657 | |
d2427a71 RH |
658 | sal = find_pc_line (func_addr, 0); |
659 | if (sal.end < func_end) | |
660 | return sal.end; | |
c5aa993b | 661 | |
d2427a71 RH |
662 | /* The line after the prologue is after the end of the function. In this |
663 | case, tell the caller to find the prologue the hard way. */ | |
664 | return 0; | |
c906108c SS |
665 | } |
666 | ||
d2427a71 RH |
667 | /* Read an instruction from memory at PC, looking through breakpoints. */ |
668 | ||
669 | unsigned int | |
e17a4113 | 670 | alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 671 | { |
e17a4113 | 672 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e8d2d628 | 673 | gdb_byte buf[ALPHA_INSN_SIZE]; |
d09f2c3f | 674 | int res; |
c5aa993b | 675 | |
d09f2c3f PA |
676 | res = target_read_memory (pc, buf, sizeof (buf)); |
677 | if (res != 0) | |
678 | memory_error (TARGET_XFER_E_IO, pc); | |
e17a4113 | 679 | return extract_unsigned_integer (buf, sizeof (buf), byte_order); |
d2427a71 | 680 | } |
c5aa993b | 681 | |
d2427a71 RH |
682 | /* To skip prologues, I use this predicate. Returns either PC itself |
683 | if the code at PC does not look like a function prologue; otherwise | |
684 | returns an address that (if we're lucky) follows the prologue. If | |
685 | LENIENT, then we must skip everything which is involved in setting | |
686 | up the frame (it's OK to skip more, just so long as we don't skip | |
687 | anything which might clobber the registers which are being saved. */ | |
c906108c | 688 | |
d2427a71 | 689 | static CORE_ADDR |
6093d2eb | 690 | alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d2427a71 RH |
691 | { |
692 | unsigned long inst; | |
693 | int offset; | |
694 | CORE_ADDR post_prologue_pc; | |
e8d2d628 | 695 | gdb_byte buf[ALPHA_INSN_SIZE]; |
c906108c | 696 | |
d2427a71 RH |
697 | /* Silently return the unaltered pc upon memory errors. |
698 | This could happen on OSF/1 if decode_line_1 tries to skip the | |
699 | prologue for quickstarted shared library functions when the | |
700 | shared library is not yet mapped in. | |
701 | Reading target memory is slow over serial lines, so we perform | |
702 | this check only if the target has shared libraries (which all | |
703 | Alpha targets do). */ | |
e8d2d628 | 704 | if (target_read_memory (pc, buf, sizeof (buf))) |
d2427a71 | 705 | return pc; |
c906108c | 706 | |
d2427a71 RH |
707 | /* See if we can determine the end of the prologue via the symbol table. |
708 | If so, then return either PC, or the PC after the prologue, whichever | |
709 | is greater. */ | |
c906108c | 710 | |
d2427a71 RH |
711 | post_prologue_pc = alpha_after_prologue (pc); |
712 | if (post_prologue_pc != 0) | |
325fac50 | 713 | return std::max (pc, post_prologue_pc); |
c906108c | 714 | |
d2427a71 RH |
715 | /* Can't determine prologue from the symbol table, need to examine |
716 | instructions. */ | |
dc1b0db2 | 717 | |
0963b4bd | 718 | /* Skip the typical prologue instructions. These are the stack adjustment |
d2427a71 RH |
719 | instruction and the instructions that save registers on the stack |
720 | or in the gcc frame. */ | |
e8d2d628 | 721 | for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE) |
d2427a71 | 722 | { |
e17a4113 | 723 | inst = alpha_read_insn (gdbarch, pc + offset); |
c906108c | 724 | |
d2427a71 RH |
725 | if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */ |
726 | continue; | |
727 | if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */ | |
728 | continue; | |
729 | if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ | |
730 | continue; | |
731 | if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */ | |
732 | continue; | |
c906108c | 733 | |
d2427a71 RH |
734 | if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */ |
735 | || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */ | |
736 | && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */ | |
737 | continue; | |
c906108c | 738 | |
d2427a71 RH |
739 | if (inst == 0x47de040f) /* bis sp,sp,fp */ |
740 | continue; | |
741 | if (inst == 0x47fe040f) /* bis zero,sp,fp */ | |
742 | continue; | |
c906108c | 743 | |
d2427a71 | 744 | break; |
c906108c | 745 | } |
d2427a71 RH |
746 | return pc + offset; |
747 | } | |
c906108c | 748 | |
46ad3598 UW |
749 | \f |
750 | static const int ldl_l_opcode = 0x2a; | |
751 | static const int ldq_l_opcode = 0x2b; | |
752 | static const int stl_c_opcode = 0x2e; | |
753 | static const int stq_c_opcode = 0x2f; | |
754 | ||
755 | /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L | |
756 | instruction and ending with a STL_C/STQ_C instruction. If such a sequence | |
757 | is found, attempt to step through it. A breakpoint is placed at the end of | |
758 | the sequence. */ | |
759 | ||
a0ff9e1a | 760 | static std::vector<CORE_ADDR> |
68f81d60 | 761 | alpha_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
46ad3598 | 762 | { |
70ab8ccd | 763 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
46ad3598 UW |
764 | CORE_ADDR loc = pc; |
765 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ | |
766 | unsigned int insn = alpha_read_insn (gdbarch, loc); | |
767 | int insn_count; | |
768 | int index; | |
769 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
770 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
771 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
772 | ||
773 | /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */ | |
774 | if (INSN_OPCODE (insn) != ldl_l_opcode | |
775 | && INSN_OPCODE (insn) != ldq_l_opcode) | |
a0ff9e1a | 776 | return {}; |
46ad3598 UW |
777 | |
778 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
779 | instructions. */ | |
780 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
781 | { | |
782 | loc += ALPHA_INSN_SIZE; | |
783 | insn = alpha_read_insn (gdbarch, loc); | |
784 | ||
785 | /* Assume that there is at most one branch in the atomic | |
786 | sequence. If a branch is found, put a breakpoint in | |
787 | its destination address. */ | |
788 | if (INSN_OPCODE (insn) >= br_opcode) | |
789 | { | |
790 | int immediate = (insn & 0x001fffff) << 2; | |
791 | ||
792 | immediate = (immediate ^ 0x400000) - 0x400000; | |
793 | ||
794 | if (bc_insn_count >= 1) | |
a0ff9e1a SM |
795 | return {}; /* More than one branch found, fallback |
796 | to the standard single-step code. */ | |
46ad3598 UW |
797 | |
798 | breaks[1] = loc + ALPHA_INSN_SIZE + immediate; | |
799 | ||
800 | bc_insn_count++; | |
801 | last_breakpoint++; | |
802 | } | |
803 | ||
804 | if (INSN_OPCODE (insn) == stl_c_opcode | |
805 | || INSN_OPCODE (insn) == stq_c_opcode) | |
806 | break; | |
807 | } | |
808 | ||
809 | /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */ | |
810 | if (INSN_OPCODE (insn) != stl_c_opcode | |
811 | && INSN_OPCODE (insn) != stq_c_opcode) | |
a0ff9e1a | 812 | return {}; |
46ad3598 UW |
813 | |
814 | closing_insn = loc; | |
815 | loc += ALPHA_INSN_SIZE; | |
816 | ||
817 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
818 | breaks[0] = loc; | |
819 | ||
820 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
821 | placed (branch instruction's destination) anywhere in sequence. */ | |
822 | if (last_breakpoint | |
823 | && (breaks[1] == breaks[0] | |
824 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
825 | last_breakpoint = 0; | |
826 | ||
a0ff9e1a SM |
827 | std::vector<CORE_ADDR> next_pcs; |
828 | ||
46ad3598 | 829 | for (index = 0; index <= last_breakpoint; index++) |
a0ff9e1a | 830 | next_pcs.push_back (breaks[index]); |
46ad3598 | 831 | |
93f9a11f | 832 | return next_pcs; |
46ad3598 UW |
833 | } |
834 | ||
d2427a71 RH |
835 | \f |
836 | /* Figure out where the longjmp will land. | |
837 | We expect the first arg to be a pointer to the jmp_buf structure from | |
838 | which we extract the PC (JB_PC) that we will land at. The PC is copied | |
839 | into the "pc". This routine returns true on success. */ | |
c906108c SS |
840 | |
841 | static int | |
bd2b40ac | 842 | alpha_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
c906108c | 843 | { |
e17a4113 | 844 | struct gdbarch *gdbarch = get_frame_arch (frame); |
08106042 | 845 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); |
e17a4113 | 846 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d2427a71 | 847 | CORE_ADDR jb_addr; |
2a1ce6ec | 848 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
c906108c | 849 | |
60ade65d | 850 | jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM); |
c906108c | 851 | |
d2427a71 RH |
852 | if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size), |
853 | raw_buffer, tdep->jb_elt_size)) | |
c906108c | 854 | return 0; |
d2427a71 | 855 | |
e17a4113 | 856 | *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order); |
d2427a71 | 857 | return 1; |
c906108c SS |
858 | } |
859 | ||
d2427a71 RH |
860 | \f |
861 | /* Frame unwinder for signal trampolines. We use alpha tdep bits that | |
862 | describe the location and shape of the sigcontext structure. After | |
863 | that, all registers are in memory, so it's easy. */ | |
864 | /* ??? Shouldn't we be able to do this generically, rather than with | |
865 | OSABI data specific to Alpha? */ | |
866 | ||
867 | struct alpha_sigtramp_unwind_cache | |
c906108c | 868 | { |
d2427a71 RH |
869 | CORE_ADDR sigcontext_addr; |
870 | }; | |
c906108c | 871 | |
d2427a71 | 872 | static struct alpha_sigtramp_unwind_cache * |
bd2b40ac | 873 | alpha_sigtramp_frame_unwind_cache (frame_info_ptr this_frame, |
d2427a71 RH |
874 | void **this_prologue_cache) |
875 | { | |
876 | struct alpha_sigtramp_unwind_cache *info; | |
c906108c | 877 | |
d2427a71 | 878 | if (*this_prologue_cache) |
9a3c8263 | 879 | return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache; |
c906108c | 880 | |
d2427a71 RH |
881 | info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache); |
882 | *this_prologue_cache = info; | |
c906108c | 883 | |
345bd07c | 884 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 885 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (arch); |
6834c9bb | 886 | info->sigcontext_addr = tdep->sigcontext_addr (this_frame); |
c906108c | 887 | |
d2427a71 | 888 | return info; |
c906108c SS |
889 | } |
890 | ||
138e7be5 MK |
891 | /* Return the address of REGNUM in a sigtramp frame. Since this is |
892 | all arithmetic, it doesn't seem worthwhile to cache it. */ | |
c5aa993b | 893 | |
d2427a71 | 894 | static CORE_ADDR |
be8626e0 MD |
895 | alpha_sigtramp_register_address (struct gdbarch *gdbarch, |
896 | CORE_ADDR sigcontext_addr, int regnum) | |
d2427a71 | 897 | { |
08106042 | 898 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); |
138e7be5 MK |
899 | |
900 | if (regnum >= 0 && regnum < 32) | |
901 | return sigcontext_addr + tdep->sc_regs_offset + regnum * 8; | |
902 | else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32) | |
903 | return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8; | |
904 | else if (regnum == ALPHA_PC_REGNUM) | |
905 | return sigcontext_addr + tdep->sc_pc_offset; | |
c5aa993b | 906 | |
d2427a71 | 907 | return 0; |
c906108c SS |
908 | } |
909 | ||
d2427a71 RH |
910 | /* Given a GDB frame, determine the address of the calling function's |
911 | frame. This will be used to create a new GDB frame struct. */ | |
140f9984 | 912 | |
dc129d82 | 913 | static void |
bd2b40ac | 914 | alpha_sigtramp_frame_this_id (frame_info_ptr this_frame, |
d2427a71 RH |
915 | void **this_prologue_cache, |
916 | struct frame_id *this_id) | |
c906108c | 917 | { |
6834c9bb | 918 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
08106042 | 919 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); |
d2427a71 | 920 | struct alpha_sigtramp_unwind_cache *info |
6834c9bb | 921 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
d2427a71 RH |
922 | CORE_ADDR stack_addr, code_addr; |
923 | ||
924 | /* If the OSABI couldn't locate the sigcontext, give up. */ | |
925 | if (info->sigcontext_addr == 0) | |
926 | return; | |
927 | ||
928 | /* If we have dynamic signal trampolines, find their start. | |
929 | If we do not, then we must assume there is a symbol record | |
930 | that can provide the start address. */ | |
d2427a71 | 931 | if (tdep->dynamic_sigtramp_offset) |
c906108c | 932 | { |
d2427a71 | 933 | int offset; |
6834c9bb | 934 | code_addr = get_frame_pc (this_frame); |
e17a4113 | 935 | offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr); |
d2427a71 RH |
936 | if (offset >= 0) |
937 | code_addr -= offset; | |
c906108c | 938 | else |
d2427a71 | 939 | code_addr = 0; |
c906108c | 940 | } |
d2427a71 | 941 | else |
6834c9bb | 942 | code_addr = get_frame_func (this_frame); |
c906108c | 943 | |
d2427a71 | 944 | /* The stack address is trivially read from the sigcontext. */ |
be8626e0 | 945 | stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr, |
d2427a71 | 946 | ALPHA_SP_REGNUM); |
6834c9bb | 947 | stack_addr = get_frame_memory_unsigned (this_frame, stack_addr, |
b21fd293 | 948 | ALPHA_REGISTER_SIZE); |
c906108c | 949 | |
d2427a71 | 950 | *this_id = frame_id_build (stack_addr, code_addr); |
c906108c SS |
951 | } |
952 | ||
d2427a71 | 953 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
c906108c | 954 | |
6834c9bb | 955 | static struct value * |
bd2b40ac | 956 | alpha_sigtramp_frame_prev_register (frame_info_ptr this_frame, |
6834c9bb | 957 | void **this_prologue_cache, int regnum) |
c906108c | 958 | { |
d2427a71 | 959 | struct alpha_sigtramp_unwind_cache *info |
6834c9bb | 960 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
d2427a71 | 961 | CORE_ADDR addr; |
c906108c | 962 | |
d2427a71 | 963 | if (info->sigcontext_addr != 0) |
c906108c | 964 | { |
d2427a71 | 965 | /* All integer and fp registers are stored in memory. */ |
6834c9bb | 966 | addr = alpha_sigtramp_register_address (get_frame_arch (this_frame), |
be8626e0 | 967 | info->sigcontext_addr, regnum); |
d2427a71 | 968 | if (addr != 0) |
dda83cd7 | 969 | return frame_unwind_got_memory (this_frame, regnum, addr); |
c906108c SS |
970 | } |
971 | ||
d2427a71 RH |
972 | /* This extra register may actually be in the sigcontext, but our |
973 | current description of it in alpha_sigtramp_frame_unwind_cache | |
974 | doesn't include it. Too bad. Fall back on whatever's in the | |
975 | outer frame. */ | |
6834c9bb | 976 | return frame_unwind_got_register (this_frame, regnum, regnum); |
d2427a71 | 977 | } |
c906108c | 978 | |
6834c9bb JB |
979 | static int |
980 | alpha_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 981 | frame_info_ptr this_frame, |
dda83cd7 | 982 | void **this_prologue_cache) |
d2427a71 | 983 | { |
6834c9bb JB |
984 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
985 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2c02bd72 | 986 | const char *name; |
c906108c | 987 | |
f2524b93 | 988 | /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead |
85102364 | 989 | look at tramp-frame.h and other simpler per-architecture |
f2524b93 AC |
990 | sigtramp unwinders. */ |
991 | ||
992 | /* We shouldn't even bother to try if the OSABI didn't register a | |
85102364 | 993 | sigcontext_addr handler or pc_in_sigtramp handler. */ |
08106042 | 994 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); |
345bd07c | 995 | if (tdep->sigcontext_addr == NULL) |
6834c9bb | 996 | return 0; |
345bd07c SM |
997 | |
998 | if (tdep->pc_in_sigtramp == NULL) | |
6834c9bb | 999 | return 0; |
c906108c | 1000 | |
d2427a71 RH |
1001 | /* Otherwise we should be in a signal frame. */ |
1002 | find_pc_partial_function (pc, &name, NULL, NULL); | |
345bd07c | 1003 | if (tdep->pc_in_sigtramp (gdbarch, pc, name)) |
6834c9bb | 1004 | return 1; |
c906108c | 1005 | |
6834c9bb | 1006 | return 0; |
c906108c | 1007 | } |
6834c9bb | 1008 | |
a154d838 SM |
1009 | static const struct frame_unwind alpha_sigtramp_frame_unwind = |
1010 | { | |
1011 | "alpha sigtramp", | |
6834c9bb | 1012 | SIGTRAMP_FRAME, |
8fbca658 | 1013 | default_frame_unwind_stop_reason, |
6834c9bb JB |
1014 | alpha_sigtramp_frame_this_id, |
1015 | alpha_sigtramp_frame_prev_register, | |
1016 | NULL, | |
1017 | alpha_sigtramp_frame_sniffer | |
1018 | }; | |
1019 | ||
d2427a71 | 1020 | \f |
c906108c | 1021 | |
d2427a71 RH |
1022 | /* Heuristic_proc_start may hunt through the text section for a long |
1023 | time across a 2400 baud serial line. Allows the user to limit this | |
1024 | search. */ | |
44096aee | 1025 | static int heuristic_fence_post = 0; |
c906108c | 1026 | |
d2427a71 RH |
1027 | /* Attempt to locate the start of the function containing PC. We assume that |
1028 | the previous function ends with an about_to_return insn. Not foolproof by | |
1029 | any means, since gcc is happy to put the epilogue in the middle of a | |
1030 | function. But we're guessing anyway... */ | |
c906108c | 1031 | |
d2427a71 | 1032 | static CORE_ADDR |
be8626e0 | 1033 | alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
d2427a71 | 1034 | { |
08106042 | 1035 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); |
d2427a71 RH |
1036 | CORE_ADDR last_non_nop = pc; |
1037 | CORE_ADDR fence = pc - heuristic_fence_post; | |
1038 | CORE_ADDR orig_pc = pc; | |
fbe586ae | 1039 | CORE_ADDR func; |
d6b48e9c | 1040 | struct inferior *inf; |
9e0b60a8 | 1041 | |
d2427a71 RH |
1042 | if (pc == 0) |
1043 | return 0; | |
9e0b60a8 | 1044 | |
fbe586ae RH |
1045 | /* First see if we can find the start of the function from minimal |
1046 | symbol information. This can succeed with a binary that doesn't | |
1047 | have debug info, but hasn't been stripped. */ | |
1048 | func = get_pc_function_start (pc); | |
1049 | if (func) | |
1050 | return func; | |
1051 | ||
44096aee | 1052 | if (heuristic_fence_post == -1 |
d2427a71 RH |
1053 | || fence < tdep->vm_min_address) |
1054 | fence = tdep->vm_min_address; | |
c906108c | 1055 | |
d2427a71 RH |
1056 | /* Search back for previous return; also stop at a 0, which might be |
1057 | seen for instance before the start of a code section. Don't include | |
1058 | nops, since this usually indicates padding between functions. */ | |
e8d2d628 | 1059 | for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE) |
c906108c | 1060 | { |
e17a4113 | 1061 | unsigned int insn = alpha_read_insn (gdbarch, pc); |
d2427a71 | 1062 | switch (insn) |
c906108c | 1063 | { |
d2427a71 RH |
1064 | case 0: /* invalid insn */ |
1065 | case 0x6bfa8001: /* ret $31,($26),1 */ | |
1066 | return last_non_nop; | |
1067 | ||
1068 | case 0x2ffe0000: /* unop: ldq_u $31,0($30) */ | |
1069 | case 0x47ff041f: /* nop: bis $31,$31,$31 */ | |
1070 | break; | |
1071 | ||
1072 | default: | |
1073 | last_non_nop = pc; | |
1074 | break; | |
c906108c | 1075 | } |
d2427a71 | 1076 | } |
c906108c | 1077 | |
d6b48e9c PA |
1078 | inf = current_inferior (); |
1079 | ||
d2427a71 RH |
1080 | /* It's not clear to me why we reach this point when stopping quietly, |
1081 | but with this test, at least we don't print out warnings for every | |
1082 | child forked (eg, on decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 1083 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
d2427a71 RH |
1084 | { |
1085 | static int blurb_printed = 0; | |
c906108c | 1086 | |
d2427a71 | 1087 | if (fence == tdep->vm_min_address) |
323e0a4a | 1088 | warning (_("Hit beginning of text section without finding \ |
5af949e3 | 1089 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
c906108c | 1090 | else |
323e0a4a | 1091 | warning (_("Hit heuristic-fence-post without finding \ |
5af949e3 | 1092 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
c906108c | 1093 | |
d2427a71 RH |
1094 | if (!blurb_printed) |
1095 | { | |
6cb06a8c | 1096 | gdb_printf (_("\ |
d2427a71 RH |
1097 | This warning occurs if you are debugging a function without any symbols\n\ |
1098 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
1099 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
1100 | \n\ | |
1101 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
323e0a4a | 1102 | (more likely) you have encountered a bug in GDB.\n")); |
d2427a71 RH |
1103 | blurb_printed = 1; |
1104 | } | |
1105 | } | |
c906108c | 1106 | |
d2427a71 RH |
1107 | return 0; |
1108 | } | |
c906108c | 1109 | |
07ea644b MD |
1110 | /* Fallback alpha frame unwinder. Uses instruction scanning and knows |
1111 | something about the traditional layout of alpha stack frames. */ | |
1112 | ||
1113 | struct alpha_heuristic_unwind_cache | |
1114 | { | |
1115 | CORE_ADDR vfp; | |
1116 | CORE_ADDR start_pc; | |
098caef4 | 1117 | trad_frame_saved_reg *saved_regs; |
07ea644b MD |
1118 | int return_reg; |
1119 | }; | |
1120 | ||
3a48e6ff JG |
1121 | /* If a probing loop sequence starts at PC, simulate it and compute |
1122 | FRAME_SIZE and PC after its execution. Otherwise, return with PC and | |
1123 | FRAME_SIZE unchanged. */ | |
1124 | ||
1125 | static void | |
1126 | alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc, | |
1127 | int *frame_size) | |
1128 | { | |
1129 | CORE_ADDR cur_pc = *pc; | |
1130 | int cur_frame_size = *frame_size; | |
1131 | int nb_of_iterations, reg_index, reg_probe; | |
1132 | unsigned int insn; | |
1133 | ||
1134 | /* The following pattern is recognized as a probing loop: | |
1135 | ||
dda83cd7 SM |
1136 | lda REG_INDEX,NB_OF_ITERATIONS |
1137 | lda REG_PROBE,<immediate>(sp) | |
3a48e6ff JG |
1138 | |
1139 | LOOP_START: | |
dda83cd7 SM |
1140 | stq zero,<immediate>(REG_PROBE) |
1141 | subq REG_INDEX,0x1,REG_INDEX | |
1142 | lda REG_PROBE,<immediate>(REG_PROBE) | |
1143 | bne REG_INDEX, LOOP_START | |
3a48e6ff | 1144 | |
dda83cd7 | 1145 | lda sp,<immediate>(REG_PROBE) |
3a48e6ff JG |
1146 | |
1147 | If anything different is found, the function returns without | |
1148 | changing PC and FRAME_SIZE. Otherwise, PC will point immediately | |
0963b4bd | 1149 | after this sequence, and FRAME_SIZE will be updated. */ |
3a48e6ff JG |
1150 | |
1151 | /* lda REG_INDEX,NB_OF_ITERATIONS */ | |
1152 | ||
1153 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1154 | if (INSN_OPCODE (insn) != lda_opcode) | |
1155 | return; | |
1156 | reg_index = MEM_RA (insn); | |
1157 | nb_of_iterations = MEM_DISP (insn); | |
1158 | ||
1159 | /* lda REG_PROBE,<immediate>(sp) */ | |
1160 | ||
1161 | cur_pc += ALPHA_INSN_SIZE; | |
1162 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1163 | if (INSN_OPCODE (insn) != lda_opcode | |
1164 | || MEM_RB (insn) != ALPHA_SP_REGNUM) | |
1165 | return; | |
1166 | reg_probe = MEM_RA (insn); | |
1167 | cur_frame_size -= MEM_DISP (insn); | |
1168 | ||
1169 | /* stq zero,<immediate>(REG_PROBE) */ | |
1170 | ||
1171 | cur_pc += ALPHA_INSN_SIZE; | |
1172 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1173 | if (INSN_OPCODE (insn) != stq_opcode | |
1174 | || MEM_RA (insn) != 0x1f | |
1175 | || MEM_RB (insn) != reg_probe) | |
1176 | return; | |
1177 | ||
1178 | /* subq REG_INDEX,0x1,REG_INDEX */ | |
1179 | ||
1180 | cur_pc += ALPHA_INSN_SIZE; | |
1181 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1182 | if (INSN_OPCODE (insn) != subq_opcode | |
1183 | || !OPR_HAS_IMMEDIATE (insn) | |
1184 | || OPR_FUNCTION (insn) != subq_function | |
1185 | || OPR_LIT(insn) != 1 | |
1186 | || OPR_RA (insn) != reg_index | |
1187 | || OPR_RC (insn) != reg_index) | |
1188 | return; | |
1189 | ||
1190 | /* lda REG_PROBE,<immediate>(REG_PROBE) */ | |
1191 | ||
1192 | cur_pc += ALPHA_INSN_SIZE; | |
1193 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1194 | if (INSN_OPCODE (insn) != lda_opcode | |
1195 | || MEM_RA (insn) != reg_probe | |
1196 | || MEM_RB (insn) != reg_probe) | |
1197 | return; | |
1198 | cur_frame_size -= MEM_DISP (insn) * nb_of_iterations; | |
1199 | ||
1200 | /* bne REG_INDEX, LOOP_START */ | |
1201 | ||
1202 | cur_pc += ALPHA_INSN_SIZE; | |
1203 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1204 | if (INSN_OPCODE (insn) != bne_opcode | |
1205 | || MEM_RA (insn) != reg_index) | |
1206 | return; | |
1207 | ||
1208 | /* lda sp,<immediate>(REG_PROBE) */ | |
1209 | ||
1210 | cur_pc += ALPHA_INSN_SIZE; | |
1211 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1212 | if (INSN_OPCODE (insn) != lda_opcode | |
1213 | || MEM_RA (insn) != ALPHA_SP_REGNUM | |
1214 | || MEM_RB (insn) != reg_probe) | |
1215 | return; | |
1216 | cur_frame_size -= MEM_DISP (insn); | |
1217 | ||
1218 | *pc = cur_pc; | |
1219 | *frame_size = cur_frame_size; | |
1220 | } | |
1221 | ||
fbe586ae | 1222 | static struct alpha_heuristic_unwind_cache * |
bd2b40ac | 1223 | alpha_heuristic_frame_unwind_cache (frame_info_ptr this_frame, |
d2427a71 RH |
1224 | void **this_prologue_cache, |
1225 | CORE_ADDR start_pc) | |
1226 | { | |
6834c9bb | 1227 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
d2427a71 RH |
1228 | struct alpha_heuristic_unwind_cache *info; |
1229 | ULONGEST val; | |
1230 | CORE_ADDR limit_pc, cur_pc; | |
1231 | int frame_reg, frame_size, return_reg, reg; | |
c906108c | 1232 | |
d2427a71 | 1233 | if (*this_prologue_cache) |
9a3c8263 | 1234 | return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache; |
c906108c | 1235 | |
d2427a71 RH |
1236 | info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache); |
1237 | *this_prologue_cache = info; | |
6834c9bb | 1238 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1239 | |
6834c9bb | 1240 | limit_pc = get_frame_pc (this_frame); |
d2427a71 | 1241 | if (start_pc == 0) |
be8626e0 | 1242 | start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc); |
d2427a71 | 1243 | info->start_pc = start_pc; |
c906108c | 1244 | |
d2427a71 RH |
1245 | frame_reg = ALPHA_SP_REGNUM; |
1246 | frame_size = 0; | |
1247 | return_reg = -1; | |
c906108c | 1248 | |
d2427a71 RH |
1249 | /* If we've identified a likely place to start, do code scanning. */ |
1250 | if (start_pc != 0) | |
c5aa993b | 1251 | { |
d2427a71 RH |
1252 | /* Limit the forward search to 50 instructions. */ |
1253 | if (start_pc + 200 < limit_pc) | |
1254 | limit_pc = start_pc + 200; | |
c5aa993b | 1255 | |
e8d2d628 | 1256 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE) |
d2427a71 | 1257 | { |
e17a4113 | 1258 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
c5aa993b | 1259 | |
d2427a71 RH |
1260 | if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ |
1261 | { | |
1262 | if (word & 0x8000) | |
1263 | { | |
1264 | /* Consider only the first stack allocation instruction | |
0963b4bd | 1265 | to contain the static size of the frame. */ |
d2427a71 RH |
1266 | if (frame_size == 0) |
1267 | frame_size = (-word) & 0xffff; | |
1268 | } | |
1269 | else | |
1270 | { | |
1271 | /* Exit loop if a positive stack adjustment is found, which | |
1272 | usually means that the stack cleanup code in the function | |
1273 | epilogue is reached. */ | |
1274 | break; | |
1275 | } | |
1276 | } | |
1277 | else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ | |
1278 | { | |
1279 | reg = (word & 0x03e00000) >> 21; | |
1280 | ||
dda83cd7 SM |
1281 | /* Ignore this instruction if we have already encountered |
1282 | an instruction saving the same register earlier in the | |
1283 | function code. The current instruction does not tell | |
1284 | us where the original value upon function entry is saved. | |
1285 | All it says is that the function we are scanning reused | |
1286 | that register for some computation of its own, and is now | |
1287 | saving its result. */ | |
a9a87d35 | 1288 | if (info->saved_regs[reg].is_addr ()) |
dda83cd7 | 1289 | continue; |
d15bfd3a | 1290 | |
d2427a71 RH |
1291 | if (reg == 31) |
1292 | continue; | |
1293 | ||
1294 | /* Do not compute the address where the register was saved yet, | |
1295 | because we don't know yet if the offset will need to be | |
1296 | relative to $sp or $fp (we can not compute the address | |
1297 | relative to $sp if $sp is updated during the execution of | |
1298 | the current subroutine, for instance when doing some alloca). | |
1299 | So just store the offset for the moment, and compute the | |
1300 | address later when we know whether this frame has a frame | |
1301 | pointer or not. */ | |
1302 | /* Hack: temporarily add one, so that the offset is non-zero | |
1303 | and we can tell which registers have save offsets below. */ | |
098caef4 | 1304 | info->saved_regs[reg].set_addr ((word & 0xffff) + 1); |
d2427a71 RH |
1305 | |
1306 | /* Starting with OSF/1-3.2C, the system libraries are shipped | |
1307 | without local symbols, but they still contain procedure | |
1308 | descriptors without a symbol reference. GDB is currently | |
1309 | unable to find these procedure descriptors and uses | |
1310 | heuristic_proc_desc instead. | |
1311 | As some low level compiler support routines (__div*, __add*) | |
1312 | use a non-standard return address register, we have to | |
1313 | add some heuristics to determine the return address register, | |
1314 | or stepping over these routines will fail. | |
1315 | Usually the return address register is the first register | |
1316 | saved on the stack, but assembler optimization might | |
1317 | rearrange the register saves. | |
1318 | So we recognize only a few registers (t7, t9, ra) within | |
1319 | the procedure prologue as valid return address registers. | |
1320 | If we encounter a return instruction, we extract the | |
7a9dd1b2 | 1321 | return address register from it. |
d2427a71 RH |
1322 | |
1323 | FIXME: Rewriting GDB to access the procedure descriptors, | |
0963b4bd MS |
1324 | e.g. via the minimal symbol table, might obviate this |
1325 | hack. */ | |
d2427a71 RH |
1326 | if (return_reg == -1 |
1327 | && cur_pc < (start_pc + 80) | |
1328 | && (reg == ALPHA_T7_REGNUM | |
1329 | || reg == ALPHA_T9_REGNUM | |
1330 | || reg == ALPHA_RA_REGNUM)) | |
1331 | return_reg = reg; | |
1332 | } | |
1333 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ | |
1334 | return_reg = (word >> 16) & 0x1f; | |
1335 | else if (word == 0x47de040f) /* bis sp,sp,fp */ | |
1336 | frame_reg = ALPHA_GCC_FP_REGNUM; | |
1337 | else if (word == 0x47fe040f) /* bis zero,sp,fp */ | |
1338 | frame_reg = ALPHA_GCC_FP_REGNUM; | |
3a48e6ff JG |
1339 | |
1340 | alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size); | |
d2427a71 | 1341 | } |
c5aa993b | 1342 | |
d2427a71 RH |
1343 | /* If we haven't found a valid return address register yet, keep |
1344 | searching in the procedure prologue. */ | |
1345 | if (return_reg == -1) | |
1346 | { | |
1347 | while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80)) | |
1348 | { | |
e17a4113 | 1349 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
c5aa993b | 1350 | |
d2427a71 RH |
1351 | if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ |
1352 | { | |
1353 | reg = (word & 0x03e00000) >> 21; | |
1354 | if (reg == ALPHA_T7_REGNUM | |
1355 | || reg == ALPHA_T9_REGNUM | |
1356 | || reg == ALPHA_RA_REGNUM) | |
1357 | { | |
1358 | return_reg = reg; | |
1359 | break; | |
1360 | } | |
1361 | } | |
1362 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ | |
1363 | { | |
1364 | return_reg = (word >> 16) & 0x1f; | |
1365 | break; | |
1366 | } | |
85b32d22 | 1367 | |
e8d2d628 | 1368 | cur_pc += ALPHA_INSN_SIZE; |
d2427a71 RH |
1369 | } |
1370 | } | |
c906108c | 1371 | } |
c906108c | 1372 | |
d2427a71 RH |
1373 | /* Failing that, do default to the customary RA. */ |
1374 | if (return_reg == -1) | |
1375 | return_reg = ALPHA_RA_REGNUM; | |
1376 | info->return_reg = return_reg; | |
f8453e34 | 1377 | |
6834c9bb | 1378 | val = get_frame_register_unsigned (this_frame, frame_reg); |
d2427a71 | 1379 | info->vfp = val + frame_size; |
c906108c | 1380 | |
d2427a71 RH |
1381 | /* Convert offsets to absolute addresses. See above about adding |
1382 | one to the offsets to make all detected offsets non-zero. */ | |
1383 | for (reg = 0; reg < ALPHA_NUM_REGS; ++reg) | |
a9a87d35 | 1384 | if (info->saved_regs[reg].is_addr ()) |
098caef4 LM |
1385 | info->saved_regs[reg].set_addr (info->saved_regs[reg].addr () |
1386 | + val - 1); | |
d2427a71 | 1387 | |
bfd66dd9 JB |
1388 | /* The stack pointer of the previous frame is computed by popping |
1389 | the current stack frame. */ | |
a9a87d35 LM |
1390 | if (!info->saved_regs[ALPHA_SP_REGNUM].is_addr ()) |
1391 | info->saved_regs[ALPHA_SP_REGNUM].set_value (info->vfp); | |
bfd66dd9 | 1392 | |
d2427a71 | 1393 | return info; |
c906108c | 1394 | } |
c906108c | 1395 | |
d2427a71 RH |
1396 | /* Given a GDB frame, determine the address of the calling function's |
1397 | frame. This will be used to create a new GDB frame struct. */ | |
1398 | ||
fbe586ae | 1399 | static void |
bd2b40ac | 1400 | alpha_heuristic_frame_this_id (frame_info_ptr this_frame, |
6834c9bb JB |
1401 | void **this_prologue_cache, |
1402 | struct frame_id *this_id) | |
c906108c | 1403 | { |
d2427a71 | 1404 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1405 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
c906108c | 1406 | |
d2427a71 | 1407 | *this_id = frame_id_build (info->vfp, info->start_pc); |
c906108c SS |
1408 | } |
1409 | ||
d2427a71 RH |
1410 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
1411 | ||
6834c9bb | 1412 | static struct value * |
bd2b40ac | 1413 | alpha_heuristic_frame_prev_register (frame_info_ptr this_frame, |
6834c9bb | 1414 | void **this_prologue_cache, int regnum) |
c906108c | 1415 | { |
d2427a71 | 1416 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1417 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
d2427a71 RH |
1418 | |
1419 | /* The PC of the previous frame is stored in the link register of | |
1420 | the current frame. Frob regnum so that we pull the value from | |
1421 | the correct place. */ | |
1422 | if (regnum == ALPHA_PC_REGNUM) | |
1423 | regnum = info->return_reg; | |
1424 | ||
6834c9bb | 1425 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
95b80706 JT |
1426 | } |
1427 | ||
a154d838 SM |
1428 | static const struct frame_unwind alpha_heuristic_frame_unwind = |
1429 | { | |
1430 | "alpha prologue", | |
d2427a71 | 1431 | NORMAL_FRAME, |
8fbca658 | 1432 | default_frame_unwind_stop_reason, |
d2427a71 | 1433 | alpha_heuristic_frame_this_id, |
6834c9bb JB |
1434 | alpha_heuristic_frame_prev_register, |
1435 | NULL, | |
1436 | default_frame_sniffer | |
d2427a71 | 1437 | }; |
c906108c | 1438 | |
fbe586ae | 1439 | static CORE_ADDR |
bd2b40ac | 1440 | alpha_heuristic_frame_base_address (frame_info_ptr this_frame, |
d2427a71 | 1441 | void **this_prologue_cache) |
c906108c | 1442 | { |
d2427a71 | 1443 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1444 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
c906108c | 1445 | |
d2427a71 | 1446 | return info->vfp; |
c906108c SS |
1447 | } |
1448 | ||
d2427a71 RH |
1449 | static const struct frame_base alpha_heuristic_frame_base = { |
1450 | &alpha_heuristic_frame_unwind, | |
1451 | alpha_heuristic_frame_base_address, | |
1452 | alpha_heuristic_frame_base_address, | |
1453 | alpha_heuristic_frame_base_address | |
1454 | }; | |
1455 | ||
c906108c | 1456 | /* Just like reinit_frame_cache, but with the right arguments to be |
d2427a71 | 1457 | callable as an sfunc. Used by the "set heuristic-fence-post" command. */ |
c906108c SS |
1458 | |
1459 | static void | |
eb4c3f4a TT |
1460 | reinit_frame_cache_sfunc (const char *args, |
1461 | int from_tty, struct cmd_list_element *c) | |
c906108c SS |
1462 | { |
1463 | reinit_frame_cache (); | |
1464 | } | |
98a8e1e5 RH |
1465 | \f |
1466 | /* Helper routines for alpha*-nat.c files to move register sets to and | |
1467 | from core files. The UNIQUE pointer is allowed to be NULL, as most | |
1468 | targets don't supply this value in their core files. */ | |
1469 | ||
1470 | void | |
390c1522 UW |
1471 | alpha_supply_int_regs (struct regcache *regcache, int regno, |
1472 | const void *r0_r30, const void *pc, const void *unique) | |
98a8e1e5 | 1473 | { |
9a3c8263 | 1474 | const gdb_byte *regs = (const gdb_byte *) r0_r30; |
98a8e1e5 RH |
1475 | int i; |
1476 | ||
1477 | for (i = 0; i < 31; ++i) | |
1478 | if (regno == i || regno == -1) | |
73e1c03f | 1479 | regcache->raw_supply (i, regs + i * 8); |
98a8e1e5 RH |
1480 | |
1481 | if (regno == ALPHA_ZERO_REGNUM || regno == -1) | |
4a1be8d2 PA |
1482 | { |
1483 | const gdb_byte zero[8] = { 0 }; | |
1484 | ||
73e1c03f | 1485 | regcache->raw_supply (ALPHA_ZERO_REGNUM, zero); |
4a1be8d2 | 1486 | } |
98a8e1e5 RH |
1487 | |
1488 | if (regno == ALPHA_PC_REGNUM || regno == -1) | |
73e1c03f | 1489 | regcache->raw_supply (ALPHA_PC_REGNUM, pc); |
98a8e1e5 RH |
1490 | |
1491 | if (regno == ALPHA_UNIQUE_REGNUM || regno == -1) | |
73e1c03f | 1492 | regcache->raw_supply (ALPHA_UNIQUE_REGNUM, unique); |
98a8e1e5 RH |
1493 | } |
1494 | ||
1495 | void | |
390c1522 UW |
1496 | alpha_fill_int_regs (const struct regcache *regcache, |
1497 | int regno, void *r0_r30, void *pc, void *unique) | |
98a8e1e5 | 1498 | { |
9a3c8263 | 1499 | gdb_byte *regs = (gdb_byte *) r0_r30; |
98a8e1e5 RH |
1500 | int i; |
1501 | ||
1502 | for (i = 0; i < 31; ++i) | |
1503 | if (regno == i || regno == -1) | |
34a79281 | 1504 | regcache->raw_collect (i, regs + i * 8); |
98a8e1e5 RH |
1505 | |
1506 | if (regno == ALPHA_PC_REGNUM || regno == -1) | |
34a79281 | 1507 | regcache->raw_collect (ALPHA_PC_REGNUM, pc); |
98a8e1e5 RH |
1508 | |
1509 | if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1)) | |
34a79281 | 1510 | regcache->raw_collect (ALPHA_UNIQUE_REGNUM, unique); |
98a8e1e5 RH |
1511 | } |
1512 | ||
1513 | void | |
390c1522 UW |
1514 | alpha_supply_fp_regs (struct regcache *regcache, int regno, |
1515 | const void *f0_f30, const void *fpcr) | |
98a8e1e5 | 1516 | { |
9a3c8263 | 1517 | const gdb_byte *regs = (const gdb_byte *) f0_f30; |
98a8e1e5 RH |
1518 | int i; |
1519 | ||
1520 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) | |
1521 | if (regno == i || regno == -1) | |
73e1c03f | 1522 | regcache->raw_supply (i, regs + (i - ALPHA_FP0_REGNUM) * 8); |
98a8e1e5 RH |
1523 | |
1524 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) | |
73e1c03f | 1525 | regcache->raw_supply (ALPHA_FPCR_REGNUM, fpcr); |
98a8e1e5 RH |
1526 | } |
1527 | ||
1528 | void | |
390c1522 UW |
1529 | alpha_fill_fp_regs (const struct regcache *regcache, |
1530 | int regno, void *f0_f30, void *fpcr) | |
98a8e1e5 | 1531 | { |
9a3c8263 | 1532 | gdb_byte *regs = (gdb_byte *) f0_f30; |
98a8e1e5 RH |
1533 | int i; |
1534 | ||
1535 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) | |
1536 | if (regno == i || regno == -1) | |
34a79281 | 1537 | regcache->raw_collect (i, regs + (i - ALPHA_FP0_REGNUM) * 8); |
98a8e1e5 RH |
1538 | |
1539 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) | |
34a79281 | 1540 | regcache->raw_collect (ALPHA_FPCR_REGNUM, fpcr); |
98a8e1e5 RH |
1541 | } |
1542 | ||
d2427a71 | 1543 | \f |
0de94d4b JB |
1544 | |
1545 | /* Return nonzero if the G_floating register value in REG is equal to | |
1546 | zero for FP control instructions. */ | |
1547 | ||
1548 | static int | |
1549 | fp_register_zero_p (LONGEST reg) | |
1550 | { | |
1551 | /* Check that all bits except the sign bit are zero. */ | |
1552 | const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1; | |
1553 | ||
1554 | return ((reg & zero_mask) == 0); | |
1555 | } | |
1556 | ||
1557 | /* Return the value of the sign bit for the G_floating register | |
1558 | value held in REG. */ | |
1559 | ||
1560 | static int | |
1561 | fp_register_sign_bit (LONGEST reg) | |
1562 | { | |
1563 | const LONGEST sign_mask = (LONGEST) 1 << 63; | |
1564 | ||
1565 | return ((reg & sign_mask) != 0); | |
1566 | } | |
1567 | ||
ec32e4be JT |
1568 | /* alpha_software_single_step() is called just before we want to resume |
1569 | the inferior, if we want to single-step it but there is no hardware | |
1570 | or kernel single-step support (NetBSD on Alpha, for example). We find | |
e0cd558a | 1571 | the target of the coming instruction and breakpoint it. */ |
ec32e4be JT |
1572 | |
1573 | static CORE_ADDR | |
7ab2d087 | 1574 | alpha_next_pc (struct regcache *regcache, CORE_ADDR pc) |
ec32e4be | 1575 | { |
ac7936df | 1576 | struct gdbarch *gdbarch = regcache->arch (); |
ec32e4be JT |
1577 | unsigned int insn; |
1578 | unsigned int op; | |
551e4f2e | 1579 | int regno; |
ec32e4be JT |
1580 | int offset; |
1581 | LONGEST rav; | |
1582 | ||
e17a4113 | 1583 | insn = alpha_read_insn (gdbarch, pc); |
ec32e4be | 1584 | |
0963b4bd | 1585 | /* Opcode is top 6 bits. */ |
ec32e4be JT |
1586 | op = (insn >> 26) & 0x3f; |
1587 | ||
1588 | if (op == 0x1a) | |
1589 | { | |
1590 | /* Jump format: target PC is: | |
1591 | RB & ~3 */ | |
7ab2d087 | 1592 | return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3); |
ec32e4be JT |
1593 | } |
1594 | ||
1595 | if ((op & 0x30) == 0x30) | |
1596 | { | |
1597 | /* Branch format: target PC is: | |
1598 | (new PC) + (4 * sext(displacement)) */ | |
f8bf5763 PM |
1599 | if (op == 0x30 /* BR */ |
1600 | || op == 0x34) /* BSR */ | |
ec32e4be JT |
1601 | { |
1602 | branch_taken: | |
dda83cd7 | 1603 | offset = (insn & 0x001fffff); |
ec32e4be JT |
1604 | if (offset & 0x00100000) |
1605 | offset |= 0xffe00000; | |
e8d2d628 MK |
1606 | offset *= ALPHA_INSN_SIZE; |
1607 | return (pc + ALPHA_INSN_SIZE + offset); | |
ec32e4be JT |
1608 | } |
1609 | ||
1610 | /* Need to determine if branch is taken; read RA. */ | |
551e4f2e JB |
1611 | regno = (insn >> 21) & 0x1f; |
1612 | switch (op) | |
dda83cd7 SM |
1613 | { |
1614 | case 0x31: /* FBEQ */ | |
1615 | case 0x36: /* FBGE */ | |
1616 | case 0x37: /* FBGT */ | |
1617 | case 0x33: /* FBLE */ | |
1618 | case 0x32: /* FBLT */ | |
1619 | case 0x35: /* FBNE */ | |
1620 | regno += gdbarch_fp0_regnum (gdbarch); | |
551e4f2e JB |
1621 | } |
1622 | ||
7ab2d087 | 1623 | rav = regcache_raw_get_signed (regcache, regno); |
0de94d4b | 1624 | |
ec32e4be JT |
1625 | switch (op) |
1626 | { | |
1627 | case 0x38: /* BLBC */ | |
1628 | if ((rav & 1) == 0) | |
1629 | goto branch_taken; | |
1630 | break; | |
1631 | case 0x3c: /* BLBS */ | |
1632 | if (rav & 1) | |
1633 | goto branch_taken; | |
1634 | break; | |
1635 | case 0x39: /* BEQ */ | |
1636 | if (rav == 0) | |
1637 | goto branch_taken; | |
1638 | break; | |
1639 | case 0x3d: /* BNE */ | |
1640 | if (rav != 0) | |
1641 | goto branch_taken; | |
1642 | break; | |
1643 | case 0x3a: /* BLT */ | |
1644 | if (rav < 0) | |
1645 | goto branch_taken; | |
1646 | break; | |
1647 | case 0x3b: /* BLE */ | |
1648 | if (rav <= 0) | |
1649 | goto branch_taken; | |
1650 | break; | |
1651 | case 0x3f: /* BGT */ | |
1652 | if (rav > 0) | |
1653 | goto branch_taken; | |
1654 | break; | |
1655 | case 0x3e: /* BGE */ | |
1656 | if (rav >= 0) | |
1657 | goto branch_taken; | |
1658 | break; | |
d2427a71 | 1659 | |
dda83cd7 SM |
1660 | /* Floating point branches. */ |
1661 | ||
1662 | case 0x31: /* FBEQ */ | |
1663 | if (fp_register_zero_p (rav)) | |
1664 | goto branch_taken; | |
1665 | break; | |
1666 | case 0x36: /* FBGE */ | |
1667 | if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav)) | |
1668 | goto branch_taken; | |
1669 | break; | |
1670 | case 0x37: /* FBGT */ | |
1671 | if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav)) | |
1672 | goto branch_taken; | |
1673 | break; | |
1674 | case 0x33: /* FBLE */ | |
1675 | if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav)) | |
1676 | goto branch_taken; | |
1677 | break; | |
1678 | case 0x32: /* FBLT */ | |
1679 | if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav)) | |
1680 | goto branch_taken; | |
1681 | break; | |
1682 | case 0x35: /* FBNE */ | |
1683 | if (! fp_register_zero_p (rav)) | |
1684 | goto branch_taken; | |
1685 | break; | |
ec32e4be JT |
1686 | } |
1687 | } | |
1688 | ||
1689 | /* Not a branch or branch not taken; target PC is: | |
1690 | pc + 4 */ | |
e8d2d628 | 1691 | return (pc + ALPHA_INSN_SIZE); |
ec32e4be JT |
1692 | } |
1693 | ||
a0ff9e1a | 1694 | std::vector<CORE_ADDR> |
f5ea389a | 1695 | alpha_software_single_step (struct regcache *regcache) |
ec32e4be | 1696 | { |
68f81d60 RH |
1697 | struct gdbarch *gdbarch = regcache->arch (); |
1698 | ||
1699 | CORE_ADDR pc = regcache_read_pc (regcache); | |
1700 | ||
1701 | std::vector<CORE_ADDR> next_pcs | |
1702 | = alpha_deal_with_atomic_sequence (gdbarch, pc); | |
1703 | if (!next_pcs.empty ()) | |
1704 | return next_pcs; | |
ec32e4be | 1705 | |
68f81d60 RH |
1706 | CORE_ADDR next_pc = alpha_next_pc (regcache, pc); |
1707 | return {next_pc}; | |
c906108c SS |
1708 | } |
1709 | ||
dc129d82 | 1710 | \f |
dc129d82 JT |
1711 | /* Initialize the current architecture based on INFO. If possible, re-use an |
1712 | architecture from ARCHES, which is a list of architectures already created | |
1713 | during this debugging session. | |
1714 | ||
1715 | Called e.g. at program startup, when reading a core file, and when reading | |
1716 | a binary file. */ | |
1717 | ||
1718 | static struct gdbarch * | |
1719 | alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1720 | { | |
dc129d82 | 1721 | /* Find a candidate among extant architectures. */ |
4be87837 DJ |
1722 | arches = gdbarch_list_lookup_by_info (arches, &info); |
1723 | if (arches != NULL) | |
1724 | return arches->gdbarch; | |
dc129d82 | 1725 | |
2b16913c SM |
1726 | gdbarch *gdbarch |
1727 | = gdbarch_alloc (&info, gdbarch_tdep_up (new alpha_gdbarch_tdep)); | |
1728 | alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); | |
dc129d82 | 1729 | |
d2427a71 RH |
1730 | /* Lowest text address. This is used by heuristic_proc_start() |
1731 | to decide when to stop looking. */ | |
594706e6 | 1732 | tdep->vm_min_address = (CORE_ADDR) 0x120000000LL; |
d9b023cc | 1733 | |
36a6271d | 1734 | tdep->dynamic_sigtramp_offset = NULL; |
5868c862 | 1735 | tdep->sigcontext_addr = NULL; |
138e7be5 MK |
1736 | tdep->sc_pc_offset = 2 * 8; |
1737 | tdep->sc_regs_offset = 4 * 8; | |
1738 | tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8; | |
36a6271d | 1739 | |
0963b4bd | 1740 | tdep->jb_pc = -1; /* longjmp support not enabled by default. */ |
accc6d1f | 1741 | |
9823e921 RH |
1742 | tdep->return_in_memory = alpha_return_in_memory_always; |
1743 | ||
dc129d82 JT |
1744 | /* Type sizes */ |
1745 | set_gdbarch_short_bit (gdbarch, 16); | |
1746 | set_gdbarch_int_bit (gdbarch, 32); | |
1747 | set_gdbarch_long_bit (gdbarch, 64); | |
1748 | set_gdbarch_long_long_bit (gdbarch, 64); | |
53375380 PA |
1749 | set_gdbarch_wchar_bit (gdbarch, 64); |
1750 | set_gdbarch_wchar_signed (gdbarch, 0); | |
dc129d82 JT |
1751 | set_gdbarch_float_bit (gdbarch, 32); |
1752 | set_gdbarch_double_bit (gdbarch, 64); | |
1753 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1754 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1755 | ||
1756 | /* Register info */ | |
1757 | set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS); | |
1758 | set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM); | |
dc129d82 JT |
1759 | set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM); |
1760 | set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM); | |
1761 | ||
1762 | set_gdbarch_register_name (gdbarch, alpha_register_name); | |
c483c494 | 1763 | set_gdbarch_register_type (gdbarch, alpha_register_type); |
dc129d82 JT |
1764 | |
1765 | set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register); | |
1766 | set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register); | |
1767 | ||
c483c494 RH |
1768 | set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p); |
1769 | set_gdbarch_register_to_value (gdbarch, alpha_register_to_value); | |
1770 | set_gdbarch_value_to_register (gdbarch, alpha_value_to_register); | |
dc129d82 | 1771 | |
615967cb RH |
1772 | set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p); |
1773 | ||
d2427a71 | 1774 | /* Prologue heuristics. */ |
dc129d82 JT |
1775 | set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue); |
1776 | ||
d2427a71 | 1777 | /* Call info. */ |
dc129d82 | 1778 | |
9823e921 | 1779 | set_gdbarch_return_value (gdbarch, alpha_return_value); |
dc129d82 JT |
1780 | |
1781 | /* Settings for calling functions in the inferior. */ | |
c88e30c0 | 1782 | set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call); |
d2427a71 | 1783 | |
dc129d82 | 1784 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
36a6271d | 1785 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
dc129d82 | 1786 | |
04180708 YQ |
1787 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1788 | alpha_breakpoint::kind_from_pc); | |
1789 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1790 | alpha_breakpoint::bp_from_kind); | |
e8d2d628 | 1791 | set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE); |
9d519230 | 1792 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
95b80706 | 1793 | |
46ad3598 | 1794 | /* Handles single stepping of atomic sequences. */ |
68f81d60 | 1795 | set_gdbarch_software_single_step (gdbarch, alpha_software_single_step); |
46ad3598 | 1796 | |
44dffaac | 1797 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 1798 | gdbarch_init_osabi (info, gdbarch); |
44dffaac | 1799 | |
accc6d1f JT |
1800 | /* Now that we have tuned the configuration, set a few final things |
1801 | based on what the OS ABI has told us. */ | |
1802 | ||
1803 | if (tdep->jb_pc >= 0) | |
1804 | set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target); | |
1805 | ||
6834c9bb JB |
1806 | frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind); |
1807 | frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind); | |
dc129d82 | 1808 | |
d2427a71 | 1809 | frame_base_set_default (gdbarch, &alpha_heuristic_frame_base); |
accc6d1f | 1810 | |
d2427a71 | 1811 | return gdbarch; |
dc129d82 JT |
1812 | } |
1813 | ||
baa490c4 RH |
1814 | void |
1815 | alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
1816 | { | |
6834c9bb | 1817 | dwarf2_append_unwinders (gdbarch); |
336d1bba | 1818 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
baa490c4 RH |
1819 | } |
1820 | ||
6c265988 | 1821 | void _initialize_alpha_tdep (); |
c906108c | 1822 | void |
6c265988 | 1823 | _initialize_alpha_tdep () |
c906108c | 1824 | { |
c906108c | 1825 | |
d2427a71 | 1826 | gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL); |
c906108c SS |
1827 | |
1828 | /* Let the user set the fence post for heuristic_proc_start. */ | |
1829 | ||
1830 | /* We really would like to have both "0" and "unlimited" work, but | |
1831 | command.c doesn't deal with that. So make it a var_zinteger | |
1832 | because the user can always use "999999" or some such for unlimited. */ | |
edefbb7c AC |
1833 | /* We need to throw away the frame cache when we set this, since it |
1834 | might change our ability to get backtraces. */ | |
1835 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, | |
7915a72c AC |
1836 | &heuristic_fence_post, _("\ |
1837 | Set the distance searched for the start of a function."), _("\ | |
1838 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
1839 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
1840 | program for the start of a function. This command sets the distance of the\n\ | |
323e0a4a | 1841 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 1842 | reinit_frame_cache_sfunc, |
0963b4bd MS |
1843 | NULL, /* FIXME: i18n: The distance searched for |
1844 | the start of a function is \"%d\". */ | |
edefbb7c | 1845 | &setlist, &showlist); |
c906108c | 1846 | } |